From 9f0ede486da3f22057fd491c9d41cf6c809e52bc Mon Sep 17 00:00:00 2001 From: Jerome Coutant Date: Wed, 10 May 2023 12:18:24 +0200 Subject: [PATCH] STM32U5: STM32Cube_FW_U5_V1.2.0 --- .../STM32Cube_FW/CMSIS/LICENSE.txt | 6 + .../STM32Cube_FW/CMSIS/partition_stm32u5xx.h | 80 + .../STM32Cube_FW/CMSIS/stm32u535xx.h | 21195 +++++++++++ .../STM32Cube_FW/CMSIS/stm32u545xx.h | 22026 +++++++++++ .../STM32Cube_FW/CMSIS/stm32u575xx.h | 2841 +- .../STM32Cube_FW/CMSIS/stm32u585xx.h | 2852 +- .../STM32Cube_FW/CMSIS/stm32u595xx.h | 25581 +++++++++++++ .../STM32Cube_FW/CMSIS/stm32u599xx.h | 29428 +++++++++++++++ .../STM32Cube_FW/CMSIS/stm32u5a5xx.h | 26462 ++++++++++++++ .../STM32Cube_FW/CMSIS/stm32u5a9xx.h | 30309 ++++++++++++++++ .../STM32Cube_FW/CMSIS/stm32u5xx.h | 37 +- .../STM32Cube_FW/CMakeLists.txt | 6 + .../Legacy/stm32_hal_legacy.h | 593 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal.c | 219 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal.h | 152 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_adc.c | 927 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_adc.h | 136 +- .../stm32u5xx_hal_adc_ex.c | 639 +- .../stm32u5xx_hal_adc_ex.h | 166 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_comp.c | 47 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_comp.h | 207 +- .../stm32u5xx_hal_cordic.c | 120 +- .../stm32u5xx_hal_cordic.h | 16 +- .../stm32u5xx_hal_cortex.c | 2 +- .../stm32u5xx_hal_cortex.h | 6 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_crc.h | 8 +- .../stm32u5xx_hal_crc_ex.c | 79 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_cryp.c | 101 +- .../stm32u5xx_hal_cryp_ex.c | 29 +- .../stm32u5xx_hal_cryp_ex.h | 2 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_dac.c | 131 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_dac.h | 56 +- .../stm32u5xx_hal_dac_ex.c | 104 +- .../stm32u5xx_hal_dac_ex.h | 44 +- .../stm32u5xx_hal_dcache.c | 788 +- .../stm32u5xx_hal_dcache.h | 72 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_dcmi.c | 38 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_dcmi.h | 5 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_def.h | 4 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_dma.c | 33 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_dma.h | 55 +- .../stm32u5xx_hal_dma2d.c | 19 +- .../stm32u5xx_hal_dma2d.h | 44 +- .../stm32u5xx_hal_dma_ex.c | 107 +- .../stm32u5xx_hal_dma_ex.h | 34 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_dsi.c | 2864 ++ .../STM32U5xx_HAL_Driver/stm32u5xx_hal_dsi.h | 1445 + .../STM32U5xx_HAL_Driver/stm32u5xx_hal_exti.c | 35 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_exti.h | 66 +- .../stm32u5xx_hal_fdcan.c | 220 +- .../stm32u5xx_hal_fdcan.h | 129 +- .../stm32u5xx_hal_flash.h | 18 +- .../stm32u5xx_hal_flash_ex.c | 20 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_fmac.c | 139 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_fmac.h | 115 +- .../stm32u5xx_hal_gfxmmu.c | 977 + .../stm32u5xx_hal_gfxmmu.h | 504 + .../STM32U5xx_HAL_Driver/stm32u5xx_hal_gpio.c | 70 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_gpio.h | 9 +- .../stm32u5xx_hal_gpio_ex.h | 260 +- .../stm32u5xx_hal_gpu2d.c | 750 + .../stm32u5xx_hal_gpu2d.h | 320 + .../STM32U5xx_HAL_Driver/stm32u5xx_hal_gtzc.c | 528 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_gtzc.h | 135 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_hash.c | 33 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_hash.h | 1 + .../stm32u5xx_hal_hash_ex.c | 1 + .../stm32u5xx_hal_hash_ex.h | 1 + .../STM32U5xx_HAL_Driver/stm32u5xx_hal_hcd.c | 3548 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_hcd.h | 314 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_i2c.c | 1630 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_i2c.h | 116 +- .../stm32u5xx_hal_i2c_ex.c | 60 +- .../stm32u5xx_hal_i2c_ex.h | 82 +- .../stm32u5xx_hal_icache.c | 34 +- .../stm32u5xx_hal_icache.h | 1 + .../STM32U5xx_HAL_Driver/stm32u5xx_hal_irda.c | 125 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_irda.h | 19 +- .../stm32u5xx_hal_irda_ex.h | 95 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_iwdg.c | 26 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_iwdg.h | 2 +- .../stm32u5xx_hal_lptim.c | 588 +- .../stm32u5xx_hal_lptim.h | 95 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc.c | 2215 ++ .../STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc.h | 719 + .../stm32u5xx_hal_ltdc_ex.c | 151 + .../stm32u5xx_hal_ltdc_ex.h | 83 + .../STM32U5xx_HAL_Driver/stm32u5xx_hal_mdf.c | 41 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_mdf.h | 59 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_mmc.c | 527 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_mmc.h | 40 +- .../stm32u5xx_hal_mmc_ex.c | 1 + .../STM32U5xx_HAL_Driver/stm32u5xx_hal_nand.c | 63 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_nand.h | 43 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_nor.c | 254 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_nor.h | 7 +- .../stm32u5xx_hal_opamp.c | 17 +- .../stm32u5xx_hal_opamp.h | 7 +- .../stm32u5xx_hal_opamp_ex.c | 3 +- .../stm32u5xx_hal_opamp_ex.h | 2 + .../STM32U5xx_HAL_Driver/stm32u5xx_hal_ospi.c | 70 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_ospi.h | 12 +- .../stm32u5xx_hal_otfdec.c | 9 +- .../stm32u5xx_hal_otfdec.h | 4 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_pcd.c | 953 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_pcd.h | 288 +- .../stm32u5xx_hal_pcd_ex.c | 280 +- .../stm32u5xx_hal_pcd_ex.h | 16 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_pka.c | 89 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_pka.h | 5 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_pssi.c | 170 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_pssi.h | 42 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_pwr.c | 3 + .../STM32U5xx_HAL_Driver/stm32u5xx_hal_pwr.h | 40 +- .../stm32u5xx_hal_pwr_ex.c | 501 +- .../stm32u5xx_hal_pwr_ex.h | 298 +- .../stm32u5xx_hal_ramcfg.c | 173 +- .../stm32u5xx_hal_ramcfg.h | 58 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_rcc.c | 353 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_rcc.h | 1579 +- .../stm32u5xx_hal_rcc_ex.c | 2322 +- .../stm32u5xx_hal_rcc_ex.h | 550 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_rng.c | 51 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_rng.h | 7 +- .../stm32u5xx_hal_rng_ex.c | 17 +- .../stm32u5xx_hal_rng_ex.h | 43 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_rtc.c | 143 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_rtc.h | 83 +- .../stm32u5xx_hal_rtc_ex.c | 647 +- .../stm32u5xx_hal_rtc_ex.h | 263 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_sai.c | 28 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_sai.h | 13 +- .../stm32u5xx_hal_sai_ex.c | 3 +- .../stm32u5xx_hal_sai_ex.h | 3 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_sd.c | 281 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_sd.h | 12 +- .../stm32u5xx_hal_sd_ex.c | 5 +- .../stm32u5xx_hal_smartcard.c | 69 +- .../stm32u5xx_hal_smartcard.h | 71 +- .../stm32u5xx_hal_smartcard_ex.c | 1 + .../stm32u5xx_hal_smartcard_ex.h | 1 + .../stm32u5xx_hal_smbus.c | 362 +- .../stm32u5xx_hal_smbus.h | 268 +- .../stm32u5xx_hal_smbus_ex.c | 55 +- .../stm32u5xx_hal_smbus_ex.h | 173 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_spi.c | 682 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_spi.h | 74 +- .../stm32u5xx_hal_spi_ex.c | 20 +- .../stm32u5xx_hal_spi_ex.h | 30 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_sram.c | 33 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_sram.h | 3 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_tim.c | 233 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_tim.h | 119 +- .../stm32u5xx_hal_tim_ex.c | 81 +- .../stm32u5xx_hal_tim_ex.h | 199 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_tsc.c | 30 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_tsc.h | 146 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_uart.c | 453 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_uart.h | 71 +- .../stm32u5xx_hal_uart_ex.c | 82 +- .../stm32u5xx_hal_uart_ex.h | 165 +- .../stm32u5xx_hal_usart.c | 352 +- .../stm32u5xx_hal_usart.h | 78 +- .../stm32u5xx_hal_usart_ex.c | 6 +- .../stm32u5xx_hal_usart_ex.h | 5 +- .../STM32U5xx_HAL_Driver/stm32u5xx_hal_xspi.c | 3911 ++ .../STM32U5xx_HAL_Driver/stm32u5xx_hal_xspi.h | 1373 + .../STM32U5xx_HAL_Driver/stm32u5xx_ll_adc.c | 160 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_adc.h | 1280 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_bus.h | 1206 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_comp.c | 23 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_comp.h | 127 +- .../stm32u5xx_ll_cordic.c | 2 +- .../stm32u5xx_ll_cordic.h | 42 +- .../stm32u5xx_ll_cortex.h | 125 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_crc.c | 1 - .../STM32U5xx_HAL_Driver/stm32u5xx_ll_crc.h | 2 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_dac.c | 6 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_dac.h | 87 +- .../stm32u5xx_ll_dcache.h | 60 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_dlyb.c | 6 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_dlyb.h | 27 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_dma.c | 12 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_dma.h | 181 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_dma2d.c | 35 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_dma2d.h | 177 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_exti.c | 2 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_exti.h | 131 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_fmac.c | 2 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_fmac.h | 106 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_fmc.c | 1 - .../STM32U5xx_HAL_Driver/stm32u5xx_ll_fmc.h | 3 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_gpio.c | 35 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_gpio.h | 35 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_i2c.c | 28 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_i2c.h | 413 +- .../stm32u5xx_ll_icache.c | 2 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_iwdg.h | 24 +- .../stm32u5xx_ll_lpgpio.c | 2 +- .../stm32u5xx_ll_lpgpio.h | 13 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_lptim.c | 4 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_lptim.h | 281 +- .../stm32u5xx_ll_lpuart.c | 9 +- .../stm32u5xx_ll_lpuart.h | 182 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_opamp.c | 8 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_opamp.h | 74 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_pka.c | 4 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_pka.h | 27 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_pwr.h | 822 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_rcc.c | 467 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_rcc.h | 906 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_rng.c | 24 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_rng.h | 40 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_rtc.c | 40 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_rtc.h | 850 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_sdmmc.c | 35 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_sdmmc.h | 21 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_spi.c | 14 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_spi.h | 201 +- .../stm32u5xx_ll_system.h | 366 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_tim.c | 65 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_tim.h | 360 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_ucpd.h | 4 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_usart.c | 43 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_usart.h | 253 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_usb.c | 1866 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_usb.h | 824 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_utils.c | 24 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_utils.h | 58 +- .../STM32U5xx_HAL_Driver/stm32u5xx_ll_wwdg.h | 12 +- .../STM32Cube_FW/stm32u5xx_hal_conf.h | 30 + .../STM32Cube_FW/system_stm32u5xx.c | 4 +- .../TOOLCHAIN_ARM/startup_stm32u575xx.S | 23 +- .../TOOLCHAIN_GCC_ARM/startup_stm32u575xx.S | 65 +- .../TOOLCHAIN_IAR/startup_stm32u575xx.S | 30 +- .../TOOLCHAIN_IAR/stm32u575xg.icf | 4 +- .../TARGET_STM32U575xG/cmsis_nvic.h | 6 +- .../TOOLCHAIN_ARM/startup_stm32u575xx.S | 23 +- .../TOOLCHAIN_GCC_ARM/startup_stm32u575xx.S | 65 +- .../TOOLCHAIN_IAR/startup_stm32u575xx.S | 30 +- .../TOOLCHAIN_IAR/stm32u575xi.icf | 4 +- .../TARGET_STM32U575xI/cmsis_nvic.h | 6 +- .../TOOLCHAIN_ARM/startup_stm32u585xx.S | 25 +- .../TOOLCHAIN_GCC_ARM/startup_stm32u585xx.S | 66 +- .../TOOLCHAIN_IAR/startup_stm32u585xx.S | 29 +- .../TOOLCHAIN_IAR/stm32u585xi.icf | 4 +- .../TARGET_STM32U585xI/cmsis_nvic.h | 6 +- targets/TARGET_STM/stm_spi_api.c | 4 + 248 files changed, 203421 insertions(+), 13216 deletions(-) create mode 100644 targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/LICENSE.txt create mode 100644 targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/partition_stm32u5xx.h create mode 100644 targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u535xx.h create mode 100644 targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u545xx.h create mode 100644 targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u595xx.h create mode 100644 targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u599xx.h create mode 100644 targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u5a5xx.h create mode 100644 targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u5a9xx.h create mode 100644 targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dsi.c create mode 100644 targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dsi.h create mode 100644 targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gfxmmu.c create mode 100644 targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gfxmmu.h create mode 100644 targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpu2d.c create mode 100644 targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpu2d.h create mode 100644 targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc.c create mode 100644 targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc.h create mode 100644 targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc_ex.c create mode 100644 targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc_ex.h create mode 100644 targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_xspi.c create mode 100644 targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_xspi.h diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/LICENSE.txt b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/LICENSE.txt new file mode 100644 index 00000000000..872e82b4670 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the Apache-2.0 license shall apply. +You may obtain a copy of the Apache-2.0 at: +https://opensource.org/licenses/Apache-2.0 diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/partition_stm32u5xx.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/partition_stm32u5xx.h new file mode 100644 index 00000000000..02b1e79e336 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/partition_stm32u5xx.h @@ -0,0 +1,80 @@ +/** + ****************************************************************************** + * @file partition_stm32u5xx.h + * @author MCD Application Team + * @brief CMSIS STM32U5xx Device Header File for Initial Setup for + * Secure / Non-Secure Zones based on CMSIS CORE V5.4.0 + * + * The file is included in system_stm32u5xx_s.c in secure application. + * It includes the configuration section that allows to select the + * STM32U5xx device partitioning file for system core secure attributes + * and interrupt secure and non-secure assignment. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32u5xx + * @{ + */ + +#ifndef PARTITION_STM32U5XX_H +#define PARTITION_STM32U5XX_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Secure_configuration_section + * @{ + */ + +#if defined(STM32U575xx) + #include "partition_stm32u575xx.h" +#elif defined(STM32U585xx) + #include "partition_stm32u585xx.h" +#elif defined(STM32U595xx) + #include "partition_stm32u595xx.h" +#elif defined(STM32U5A5xx) + #include "partition_stm32u5a5xx.h" +#elif defined(STM32U599xx) + #include "partition_stm32u599xx.h" +#elif defined(STM32U5A9xx) + #include "partition_stm32u5a9xx.h" +#elif defined(STM32U535xx) + #include "partition_stm32u535xx.h" +#elif defined(STM32U545xx) + #include "partition_stm32u545xx.h" +#else + #error "Please select first the target STM32U5xx device used in your application (in stm32u5xx.h file)" +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* PARTITION_STM32U5XX_H */ +/** + * @} + */ + +/** + * @} + */ + + + + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u535xx.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u535xx.h new file mode 100644 index 00000000000..ddc8c354f71 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u535xx.h @@ -0,0 +1,21195 @@ +/** + ****************************************************************************** + * @file stm32u535xx.h + * @author MCD Application Team + * @brief CMSIS STM32U535xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32U535xx_H +#define STM32U535xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32U535xx + * @{ + */ + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32U535xx Specific Interrupt Numbers ================================= */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + RTC_S_IRQn = 3, /*!< RTC secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ + GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + IWDG_IRQn = 27, /*!< IWDG global interrupt */ + GPDMA1_Channel0_IRQn = 29, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 30, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 31, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 32, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 33, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 34, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 35, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 36, /*!< GPDMA1 Channel 7 global interrupt */ + ADC1_IRQn = 37, /*!< ADC1 global interrupt */ + DAC1_IRQn = 38, /*!< DAC1 global interrupt */ + FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ + TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 45, /*!< TIM2 global interrupt */ + TIM3_IRQn = 46, /*!< TIM3 global interrupt */ + TIM4_IRQn = 47, /*!< TIM4 global interrupt */ + TIM5_IRQn = 48, /*!< TIM5 global interrupt */ + TIM6_IRQn = 49, /*!< TIM6 global interrupt */ + TIM7_IRQn = 50, /*!< TIM7 global interrupt */ + TIM8_BRK_IRQn = 51, /*!< TIM8 Break interrupt */ + TIM8_UP_IRQn = 52, /*!< TIM8 Update interrupt */ + TIM8_TRG_COM_IRQn = 53, /*!< TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQn = 54, /*!< TIM8 Capture Compare interrupt */ + I2C1_EV_IRQn = 55, /*!< I2C1 Event interrupt */ + I2C1_ER_IRQn = 56, /*!< I2C1 Error interrupt */ + I2C2_EV_IRQn = 57, /*!< I2C2 Event interrupt */ + I2C2_ER_IRQn = 58, /*!< I2C2 Error interrupt */ + SPI1_IRQn = 59, /*!< SPI1 global interrupt */ + SPI2_IRQn = 60, /*!< SPI2 global interrupt */ + USART1_IRQn = 61, /*!< USART1 global interrupt */ + USART3_IRQn = 63, /*!< USART3 global interrupt */ + UART4_IRQn = 64, /*!< UART4 global interrupt */ + UART5_IRQn = 65, /*!< UART5 global interrupt */ + LPUART1_IRQn = 66, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 67, /*!< LPTIM1 global interrupt */ + LPTIM2_IRQn = 68, /*!< LPTIM2 global interrupt */ + TIM15_IRQn = 69, /*!< TIM15 global interrupt */ + TIM16_IRQn = 70, /*!< TIM16 global interrupt */ + TIM17_IRQn = 71, /*!< TIM17 global interrupt */ + COMP_IRQn = 72, /*!< COMP1 and COMP2 through EXTI Lines interrupts */ + USB_IRQn = 73, /*!< USB global interrupt */ + CRS_IRQn = 74, /*!< CRS global interrupt */ + OCTOSPI1_IRQn = 76, /*!< OctoSPI1 global interrupt */ + PWR_S3WU_IRQn = 77, /*!< PWR wake up from Stop3 interrupt */ + SDMMC1_IRQn = 78, /*!< SDMMC1 global interrupt */ + GPDMA1_Channel8_IRQn = 80, /*!< GPDMA1 Channel 8 global interrupt */ + GPDMA1_Channel9_IRQn = 81, /*!< GPDMA1 Channel 9 global interrupt */ + GPDMA1_Channel10_IRQn = 82, /*!< GPDMA1 Channel 10 global interrupt */ + GPDMA1_Channel11_IRQn = 83, /*!< GPDMA1 Channel 11 global interrupt */ + GPDMA1_Channel12_IRQn = 84, /*!< GPDMA1 Channel 12 global interrupt */ + GPDMA1_Channel13_IRQn = 85, /*!< GPDMA1 Channel 13 global interrupt */ + GPDMA1_Channel14_IRQn = 86, /*!< GPDMA1 Channel 14 global interrupt */ + GPDMA1_Channel15_IRQn = 87, /*!< GPDMA1 Channel 15 global interrupt */ + I2C3_EV_IRQn = 88, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 89, /*!< I2C3 error interrupt */ + SAI1_IRQn = 90, /*!< Serial Audio Interface 1 global interrupt */ + TSC_IRQn = 92, /*!< Touch Sense Controller global interrupt */ + RNG_IRQn = 94, /*!< RNG global interrupt */ + FPU_IRQn = 95, /*!< FPU global interrupt */ + HASH_IRQn = 96, /*!< HASH global interrupt */ + LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */ + SPI3_IRQn = 99, /*!< SPI3 global interrupt */ + I2C4_ER_IRQn = 100, /*!< I2C4 Error interrupt */ + I2C4_EV_IRQn = 101, /*!< I2C4 Event interrupt */ + MDF1_FLT0_IRQn = 102, /*!< MDF1 Filter 0 global interrupt */ + MDF1_FLT1_IRQn = 103, /*!< MDF1 Filter 1 global interrupt */ + ICACHE_IRQn = 107, /*!< Instruction cache global interrupt */ + LPTIM4_IRQn = 110, /*!< LPTIM4 global interrupt */ + DCACHE1_IRQn = 111, /*!< Data cache global interrupt */ + ADF1_IRQn = 112, /*!< ADF interrupt */ + ADC4_IRQn = 113, /*!< ADC4 (12bits) global interrupt */ + LPDMA1_Channel0_IRQn = 114, /*!< LPDMA1 SmartRun Channel 0 global interrupt */ + LPDMA1_Channel1_IRQn = 115, /*!< LPDMA1 SmartRun Channel 1 global interrupt */ + LPDMA1_Channel2_IRQn = 116, /*!< LPDMA1 SmartRun Channel 2 global interrupt */ + LPDMA1_Channel3_IRQn = 117, /*!< LPDMA1 SmartRun Channel 3 global interrupt */ + DCMI_PSSI_IRQn = 119, /*!< DCMI/PSSI global interrupt */ + CORDIC_IRQn = 123, /*!< CORDIC global interrupt */ + FMAC_IRQn = 124, /*!< FMAC global interrupt */ + LSECSSD_IRQn = 125, /*!< LSECSSD and MSI_PLL_UNLOCK global interrupts */ +} IRQn_Type; + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32u5xx.h" /*!< STM32U5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ + uint32_t RESERVED3[246]; /*!< Reserved, */ + __IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */ + __IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; +} I2C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, 0x24 */ + __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ + uint32_t RESERVED4[7]; /*!< Reserved4, Address offset: 0x84-0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ + uint32_t RESERVED5[7]; /*!< Reserved5, Address offset: 0xA4-0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ + uint32_t RESERVED7[7]; /*!< Reserved7, Address offset: 0xD4-0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */ + __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */ + __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */ + __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */ + __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x180 */ + uint32_t RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x200 */ + __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ + uint32_t RESERVED2[240]; /*!< Reserved, Address offset: 0x30-0x3EC */ + __IO uint32_t HWCFGR; /*!< ICACHE HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< ICACHE version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ICACHE IP identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ICACHE size identification register, Address offset: 0x3FC */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + + +/** + * @brief MDF/ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ +}MDF_TypeDef; + +/** + * @brief MDF/ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ + __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ + __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ + __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ + __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + + + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x20 */ + __IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + uint32_t RESERVED1[1]; /*!< Reserved1, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + __IO uint32_t BDSR; /*!< Power backup domain status register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + uint32_t RESERVED2[2]; /*!< Reserved2, Address offset: 0x78-0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */ + __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */ + __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */ + __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */ + __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */ + __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */ + __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */ + __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */ + __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */ + __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */ + __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */ + uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + uint32_t RESERVED2[16];/*!< RESERVED2, Address offset: 0x30 - 0x6C */ +} SYSCFG_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + __IO uint32_t RESERVED0[8]; /*!< Reserved, */ + __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IO uint32_t TXBD; /*!= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0x30000UL) /*!< SRAM1=192k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ +#define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */ + +/* External memories base addresses - Not aliased */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ + + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (512 KB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (192 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x20030000UL) /*!< SRAM2 (64 KB) non-secure base address */ +#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) +#define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08308UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define USB_DRD_BASE_NS (APB2PERIPH_BASE_NS + 0x06000UL) +#define USB_DRD_PMAADDR_NS (APB2PERIPH_BASE_NS + 0x06400UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL) +#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL) +#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) +#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS) +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1308UL) +#define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL) +#define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL) +#define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL) +#define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL) +#define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL) +#define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL) +#define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL) +#define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL) +#define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 2 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (192 KB) secure base address */ +#define SRAM2_BASE_S (0x30030000UL) /*!< SRAM2 (64 KB) secure base address */ +#define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) + +/*!< APB3 Secure peripherals */ +#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) +#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08308UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define USB_DRD_BASE_S (APB2PERIPH_BASE_S + 0x06000UL) +#define USB_DRD_PMAADDR_S (APB2PERIPH_BASE_S + 0x06400UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) +#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) +#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL) +#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1308UL) +#define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) +#define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL) +#define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL) +#define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL) +#define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL) +#define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL) +#define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) +#define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) + + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0044000UL) +#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ +#define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */ + + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0U) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0U) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1U) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define USB_DRD_FS_NS ((USB_DRD_TypeDef *) USB_DRD_BASE_NS) +#define USB_DRD_PMA_BUFF_NS ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS) +#define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS) +#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) +#define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS) +#define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS) +#define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS) +#define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS) +#define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) + +/*!< APB2 Secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) + +/*!< APB3 secure peripherals */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) +#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define USB_DRD_FS_S ((USB_DRD_TypeDef *) USB_DRD_BASE_S) +#define USB_DRD_PMA_BUFF_S ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S) +#define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S) +#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) +#define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S) +#define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S) +#define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S) +#define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S) +#define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S) + +/*!< DBGMCU peripheral */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM4_BASE SRAM4_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define FMAC FMAC_S +#define FMAC_BASE FMAC_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define LPDMA1 LPDMA1_S +#define LPDMA1_BASE LPDMA1_BASE_S + +#define LPDMA1_Channel0 LPDMA1_Channel0_S +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S + +#define LPDMA1_Channel1 LPDMA1_Channel1_S +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S + +#define LPDMA1_Channel2 LPDMA1_Channel2_S +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S + +#define LPDMA1_Channel3 LPDMA1_Channel3_S +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + + +#define LPGPIO1 LPGPIO1_S +#define LPGPIO1_BASE LPGPIO1_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_S +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZSC2 GTZC_TZSC2_S +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_TZIC2 GTZC_TZIC2_S +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + + +#define GTZC_MPCBB4 GTZC_MPCBB4_S +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define DAC DAC_S +#define DAC_BASE DAC_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define OPAMP OPAMP_S +#define OPAMP_BASE OPAMP_BASE_S + +#define OPAMP1 OPAMP1_S +#define OPAMP1_BASE OPAMP1_BASE_S + +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define COMP12 COMP12_S +#define COMP12_BASE COMP12_BASE_S + +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S + +#define COMP12_COMMON COMP12_COMMON_S +#define COMP12_COMMON_BASE COMP1_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + + +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S + +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + + + +#define USB_DRD_FS USB_DRD_FS_S +#define USB_DRD_BASE USB_DRD_BASE_S +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_S +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_S + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM4_BASE SRAM4_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define FMAC FMAC_NS +#define FMAC_BASE FMAC_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define LPDMA1 LPDMA1_NS +#define LPDMA1_BASE LPDMA1_BASE_NS + +#define LPDMA1_Channel0 LPDMA1_Channel0_NS +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS + +#define LPDMA1_Channel1 LPDMA1_Channel1_NS +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS + +#define LPDMA1_Channel2 LPDMA1_Channel2_NS +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS + +#define LPDMA1_Channel3 LPDMA1_Channel3_NS +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define LPGPIO1 LPGPIO1_NS +#define LPGPIO1_BASE LPGPIO1_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_NS +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZSC2 GTZC_TZSC2_NS +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_TZIC2 GTZC_TZIC2_NS +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + + +#define GTZC_MPCBB4 GTZC_MPCBB4_NS +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define OPAMP OPAMP_NS +#define OPAMP_BASE OPAMP_BASE_NS + +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS + +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define COMP12 COMP12_NS +#define COMP12_BASE COMP12_BASE_NS + +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS + +#define COMP12_COMMON COMP12_COMMON_NS +#define COMP12_COMMON_BASE COMP1_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS + +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + + +#define USB_DRD_FS USB_DRD_FS_NS +#define USB_DRD_BASE USB_DRD_BASE_NS +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_NS +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_NS + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS +#endif + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ +#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_ADCALLIN_Pos (16U) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ + +#define ADC_CR_CALINDEX_Pos (24U) +#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ +#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ +#define ADC_CR_CALINDEX0_Pos (24U) +#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ +#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ +#define ADC_CR_CALINDEX1_Pos (25U) +#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ +#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ +#define ADC_CR_CALINDEX2_Pos (26U) +#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ +#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ +#define ADC_CR_CALINDEX3_Pos (27U) +#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ +#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR1_DMNGT_Pos (0U) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC4_CFGR1_DMAEN_Pos (0U) +#define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC4_CFGR1_DMACFG_Pos (1U) +#define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC4_CFGR1_SCANDIR_Pos (4U) +#define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC4_CFGR1_ALIGN_Pos (5U) +#define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (5U) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ + +#define ADC_CFGR1_AUTDLY_Pos (14U) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC4_CFGR1_WAIT_Pos (14U) +#define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR1_DISCNUM_Pos (17U) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20U) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR1_JAWD1EN_Pos (24U) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR1_JAUTO_Pos (25U) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +/* Specific ADC4 */ +#define ADC4_CFGR1_EXTSEL_Pos (6U) +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ + +#define ADC4_CFGR1_CHSELRMOD_Pos (21U) +#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_BULB_Pos (13U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (27U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* Specific ADC4 */ +#define ADC4_CFGR2_OVSR_Pos (2U) +#define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC4_CFGR2_LFTRIG_Pos (29U) +#define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC4_SMPR_SMP1_Pos (0U) +#define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC4_SMPR_SMP2_Pos (4U) +#define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC4_SMPR_SMPSEL_Pos (8U) +#define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ +#define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ +#define ADC4_SMPR_SMPSEL0_Pos (8U) +#define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ +#define ADC4_SMPR_SMPSEL1_Pos (9U) +#define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ +#define ADC4_SMPR_SMPSEL2_Pos (10U) +#define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ +#define ADC4_SMPR_SMPSEL3_Pos (11U) +#define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ +#define ADC4_SMPR_SMPSEL4_Pos (12U) +#define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ +#define ADC4_SMPR_SMPSEL5_Pos (13U) +#define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ +#define ADC4_SMPR_SMPSEL6_Pos (14U) +#define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ +#define ADC4_SMPR_SMPSEL7_Pos (15U) +#define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ +#define ADC4_SMPR_SMPSEL8_Pos (16U) +#define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ +#define ADC4_SMPR_SMPSEL9_Pos (17U) +#define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ +#define ADC4_SMPR_SMPSEL10_Pos (18U) +#define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ +#define ADC4_SMPR_SMPSEL11_Pos (19U) +#define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ +#define ADC4_SMPR_SMPSEL12_Pos (20U) +#define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ +#define ADC4_SMPR_SMPSEL13_Pos (21U) +#define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ +#define ADC4_SMPR_SMPSEL14_Pos (22U) +#define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ +#define ADC4_SMPR_SMPSEL15_Pos (23U) +#define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ +#define ADC4_SMPR_SMPSEL16_Pos (24U) +#define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ +#define ADC4_SMPR_SMPSEL17_Pos (25U) +#define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ +#define ADC4_SMPR_SMPSEL18_Pos (26U) +#define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ +#define ADC4_SMPR_SMPSEL19_Pos (27U) +#define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ +#define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ +#define ADC4_SMPR_SMPSEL20_Pos (26U) +#define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ +#define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL21_Pos (26U) +#define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ +#define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL22_Pos (30U) +#define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ +#define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ +#define ADC4_SMPR_SMPSEL23_Pos (31U) +#define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ +#define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +#define ADC_HTR_AWDFILT_Pos (29U) +#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ +#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_PW register ********************/ +#define ADC4_PWRR_AUTOFF_Pos (0U) +#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ +#define ADC4_PWRR_DPD_Pos (1U) +#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ +#define ADC4_PWRR_VREFPROT_Pos (2U) +#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ +#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ +#define ADC4_PWRR_VREFSECSMP_Pos (3U) +#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ +#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ + +/* Legacy definitions */ +#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos +#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk +#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF +#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos +#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk +#define ADC4_PW_DPD ADC4_PWRR_DPD +#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos +#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk +#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT +#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos +#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk +#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_USAT_Pos (25U) +#define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_SSAT_Pos (26U) +#define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (27U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR2_USAT_Pos (25U) +#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR2_SSAT_Pos (26U) +#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (27U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR3_USAT_Pos (25U) +#define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR3_SSAT_Pos (26U) +#define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (27U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR4_USAT_Pos (25U) +#define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR4_SSAT_Pos (26U) +#define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (27U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_GCOMP register ********************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ +#define ADC_GCOMP_GCOMP_Pos (31U) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19U) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20U) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21U) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22U) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL23_Pos (23U) +#define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_I_APB_ADDR_Pos (0U) +#define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ +#define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ + +#define ADC_CALFACT_I_APB_DATA_Pos (08U) +#define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ +#define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ + +#define ADC_CALFACT_VALIDITY_Pos (16U) +#define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_LATCH_COEF_Pos (24U) +#define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CAPTURE_COEF_Pos (25U) +#define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ + +#define ADC4_CALFACT_CALFACT_Pos (0U) +#define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_CALFACT_Pos (0U) +#define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */ +#define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */ +#define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OR register ********************/ +#define ADC_OR_CHN0SEL_Pos (0U) +#define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ +#define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ + +/************************* ADC Common registers *****************************/ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_VSENSEEN_Pos (23U) +#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ +#define ADC_CCR_VDDCOREN_Pos (26U) +#define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ +#define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ + + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) + +#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ + +#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11U) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ1_Pos (12U) +#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */ +#define FLASH_ACR_PDREQ2_Pos (13U) +#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */ +#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14U) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0U) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1U) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3U) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4U) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5U) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6U) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7U) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13U) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16U) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17U) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18U) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19U) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD1_Pos (20U) +#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */ +#define FLASH_NSSR_PD2_Pos (21U) +#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */ +#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0U) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1U) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3U) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4U) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5U) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6U) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7U) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16U) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17U) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR register *****************/ +#define FLASH_NSCR_PG_Pos (0U) +#define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR_PER_Pos (1U) +#define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR_MER1_Pos (2U) +#define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */ +#define FLASH_NSCR_PNB_Pos (3U) +#define FLASH_NSCR_PNB_Msk (0x1FUL << FLASH_NSCR_PNB_Pos) /*!< 0x000001F8 */ +#define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR_BKER_Pos (11U) +#define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */ +#define FLASH_NSCR_BWR_Pos (14U) +#define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR_MER2_Pos (15U) +#define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */ +#define FLASH_NSCR_STRT_Pos (16U) +#define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR_OPTSTRT_Pos (17U) +#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR_EOPIE_Pos (24U) +#define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR_ERRIE_Pos (25U) +#define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR_OBL_LAUNCH_Pos (27U) +#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR_OPTLOCK_Pos (30U) +#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR_LOCK_Pos (31U) +#define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR register ****************/ +#define FLASH_SECCR_PG_Pos (0U) +#define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR_PER_Pos (1U) +#define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR_MER1_Pos (2U) +#define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR_PNB_Pos (3U) +#define FLASH_SECCR_PNB_Msk (0x1FUL << FLASH_SECCR_PNB_Pos) /*!< 0x000001F8 */ +#define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR_BKER_Pos (11U) +#define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */ +#define FLASH_SECCR_BWR_Pos (14U) +#define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR_MER2_Pos (15U) +#define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */ +#define FLASH_SECCR_STRT_Pos (16U) +#define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR_EOPIE_Pos (24U) +#define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR_ERRIE_Pos (25U) +#define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR_INV_Pos (29U) +#define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR_LOCK_Pos (31U) +#define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0003FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_BK_ECC_Pos (21U) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (22U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0x3FFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x0003FFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */ +#define FLASH_OPSR_BK_OP_Pos (21U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (22U) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8U) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_nRST_SHDW_Pos (14U) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ +#define FLASH_OPTR_SRAM_RST_Pos (15U) +#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SWAP_BANK_Pos (20U) +#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */ +#define FLASH_OPTR_DUALBANK_Pos (21U) +#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */ +#define FLASH_OPTR_BKPRAM_ECC_Pos (22U) +#define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTR_SRAM2_ECC_Pos (24U) +#define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25U) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26U) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_PA15_PUPEN_Pos (28U) +#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */ +#define FLASH_OPTR_IO_VDD_HSLV_Pos (29U) +#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */ +#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30U) +#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */ +#define FLASH_OPTR_TZEN_Pos (31U) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7U) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7U) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0U) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7U) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWM1R1 register **************/ +#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0U) +#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0x1FUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16U) +#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0x1FUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWM1R2 register **************/ +#define FLASH_SECWM1R2_HDP1_PEND_Pos (16U) +#define FLASH_SECWM1R2_HDP1_PEND_Msk (0x1FUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWM1R2_HDP1EN_Pos (31U) +#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0U) +#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */ +#define FLASH_WRP1AR_WRP1A_PEND_Pos (16U) +#define FLASH_WRP1AR_WRP1A_PEND_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */ +#define FLASH_WRP1AR_UNLOCK_Pos (31U) +#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0U) +#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */ +#define FLASH_WRP1BR_WRP1B_PEND_Pos (16U) +#define FLASH_WRP1BR_WRP1B_PEND_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */ +#define FLASH_WRP1BR_UNLOCK_Pos (31U) +#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */ + +/***************** Bits definition for FLASH_SECWM2R1 register **************/ +#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0U) +#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0x1FUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */ +#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16U) +#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0x1FUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */ + +/***************** Bits definition for FLASH_SECWM2R2 register **************/ +#define FLASH_SECWM2R2_HDP2_PEND_Pos (16U) +#define FLASH_SECWM2R2_HDP2_PEND_Msk (0x1FUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */ +#define FLASH_SECWM2R2_HDP2EN_Pos (31U) +#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */ + +/****************** Bits definition for FLASH_WRP2AR register ***************/ +#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0U) +#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0x1FUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */ +#define FLASH_WRP2AR_WRP2A_PEND_Pos (16U) +#define FLASH_WRP2AR_WRP2A_PEND_Msk (0x1FUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */ +#define FLASH_WRP2AR_UNLOCK_Pos (31U) +#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP2BR register ***************/ +#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0U) +#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0x1FUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */ +#define FLASH_WRP2BR_WRP2B_PEND_Pos (16U) +#define FLASH_WRP2BR_WRP2B_PEND_Msk (0x1FUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */ +#define FLASH_WRP2BR_UNLOCK_Pos (31U) +#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0U) +#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */ +#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1U) +#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */ +#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0U) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1U) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************************************************************************/ +/* */ +/* Filter Mathematical ACcelerator unit (FMAC) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1_BASE_Pos (0U) +#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U) +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ +#define FMAC_X1BUFCFG_FULL_WM_Pos (24U) +#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ +#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ + +/***************** Bit definition for FMAC_X2BUFCFG register ****************/ +#define FMAC_X2BUFCFG_X2_BASE_Pos (0U) +#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U) +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ + +/***************** Bit definition for FMAC_YBUFCFG register *****************/ +#define FMAC_YBUFCFG_Y_BASE_Pos (0U) +#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ +#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U) +#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ +#define FMAC_YBUFCFG_EMPTY_WM_Pos (24U) +#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ +#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ + +/****************** Bit definition for FMAC_PARAM register ******************/ +#define FMAC_PARAM_P_Pos (0U) +#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ +#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ +#define FMAC_PARAM_Q_Pos (8U) +#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ +#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ +#define FMAC_PARAM_R_Pos (16U) +#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ +#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ +#define FMAC_PARAM_FUNC_Pos (24U) +#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ +#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ +#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ +#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ +#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ +#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ +#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ +#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ +#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ +#define FMAC_PARAM_START_Pos (31U) +#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ +#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ + +/******************** Bit definition for FMAC_CR register *******************/ +#define FMAC_CR_RIEN_Pos (0U) +#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ +#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ +#define FMAC_CR_WIEN_Pos (1U) +#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ +#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ +#define FMAC_CR_OVFLIEN_Pos (2U) +#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ +#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ +#define FMAC_CR_UNFLIEN_Pos (3U) +#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ +#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ +#define FMAC_CR_SATIEN_Pos (4U) +#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ +#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ +#define FMAC_CR_DMAREN_Pos (8U) +#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ +#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ +#define FMAC_CR_DMAWEN_Pos (9U) +#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ +#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ +#define FMAC_CR_CLIPEN_Pos (15U) +#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ +#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ +#define FMAC_CR_RESET_Pos (16U) +#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ +#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_SR register ********************/ +#define FMAC_SR_YEMPTY_Pos (0U) +#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ +#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ +#define FMAC_SR_X1FULL_Pos (1U) +#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ +#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ +#define FMAC_SR_OVFL_Pos (8U) +#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ +#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ +#define FMAC_SR_UNFL_Pos (9U) +#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ +#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ +#define FMAC_SR_SAT_Pos (10U) +#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ +#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ + +/****************** Bit definition for FMAC_WDATA register ******************/ +#define FMAC_WDATA_WDATA_Pos (0U) +#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ + +/****************** Bit definition for FMACX_RDATA register *****************/ +#define FMAC_RDATA_RDATA_Pos (0U) +#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ + + +/******************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + +/****************** Bits definition for GPIO_HSLVR register ******************/ +#define GPIO_HSLVR_HSLV0_Pos (0U) +#define GPIO_HSLVR_HSLV0_Msk (0x1UL << GPIO_HSLVR_HSLV0_Pos) /*!< 0x00000001 */ +#define GPIO_HSLVR_HSLV0 GPIO_HSLVR_HSLV0_Msk +#define GPIO_HSLVR_HSLV1_Pos (1U) +#define GPIO_HSLVR_HSLV1_Msk (0x1UL << GPIO_HSLVR_HSLV1_Pos) /*!< 0x00000002 */ +#define GPIO_HSLVR_HSLV1 GPIO_HSLVR_HSLV1_Msk +#define GPIO_HSLVR_HSLV2_Pos (2U) +#define GPIO_HSLVR_HSLV2_Msk (0x1UL << GPIO_HSLVR_HSLV2_Pos) /*!< 0x00000004 */ +#define GPIO_HSLVR_HSLV2 GPIO_HSLVR_HSLV2_Msk +#define GPIO_HSLVR_HSLV3_Pos (3U) +#define GPIO_HSLVR_HSLV3_Msk (0x1UL << GPIO_HSLVR_HSLV3_Pos) /*!< 0x00000008 */ +#define GPIO_HSLVR_HSLV3 GPIO_HSLVR_HSLV3_Msk +#define GPIO_HSLVR_HSLV4_Pos (4U) +#define GPIO_HSLVR_HSLV4_Msk (0x1UL << GPIO_HSLVR_HSLV4_Pos) /*!< 0x00000010 */ +#define GPIO_HSLVR_HSLV4 GPIO_HSLVR_HSLV4_Msk +#define GPIO_HSLVR_HSLV5_Pos (5U) +#define GPIO_HSLVR_HSLV5_Msk (0x1UL << GPIO_HSLVR_HSLV5_Pos) /*!< 0x00000020 */ +#define GPIO_HSLVR_HSLV5 GPIO_HSLVR_HSLV5_Msk +#define GPIO_HSLVR_HSLV6_Pos (6U) +#define GPIO_HSLVR_HSLV6_Msk (0x1UL << GPIO_HSLVR_HSLV6_Pos) /*!< 0x00000040 */ +#define GPIO_HSLVR_HSLV6 GPIO_HSLVR_HSLV6_Msk +#define GPIO_HSLVR_HSLV7_Pos (7U) +#define GPIO_HSLVR_HSLV7_Msk (0x1UL << GPIO_HSLVR_HSLV7_Pos) /*!< 0x00000080 */ +#define GPIO_HSLVR_HSLV7 GPIO_HSLVR_HSLV7_Msk +#define GPIO_HSLVR_HSLV8_Pos (8U) +#define GPIO_HSLVR_HSLV8_Msk (0x1UL << GPIO_HSLVR_HSLV8_Pos) /*!< 0x00000100 */ +#define GPIO_HSLVR_HSLV8 GPIO_HSLVR_HSLV8_Msk +#define GPIO_HSLVR_HSLV9_Pos (9U) +#define GPIO_HSLVR_HSLV9_Msk (0x1UL << GPIO_HSLVR_HSLV9_Pos) /*!< 0x00000200 */ +#define GPIO_HSLVR_HSLV9 GPIO_HSLVR_HSLV9_Msk +#define GPIO_HSLVR_HSLV10_Pos (10U) +#define GPIO_HSLVR_HSLV10_Msk (0x1UL << GPIO_HSLVR_HSLV10_Pos) /*!< 0x00000400 */ +#define GPIO_HSLVR_HSLV10 GPIO_HSLVR_HSLV10_Msk +#define GPIO_HSLVR_HSLV11_Pos (11U) +#define GPIO_HSLVR_HSLV11_Msk (x1UL << GPIO_HSLVR_HSLV11_Pos) /*!< 0x00000800 */ +#define GPIO_HSLVR_HSLV11 GPIO_HSLVR_HSLV11_Msk +#define GPIO_HSLVR_HSLV12_Pos (12U) +#define GPIO_HSLVR_HSLV12_Msk (0x1UL << GPIO_HSLVR_HSLV12_Pos) /*!< 0x00001000 */ +#define GPIO_HSLVR_HSLV12 GPIO_HSLVR_HSLV12_Msk +#define GPIO_HSLVR_HSLV13_Pos (13U) +#define GPIO_HSLVR_HSLV13_Msk (0x1UL << GPIO_HSLVR_HSLV13_Pos) /*!< 0x00002000 */ +#define GPIO_HSLVR_HSLV13 GPIO_HSLVR_HSLV13_Msk +#define GPIO_HSLVR_HSLV14_Pos (14U) +#define GPIO_HSLVR_HSLV14_Msk (0x1UL << GPIO_HSLVR_HSLV14_Pos) /*!< 0x00004000 */ +#define GPIO_HSLVR_HSLV14 GPIO_HSLVR_HSLV14_Msk +#define GPIO_HSLVR_HSLV15_Pos (15U) +#define GPIO_HSLVR_HSLV15_Msk (0x1UL << GPIO_HSLVR_HSLV15_Pos) /*!< 0x00008000 */ +#define GPIO_HSLVR_HSLV15 GPIO_HSLVR_HSLV15_Msk + +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1UL << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1UL << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1UL << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1UL << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1UL << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1UL << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1UL << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1UL << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk +#define GPIO_SECCFGR_SEC8_Pos (8U) +#define GPIO_SECCFGR_SEC8_Msk (0x1UL << GPIO_SECCFGR_SEC8_Pos) /*!< 0x00000100 */ +#define GPIO_SECCFGR_SEC8 GPIO_SECCFGR_SEC8_Msk +#define GPIO_SECCFGR_SEC9_Pos (9U) +#define GPIO_SECCFGR_SEC9_Msk (0x1UL << GPIO_SECCFGR_SEC9_Pos) /*!< 0x00000200 */ +#define GPIO_SECCFGR_SEC9 GPIO_SECCFGR_SEC9_Msk +#define GPIO_SECCFGR_SEC10_Pos (10U) +#define GPIO_SECCFGR_SEC10_Msk (0x1UL << GPIO_SECCFGR_SEC10_Pos) /*!< 0x00000400 */ +#define GPIO_SECCFGR_SEC10 GPIO_SECCFGR_SEC10_Msk +#define GPIO_SECCFGR_SEC11_Pos (11U) +#define GPIO_SECCFGR_SEC11_Msk (x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */ +#define GPIO_SECCFGR_SEC11 GPIO_SECCFGR_SEC11_Msk +#define GPIO_SECCFGR_SEC12_Pos (12U) +#define GPIO_SECCFGR_SEC12_Msk (0x1UL << GPIO_SECCFGR_SEC12_Pos) /*!< 0x00001000 */ +#define GPIO_SECCFGR_SEC12 GPIO_SECCFGR_SEC12_Msk +#define GPIO_SECCFGR_SEC13_Pos (13U) +#define GPIO_SECCFGR_SEC13_Msk (0x1UL << GPIO_SECCFGR_SEC13_Pos) /*!< 0x00002000 */ +#define GPIO_SECCFGR_SEC13 GPIO_SECCFGR_SEC13_Msk +#define GPIO_SECCFGR_SEC14_Pos (14U) +#define GPIO_SECCFGR_SEC14_Msk (0x1UL << GPIO_SECCFGR_SEC14_Pos) /*!< 0x00004000 */ +#define GPIO_SECCFGR_SEC14 GPIO_SECCFGR_SEC14_Msk +#define GPIO_SECCFGR_SEC15_Pos (15U) +#define GPIO_SECCFGR_SEC15_Msk (0x1UL << GPIO_SECCFGR_SEC15_Pos) /*!< 0x00008000 */ +#define GPIO_SECCFGR_SEC15 GPIO_SECCFGR_SEC15_Msk + +/******************************************************************************/ +/* */ +/* Low Power General Purpose IOs (LPGPIO) */ +/* */ +/******************************************************************************/ +/****************** Bits definition for LPGPIO_MODER register *****************/ +#define LPGPIO_MODER_MOD0_Pos (0U) +#define LPGPIO_MODER_MOD0_Msk (0x1UL << LPGPIO_MODER_MOD0_Pos) /*!< 0x00000001 */ +#define LPGPIO_MODER_MOD0 LPGPIO_MODER_MOD0_Msk +#define LPGPIO_MODER_MOD1_Pos (1U) +#define LPGPIO_MODER_MOD1_Msk (0x1UL << LPGPIO_MODER_MOD1_Pos) /*!< 0x00000002 */ +#define LPGPIO_MODER_MOD1 LPGPIO_MODER_MOD1_Msk +#define LPGPIO_MODER_MOD2_Pos (2U) +#define LPGPIO_MODER_MOD2_Msk (0x1UL << LPGPIO_MODER_MOD2_Pos) /*!< 0x00000004 */ +#define LPGPIO_MODER_MOD2 LPGPIO_MODER_MOD2_Msk +#define LPGPIO_MODER_MOD3_Pos (3U) +#define LPGPIO_MODER_MOD3_Msk (0x1UL << LPGPIO_MODER_MOD3_Pos) /*!< 0x00000008 */ +#define LPGPIO_MODER_MOD3 LPGPIO_MODER_MOD3_Msk +#define LPGPIO_MODER_MOD4_Pos (4U) +#define LPGPIO_MODER_MOD4_Msk (0x1UL << LPGPIO_MODER_MOD4_Pos) /*!< 0x00000010 */ +#define LPGPIO_MODER_MOD4 LPGPIO_MODER_MOD4_Msk +#define LPGPIO_MODER_MOD5_Pos (5U) +#define LPGPIO_MODER_MOD5_Msk (0x1UL << LPGPIO_MODER_MOD5_Pos) /*!< 0x00000020 */ +#define LPGPIO_MODER_MOD5 LPGPIO_MODER_MOD5_Msk +#define LPGPIO_MODER_MOD6_Pos (6U) +#define LPGPIO_MODER_MOD6_Msk (0x1UL << LPGPIO_MODER_MOD6_Pos) /*!< 0x00000040 */ +#define LPGPIO_MODER_MOD6 LPGPIO_MODER_MOD6_Msk +#define LPGPIO_MODER_MOD7_Pos (7U) +#define LPGPIO_MODER_MOD7_Msk (0x1UL << LPGPIO_MODER_MOD7_Pos) /*!< 0x00000080 */ +#define LPGPIO_MODER_MOD7 LPGPIO_MODER_MOD7_Msk +#define LPGPIO_MODER_MOD8_Pos (8U) +#define LPGPIO_MODER_MOD8_Msk (0x1UL << LPGPIO_MODER_MOD8_Pos) /*!< 0x00000100 */ +#define LPGPIO_MODER_MOD8 LPGPIO_MODER_MOD8_Msk +#define LPGPIO_MODER_MOD9_Pos (9U) +#define LPGPIO_MODER_MOD9_Msk (0x1UL << LPGPIO_MODER_MOD9_Pos) /*!< 0x00000200 */ +#define LPGPIO_MODER_MOD9 LPGPIO_MODER_MOD9_Msk +#define LPGPIO_MODER_MOD10_Pos (10U) +#define LPGPIO_MODER_MOD10_Msk (0x1UL << LPGPIO_MODER_MOD10_Pos) /*!< 0x00000400 */ +#define LPGPIO_MODER_MOD10 LPGPIO_MODER_MOD10_Msk +#define LPGPIO_MODER_MOD11_Pos (11U) +#define LPGPIO_MODER_MOD11_Msk (0x1UL << LPGPIO_MODER_MOD11_Pos) /*!< 0x00000800 */ +#define LPGPIO_MODER_MOD11 LPGPIO_MODER_MOD11_Msk +#define LPGPIO_MODER_MOD12_Pos (12U) +#define LPGPIO_MODER_MOD12_Msk (0x1UL << LPGPIO_MODER_MOD12_Pos) /*!< 0x00001000 */ +#define LPGPIO_MODER_MOD12 LPGPIO_MODER_MOD12_Msk +#define LPGPIO_MODER_MOD13_Pos (13U) +#define LPGPIO_MODER_MOD13_Msk (0x1UL << LPGPIO_MODER_MOD13_Pos) /*!< 0x00002000 */ +#define LPGPIO_MODER_MOD13 LPGPIO_MODER_MOD13_Msk +#define LPGPIO_MODER_MOD14_Pos (14U) +#define LPGPIO_MODER_MOD14_Msk (0x1UL << LPGPIO_MODER_MOD14_Pos) /*!< 0x00004000 */ +#define LPGPIO_MODER_MOD14 LPGPIO_MODER_MOD14_Msk +#define LPGPIO_MODER_MOD15_Pos (15U) +#define LPGPIO_MODER_MOD15_Msk (0x1UL << LPGPIO_MODER_MOD15_Pos) /*!< 0x00008000 */ +#define LPGPIO_MODER_MOD15 LPGPIO_MODER_MOD15_Msk + +/****************** Bits definition for LPGPIO_IDR register *******************/ +#define LPGPIO_IDR_ID0_Pos (0U) +#define LPGPIO_IDR_ID0_Msk (0x1UL << LPGPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define LPGPIO_IDR_ID0 LPGPIO_IDR_ID0_Msk +#define LPGPIO_IDR_ID1_Pos (1U) +#define LPGPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define LPGPIO_IDR_ID1 LPGPIO_IDR_ID1_Msk +#define LPGPIO_IDR_ID2_Pos (2U) +#define LPGPIO_IDR_ID2_Msk (0x1UL << LPGPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define LPGPIO_IDR_ID2 LPGPIO_IDR_ID2_Msk +#define LPGPIO_IDR_ID3_Pos (3U) +#define LPGPIO_IDR_ID3_Msk (0x1UL << LPGPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define LPGPIO_IDR_ID3 LPGPIO_IDR_ID3_Msk +#define LPGPIO_IDR_ID4_Pos (4U) +#define LPGPIO_IDR_ID4_Msk (0x1UL << LPGPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define LPGPIO_IDR_ID4 LPGPIO_IDR_ID4_Msk +#define LPGPIO_IDR_ID5_Pos (5U) +#define LPGPIO_IDR_ID5_Msk (0x1UL << LPGPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define LPGPIO_IDR_ID5 LPGPIO_IDR_ID5_Msk +#define LPGPIO_IDR_ID6_Pos (6U) +#define LPGPIO_IDR_ID6_Msk (0x1UL << LPGPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define LPGPIO_IDR_ID6 LPGPIO_IDR_ID6_Msk +#define LPGPIO_IDR_ID7_Pos (7U) +#define LPGPIO_IDR_ID7_Msk (0x1UL << LPGPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define LPGPIO_IDR_ID7 LPGPIO_IDR_ID7_Msk +#define LPGPIO_IDR_ID8_Pos (8U) +#define LPGPIO_IDR_ID8_Msk (0x1UL << LPGPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define LPGPIO_IDR_ID8 LPGPIO_IDR_ID8_Msk +#define LPGPIO_IDR_ID9_Pos (9U) +#define LPGPIO_IDR_ID9_Msk (0x1UL << LPGPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define LPGPIO_IDR_ID9 LPGPIO_IDR_ID9_Msk +#define LPGPIO_IDR_ID10_Pos (10U) +#define LPGPIO_IDR_ID10_Msk (0x1UL << LPGPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define LPGPIO_IDR_ID10 LPGPIO_IDR_ID10_Msk +#define LPGPIO_IDR_ID11_Pos (11U) +#define LPGPIO_IDR_ID11_Msk (0x1UL << LPGPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define LPGPIO_IDR_ID11 LPGPIO_IDR_ID11_Msk +#define LPGPIO_IDR_ID12_Pos (12U) +#define LPGPIO_IDR_ID12_Msk (0x1UL << LPGPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define LPGPIO_IDR_ID12 LPGPIO_IDR_ID12_Msk +#define LPGPIO_IDR_ID13_Pos (13U) +#define LPGPIO_IDR_ID13_Msk (0x1UL << LPGPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define LPGPIO_IDR_ID13 LPGPIO_IDR_ID13_Msk +#define LPGPIO_IDR_ID14_Pos (14U) +#define LPGPIO_IDR_ID14_Msk (0x1UL << LPGPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define LPGPIO_IDR_ID14 LPGPIO_IDR_ID14_Msk +#define LPGPIO_IDR_ID15_Pos (15U) +#define LPGPIO_IDR_ID15_Msk (0x1UL << LPGPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define LPGPIO_IDR_ID15 LPGPIO_IDR_ID15_Msk + +/****************** Bits definition for LPGPIO_ODR register *******************/ +#define LPGPIO_ODR_OD0_Pos (0U) +#define LPGPIO_ODR_OD0_Msk (0x1UL << LPGPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define LPGPIO_ODR_OD0 LPGPIO_ODR_OD0_Msk +#define LPGPIO_ODR_OD1_Pos (1U) +#define LPGPIO_ODR_OD1_Msk (0x1UL << LPGPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define LPGPIO_ODR_OD1 LPGPIO_ODR_OD1_Msk +#define LPGPIO_ODR_OD2_Pos (2U) +#define LPGPIO_ODR_OD2_Msk (0x1UL << LPGPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define LPGPIO_ODR_OD2 LPGPIO_ODR_OD2_Msk +#define LPGPIO_ODR_OD3_Pos (3U) +#define LPGPIO_ODR_OD3_Msk (0x1UL << LPGPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define LPGPIO_ODR_OD3 LPGPIO_ODR_OD3_Msk +#define LPGPIO_ODR_OD4_Pos (4U) +#define LPGPIO_ODR_OD4_Msk (0x1UL << LPGPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define LPGPIO_ODR_OD4 LPGPIO_ODR_OD4_Msk +#define LPGPIO_ODR_OD5_Pos (5U) +#define LPGPIO_ODR_OD5_Msk (0x1UL << LPGPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define LPGPIO_ODR_OD5 LPGPIO_ODR_OD5_Msk +#define LPGPIO_ODR_OD6_Pos (6U) +#define LPGPIO_ODR_OD6_Msk (0x1UL << LPGPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define LPGPIO_ODR_OD6 LPGPIO_ODR_OD6_Msk +#define LPGPIO_ODR_OD7_Pos (7U) +#define LPGPIO_ODR_OD7_Msk (0x1UL << LPGPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define LPGPIO_ODR_OD7 LPGPIO_ODR_OD7_Msk +#define LPGPIO_ODR_OD8_Pos (8U) +#define LPGPIO_ODR_OD8_Msk (0x1UL << LPGPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define LPGPIO_ODR_OD8 LPGPIO_ODR_OD8_Msk +#define LPGPIO_ODR_OD9_Pos (9U) +#define LPGPIO_ODR_OD9_Msk (0x1UL << LPGPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define LPGPIO_ODR_OD9 LPGPIO_ODR_OD9_Msk +#define LPGPIO_ODR_OD10_Pos (10U) +#define LPGPIO_ODR_OD10_Msk (0x1UL << LPGPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define LPGPIO_ODR_OD10 LPGPIO_ODR_OD10_Msk +#define LPGPIO_ODR_OD11_Pos (11U) +#define LPGPIO_ODR_OD11_Msk (0x1UL << LPGPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define LPGPIO_ODR_OD11 LPGPIO_ODR_OD11_Msk +#define LPGPIO_ODR_OD12_Pos (12U) +#define LPGPIO_ODR_OD12_Msk (0x1UL << LPGPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define LPGPIO_ODR_OD12 LPGPIO_ODR_OD12_Msk +#define LPGPIO_ODR_OD13_Pos (13U) +#define LPGPIO_ODR_OD13_Msk (0x1UL << LPGPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define LPGPIO_ODR_OD13 LPGPIO_ODR_OD13_Msk +#define LPGPIO_ODR_OD14_Pos (14U) +#define LPGPIO_ODR_OD14_Msk (0x1UL << LPGPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define LPGPIO_ODR_OD14 LPGPIO_ODR_OD14_Msk +#define LPGPIO_ODR_OD15_Pos (15U) +#define LPGPIO_ODR_OD15_Msk (0x1UL << LPGPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define LPGPIO_ODR_OD15 LPGPIO_ODR_OD15_Msk + +/****************** Bits definition for LPGPIO_BSRR register ******************/ +#define LPGPIO_BSRR_BS0_Pos (0U) +#define LPGPIO_BSRR_BS0_Msk (0x1UL << LPGPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define LPGPIO_BSRR_BS0 LPGPIO_BSRR_BS0_Msk +#define LPGPIO_BSRR_BS1_Pos (1U) +#define LPGPIO_BSRR_BS1_Msk (0x1UL << LPGPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define LPGPIO_BSRR_BS1 LPGPIO_BSRR_BS1_Msk +#define LPGPIO_BSRR_BS2_Pos (2U) +#define LPGPIO_BSRR_BS2_Msk (0x1UL << LPGPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define LPGPIO_BSRR_BS2 LPGPIO_BSRR_BS2_Msk +#define LPGPIO_BSRR_BS3_Pos (3U) +#define LPGPIO_BSRR_BS3_Msk (0x1UL << LPGPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define LPGPIO_BSRR_BS3 LPGPIO_BSRR_BS3_Msk +#define LPGPIO_BSRR_BS4_Pos (4U) +#define LPGPIO_BSRR_BS4_Msk (0x1UL << LPGPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define LPGPIO_BSRR_BS4 LPGPIO_BSRR_BS4_Msk +#define LPGPIO_BSRR_BS5_Pos (5U) +#define LPGPIO_BSRR_BS5_Msk (0x1UL << LPGPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define LPGPIO_BSRR_BS5 LPGPIO_BSRR_BS5_Msk +#define LPGPIO_BSRR_BS6_Pos (6U) +#define LPGPIO_BSRR_BS6_Msk (0x1UL << LPGPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define LPGPIO_BSRR_BS6 LPGPIO_BSRR_BS6_Msk +#define LPGPIO_BSRR_BS7_Pos (7U) +#define LPGPIO_BSRR_BS7_Msk (0x1UL << LPGPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define LPGPIO_BSRR_BS7 LPGPIO_BSRR_BS7_Msk +#define LPGPIO_BSRR_BS8_Pos (8U) +#define LPGPIO_BSRR_BS8_Msk (0x1UL << LPGPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define LPGPIO_BSRR_BS8 LPGPIO_BSRR_BS8_Msk +#define LPGPIO_BSRR_BS9_Pos (9U) +#define LPGPIO_BSRR_BS9_Msk (0x1UL << LPGPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define LPGPIO_BSRR_BS9 LPGPIO_BSRR_BS9_Msk +#define LPGPIO_BSRR_BS10_Pos (10U) +#define LPGPIO_BSRR_BS10_Msk (0x1UL << LPGPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define LPGPIO_BSRR_BS10 LPGPIO_BSRR_BS10_Msk +#define LPGPIO_BSRR_BS11_Pos (11U) +#define LPGPIO_BSRR_BS11_Msk (0x1UL << LPGPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define LPGPIO_BSRR_BS11 LPGPIO_BSRR_BS11_Msk +#define LPGPIO_BSRR_BS12_Pos (12U) +#define LPGPIO_BSRR_BS12_Msk (0x1UL << LPGPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define LPGPIO_BSRR_BS12 LPGPIO_BSRR_BS12_Msk +#define LPGPIO_BSRR_BS13_Pos (13U) +#define LPGPIO_BSRR_BS13_Msk (0x1UL << LPGPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define LPGPIO_BSRR_BS13 LPGPIO_BSRR_BS13_Msk +#define LPGPIO_BSRR_BS14_Pos (14U) +#define LPGPIO_BSRR_BS14_Msk (0x1UL << LPGPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define LPGPIO_BSRR_BS14 LPGPIO_BSRR_BS14_Msk +#define LPGPIO_BSRR_BS15_Pos (15U) +#define LPGPIO_BSRR_BS15_Msk (0x1UL << LPGPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define LPGPIO_BSRR_BS15 LPGPIO_BSRR_BS15_Msk +#define LPGPIO_BSRR_BR0_Pos (16U) +#define LPGPIO_BSRR_BR0_Msk (0x1UL << LPGPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define LPGPIO_BSRR_BR0 LPGPIO_BSRR_BR0_Msk +#define LPGPIO_BSRR_BR1_Pos (17U) +#define LPGPIO_BSRR_BR1_Msk (0x1UL << LPGPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define LPGPIO_BSRR_BR1 LPGPIO_BSRR_BR1_Msk +#define LPGPIO_BSRR_BR2_Pos (18U) +#define LPGPIO_BSRR_BR2_Msk (0x1UL << LPGPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define LPGPIO_BSRR_BR2 LPGPIO_BSRR_BR2_Msk +#define LPGPIO_BSRR_BR3_Pos (19U) +#define LPGPIO_BSRR_BR3_Msk (0x1UL << LPGPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define LPGPIO_BSRR_BR3 LPGPIO_BSRR_BR3_Msk +#define LPGPIO_BSRR_BR4_Pos (20U) +#define LPGPIO_BSRR_BR4_Msk (0x1UL << LPGPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define LPGPIO_BSRR_BR4 LPGPIO_BSRR_BR4_Msk +#define LPGPIO_BSRR_BR5_Pos (21U) +#define LPGPIO_BSRR_BR5_Msk (0x1UL << LPGPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define LPGPIO_BSRR_BR5 LPGPIO_BSRR_BR5_Msk +#define LPGPIO_BSRR_BR6_Pos (22U) +#define LPGPIO_BSRR_BR6_Msk (0x1UL << LPGPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define LPGPIO_BSRR_BR6 LPGPIO_BSRR_BR6_Msk +#define LPGPIO_BSRR_BR7_Pos (23U) +#define LPGPIO_BSRR_BR7_Msk (0x1UL << LPGPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define LPGPIO_BSRR_BR7 LPGPIO_BSRR_BR7_Msk +#define LPGPIO_BSRR_BR8_Pos (24U) +#define LPGPIO_BSRR_BR8_Msk (0x1UL << LPGPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define LPGPIO_BSRR_BR8 LPGPIO_BSRR_BR8_Msk +#define LPGPIO_BSRR_BR9_Pos (25U) +#define LPGPIO_BSRR_BR9_Msk (0x1UL << LPGPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define LPGPIO_BSRR_BR9 LPGPIO_BSRR_BR9_Msk +#define LPGPIO_BSRR_BR10_Pos (26U) +#define LPGPIO_BSRR_BR10_Msk (0x1UL << LPGPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define LPGPIO_BSRR_BR10 LPGPIO_BSRR_BR10_Msk +#define LPGPIO_BSRR_BR11_Pos (27U) +#define LPGPIO_BSRR_BR11_Msk (0x1UL << LPGPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define LPGPIO_BSRR_BR11 LPGPIO_BSRR_BR11_Msk +#define LPGPIO_BSRR_BR12_Pos (28U) +#define LPGPIO_BSRR_BR12_Msk (0x1UL << LPGPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define LPGPIO_BSRR_BR12 LPGPIO_BSRR_BR12_Msk +#define LPGPIO_BSRR_BR13_Pos (29U) +#define LPGPIO_BSRR_BR13_Msk (0x1UL << LPGPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define LPGPIO_BSRR_BR13 LPGPIO_BSRR_BR13_Msk +#define LPGPIO_BSRR_BR14_Pos (30U) +#define LPGPIO_BSRR_BR14_Msk (0x1UL << LPGPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define LPGPIO_BSRR_BR14 LPGPIO_BSRR_BR14_Msk +#define LPGPIO_BSRR_BR15_Pos (31U) +#define LPGPIO_BSRR_BR15_Msk (0x1UL << LPGPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define LPGPIO_BSRR_BR15 LPGPIO_BSRR_BR15_Msk + +/****************** Bits definition for LPGPIO_BRR register ******************/ +#define LPGPIO_BRR_BR0_Pos (0U) +#define LPGPIO_BRR_BR0_Msk (0x1UL << LPGPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define LPGPIO_BRR_BR0 LPGPIO_BRR_BR0_Msk +#define LPGPIO_BRR_BR1_Pos (1U) +#define LPGPIO_BRR_BR1_Msk (0x1UL << LPGPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define LPGPIO_BRR_BR1 LPGPIO_BRR_BR1_Msk +#define LPGPIO_BRR_BR2_Pos (2U) +#define LPGPIO_BRR_BR2_Msk (0x1UL << LPGPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define LPGPIO_BRR_BR2 LPGPIO_BRR_BR2_Msk +#define LPGPIO_BRR_BR3_Pos (3U) +#define LPGPIO_BRR_BR3_Msk (0x1UL << LPGPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define LPGPIO_BRR_BR3 LPGPIO_BRR_BR3_Msk +#define LPGPIO_BRR_BR4_Pos (4U) +#define LPGPIO_BRR_BR4_Msk (0x1UL << LPGPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define LPGPIO_BRR_BR4 LPGPIO_BRR_BR4_Msk +#define LPGPIO_BRR_BR5_Pos (5U) +#define LPGPIO_BRR_BR5_Msk (0x1UL << LPGPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define LPGPIO_BRR_BR5 LPGPIO_BRR_BR5_Msk +#define LPGPIO_BRR_BR6_Pos (6U) +#define LPGPIO_BRR_BR6_Msk (0x1UL << LPGPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define LPGPIO_BRR_BR6 LPGPIO_BRR_BR6_Msk +#define LPGPIO_BRR_BR7_Pos (7U) +#define LPGPIO_BRR_BR7_Msk (0x1UL << LPGPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define LPGPIO_BRR_BR7 LPGPIO_BRR_BR7_Msk +#define LPGPIO_BRR_BR8_Pos (8U) +#define LPGPIO_BRR_BR8_Msk (0x1UL << LPGPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define LPGPIO_BRR_BR8 LPGPIO_BRR_BR8_Msk +#define LPGPIO_BRR_BR9_Pos (9U) +#define LPGPIO_BRR_BR9_Msk (0x1UL << LPGPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define LPGPIO_BRR_BR9 LPGPIO_BRR_BR9_Msk +#define LPGPIO_BRR_BR10_Pos (10U) +#define LPGPIO_BRR_BR10_Msk (0x1UL << LPGPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define LPGPIO_BRR_BR10 LPGPIO_BRR_BR10_Msk +#define LPGPIO_BRR_BR11_Pos (11U) +#define LPGPIO_BRR_BR11_Msk (0x1UL << LPGPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define LPGPIO_BRR_BR11 LPGPIO_BRR_BR11_Msk +#define LPGPIO_BRR_BR12_Pos (12U) +#define LPGPIO_BRR_BR12_Msk (0x1UL << LPGPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define LPGPIO_BRR_BR12 LPGPIO_BRR_BR12_Msk +#define LPGPIO_BRR_BR13_Pos (13U) +#define LPGPIO_BRR_BR13_Msk (0x1UL << LPGPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define LPGPIO_BRR_BR13 LPGPIO_BRR_BR13_Msk +#define LPGPIO_BRR_BR14_Pos (14U) +#define LPGPIO_BRR_BR14_Msk (0x1UL << LPGPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define LPGPIO_BRR_BR14 LPGPIO_BRR_BR14_Msk +#define LPGPIO_BRR_BR15_Pos (15U) +#define LPGPIO_BRR_BR15_Msk (0x1UL << LPGPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define LPGPIO_BRR_BR15 LPGPIO_BRR_BR15_Msk + +/******************************************************************************/ +/* */ +/* ICACHE */ +/* */ +/******************************************************************************/ +/****************** Bit definition for ICACHE_CR register *******************/ +#define ICACHE_CR_EN_Pos (0U) +#define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */ +#define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< Enable */ +#define ICACHE_CR_CACHEINV_Pos (1U) +#define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ +#define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< Cache invalidation */ +#define ICACHE_CR_WAYSEL_Pos (2U) +#define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */ +#define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< Ways selection */ +#define ICACHE_CR_HITMEN_Pos (16U) +#define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */ +#define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< Hit monitor enable */ +#define ICACHE_CR_MISSMEN_Pos (17U) +#define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */ +#define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< Miss monitor enable */ +#define ICACHE_CR_HITMRST_Pos (18U) +#define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */ +#define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< Hit monitor reset */ +#define ICACHE_CR_MISSMRST_Pos (19U) +#define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */ +#define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< Miss monitor reset */ + +/****************** Bit definition for ICACHE_SR register *******************/ +#define ICACHE_SR_BUSYF_Pos (0U) +#define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< Busy flag */ +#define ICACHE_SR_BSYENDF_Pos (1U) +#define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< Busy end flag */ +#define ICACHE_SR_ERRF_Pos (2U) +#define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< Cache error flag */ + +/****************** Bit definition for ICACHE_IER register ******************/ +#define ICACHE_IER_BSYENDIE_Pos (1U) +#define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */ +#define ICACHE_IER_ERRIE_Pos (2U) +#define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< Cache error interrupt enable */ + +/****************** Bit definition for ICACHE_FCR register ******************/ +#define ICACHE_FCR_CBSYENDF_Pos (1U) +#define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< Busy end flag clear */ +#define ICACHE_FCR_CERRF_Pos (2U) +#define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk /*!< Cache error flag clear */ + +/****************** Bit definition for ICACHE_HMONR register ****************/ +#define ICACHE_HMONR_HITMON_Pos (0U) +#define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */ +#define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< Cache hit monitor register */ + +/****************** Bit definition for ICACHE_MMONR register ****************/ +#define ICACHE_MMONR_MISSMON_Pos (0U) +#define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */ +#define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< Cache miss monitor register */ + +/****************** Bit definition for ICACHE_CRRx register *****************/ +#define ICACHE_CRRx_BASEADDR_Pos (0U) +#define ICACHE_CRRx_BASEADDR_Msk (0xFFUL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x000000FF */ +#define ICACHE_CRRx_BASEADDR ICACHE_CRRx_BASEADDR_Msk /*!< Base address of region X to remap */ +#define ICACHE_CRRx_RSIZE_Pos (9U) +#define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00 */ +#define ICACHE_CRRx_RSIZE ICACHE_CRRx_RSIZE_Msk /*!< Region X size */ +#define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200 */ +#define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400 */ +#define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800 */ +#define ICACHE_CRRx_REN_Pos (15U) +#define ICACHE_CRRx_REN_Msk (0x1UL << ICACHE_CRRx_REN_Pos) /*!< 0x00008000 */ +#define ICACHE_CRRx_REN ICACHE_CRRx_REN_Msk /*!< Region X enable */ +#define ICACHE_CRRx_REMAPADDR_Pos (16U) +#define ICACHE_CRRx_REMAPADDR_Msk (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x07FF0000 */ +#define ICACHE_CRRx_REMAPADDR ICACHE_CRRx_REMAPADDR_Msk /*!< Remap address of Region X to be remapped */ +#define ICACHE_CRRx_MSTSEL_Pos (28U) +#define ICACHE_CRRx_MSTSEL_Msk (0x1UL << ICACHE_CRRx_MSTSEL_Pos) /*!< 0x10000000 */ +#define ICACHE_CRRx_MSTSEL ICACHE_CRRx_MSTSEL_Msk /*!< Region X AHB cache master selection */ +#define ICACHE_CRRx_HBURST_Pos (31U) +#define ICACHE_CRRx_HBURST_Msk (0x1UL << ICACHE_CRRx_HBURST_Pos) /*!< 0x80000000 */ +#define ICACHE_CRRx_HBURST ICACHE_CRRx_HBURST_Msk /*!< Region X output burst type */ + +/******************************************************************************/ +/* */ +/* DCACHE */ +/* */ +/******************************************************************************/ +/****************** Bit definition for DCACHE_CR register *******************/ +#define DCACHE_CR_EN_Pos (0U) +#define DCACHE_CR_EN_Msk (0x1UL << DCACHE_CR_EN_Pos) /*!< 0x00000001 */ +#define DCACHE_CR_EN DCACHE_CR_EN_Msk /*!< Enable */ +#define DCACHE_CR_CACHEINV_Pos (1U) +#define DCACHE_CR_CACHEINV_Msk (0x1UL << DCACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ +#define DCACHE_CR_CACHEINV DCACHE_CR_CACHEINV_Msk /*!< Cache invalidation */ +#define DCACHE_CR_CACHECMD_Pos (8U) +#define DCACHE_CR_CACHECMD_Msk (0x7UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000700 */ +#define DCACHE_CR_CACHECMD DCACHE_CR_CACHECMD_Msk /*!< Cache command */ +#define DCACHE_CR_CACHECMD_0 (0x1UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000100 */ +#define DCACHE_CR_CACHECMD_1 (0x2UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000200 */ +#define DCACHE_CR_CACHECMD_2 (0x4UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000400 */ +#define DCACHE_CR_STARTCMD_Pos (11U) +#define DCACHE_CR_STARTCMD_Msk (0x1UL << DCACHE_CR_STARTCMD_Pos) /*!< 0x00000800 */ +#define DCACHE_CR_STARTCMD DCACHE_CR_STARTCMD_Msk /*!< Start command */ +#define DCACHE_CR_RHITMEN_Pos (16U) +#define DCACHE_CR_RHITMEN_Msk (0x1UL << DCACHE_CR_RHITMEN_Pos) /*!< 0x00010000 */ +#define DCACHE_CR_RHITMEN DCACHE_CR_RHITMEN_Msk /*!< Read Hit monitor enable */ +#define DCACHE_CR_RMISSMEN_Pos (17U) +#define DCACHE_CR_RMISSMEN_Msk (0x1UL << DCACHE_CR_RMISSMEN_Pos) /*!< 0x00020000 */ +#define DCACHE_CR_RMISSMEN DCACHE_CR_RMISSMEN_Msk /*!< Read Miss monitor enable */ +#define DCACHE_CR_RHITMRST_Pos (18U) +#define DCACHE_CR_RHITMRST_Msk (0x1UL << DCACHE_CR_RHITMRST_Pos) /*!< 0x00040000 */ +#define DCACHE_CR_RHITMRST DCACHE_CR_RHITMRST_Msk /*!< Read Hit monitor reset */ +#define DCACHE_CR_RMISSMRST_Pos (19U) +#define DCACHE_CR_RMISSMRST_Msk (0x1UL << DCACHE_CR_RMISSMRST_Pos) /*!< 0x00080000 */ +#define DCACHE_CR_RMISSMRST DCACHE_CR_RMISSMRST_Msk /*!< Read Miss monitor reset */ +#define DCACHE_CR_WHITMEN_Pos (20U) +#define DCACHE_CR_WHITMEN_Msk (0x1UL << DCACHE_CR_WHITMEN_Pos) /*!< 0x00100000 */ +#define DCACHE_CR_WHITMEN DCACHE_CR_WHITMEN_Msk /*!< Write Hit monitor enable */ +#define DCACHE_CR_WMISSMEN_Pos (21U) +#define DCACHE_CR_WMISSMEN_Msk (0x1UL << DCACHE_CR_WMISSMEN_Pos) /*!< 0x00200000 */ +#define DCACHE_CR_WMISSMEN DCACHE_CR_WMISSMEN_Msk /*!< Write Miss monitor enable */ +#define DCACHE_CR_WHITMRST_Pos (22U) +#define DCACHE_CR_WHITMRST_Msk (0x1UL << DCACHE_CR_WHITMRST_Pos) /*!< 0x00400000 */ +#define DCACHE_CR_WHITMRST DCACHE_CR_WHITMRST_Msk /*!< Write Hit monitor reset */ +#define DCACHE_CR_WMISSMRST_Pos (23U) +#define DCACHE_CR_WMISSMRST_Msk (0x1UL << DCACHE_CR_WMISSMRST_Pos) /*!< 0x00800000 */ +#define DCACHE_CR_WMISSMRST DCACHE_CR_WMISSMRST_Msk /*!< Write Miss monitor reset */ +#define DCACHE_CR_HBURST_Pos (31U) +#define DCACHE_CR_HBURST_Msk (0x1UL << DCACHE_CR_HBURST_Pos) /*!< 0x80000000 */ +#define DCACHE_CR_HBURST DCACHE_CR_HBURST_Msk /*!< Read burst type */ + +/****************** Bit definition for DCACHE_SR register *******************/ +#define DCACHE_SR_BUSYF_Pos (0U) +#define DCACHE_SR_BUSYF_Msk (0x1UL << DCACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define DCACHE_SR_BUSYF DCACHE_SR_BUSYF_Msk /*!< Busy flag */ +#define DCACHE_SR_BSYENDF_Pos (1U) +#define DCACHE_SR_BSYENDF_Msk (0x1UL << DCACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define DCACHE_SR_BSYENDF DCACHE_SR_BSYENDF_Msk /*!< Busy end flag */ +#define DCACHE_SR_ERRF_Pos (2U) +#define DCACHE_SR_ERRF_Msk (0x1UL << DCACHE_SR_ERRF_Pos) /*!< 0x00000004 */ +#define DCACHE_SR_ERRF DCACHE_SR_ERRF_Msk /*!< Cache error flag */ +#define DCACHE_SR_BUSYCMDF_Pos (3U) +#define DCACHE_SR_BUSYCMDF_Msk (0x1UL << DCACHE_SR_BUSYCMDF_Pos) /*!< 0x00000008 */ +#define DCACHE_SR_BUSYCMDF DCACHE_SR_BUSYCMDF_Msk /*!< Busy command flag */ +#define DCACHE_SR_CMDENDF_Pos (4U) +#define DCACHE_SR_CMDENDF_Msk (0x1UL << DCACHE_SR_CMDENDF_Pos) /*!< 0x00000010 */ +#define DCACHE_SR_CMDENDF DCACHE_SR_CMDENDF_Msk /*!< Command end flag */ + +/****************** Bit definition for DCACHE_IER register ******************/ +#define DCACHE_IER_BSYENDIE_Pos (1U) +#define DCACHE_IER_BSYENDIE_Msk (0x1UL << DCACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define DCACHE_IER_BSYENDIE DCACHE_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */ +#define DCACHE_IER_ERRIE_Pos (2U) +#define DCACHE_IER_ERRIE_Msk (0x1UL << DCACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define DCACHE_IER_ERRIE DCACHE_IER_ERRIE_Msk /*!< Cache error interrupt enable */ +#define DCACHE_IER_CMDENDIE_Pos (4U) +#define DCACHE_IER_CMDENDIE_Msk (0x1UL << DCACHE_IER_CMDENDIE_Pos) /*!< 0x00000010 */ +#define DCACHE_IER_CMDENDIE DCACHE_IER_CMDENDIE_Msk /*!< Command end interrupt enable */ + +/****************** Bit definition for DCACHE_FCR register ******************/ +#define DCACHE_FCR_CBSYENDF_Pos (1U) +#define DCACHE_FCR_CBSYENDF_Msk (0x1UL << DCACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define DCACHE_FCR_CBSYENDF DCACHE_FCR_CBSYENDF_Msk /*!< Busy end flag clear */ +#define DCACHE_FCR_CERRF_Pos (2U) +#define DCACHE_FCR_CERRF_Msk (0x1UL << DCACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define DCACHE_FCR_CERRF DCACHE_FCR_CERRF_Msk /*!< Cache error flag clear */ +#define DCACHE_FCR_CCMDENDF_Pos (4U) +#define DCACHE_FCR_CCMDENDF_Msk (0x1UL << DCACHE_FCR_CCMDENDF_Pos) /*!< 0x00000010 */ +#define DCACHE_FCR_CCMDENDF DCACHE_FCR_CCMDENDF_Msk /*!< Command end flag clear */ + +/****************** Bit definition for DCACHE_RHMONR register ****************/ +#define DCACHE_RHMONR_RHITMON_Pos (0U) +#define DCACHE_RHMONR_RHITMON_Msk (0xFFFFFFFFUL << DCACHE_RHMONR_RHITMON_Pos) /*!< 0xFFFFFFFF */ +#define DCACHE_RHMONR_RHITMON DCACHE_RHMONR_RHITMON_Msk /*!< Cache Read hit monitor register */ + +/****************** Bit definition for DCACHE_RMMONR register ****************/ +#define DCACHE_RMMONR_RMISSMON_Pos (0U) +#define DCACHE_RMMONR_RMISSMON_Msk (0xFFFFUL << DCACHE_RMMONR_RMISSMON_Pos) /*!< 0x0000FFFF */ +#define DCACHE_RMMONR_RMISSMON DCACHE_RMMONR_RMISSMON_Msk /*!< Cache Read miss monitor register */ + +/****************** Bit definition for DCACHE_WHMONR register ****************/ +#define DCACHE_WHMONR_WHITMON_Pos (0U) +#define DCACHE_WHMONR_WHITMON_Msk (0xFFFFFFFFUL << DCACHE_WHMONR_WHITMON_Pos) /*!< 0xFFFFFFFF */ +#define DCACHE_WHMONR_WHITMON DCACHE_WHMONR_WHITMON_Msk /*!< Cache Read hit monitor register */ + +/****************** Bit definition for DCACHE_WMMONR register ****************/ +#define DCACHE_WMMONR_WMISSMON_Pos (0U) +#define DCACHE_WMMONR_WMISSMON_Msk (0xFFFFUL << DCACHE_WMMONR_WMISSMON_Pos) /*!< 0x0000FFFF */ +#define DCACHE_WMMONR_WMISSMON DCACHE_WMMONR_WMISSMON_Msk /*!< Cache Read miss monitor register */ + +/****************** Bit definition for DCACHE_CMDRSADDRR register ****************/ +#define DCACHE_CMDRSADDRR_CMDSTARTADDR_Pos (0U) +#define DCACHE_CMDRSADDRR_CMDSTARTADDR_Msk (0xFFFFFFF0UL << DCACHE_CMDRSADDRR_CMDSTARTADDR_Pos) /*!< 0xFFFFFFF0 */ +#define DCACHE_CMDRSADDRR_CMDSTARTADDR DCACHE_CMDRSADDRR_CMDSTARTADDR_Msk /*!< Command start address */ + +/****************** Bit definition for DCACHE_CMDREADDRR register ****************/ +#define DCACHE_CMDREADDRR_CMDENDADDR_Pos (0U) +#define DCACHE_CMDREADDRR_CMDENDADDR_Msk (0xFFFFFFF0UL << DCACHE_CMDREADDRR_CMDENDADDR_Pos) /*!< 0xFFFFFFF0 */ +#define DCACHE_CMDREADDRR_CMDENDADDR DCACHE_CMDREADDRR_CMDENDADDR_Msk /*!< Command end address */ + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ + +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x000000F0 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ +#define COMP_CSR_INPSEL_Pos (8U) +#define COMP_CSR_INPSEL_Msk (0x7UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000700 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000200 */ +#define COMP_CSR_INPSEL_2 (0x4UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000400 */ +#define COMP_CSR_WINMODE_Pos (11U) +#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000800 */ +#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ +#define COMP_CSR_WINOUT_Pos (14U) +#define COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk /*!< Pair of comparators window output level. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00030000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator input hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ +#define COMP_CSR_PWRMODE_Pos (18U) +#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x000C0000 */ +#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */ +#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00040000 */ +#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKSEL_Pos (20U) +#define COMP_CSR_BLANKSEL_Msk (0x1FUL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01F00000 */ +#define COMP_CSR_BLANKSEL COMP_CSR_BLANKSEL_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKSEL_0 (0x01UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKSEL_1 (0x02UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00200000 */ +#define COMP_CSR_BLANKSEL_2 (0x04UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BLANKSEL_3 (0x08UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00800000 */ +#define COMP_CSR_BLANKSEL_4 (0x10UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* Operational Amplifier (OPAMP) */ +/* */ +/******************************************************************************/ +/********************* Bit definition for OPAMPx_CSR register ***************/ +#define OPAMP_CSR_OPAEN_Pos (0U) +#define OPAMP_CSR_OPAEN_Msk (0x1UL << OPAMP_CSR_OPAEN_Pos) /*!< 0x00000001 */ +#define OPAMP_CSR_OPAEN OPAMP_CSR_OPAEN_Msk /*!< OPAMP enable */ +#define OPAMP_CSR_OPALPM_Pos (1U) +#define OPAMP_CSR_OPALPM_Msk (0x1UL << OPAMP_CSR_OPALPM_Pos) /*!< 0x00000002 */ +#define OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk /*!< Operational amplifier Low Power Mode */ +#define OPAMP_CSR_OPAMODE_Pos (2U) +#define OPAMP_CSR_OPAMODE_Msk (0x3UL << OPAMP_CSR_OPAMODE_Pos) /*!< 0x0000000C */ +#define OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk /*!< Operational amplifier PGA mode */ +#define OPAMP_CSR_OPAMODE_0 (0x1UL << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000004 */ +#define OPAMP_CSR_OPAMODE_1 (0x2UL << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000008 */ +#define OPAMP_CSR_PGA_GAIN_Pos (4U) +#define OPAMP_CSR_PGA_GAIN_Msk (0x3UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00000030 */ +#define OPAMP_CSR_PGA_GAIN OPAMP_CSR_PGA_GAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */ +#define OPAMP_CSR_PGA_GAIN_0 (0x1UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00000010 */ +#define OPAMP_CSR_PGA_GAIN_1 (0x2UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00000020 */ +#define OPAMP_CSR_VM_SEL_Pos (8U) +#define OPAMP_CSR_VM_SEL_Msk (0x3UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000300 */ +#define OPAMP_CSR_VM_SEL OPAMP_CSR_VM_SEL_Msk /*!< Inverting input selection */ +#define OPAMP_CSR_VM_SEL_0 (0x1UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000100 */ +#define OPAMP_CSR_VM_SEL_1 (0x2UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000200 */ +#define OPAMP_CSR_VP_SEL_Pos (10U) +#define OPAMP_CSR_VP_SEL_Msk (0x1UL << OPAMP_CSR_VP_SEL_Pos) /*!< 0x00000400 */ +#define OPAMP_CSR_VP_SEL OPAMP_CSR_VP_SEL_Msk /*!< Non inverted input selection */ +#define OPAMP_CSR_CALON_Pos (12U) +#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00001000 */ +#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */ +#define OPAMP_CSR_CALSEL_Pos (13U) +#define OPAMP_CSR_CALSEL_Msk (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */ +#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */ +#define OPAMP_CSR_USERTRIM_Pos (14U) +#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00004000 */ +#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */ +#define OPAMP_CSR_CALOUT_Pos (15U) +#define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos) /*!< 0x00008000 */ +#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier calibration output */ +#define OPAMP_CSR_HSM_Pos (30U) +#define OPAMP_CSR_HSM_Msk (0x1UL << OPAMP_CSR_HSM_Pos) /*!< 0x40000000 */ +#define OPAMP_CSR_HSM OPAMP_CSR_HSM_Msk /*!< Operational amplifier high speed mode */ +#define OPAMP_CSR_OPARANGE_Pos (31U) +#define OPAMP_CSR_OPARANGE_Msk (0x1UL << OPAMP_CSR_OPARANGE_Pos) /*!< 0x80000000 */ +#define OPAMP_CSR_OPARANGE OPAMP_CSR_OPARANGE_Msk /*!< Operational amplifier range setting */ + +/******************* Bit definition for OPAMPx_OTR register ******************/ +#define OPAMP_OTR_TRIMOFFSETN_Pos (0U) +#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */ +#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */ +#define OPAMP_OTR_TRIMOFFSETP_Pos (8U) +#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */ +#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */ + +/******************* Bit definition for OPAMPx_LPOTR register ****************/ +#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0U) +#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */ +#define OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */ +#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8U) +#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */ +#define OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */ + +/******************************************************************************/ +/* */ +/* MDF/ADF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for MDF/ADF_GCR register ********************/ +#define MDF_GCR_TRGO_Pos (0U) +#define MDF_GCR_TRGO_Msk (0x1UL << MDF_GCR_TRGO_Pos) /*!< 0x00000001 */ +#define MDF_GCR_TRGO MDF_GCR_TRGO_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk + +/******************** Bits definition for TAMP_COUNTR register ***************/ +#define TAMP_COUNTR_Pos (16U) +#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ +#define TAMP_COUNTR TAMP_COUNTR_Msk + +/******************** Bits definition for TAMP_ERCFGR register ***************/ +#define TAMP_ERCFGR0_Pos (0U) +#define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* Touch Sensing Controller (TSC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TSC_CR register *********************/ +#define TSC_CR_TSCE_Pos (0U) +#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ +#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32u5xx.h" /*!< STM32U5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ + uint32_t RESERVED3[246]; /*!< Reserved, */ + __IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */ + __IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; +} I2C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, 0x24 */ + __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ + uint32_t RESERVED4[7]; /*!< Reserved4, Address offset: 0x84-0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ + uint32_t RESERVED5[7]; /*!< Reserved5, Address offset: 0xA4-0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ + uint32_t RESERVED7[7]; /*!< Reserved7, Address offset: 0xD4-0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */ + __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */ + __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */ + __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */ + __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x180 */ + uint32_t RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x200 */ + __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ + uint32_t RESERVED2[240]; /*!< Reserved, Address offset: 0x30-0x3EC */ + __IO uint32_t HWCFGR; /*!< ICACHE HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< ICACHE version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ICACHE IP identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ICACHE size identification register, Address offset: 0x3FC */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + + +/** + * @brief MDF/ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ +}MDF_TypeDef; + +/** + * @brief MDF/ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ + __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ + __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ + __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ + __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + + +/** + * @brief OTFDEC register + */ +typedef struct +{ + __IO uint32_t REG_CONFIGR; /*!< OTFDEC Region Configuration register, Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_START_ADDR; /*!< OTFDEC Region Start Address register, Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_END_ADDR; /*!< OTFDEC Region End Address register, Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER0; /*!< OTFDEC Region Nonce register 0, Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER1; /*!< OTFDEC Region Nonce register 1, Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR0; /*!< OTFDEC Region Key register 0, Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR1; /*!< OTFDEC Region Key register 1, Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR2; /*!< OTFDEC Region Key register 2, Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR3; /*!< OTFDEC Region Key register 3, Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4) */ +} OTFDEC_Region_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< OTFDEC Control register, Address offset: 0x000 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x004-0x00C */ + __IO uint32_t PRIVCFGR; /*!< OTFDEC Privileged access control Configuration register, Address offset: 0x010 */ + uint32_t RESERVED2[187]; /*!< Reserved, Address offset: 0x014-0x2FC */ + __IO uint32_t ISR; /*!< OTFDEC Interrupt Status register, Address offset: 0x300 */ + __IO uint32_t ICR; /*!< OTFDEC Interrupt Clear register, Address offset: 0x304 */ + __IO uint32_t IER; /*!< OTFDEC Interrupt Enable register, Address offset: 0x308 */ +} OTFDEC_TypeDef; + + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x20 */ + __IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + uint32_t RESERVED1[1]; /*!< Reserved1, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + __IO uint32_t BDSR; /*!< Power backup domain status register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + uint32_t RESERVED2[2]; /*!< Reserved2, Address offset: 0x78-0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */ + __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */ + __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */ + __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */ + __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */ + __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */ + __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */ + __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */ + __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */ + __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */ + __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */ + uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + uint32_t RESERVED2[16];/*!< RESERVED2, Address offset: 0x30 - 0x6C */ +} SYSCFG_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + __IO uint32_t RESERVED0[8]; /*!< Reserved, */ + __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IO uint32_t TXBD; /*!= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0x30000UL) /*!< SRAM1=192k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ +#define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */ + +/* External memories base addresses - Not aliased */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ + + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (512 KB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (192 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x20030000UL) /*!< SRAM2 (64 KB) non-secure base address */ +#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) +#define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08308UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define USB_DRD_BASE_NS (APB2PERIPH_BASE_NS + 0x06000UL) +#define USB_DRD_PMAADDR_NS (APB2PERIPH_BASE_NS + 0x06400UL) +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) +#define OTFDEC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5000UL) +#define OTFDEC1_REGION1_BASE_NS (OTFDEC1_BASE_NS + 0x20UL) +#define OTFDEC1_REGION2_BASE_NS (OTFDEC1_BASE_NS + 0x50UL) +#define OTFDEC1_REGION3_BASE_NS (OTFDEC1_BASE_NS + 0x80UL) +#define OTFDEC1_REGION4_BASE_NS (OTFDEC1_BASE_NS + 0xB0UL) +#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL) +#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL) +#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) +#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS) +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1308UL) +#define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL) +#define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL) +#define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL) +#define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL) +#define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL) +#define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL) +#define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL) +#define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL) +#define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 2 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (192 KB) secure base address */ +#define SRAM2_BASE_S (0x30030000UL) /*!< SRAM2 (64 KB) secure base address */ +#define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) + +/*!< APB3 Secure peripherals */ +#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) +#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08308UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define USB_DRD_BASE_S (APB2PERIPH_BASE_S + 0x06000UL) +#define USB_DRD_PMAADDR_S (APB2PERIPH_BASE_S + 0x06400UL) +#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) +#define OTFDEC1_BASE_S (AHB2PERIPH_BASE_S + 0xA5000UL) +#define OTFDEC1_REGION1_BASE_S (OTFDEC1_BASE_S + 0x20UL) +#define OTFDEC1_REGION2_BASE_S (OTFDEC1_BASE_S + 0x50UL) +#define OTFDEC1_REGION3_BASE_S (OTFDEC1_BASE_S + 0x80UL) +#define OTFDEC1_REGION4_BASE_S (OTFDEC1_BASE_S + 0xB0UL) +#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) +#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) +#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL) +#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1308UL) +#define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) +#define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL) +#define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL) +#define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL) +#define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL) +#define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL) +#define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) +#define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) + + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0044000UL) +#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ +#define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */ + + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0U) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0U) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1U) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define USB_DRD_FS_NS ((USB_DRD_TypeDef *) USB_DRD_BASE_NS) +#define USB_DRD_PMA_BUFF_NS ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define OTFDEC1_NS ((OTFDEC_TypeDef *) OTFDEC1_BASE_NS) +#define OTFDEC1_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_NS) +#define OTFDEC1_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_NS) +#define OTFDEC1_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_NS) +#define OTFDEC1_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS) +#define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS) +#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) +#define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS) +#define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS) +#define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS) +#define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS) +#define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) + +/*!< APB2 Secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) + +/*!< APB3 secure peripherals */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) +#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define USB_DRD_FS_S ((USB_DRD_TypeDef *) USB_DRD_BASE_S) +#define USB_DRD_PMA_BUFF_S ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_S) +#define AES_S ((AES_TypeDef *) AES_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SAES_S ((AES_TypeDef *) SAES_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define OTFDEC1_S ((OTFDEC_TypeDef *) OTFDEC1_BASE_S) +#define OTFDEC1_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_S) +#define OTFDEC1_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_S) +#define OTFDEC1_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_S) +#define OTFDEC1_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S) +#define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S) +#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) +#define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S) +#define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S) +#define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S) +#define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S) +#define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S) + +/*!< DBGMCU peripheral */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM4_BASE SRAM4_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define FMAC FMAC_S +#define FMAC_BASE FMAC_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define LPDMA1 LPDMA1_S +#define LPDMA1_BASE LPDMA1_BASE_S + +#define LPDMA1_Channel0 LPDMA1_Channel0_S +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S + +#define LPDMA1_Channel1 LPDMA1_Channel1_S +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S + +#define LPDMA1_Channel2 LPDMA1_Channel2_S +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S + +#define LPDMA1_Channel3 LPDMA1_Channel3_S +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + + +#define LPGPIO1 LPGPIO1_S +#define LPGPIO1_BASE LPGPIO1_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_S +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZSC2 GTZC_TZSC2_S +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_TZIC2 GTZC_TZIC2_S +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + + +#define GTZC_MPCBB4 GTZC_MPCBB4_S +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define DAC DAC_S +#define DAC_BASE DAC_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define OPAMP OPAMP_S +#define OPAMP_BASE OPAMP_BASE_S + +#define OPAMP1 OPAMP1_S +#define OPAMP1_BASE OPAMP1_BASE_S + +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define COMP12 COMP12_S +#define COMP12_BASE COMP12_BASE_S + +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S + +#define COMP12_COMMON COMP12_COMMON_S +#define COMP12_COMMON_BASE COMP1_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + + +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S + +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define AES AES_S +#define AES_BASE AES_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S + +#define OTFDEC1 OTFDEC1_S +#define OTFDEC1_BASE OTFDEC1_BASE_S + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_S +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_S + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_S +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_S + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_S +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_S + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_S +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_S + + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + + + +#define USB_DRD_FS USB_DRD_FS_S +#define USB_DRD_BASE USB_DRD_BASE_S +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_S +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_S + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM4_BASE SRAM4_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define FMAC FMAC_NS +#define FMAC_BASE FMAC_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define LPDMA1 LPDMA1_NS +#define LPDMA1_BASE LPDMA1_BASE_NS + +#define LPDMA1_Channel0 LPDMA1_Channel0_NS +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS + +#define LPDMA1_Channel1 LPDMA1_Channel1_NS +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS + +#define LPDMA1_Channel2 LPDMA1_Channel2_NS +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS + +#define LPDMA1_Channel3 LPDMA1_Channel3_NS +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define LPGPIO1 LPGPIO1_NS +#define LPGPIO1_BASE LPGPIO1_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_NS +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZSC2 GTZC_TZSC2_NS +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_TZIC2 GTZC_TZIC2_NS +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + + +#define GTZC_MPCBB4 GTZC_MPCBB4_NS +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define OPAMP OPAMP_NS +#define OPAMP_BASE OPAMP_BASE_NS + +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS + +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define COMP12 COMP12_NS +#define COMP12_BASE COMP12_BASE_NS + +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS + +#define COMP12_COMMON COMP12_COMMON_NS +#define COMP12_COMMON_BASE COMP1_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS + +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define AES AES_NS +#define AES_BASE AES_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS + +#define OTFDEC1 OTFDEC1_NS +#define OTFDEC1_BASE OTFDEC1_BASE_NS + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_NS +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_NS + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_NS +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_NS + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_NS +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_NS + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_NS +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_NS + + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + + +#define USB_DRD_FS USB_DRD_FS_NS +#define USB_DRD_BASE USB_DRD_BASE_NS +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_NS +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_NS + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS +#endif + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ +#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_ADCALLIN_Pos (16U) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ + +#define ADC_CR_CALINDEX_Pos (24U) +#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ +#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ +#define ADC_CR_CALINDEX0_Pos (24U) +#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ +#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ +#define ADC_CR_CALINDEX1_Pos (25U) +#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ +#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ +#define ADC_CR_CALINDEX2_Pos (26U) +#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ +#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ +#define ADC_CR_CALINDEX3_Pos (27U) +#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ +#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR1_DMNGT_Pos (0U) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC4_CFGR1_DMAEN_Pos (0U) +#define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC4_CFGR1_DMACFG_Pos (1U) +#define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC4_CFGR1_SCANDIR_Pos (4U) +#define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC4_CFGR1_ALIGN_Pos (5U) +#define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (5U) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ + +#define ADC_CFGR1_AUTDLY_Pos (14U) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC4_CFGR1_WAIT_Pos (14U) +#define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR1_DISCNUM_Pos (17U) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20U) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR1_JAWD1EN_Pos (24U) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR1_JAUTO_Pos (25U) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +/* Specific ADC4 */ +#define ADC4_CFGR1_EXTSEL_Pos (6U) +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ + +#define ADC4_CFGR1_CHSELRMOD_Pos (21U) +#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_BULB_Pos (13U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (27U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* Specific ADC4 */ +#define ADC4_CFGR2_OVSR_Pos (2U) +#define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC4_CFGR2_LFTRIG_Pos (29U) +#define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC4_SMPR_SMP1_Pos (0U) +#define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC4_SMPR_SMP2_Pos (4U) +#define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC4_SMPR_SMPSEL_Pos (8U) +#define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ +#define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ +#define ADC4_SMPR_SMPSEL0_Pos (8U) +#define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ +#define ADC4_SMPR_SMPSEL1_Pos (9U) +#define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ +#define ADC4_SMPR_SMPSEL2_Pos (10U) +#define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ +#define ADC4_SMPR_SMPSEL3_Pos (11U) +#define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ +#define ADC4_SMPR_SMPSEL4_Pos (12U) +#define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ +#define ADC4_SMPR_SMPSEL5_Pos (13U) +#define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ +#define ADC4_SMPR_SMPSEL6_Pos (14U) +#define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ +#define ADC4_SMPR_SMPSEL7_Pos (15U) +#define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ +#define ADC4_SMPR_SMPSEL8_Pos (16U) +#define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ +#define ADC4_SMPR_SMPSEL9_Pos (17U) +#define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ +#define ADC4_SMPR_SMPSEL10_Pos (18U) +#define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ +#define ADC4_SMPR_SMPSEL11_Pos (19U) +#define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ +#define ADC4_SMPR_SMPSEL12_Pos (20U) +#define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ +#define ADC4_SMPR_SMPSEL13_Pos (21U) +#define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ +#define ADC4_SMPR_SMPSEL14_Pos (22U) +#define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ +#define ADC4_SMPR_SMPSEL15_Pos (23U) +#define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ +#define ADC4_SMPR_SMPSEL16_Pos (24U) +#define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ +#define ADC4_SMPR_SMPSEL17_Pos (25U) +#define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ +#define ADC4_SMPR_SMPSEL18_Pos (26U) +#define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ +#define ADC4_SMPR_SMPSEL19_Pos (27U) +#define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ +#define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ +#define ADC4_SMPR_SMPSEL20_Pos (26U) +#define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ +#define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL21_Pos (26U) +#define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ +#define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL22_Pos (30U) +#define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ +#define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ +#define ADC4_SMPR_SMPSEL23_Pos (31U) +#define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ +#define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +#define ADC_HTR_AWDFILT_Pos (29U) +#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ +#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_PW register ********************/ +#define ADC4_PWRR_AUTOFF_Pos (0U) +#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ +#define ADC4_PWRR_DPD_Pos (1U) +#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ +#define ADC4_PWRR_VREFPROT_Pos (2U) +#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ +#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ +#define ADC4_PWRR_VREFSECSMP_Pos (3U) +#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ +#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ + +/* Legacy definitions */ +#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos +#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk +#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF +#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos +#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk +#define ADC4_PW_DPD ADC4_PWRR_DPD +#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos +#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk +#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT +#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos +#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk +#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_USAT_Pos (25U) +#define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_SSAT_Pos (26U) +#define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (27U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR2_USAT_Pos (25U) +#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR2_SSAT_Pos (26U) +#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (27U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR3_USAT_Pos (25U) +#define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR3_SSAT_Pos (26U) +#define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (27U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR4_USAT_Pos (25U) +#define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR4_SSAT_Pos (26U) +#define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (27U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_GCOMP register ********************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ +#define ADC_GCOMP_GCOMP_Pos (31U) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19U) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20U) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21U) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22U) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL23_Pos (23U) +#define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_I_APB_ADDR_Pos (0U) +#define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ +#define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ + +#define ADC_CALFACT_I_APB_DATA_Pos (08U) +#define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ +#define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ + +#define ADC_CALFACT_VALIDITY_Pos (16U) +#define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_LATCH_COEF_Pos (24U) +#define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CAPTURE_COEF_Pos (25U) +#define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ + +#define ADC4_CALFACT_CALFACT_Pos (0U) +#define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_CALFACT_Pos (0U) +#define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */ +#define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */ +#define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OR register ********************/ +#define ADC_OR_CHN0SEL_Pos (0U) +#define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ +#define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ + +/************************* ADC Common registers *****************************/ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_VSENSEEN_Pos (23U) +#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ +#define ADC_CCR_VDDCOREN_Pos (26U) +#define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ +#define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ + + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) + +#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ + +#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11U) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ1_Pos (12U) +#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */ +#define FLASH_ACR_PDREQ2_Pos (13U) +#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */ +#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14U) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0U) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1U) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3U) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4U) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5U) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6U) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7U) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13U) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16U) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17U) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18U) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19U) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD1_Pos (20U) +#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */ +#define FLASH_NSSR_PD2_Pos (21U) +#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */ +#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0U) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1U) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3U) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4U) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5U) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6U) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7U) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16U) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17U) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR register *****************/ +#define FLASH_NSCR_PG_Pos (0U) +#define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR_PER_Pos (1U) +#define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR_MER1_Pos (2U) +#define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */ +#define FLASH_NSCR_PNB_Pos (3U) +#define FLASH_NSCR_PNB_Msk (0x1FUL << FLASH_NSCR_PNB_Pos) /*!< 0x000001F8 */ +#define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR_BKER_Pos (11U) +#define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */ +#define FLASH_NSCR_BWR_Pos (14U) +#define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR_MER2_Pos (15U) +#define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */ +#define FLASH_NSCR_STRT_Pos (16U) +#define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR_OPTSTRT_Pos (17U) +#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR_EOPIE_Pos (24U) +#define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR_ERRIE_Pos (25U) +#define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR_OBL_LAUNCH_Pos (27U) +#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR_OPTLOCK_Pos (30U) +#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR_LOCK_Pos (31U) +#define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR register ****************/ +#define FLASH_SECCR_PG_Pos (0U) +#define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR_PER_Pos (1U) +#define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR_MER1_Pos (2U) +#define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR_PNB_Pos (3U) +#define FLASH_SECCR_PNB_Msk (0x1FUL << FLASH_SECCR_PNB_Pos) /*!< 0x000001F8 */ +#define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR_BKER_Pos (11U) +#define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */ +#define FLASH_SECCR_BWR_Pos (14U) +#define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR_MER2_Pos (15U) +#define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */ +#define FLASH_SECCR_STRT_Pos (16U) +#define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR_EOPIE_Pos (24U) +#define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR_ERRIE_Pos (25U) +#define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR_INV_Pos (29U) +#define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR_LOCK_Pos (31U) +#define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0003FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_BK_ECC_Pos (21U) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (22U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0x3FFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x0003FFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */ +#define FLASH_OPSR_BK_OP_Pos (21U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (22U) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8U) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_nRST_SHDW_Pos (14U) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ +#define FLASH_OPTR_SRAM_RST_Pos (15U) +#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SWAP_BANK_Pos (20U) +#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */ +#define FLASH_OPTR_DUALBANK_Pos (21U) +#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */ +#define FLASH_OPTR_BKPRAM_ECC_Pos (22U) +#define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTR_SRAM2_ECC_Pos (24U) +#define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25U) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26U) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_PA15_PUPEN_Pos (28U) +#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */ +#define FLASH_OPTR_IO_VDD_HSLV_Pos (29U) +#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */ +#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30U) +#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */ +#define FLASH_OPTR_TZEN_Pos (31U) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7U) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7U) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0U) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7U) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWM1R1 register **************/ +#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0U) +#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0x1FUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16U) +#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0x1FUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWM1R2 register **************/ +#define FLASH_SECWM1R2_HDP1_PEND_Pos (16U) +#define FLASH_SECWM1R2_HDP1_PEND_Msk (0x1FUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWM1R2_HDP1EN_Pos (31U) +#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0U) +#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */ +#define FLASH_WRP1AR_WRP1A_PEND_Pos (16U) +#define FLASH_WRP1AR_WRP1A_PEND_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */ +#define FLASH_WRP1AR_UNLOCK_Pos (31U) +#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0U) +#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */ +#define FLASH_WRP1BR_WRP1B_PEND_Pos (16U) +#define FLASH_WRP1BR_WRP1B_PEND_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */ +#define FLASH_WRP1BR_UNLOCK_Pos (31U) +#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */ + +/***************** Bits definition for FLASH_SECWM2R1 register **************/ +#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0U) +#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0x1FUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */ +#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16U) +#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0x1FUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */ + +/***************** Bits definition for FLASH_SECWM2R2 register **************/ +#define FLASH_SECWM2R2_HDP2_PEND_Pos (16U) +#define FLASH_SECWM2R2_HDP2_PEND_Msk (0x1FUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */ +#define FLASH_SECWM2R2_HDP2EN_Pos (31U) +#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */ + +/****************** Bits definition for FLASH_WRP2AR register ***************/ +#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0U) +#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0x1FUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */ +#define FLASH_WRP2AR_WRP2A_PEND_Pos (16U) +#define FLASH_WRP2AR_WRP2A_PEND_Msk (0x1FUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */ +#define FLASH_WRP2AR_UNLOCK_Pos (31U) +#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP2BR register ***************/ +#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0U) +#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0x1FUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */ +#define FLASH_WRP2BR_WRP2B_PEND_Pos (16U) +#define FLASH_WRP2BR_WRP2B_PEND_Msk (0x1FUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */ +#define FLASH_WRP2BR_UNLOCK_Pos (31U) +#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0U) +#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */ +#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1U) +#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */ +#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0U) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1U) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************************************************************************/ +/* */ +/* Filter Mathematical ACcelerator unit (FMAC) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1_BASE_Pos (0U) +#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U) +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ +#define FMAC_X1BUFCFG_FULL_WM_Pos (24U) +#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ +#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ + +/***************** Bit definition for FMAC_X2BUFCFG register ****************/ +#define FMAC_X2BUFCFG_X2_BASE_Pos (0U) +#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U) +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ + +/***************** Bit definition for FMAC_YBUFCFG register *****************/ +#define FMAC_YBUFCFG_Y_BASE_Pos (0U) +#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ +#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U) +#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ +#define FMAC_YBUFCFG_EMPTY_WM_Pos (24U) +#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ +#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ + +/****************** Bit definition for FMAC_PARAM register ******************/ +#define FMAC_PARAM_P_Pos (0U) +#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ +#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ +#define FMAC_PARAM_Q_Pos (8U) +#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ +#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ +#define FMAC_PARAM_R_Pos (16U) +#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ +#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ +#define FMAC_PARAM_FUNC_Pos (24U) +#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ +#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ +#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ +#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ +#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ +#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ +#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ +#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ +#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ +#define FMAC_PARAM_START_Pos (31U) +#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ +#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ + +/******************** Bit definition for FMAC_CR register *******************/ +#define FMAC_CR_RIEN_Pos (0U) +#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ +#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ +#define FMAC_CR_WIEN_Pos (1U) +#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ +#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ +#define FMAC_CR_OVFLIEN_Pos (2U) +#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ +#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ +#define FMAC_CR_UNFLIEN_Pos (3U) +#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ +#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ +#define FMAC_CR_SATIEN_Pos (4U) +#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ +#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ +#define FMAC_CR_DMAREN_Pos (8U) +#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ +#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ +#define FMAC_CR_DMAWEN_Pos (9U) +#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ +#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ +#define FMAC_CR_CLIPEN_Pos (15U) +#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ +#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ +#define FMAC_CR_RESET_Pos (16U) +#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ +#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_SR register ********************/ +#define FMAC_SR_YEMPTY_Pos (0U) +#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ +#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ +#define FMAC_SR_X1FULL_Pos (1U) +#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ +#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ +#define FMAC_SR_OVFL_Pos (8U) +#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ +#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ +#define FMAC_SR_UNFL_Pos (9U) +#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ +#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ +#define FMAC_SR_SAT_Pos (10U) +#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ +#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ + +/****************** Bit definition for FMAC_WDATA register ******************/ +#define FMAC_WDATA_WDATA_Pos (0U) +#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ + +/****************** Bit definition for FMACX_RDATA register *****************/ +#define FMAC_RDATA_RDATA_Pos (0U) +#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ + + +/******************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + +/****************** Bits definition for GPIO_HSLVR register ******************/ +#define GPIO_HSLVR_HSLV0_Pos (0U) +#define GPIO_HSLVR_HSLV0_Msk (0x1UL << GPIO_HSLVR_HSLV0_Pos) /*!< 0x00000001 */ +#define GPIO_HSLVR_HSLV0 GPIO_HSLVR_HSLV0_Msk +#define GPIO_HSLVR_HSLV1_Pos (1U) +#define GPIO_HSLVR_HSLV1_Msk (0x1UL << GPIO_HSLVR_HSLV1_Pos) /*!< 0x00000002 */ +#define GPIO_HSLVR_HSLV1 GPIO_HSLVR_HSLV1_Msk +#define GPIO_HSLVR_HSLV2_Pos (2U) +#define GPIO_HSLVR_HSLV2_Msk (0x1UL << GPIO_HSLVR_HSLV2_Pos) /*!< 0x00000004 */ +#define GPIO_HSLVR_HSLV2 GPIO_HSLVR_HSLV2_Msk +#define GPIO_HSLVR_HSLV3_Pos (3U) +#define GPIO_HSLVR_HSLV3_Msk (0x1UL << GPIO_HSLVR_HSLV3_Pos) /*!< 0x00000008 */ +#define GPIO_HSLVR_HSLV3 GPIO_HSLVR_HSLV3_Msk +#define GPIO_HSLVR_HSLV4_Pos (4U) +#define GPIO_HSLVR_HSLV4_Msk (0x1UL << GPIO_HSLVR_HSLV4_Pos) /*!< 0x00000010 */ +#define GPIO_HSLVR_HSLV4 GPIO_HSLVR_HSLV4_Msk +#define GPIO_HSLVR_HSLV5_Pos (5U) +#define GPIO_HSLVR_HSLV5_Msk (0x1UL << GPIO_HSLVR_HSLV5_Pos) /*!< 0x00000020 */ +#define GPIO_HSLVR_HSLV5 GPIO_HSLVR_HSLV5_Msk +#define GPIO_HSLVR_HSLV6_Pos (6U) +#define GPIO_HSLVR_HSLV6_Msk (0x1UL << GPIO_HSLVR_HSLV6_Pos) /*!< 0x00000040 */ +#define GPIO_HSLVR_HSLV6 GPIO_HSLVR_HSLV6_Msk +#define GPIO_HSLVR_HSLV7_Pos (7U) +#define GPIO_HSLVR_HSLV7_Msk (0x1UL << GPIO_HSLVR_HSLV7_Pos) /*!< 0x00000080 */ +#define GPIO_HSLVR_HSLV7 GPIO_HSLVR_HSLV7_Msk +#define GPIO_HSLVR_HSLV8_Pos (8U) +#define GPIO_HSLVR_HSLV8_Msk (0x1UL << GPIO_HSLVR_HSLV8_Pos) /*!< 0x00000100 */ +#define GPIO_HSLVR_HSLV8 GPIO_HSLVR_HSLV8_Msk +#define GPIO_HSLVR_HSLV9_Pos (9U) +#define GPIO_HSLVR_HSLV9_Msk (0x1UL << GPIO_HSLVR_HSLV9_Pos) /*!< 0x00000200 */ +#define GPIO_HSLVR_HSLV9 GPIO_HSLVR_HSLV9_Msk +#define GPIO_HSLVR_HSLV10_Pos (10U) +#define GPIO_HSLVR_HSLV10_Msk (0x1UL << GPIO_HSLVR_HSLV10_Pos) /*!< 0x00000400 */ +#define GPIO_HSLVR_HSLV10 GPIO_HSLVR_HSLV10_Msk +#define GPIO_HSLVR_HSLV11_Pos (11U) +#define GPIO_HSLVR_HSLV11_Msk (x1UL << GPIO_HSLVR_HSLV11_Pos) /*!< 0x00000800 */ +#define GPIO_HSLVR_HSLV11 GPIO_HSLVR_HSLV11_Msk +#define GPIO_HSLVR_HSLV12_Pos (12U) +#define GPIO_HSLVR_HSLV12_Msk (0x1UL << GPIO_HSLVR_HSLV12_Pos) /*!< 0x00001000 */ +#define GPIO_HSLVR_HSLV12 GPIO_HSLVR_HSLV12_Msk +#define GPIO_HSLVR_HSLV13_Pos (13U) +#define GPIO_HSLVR_HSLV13_Msk (0x1UL << GPIO_HSLVR_HSLV13_Pos) /*!< 0x00002000 */ +#define GPIO_HSLVR_HSLV13 GPIO_HSLVR_HSLV13_Msk +#define GPIO_HSLVR_HSLV14_Pos (14U) +#define GPIO_HSLVR_HSLV14_Msk (0x1UL << GPIO_HSLVR_HSLV14_Pos) /*!< 0x00004000 */ +#define GPIO_HSLVR_HSLV14 GPIO_HSLVR_HSLV14_Msk +#define GPIO_HSLVR_HSLV15_Pos (15U) +#define GPIO_HSLVR_HSLV15_Msk (0x1UL << GPIO_HSLVR_HSLV15_Pos) /*!< 0x00008000 */ +#define GPIO_HSLVR_HSLV15 GPIO_HSLVR_HSLV15_Msk + +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1UL << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1UL << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1UL << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1UL << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1UL << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1UL << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1UL << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1UL << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk +#define GPIO_SECCFGR_SEC8_Pos (8U) +#define GPIO_SECCFGR_SEC8_Msk (0x1UL << GPIO_SECCFGR_SEC8_Pos) /*!< 0x00000100 */ +#define GPIO_SECCFGR_SEC8 GPIO_SECCFGR_SEC8_Msk +#define GPIO_SECCFGR_SEC9_Pos (9U) +#define GPIO_SECCFGR_SEC9_Msk (0x1UL << GPIO_SECCFGR_SEC9_Pos) /*!< 0x00000200 */ +#define GPIO_SECCFGR_SEC9 GPIO_SECCFGR_SEC9_Msk +#define GPIO_SECCFGR_SEC10_Pos (10U) +#define GPIO_SECCFGR_SEC10_Msk (0x1UL << GPIO_SECCFGR_SEC10_Pos) /*!< 0x00000400 */ +#define GPIO_SECCFGR_SEC10 GPIO_SECCFGR_SEC10_Msk +#define GPIO_SECCFGR_SEC11_Pos (11U) +#define GPIO_SECCFGR_SEC11_Msk (x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */ +#define GPIO_SECCFGR_SEC11 GPIO_SECCFGR_SEC11_Msk +#define GPIO_SECCFGR_SEC12_Pos (12U) +#define GPIO_SECCFGR_SEC12_Msk (0x1UL << GPIO_SECCFGR_SEC12_Pos) /*!< 0x00001000 */ +#define GPIO_SECCFGR_SEC12 GPIO_SECCFGR_SEC12_Msk +#define GPIO_SECCFGR_SEC13_Pos (13U) +#define GPIO_SECCFGR_SEC13_Msk (0x1UL << GPIO_SECCFGR_SEC13_Pos) /*!< 0x00002000 */ +#define GPIO_SECCFGR_SEC13 GPIO_SECCFGR_SEC13_Msk +#define GPIO_SECCFGR_SEC14_Pos (14U) +#define GPIO_SECCFGR_SEC14_Msk (0x1UL << GPIO_SECCFGR_SEC14_Pos) /*!< 0x00004000 */ +#define GPIO_SECCFGR_SEC14 GPIO_SECCFGR_SEC14_Msk +#define GPIO_SECCFGR_SEC15_Pos (15U) +#define GPIO_SECCFGR_SEC15_Msk (0x1UL << GPIO_SECCFGR_SEC15_Pos) /*!< 0x00008000 */ +#define GPIO_SECCFGR_SEC15 GPIO_SECCFGR_SEC15_Msk + +/******************************************************************************/ +/* */ +/* Low Power General Purpose IOs (LPGPIO) */ +/* */ +/******************************************************************************/ +/****************** Bits definition for LPGPIO_MODER register *****************/ +#define LPGPIO_MODER_MOD0_Pos (0U) +#define LPGPIO_MODER_MOD0_Msk (0x1UL << LPGPIO_MODER_MOD0_Pos) /*!< 0x00000001 */ +#define LPGPIO_MODER_MOD0 LPGPIO_MODER_MOD0_Msk +#define LPGPIO_MODER_MOD1_Pos (1U) +#define LPGPIO_MODER_MOD1_Msk (0x1UL << LPGPIO_MODER_MOD1_Pos) /*!< 0x00000002 */ +#define LPGPIO_MODER_MOD1 LPGPIO_MODER_MOD1_Msk +#define LPGPIO_MODER_MOD2_Pos (2U) +#define LPGPIO_MODER_MOD2_Msk (0x1UL << LPGPIO_MODER_MOD2_Pos) /*!< 0x00000004 */ +#define LPGPIO_MODER_MOD2 LPGPIO_MODER_MOD2_Msk +#define LPGPIO_MODER_MOD3_Pos (3U) +#define LPGPIO_MODER_MOD3_Msk (0x1UL << LPGPIO_MODER_MOD3_Pos) /*!< 0x00000008 */ +#define LPGPIO_MODER_MOD3 LPGPIO_MODER_MOD3_Msk +#define LPGPIO_MODER_MOD4_Pos (4U) +#define LPGPIO_MODER_MOD4_Msk (0x1UL << LPGPIO_MODER_MOD4_Pos) /*!< 0x00000010 */ +#define LPGPIO_MODER_MOD4 LPGPIO_MODER_MOD4_Msk +#define LPGPIO_MODER_MOD5_Pos (5U) +#define LPGPIO_MODER_MOD5_Msk (0x1UL << LPGPIO_MODER_MOD5_Pos) /*!< 0x00000020 */ +#define LPGPIO_MODER_MOD5 LPGPIO_MODER_MOD5_Msk +#define LPGPIO_MODER_MOD6_Pos (6U) +#define LPGPIO_MODER_MOD6_Msk (0x1UL << LPGPIO_MODER_MOD6_Pos) /*!< 0x00000040 */ +#define LPGPIO_MODER_MOD6 LPGPIO_MODER_MOD6_Msk +#define LPGPIO_MODER_MOD7_Pos (7U) +#define LPGPIO_MODER_MOD7_Msk (0x1UL << LPGPIO_MODER_MOD7_Pos) /*!< 0x00000080 */ +#define LPGPIO_MODER_MOD7 LPGPIO_MODER_MOD7_Msk +#define LPGPIO_MODER_MOD8_Pos (8U) +#define LPGPIO_MODER_MOD8_Msk (0x1UL << LPGPIO_MODER_MOD8_Pos) /*!< 0x00000100 */ +#define LPGPIO_MODER_MOD8 LPGPIO_MODER_MOD8_Msk +#define LPGPIO_MODER_MOD9_Pos (9U) +#define LPGPIO_MODER_MOD9_Msk (0x1UL << LPGPIO_MODER_MOD9_Pos) /*!< 0x00000200 */ +#define LPGPIO_MODER_MOD9 LPGPIO_MODER_MOD9_Msk +#define LPGPIO_MODER_MOD10_Pos (10U) +#define LPGPIO_MODER_MOD10_Msk (0x1UL << LPGPIO_MODER_MOD10_Pos) /*!< 0x00000400 */ +#define LPGPIO_MODER_MOD10 LPGPIO_MODER_MOD10_Msk +#define LPGPIO_MODER_MOD11_Pos (11U) +#define LPGPIO_MODER_MOD11_Msk (0x1UL << LPGPIO_MODER_MOD11_Pos) /*!< 0x00000800 */ +#define LPGPIO_MODER_MOD11 LPGPIO_MODER_MOD11_Msk +#define LPGPIO_MODER_MOD12_Pos (12U) +#define LPGPIO_MODER_MOD12_Msk (0x1UL << LPGPIO_MODER_MOD12_Pos) /*!< 0x00001000 */ +#define LPGPIO_MODER_MOD12 LPGPIO_MODER_MOD12_Msk +#define LPGPIO_MODER_MOD13_Pos (13U) +#define LPGPIO_MODER_MOD13_Msk (0x1UL << LPGPIO_MODER_MOD13_Pos) /*!< 0x00002000 */ +#define LPGPIO_MODER_MOD13 LPGPIO_MODER_MOD13_Msk +#define LPGPIO_MODER_MOD14_Pos (14U) +#define LPGPIO_MODER_MOD14_Msk (0x1UL << LPGPIO_MODER_MOD14_Pos) /*!< 0x00004000 */ +#define LPGPIO_MODER_MOD14 LPGPIO_MODER_MOD14_Msk +#define LPGPIO_MODER_MOD15_Pos (15U) +#define LPGPIO_MODER_MOD15_Msk (0x1UL << LPGPIO_MODER_MOD15_Pos) /*!< 0x00008000 */ +#define LPGPIO_MODER_MOD15 LPGPIO_MODER_MOD15_Msk + +/****************** Bits definition for LPGPIO_IDR register *******************/ +#define LPGPIO_IDR_ID0_Pos (0U) +#define LPGPIO_IDR_ID0_Msk (0x1UL << LPGPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define LPGPIO_IDR_ID0 LPGPIO_IDR_ID0_Msk +#define LPGPIO_IDR_ID1_Pos (1U) +#define LPGPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define LPGPIO_IDR_ID1 LPGPIO_IDR_ID1_Msk +#define LPGPIO_IDR_ID2_Pos (2U) +#define LPGPIO_IDR_ID2_Msk (0x1UL << LPGPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define LPGPIO_IDR_ID2 LPGPIO_IDR_ID2_Msk +#define LPGPIO_IDR_ID3_Pos (3U) +#define LPGPIO_IDR_ID3_Msk (0x1UL << LPGPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define LPGPIO_IDR_ID3 LPGPIO_IDR_ID3_Msk +#define LPGPIO_IDR_ID4_Pos (4U) +#define LPGPIO_IDR_ID4_Msk (0x1UL << LPGPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define LPGPIO_IDR_ID4 LPGPIO_IDR_ID4_Msk +#define LPGPIO_IDR_ID5_Pos (5U) +#define LPGPIO_IDR_ID5_Msk (0x1UL << LPGPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define LPGPIO_IDR_ID5 LPGPIO_IDR_ID5_Msk +#define LPGPIO_IDR_ID6_Pos (6U) +#define LPGPIO_IDR_ID6_Msk (0x1UL << LPGPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define LPGPIO_IDR_ID6 LPGPIO_IDR_ID6_Msk +#define LPGPIO_IDR_ID7_Pos (7U) +#define LPGPIO_IDR_ID7_Msk (0x1UL << LPGPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define LPGPIO_IDR_ID7 LPGPIO_IDR_ID7_Msk +#define LPGPIO_IDR_ID8_Pos (8U) +#define LPGPIO_IDR_ID8_Msk (0x1UL << LPGPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define LPGPIO_IDR_ID8 LPGPIO_IDR_ID8_Msk +#define LPGPIO_IDR_ID9_Pos (9U) +#define LPGPIO_IDR_ID9_Msk (0x1UL << LPGPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define LPGPIO_IDR_ID9 LPGPIO_IDR_ID9_Msk +#define LPGPIO_IDR_ID10_Pos (10U) +#define LPGPIO_IDR_ID10_Msk (0x1UL << LPGPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define LPGPIO_IDR_ID10 LPGPIO_IDR_ID10_Msk +#define LPGPIO_IDR_ID11_Pos (11U) +#define LPGPIO_IDR_ID11_Msk (0x1UL << LPGPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define LPGPIO_IDR_ID11 LPGPIO_IDR_ID11_Msk +#define LPGPIO_IDR_ID12_Pos (12U) +#define LPGPIO_IDR_ID12_Msk (0x1UL << LPGPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define LPGPIO_IDR_ID12 LPGPIO_IDR_ID12_Msk +#define LPGPIO_IDR_ID13_Pos (13U) +#define LPGPIO_IDR_ID13_Msk (0x1UL << LPGPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define LPGPIO_IDR_ID13 LPGPIO_IDR_ID13_Msk +#define LPGPIO_IDR_ID14_Pos (14U) +#define LPGPIO_IDR_ID14_Msk (0x1UL << LPGPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define LPGPIO_IDR_ID14 LPGPIO_IDR_ID14_Msk +#define LPGPIO_IDR_ID15_Pos (15U) +#define LPGPIO_IDR_ID15_Msk (0x1UL << LPGPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define LPGPIO_IDR_ID15 LPGPIO_IDR_ID15_Msk + +/****************** Bits definition for LPGPIO_ODR register *******************/ +#define LPGPIO_ODR_OD0_Pos (0U) +#define LPGPIO_ODR_OD0_Msk (0x1UL << LPGPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define LPGPIO_ODR_OD0 LPGPIO_ODR_OD0_Msk +#define LPGPIO_ODR_OD1_Pos (1U) +#define LPGPIO_ODR_OD1_Msk (0x1UL << LPGPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define LPGPIO_ODR_OD1 LPGPIO_ODR_OD1_Msk +#define LPGPIO_ODR_OD2_Pos (2U) +#define LPGPIO_ODR_OD2_Msk (0x1UL << LPGPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define LPGPIO_ODR_OD2 LPGPIO_ODR_OD2_Msk +#define LPGPIO_ODR_OD3_Pos (3U) +#define LPGPIO_ODR_OD3_Msk (0x1UL << LPGPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define LPGPIO_ODR_OD3 LPGPIO_ODR_OD3_Msk +#define LPGPIO_ODR_OD4_Pos (4U) +#define LPGPIO_ODR_OD4_Msk (0x1UL << LPGPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define LPGPIO_ODR_OD4 LPGPIO_ODR_OD4_Msk +#define LPGPIO_ODR_OD5_Pos (5U) +#define LPGPIO_ODR_OD5_Msk (0x1UL << LPGPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define LPGPIO_ODR_OD5 LPGPIO_ODR_OD5_Msk +#define LPGPIO_ODR_OD6_Pos (6U) +#define LPGPIO_ODR_OD6_Msk (0x1UL << LPGPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define LPGPIO_ODR_OD6 LPGPIO_ODR_OD6_Msk +#define LPGPIO_ODR_OD7_Pos (7U) +#define LPGPIO_ODR_OD7_Msk (0x1UL << LPGPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define LPGPIO_ODR_OD7 LPGPIO_ODR_OD7_Msk +#define LPGPIO_ODR_OD8_Pos (8U) +#define LPGPIO_ODR_OD8_Msk (0x1UL << LPGPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define LPGPIO_ODR_OD8 LPGPIO_ODR_OD8_Msk +#define LPGPIO_ODR_OD9_Pos (9U) +#define LPGPIO_ODR_OD9_Msk (0x1UL << LPGPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define LPGPIO_ODR_OD9 LPGPIO_ODR_OD9_Msk +#define LPGPIO_ODR_OD10_Pos (10U) +#define LPGPIO_ODR_OD10_Msk (0x1UL << LPGPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define LPGPIO_ODR_OD10 LPGPIO_ODR_OD10_Msk +#define LPGPIO_ODR_OD11_Pos (11U) +#define LPGPIO_ODR_OD11_Msk (0x1UL << LPGPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define LPGPIO_ODR_OD11 LPGPIO_ODR_OD11_Msk +#define LPGPIO_ODR_OD12_Pos (12U) +#define LPGPIO_ODR_OD12_Msk (0x1UL << LPGPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define LPGPIO_ODR_OD12 LPGPIO_ODR_OD12_Msk +#define LPGPIO_ODR_OD13_Pos (13U) +#define LPGPIO_ODR_OD13_Msk (0x1UL << LPGPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define LPGPIO_ODR_OD13 LPGPIO_ODR_OD13_Msk +#define LPGPIO_ODR_OD14_Pos (14U) +#define LPGPIO_ODR_OD14_Msk (0x1UL << LPGPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define LPGPIO_ODR_OD14 LPGPIO_ODR_OD14_Msk +#define LPGPIO_ODR_OD15_Pos (15U) +#define LPGPIO_ODR_OD15_Msk (0x1UL << LPGPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define LPGPIO_ODR_OD15 LPGPIO_ODR_OD15_Msk + +/****************** Bits definition for LPGPIO_BSRR register ******************/ +#define LPGPIO_BSRR_BS0_Pos (0U) +#define LPGPIO_BSRR_BS0_Msk (0x1UL << LPGPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define LPGPIO_BSRR_BS0 LPGPIO_BSRR_BS0_Msk +#define LPGPIO_BSRR_BS1_Pos (1U) +#define LPGPIO_BSRR_BS1_Msk (0x1UL << LPGPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define LPGPIO_BSRR_BS1 LPGPIO_BSRR_BS1_Msk +#define LPGPIO_BSRR_BS2_Pos (2U) +#define LPGPIO_BSRR_BS2_Msk (0x1UL << LPGPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define LPGPIO_BSRR_BS2 LPGPIO_BSRR_BS2_Msk +#define LPGPIO_BSRR_BS3_Pos (3U) +#define LPGPIO_BSRR_BS3_Msk (0x1UL << LPGPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define LPGPIO_BSRR_BS3 LPGPIO_BSRR_BS3_Msk +#define LPGPIO_BSRR_BS4_Pos (4U) +#define LPGPIO_BSRR_BS4_Msk (0x1UL << LPGPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define LPGPIO_BSRR_BS4 LPGPIO_BSRR_BS4_Msk +#define LPGPIO_BSRR_BS5_Pos (5U) +#define LPGPIO_BSRR_BS5_Msk (0x1UL << LPGPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define LPGPIO_BSRR_BS5 LPGPIO_BSRR_BS5_Msk +#define LPGPIO_BSRR_BS6_Pos (6U) +#define LPGPIO_BSRR_BS6_Msk (0x1UL << LPGPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define LPGPIO_BSRR_BS6 LPGPIO_BSRR_BS6_Msk +#define LPGPIO_BSRR_BS7_Pos (7U) +#define LPGPIO_BSRR_BS7_Msk (0x1UL << LPGPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define LPGPIO_BSRR_BS7 LPGPIO_BSRR_BS7_Msk +#define LPGPIO_BSRR_BS8_Pos (8U) +#define LPGPIO_BSRR_BS8_Msk (0x1UL << LPGPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define LPGPIO_BSRR_BS8 LPGPIO_BSRR_BS8_Msk +#define LPGPIO_BSRR_BS9_Pos (9U) +#define LPGPIO_BSRR_BS9_Msk (0x1UL << LPGPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define LPGPIO_BSRR_BS9 LPGPIO_BSRR_BS9_Msk +#define LPGPIO_BSRR_BS10_Pos (10U) +#define LPGPIO_BSRR_BS10_Msk (0x1UL << LPGPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define LPGPIO_BSRR_BS10 LPGPIO_BSRR_BS10_Msk +#define LPGPIO_BSRR_BS11_Pos (11U) +#define LPGPIO_BSRR_BS11_Msk (0x1UL << LPGPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define LPGPIO_BSRR_BS11 LPGPIO_BSRR_BS11_Msk +#define LPGPIO_BSRR_BS12_Pos (12U) +#define LPGPIO_BSRR_BS12_Msk (0x1UL << LPGPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define LPGPIO_BSRR_BS12 LPGPIO_BSRR_BS12_Msk +#define LPGPIO_BSRR_BS13_Pos (13U) +#define LPGPIO_BSRR_BS13_Msk (0x1UL << LPGPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define LPGPIO_BSRR_BS13 LPGPIO_BSRR_BS13_Msk +#define LPGPIO_BSRR_BS14_Pos (14U) +#define LPGPIO_BSRR_BS14_Msk (0x1UL << LPGPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define LPGPIO_BSRR_BS14 LPGPIO_BSRR_BS14_Msk +#define LPGPIO_BSRR_BS15_Pos (15U) +#define LPGPIO_BSRR_BS15_Msk (0x1UL << LPGPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define LPGPIO_BSRR_BS15 LPGPIO_BSRR_BS15_Msk +#define LPGPIO_BSRR_BR0_Pos (16U) +#define LPGPIO_BSRR_BR0_Msk (0x1UL << LPGPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define LPGPIO_BSRR_BR0 LPGPIO_BSRR_BR0_Msk +#define LPGPIO_BSRR_BR1_Pos (17U) +#define LPGPIO_BSRR_BR1_Msk (0x1UL << LPGPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define LPGPIO_BSRR_BR1 LPGPIO_BSRR_BR1_Msk +#define LPGPIO_BSRR_BR2_Pos (18U) +#define LPGPIO_BSRR_BR2_Msk (0x1UL << LPGPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define LPGPIO_BSRR_BR2 LPGPIO_BSRR_BR2_Msk +#define LPGPIO_BSRR_BR3_Pos (19U) +#define LPGPIO_BSRR_BR3_Msk (0x1UL << LPGPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define LPGPIO_BSRR_BR3 LPGPIO_BSRR_BR3_Msk +#define LPGPIO_BSRR_BR4_Pos (20U) +#define LPGPIO_BSRR_BR4_Msk (0x1UL << LPGPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define LPGPIO_BSRR_BR4 LPGPIO_BSRR_BR4_Msk +#define LPGPIO_BSRR_BR5_Pos (21U) +#define LPGPIO_BSRR_BR5_Msk (0x1UL << LPGPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define LPGPIO_BSRR_BR5 LPGPIO_BSRR_BR5_Msk +#define LPGPIO_BSRR_BR6_Pos (22U) +#define LPGPIO_BSRR_BR6_Msk (0x1UL << LPGPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define LPGPIO_BSRR_BR6 LPGPIO_BSRR_BR6_Msk +#define LPGPIO_BSRR_BR7_Pos (23U) +#define LPGPIO_BSRR_BR7_Msk (0x1UL << LPGPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define LPGPIO_BSRR_BR7 LPGPIO_BSRR_BR7_Msk +#define LPGPIO_BSRR_BR8_Pos (24U) +#define LPGPIO_BSRR_BR8_Msk (0x1UL << LPGPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define LPGPIO_BSRR_BR8 LPGPIO_BSRR_BR8_Msk +#define LPGPIO_BSRR_BR9_Pos (25U) +#define LPGPIO_BSRR_BR9_Msk (0x1UL << LPGPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define LPGPIO_BSRR_BR9 LPGPIO_BSRR_BR9_Msk +#define LPGPIO_BSRR_BR10_Pos (26U) +#define LPGPIO_BSRR_BR10_Msk (0x1UL << LPGPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define LPGPIO_BSRR_BR10 LPGPIO_BSRR_BR10_Msk +#define LPGPIO_BSRR_BR11_Pos (27U) +#define LPGPIO_BSRR_BR11_Msk (0x1UL << LPGPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define LPGPIO_BSRR_BR11 LPGPIO_BSRR_BR11_Msk +#define LPGPIO_BSRR_BR12_Pos (28U) +#define LPGPIO_BSRR_BR12_Msk (0x1UL << LPGPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define LPGPIO_BSRR_BR12 LPGPIO_BSRR_BR12_Msk +#define LPGPIO_BSRR_BR13_Pos (29U) +#define LPGPIO_BSRR_BR13_Msk (0x1UL << LPGPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define LPGPIO_BSRR_BR13 LPGPIO_BSRR_BR13_Msk +#define LPGPIO_BSRR_BR14_Pos (30U) +#define LPGPIO_BSRR_BR14_Msk (0x1UL << LPGPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define LPGPIO_BSRR_BR14 LPGPIO_BSRR_BR14_Msk +#define LPGPIO_BSRR_BR15_Pos (31U) +#define LPGPIO_BSRR_BR15_Msk (0x1UL << LPGPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define LPGPIO_BSRR_BR15 LPGPIO_BSRR_BR15_Msk + +/****************** Bits definition for LPGPIO_BRR register ******************/ +#define LPGPIO_BRR_BR0_Pos (0U) +#define LPGPIO_BRR_BR0_Msk (0x1UL << LPGPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define LPGPIO_BRR_BR0 LPGPIO_BRR_BR0_Msk +#define LPGPIO_BRR_BR1_Pos (1U) +#define LPGPIO_BRR_BR1_Msk (0x1UL << LPGPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define LPGPIO_BRR_BR1 LPGPIO_BRR_BR1_Msk +#define LPGPIO_BRR_BR2_Pos (2U) +#define LPGPIO_BRR_BR2_Msk (0x1UL << LPGPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define LPGPIO_BRR_BR2 LPGPIO_BRR_BR2_Msk +#define LPGPIO_BRR_BR3_Pos (3U) +#define LPGPIO_BRR_BR3_Msk (0x1UL << LPGPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define LPGPIO_BRR_BR3 LPGPIO_BRR_BR3_Msk +#define LPGPIO_BRR_BR4_Pos (4U) +#define LPGPIO_BRR_BR4_Msk (0x1UL << LPGPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define LPGPIO_BRR_BR4 LPGPIO_BRR_BR4_Msk +#define LPGPIO_BRR_BR5_Pos (5U) +#define LPGPIO_BRR_BR5_Msk (0x1UL << LPGPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define LPGPIO_BRR_BR5 LPGPIO_BRR_BR5_Msk +#define LPGPIO_BRR_BR6_Pos (6U) +#define LPGPIO_BRR_BR6_Msk (0x1UL << LPGPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define LPGPIO_BRR_BR6 LPGPIO_BRR_BR6_Msk +#define LPGPIO_BRR_BR7_Pos (7U) +#define LPGPIO_BRR_BR7_Msk (0x1UL << LPGPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define LPGPIO_BRR_BR7 LPGPIO_BRR_BR7_Msk +#define LPGPIO_BRR_BR8_Pos (8U) +#define LPGPIO_BRR_BR8_Msk (0x1UL << LPGPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define LPGPIO_BRR_BR8 LPGPIO_BRR_BR8_Msk +#define LPGPIO_BRR_BR9_Pos (9U) +#define LPGPIO_BRR_BR9_Msk (0x1UL << LPGPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define LPGPIO_BRR_BR9 LPGPIO_BRR_BR9_Msk +#define LPGPIO_BRR_BR10_Pos (10U) +#define LPGPIO_BRR_BR10_Msk (0x1UL << LPGPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define LPGPIO_BRR_BR10 LPGPIO_BRR_BR10_Msk +#define LPGPIO_BRR_BR11_Pos (11U) +#define LPGPIO_BRR_BR11_Msk (0x1UL << LPGPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define LPGPIO_BRR_BR11 LPGPIO_BRR_BR11_Msk +#define LPGPIO_BRR_BR12_Pos (12U) +#define LPGPIO_BRR_BR12_Msk (0x1UL << LPGPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define LPGPIO_BRR_BR12 LPGPIO_BRR_BR12_Msk +#define LPGPIO_BRR_BR13_Pos (13U) +#define LPGPIO_BRR_BR13_Msk (0x1UL << LPGPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define LPGPIO_BRR_BR13 LPGPIO_BRR_BR13_Msk +#define LPGPIO_BRR_BR14_Pos (14U) +#define LPGPIO_BRR_BR14_Msk (0x1UL << LPGPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define LPGPIO_BRR_BR14 LPGPIO_BRR_BR14_Msk +#define LPGPIO_BRR_BR15_Pos (15U) +#define LPGPIO_BRR_BR15_Msk (0x1UL << LPGPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define LPGPIO_BRR_BR15 LPGPIO_BRR_BR15_Msk + +/******************************************************************************/ +/* */ +/* ICACHE */ +/* */ +/******************************************************************************/ +/****************** Bit definition for ICACHE_CR register *******************/ +#define ICACHE_CR_EN_Pos (0U) +#define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */ +#define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< Enable */ +#define ICACHE_CR_CACHEINV_Pos (1U) +#define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ +#define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< Cache invalidation */ +#define ICACHE_CR_WAYSEL_Pos (2U) +#define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */ +#define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< Ways selection */ +#define ICACHE_CR_HITMEN_Pos (16U) +#define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */ +#define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< Hit monitor enable */ +#define ICACHE_CR_MISSMEN_Pos (17U) +#define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */ +#define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< Miss monitor enable */ +#define ICACHE_CR_HITMRST_Pos (18U) +#define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */ +#define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< Hit monitor reset */ +#define ICACHE_CR_MISSMRST_Pos (19U) +#define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */ +#define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< Miss monitor reset */ + +/****************** Bit definition for ICACHE_SR register *******************/ +#define ICACHE_SR_BUSYF_Pos (0U) +#define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< Busy flag */ +#define ICACHE_SR_BSYENDF_Pos (1U) +#define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< Busy end flag */ +#define ICACHE_SR_ERRF_Pos (2U) +#define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< Cache error flag */ + +/****************** Bit definition for ICACHE_IER register ******************/ +#define ICACHE_IER_BSYENDIE_Pos (1U) +#define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */ +#define ICACHE_IER_ERRIE_Pos (2U) +#define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< Cache error interrupt enable */ + +/****************** Bit definition for ICACHE_FCR register ******************/ +#define ICACHE_FCR_CBSYENDF_Pos (1U) +#define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< Busy end flag clear */ +#define ICACHE_FCR_CERRF_Pos (2U) +#define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk /*!< Cache error flag clear */ + +/****************** Bit definition for ICACHE_HMONR register ****************/ +#define ICACHE_HMONR_HITMON_Pos (0U) +#define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */ +#define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< Cache hit monitor register */ + +/****************** Bit definition for ICACHE_MMONR register ****************/ +#define ICACHE_MMONR_MISSMON_Pos (0U) +#define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */ +#define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< Cache miss monitor register */ + +/****************** Bit definition for ICACHE_CRRx register *****************/ +#define ICACHE_CRRx_BASEADDR_Pos (0U) +#define ICACHE_CRRx_BASEADDR_Msk (0xFFUL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x000000FF */ +#define ICACHE_CRRx_BASEADDR ICACHE_CRRx_BASEADDR_Msk /*!< Base address of region X to remap */ +#define ICACHE_CRRx_RSIZE_Pos (9U) +#define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00 */ +#define ICACHE_CRRx_RSIZE ICACHE_CRRx_RSIZE_Msk /*!< Region X size */ +#define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200 */ +#define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400 */ +#define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800 */ +#define ICACHE_CRRx_REN_Pos (15U) +#define ICACHE_CRRx_REN_Msk (0x1UL << ICACHE_CRRx_REN_Pos) /*!< 0x00008000 */ +#define ICACHE_CRRx_REN ICACHE_CRRx_REN_Msk /*!< Region X enable */ +#define ICACHE_CRRx_REMAPADDR_Pos (16U) +#define ICACHE_CRRx_REMAPADDR_Msk (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x07FF0000 */ +#define ICACHE_CRRx_REMAPADDR ICACHE_CRRx_REMAPADDR_Msk /*!< Remap address of Region X to be remapped */ +#define ICACHE_CRRx_MSTSEL_Pos (28U) +#define ICACHE_CRRx_MSTSEL_Msk (0x1UL << ICACHE_CRRx_MSTSEL_Pos) /*!< 0x10000000 */ +#define ICACHE_CRRx_MSTSEL ICACHE_CRRx_MSTSEL_Msk /*!< Region X AHB cache master selection */ +#define ICACHE_CRRx_HBURST_Pos (31U) +#define ICACHE_CRRx_HBURST_Msk (0x1UL << ICACHE_CRRx_HBURST_Pos) /*!< 0x80000000 */ +#define ICACHE_CRRx_HBURST ICACHE_CRRx_HBURST_Msk /*!< Region X output burst type */ + +/******************************************************************************/ +/* */ +/* DCACHE */ +/* */ +/******************************************************************************/ +/****************** Bit definition for DCACHE_CR register *******************/ +#define DCACHE_CR_EN_Pos (0U) +#define DCACHE_CR_EN_Msk (0x1UL << DCACHE_CR_EN_Pos) /*!< 0x00000001 */ +#define DCACHE_CR_EN DCACHE_CR_EN_Msk /*!< Enable */ +#define DCACHE_CR_CACHEINV_Pos (1U) +#define DCACHE_CR_CACHEINV_Msk (0x1UL << DCACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ +#define DCACHE_CR_CACHEINV DCACHE_CR_CACHEINV_Msk /*!< Cache invalidation */ +#define DCACHE_CR_CACHECMD_Pos (8U) +#define DCACHE_CR_CACHECMD_Msk (0x7UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000700 */ +#define DCACHE_CR_CACHECMD DCACHE_CR_CACHECMD_Msk /*!< Cache command */ +#define DCACHE_CR_CACHECMD_0 (0x1UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000100 */ +#define DCACHE_CR_CACHECMD_1 (0x2UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000200 */ +#define DCACHE_CR_CACHECMD_2 (0x4UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000400 */ +#define DCACHE_CR_STARTCMD_Pos (11U) +#define DCACHE_CR_STARTCMD_Msk (0x1UL << DCACHE_CR_STARTCMD_Pos) /*!< 0x00000800 */ +#define DCACHE_CR_STARTCMD DCACHE_CR_STARTCMD_Msk /*!< Start command */ +#define DCACHE_CR_RHITMEN_Pos (16U) +#define DCACHE_CR_RHITMEN_Msk (0x1UL << DCACHE_CR_RHITMEN_Pos) /*!< 0x00010000 */ +#define DCACHE_CR_RHITMEN DCACHE_CR_RHITMEN_Msk /*!< Read Hit monitor enable */ +#define DCACHE_CR_RMISSMEN_Pos (17U) +#define DCACHE_CR_RMISSMEN_Msk (0x1UL << DCACHE_CR_RMISSMEN_Pos) /*!< 0x00020000 */ +#define DCACHE_CR_RMISSMEN DCACHE_CR_RMISSMEN_Msk /*!< Read Miss monitor enable */ +#define DCACHE_CR_RHITMRST_Pos (18U) +#define DCACHE_CR_RHITMRST_Msk (0x1UL << DCACHE_CR_RHITMRST_Pos) /*!< 0x00040000 */ +#define DCACHE_CR_RHITMRST DCACHE_CR_RHITMRST_Msk /*!< Read Hit monitor reset */ +#define DCACHE_CR_RMISSMRST_Pos (19U) +#define DCACHE_CR_RMISSMRST_Msk (0x1UL << DCACHE_CR_RMISSMRST_Pos) /*!< 0x00080000 */ +#define DCACHE_CR_RMISSMRST DCACHE_CR_RMISSMRST_Msk /*!< Read Miss monitor reset */ +#define DCACHE_CR_WHITMEN_Pos (20U) +#define DCACHE_CR_WHITMEN_Msk (0x1UL << DCACHE_CR_WHITMEN_Pos) /*!< 0x00100000 */ +#define DCACHE_CR_WHITMEN DCACHE_CR_WHITMEN_Msk /*!< Write Hit monitor enable */ +#define DCACHE_CR_WMISSMEN_Pos (21U) +#define DCACHE_CR_WMISSMEN_Msk (0x1UL << DCACHE_CR_WMISSMEN_Pos) /*!< 0x00200000 */ +#define DCACHE_CR_WMISSMEN DCACHE_CR_WMISSMEN_Msk /*!< Write Miss monitor enable */ +#define DCACHE_CR_WHITMRST_Pos (22U) +#define DCACHE_CR_WHITMRST_Msk (0x1UL << DCACHE_CR_WHITMRST_Pos) /*!< 0x00400000 */ +#define DCACHE_CR_WHITMRST DCACHE_CR_WHITMRST_Msk /*!< Write Hit monitor reset */ +#define DCACHE_CR_WMISSMRST_Pos (23U) +#define DCACHE_CR_WMISSMRST_Msk (0x1UL << DCACHE_CR_WMISSMRST_Pos) /*!< 0x00800000 */ +#define DCACHE_CR_WMISSMRST DCACHE_CR_WMISSMRST_Msk /*!< Write Miss monitor reset */ +#define DCACHE_CR_HBURST_Pos (31U) +#define DCACHE_CR_HBURST_Msk (0x1UL << DCACHE_CR_HBURST_Pos) /*!< 0x80000000 */ +#define DCACHE_CR_HBURST DCACHE_CR_HBURST_Msk /*!< Read burst type */ + +/****************** Bit definition for DCACHE_SR register *******************/ +#define DCACHE_SR_BUSYF_Pos (0U) +#define DCACHE_SR_BUSYF_Msk (0x1UL << DCACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define DCACHE_SR_BUSYF DCACHE_SR_BUSYF_Msk /*!< Busy flag */ +#define DCACHE_SR_BSYENDF_Pos (1U) +#define DCACHE_SR_BSYENDF_Msk (0x1UL << DCACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define DCACHE_SR_BSYENDF DCACHE_SR_BSYENDF_Msk /*!< Busy end flag */ +#define DCACHE_SR_ERRF_Pos (2U) +#define DCACHE_SR_ERRF_Msk (0x1UL << DCACHE_SR_ERRF_Pos) /*!< 0x00000004 */ +#define DCACHE_SR_ERRF DCACHE_SR_ERRF_Msk /*!< Cache error flag */ +#define DCACHE_SR_BUSYCMDF_Pos (3U) +#define DCACHE_SR_BUSYCMDF_Msk (0x1UL << DCACHE_SR_BUSYCMDF_Pos) /*!< 0x00000008 */ +#define DCACHE_SR_BUSYCMDF DCACHE_SR_BUSYCMDF_Msk /*!< Busy command flag */ +#define DCACHE_SR_CMDENDF_Pos (4U) +#define DCACHE_SR_CMDENDF_Msk (0x1UL << DCACHE_SR_CMDENDF_Pos) /*!< 0x00000010 */ +#define DCACHE_SR_CMDENDF DCACHE_SR_CMDENDF_Msk /*!< Command end flag */ + +/****************** Bit definition for DCACHE_IER register ******************/ +#define DCACHE_IER_BSYENDIE_Pos (1U) +#define DCACHE_IER_BSYENDIE_Msk (0x1UL << DCACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define DCACHE_IER_BSYENDIE DCACHE_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */ +#define DCACHE_IER_ERRIE_Pos (2U) +#define DCACHE_IER_ERRIE_Msk (0x1UL << DCACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define DCACHE_IER_ERRIE DCACHE_IER_ERRIE_Msk /*!< Cache error interrupt enable */ +#define DCACHE_IER_CMDENDIE_Pos (4U) +#define DCACHE_IER_CMDENDIE_Msk (0x1UL << DCACHE_IER_CMDENDIE_Pos) /*!< 0x00000010 */ +#define DCACHE_IER_CMDENDIE DCACHE_IER_CMDENDIE_Msk /*!< Command end interrupt enable */ + +/****************** Bit definition for DCACHE_FCR register ******************/ +#define DCACHE_FCR_CBSYENDF_Pos (1U) +#define DCACHE_FCR_CBSYENDF_Msk (0x1UL << DCACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define DCACHE_FCR_CBSYENDF DCACHE_FCR_CBSYENDF_Msk /*!< Busy end flag clear */ +#define DCACHE_FCR_CERRF_Pos (2U) +#define DCACHE_FCR_CERRF_Msk (0x1UL << DCACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define DCACHE_FCR_CERRF DCACHE_FCR_CERRF_Msk /*!< Cache error flag clear */ +#define DCACHE_FCR_CCMDENDF_Pos (4U) +#define DCACHE_FCR_CCMDENDF_Msk (0x1UL << DCACHE_FCR_CCMDENDF_Pos) /*!< 0x00000010 */ +#define DCACHE_FCR_CCMDENDF DCACHE_FCR_CCMDENDF_Msk /*!< Command end flag clear */ + +/****************** Bit definition for DCACHE_RHMONR register ****************/ +#define DCACHE_RHMONR_RHITMON_Pos (0U) +#define DCACHE_RHMONR_RHITMON_Msk (0xFFFFFFFFUL << DCACHE_RHMONR_RHITMON_Pos) /*!< 0xFFFFFFFF */ +#define DCACHE_RHMONR_RHITMON DCACHE_RHMONR_RHITMON_Msk /*!< Cache Read hit monitor register */ + +/****************** Bit definition for DCACHE_RMMONR register ****************/ +#define DCACHE_RMMONR_RMISSMON_Pos (0U) +#define DCACHE_RMMONR_RMISSMON_Msk (0xFFFFUL << DCACHE_RMMONR_RMISSMON_Pos) /*!< 0x0000FFFF */ +#define DCACHE_RMMONR_RMISSMON DCACHE_RMMONR_RMISSMON_Msk /*!< Cache Read miss monitor register */ + +/****************** Bit definition for DCACHE_WHMONR register ****************/ +#define DCACHE_WHMONR_WHITMON_Pos (0U) +#define DCACHE_WHMONR_WHITMON_Msk (0xFFFFFFFFUL << DCACHE_WHMONR_WHITMON_Pos) /*!< 0xFFFFFFFF */ +#define DCACHE_WHMONR_WHITMON DCACHE_WHMONR_WHITMON_Msk /*!< Cache Read hit monitor register */ + +/****************** Bit definition for DCACHE_WMMONR register ****************/ +#define DCACHE_WMMONR_WMISSMON_Pos (0U) +#define DCACHE_WMMONR_WMISSMON_Msk (0xFFFFUL << DCACHE_WMMONR_WMISSMON_Pos) /*!< 0x0000FFFF */ +#define DCACHE_WMMONR_WMISSMON DCACHE_WMMONR_WMISSMON_Msk /*!< Cache Read miss monitor register */ + +/****************** Bit definition for DCACHE_CMDRSADDRR register ****************/ +#define DCACHE_CMDRSADDRR_CMDSTARTADDR_Pos (0U) +#define DCACHE_CMDRSADDRR_CMDSTARTADDR_Msk (0xFFFFFFF0UL << DCACHE_CMDRSADDRR_CMDSTARTADDR_Pos) /*!< 0xFFFFFFF0 */ +#define DCACHE_CMDRSADDRR_CMDSTARTADDR DCACHE_CMDRSADDRR_CMDSTARTADDR_Msk /*!< Command start address */ + +/****************** Bit definition for DCACHE_CMDREADDRR register ****************/ +#define DCACHE_CMDREADDRR_CMDENDADDR_Pos (0U) +#define DCACHE_CMDREADDRR_CMDENDADDR_Msk (0xFFFFFFF0UL << DCACHE_CMDREADDRR_CMDENDADDR_Pos) /*!< 0xFFFFFFF0 */ +#define DCACHE_CMDREADDRR_CMDENDADDR DCACHE_CMDREADDRR_CMDENDADDR_Msk /*!< Command end address */ + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ + +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x000000F0 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ +#define COMP_CSR_INPSEL_Pos (8U) +#define COMP_CSR_INPSEL_Msk (0x7UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000700 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000200 */ +#define COMP_CSR_INPSEL_2 (0x4UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000400 */ +#define COMP_CSR_WINMODE_Pos (11U) +#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000800 */ +#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ +#define COMP_CSR_WINOUT_Pos (14U) +#define COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk /*!< Pair of comparators window output level. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00030000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator input hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ +#define COMP_CSR_PWRMODE_Pos (18U) +#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x000C0000 */ +#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */ +#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00040000 */ +#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKSEL_Pos (20U) +#define COMP_CSR_BLANKSEL_Msk (0x1FUL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01F00000 */ +#define COMP_CSR_BLANKSEL COMP_CSR_BLANKSEL_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKSEL_0 (0x01UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKSEL_1 (0x02UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00200000 */ +#define COMP_CSR_BLANKSEL_2 (0x04UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BLANKSEL_3 (0x08UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00800000 */ +#define COMP_CSR_BLANKSEL_4 (0x10UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* Operational Amplifier (OPAMP) */ +/* */ +/******************************************************************************/ +/********************* Bit definition for OPAMPx_CSR register ***************/ +#define OPAMP_CSR_OPAEN_Pos (0U) +#define OPAMP_CSR_OPAEN_Msk (0x1UL << OPAMP_CSR_OPAEN_Pos) /*!< 0x00000001 */ +#define OPAMP_CSR_OPAEN OPAMP_CSR_OPAEN_Msk /*!< OPAMP enable */ +#define OPAMP_CSR_OPALPM_Pos (1U) +#define OPAMP_CSR_OPALPM_Msk (0x1UL << OPAMP_CSR_OPALPM_Pos) /*!< 0x00000002 */ +#define OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk /*!< Operational amplifier Low Power Mode */ +#define OPAMP_CSR_OPAMODE_Pos (2U) +#define OPAMP_CSR_OPAMODE_Msk (0x3UL << OPAMP_CSR_OPAMODE_Pos) /*!< 0x0000000C */ +#define OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk /*!< Operational amplifier PGA mode */ +#define OPAMP_CSR_OPAMODE_0 (0x1UL << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000004 */ +#define OPAMP_CSR_OPAMODE_1 (0x2UL << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000008 */ +#define OPAMP_CSR_PGA_GAIN_Pos (4U) +#define OPAMP_CSR_PGA_GAIN_Msk (0x3UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00000030 */ +#define OPAMP_CSR_PGA_GAIN OPAMP_CSR_PGA_GAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */ +#define OPAMP_CSR_PGA_GAIN_0 (0x1UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00000010 */ +#define OPAMP_CSR_PGA_GAIN_1 (0x2UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00000020 */ +#define OPAMP_CSR_VM_SEL_Pos (8U) +#define OPAMP_CSR_VM_SEL_Msk (0x3UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000300 */ +#define OPAMP_CSR_VM_SEL OPAMP_CSR_VM_SEL_Msk /*!< Inverting input selection */ +#define OPAMP_CSR_VM_SEL_0 (0x1UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000100 */ +#define OPAMP_CSR_VM_SEL_1 (0x2UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000200 */ +#define OPAMP_CSR_VP_SEL_Pos (10U) +#define OPAMP_CSR_VP_SEL_Msk (0x1UL << OPAMP_CSR_VP_SEL_Pos) /*!< 0x00000400 */ +#define OPAMP_CSR_VP_SEL OPAMP_CSR_VP_SEL_Msk /*!< Non inverted input selection */ +#define OPAMP_CSR_CALON_Pos (12U) +#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00001000 */ +#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */ +#define OPAMP_CSR_CALSEL_Pos (13U) +#define OPAMP_CSR_CALSEL_Msk (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */ +#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */ +#define OPAMP_CSR_USERTRIM_Pos (14U) +#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00004000 */ +#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */ +#define OPAMP_CSR_CALOUT_Pos (15U) +#define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos) /*!< 0x00008000 */ +#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier calibration output */ +#define OPAMP_CSR_HSM_Pos (30U) +#define OPAMP_CSR_HSM_Msk (0x1UL << OPAMP_CSR_HSM_Pos) /*!< 0x40000000 */ +#define OPAMP_CSR_HSM OPAMP_CSR_HSM_Msk /*!< Operational amplifier high speed mode */ +#define OPAMP_CSR_OPARANGE_Pos (31U) +#define OPAMP_CSR_OPARANGE_Msk (0x1UL << OPAMP_CSR_OPARANGE_Pos) /*!< 0x80000000 */ +#define OPAMP_CSR_OPARANGE OPAMP_CSR_OPARANGE_Msk /*!< Operational amplifier range setting */ + +/******************* Bit definition for OPAMPx_OTR register ******************/ +#define OPAMP_OTR_TRIMOFFSETN_Pos (0U) +#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */ +#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */ +#define OPAMP_OTR_TRIMOFFSETP_Pos (8U) +#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */ +#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */ + +/******************* Bit definition for OPAMPx_LPOTR register ****************/ +#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0U) +#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */ +#define OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */ +#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8U) +#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */ +#define OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */ + +/******************************************************************************/ +/* */ +/* MDF/ADF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for MDF/ADF_GCR register ********************/ +#define MDF_GCR_TRGO_Pos (0U) +#define MDF_GCR_TRGO_Msk (0x1UL << MDF_GCR_TRGO_Pos) /*!< 0x00000001 */ +#define MDF_GCR_TRGO MDF_GCR_TRGO_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk + +/******************** Bits definition for TAMP_COUNTR register ***************/ +#define TAMP_COUNTR_Pos (16U) +#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ +#define TAMP_COUNTR TAMP_COUNTR_Msk + +/******************** Bits definition for TAMP_ERCFGR register ***************/ +#define TAMP_ERCFGR0_Pos (0U) +#define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* Touch Sensing Controller (TSC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TSC_CR register *********************/ +#define TSC_CR_TSCE_Pos (0U) +#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ +#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/** @addtogroup STM32U5xx_Peripheral_Exported_macros + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS)|| \ + ((INSTANCE) == ADC1_S) || \ + ((INSTANCE) == ADC4_NS)|| \ + ((INSTANCE) == ADC4_S)) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)) + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \ + ((INSTANCE) == ADC12_COMMON_S) || \ + ((INSTANCE) == ADC4_COMMON_NS) || \ + ((INSTANCE) == ADC4_COMMON_S)) + +/******************************* AES Instances ********************************/ +#define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES_NS) || ((INSTANCE) == AES_S)) + +/******************************* PKA Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************** FDCAN Instances *****************************/ +#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S)) + +/******************************** COMP Instances ******************************/ +#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S)) + +/******************************* CORDIC Instances *****************************/ +#define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) + +/******************************* DAC Instances ********************************/ +#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) + +/******************************* DELAYBLOCK Instances *******************************/ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \ + ((INSTANCE) == DLYB_SDMMC1_S) || \ + ((INSTANCE) == DLYB_OCTOSPI1_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI1_S )) + +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ + ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ + ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ + ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ + ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S) || \ + ((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ + ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ + ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ + ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) + +#define IS_GPDMA_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ + ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ + ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ + ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ + ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) + +#define IS_LPDMA_INSTANCE(INSTANCE) (((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ + ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ + ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ + ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) + +#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) + +/****************************** OTFDEC Instances ********************************/ +#define IS_OTFDEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OTFDEC1_NS) || ((INSTANCE) == OTFDEC1_S)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM4_NS) || ((INSTANCE) == RAMCFG_SRAM4_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG ECC Instances *****************************/ +#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG IT Instances ******************************/ +#define IS_RAMCFG_IT_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) + +/******************************** FMAC Instances ******************************/ +#define IS_FMAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FMAC_NS) || ((INSTANCE) == FMAC_S)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \ + ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \ + ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \ + ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \ + ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \ + ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \ + ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S) || \ + ((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) + +/******************************* LPGPIO Instances *****************************/ +#define IS_LPGPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) + +/******************************* DCMI Instances *******************************/ +#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) + +/******************************* DCACHE Instances *****************************/ +#define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S)) + +/******************************* PSSI Instances *******************************/ +#define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) + +/******************************* GPIO AF Instances ****************************/ +/* On U5, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On U5, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************* I2C Instances : Group belongingness *********************/ +#define IS_I2C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +#define IS_I2C_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/****************************** OPAMP Instances *******************************/ +#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1_NS) || ((INSTANCE) == OPAMP1_S)) + +/******************************* OSPI Instances *******************************/ +#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \ + ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S)) + +/****************************** SDMMC Instances *******************************/ +#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S)) +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +/******************* SMBUS Instances : Group belongingness *********************/ +#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) + +#define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) + +#define IS_SPI_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ +#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) ||\ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) ||\ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) ||\ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) ||\ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) ||\ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) ||\ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)||\ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : supporting HSE32 as input ********************/ +#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) ||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ + ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ + ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S) || \ + ((__INSTANCE__) == TIM4_NS) || ((__INSTANCE__) == TIM4_S) || \ + ((__INSTANCE__) == TIM5_NS) || ((__INSTANCE__) == TIM5_S) || \ + ((__INSTANCE__) == TIM6_NS) || ((__INSTANCE__) == TIM6_S) || \ + ((__INSTANCE__) == TIM7_NS) || ((__INSTANCE__) == TIM7_S) || \ + ((__INSTANCE__) == TIM8_NS) || ((__INSTANCE__) == TIM8_S) || \ + ((__INSTANCE__) == TIM15_NS) || ((__INSTANCE__) == TIM15_S)) + +/****************************** TSC Instances *********************************/ +#define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : AUTONOMOUS mode ***************************/ +#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +/******************************* USB DRD FS HCD Instances *************************/ +#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/******************************* USB DRD FS PCD Instances *************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/******************************* MDF/ADF Instances ****************************/ +#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_NS) || ((INSTANCE) == MDF1_Filter0_S) || \ + ((INSTANCE) == MDF1_Filter1_NS) || ((INSTANCE) == MDF1_Filter1_S) || \ + ((INSTANCE) == MDF1_Filter2_NS) || ((INSTANCE) == MDF1_Filter2_S) || \ + ((INSTANCE) == MDF1_Filter3_NS) || ((INSTANCE) == MDF1_Filter3_S) || \ + ((INSTANCE) == MDF1_Filter4_NS) || ((INSTANCE) == MDF1_Filter4_S) || \ + ((INSTANCE) == MDF1_Filter5_NS) || ((INSTANCE) == MDF1_Filter5_S) || \ + ((INSTANCE) == ADF1_Filter0_NS) || ((INSTANCE) == ADF1_Filter0_S)) + + +/** @} */ /* End of group STM32U5xx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32U545xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U545xx_H */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u575xx.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u575xx.h index eea2fbe5b31..fc3a3bd2fce 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u575xx.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u575xx.h @@ -7,12 +7,12 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -67,10 +67,10 @@ typedef enum /* =========================================== STM32U575xx Specific Interrupt Numbers ================================= */ WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ - PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM through EXTI Line detection Interrupt */ RTC_IRQn = 2, /*!< RTC non-secure interrupt */ RTC_S_IRQn = 3, /*!< RTC secure interrupt */ - TAMP_IRQn = 4, /*!< Tamper non-secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ @@ -186,9 +186,9 @@ typedef enum MDF1_FLT5_IRQn = 122, /*!< MDF1 Filter 5 global interrupt */ CORDIC_IRQn = 123, /*!< CORDIC global interrupt */ FMAC_IRQn = 124, /*!< FMAC global interrupt */ + LSECSSD_IRQn = 125, /*!< LSECSSD and MSI_PLL_UNLOCK global interrupts */ } IRQn_Type; - /* =========================================================================================================================== */ /* ================ Processor and Core Peripheral Section ================ */ /* =========================================================================================================================== */ @@ -743,7 +743,7 @@ typedef struct */ typedef struct { - __IO uint32_t CSR; /*!< Comparator control/status register , Address offset: 0x00 */ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ } COMP_TypeDef; typedef struct @@ -762,8 +762,12 @@ typedef struct __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ } OPAMP_TypeDef; -/*Aliases */ -#define OPAMP_Common_TypeDef OPAMP_TypeDef +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + /** * @brief MDF/ADF @@ -810,109 +814,115 @@ typedef struct typedef struct { - __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ - __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ - __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ - __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ - __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */ - uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ - __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ - __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ - uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ - __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ - uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ - __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ - uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ - __IO uint32_t DR; /*!< OCTOPSI Data register, Address offset: 0x050 */ - uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ - __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ - uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ - __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ - uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ - __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ - uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ - __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ - uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ - __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ - uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ - __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ - uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ - __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ - uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ - __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ - uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ - __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */ - uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ - __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */ - uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ - __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */ - uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ - __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */ - uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ - __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ - uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ - __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ - uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ - __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ - uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ - __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ - uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ - __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ -} OCTOSPI_TypeDef; + __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + + /** - * @brief OCTO Serial Peripheral Interface IO Manager + * @brief Serial Peripheral Interface IO Manager */ typedef struct { - __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */ - __IO uint32_t PCR[8]; /*!< OCTOSPI IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ -} OCTOSPIM_TypeDef; + __IO uint32_t CR; /*!< OCTOSPIM IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[8]; /*!< OCTOSPIM IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ +} XSPIM_TypeDef; + +typedef XSPIM_TypeDef OCTOSPIM_TypeDef; /** * @brief Power Control */ typedef struct { - __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ - __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ - __IO uint32_t VOSR; /*!< PWR voltage scaling register, Address offset: 0x0C */ - __IO uint32_t SVMCR; /*!< PWR supply voltage monitoring control register, Address offset: 0x10 */ - __IO uint32_t WUCR1; /*!< PWR wakeup control register 1, Address offset: 0x14 */ - __IO uint32_t WUCR2; /*!< PWR wakeup control register 2, Address offset: 0x18 */ - __IO uint32_t WUCR3; /*!< PWR wakeup control register 3, Address offset: 0x1C */ - __IO uint32_t BDCR1; /*!< PWR backup domain control register 1, Address offset: 0x20 */ - __IO uint32_t BDCR2; /*!< PWR backup domain control register 2, Address offset: 0x24 */ - __IO uint32_t DBPR; /*!< PWR disable backup domain register, Address offset: 0x28 */ - __IO uint32_t UCPDR; /*!< PWR USB Type-C and Power Delivery register, Address offset: 0x2C */ - __IO uint32_t SECCFGR; /*!< PWR Security configuration register, Address offset: 0x30 */ - __IO uint32_t PRIVCFGR; /*!< PWR privilege control register, Address offset: 0x34 */ - __IO uint32_t SR; /*!< PWR status register, Address offset: 0x38 */ - __IO uint32_t SVMSR; /*!< PWR supply voltage monitoring status register, Address offset: 0x3C */ - __IO uint32_t BDSR; /*!< PWR backup domain status register, Address offset: 0x40 */ - __IO uint32_t WUSR; /*!< PWR wakeup status register, Address offset: 0x44 */ - __IO uint32_t WUSCR; /*!< PWR wakeup status clear register, Address offset: 0x48 */ - __IO uint32_t APCR; /*!< PWR apply pull configuration register, Address offset: 0x4C */ - __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ - __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ - __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ - __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ - __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ - __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ - __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ - __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ - __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ - __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ - __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */ - __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */ - __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ - __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ - __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ - __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ - __IO uint32_t PUCRI; /*!< Power Port I pull-up control register, Address offset: 0x90 */ - __IO uint32_t PDCRI; /*!< Power Port I pull-down control register, Address offset: 0x94 */ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x20 */ + __IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Power USB Type-C and Power Delivery register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + __IO uint32_t BDSR; /*!< Power backup domain status register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */ + __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ + __IO uint32_t PUCRI; /*!< Power Port I pull-up control register, Address offset: 0x90 */ + __IO uint32_t PDCRI; /*!< Power Port I pull-down control register, Address offset: 0x94 */ } PWR_TypeDef; /** @@ -1206,7 +1216,6 @@ typedef struct /** * @brief Delay Block DLYB */ - typedef struct { __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ @@ -1220,7 +1229,7 @@ typedef struct { __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ - uint32_t RESERVED0; /*!< Reserved Address offset: 0x08 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ @@ -1479,7 +1488,7 @@ typedef struct __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ /* Specific to ADC 14Bits*/ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ /* Specific to ADC 14Bits*/ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ - __IO uint32_t PW; /*!< ADC power register, Address offset: 0x44 */ + __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ uint32_t RESERVED1; /*!< Reserved, 0x048 */ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ /* Specific to ADC 14Bits*/ uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C */ @@ -1514,6 +1523,10 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ } ADC_Common_TypeDef; + +/* Legacy registers naming */ +#define PW PWRR + /** * @brief CORDIC */ @@ -1787,6 +1800,7 @@ typedef struct #define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) #define DLYB_OCTOSPI2_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF400UL) #define FMC_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB0400UL) /*!< FMC control registers base address */ +/*!< FMC Banks Non secure registers base address */ #define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) #define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) #define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) @@ -1869,12 +1883,10 @@ typedef struct /*!< APB3 Secure peripherals */ #define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) -#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) -#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1308UL) #define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) #define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) #define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) -#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4300UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) #define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) #define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) #define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) @@ -1969,6 +1981,8 @@ typedef struct #define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) #define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) #define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1308UL) #define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) #define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) #define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) @@ -1982,9 +1996,9 @@ typedef struct #define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) #define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) + /* Debug MCU registers base address */ #define DBGMCU_BASE (0xE0044000UL) - #define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ #define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */ @@ -1993,7 +2007,7 @@ typedef struct #define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */ #define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */ -/* USB OTG FS registers Base address */ +/* USB OTG registers Base address */ #define USB_OTG_GLOBAL_BASE (0x0000UL) #define USB_OTG_DEVICE_BASE (0x0800UL) #define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) @@ -2129,6 +2143,7 @@ typedef struct #define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) #define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) #define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) #define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) #define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) #define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) @@ -2199,7 +2214,6 @@ typedef struct #define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) #define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) #define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) -#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS) #define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) #define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) #define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) @@ -2209,6 +2223,7 @@ typedef struct #define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) #define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) #define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS) #define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) #define OCTOSPI2_NS ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS) @@ -2280,6 +2295,7 @@ typedef struct #define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) #define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) #define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) #define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) #define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) #define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) @@ -2350,7 +2366,6 @@ typedef struct #define HASH_S ((HASH_TypeDef *) HASH_BASE_S) #define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) #define RNG_S ((RNG_TypeDef *) RNG_BASE_S) -#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S) #define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) #define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) #define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) @@ -2360,6 +2375,7 @@ typedef struct #define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) #define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) #define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S) #define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) #define OCTOSPI2_S ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S) @@ -2674,6 +2690,9 @@ typedef struct #define OPAMP2 OPAMP2_S #define OPAMP2_BASE OPAMP2_BASE_S +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S + #define LPTIM1 LPTIM1_S #define LPTIM1_BASE LPTIM1_BASE_S @@ -2740,6 +2759,7 @@ typedef struct #define ADC12_COMMON ADC12_COMMON_S #define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + #define ADC4 ADC4_S #define ADC4_BASE ADC4_BASE_S @@ -2825,7 +2845,6 @@ typedef struct #define ADF1_Filter0_BASE ADF1_Filter0_BASE_S #else - /*!< Memory base addresses for Non secure peripherals */ #define FLASH_BASE FLASH_BASE_NS #define SRAM1_BASE SRAM1_BASE_NS @@ -2953,7 +2972,6 @@ typedef struct #define GPIOI GPIOI_NS #define GPIOI_BASE GPIOI_BASE_NS - #define LPGPIO1 LPGPIO1_NS #define LPGPIO1_BASE LPGPIO1_BASE_NS @@ -3111,6 +3129,9 @@ typedef struct #define OPAMP2 OPAMP2_NS #define OPAMP2_BASE OPAMP2_BASE_NS +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS + #define LPTIM1 LPTIM1_NS #define LPTIM1_BASE LPTIM1_BASE_NS @@ -3257,9 +3278,17 @@ typedef struct #define ADF1_Filter0 ADF1_Filter0_NS #define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS - #endif +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + /******************************************************************************/ /* */ /* Analog to Digital Converter */ @@ -3372,18 +3401,21 @@ typedef struct #define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ #define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ +#define ADC_CR_CALINDEX_Pos (24U) +#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ +#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ #define ADC_CR_CALINDEX0_Pos (24U) #define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ -#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC Linearity calibration ready Word 3 */ +#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ #define ADC_CR_CALINDEX1_Pos (25U) #define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ -#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC Linearity calibration ready Word 4 */ +#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ #define ADC_CR_CALINDEX2_Pos (26U) #define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ -#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC Linearity calibration ready Word 5 */ +#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ #define ADC_CR_CALINDEX3_Pos (27U) #define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ -#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC Linearity calibration ready Word 6 */ +#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ #define ADC_CR_ADVREGEN_Pos (28U) #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ @@ -3452,7 +3484,6 @@ typedef struct #define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ #define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ - #define ADC_CFGR1_DISCEN_Pos (16U) #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ @@ -3525,7 +3556,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_OVSR_Pos (16U) #define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ @@ -3737,7 +3767,6 @@ typedef struct #define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ #define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ - /******************** Bit definition for ADC_SMPR2 register ********************/ #define ADC_SMPR2_SMP10_Pos (0U) #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ @@ -3846,7 +3875,7 @@ typedef struct #define ADC_HTR_AWDFILT_Pos (29U) #define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ -#define ADC_HTR_AWDFILT ADC_HTR_HT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ +#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ #define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ #define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ #define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ @@ -4012,19 +4041,32 @@ typedef struct #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ /******************** Bit definition for ADC_PW register ********************/ -#define ADC4_PW_AUTOFF_Pos (0U) -#define ADC4_PW_AUTOFF_Msk (0x1UL << ADC4_PW_AUTOFF_Pos) /*!< 0x00000001 */ -#define ADC4_PW_AUTOFF ADC4_PW_AUTOFF_Msk /*!< ADC Auto-Off mode */ -#define ADC4_PW_DPD_Pos (1U) -#define ADC4_PW_DPD_Msk (0x1UL << ADC4_PW_DPD_Pos) /*!< 0x00000002 */ -#define ADC4_PW_DPD ADC4_PW_DPD_Msk /*!< ADC Deep Power mode */ -#define ADC4_PW_VREFPROT_Pos (2U) -#define ADC4_PW_VREFPROT_Msk (0x1UL << ADC4_PW_VREFPROT_Pos) /*!< 0x00000004 */ -#define ADC4_PW_VREFPROT ADC4_PW_VREFPROT_Msk /*!< ADC Vref protection */ -#define ADC4_PW_VREFSECSMP_Pos (3U) -#define ADC4_PW_VREFSECSMP_Msk (0x1UL << ADC4_PW_VREFSECSMP_Pos) /*!< 0x00000008 */ -#define ADC4_PW_VREFSECSMP ADC4_PW_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ - +#define ADC4_PWRR_AUTOFF_Pos (0U) +#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ +#define ADC4_PWRR_DPD_Pos (1U) +#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ +#define ADC4_PWRR_VREFPROT_Pos (2U) +#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ +#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ +#define ADC4_PWRR_VREFSECSMP_Pos (3U) +#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ +#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ + +/* Legacy definitions */ +#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos +#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk +#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF +#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos +#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk +#define ADC4_PW_DPD ADC4_PWRR_DPD +#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos +#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk +#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT +#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos +#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk +#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP /******************** Bit definition for ADC_JSQR register ********************/ #define ADC_JSQR_JL_Pos (0U) @@ -4124,7 +4166,6 @@ typedef struct #define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ #define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ - #define ADC_OFR1_OFFSET1_CH_Pos (27U) #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ @@ -4134,10 +4175,9 @@ typedef struct #define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ - /******************** Bit definition for ADC_OFR2 register ********************/ #define ADC_OFR2_OFFSET2_Pos (0U) -#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ #define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ #define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ @@ -4169,13 +4209,11 @@ typedef struct #define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ #define ADC_OFR2_USAT_Pos (25U) #define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ -#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ - -#define ADC_OFR2_SSAT_Pos (26U) -#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ -#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ - +#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ +#define ADC_OFR2_SSAT_Pos (26U) +#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ #define ADC_OFR2_OFFSET2_CH_Pos (27U) #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ @@ -4188,7 +4226,7 @@ typedef struct /******************** Bit definition for ADC_OFR3 register ********************/ #define ADC_OFR3_OFFSET3_Pos (0U) -#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ #define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ #define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ @@ -4226,7 +4264,6 @@ typedef struct #define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ #define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ - #define ADC_OFR3_OFFSET3_CH_Pos (27U) #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ @@ -4236,10 +4273,9 @@ typedef struct #define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ - /******************** Bit definition for ADC_OFR4 register ********************/ #define ADC_OFR4_OFFSET4_Pos (0U) -#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ #define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ #define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ @@ -4294,7 +4330,6 @@ typedef struct #define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ #define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ - /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) #define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ @@ -4472,7 +4507,6 @@ typedef struct #define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ #define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ - /******************** Bit definition for ADC_AWD1TR register *******************/ #define ADC_AWD1TR_LT1_Pos (0U) #define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ @@ -4685,7 +4719,6 @@ typedef struct #define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ #define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_AWD3TR register *******************/ #define ADC_AWD3TR_LT3_Pos (0U) #define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ @@ -4719,7 +4752,6 @@ typedef struct #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ #define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ - /******************** Bit definition for ADC_AWD3CR register ********************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) #define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ @@ -4809,7 +4841,6 @@ typedef struct #define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ #define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ - #define ADC4_CALFACT_CALFACT_Pos (0U) #define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ #define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ @@ -4821,8 +4852,6 @@ typedef struct #define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ #define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ - - /******************** Bit definition for ADC_CALFACT2 register ********************/ #define ADC_CALFACT2_CALFACT_Pos (0U) #define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ @@ -4860,16 +4889,12 @@ typedef struct #define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */ #define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_OR register ********************/ #define ADC_OR_CHN0SEL_Pos (0U) #define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ #define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ - /************************* ADC Common registers *****************************/ -/******************** Bit definition for ADC_CCR register ********************/ - #define ADC_CCR_PRESC_Pos (18U) #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ @@ -4957,7 +4982,6 @@ typedef struct #define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ #define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ - /******************************************************************************/ /* */ /* CRC calculation unit */ @@ -5001,7 +5025,6 @@ typedef struct #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ - /******************************************************************************/ /* */ /* CRS Clock Recovery System */ @@ -5097,7 +5120,6 @@ typedef struct #define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ - /******************************************************************************/ /* */ /* RNG */ @@ -5446,7 +5468,6 @@ typedef struct #define DAC_AUTOCR_AUTOMODE_Msk (0x1UL << DAC_AUTOCR_AUTOMODE_Pos) /*!< 0x00400000 */ #define DAC_AUTOCR_AUTOMODE DAC_AUTOCR_AUTOMODE_Msk /*!< AUTOCR Enable */ - /******************************************************************************/ /* */ /* HASH */ @@ -5541,7 +5562,6 @@ typedef struct #define HASH_SR_NBWP_2 (0x04UL << HASH_SR_NBWP_Pos) /*!< 0x00000800 */ #define HASH_SR_NBWP_3 (0x08UL << HASH_SR_NBWP_Pos) /*!< 0x00001000 */ - /******************************************************************************/ /* */ /* Debug MCU */ @@ -5613,9 +5633,6 @@ typedef struct #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U) #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk -#define DBGMCU_APB1FZR2_DBG_FDCAN_STOP_Pos (9U) -#define DBGMCU_APB1FZR2_DBG_FDCAN_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_FDCAN_STOP_Pos) -#define DBGMCU_APB1FZR2_DBG_FDCAN_STOP DBGMCU_APB1FZR2_DBG_FDCAN_STOP_Msk /******************** Bit definition for DBGMCU_APB2FZR register ***********/ #define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) @@ -5821,7 +5838,6 @@ typedef struct #define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */ #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk - /******************** Bits definition for DCMI_MIS register *****************/ #define DCMI_MIS_FRAME_MIS_Pos (0U) #define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */ @@ -5839,7 +5855,6 @@ typedef struct #define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */ #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk - /******************** Bits definition for DCMI_ICR register *****************/ #define DCMI_ICR_FRAME_ISC_Pos (0U) #define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */ @@ -5857,7 +5872,6 @@ typedef struct #define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */ #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk - /******************** Bits definition for DCMI_ESCR register ******************/ #define DCMI_ESCR_FSC_Pos (0U) #define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */ @@ -6220,7 +6234,7 @@ typedef struct #define DMA_CSR_USEF DMA_CSR_USEF_Msk /*!< User setting error flag */ #define DMA_CSR_SUSPF_Pos (13U) #define DMA_CSR_SUSPF_Msk (0x1UL << DMA_CSR_SUSPF_Pos) /*!< 0x00002000 */ -#define DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk /*!< User setting error flag */ +#define DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk /*!< Completed suspension flag */ #define DMA_CSR_TOF_Pos (14U) #define DMA_CSR_TOF_Msk (0x1UL << DMA_CSR_TOF_Pos) /*!< 0x00004000 */ #define DMA_CSR_TOF DMA_CSR_TOF_Msk /*!< Trigger overrun flag */ @@ -6428,7 +6442,6 @@ typedef struct #define DMA_CLLR_UT1_Msk (0x1UL << DMA_CLLR_UT1_Pos) /*!< 0x80000000 */ #define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update transfer register 1 from SRAM */ - /******************************************************************************/ /* */ /* AHB Master DMA2D Controller (DMA2D) */ @@ -6555,11 +6568,6 @@ typedef struct #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */ #define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */ #define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */ -#define DMA2D_FGPFCCR_CSS_Pos (18U) -#define DMA2D_FGPFCCR_CSS_Msk (0x3UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x000C0000 */ -#define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sampling */ -#define DMA2D_FGPFCCR_CSS_0 (0x1UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00040000 */ -#define DMA2D_FGPFCCR_CSS_1 (0x2UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00080000 */ #define DMA2D_FGPFCCR_AI_Pos (20U) #define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */ #define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Foreground Input Alpha Inverted */ @@ -6733,7 +6741,6 @@ typedef struct #define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */ #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */ - /******************************************************************************/ /* */ /* External Interrupt/Event Controller */ @@ -6812,9 +6819,6 @@ typedef struct #define EXTI_RTSR1_RT23_Pos (23U) #define EXTI_RTSR1_RT23_Msk (0x1UL << EXTI_RTSR1_RT23_Pos) /*!< 0x00800000 */ #define EXTI_RTSR1_RT23 EXTI_RTSR1_RT23_Msk /*!< Rising trigger configuration for input line 23 */ -#define EXTI_RTSR1_RT24_Pos (24U) -#define EXTI_RTSR1_RT24_Msk (0x1UL << EXTI_RTSR1_RT24_Pos) /*!< 0x01000000 */ -#define EXTI_RTSR1_RT24 EXTI_RTSR1_RT24_Msk /*!< Rising trigger configuration for input line 24 */ /****************** Bit definition for EXTI_FTSR1 register ******************/ #define EXTI_FTSR1_FT0_Pos (0U) @@ -6889,9 +6893,6 @@ typedef struct #define EXTI_FTSR1_FT23_Pos (23U) #define EXTI_FTSR1_FT23_Msk (0x1UL << EXTI_FTSR1_FT23_Pos) /*!< 0x00800000 */ #define EXTI_FTSR1_FT23 EXTI_FTSR1_FT23_Msk /*!< Falling trigger configuration for input line 23 */ -#define EXTI_FTSR1_FT24_Pos (24U) -#define EXTI_FTSR1_FT24_Msk (0x1UL << EXTI_FTSR1_FT24_Pos) /*!< 0x01000000 */ -#define EXTI_FTSR1_FT24 EXTI_FTSR1_FT24_Msk /*!< Falling trigger configuration for input line 24 */ /****************** Bit definition for EXTI_SWIER1 register *****************/ #define EXTI_SWIER1_SWI0_Pos (0U) @@ -6966,9 +6967,6 @@ typedef struct #define EXTI_SWIER1_SWI23_Pos (23U) #define EXTI_SWIER1_SWI23_Msk (0x1UL << EXTI_SWIER1_SWI23_Pos) /*!< 0x00800000 */ #define EXTI_SWIER1_SWI23 EXTI_SWIER1_SWI23_Msk /*!< Software Interrupt on line 23 */ -#define EXTI_SWIER1_SWI24_Pos (24U) -#define EXTI_SWIER1_SWI24_Msk (0x1UL << EXTI_SWIER1_SWI24_Pos) /*!< 0x01000000 */ -#define EXTI_SWIER1_SWI24 EXTI_SWIER1_SWI24_Msk /*!< Software Interrupt on line 24 */ /******************* Bit definition for EXTI_RPR1 register ******************/ #define EXTI_RPR1_RPIF0_Pos (0U) @@ -7043,9 +7041,6 @@ typedef struct #define EXTI_RPR1_RPIF23_Pos (23U) #define EXTI_RPR1_RPIF23_Msk (0x1UL << EXTI_RPR1_RPIF23_Pos) /*!< 0x00800000 */ #define EXTI_RPR1_RPIF23 EXTI_RPR1_RPIF23_Msk /*!< Rising Pending Interrupt Flag on line 23 */ -#define EXTI_RPR1_RPIF24_Pos (24U) -#define EXTI_RPR1_RPIF24_Msk (0x1UL << EXTI_RPR1_RPIF24_Pos) /*!< 0x01000000 */ -#define EXTI_RPR1_RPIF24 EXTI_RPR1_RPIF24_Msk /*!< Rising Pending Interrupt Flag on line 24 */ /******************* Bit definition for EXTI_FPR1 register ******************/ #define EXTI_FPR1_FPIF0_Pos (0U) @@ -7120,163 +7115,154 @@ typedef struct #define EXTI_FPR1_FPIF23_Pos (23U) #define EXTI_FPR1_FPIF23_Msk (0x1UL << EXTI_FPR1_FPIF23_Pos) /*!< 0x00800000 */ #define EXTI_FPR1_FPIF23 EXTI_FPR1_FPIF23_Msk /*!< Falling Pending Interrupt Flag on line 23 */ -#define EXTI_FPR1_FPIF24_Pos (24U) -#define EXTI_FPR1_FPIF24_Msk (0x1UL << EXTI_FPR1_FPIF24_Pos) /*!< 0x01000000 */ -#define EXTI_FPR1_FPIF24 EXTI_FPR1_FPIF24_Msk /*!< Falling Pending Interrupt Flag on line 24 */ - -/******************* Bit definition for EXTI_SECENR1 register ******************/ -#define EXTI_SECENR1_RPIF0_Pos (0U) -#define EXTI_SECENR1_RPIF0_Msk (0x1UL << EXTI_SECENR1_RPIF0_Pos) /*!< 0x00000001 */ -#define EXTI_SECENR1_RPIF0 EXTI_SECENR1_RPIF0_Msk /*!< Security enable on line 0 */ -#define EXTI_SECENR1_RPIF1_Pos (1U) -#define EXTI_SECENR1_RPIF1_Msk (0x1UL << EXTI_SECENR1_RPIF1_Pos) /*!< 0x00000002 */ -#define EXTI_SECENR1_RPIF1 EXTI_SECENR1_RPIF1_Msk /*!< Security enable on line 1 */ -#define EXTI_SECENR1_RPIF2_Pos (2U) -#define EXTI_SECENR1_RPIF2_Msk (0x1UL << EXTI_SECENR1_RPIF2_Pos) /*!< 0x00000004 */ -#define EXTI_SECENR1_RPIF2 EXTI_SECENR1_RPIF2_Msk /*!< Security enable on line 2 */ -#define EXTI_SECENR1_RPIF3_Pos (3U) -#define EXTI_SECENR1_RPIF3_Msk (0x1UL << EXTI_SECENR1_RPIF3_Pos) /*!< 0x00000008 */ -#define EXTI_SECENR1_RPIF3 EXTI_SECENR1_RPIF3_Msk /*!< Security enable on line 3 */ -#define EXTI_SECENR1_RPIF4_Pos (4U) -#define EXTI_SECENR1_RPIF4_Msk (0x1UL << EXTI_SECENR1_RPIF4_Pos) /*!< 0x00000010 */ -#define EXTI_SECENR1_RPIF4 EXTI_SECENR1_RPIF4_Msk /*!< Security enable on line 4 */ -#define EXTI_SECENR1_RPIF5_Pos (5U) -#define EXTI_SECENR1_RPIF5_Msk (0x1UL << EXTI_SECENR1_RPIF5_Pos) /*!< 0x00000020 */ -#define EXTI_SECENR1_RPIF5 EXTI_SECENR1_RPIF5_Msk /*!< Security enable on line 5 */ -#define EXTI_SECENR1_RPIF6_Pos (6U) -#define EXTI_SECENR1_RPIF6_Msk (0x1UL << EXTI_SECENR1_RPIF6_Pos) /*!< 0x00000040 */ -#define EXTI_SECENR1_RPIF6 EXTI_SECENR1_RPIF6_Msk /*!< Security enable on line 6 */ -#define EXTI_SECENR1_RPIF7_Pos (7U) -#define EXTI_SECENR1_RPIF7_Msk (0x1UL << EXTI_SECENR1_RPIF7_Pos) /*!< 0x00000080 */ -#define EXTI_SECENR1_RPIF7 EXTI_SECENR1_RPIF7_Msk /*!< Security enable on line 7 */ -#define EXTI_SECENR1_RPIF8_Pos (8U) -#define EXTI_SECENR1_RPIF8_Msk (0x1UL << EXTI_SECENR1_RPIF8_Pos) /*!< 0x00000100 */ -#define EXTI_SECENR1_RPIF8 EXTI_SECENR1_RPIF8_Msk /*!< Security enable on line 8 */ -#define EXTI_SECENR1_RPIF9_Pos (9U) -#define EXTI_SECENR1_RPIF9_Msk (0x1UL << EXTI_SECENR1_RPIF9_Pos) /*!< 0x00000200 */ -#define EXTI_SECENR1_RPIF9 EXTI_SECENR1_RPIF9_Msk /*!< Security enable on line 9 */ -#define EXTI_SECENR1_RPIF10_Pos (10U) -#define EXTI_SECENR1_RPIF10_Msk (0x1UL << EXTI_SECENR1_RPIF10_Pos) /*!< 0x00000400 */ -#define EXTI_SECENR1_RPIF10 EXTI_SECENR1_RPIF10_Msk /*!< Security enable on line 10 */ -#define EXTI_SECENR1_RPIF11_Pos (11U) -#define EXTI_SECENR1_RPIF11_Msk (0x1UL << EXTI_SECENR1_RPIF11_Pos) /*!< 0x00000800 */ -#define EXTI_SECENR1_RPIF11 EXTI_SECENR1_RPIF11_Msk /*!< Security enable on line 11 */ -#define EXTI_SECENR1_RPIF12_Pos (12U) -#define EXTI_SECENR1_RPIF12_Msk (0x1UL << EXTI_SECENR1_RPIF12_Pos) /*!< 0x00001000 */ -#define EXTI_SECENR1_RPIF12 EXTI_SECENR1_RPIF12_Msk /*!< Security enable on line 12 */ -#define EXTI_SECENR1_RPIF13_Pos (13U) -#define EXTI_SECENR1_RPIF13_Msk (0x1UL << EXTI_SECENR1_RPIF13_Pos) /*!< 0x00002000 */ -#define EXTI_SECENR1_RPIF13 EXTI_SECENR1_RPIF13_Msk /*!< Security enable on line 13 */ -#define EXTI_SECENR1_RPIF14_Pos (14U) -#define EXTI_SECENR1_RPIF14_Msk (0x1UL << EXTI_SECENR1_RPIF14_Pos) /*!< 0x00004000 */ -#define EXTI_SECENR1_RPIF14 EXTI_SECENR1_RPIF14_Msk /*!< Security enable on line 14 */ -#define EXTI_SECENR1_RPIF15_Pos (15U) -#define EXTI_SECENR1_RPIF15_Msk (0x1UL << EXTI_SECENR1_RPIF15_Pos) /*!< 0x00008000 */ -#define EXTI_SECENR1_RPIF15 EXTI_SECENR1_RPIF15_Msk /*!< Security enable on line 15 */ -#define EXTI_SECENR1_RPIF16_Pos (16U) -#define EXTI_SECENR1_RPIF16_Msk (0x1UL << EXTI_SECENR1_RPIF16_Pos) /*!< 0x00010000 */ -#define EXTI_SECENR1_RPIF16 EXTI_SECENR1_RPIF16_Msk /*!< Security enable on line 16 */ -#define EXTI_SECENR1_RPIF17_Pos (17U) -#define EXTI_SECENR1_RPIF17_Msk (0x1UL << EXTI_SECENR1_RPIF17_Pos) /*!< 0x00020000 */ -#define EXTI_SECENR1_RPIF17 EXTI_SECENR1_RPIF17_Msk /*!< Security enable on line 17 */ -#define EXTI_SECENR1_RPIF18_Pos (18U) -#define EXTI_SECENR1_RPIF18_Msk (0x1UL << EXTI_SECENR1_RPIF18_Pos) /*!< 0x00040000 */ -#define EXTI_SECENR1_RPIF18 EXTI_SECENR1_RPIF18_Msk /*!< Security enable on line 18 */ -#define EXTI_SECENR1_RPIF19_Pos (19U) -#define EXTI_SECENR1_RPIF19_Msk (0x1UL << EXTI_SECENR1_RPIF19_Pos) /*!< 0x00080000 */ -#define EXTI_SECENR1_RPIF19 EXTI_SECENR1_RPIF19_Msk /*!< Security enable on line 19 */ -#define EXTI_SECENR1_RPIF20_Pos (20U) -#define EXTI_SECENR1_RPIF20_Msk (0x1UL << EXTI_SECENR1_RPIF20_Pos) /*!< 0x00100000 */ -#define EXTI_SECENR1_RPIF20 EXTI_SECENR1_RPIF20_Msk /*!< Security enable on line 20 */ -#define EXTI_SECENR1_RPIF21_Pos (21U) -#define EXTI_SECENR1_RPIF21_Msk (0x1UL << EXTI_SECENR1_RPIF21_Pos) /*!< 0x00200000 */ -#define EXTI_SECENR1_RPIF21 EXTI_SECENR1_RPIF21_Msk /*!< Security enable on line 21 */ -#define EXTI_SECENR1_RPIF22_Pos (22U) -#define EXTI_SECENR1_RPIF22_Msk (0x1UL << EXTI_SECENR1_RPIF22_Pos) /*!< 0x00400000 */ -#define EXTI_SECENR1_RPIF22 EXTI_SECENR1_RPIF22_Msk /*!< Security enable on line 22 */ -#define EXTI_SECENR1_RPIF23_Pos (23U) -#define EXTI_SECENR1_RPIF23_Msk (0x1UL << EXTI_SECENR1_RPIF23_Pos) /*!< 0x00800000 */ -#define EXTI_SECENR1_RPIF23 EXTI_SECENR1_RPIF23_Msk /*!< Security enable on line 23 */ -#define EXTI_SECENR1_RPIF24_Pos (24U) -#define EXTI_SECENR1_RPIF24_Msk (0x1UL << EXTI_SECENR1_RPIF24_Pos) /*!< 0x01000000 */ -#define EXTI_SECENR1_RPIF24 EXTI_SECENR1_RPIF24_Msk /*!< Security enable on line 24 */ - -/******************* Bit definition for EXTI_PRIVENR1 register ******************/ -#define EXTI_PRIVENR1_RPIF0_Pos (0U) -#define EXTI_PRIVENR1_RPIF0_Msk (0x1UL << EXTI_PRIVENR1_RPIF0_Pos) /*!< 0x00000001 */ -#define EXTI_PRIVENR1_RPIF0 EXTI_PRIVENR1_RPIF0_Msk /*!< Privilege enable on line 0 */ -#define EXTI_PRIVENR1_RPIF1_Pos (1U) -#define EXTI_PRIVENR1_RPIF1_Msk (0x1UL << EXTI_PRIVENR1_RPIF1_Pos) /*!< 0x00000002 */ -#define EXTI_PRIVENR1_RPIF1 EXTI_PRIVENR1_RPIF1_Msk /*!< Privilege enable on line 1 */ -#define EXTI_PRIVENR1_RPIF2_Pos (2U) -#define EXTI_PRIVENR1_RPIF2_Msk (0x1UL << EXTI_PRIVENR1_RPIF2_Pos) /*!< 0x00000004 */ -#define EXTI_PRIVENR1_RPIF2 EXTI_PRIVENR1_RPIF2_Msk /*!< Privilege enable on line 2 */ -#define EXTI_PRIVENR1_RPIF3_Pos (3U) -#define EXTI_PRIVENR1_RPIF3_Msk (0x1UL << EXTI_PRIVENR1_RPIF3_Pos) /*!< 0x00000008 */ -#define EXTI_PRIVENR1_RPIF3 EXTI_PRIVENR1_RPIF3_Msk /*!< Privilege enable on line 3 */ -#define EXTI_PRIVENR1_RPIF4_Pos (4U) -#define EXTI_PRIVENR1_RPIF4_Msk (0x1UL << EXTI_PRIVENR1_RPIF4_Pos) /*!< 0x00000010 */ -#define EXTI_PRIVENR1_RPIF4 EXTI_PRIVENR1_RPIF4_Msk /*!< Privilege enable on line 4 */ -#define EXTI_PRIVENR1_RPIF5_Pos (5U) -#define EXTI_PRIVENR1_RPIF5_Msk (0x1UL << EXTI_PRIVENR1_RPIF5_Pos) /*!< 0x00000020 */ -#define EXTI_PRIVENR1_RPIF5 EXTI_PRIVENR1_RPIF5_Msk /*!< Privilege enable on line 5 */ -#define EXTI_PRIVENR1_RPIF6_Pos (6U) -#define EXTI_PRIVENR1_RPIF6_Msk (0x1UL << EXTI_PRIVENR1_RPIF6_Pos) /*!< 0x00000040 */ -#define EXTI_PRIVENR1_RPIF6 EXTI_PRIVENR1_RPIF6_Msk /*!< Privilege enable on line 6 */ -#define EXTI_PRIVENR1_RPIF7_Pos (7U) -#define EXTI_PRIVENR1_RPIF7_Msk (0x1UL << EXTI_PRIVENR1_RPIF7_Pos) /*!< 0x00000080 */ -#define EXTI_PRIVENR1_RPIF7 EXTI_PRIVENR1_RPIF7_Msk /*!< Privilege enable on line 7 */ -#define EXTI_PRIVENR1_RPIF8_Pos (8U) -#define EXTI_PRIVENR1_RPIF8_Msk (0x1UL << EXTI_PRIVENR1_RPIF8_Pos) /*!< 0x00000100 */ -#define EXTI_PRIVENR1_RPIF8 EXTI_PRIVENR1_RPIF8_Msk /*!< Privilege enable on line 8 */ -#define EXTI_PRIVENR1_RPIF9_Pos (9U) -#define EXTI_PRIVENR1_RPIF9_Msk (0x1UL << EXTI_PRIVENR1_RPIF9_Pos) /*!< 0x00000200 */ -#define EXTI_PRIVENR1_RPIF9 EXTI_PRIVENR1_RPIF9_Msk /*!< Privilege enable on line 9 */ -#define EXTI_PRIVENR1_RPIF10_Pos (10U) -#define EXTI_PRIVENR1_RPIF10_Msk (0x1UL << EXTI_PRIVENR1_RPIF10_Pos) /*!< 0x00000400 */ -#define EXTI_PRIVENR1_RPIF10 EXTI_PRIVENR1_RPIF10_Msk /*!< Privilege enable on line 10 */ -#define EXTI_PRIVENR1_RPIF11_Pos (11U) -#define EXTI_PRIVENR1_RPIF11_Msk (0x1UL << EXTI_PRIVENR1_RPIF11_Pos) /*!< 0x00000800 */ -#define EXTI_PRIVENR1_RPIF11 EXTI_PRIVENR1_RPIF11_Msk /*!< Privilege enable on line 11 */ -#define EXTI_PRIVENR1_RPIF12_Pos (12U) -#define EXTI_PRIVENR1_RPIF12_Msk (0x1UL << EXTI_PRIVENR1_RPIF12_Pos) /*!< 0x00001000 */ -#define EXTI_PRIVENR1_RPIF12 EXTI_PRIVENR1_RPIF12_Msk /*!< Privilege enable on line 12 */ -#define EXTI_PRIVENR1_RPIF13_Pos (13U) -#define EXTI_PRIVENR1_RPIF13_Msk (0x1UL << EXTI_PRIVENR1_RPIF13_Pos) /*!< 0x00002000 */ -#define EXTI_PRIVENR1_RPIF13 EXTI_PRIVENR1_RPIF13_Msk /*!< Privilege enable on line 13 */ -#define EXTI_PRIVENR1_RPIF14_Pos (14U) -#define EXTI_PRIVENR1_RPIF14_Msk (0x1UL << EXTI_PRIVENR1_RPIF14_Pos) /*!< 0x00004000 */ -#define EXTI_PRIVENR1_RPIF14 EXTI_PRIVENR1_RPIF14_Msk /*!< Privilege enable on line 14 */ -#define EXTI_PRIVENR1_RPIF15_Pos (15U) -#define EXTI_PRIVENR1_RPIF15_Msk (0x1UL << EXTI_PRIVENR1_RPIF15_Pos) /*!< 0x00008000 */ -#define EXTI_PRIVENR1_RPIF15 EXTI_PRIVENR1_RPIF15_Msk /*!< Privilege enable on line 15 */ -#define EXTI_PRIVENR1_RPIF16_Pos (16U) -#define EXTI_PRIVENR1_RPIF16_Msk (0x1UL << EXTI_PRIVENR1_RPIF16_Pos) /*!< 0x00010000 */ -#define EXTI_PRIVENR1_RPIF16 EXTI_PRIVENR1_RPIF16_Msk /*!< Privilege enable on line 16 */ -#define EXTI_PRIVENR1_RPIF17_Pos (17U) -#define EXTI_PRIVENR1_RPIF17_Msk (0x1UL << EXTI_PRIVENR1_RPIF17_Pos) /*!< 0x00020000 */ -#define EXTI_PRIVENR1_RPIF17 EXTI_PRIVENR1_RPIF17_Msk /*!< Privilege enable on line 17 */ -#define EXTI_PRIVENR1_RPIF18_Pos (18U) -#define EXTI_PRIVENR1_RPIF18_Msk (0x1UL << EXTI_PRIVENR1_RPIF18_Pos) /*!< 0x00040000 */ -#define EXTI_PRIVENR1_RPIF18 EXTI_PRIVENR1_RPIF18_Msk /*!< Privilege enable on line 18 */ -#define EXTI_PRIVENR1_RPIF19_Pos (19U) -#define EXTI_PRIVENR1_RPIF19_Msk (0x1UL << EXTI_PRIVENR1_RPIF19_Pos) /*!< 0x00080000 */ -#define EXTI_PRIVENR1_RPIF19 EXTI_PRIVENR1_RPIF19_Msk /*!< Privilege enable on line 19 */ -#define EXTI_PRIVENR1_RPIF20_Pos (20U) -#define EXTI_PRIVENR1_RPIF20_Msk (0x1UL << EXTI_PRIVENR1_RPIF20_Pos) /*!< 0x00100000 */ -#define EXTI_PRIVENR1_RPIF20 EXTI_PRIVENR1_RPIF20_Msk /*!< Privilege enable on line 20 */ -#define EXTI_PRIVENR1_RPIF21_Pos (21U) -#define EXTI_PRIVENR1_RPIF21_Msk (0x1UL << EXTI_PRIVENR1_RPIF21_Pos) /*!< 0x00200000 */ -#define EXTI_PRIVENR1_RPIF21 EXTI_PRIVENR1_RPIF21_Msk /*!< Privilege enable on line 21 */ -#define EXTI_PRIVENR1_RPIF22_Pos (22U) -#define EXTI_PRIVENR1_RPIF22_Msk (0x1UL << EXTI_PRIVENR1_RPIF22_Pos) /*!< 0x00400000 */ -#define EXTI_PRIVENR1_RPIF22 EXTI_PRIVENR1_RPIF22_Msk /*!< Privilege enable on line 22 */ -#define EXTI_PRIVENR1_RPIF23_Pos (23U) -#define EXTI_PRIVENR1_RPIF23_Msk (0x1UL << EXTI_PRIVENR1_RPIF23_Pos) /*!< 0x00800000 */ -#define EXTI_PRIVENR1_RPIF23 EXTI_PRIVENR1_RPIF23_Msk /*!< Privilege enable on line 23 */ -#define EXTI_PRIVENR1_RPIF24_Pos (24U) -#define EXTI_PRIVENR1_RPIF24_Msk (0x1UL << EXTI_PRIVENR1_RPIF24_Pos) /*!< 0x01000000 */ -#define EXTI_PRIVENR1_RPIF24 EXTI_PRIVENR1_RPIF24_Msk /*!< Privilege enable on line 24 */ + +/******************* Bit definition for EXTI_SECCFGR1 register ******************/ +#define EXTI_SECCFGR1_SEC0_Pos (0U) +#define EXTI_SECCFGR1_SEC0_Msk (0x1UL << EXTI_SECCFGR1_SEC0_Pos) /*!< 0x00000001 */ +#define EXTI_SECCFGR1_SEC0 EXTI_SECCFGR1_SEC0_Msk /*!< Security enable on line 0 */ +#define EXTI_SECCFGR1_SEC1_Pos (1U) +#define EXTI_SECCFGR1_SEC1_Msk (0x1UL << EXTI_SECCFGR1_SEC1_Pos) /*!< 0x00000002 */ +#define EXTI_SECCFGR1_SEC1 EXTI_SECCFGR1_SEC1_Msk /*!< Security enable on line 1 */ +#define EXTI_SECCFGR1_SEC2_Pos (2U) +#define EXTI_SECCFGR1_SEC2_Msk (0x1UL << EXTI_SECCFGR1_SEC2_Pos) /*!< 0x00000004 */ +#define EXTI_SECCFGR1_SEC2 EXTI_SECCFGR1_SEC2_Msk /*!< Security enable on line 2 */ +#define EXTI_SECCFGR1_SEC3_Pos (3U) +#define EXTI_SECCFGR1_SEC3_Msk (0x1UL << EXTI_SECCFGR1_SEC3_Pos) /*!< 0x00000008 */ +#define EXTI_SECCFGR1_SEC3 EXTI_SECCFGR1_SEC3_Msk /*!< Security enable on line 3 */ +#define EXTI_SECCFGR1_SEC4_Pos (4U) +#define EXTI_SECCFGR1_SEC4_Msk (0x1UL << EXTI_SECCFGR1_SEC4_Pos) /*!< 0x00000010 */ +#define EXTI_SECCFGR1_SEC4 EXTI_SECCFGR1_SEC4_Msk /*!< Security enable on line 4 */ +#define EXTI_SECCFGR1_SEC5_Pos (5U) +#define EXTI_SECCFGR1_SEC5_Msk (0x1UL << EXTI_SECCFGR1_SEC5_Pos) /*!< 0x00000020 */ +#define EXTI_SECCFGR1_SEC5 EXTI_SECCFGR1_SEC5_Msk /*!< Security enable on line 5 */ +#define EXTI_SECCFGR1_SEC6_Pos (6U) +#define EXTI_SECCFGR1_SEC6_Msk (0x1UL << EXTI_SECCFGR1_SEC6_Pos) /*!< 0x00000040 */ +#define EXTI_SECCFGR1_SEC6 EXTI_SECCFGR1_SEC6_Msk /*!< Security enable on line 6 */ +#define EXTI_SECCFGR1_SEC7_Pos (7U) +#define EXTI_SECCFGR1_SEC7_Msk (0x1UL << EXTI_SECCFGR1_SEC7_Pos) /*!< 0x00000080 */ +#define EXTI_SECCFGR1_SEC7 EXTI_SECCFGR1_SEC7_Msk /*!< Security enable on line 7 */ +#define EXTI_SECCFGR1_SEC8_Pos (8U) +#define EXTI_SECCFGR1_SEC8_Msk (0x1UL << EXTI_SECCFGR1_SEC8_Pos) /*!< 0x00000100 */ +#define EXTI_SECCFGR1_SEC8 EXTI_SECCFGR1_SEC8_Msk /*!< Security enable on line 8 */ +#define EXTI_SECCFGR1_SEC9_Pos (9U) +#define EXTI_SECCFGR1_SEC9_Msk (0x1UL << EXTI_SECCFGR1_SEC9_Pos) /*!< 0x00000200 */ +#define EXTI_SECCFGR1_SEC9 EXTI_SECCFGR1_SEC9_Msk /*!< Security enable on line 9 */ +#define EXTI_SECCFGR1_SEC10_Pos (10U) +#define EXTI_SECCFGR1_SEC10_Msk (0x1UL << EXTI_SECCFGR1_SEC10_Pos) /*!< 0x00000400 */ +#define EXTI_SECCFGR1_SEC10 EXTI_SECCFGR1_SEC10_Msk /*!< Security enable on line 10 */ +#define EXTI_SECCFGR1_SEC11_Pos (11U) +#define EXTI_SECCFGR1_SEC11_Msk (0x1UL << EXTI_SECCFGR1_SEC11_Pos) /*!< 0x00000800 */ +#define EXTI_SECCFGR1_SEC11 EXTI_SECCFGR1_SEC11_Msk /*!< Security enable on line 11 */ +#define EXTI_SECCFGR1_SEC12_Pos (12U) +#define EXTI_SECCFGR1_SEC12_Msk (0x1UL << EXTI_SECCFGR1_SEC12_Pos) /*!< 0x00001000 */ +#define EXTI_SECCFGR1_SEC12 EXTI_SECCFGR1_SEC12_Msk /*!< Security enable on line 12 */ +#define EXTI_SECCFGR1_SEC13_Pos (13U) +#define EXTI_SECCFGR1_SEC13_Msk (0x1UL << EXTI_SECCFGR1_SEC13_Pos) /*!< 0x00002000 */ +#define EXTI_SECCFGR1_SEC13 EXTI_SECCFGR1_SEC13_Msk /*!< Security enable on line 13 */ +#define EXTI_SECCFGR1_SEC14_Pos (14U) +#define EXTI_SECCFGR1_SEC14_Msk (0x1UL << EXTI_SECCFGR1_SEC14_Pos) /*!< 0x00004000 */ +#define EXTI_SECCFGR1_SEC14 EXTI_SECCFGR1_SEC14_Msk /*!< Security enable on line 14 */ +#define EXTI_SECCFGR1_SEC15_Pos (15U) +#define EXTI_SECCFGR1_SEC15_Msk (0x1UL << EXTI_SECCFGR1_SEC15_Pos) /*!< 0x00008000 */ +#define EXTI_SECCFGR1_SEC15 EXTI_SECCFGR1_SEC15_Msk /*!< Security enable on line 15 */ +#define EXTI_SECCFGR1_SEC16_Pos (16U) +#define EXTI_SECCFGR1_SEC16_Msk (0x1UL << EXTI_SECCFGR1_SEC16_Pos) /*!< 0x00010000 */ +#define EXTI_SECCFGR1_SEC16 EXTI_SECCFGR1_SEC16_Msk /*!< Security enable on line 16 */ +#define EXTI_SECCFGR1_SEC17_Pos (17U) +#define EXTI_SECCFGR1_SEC17_Msk (0x1UL << EXTI_SECCFGR1_SEC17_Pos) /*!< 0x00020000 */ +#define EXTI_SECCFGR1_SEC17 EXTI_SECCFGR1_SEC17_Msk /*!< Security enable on line 17 */ +#define EXTI_SECCFGR1_SEC18_Pos (18U) +#define EXTI_SECCFGR1_SEC18_Msk (0x1UL << EXTI_SECCFGR1_SEC18_Pos) /*!< 0x00040000 */ +#define EXTI_SECCFGR1_SEC18 EXTI_SECCFGR1_SEC18_Msk /*!< Security enable on line 18 */ +#define EXTI_SECCFGR1_SEC19_Pos (19U) +#define EXTI_SECCFGR1_SEC19_Msk (0x1UL << EXTI_SECCFGR1_SEC19_Pos) /*!< 0x00080000 */ +#define EXTI_SECCFGR1_SEC19 EXTI_SECCFGR1_SEC19_Msk /*!< Security enable on line 19 */ +#define EXTI_SECCFGR1_SEC20_Pos (20U) +#define EXTI_SECCFGR1_SEC20_Msk (0x1UL << EXTI_SECCFGR1_SEC20_Pos) /*!< 0x00100000 */ +#define EXTI_SECCFGR1_SEC20 EXTI_SECCFGR1_SEC20_Msk /*!< Security enable on line 20 */ +#define EXTI_SECCFGR1_SEC21_Pos (21U) +#define EXTI_SECCFGR1_SEC21_Msk (0x1UL << EXTI_SECCFGR1_SEC21_Pos) /*!< 0x00200000 */ +#define EXTI_SECCFGR1_SEC21 EXTI_SECCFGR1_SEC21_Msk /*!< Security enable on line 21 */ +#define EXTI_SECCFGR1_SEC22_Pos (22U) +#define EXTI_SECCFGR1_SEC22_Msk (0x1UL << EXTI_SECCFGR1_SEC22_Pos) /*!< 0x00400000 */ +#define EXTI_SECCFGR1_SEC22 EXTI_SECCFGR1_SEC22_Msk /*!< Security enable on line 22 */ +#define EXTI_SECCFGR1_SEC23_Pos (23U) +#define EXTI_SECCFGR1_SEC23_Msk (0x1UL << EXTI_SECCFGR1_SEC23_Pos) /*!< 0x00800000 */ +#define EXTI_SECCFGR1_SEC23 EXTI_SECCFGR1_SEC23_Msk /*!< Security enable on line 23 */ + +/******************* Bit definition for EXTI_PRIVCFGR1 register ******************/ +#define EXTI_PRIVCFGR1_PRIV0_Pos (0U) +#define EXTI_PRIVCFGR1_PRIV0_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR1_PRIV0 EXTI_PRIVCFGR1_PRIV0_Msk /*!< Privilege enable on line 0 */ +#define EXTI_PRIVCFGR1_PRIV1_Pos (1U) +#define EXTI_PRIVCFGR1_PRIV1_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR1_PRIV1 EXTI_PRIVCFGR1_PRIV1_Msk /*!< Privilege enable on line 1 */ +#define EXTI_PRIVCFGR1_PRIV2_Pos (2U) +#define EXTI_PRIVCFGR1_PRIV2_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR1_PRIV2 EXTI_PRIVCFGR1_PRIV2_Msk /*!< Privilege enable on line 2 */ +#define EXTI_PRIVCFGR1_PRIV3_Pos (3U) +#define EXTI_PRIVCFGR1_PRIV3_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR1_PRIV3 EXTI_PRIVCFGR1_PRIV3_Msk /*!< Privilege enable on line 3 */ +#define EXTI_PRIVCFGR1_PRIV4_Pos (4U) +#define EXTI_PRIVCFGR1_PRIV4_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */ +#define EXTI_PRIVCFGR1_PRIV4 EXTI_PRIVCFGR1_PRIV4_Msk /*!< Privilege enable on line 4 */ +#define EXTI_PRIVCFGR1_PRIV5_Pos (5U) +#define EXTI_PRIVCFGR1_PRIV5_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */ +#define EXTI_PRIVCFGR1_PRIV5 EXTI_PRIVCFGR1_PRIV5_Msk /*!< Privilege enable on line 5 */ +#define EXTI_PRIVCFGR1_PRIV6_Pos (6U) +#define EXTI_PRIVCFGR1_PRIV6_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */ +#define EXTI_PRIVCFGR1_PRIV6 EXTI_PRIVCFGR1_PRIV6_Msk /*!< Privilege enable on line 6 */ +#define EXTI_PRIVCFGR1_PRIV7_Pos (7U) +#define EXTI_PRIVCFGR1_PRIV7_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */ +#define EXTI_PRIVCFGR1_PRIV7 EXTI_PRIVCFGR1_PRIV7_Msk /*!< Privilege enable on line 7 */ +#define EXTI_PRIVCFGR1_PRIV8_Pos (8U) +#define EXTI_PRIVCFGR1_PRIV8_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */ +#define EXTI_PRIVCFGR1_PRIV8 EXTI_PRIVCFGR1_PRIV8_Msk /*!< Privilege enable on line 8 */ +#define EXTI_PRIVCFGR1_PRIV9_Pos (9U) +#define EXTI_PRIVCFGR1_PRIV9_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */ +#define EXTI_PRIVCFGR1_PRIV9 EXTI_PRIVCFGR1_PRIV9_Msk /*!< Privilege enable on line 9 */ +#define EXTI_PRIVCFGR1_PRIV10_Pos (10U) +#define EXTI_PRIVCFGR1_PRIV10_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */ +#define EXTI_PRIVCFGR1_PRIV10 EXTI_PRIVCFGR1_PRIV10_Msk /*!< Privilege enable on line 10 */ +#define EXTI_PRIVCFGR1_PRIV11_Pos (11U) +#define EXTI_PRIVCFGR1_PRIV11_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */ +#define EXTI_PRIVCFGR1_PRIV11 EXTI_PRIVCFGR1_PRIV11_Msk /*!< Privilege enable on line 11 */ +#define EXTI_PRIVCFGR1_PRIV12_Pos (12U) +#define EXTI_PRIVCFGR1_PRIV12_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */ +#define EXTI_PRIVCFGR1_PRIV12 EXTI_PRIVCFGR1_PRIV12_Msk /*!< Privilege enable on line 12 */ +#define EXTI_PRIVCFGR1_PRIV13_Pos (13U) +#define EXTI_PRIVCFGR1_PRIV13_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */ +#define EXTI_PRIVCFGR1_PRIV13 EXTI_PRIVCFGR1_PRIV13_Msk /*!< Privilege enable on line 13 */ +#define EXTI_PRIVCFGR1_PRIV14_Pos (14U) +#define EXTI_PRIVCFGR1_PRIV14_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */ +#define EXTI_PRIVCFGR1_PRIV14 EXTI_PRIVCFGR1_PRIV14_Msk /*!< Privilege enable on line 14 */ +#define EXTI_PRIVCFGR1_PRIV15_Pos (15U) +#define EXTI_PRIVCFGR1_PRIV15_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */ +#define EXTI_PRIVCFGR1_PRIV15 EXTI_PRIVCFGR1_PRIV15_Msk /*!< Privilege enable on line 15 */ +#define EXTI_PRIVCFGR1_PRIV16_Pos (16U) +#define EXTI_PRIVCFGR1_PRIV16_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV16_Pos) /*!< 0x00010000 */ +#define EXTI_PRIVCFGR1_PRIV16 EXTI_PRIVCFGR1_PRIV16_Msk /*!< Privilege enable on line 16 */ +#define EXTI_PRIVCFGR1_PRIV17_Pos (17U) +#define EXTI_PRIVCFGR1_PRIV17_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */ +#define EXTI_PRIVCFGR1_PRIV17 EXTI_PRIVCFGR1_PRIV17_Msk /*!< Privilege enable on line 17 */ +#define EXTI_PRIVCFGR1_PRIV18_Pos (18U) +#define EXTI_PRIVCFGR1_PRIV18_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */ +#define EXTI_PRIVCFGR1_PRIV18 EXTI_PRIVCFGR1_PRIV18_Msk /*!< Privilege enable on line 18 */ +#define EXTI_PRIVCFGR1_PRIV19_Pos (19U) +#define EXTI_PRIVCFGR1_PRIV19_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV19_Pos) /*!< 0x00080000 */ +#define EXTI_PRIVCFGR1_PRIV19 EXTI_PRIVCFGR1_PRIV19_Msk /*!< Privilege enable on line 19 */ +#define EXTI_PRIVCFGR1_PRIV20_Pos (20U) +#define EXTI_PRIVCFGR1_PRIV20_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV20_Pos) /*!< 0x00100000 */ +#define EXTI_PRIVCFGR1_PRIV20 EXTI_PRIVCFGR1_PRIV20_Msk /*!< Privilege enable on line 20 */ +#define EXTI_PRIVCFGR1_PRIV21_Pos (21U) +#define EXTI_PRIVCFGR1_PRIV21_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV21_Pos) /*!< 0x00200000 */ +#define EXTI_PRIVCFGR1_PRIV21 EXTI_PRIVCFGR1_PRIV21_Msk /*!< Privilege enable on line 21 */ +#define EXTI_PRIVCFGR1_PRIV22_Pos (22U) +#define EXTI_PRIVCFGR1_PRIV22_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV22_Pos) /*!< 0x00400000 */ +#define EXTI_PRIVCFGR1_PRIV22 EXTI_PRIVCFGR1_PRIV22_Msk /*!< Privilege enable on line 22 */ +#define EXTI_PRIVCFGR1_PRIV23_Pos (23U) +#define EXTI_PRIVCFGR1_PRIV23_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV23_Pos) /*!< 0x00800000 */ +#define EXTI_PRIVCFGR1_PRIV23 EXTI_PRIVCFGR1_PRIV23_Msk /*!< Privilege enable on line 23 */ /***************** Bit definition for EXTI_EXTICR1 register **************/ #define EXTI_EXTICR1_EXTI0_Pos (0U) @@ -7398,6 +7384,11 @@ typedef struct #define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ #define EXTI_EXTICR4_EXTI15_3 (0x8UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x08000000 */ +/***************** Bit definition for EXTI_LOCKR register **************/ +#define EXTI_LOCKR_LOCK_Pos (0U) +#define EXTI_LOCKR_LOCK_Msk (0x1UL << EXTI_LOCKR_LOCK_Pos) /*!< 0x00000001 */ +#define EXTI_LOCKR_LOCK EXTI_LOCKR_LOCK_Msk /*!< Global security and privilege configuration registers lock */ + /******************* Bit definition for EXTI_IMR1 register ******************/ #define EXTI_IMR1_IM0_Pos (0U) #define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ @@ -7471,9 +7462,6 @@ typedef struct #define EXTI_IMR1_IM23_Pos (23U) #define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */ -#define EXTI_IMR1_IM24_Pos (24U) -#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ -#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */ /******************* Bit definition for EXTI_EMR1 register ******************/ #define EXTI_EMR1_EM0_Pos (0U) @@ -7548,10 +7536,6 @@ typedef struct #define EXTI_EMR1_EM23_Pos (23U) #define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */ -#define EXTI_EMR1_EM24_Pos (24U) -#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */ -#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */ - /******************************************************************************/ /* */ @@ -8131,19 +8115,19 @@ typedef struct #define FDCAN_CKDIV_PDIV_Msk (0xFUL << FDCAN_CKDIV_PDIV_Pos) /*!< 0x0000000F */ #define FDCAN_CKDIV_PDIV FDCAN_CKDIV_PDIV_Msk /*!> 1U) @@ -8398,9 +8382,9 @@ typedef struct #define FLASH_OPTR_nRST_SHDW_Pos (14U) #define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ #define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ -#define FLASH_OPTR_SRAM134_RST_Pos (15U) -#define FLASH_OPTR_SRAM134_RST_Msk (0x1UL << FLASH_OPTR_SRAM134_RST_Pos) /*!< 0x00008000 */ -#define FLASH_OPTR_SRAM134_RST FLASH_OPTR_SRAM134_RST_Msk /*!< SRAM1, SRAM3 and SRAM4 erase upon system reset */ +#define FLASH_OPTR_SRAM_RST_Pos (15U) +#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ #define FLASH_OPTR_IWDG_SW_Pos (16U) #define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ @@ -8560,7 +8544,6 @@ typedef struct #define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ #define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ - /******************************************************************************/ /* */ /* Filter Mathematical ACcelerator unit (FMAC) */ @@ -8676,7 +8659,6 @@ typedef struct #define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ #define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ - /******************************************************************************/ /* */ /* Flexible Memory Controller */ @@ -9027,7 +9009,6 @@ typedef struct #define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */ #define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ #define RTC_ALRMAR_SU_Pos (0U) @@ -17372,11 +17805,12 @@ typedef struct #define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ #define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ #define TAMP_ATCR1_ATCKSEL_Pos (16U) -#define TAMP_ATCR1_ATCKSEL_Msk (0x7UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00070000 */ +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ #define TAMP_ATCR1_ATPER_Pos (24U) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk @@ -18839,7 +19273,6 @@ typedef struct #define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */ #define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */ - /******************************************************************************/ /* */ /* SYSCFG */ @@ -18898,7 +19331,7 @@ typedef struct /****************** Bit definition for SYSCFG_CSLCKR register ***************/ #define SYSCFG_CSLCKR_LOCKSVTAIRCR_Pos (0U) #define SYSCFG_CSLCKR_LOCKSVTAIRCR_Msk (0x1UL << SYSCFG_CSLCKR_LOCKSVTAIRCR_Pos) /*!< 0x00000001 */ -#define SYSCFG_CSLCKR_LOCKSVTAIRCR SYSCFG_CSLCKR_LOCKSVTAIRCR_Msk /*!< Disable changes to the secure vectror table address, handling of system faults */ +#define SYSCFG_CSLCKR_LOCKSVTAIRCR SYSCFG_CSLCKR_LOCKSVTAIRCR_Msk /*!< Disable changes to the secure vector table address, handling of system faults */ #define SYSCFG_CSLCKR_LOCKSMPU_Pos (1U) #define SYSCFG_CSLCKR_LOCKSMPU_Msk (0x1UL << SYSCFG_CSLCKR_LOCKSMPU_Pos) /*!< 0x00000002 */ #define SYSCFG_CSLCKR_LOCKSMPU SYSCFG_CSLCKR_LOCKSMPU_Msk /*!< Disable changes to the secure MPU registers writes by SW or debug agent */ @@ -18989,7 +19422,6 @@ typedef struct #define SYSCFG_UCPD_CC2ENRXFILTER_Msk (0x1UL << SYSCFG_UCPD_CC2ENRXFILTER_Pos) /*!< 0x0000002 */ #define SYSCFG_UCPD_CC2ENRXFILTER SYSCFG_UCPD_CC2ENRXFILTER_Msk /*!< USB PD BMC receiver 2 low-power analog filter */ - /*****************************************************************************/ /* */ /* Global TrustZone Control */ @@ -19024,7 +19456,7 @@ typedef struct /******* Bits definition for TZSC _SECCFGRx/_PRIVCFGRx registers *****/ /******* Bits definition for TZIC _IERx/_SRx/_IFCRx registers ********/ -/*************** Bits definition for register x=1 (TZSC1) *************/ +/*************** Bits definition for register x=1 (GTZC1) *************/ #define GTZC_CFGR1_TIM2_Pos (0U) #define GTZC_CFGR1_TIM2_Msk (0x01UL << GTZC_CFGR1_TIM2_Pos) #define GTZC_CFGR1_TIM3_Pos (1U) @@ -19066,7 +19498,7 @@ typedef struct #define GTZC_CFGR1_UCPD1_Pos (19U) #define GTZC_CFGR1_UCPD1_Msk (0x01UL << GTZC_CFGR1_UCPD1_Pos) -/*************** Bits definition for register x=2 (TZSC1) *************/ +/*************** Bits definition for register x=2 (GTZC1) *************/ #define GTZC_CFGR2_TIM1_Pos (0U) #define GTZC_CFGR2_TIM1_Msk (0x01UL << GTZC_CFGR2_TIM1_Pos) #define GTZC_CFGR2_SPI1_Pos (1U) @@ -19086,7 +19518,7 @@ typedef struct #define GTZC_CFGR2_SAI2_Pos (8U) #define GTZC_CFGR2_SAI2_Msk (0x01UL << GTZC_CFGR2_SAI2_Pos) -/*************** Bits definition for register x=3 (TZSC1) *************/ +/*************** Bits definition for register x=3 (GTZC1) *************/ #define GTZC_CFGR3_MDF1_Pos (0U) #define GTZC_CFGR3_MDF1_Msk (0x01UL << GTZC_CFGR3_MDF1_Pos) #define GTZC_CFGR3_CORDIC_Pos (1U) @@ -19134,7 +19566,7 @@ typedef struct #define GTZC_CFGR3_RAMCFG_Pos (22U) #define GTZC_CFGR3_RAMCFG_Msk (0x01UL << GTZC_CFGR3_RAMCFG_Pos) -/*************** Bits definition for register x=4 (TZSC1) *************/ +/*************** Bits definition for register x=4 (GTZC1) *************/ #define GTZC_CFGR4_GPDMA1_Pos (0U) #define GTZC_CFGR4_GPDMA1_Msk (0x01UL << GTZC_CFGR4_GPDMA1_Pos) #define GTZC_CFGR4_FLASH_REG_Pos (1U) @@ -19170,7 +19602,7 @@ typedef struct #define GTZC_CFGR4_MPCBB3_REG_Pos (29U) #define GTZC_CFGR4_MPCBB3_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB3_REG_Pos) -/*************** Bits definition for register x=1 (TZSC2) *************/ +/*************** Bits definition for register x=1 (GTZC2) *************/ #define GTZC_CFGR1_SPI3_Pos (0U) #define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos) #define GTZC_CFGR1_LPUART1_Pos (1U) @@ -19196,7 +19628,7 @@ typedef struct #define GTZC_CFGR1_ADF1_Pos (12U) #define GTZC_CFGR1_ADF1_Msk (0x01UL << GTZC_CFGR1_ADF1_Pos) -/*************** Bits definition for register x=2 (TZSC2) *************/ +/*************** Bits definition for register x=2 (GTZC2) *************/ #define GTZC_CFGR2_SYSCFG_Pos (0U) #define GTZC_CFGR2_SYSCFG_Msk (0x01UL << GTZC_CFGR2_SYSCFG_Pos) #define GTZC_CFGR2_RTC_Pos (1U) @@ -20231,6 +20663,20 @@ typedef struct #define UCPD_CFG2_RXAFILTEN_Msk (0x1UL << UCPD_CFG2_RXAFILTEN_Pos) /*!< 0x00000100 */ #define UCPD_CFG2_RXAFILTEN UCPD_CFG2_RXAFILTEN_Msk /*!< RX Analog Filter enable */ +/******************** Bits definition for UCPD_CFG3 register *******************/ +#define UCPD_CFG3_TRIM_CC1_RD_Pos (0U) +#define UCPD_CFG3_TRIM_CC1_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RD_Pos) /*!< 0x0000000F */ +#define UCPD_CFG3_TRIM_CC1_RD UCPD_CFG3_TRIM_CC1_RD_Msk /*!< SW trim value for RD resistor (CC1) */ +#define UCPD_CFG3_TRIM_CC1_RP_Pos (9U) +#define UCPD_CFG3_TRIM_CC1_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RP_Pos) /*!< 0x00001E00 */ +#define UCPD_CFG3_TRIM_CC1_RP UCPD_CFG3_TRIM_CC1_RP_Msk /*!< SW trim value for RP current sources (CC1) */ +#define UCPD_CFG3_TRIM_CC2_RD_Pos (16U) +#define UCPD_CFG3_TRIM_CC2_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RD_Pos) /*!< 0x000F0000 */ +#define UCPD_CFG3_TRIM_CC2_RD UCPD_CFG3_TRIM_CC2_RD_Msk /*!< SW trim value for RD resistor (CC2) */ +#define UCPD_CFG3_TRIM_CC2_RP_Pos (25U) +#define UCPD_CFG3_TRIM_CC2_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RP_Pos) /*!< 0x1E000000 */ +#define UCPD_CFG3_TRIM_CC2_RP UCPD_CFG3_TRIM_CC2_RP_Msk /*!< SW trim value for RP current sources (CC2) */ + /******************** Bits definition for UCPD_CR register ********************/ #define UCPD_CR_TXMODE_Pos (0U) #define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */ @@ -21214,16 +21660,16 @@ typedef struct #define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */ #define USB_OTG_GCCFG_DCDEN_Pos (18U) #define USB_OTG_GCCFG_DCDEN_Msk (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */ -#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/ +#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable */ #define USB_OTG_GCCFG_PDEN_Pos (19U) #define USB_OTG_GCCFG_PDEN_Msk (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */ -#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/ +#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable */ #define USB_OTG_GCCFG_SDEN_Pos (20U) #define USB_OTG_GCCFG_SDEN_Msk (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */ #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */ #define USB_OTG_GCCFG_VBDEN_Pos (21U) #define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */ -#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */ +#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Vbus detection enable */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -21243,7 +21689,6 @@ typedef struct #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */ - /******************** Bit definition for USB_OTG_GHWCFG3 register ********************/ #define USB_OTG_GHWCFG3_LPMMode_Pos (14U) #define USB_OTG_GHWCFG3_LPMMode_Msk (0x1U << USB_OTG_GHWCFG3_LPMMode_Pos) /*!< 0x00004000 */ @@ -21795,12 +22240,12 @@ typedef struct #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */ #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!> 1U) @@ -8838,9 +8831,9 @@ typedef struct #define FLASH_OPTR_nRST_SHDW_Pos (14U) #define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ #define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ -#define FLASH_OPTR_SRAM134_RST_Pos (15U) -#define FLASH_OPTR_SRAM134_RST_Msk (0x1UL << FLASH_OPTR_SRAM134_RST_Pos) /*!< 0x00008000 */ -#define FLASH_OPTR_SRAM134_RST FLASH_OPTR_SRAM134_RST_Msk /*!< SRAM1, SRAM3 and SRAM4 erase upon system reset */ +#define FLASH_OPTR_SRAM_RST_Pos (15U) +#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ #define FLASH_OPTR_IWDG_SW_Pos (16U) #define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ @@ -9000,7 +8993,6 @@ typedef struct #define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ #define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ - /******************************************************************************/ /* */ /* Filter Mathematical ACcelerator unit (FMAC) */ @@ -9116,7 +9108,6 @@ typedef struct #define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ #define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ - /******************************************************************************/ /* */ /* Flexible Memory Controller */ @@ -9467,7 +9458,6 @@ typedef struct #define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */ #define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ #define RTC_ALRMAR_SU_Pos (0U) @@ -17922,11 +18364,12 @@ typedef struct #define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ #define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ #define TAMP_ATCR1_ATCKSEL_Pos (16U) -#define TAMP_ATCR1_ATCKSEL_Msk (0x7UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00070000 */ +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ #define TAMP_ATCR1_ATPER_Pos (24U) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk @@ -19389,7 +19832,6 @@ typedef struct #define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */ #define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */ - /******************************************************************************/ /* */ /* SYSCFG */ @@ -19448,7 +19890,7 @@ typedef struct /****************** Bit definition for SYSCFG_CSLCKR register ***************/ #define SYSCFG_CSLCKR_LOCKSVTAIRCR_Pos (0U) #define SYSCFG_CSLCKR_LOCKSVTAIRCR_Msk (0x1UL << SYSCFG_CSLCKR_LOCKSVTAIRCR_Pos) /*!< 0x00000001 */ -#define SYSCFG_CSLCKR_LOCKSVTAIRCR SYSCFG_CSLCKR_LOCKSVTAIRCR_Msk /*!< Disable changes to the secure vectror table address, handling of system faults */ +#define SYSCFG_CSLCKR_LOCKSVTAIRCR SYSCFG_CSLCKR_LOCKSVTAIRCR_Msk /*!< Disable changes to the secure vector table address, handling of system faults */ #define SYSCFG_CSLCKR_LOCKSMPU_Pos (1U) #define SYSCFG_CSLCKR_LOCKSMPU_Msk (0x1UL << SYSCFG_CSLCKR_LOCKSMPU_Pos) /*!< 0x00000002 */ #define SYSCFG_CSLCKR_LOCKSMPU SYSCFG_CSLCKR_LOCKSMPU_Msk /*!< Disable changes to the secure MPU registers writes by SW or debug agent */ @@ -19539,7 +19981,6 @@ typedef struct #define SYSCFG_UCPD_CC2ENRXFILTER_Msk (0x1UL << SYSCFG_UCPD_CC2ENRXFILTER_Pos) /*!< 0x0000002 */ #define SYSCFG_UCPD_CC2ENRXFILTER SYSCFG_UCPD_CC2ENRXFILTER_Msk /*!< USB PD BMC receiver 2 low-power analog filter */ - /*****************************************************************************/ /* */ /* Global TrustZone Control */ @@ -19574,7 +20015,7 @@ typedef struct /******* Bits definition for TZSC _SECCFGRx/_PRIVCFGRx registers *****/ /******* Bits definition for TZIC _IERx/_SRx/_IFCRx registers ********/ -/*************** Bits definition for register x=1 (TZSC1) *************/ +/*************** Bits definition for register x=1 (GTZC1) *************/ #define GTZC_CFGR1_TIM2_Pos (0U) #define GTZC_CFGR1_TIM2_Msk (0x01UL << GTZC_CFGR1_TIM2_Pos) #define GTZC_CFGR1_TIM3_Pos (1U) @@ -19616,7 +20057,7 @@ typedef struct #define GTZC_CFGR1_UCPD1_Pos (19U) #define GTZC_CFGR1_UCPD1_Msk (0x01UL << GTZC_CFGR1_UCPD1_Pos) -/*************** Bits definition for register x=2 (TZSC1) *************/ +/*************** Bits definition for register x=2 (GTZC1) *************/ #define GTZC_CFGR2_TIM1_Pos (0U) #define GTZC_CFGR2_TIM1_Msk (0x01UL << GTZC_CFGR2_TIM1_Pos) #define GTZC_CFGR2_SPI1_Pos (1U) @@ -19636,7 +20077,7 @@ typedef struct #define GTZC_CFGR2_SAI2_Pos (8U) #define GTZC_CFGR2_SAI2_Msk (0x01UL << GTZC_CFGR2_SAI2_Pos) -/*************** Bits definition for register x=3 (TZSC1) *************/ +/*************** Bits definition for register x=3 (GTZC1) *************/ #define GTZC_CFGR3_MDF1_Pos (0U) #define GTZC_CFGR3_MDF1_Msk (0x01UL << GTZC_CFGR3_MDF1_Pos) #define GTZC_CFGR3_CORDIC_Pos (1U) @@ -19684,7 +20125,7 @@ typedef struct #define GTZC_CFGR3_RAMCFG_Pos (22U) #define GTZC_CFGR3_RAMCFG_Msk (0x01UL << GTZC_CFGR3_RAMCFG_Pos) -/*************** Bits definition for register x=4 (TZSC1) *************/ +/*************** Bits definition for register x=4 (GTZC1) *************/ #define GTZC_CFGR4_GPDMA1_Pos (0U) #define GTZC_CFGR4_GPDMA1_Msk (0x01UL << GTZC_CFGR4_GPDMA1_Pos) #define GTZC_CFGR4_FLASH_REG_Pos (1U) @@ -19720,7 +20161,7 @@ typedef struct #define GTZC_CFGR4_MPCBB3_REG_Pos (29U) #define GTZC_CFGR4_MPCBB3_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB3_REG_Pos) -/*************** Bits definition for register x=1 (TZSC2) *************/ +/*************** Bits definition for register x=1 (GTZC2) *************/ #define GTZC_CFGR1_SPI3_Pos (0U) #define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos) #define GTZC_CFGR1_LPUART1_Pos (1U) @@ -19746,7 +20187,7 @@ typedef struct #define GTZC_CFGR1_ADF1_Pos (12U) #define GTZC_CFGR1_ADF1_Msk (0x01UL << GTZC_CFGR1_ADF1_Pos) -/*************** Bits definition for register x=2 (TZSC2) *************/ +/*************** Bits definition for register x=2 (GTZC2) *************/ #define GTZC_CFGR2_SYSCFG_Pos (0U) #define GTZC_CFGR2_SYSCFG_Msk (0x01UL << GTZC_CFGR2_SYSCFG_Pos) #define GTZC_CFGR2_RTC_Pos (1U) @@ -20781,6 +21222,20 @@ typedef struct #define UCPD_CFG2_RXAFILTEN_Msk (0x1UL << UCPD_CFG2_RXAFILTEN_Pos) /*!< 0x00000100 */ #define UCPD_CFG2_RXAFILTEN UCPD_CFG2_RXAFILTEN_Msk /*!< RX Analog Filter enable */ +/******************** Bits definition for UCPD_CFG3 register *******************/ +#define UCPD_CFG3_TRIM_CC1_RD_Pos (0U) +#define UCPD_CFG3_TRIM_CC1_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RD_Pos) /*!< 0x0000000F */ +#define UCPD_CFG3_TRIM_CC1_RD UCPD_CFG3_TRIM_CC1_RD_Msk /*!< SW trim value for RD resistor (CC1) */ +#define UCPD_CFG3_TRIM_CC1_RP_Pos (9U) +#define UCPD_CFG3_TRIM_CC1_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RP_Pos) /*!< 0x00001E00 */ +#define UCPD_CFG3_TRIM_CC1_RP UCPD_CFG3_TRIM_CC1_RP_Msk /*!< SW trim value for RP current sources (CC1) */ +#define UCPD_CFG3_TRIM_CC2_RD_Pos (16U) +#define UCPD_CFG3_TRIM_CC2_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RD_Pos) /*!< 0x000F0000 */ +#define UCPD_CFG3_TRIM_CC2_RD UCPD_CFG3_TRIM_CC2_RD_Msk /*!< SW trim value for RD resistor (CC2) */ +#define UCPD_CFG3_TRIM_CC2_RP_Pos (25U) +#define UCPD_CFG3_TRIM_CC2_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RP_Pos) /*!< 0x1E000000 */ +#define UCPD_CFG3_TRIM_CC2_RP UCPD_CFG3_TRIM_CC2_RP_Msk /*!< SW trim value for RP current sources (CC2) */ + /******************** Bits definition for UCPD_CR register ********************/ #define UCPD_CR_TXMODE_Pos (0U) #define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */ @@ -21764,16 +22219,16 @@ typedef struct #define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */ #define USB_OTG_GCCFG_DCDEN_Pos (18U) #define USB_OTG_GCCFG_DCDEN_Msk (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */ -#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/ +#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable */ #define USB_OTG_GCCFG_PDEN_Pos (19U) #define USB_OTG_GCCFG_PDEN_Msk (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */ -#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/ +#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable */ #define USB_OTG_GCCFG_SDEN_Pos (20U) #define USB_OTG_GCCFG_SDEN_Msk (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */ #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */ #define USB_OTG_GCCFG_VBDEN_Pos (21U) #define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */ -#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */ +#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Vbus detection enable */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -21793,7 +22248,6 @@ typedef struct #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */ - /******************** Bit definition for USB_OTG_GHWCFG3 register ********************/ #define USB_OTG_GHWCFG3_LPMMode_Pos (14U) #define USB_OTG_GHWCFG3_LPMMode_Msk (0x1U << USB_OTG_GHWCFG3_LPMMode_Pos) /*!< 0x00004000 */ @@ -22345,12 +22799,12 @@ typedef struct #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */ #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32u5xx.h" /*!< STM32U5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ + uint32_t RESERVED3[246]; /*!< Reserved, */ + __IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */ + __IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; +} I2C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, 0x24 */ + __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FC */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FC */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFC */ +} DMA2D_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ + __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */ + __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */ + __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */ + __IO uint32_t SECBB1R5; /*!< FLASH secure block-based bank 1 register 5, Address offset: 0x90 */ + __IO uint32_t SECBB1R6; /*!< FLASH secure block-based bank 1 register 6, Address offset: 0x94 */ + __IO uint32_t SECBB1R7; /*!< FLASH secure block-based bank 1 register 7, Address offset: 0x98 */ + __IO uint32_t SECBB1R8; /*!< FLASH secure block-based bank 1 register 8, Address offset: 0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */ + __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */ + __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */ + __IO uint32_t SECBB2R5; /*!< FLASH secure block-based bank 2 register 5, Address offset: 0xB0 */ + __IO uint32_t SECBB2R6; /*!< FLASH secure block-based bank 2 register 6, Address offset: 0xB4 */ + __IO uint32_t SECBB2R7; /*!< FLASH secure block-based bank 2 register 7, Address offset: 0xB8 */ + __IO uint32_t SECBB2R8; /*!< FLASH secure block-based bank 2 register 8, Address offset: 0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */ + __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */ + __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */ + __IO uint32_t PRIVBB1R5; /*!< FLASH privilege block-based bank 1 register 5, Address offset: 0xE0 */ + __IO uint32_t PRIVBB1R6; /*!< FLASH privilege block-based bank 1 register 6, Address offset: 0xE4 */ + __IO uint32_t PRIVBB1R7; /*!< FLASH privilege block-based bank 1 register 7, Address offset: 0xE8 */ + __IO uint32_t PRIVBB1R8; /*!< FLASH privilege block-based bank 1 register 8, Address offset: 0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */ + __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */ + __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */ + __IO uint32_t PRIVBB2R5; /*!< FLASH privilege block-based bank 2 register 5, Address offset: 0x100 */ + __IO uint32_t PRIVBB2R6; /*!< FLASH privilege block-based bank 2 register 6, Address offset: 0x104 */ + __IO uint32_t PRIVBB2R7; /*!< FLASH privilege block-based bank 2 register 7, Address offset: 0x108 */ + __IO uint32_t PRIVBB2R8; /*!< FLASH privilege block-based bank 2 register 8, Address offset: 0x10C */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */ + __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */ + __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */ + __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */ + __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */ + __IO uint32_t MPCWM6ACFGR; /*!< TZSC memory 6 sub-region A watermark configuration register, Address offset: 0x90 */ + __IO uint32_t MPCWM6AR; /*!< TZSC memory 6 sub-region A watermark register, Address offset: 0x94 */ + __IO uint32_t MPCWM6BCFGR; /*!< TZSC memory 6 sub-region B watermark configuration register, Address offset: 0x98 */ + __IO uint32_t MPCWM6BR; /*!< TZSC memory 6 sub-region B watermark register, Address offset: 0x9C */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register 1, Address offset: 0x10 */ + __IO uint32_t CFGLOCKR2; /*!< MPCBBx Configuration lock register 2, Address offset: 0x14 */ + uint32_t RESERVED2[58]; /*!< Reserved2, Address offset: 0x18-0xFC */ + __IO uint32_t SECCFGR[52]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x1CC */ + uint32_t RESERVED3[12]; /*!< Reserved3, Address offset: 0x1D0-0x1FC */ + __IO uint32_t PRIVCFGR[52]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x2CC */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ + uint32_t RESERVED2[240]; /*!< Reserved, Address offset: 0x30-0x3EC */ + __IO uint32_t HWCFGR; /*!< ICACHE HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< ICACHE version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ICACHE IP identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ICACHE size identification register, Address offset: 0x3FC */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + + +/** + * @brief MDF/ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ +}MDF_TypeDef; + +/** + * @brief MDF/ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ + __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ + __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ + __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ + __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief HEXA and OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ + uint32_t RESERVED22[3]; /*!< Reserved, Address offset: 0x204-0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-cycle calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x210 */ + uint32_t RESERVED23; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL master calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x218 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI slave output calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x220 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI slave input calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x228 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + +typedef XSPI_TypeDef HSPI_TypeDef; + + +/** + * @brief Serial Peripheral Interface IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPIM IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[8]; /*!< OCTOSPIM IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ +} XSPIM_TypeDef; + +typedef XSPIM_TypeDef OCTOSPIM_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x20 */ + __IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Power USB Type-C and Power Delivery register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + __IO uint32_t BDSR; /*!< Power backup domain status register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */ + __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ + __IO uint32_t PUCRI; /*!< Power Port I pull-up control register, Address offset: 0x90 */ + __IO uint32_t PDCRI; /*!< Power Port I pull-down control register, Address offset: 0x94 */ + __IO uint32_t PUCRJ; /*!< Power Port J pull-up control register, Address offset: 0x98 */ + __IO uint32_t PDCRJ; /*!< Power Port J pull-down control register, Address offset: 0x9C */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x0A0-0x0A4 */ + __IO uint32_t CR4; /*!< Power power control register 4, Address offset: 0xA8 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */ + __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */ + __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */ + __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */ + __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */ + __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */ + __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */ + __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */ + __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */ + __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */ + __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */ + uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + uint32_t RESERVED2[17];/*!< RESERVED2, Address offset: 0x30 - 0x70 */ + __IO uint32_t OTGHSPHYCR; /*!< SYSCFG USB OTG_HS PHY register Address offset: 0x74 */ + uint32_t RESERVED3; /*!< RESERVED3, Address offset: 0x78 */ + __IO uint32_t OTGHSPHYTUNER2;/*!< SYSCFG USB OTG_HS PHY tune register 2 Address offset: 0x7C */ +} SYSCFG_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief Flexible Memory Controller + */ +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief ADC + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ /* Specific to ADC 14Bits*/ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t AWD1TR; /*!< ADC watchdog threshold register, Address offset: 0x20 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ /* Specific to ADC 12Bits*/ + __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x2C */ /* Specific to ADC 12Bits*/ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ /* Specific to ADC 14Bits*/ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ + uint32_t RESERVED1; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ /* Specific to ADC 14Bits*/ + __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED3[3]; /*!< Reserved, 0x074 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED4[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0xA8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0xAC */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ /* Specific to ADC 14Bits*/ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED5; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0xD0 */ /* Specific to ADC 12Bits*/ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode, Address offset: 0x310 */ +} ADC_Common_TypeDef; + + +/* Legacy registers naming */ +#define PW PWRR + +/** + * @brief CORDIC + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief Touch Sensing Controller (TSC) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ +} TSC_TypeDef; + +/** + * @brief WWDG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32U5xx_peripherals */ + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0xC0000UL) /*!< SRAM1=768k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ +#define SRAM3_SIZE (0xD0000UL) /*!< SRAM3=832k */ +#define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */ +#define SRAM5_SIZE (0xD0000UL) /*!< SRAM5=832k */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< OCTOSPI2 memories accessible over AHB base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ +#define HSPI1_BASE (0xA0000000UL) /*!< HSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (4 MB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (768 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x200C0000UL) /*!< SRAM2 (64 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x200D0000UL) /*!< SRAM3 (832 KB) non-secure base address */ +#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */ +#define SRAM5_BASE_NS (0x201A0000UL) /*!< SRAM5 (832 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define I2C5_BASE_NS (APB1PERIPH_BASE_NS + 0x9800UL) +#define I2C6_BASE_NS (APB1PERIPH_BASE_NS + 0x9C00UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) +#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) +#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x004UL) +#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x024UL) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) +#define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP2_BASE_NS (APB3PERIPH_BASE_NS + 0x5010UL) +#define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define RAMCFG_SRAM5_BASE_NS (RAMCFG_BASE_NS + 0x0140UL) +#define DMA2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0B000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define GTZC_MPCBB5_BASE_NS (AHB1PERIPH_BASE_NS + 0x13800UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define GPIOI_BASE_NS (AHB2PERIPH_BASE_NS + 0x02000UL) +#define GPIOJ_BASE_NS (AHB2PERIPH_BASE_NS + 0x02400UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define USB_OTG_HS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define OCTOSPIM_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xA4000UL) /*!< OCTOSPIO Manager control registers base address */ +#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL) +#define SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL) +#define DLYB_SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF400UL) +#define FMC_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB0400UL) /*!< FMC control registers base address */ +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ +#define HSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB3400UL) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS) +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1300UL) +#define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL) +#define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL) +#define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL) +#define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL) +#define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL) +#define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL) +#define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL) +#define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL) +#define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (4 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (768 KB) secure base address */ +#define SRAM2_BASE_S (0x300C0000UL) /*!< SRAM2 (64 KB) secure base address */ +#define SRAM3_BASE_S (0x300D0000UL) /*!< SRAM3 (832 KB) secure base address */ +#define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */ +#define SRAM5_BASE_S (0x301A0000UL) /*!< SRAM5 (832 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define I2C5_BASE_S (APB1PERIPH_BASE_S + 0x9800UL) +#define I2C6_BASE_S (APB1PERIPH_BASE_S + 0x9C00UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) +#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) +#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x004UL) +#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x024UL) + +/*!< APB3 Secure peripherals */ +#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) +#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP2_BASE_S (APB3PERIPH_BASE_S + 0x5010UL) +#define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define COMP2_BASE_S (COMP12_BASE_S + 0x04UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define RAMCFG_SRAM5_BASE_S (RAMCFG_BASE_S + 0x0140UL) +#define DMA2D_BASE_S (AHB1PERIPH_BASE_S + 0x0B000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define GTZC_MPCBB5_BASE_S (AHB1PERIPH_BASE_S + 0x13800UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define GPIOI_BASE_S (AHB2PERIPH_BASE_S + 0x02000UL) +#define GPIOJ_BASE_S (AHB2PERIPH_BASE_S + 0x02400UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define USB_OTG_HS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */ +#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) +#define SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) +#define DLYB_SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_S (AHB2PERIPH_BASE_S + 0xAF400UL) +#define FMC_R_BASE_S (AHB2PERIPH_BASE_S + 0xB0400UL) /*!< FMC control registers base address */ +#define HSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB3400UL) +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_S (AHB2PERIPH_BASE_S + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1300UL) +#define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) +#define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL) +#define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL) +#define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL) +#define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL) +#define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL) +#define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) +#define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) + + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0044000UL) +#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ +#define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */ + +/* USB OTG registers Base address */ +#define USB_OTG_GLOBAL_BASE (0x0000UL) +#define USB_OTG_DEVICE_BASE (0x0800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) +#define USB_OTG_EP_REG_SIZE (0x0020UL) +#define USB_OTG_HOST_BASE (0x0400UL) +#define USB_OTG_HOST_PORT_BASE (0x0440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) +#define USB_OTG_PCGCCTL_BASE (0x0E00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0U) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0U) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1U) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) +#define USART6_NS ((USART_TypeDef *) USART6_BASE_NS) +#define I2C5_NS ((I2C_TypeDef *) I2C5_BASE_NS) +#define I2C6_NS ((I2C_TypeDef *) I2C6_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) +#define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS) +#define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) +#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS) +#define RAMCFG_SRAM5_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GTZC_MPCBB5_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GPIOI_NS ((GPIO_TypeDef *) GPIOI_BASE_NS) +#define GPIOJ_NS ((GPIO_TypeDef *) GPIOJ_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define USB_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) +#define DLYB_OCTOSPI2_NS ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_NS) +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS) +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define OCTOSPI2_NS ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS) +#define HSPI1_NS ((HSPI_TypeDef *) HSPI1_R_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS) +#define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS) +#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) +#define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS) +#define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS) +#define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS) +#define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS) +#define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) +#define USART6_S ((USART_TypeDef *) USART6_BASE_S) +#define I2C5_S ((I2C_TypeDef *) I2C5_BASE_S) +#define I2C6_S ((I2C_TypeDef *) I2C6_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) + +/*!< APB2 Secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) +#define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S) +#define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S) + +/*!< APB3 secure peripherals */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) +#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) +#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S) +#define RAMCFG_SRAM5_S ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GTZC_MPCBB5_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_S) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GPIOI_S ((GPIO_TypeDef *) GPIOI_BASE_S) +#define GPIOJ_S ((GPIO_TypeDef *) GPIOJ_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define USB_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) +#define DLYB_OCTOSPI2_S ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_S) +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S) +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define OCTOSPI2_S ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S) +#define HSPI1_S ((HSPI_TypeDef *) HSPI1_R_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S) +#define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S) +#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) +#define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S) +#define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S) +#define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S) +#define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S) +#define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S) + +/*!< DBGMCU peripheral */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define SRAM4_BASE SRAM4_BASE_S +#define SRAM5_BASE SRAM5_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define FMAC FMAC_S +#define FMAC_BASE FMAC_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define LPDMA1 LPDMA1_S +#define LPDMA1_BASE LPDMA1_BASE_S + +#define LPDMA1_Channel0 LPDMA1_Channel0_S +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S + +#define LPDMA1_Channel1 LPDMA1_Channel1_S +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S + +#define LPDMA1_Channel2 LPDMA1_Channel2_S +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S + +#define LPDMA1_Channel3 LPDMA1_Channel3_S +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define GPIOI GPIOI_S +#define GPIOI_BASE GPIOI_BASE_S + +#define GPIOJ GPIOJ_S +#define GPIOJ_BASE GPIOJ_BASE_S + +#define LPGPIO1 LPGPIO1_S +#define LPGPIO1_BASE LPGPIO1_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_S +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_S +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZSC2 GTZC_TZSC2_S +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_TZIC2 GTZC_TZIC2_S +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define GTZC_MPCBB4 GTZC_MPCBB4_S +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S + +#define GTZC_MPCBB5 GTZC_MPCBB5_S +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define I2C5 I2C5_S +#define I2C5_BASE I2C5_BASE_S + +#define I2C6 I2C6_S +#define I2C6_BASE I2C6_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define DAC DAC_S +#define DAC_BASE DAC_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define OPAMP OPAMP_S +#define OPAMP_BASE OPAMP_BASE_S + +#define OPAMP1 OPAMP1_S +#define OPAMP1_BASE OPAMP1_BASE_S + +#define OPAMP2 OPAMP2_S +#define OPAMP2_BASE OPAMP2_BASE_S + +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define COMP12 COMP12_S +#define COMP12_BASE COMP12_BASE_S + +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S + +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S + +#define COMP12_COMMON COMP12_COMMON_S +#define COMP12_COMMON_BASE COMP1_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + +#define SAI2 SAI2_S +#define SAI2_BASE SAI2_BASE_S + +#define SAI2_Block_A SAI2_Block_A_S +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S + +#define SAI2_Block_B SAI2_Block_B_S +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + + +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S + +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + +#define SDMMC2 SDMMC2_S +#define SDMMC2_BASE SDMMC2_BASE_S + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define OCTOSPI2 OCTOSPI2_S +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_S + +#define OCTOSPIM OCTOSPIM_S +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_SDMMC2 DLYB_SDMMC2_S +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_S +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_S + +#define HSPI1 HSPI1_S +#define HSPI1_R_BASE HSPI1_R_BASE_S + +#define DMA2D DMA2D_S +#define DMA2D_BASE DMA2D_BASE_S + +#define USB_OTG_HS USB_OTG_HS_S +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_S + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM3_BASE SRAM3_BASE_NS +#define SRAM4_BASE SRAM4_BASE_NS +#define SRAM5_BASE SRAM5_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DMA2D DMA2D_NS +#define DMA2D_BASE DMA2D_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define FMAC FMAC_NS +#define FMAC_BASE FMAC_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define LPDMA1 LPDMA1_NS +#define LPDMA1_BASE LPDMA1_BASE_NS + +#define LPDMA1_Channel0 LPDMA1_Channel0_NS +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS + +#define LPDMA1_Channel1 LPDMA1_Channel1_NS +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS + +#define LPDMA1_Channel2 LPDMA1_Channel2_NS +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS + +#define LPDMA1_Channel3 LPDMA1_Channel3_NS +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define GPIOI GPIOI_NS +#define GPIOI_BASE GPIOI_BASE_NS +#define GPIOJ GPIOJ_NS +#define GPIOJ_BASE GPIOJ_BASE_NS + +#define LPGPIO1 LPGPIO1_NS +#define LPGPIO1_BASE LPGPIO1_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_NS +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_NS +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZSC2 GTZC_TZSC2_NS +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_TZIC2 GTZC_TZIC2_NS +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define GTZC_MPCBB4 GTZC_MPCBB4_NS +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS + +#define GTZC_MPCBB5 GTZC_MPCBB5_NS +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define I2C5 I2C5_NS +#define I2C5_BASE I2C5_BASE_NS + +#define I2C6 I2C6_NS +#define I2C6_BASE I2C6_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define OPAMP OPAMP_NS +#define OPAMP_BASE OPAMP_BASE_NS + +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS + +#define OPAMP2 OPAMP2_NS +#define OPAMP2_BASE OPAMP2_BASE_NS + +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define COMP12 COMP12_NS +#define COMP12_BASE COMP12_BASE_NS + +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS + +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS + +#define COMP12_COMMON COMP12_COMMON_NS +#define COMP12_COMMON_BASE COMP1_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + +#define SAI2 SAI2_NS +#define SAI2_BASE SAI2_BASE_NS + +#define SAI2_Block_A SAI2_Block_A_NS +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS + +#define SAI2_Block_B SAI2_Block_B_NS +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS + +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + +#define SDMMC2 SDMMC2_NS +#define SDMMC2_BASE SDMMC2_BASE_NS + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define OCTOSPI2 OCTOSPI2_NS +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_NS + +#define OCTOSPIM OCTOSPIM_NS +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_SDMMC2 DLYB_SDMMC2_NS +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_NS +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_NS + +#define HSPI1 HSPI1_NS +#define HSPI1_R_BASE HSPI1_R_BASE_NS + +#define USB_OTG_HS USB_OTG_HS_NS +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_NS + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS +#endif + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +#define ADC_MULTIMODE_SUPPORT +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ +#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_ADCALLIN_Pos (16U) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ + +#define ADC_CR_CALINDEX_Pos (24U) +#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ +#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ +#define ADC_CR_CALINDEX0_Pos (24U) +#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ +#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ +#define ADC_CR_CALINDEX1_Pos (25U) +#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ +#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ +#define ADC_CR_CALINDEX2_Pos (26U) +#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ +#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ +#define ADC_CR_CALINDEX3_Pos (27U) +#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ +#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR1_DMNGT_Pos (0U) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC4_CFGR1_DMAEN_Pos (0U) +#define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC4_CFGR1_DMACFG_Pos (1U) +#define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC4_CFGR1_SCANDIR_Pos (4U) +#define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC4_CFGR1_ALIGN_Pos (5U) +#define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (5U) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ + +#define ADC_CFGR1_AUTDLY_Pos (14U) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC4_CFGR1_WAIT_Pos (14U) +#define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR1_DISCNUM_Pos (17U) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20U) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR1_JAWD1EN_Pos (24U) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR1_JAUTO_Pos (25U) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +/* Specific ADC4 */ +#define ADC4_CFGR1_EXTSEL_Pos (6U) +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ + +#define ADC4_CFGR1_CHSELRMOD_Pos (21U) +#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_BULB_Pos (13U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (27U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* Specific ADC4 */ +#define ADC4_CFGR2_OVSR_Pos (2U) +#define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC4_CFGR2_LFTRIG_Pos (29U) +#define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC4_SMPR_SMP1_Pos (0U) +#define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC4_SMPR_SMP2_Pos (4U) +#define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC4_SMPR_SMPSEL_Pos (8U) +#define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ +#define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ +#define ADC4_SMPR_SMPSEL0_Pos (8U) +#define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ +#define ADC4_SMPR_SMPSEL1_Pos (9U) +#define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ +#define ADC4_SMPR_SMPSEL2_Pos (10U) +#define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ +#define ADC4_SMPR_SMPSEL3_Pos (11U) +#define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ +#define ADC4_SMPR_SMPSEL4_Pos (12U) +#define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ +#define ADC4_SMPR_SMPSEL5_Pos (13U) +#define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ +#define ADC4_SMPR_SMPSEL6_Pos (14U) +#define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ +#define ADC4_SMPR_SMPSEL7_Pos (15U) +#define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ +#define ADC4_SMPR_SMPSEL8_Pos (16U) +#define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ +#define ADC4_SMPR_SMPSEL9_Pos (17U) +#define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ +#define ADC4_SMPR_SMPSEL10_Pos (18U) +#define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ +#define ADC4_SMPR_SMPSEL11_Pos (19U) +#define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ +#define ADC4_SMPR_SMPSEL12_Pos (20U) +#define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ +#define ADC4_SMPR_SMPSEL13_Pos (21U) +#define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ +#define ADC4_SMPR_SMPSEL14_Pos (22U) +#define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ +#define ADC4_SMPR_SMPSEL15_Pos (23U) +#define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ +#define ADC4_SMPR_SMPSEL16_Pos (24U) +#define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ +#define ADC4_SMPR_SMPSEL17_Pos (25U) +#define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ +#define ADC4_SMPR_SMPSEL18_Pos (26U) +#define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ +#define ADC4_SMPR_SMPSEL19_Pos (27U) +#define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ +#define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ +#define ADC4_SMPR_SMPSEL20_Pos (26U) +#define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ +#define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL21_Pos (26U) +#define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ +#define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL22_Pos (30U) +#define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ +#define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ +#define ADC4_SMPR_SMPSEL23_Pos (31U) +#define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ +#define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +#define ADC_HTR_AWDFILT_Pos (29U) +#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ +#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_PW register ********************/ +#define ADC4_PWRR_AUTOFF_Pos (0U) +#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ +#define ADC4_PWRR_DPD_Pos (1U) +#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ +#define ADC4_PWRR_VREFPROT_Pos (2U) +#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ +#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ +#define ADC4_PWRR_VREFSECSMP_Pos (3U) +#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ +#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ + +/* Legacy definitions */ +#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos +#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk +#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF +#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos +#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk +#define ADC4_PW_DPD ADC4_PWRR_DPD +#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos +#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk +#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT +#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos +#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk +#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_USAT_Pos (25U) +#define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_SSAT_Pos (26U) +#define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (27U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR2_USAT_Pos (25U) +#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR2_SSAT_Pos (26U) +#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (27U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR3_USAT_Pos (25U) +#define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR3_SSAT_Pos (26U) +#define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (27U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR4_USAT_Pos (25U) +#define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR4_SSAT_Pos (26U) +#define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (27U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_GCOMP register ********************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ +#define ADC_GCOMP_GCOMP_Pos (31U) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19U) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20U) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21U) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22U) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL23_Pos (23U) +#define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_I_APB_ADDR_Pos (0U) +#define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ +#define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ + +#define ADC_CALFACT_I_APB_DATA_Pos (08U) +#define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ +#define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ + +#define ADC_CALFACT_VALIDITY_Pos (16U) +#define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_LATCH_COEF_Pos (24U) +#define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CAPTURE_COEF_Pos (25U) +#define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ + +#define ADC4_CALFACT_CALFACT_Pos (0U) +#define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_CALFACT_Pos (0U) +#define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */ +#define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */ +#define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OR register ********************/ +#define ADC_OR_CHN0SEL_Pos (0U) +#define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ +#define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_LDORDY_MST_Pos (12U) +#define ADC_CSR_LDORDY_MST_Msk (0x1UL << ADC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADC_CSR_LDORDY_MST ADC_CSR_LDORDY_MST_Msk /*!< Voltage regulator ready flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_LDORDY_SLV_Pos (28U) +#define ADC_CSR_LDORDY_SLV_Msk (0x1UL << ADC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CSR_LDORDY_SLV ADC_CSR_LDORDY_SLV_Msk /*!< Voltage regulator ready flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DAMDF_Pos (14U) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_VSENSEEN_Pos (23U) +#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ +#define ADC_CCR_VDDCOREN_Pos (26U) +#define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ +#define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0U) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) + +#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ + +#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11U) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ1_Pos (12U) +#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */ +#define FLASH_ACR_PDREQ2_Pos (13U) +#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */ +#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14U) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0U) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1U) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3U) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4U) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5U) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6U) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7U) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13U) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16U) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17U) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18U) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19U) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD1_Pos (20U) +#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */ +#define FLASH_NSSR_PD2_Pos (21U) +#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */ +#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0U) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1U) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3U) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4U) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5U) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6U) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7U) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16U) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17U) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR register *****************/ +#define FLASH_NSCR_PG_Pos (0U) +#define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR_PER_Pos (1U) +#define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR_MER1_Pos (2U) +#define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */ +#define FLASH_NSCR_PNB_Pos (3U) +#define FLASH_NSCR_PNB_Msk (0xFFUL << FLASH_NSCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR_BKER_Pos (11U) +#define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */ +#define FLASH_NSCR_BWR_Pos (14U) +#define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR_MER2_Pos (15U) +#define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */ +#define FLASH_NSCR_STRT_Pos (16U) +#define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR_OPTSTRT_Pos (17U) +#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR_EOPIE_Pos (24U) +#define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR_ERRIE_Pos (25U) +#define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR_OBL_LAUNCH_Pos (27U) +#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR_OPTLOCK_Pos (30U) +#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR_LOCK_Pos (31U) +#define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR register ****************/ +#define FLASH_SECCR_PG_Pos (0U) +#define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR_PER_Pos (1U) +#define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR_MER1_Pos (2U) +#define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR_PNB_Pos (3U) +#define FLASH_SECCR_PNB_Msk (0xFFUL << FLASH_SECCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR_BKER_Pos (11U) +#define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */ +#define FLASH_SECCR_BWR_Pos (14U) +#define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR_MER2_Pos (15U) +#define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */ +#define FLASH_SECCR_STRT_Pos (16U) +#define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR_EOPIE_Pos (24U) +#define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR_ERRIE_Pos (25U) +#define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR_INV_Pos (29U) +#define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR_LOCK_Pos (31U) +#define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0x1FFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x001FFFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_BK_ECC_Pos (21U) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (22U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0x1FFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x001FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */ +#define FLASH_OPSR_BK_OP_Pos (21U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (22U) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8U) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_nRST_SHDW_Pos (14U) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ +#define FLASH_OPTR_SRAM_RST_Pos (15U) +#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SWAP_BANK_Pos (20U) +#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */ +#define FLASH_OPTR_DUALBANK_Pos (21U) +#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */ +#define FLASH_OPTR_BKPRAM_ECC_Pos (22U) +#define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTR_SRAM3_ECC_Pos (23U) +#define FLASH_OPTR_SRAM3_ECC_Msk (0x1UL << FLASH_OPTR_SRAM3_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_SRAM3_ECC FLASH_OPTR_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */ +#define FLASH_OPTR_SRAM2_ECC_Pos (24U) +#define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25U) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26U) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_PA15_PUPEN_Pos (28U) +#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */ +#define FLASH_OPTR_IO_VDD_HSLV_Pos (29U) +#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */ +#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30U) +#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */ +#define FLASH_OPTR_TZEN_Pos (31U) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7U) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7U) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0U) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7U) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWM1R1 register **************/ +#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0U) +#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16U) +#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWM1R2 register **************/ +#define FLASH_SECWM1R2_HDP1_PEND_Pos (16U) +#define FLASH_SECWM1R2_HDP1_PEND_Msk (0xFFUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWM1R2_HDP1EN_Pos (31U) +#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0U) +#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */ +#define FLASH_WRP1AR_WRP1A_PEND_Pos (16U) +#define FLASH_WRP1AR_WRP1A_PEND_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */ +#define FLASH_WRP1AR_UNLOCK_Pos (31U) +#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0U) +#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */ +#define FLASH_WRP1BR_WRP1B_PEND_Pos (16U) +#define FLASH_WRP1BR_WRP1B_PEND_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */ +#define FLASH_WRP1BR_UNLOCK_Pos (31U) +#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */ + +/***************** Bits definition for FLASH_SECWM2R1 register **************/ +#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0U) +#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */ +#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16U) +#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */ + +/***************** Bits definition for FLASH_SECWM2R2 register **************/ +#define FLASH_SECWM2R2_HDP2_PEND_Pos (16U) +#define FLASH_SECWM2R2_HDP2_PEND_Msk (0xFFUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */ +#define FLASH_SECWM2R2_HDP2EN_Pos (31U) +#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */ + +/****************** Bits definition for FLASH_WRP2AR register ***************/ +#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0U) +#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */ +#define FLASH_WRP2AR_WRP2A_PEND_Pos (16U) +#define FLASH_WRP2AR_WRP2A_PEND_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */ +#define FLASH_WRP2AR_UNLOCK_Pos (31U) +#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP2BR register ***************/ +#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0U) +#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */ +#define FLASH_WRP2BR_WRP2B_PEND_Pos (16U) +#define FLASH_WRP2BR_WRP2B_PEND_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */ +#define FLASH_WRP2BR_UNLOCK_Pos (31U) +#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0U) +#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */ +#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1U) +#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */ +#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0U) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1U) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************************************************************************/ +/* */ +/* Filter Mathematical ACcelerator unit (FMAC) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1_BASE_Pos (0U) +#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U) +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ +#define FMAC_X1BUFCFG_FULL_WM_Pos (24U) +#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ +#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ + +/***************** Bit definition for FMAC_X2BUFCFG register ****************/ +#define FMAC_X2BUFCFG_X2_BASE_Pos (0U) +#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U) +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ + +/***************** Bit definition for FMAC_YBUFCFG register *****************/ +#define FMAC_YBUFCFG_Y_BASE_Pos (0U) +#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ +#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U) +#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ +#define FMAC_YBUFCFG_EMPTY_WM_Pos (24U) +#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ +#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ + +/****************** Bit definition for FMAC_PARAM register ******************/ +#define FMAC_PARAM_P_Pos (0U) +#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ +#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ +#define FMAC_PARAM_Q_Pos (8U) +#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ +#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ +#define FMAC_PARAM_R_Pos (16U) +#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ +#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ +#define FMAC_PARAM_FUNC_Pos (24U) +#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ +#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ +#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ +#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ +#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ +#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ +#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ +#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ +#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ +#define FMAC_PARAM_START_Pos (31U) +#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ +#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ + +/******************** Bit definition for FMAC_CR register *******************/ +#define FMAC_CR_RIEN_Pos (0U) +#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ +#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ +#define FMAC_CR_WIEN_Pos (1U) +#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ +#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ +#define FMAC_CR_OVFLIEN_Pos (2U) +#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ +#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ +#define FMAC_CR_UNFLIEN_Pos (3U) +#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ +#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ +#define FMAC_CR_SATIEN_Pos (4U) +#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ +#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ +#define FMAC_CR_DMAREN_Pos (8U) +#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ +#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ +#define FMAC_CR_DMAWEN_Pos (9U) +#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ +#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ +#define FMAC_CR_CLIPEN_Pos (15U) +#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ +#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ +#define FMAC_CR_RESET_Pos (16U) +#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ +#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_SR register ********************/ +#define FMAC_SR_YEMPTY_Pos (0U) +#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ +#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ +#define FMAC_SR_X1FULL_Pos (1U) +#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ +#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ +#define FMAC_SR_OVFL_Pos (8U) +#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ +#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ +#define FMAC_SR_UNFL_Pos (9U) +#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ +#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ +#define FMAC_SR_SAT_Pos (10U) +#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ +#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ + +/****************** Bit definition for FMAC_WDATA register ******************/ +#define FMAC_WDATA_WDATA_Pos (0U) +#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ + +/****************** Bit definition for FMACX_RDATA register *****************/ +#define FMAC_RDATA_RDATA_Pos (0U) +#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20U) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk + +/******************** Bits definition for TAMP_COUNTR register ***************/ +#define TAMP_COUNTR_Pos (16U) +#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ +#define TAMP_COUNTR TAMP_COUNTR_Msk + +/******************** Bits definition for TAMP_ERCFGR register ***************/ +#define TAMP_ERCFGR0_Pos (0U) +#define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* Touch Sensing Controller (TSC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TSC_CR register *********************/ +#define TSC_CR_TSCE_Pos (0U) +#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ +#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32u5xx.h" /*!< STM32U5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ + uint32_t RESERVED3[246]; /*!< Reserved, */ + __IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */ + __IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; +} I2C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, 0x24 */ + __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FC */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FC */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFC */ +} DMA2D_TypeDef; + +/** + * @brief DSI Controller + */ +typedef struct +{ + __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ + __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ + __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ + __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ + __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ + __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ + __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ + __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ + __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ + __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ + __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ + __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ + __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ + __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ + __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ + __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ + __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ + __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ + __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ + __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ + __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ + __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ + __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ + __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ + __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ + __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ + uint32_t RESERVED1; /*!< Reserved, 0x90 */ + __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ + __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ + __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ + __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ + __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ + __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ + __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ + __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ + uint32_t RESERVED2[2]; /*!< Reserved, 0xB4 - 0xBB */ + __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ + __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ + uint32_t RESERVED3[3]; /*!< Reserved, 0xD0 - 0xD7 */ + __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ + uint32_t RESERVED4[5]; /*!< Reserved, 0xE0 - 0xF3 */ + __IO uint32_t DLTRCR; /*!< DSI Host Data Lane Timer Read Configuration Register, Address offset: 0xF4 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0xF8 - 0xFF */ + __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x104 - 0x10B */ + __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ + __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ + uint32_t RESERVED7; /*!< Reserved, 0x114 */ + __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ + uint32_t RESERVED8[7]; /*!< Reserved, 0x11C - 0x137 */ + __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ + __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chunks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ + __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ + __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ + __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ + __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ + __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ + __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ + __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ + uint32_t RESERVED9; /*!< Reserved, 0x164 */ + __IO uint32_t FBSR; /*!< DSI Host FIFO and Buffer Status Register, Address offset: 0x168 */ + uint32_t RESERVED10[165];/*!< Reserved, 0x16C - 0x3FF */ + __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ + __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ + __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ + __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ + __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ + uint32_t RESERVED11; /*!< Reserved, 0x414 */ + __IO uint32_t WPCR[1]; /*!< DSI Wrapper PHY Configuration Register 0, Address offset: 0x418 */ + uint32_t RESERVED12[5]; /*!< Reserved, 0x41C - 0x42F */ + __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ + uint32_t WPTR; /*!< DSI Wrapper PLL tuning register, Address offset: 0x434 */ + uint32_t RESERVED13[244];/*!< Reserved, 0x43C - 0x804 */ + __IO uint32_t BCFGR; /*!< DSI Bias Configuration Register, Address offset: 0x808 */ + uint32_t RESERVED14[254];/*!< Reserved, 0x80C - 0xC00 */ + __IO uint32_t DPCBCR; /*!< D-PHY clock band control register, Address offset: 0xC04 */ + uint32_t RESERVED15[11]; /*!< Reserved, 0xC08 - 0xC30 */ + __IO uint32_t DPCSRCR; /*!< D-PHY clock slew rate control register, Address offset: 0xC34 */ + uint32_t RESERVED16[9]; /*!< Reserved, 0xC38 - 0xC58 */ + __IO uint32_t DPDL0HSOCR; /*!< D-PHY data Lane 0 HS offset control register, Address offset: 0x0C5C */ + __IO uint32_t DPDL0LPXOCR; /*!< D-PHY data Lane 0 HS LPX offset control register, Address offset: 0x0C60 */ + uint32_t RESERVED17[3]; /*!< Reserved, 0xC64-0xC6C */ + __IO uint32_t DPDL0BCR; /*!< D-PHY data Lane0 band control register, Address offset: 0x0C70 */ + uint32_t RESERVED18[11]; /*!< Reserved, 0xC74 - 0xC9C */ + __IO uint32_t DPDL0SRCR; /*!< D-PHY data Lane0 slew rate control register, Address offset: 0x0CA0 */ + uint32_t RESERVED19[20]; /*!< Reserved, 0xCA4 - 0xD04 */ + __IO uint32_t DPDL1HSOCR; /*!< D-PHY data Lane 1 HS offset control register, Address offset: 0x0CF4 */ + __IO uint32_t DPDL1LPXOCR; /*!< D-PHY data Lane 1 HS LPX offset control register, Address offset: 0x0CF8 */ + uint32_t RESERVED20[3]; /*!< Reserved, 0xCF8 - 0xD04 */ + __IO uint32_t DPDL1BCR; /*!< D-PHY data Lane1 band control register, Address offset: 0x0D08 */ + uint32_t RESERVED21[11]; /*!< Reserved, 0xD0C - 0xD34 */ + __IO uint32_t DPDL1SRCR; /*!< D-PHY data Lane1 slew rate control register, Address Offset: 0x0D38 */ +} DSI_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ + __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */ + __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */ + __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */ + __IO uint32_t SECBB1R5; /*!< FLASH secure block-based bank 1 register 5, Address offset: 0x90 */ + __IO uint32_t SECBB1R6; /*!< FLASH secure block-based bank 1 register 6, Address offset: 0x94 */ + __IO uint32_t SECBB1R7; /*!< FLASH secure block-based bank 1 register 7, Address offset: 0x98 */ + __IO uint32_t SECBB1R8; /*!< FLASH secure block-based bank 1 register 8, Address offset: 0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */ + __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */ + __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */ + __IO uint32_t SECBB2R5; /*!< FLASH secure block-based bank 2 register 5, Address offset: 0xB0 */ + __IO uint32_t SECBB2R6; /*!< FLASH secure block-based bank 2 register 6, Address offset: 0xB4 */ + __IO uint32_t SECBB2R7; /*!< FLASH secure block-based bank 2 register 7, Address offset: 0xB8 */ + __IO uint32_t SECBB2R8; /*!< FLASH secure block-based bank 2 register 8, Address offset: 0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */ + __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */ + __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */ + __IO uint32_t PRIVBB1R5; /*!< FLASH privilege block-based bank 1 register 5, Address offset: 0xE0 */ + __IO uint32_t PRIVBB1R6; /*!< FLASH privilege block-based bank 1 register 6, Address offset: 0xE4 */ + __IO uint32_t PRIVBB1R7; /*!< FLASH privilege block-based bank 1 register 7, Address offset: 0xE8 */ + __IO uint32_t PRIVBB1R8; /*!< FLASH privilege block-based bank 1 register 8, Address offset: 0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */ + __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */ + __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */ + __IO uint32_t PRIVBB2R5; /*!< FLASH privilege block-based bank 2 register 5, Address offset: 0x100 */ + __IO uint32_t PRIVBB2R6; /*!< FLASH privilege block-based bank 2 register 6, Address offset: 0x104 */ + __IO uint32_t PRIVBB2R7; /*!< FLASH privilege block-based bank 2 register 7, Address offset: 0x108 */ + __IO uint32_t PRIVBB2R8; /*!< FLASH privilege block-based bank 2 register 8, Address offset: 0x10C */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief GFXMMU registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */ + __IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */ + __IO uint32_t CCR; /*!< GFXMMU Cache Control Register, Address offset: 0x0C */ + __IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x14 to 0x1C */ + __IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */ + __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ + __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ + __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ + uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */ + __IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */ + __IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */ + __IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */ + __IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */ + __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC + For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ +} GFXMMU_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */ + __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */ + __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */ + __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */ + __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */ + __IO uint32_t MPCWM6ACFGR; /*!< TZSC memory 6 sub-region A watermark configuration register, Address offset: 0x90 */ + __IO uint32_t MPCWM6AR; /*!< TZSC memory 6 sub-region A watermark register, Address offset: 0x94 */ + __IO uint32_t MPCWM6BCFGR; /*!< TZSC memory 6 sub-region B watermark configuration register, Address offset: 0x98 */ + __IO uint32_t MPCWM6BR; /*!< TZSC memory 6 sub-region B watermark register, Address offset: 0x9C */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register 1, Address offset: 0x10 */ + __IO uint32_t CFGLOCKR2; /*!< MPCBBx Configuration lock register 2, Address offset: 0x14 */ + uint32_t RESERVED2[58]; /*!< Reserved2, Address offset: 0x18-0xFC */ + __IO uint32_t SECCFGR[52]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x1CC */ + uint32_t RESERVED3[12]; /*!< Reserved3, Address offset: 0x1D0-0x1FC */ + __IO uint32_t PRIVCFGR[52]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x2CC */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ + uint32_t RESERVED2[240]; /*!< Reserved, Address offset: 0x30-0x3EC */ + __IO uint32_t HWCFGR; /*!< ICACHE HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< ICACHE version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ICACHE IP identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ICACHE size identification register, Address offset: 0x3FC */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + + +/** + * @brief MDF/ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ +}MDF_TypeDef; + +/** + * @brief MDF/ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ + __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ + __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ + __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ + __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief HEXA and OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ + uint32_t RESERVED22[3]; /*!< Reserved, Address offset: 0x204-0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-cycle calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x210 */ + uint32_t RESERVED23; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL master calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x218 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI slave output calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x220 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI slave input calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x228 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + +typedef XSPI_TypeDef HSPI_TypeDef; + + +/** + * @brief Serial Peripheral Interface IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPIM IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[8]; /*!< OCTOSPIM IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ +} XSPIM_TypeDef; + +typedef XSPIM_TypeDef OCTOSPIM_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x20 */ + __IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Power USB Type-C and Power Delivery register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + __IO uint32_t BDSR; /*!< Power backup domain status register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */ + __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ + __IO uint32_t PUCRI; /*!< Power Port I pull-up control register, Address offset: 0x90 */ + __IO uint32_t PDCRI; /*!< Power Port I pull-down control register, Address offset: 0x94 */ + __IO uint32_t PUCRJ; /*!< Power Port J pull-up control register, Address offset: 0x98 */ + __IO uint32_t PDCRJ; /*!< Power Port J pull-down control register, Address offset: 0x9C */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x0A0-0x0A4 */ + __IO uint32_t CR4; /*!< Power power control register 4, Address offset: 0xA8 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */ + __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */ + __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */ + __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */ + __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */ + __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */ + __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */ + __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */ + __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */ + __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */ + __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */ + uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + uint32_t RESERVED2[17];/*!< RESERVED2, Address offset: 0x30 - 0x70 */ + __IO uint32_t OTGHSPHYCR; /*!< SYSCFG USB OTG_HS PHY register Address offset: 0x74 */ + uint32_t RESERVED3; /*!< RESERVED3, Address offset: 0x78 */ + __IO uint32_t OTGHSPHYTUNER2;/*!< SYSCFG USB OTG_HS PHY tune register 2 Address offset: 0x7C */ +} SYSCFG_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief Flexible Memory Controller + */ +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief ADC + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ /* Specific to ADC 14Bits*/ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t AWD1TR; /*!< ADC watchdog threshold register, Address offset: 0x20 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ /* Specific to ADC 12Bits*/ + __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x2C */ /* Specific to ADC 12Bits*/ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ /* Specific to ADC 14Bits*/ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ + uint32_t RESERVED1; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ /* Specific to ADC 14Bits*/ + __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED3[3]; /*!< Reserved, 0x074 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED4[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0xA8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0xAC */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ /* Specific to ADC 14Bits*/ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED5; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0xD0 */ /* Specific to ADC 12Bits*/ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode, Address offset: 0x310 */ +} ADC_Common_TypeDef; + + +/* Legacy registers naming */ +#define PW PWRR + +/** + * @brief CORDIC + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief Touch Sensing Controller (TSC) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ +} TSC_TypeDef; + +/** + * @brief WWDG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32U5xx_peripherals */ + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0xC0000UL) /*!< SRAM1=768k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ +#define SRAM3_SIZE (0xD0000UL) /*!< SRAM3=832k */ +#define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */ +#define SRAM5_SIZE (0xD0000UL) /*!< SRAM5=832k */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< OCTOSPI2 memories accessible over AHB base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ +#define HSPI1_BASE (0xA0000000UL) /*!< HSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (4 MB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (768 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x200C0000UL) /*!< SRAM2 (64 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x200D0000UL) /*!< SRAM3 (832 KB) non-secure base address */ +#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */ +#define SRAM5_BASE_NS (0x201A0000UL) /*!< SRAM5 (832 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define I2C5_BASE_NS (APB1PERIPH_BASE_NS + 0x9800UL) +#define I2C6_BASE_NS (APB1PERIPH_BASE_NS + 0x9C00UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) +#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) +#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x004UL) +#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x024UL) +#define LTDC_BASE_NS (APB2PERIPH_BASE_NS + 0x6800UL) +#define LTDC_Layer1_BASE_NS (LTDC_BASE_NS + 0x0084UL) +#define LTDC_Layer2_BASE_NS (LTDC_BASE_NS + 0x0104UL) +#define DSI_BASE_NS (APB2PERIPH_BASE_NS + 0x6C00UL) +#define REFBIAS_BASE_NS (DSI_BASE_NS + 0x800UL) +#define DPHY_BASE_NS (DSI_BASE_NS + 0xC00UL) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) +#define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP2_BASE_NS (APB3PERIPH_BASE_NS + 0x5010UL) +#define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define RAMCFG_SRAM5_BASE_NS (RAMCFG_BASE_NS + 0x0140UL) +#define DMA2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0B000UL) +#define GFXMMU_BASE_NS (AHB1PERIPH_BASE_NS + 0x0C000UL) +#define GPU2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0F000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define DCACHE2_BASE_NS (AHB1PERIPH_BASE_NS + 0x11800UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define GTZC_MPCBB5_BASE_NS (AHB1PERIPH_BASE_NS + 0x13800UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define GPIOI_BASE_NS (AHB2PERIPH_BASE_NS + 0x02000UL) +#define GPIOJ_BASE_NS (AHB2PERIPH_BASE_NS + 0x02400UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define USB_OTG_HS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define OCTOSPIM_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xA4000UL) /*!< OCTOSPIO Manager control registers base address */ +#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL) +#define SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL) +#define DLYB_SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF400UL) +#define FMC_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB0400UL) /*!< FMC control registers base address */ +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ +#define HSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB3400UL) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS) +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1300UL) +#define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL) +#define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL) +#define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL) +#define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL) +#define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL) +#define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL) +#define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL) +#define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL) +#define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL) +/* GFXMMU non secure virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE_NS (0x24000000UL) +#define GFXMMU_VIRTUAL_BUFFER0_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS) +#define GFXMMU_VIRTUAL_BUFFER1_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0x400000UL) +#define GFXMMU_VIRTUAL_BUFFER2_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0x800000UL) +#define GFXMMU_VIRTUAL_BUFFER3_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0xC00000UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (4 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (768 KB) secure base address */ +#define SRAM2_BASE_S (0x300C0000UL) /*!< SRAM2 (64 KB) secure base address */ +#define SRAM3_BASE_S (0x300D0000UL) /*!< SRAM3 (832 KB) secure base address */ +#define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */ +#define SRAM5_BASE_S (0x301A0000UL) /*!< SRAM5 (832 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define I2C5_BASE_S (APB1PERIPH_BASE_S + 0x9800UL) +#define I2C6_BASE_S (APB1PERIPH_BASE_S + 0x9C00UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) +#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) +#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x004UL) +#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x024UL) +#define LTDC_BASE_S (APB2PERIPH_BASE_S + 0x6800UL) +#define LTDC_Layer1_BASE_S (LTDC_BASE_S + 0x0084UL) +#define LTDC_Layer2_BASE_S (LTDC_BASE_S + 0x0104UL) +#define DSI_BASE_S (APB2PERIPH_BASE_S + 0x6C00UL) +#define REFBIAS_BASE_S (DSI_BASE_S + 0x800UL) +#define DPHY_BASE_S (DSI_BASE_S + 0xC00UL) + +/*!< APB3 Secure peripherals */ +#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) +#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP2_BASE_S (APB3PERIPH_BASE_S + 0x5010UL) +#define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define COMP2_BASE_S (COMP12_BASE_S + 0x04UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define RAMCFG_SRAM5_BASE_S (RAMCFG_BASE_S + 0x0140UL) +#define DMA2D_BASE_S (AHB1PERIPH_BASE_S + 0x0B000UL) +#define GFXMMU_BASE_S (AHB1PERIPH_BASE_S + 0x0C000UL) +#define GPU2D_BASE_S (AHB1PERIPH_BASE_S + 0x0F000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define DCACHE2_BASE_S (AHB1PERIPH_BASE_S + 0x11800UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define GTZC_MPCBB5_BASE_S (AHB1PERIPH_BASE_S + 0x13800UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define GPIOI_BASE_S (AHB2PERIPH_BASE_S + 0x02000UL) +#define GPIOJ_BASE_S (AHB2PERIPH_BASE_S + 0x02400UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define USB_OTG_HS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */ +#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) +#define SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) +#define DLYB_SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_S (AHB2PERIPH_BASE_S + 0xAF400UL) +#define FMC_R_BASE_S (AHB2PERIPH_BASE_S + 0xB0400UL) /*!< FMC control registers base address */ +#define HSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB3400UL) +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_S (AHB2PERIPH_BASE_S + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1300UL) +#define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) +#define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL) +#define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL) +#define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL) +#define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL) +#define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL) +#define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) +#define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) + +/* GFXMMU secure virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE_S (0x34000000UL) +#define GFXMMU_VIRTUAL_BUFFER0_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S) +#define GFXMMU_VIRTUAL_BUFFER1_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0x400000UL) +#define GFXMMU_VIRTUAL_BUFFER2_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0x800000UL) +#define GFXMMU_VIRTUAL_BUFFER3_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0xC00000UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0044000UL) +#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ +#define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */ + +/* USB OTG registers Base address */ +#define USB_OTG_GLOBAL_BASE (0x0000UL) +#define USB_OTG_DEVICE_BASE (0x0800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) +#define USB_OTG_EP_REG_SIZE (0x0020UL) +#define USB_OTG_HOST_BASE (0x0400UL) +#define USB_OTG_HOST_PORT_BASE (0x0440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) +#define USB_OTG_PCGCCTL_BASE (0x0E00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0U) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0U) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1U) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) +#define USART6_NS ((USART_TypeDef *) USART6_BASE_NS) +#define I2C5_NS ((I2C_TypeDef *) I2C5_BASE_NS) +#define I2C6_NS ((I2C_TypeDef *) I2C6_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) +#define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS) +#define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS) +#define LTDC_NS ((LTDC_TypeDef *) LTDC_BASE_NS) +#define LTDC_Layer1_NS ((LTDC_Layer_TypeDef *) LTDC_Layer1_BASE_NS) +#define LTDC_Layer2_NS ((LTDC_Layer_TypeDef *) LTDC_Layer2_BASE_NS) +#define DSI_NS ((DSI_TypeDef *) DSI_BASE_NS) +#define REFBIAS_NS ((REFBIAS_TypeDef *) REFBIAS_BASE_NS) +#define DPHY_NS ((DPHY_TypeDef *) DPHY_BASE_NS) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) +#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS) +#define RAMCFG_SRAM5_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define DCACHE2_NS ((DCACHE_TypeDef *) DCACHE2_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GTZC_MPCBB5_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_NS) +#define GFXMMU_NS ((GFXMMU_TypeDef *) GFXMMU_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GPIOI_NS ((GPIO_TypeDef *) GPIOI_BASE_NS) +#define GPIOJ_NS ((GPIO_TypeDef *) GPIOJ_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define USB_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) +#define DLYB_OCTOSPI2_NS ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_NS) +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS) +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define OCTOSPI2_NS ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS) +#define HSPI1_NS ((HSPI_TypeDef *) HSPI1_R_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS) +#define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS) +#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) +#define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS) +#define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS) +#define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS) +#define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS) +#define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) +#define USART6_S ((USART_TypeDef *) USART6_BASE_S) +#define I2C5_S ((I2C_TypeDef *) I2C5_BASE_S) +#define I2C6_S ((I2C_TypeDef *) I2C6_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) + +/*!< APB2 Secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) +#define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S) +#define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S) +#define LTDC_S ((LTDC_TypeDef *) LTDC_BASE_S) +#define LTDC_Layer1_S ((LTDC_Layer_TypeDef *) LTDC_Layer1_BASE_S) +#define LTDC_Layer2_S ((LTDC_Layer_TypeDef *) LTDC_Layer2_BASE_S) +#define DSI_S ((DSI_TypeDef *) DSI_BASE_S) +#define REFBIAS_S ((REFBIAS_TypeDef *) REFBIAS_BASE_S) +#define DPHY_S ((DPHY_TypeDef *) DPHY_BASE_S) + +/*!< APB3 secure peripherals */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) +#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) +#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S) +#define RAMCFG_SRAM5_S ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define DCACHE2_S ((DCACHE_TypeDef *) DCACHE2_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GTZC_MPCBB5_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_S) +#define GFXMMU_S ((GFXMMU_TypeDef *) GFXMMU_BASE_S) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GPIOI_S ((GPIO_TypeDef *) GPIOI_BASE_S) +#define GPIOJ_S ((GPIO_TypeDef *) GPIOJ_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define USB_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) +#define DLYB_OCTOSPI2_S ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_S) +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S) +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define OCTOSPI2_S ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S) +#define HSPI1_S ((HSPI_TypeDef *) HSPI1_R_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S) +#define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S) +#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) +#define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S) +#define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S) +#define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S) +#define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S) +#define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S) + +/*!< DBGMCU peripheral */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define SRAM4_BASE SRAM4_BASE_S +#define SRAM5_BASE SRAM5_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define FMAC FMAC_S +#define FMAC_BASE FMAC_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define LPDMA1 LPDMA1_S +#define LPDMA1_BASE LPDMA1_BASE_S + +#define LPDMA1_Channel0 LPDMA1_Channel0_S +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S + +#define LPDMA1_Channel1 LPDMA1_Channel1_S +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S + +#define LPDMA1_Channel2 LPDMA1_Channel2_S +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S + +#define LPDMA1_Channel3 LPDMA1_Channel3_S +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define GPIOI GPIOI_S +#define GPIOI_BASE GPIOI_BASE_S + +#define GPIOJ GPIOJ_S +#define GPIOJ_BASE GPIOJ_BASE_S + +#define LPGPIO1 LPGPIO1_S +#define LPGPIO1_BASE LPGPIO1_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_S +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_S +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define DCACHE2 DCACHE2_S +#define DCACHE2_BASE DCACHE2_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZSC2 GTZC_TZSC2_S +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_TZIC2 GTZC_TZIC2_S +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define GTZC_MPCBB4 GTZC_MPCBB4_S +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S + +#define GTZC_MPCBB5 GTZC_MPCBB5_S +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define I2C5 I2C5_S +#define I2C5_BASE I2C5_BASE_S + +#define I2C6 I2C6_S +#define I2C6_BASE I2C6_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define DAC DAC_S +#define DAC_BASE DAC_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define OPAMP OPAMP_S +#define OPAMP_BASE OPAMP_BASE_S + +#define OPAMP1 OPAMP1_S +#define OPAMP1_BASE OPAMP1_BASE_S + +#define OPAMP2 OPAMP2_S +#define OPAMP2_BASE OPAMP2_BASE_S + +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define COMP12 COMP12_S +#define COMP12_BASE COMP12_BASE_S + +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S + +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S + +#define COMP12_COMMON COMP12_COMMON_S +#define COMP12_COMMON_BASE COMP1_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + +#define SAI2 SAI2_S +#define SAI2_BASE SAI2_BASE_S + +#define SAI2_Block_A SAI2_Block_A_S +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S + +#define SAI2_Block_B SAI2_Block_B_S +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + + +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S + +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + +#define SDMMC2 SDMMC2_S +#define SDMMC2_BASE SDMMC2_BASE_S + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define OCTOSPI2 OCTOSPI2_S +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_S + +#define OCTOSPIM OCTOSPIM_S +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_SDMMC2 DLYB_SDMMC2_S +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_S +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_S + +#define HSPI1 HSPI1_S +#define HSPI1_R_BASE HSPI1_R_BASE_S + +#define DMA2D DMA2D_S +#define DMA2D_BASE DMA2D_BASE_S + +#define USB_OTG_HS USB_OTG_HS_S +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_S + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#define GFXMMU GFXMMU_S +#define GFXMMU_BASE GFXMMU_BASE_S +/* GFXMMU virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE GFXMMU_VIRTUAL_BUFFERS_BASE_S +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_S +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_S +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_S +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_S + +#define GPU2D GPU2D_BASE_S + +#define LTDC LTDC_S +#define LTDC_BASE LTDC_BASE_S + +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_S +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_S + +#define DSI DSI_S +#define DSI_BASE DSI_BASE_S + +#define REFBIAS REFBIAS_S +#define REFBIAS_BASE REFBIAS_BASE_S + +#define DPHY DPHY_S +#define DPHY_BASE DPHY_BASE_S + +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM3_BASE SRAM3_BASE_NS +#define SRAM4_BASE SRAM4_BASE_NS +#define SRAM5_BASE SRAM5_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DMA2D DMA2D_NS +#define DMA2D_BASE DMA2D_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define FMAC FMAC_NS +#define FMAC_BASE FMAC_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define LPDMA1 LPDMA1_NS +#define LPDMA1_BASE LPDMA1_BASE_NS + +#define LPDMA1_Channel0 LPDMA1_Channel0_NS +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS + +#define LPDMA1_Channel1 LPDMA1_Channel1_NS +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS + +#define LPDMA1_Channel2 LPDMA1_Channel2_NS +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS + +#define LPDMA1_Channel3 LPDMA1_Channel3_NS +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define GPIOI GPIOI_NS +#define GPIOI_BASE GPIOI_BASE_NS +#define GPIOJ GPIOJ_NS +#define GPIOJ_BASE GPIOJ_BASE_NS + +#define LPGPIO1 LPGPIO1_NS +#define LPGPIO1_BASE LPGPIO1_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_NS +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_NS +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define DCACHE2 DCACHE2_NS +#define DCACHE2_BASE DCACHE2_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZSC2 GTZC_TZSC2_NS +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_TZIC2 GTZC_TZIC2_NS +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define GTZC_MPCBB4 GTZC_MPCBB4_NS +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS + +#define GTZC_MPCBB5 GTZC_MPCBB5_NS +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define I2C5 I2C5_NS +#define I2C5_BASE I2C5_BASE_NS + +#define I2C6 I2C6_NS +#define I2C6_BASE I2C6_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define OPAMP OPAMP_NS +#define OPAMP_BASE OPAMP_BASE_NS + +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS + +#define OPAMP2 OPAMP2_NS +#define OPAMP2_BASE OPAMP2_BASE_NS + +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define COMP12 COMP12_NS +#define COMP12_BASE COMP12_BASE_NS + +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS + +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS + +#define COMP12_COMMON COMP12_COMMON_NS +#define COMP12_COMMON_BASE COMP1_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + +#define SAI2 SAI2_NS +#define SAI2_BASE SAI2_BASE_NS + +#define SAI2_Block_A SAI2_Block_A_NS +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS + +#define SAI2_Block_B SAI2_Block_B_NS +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS + +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + +#define SDMMC2 SDMMC2_NS +#define SDMMC2_BASE SDMMC2_BASE_NS + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define OCTOSPI2 OCTOSPI2_NS +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_NS + +#define OCTOSPIM OCTOSPIM_NS +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_SDMMC2 DLYB_SDMMC2_NS +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_NS +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_NS + +#define HSPI1 HSPI1_NS +#define HSPI1_R_BASE HSPI1_R_BASE_NS + +#define USB_OTG_HS USB_OTG_HS_NS +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_NS + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS +#define GFXMMU GFXMMU_NS +#define GFXMMU_BASE GFXMMU_BASE_NS +/* GFXMMU virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE GFXMMU_VIRTUAL_BUFFERS_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_NS + +#define GPU2D GPU2D_BASE_NS + +#define LTDC LTDC_NS +#define LTDC_BASE LTDC_BASE_NS + +#define LTDC_Layer1 LTDC_Layer1_NS +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_NS + +#define LTDC_Layer2 LTDC_Layer2_NS +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_NS + +#define DSI DSI_NS +#define DSI_BASE DSI_BASE_NS + +#define REFBIAS REFBIAS_NS +#define REFBIAS_BASE REFBIAS_BASE_NS + +#define DPHY DPHY_NS +#define DPHY_BASE DPHY_BASE_NS + +#endif + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +#define ADC_MULTIMODE_SUPPORT +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ +#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_ADCALLIN_Pos (16U) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ + +#define ADC_CR_CALINDEX_Pos (24U) +#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ +#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ +#define ADC_CR_CALINDEX0_Pos (24U) +#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ +#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ +#define ADC_CR_CALINDEX1_Pos (25U) +#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ +#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ +#define ADC_CR_CALINDEX2_Pos (26U) +#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ +#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ +#define ADC_CR_CALINDEX3_Pos (27U) +#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ +#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR1_DMNGT_Pos (0U) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC4_CFGR1_DMAEN_Pos (0U) +#define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC4_CFGR1_DMACFG_Pos (1U) +#define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC4_CFGR1_SCANDIR_Pos (4U) +#define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC4_CFGR1_ALIGN_Pos (5U) +#define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (5U) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ + +#define ADC_CFGR1_AUTDLY_Pos (14U) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC4_CFGR1_WAIT_Pos (14U) +#define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR1_DISCNUM_Pos (17U) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20U) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR1_JAWD1EN_Pos (24U) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR1_JAUTO_Pos (25U) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +/* Specific ADC4 */ +#define ADC4_CFGR1_EXTSEL_Pos (6U) +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ + +#define ADC4_CFGR1_CHSELRMOD_Pos (21U) +#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_BULB_Pos (13U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (27U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* Specific ADC4 */ +#define ADC4_CFGR2_OVSR_Pos (2U) +#define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC4_CFGR2_LFTRIG_Pos (29U) +#define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC4_SMPR_SMP1_Pos (0U) +#define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC4_SMPR_SMP2_Pos (4U) +#define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC4_SMPR_SMPSEL_Pos (8U) +#define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ +#define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ +#define ADC4_SMPR_SMPSEL0_Pos (8U) +#define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ +#define ADC4_SMPR_SMPSEL1_Pos (9U) +#define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ +#define ADC4_SMPR_SMPSEL2_Pos (10U) +#define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ +#define ADC4_SMPR_SMPSEL3_Pos (11U) +#define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ +#define ADC4_SMPR_SMPSEL4_Pos (12U) +#define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ +#define ADC4_SMPR_SMPSEL5_Pos (13U) +#define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ +#define ADC4_SMPR_SMPSEL6_Pos (14U) +#define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ +#define ADC4_SMPR_SMPSEL7_Pos (15U) +#define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ +#define ADC4_SMPR_SMPSEL8_Pos (16U) +#define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ +#define ADC4_SMPR_SMPSEL9_Pos (17U) +#define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ +#define ADC4_SMPR_SMPSEL10_Pos (18U) +#define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ +#define ADC4_SMPR_SMPSEL11_Pos (19U) +#define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ +#define ADC4_SMPR_SMPSEL12_Pos (20U) +#define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ +#define ADC4_SMPR_SMPSEL13_Pos (21U) +#define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ +#define ADC4_SMPR_SMPSEL14_Pos (22U) +#define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ +#define ADC4_SMPR_SMPSEL15_Pos (23U) +#define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ +#define ADC4_SMPR_SMPSEL16_Pos (24U) +#define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ +#define ADC4_SMPR_SMPSEL17_Pos (25U) +#define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ +#define ADC4_SMPR_SMPSEL18_Pos (26U) +#define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ +#define ADC4_SMPR_SMPSEL19_Pos (27U) +#define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ +#define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ +#define ADC4_SMPR_SMPSEL20_Pos (26U) +#define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ +#define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL21_Pos (26U) +#define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ +#define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL22_Pos (30U) +#define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ +#define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ +#define ADC4_SMPR_SMPSEL23_Pos (31U) +#define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ +#define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +#define ADC_HTR_AWDFILT_Pos (29U) +#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ +#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_PW register ********************/ +#define ADC4_PWRR_AUTOFF_Pos (0U) +#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ +#define ADC4_PWRR_DPD_Pos (1U) +#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ +#define ADC4_PWRR_VREFPROT_Pos (2U) +#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ +#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ +#define ADC4_PWRR_VREFSECSMP_Pos (3U) +#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ +#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ + +/* Legacy definitions */ +#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos +#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk +#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF +#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos +#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk +#define ADC4_PW_DPD ADC4_PWRR_DPD +#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos +#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk +#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT +#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos +#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk +#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_USAT_Pos (25U) +#define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_SSAT_Pos (26U) +#define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (27U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR2_USAT_Pos (25U) +#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR2_SSAT_Pos (26U) +#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (27U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR3_USAT_Pos (25U) +#define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR3_SSAT_Pos (26U) +#define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (27U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR4_USAT_Pos (25U) +#define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR4_SSAT_Pos (26U) +#define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (27U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_GCOMP register ********************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ +#define ADC_GCOMP_GCOMP_Pos (31U) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19U) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20U) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21U) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22U) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL23_Pos (23U) +#define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_I_APB_ADDR_Pos (0U) +#define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ +#define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ + +#define ADC_CALFACT_I_APB_DATA_Pos (08U) +#define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ +#define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ + +#define ADC_CALFACT_VALIDITY_Pos (16U) +#define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_LATCH_COEF_Pos (24U) +#define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CAPTURE_COEF_Pos (25U) +#define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ + +#define ADC4_CALFACT_CALFACT_Pos (0U) +#define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_CALFACT_Pos (0U) +#define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */ +#define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */ +#define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OR register ********************/ +#define ADC_OR_CHN0SEL_Pos (0U) +#define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ +#define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_LDORDY_MST_Pos (12U) +#define ADC_CSR_LDORDY_MST_Msk (0x1UL << ADC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADC_CSR_LDORDY_MST ADC_CSR_LDORDY_MST_Msk /*!< Voltage regulator ready flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_LDORDY_SLV_Pos (28U) +#define ADC_CSR_LDORDY_SLV_Msk (0x1UL << ADC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CSR_LDORDY_SLV ADC_CSR_LDORDY_SLV_Msk /*!< Voltage regulator ready flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DAMDF_Pos (14U) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_VSENSEEN_Pos (23U) +#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ +#define ADC_CCR_VDDCOREN_Pos (26U) +#define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ +#define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0U) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) + +#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ + +#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11U) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ1_Pos (12U) +#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */ +#define FLASH_ACR_PDREQ2_Pos (13U) +#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */ +#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14U) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0U) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1U) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3U) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4U) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5U) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6U) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7U) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13U) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16U) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17U) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18U) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19U) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD1_Pos (20U) +#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */ +#define FLASH_NSSR_PD2_Pos (21U) +#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */ +#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0U) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1U) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3U) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4U) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5U) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6U) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7U) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16U) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17U) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR register *****************/ +#define FLASH_NSCR_PG_Pos (0U) +#define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR_PER_Pos (1U) +#define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR_MER1_Pos (2U) +#define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */ +#define FLASH_NSCR_PNB_Pos (3U) +#define FLASH_NSCR_PNB_Msk (0xFFUL << FLASH_NSCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR_BKER_Pos (11U) +#define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */ +#define FLASH_NSCR_BWR_Pos (14U) +#define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR_MER2_Pos (15U) +#define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */ +#define FLASH_NSCR_STRT_Pos (16U) +#define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR_OPTSTRT_Pos (17U) +#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR_EOPIE_Pos (24U) +#define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR_ERRIE_Pos (25U) +#define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR_OBL_LAUNCH_Pos (27U) +#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR_OPTLOCK_Pos (30U) +#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR_LOCK_Pos (31U) +#define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR register ****************/ +#define FLASH_SECCR_PG_Pos (0U) +#define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR_PER_Pos (1U) +#define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR_MER1_Pos (2U) +#define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR_PNB_Pos (3U) +#define FLASH_SECCR_PNB_Msk (0xFFUL << FLASH_SECCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR_BKER_Pos (11U) +#define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */ +#define FLASH_SECCR_BWR_Pos (14U) +#define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR_MER2_Pos (15U) +#define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */ +#define FLASH_SECCR_STRT_Pos (16U) +#define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR_EOPIE_Pos (24U) +#define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR_ERRIE_Pos (25U) +#define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR_INV_Pos (29U) +#define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR_LOCK_Pos (31U) +#define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0x1FFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x001FFFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_BK_ECC_Pos (21U) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (22U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0x1FFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x001FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */ +#define FLASH_OPSR_BK_OP_Pos (21U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (22U) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8U) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_nRST_SHDW_Pos (14U) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ +#define FLASH_OPTR_SRAM_RST_Pos (15U) +#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SWAP_BANK_Pos (20U) +#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */ +#define FLASH_OPTR_DUALBANK_Pos (21U) +#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */ +#define FLASH_OPTR_BKPRAM_ECC_Pos (22U) +#define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTR_SRAM3_ECC_Pos (23U) +#define FLASH_OPTR_SRAM3_ECC_Msk (0x1UL << FLASH_OPTR_SRAM3_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_SRAM3_ECC FLASH_OPTR_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */ +#define FLASH_OPTR_SRAM2_ECC_Pos (24U) +#define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25U) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26U) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_PA15_PUPEN_Pos (28U) +#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */ +#define FLASH_OPTR_IO_VDD_HSLV_Pos (29U) +#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */ +#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30U) +#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */ +#define FLASH_OPTR_TZEN_Pos (31U) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7U) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7U) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0U) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7U) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWM1R1 register **************/ +#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0U) +#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16U) +#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWM1R2 register **************/ +#define FLASH_SECWM1R2_HDP1_PEND_Pos (16U) +#define FLASH_SECWM1R2_HDP1_PEND_Msk (0xFFUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWM1R2_HDP1EN_Pos (31U) +#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0U) +#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */ +#define FLASH_WRP1AR_WRP1A_PEND_Pos (16U) +#define FLASH_WRP1AR_WRP1A_PEND_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */ +#define FLASH_WRP1AR_UNLOCK_Pos (31U) +#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0U) +#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */ +#define FLASH_WRP1BR_WRP1B_PEND_Pos (16U) +#define FLASH_WRP1BR_WRP1B_PEND_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */ +#define FLASH_WRP1BR_UNLOCK_Pos (31U) +#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */ + +/***************** Bits definition for FLASH_SECWM2R1 register **************/ +#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0U) +#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */ +#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16U) +#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */ + +/***************** Bits definition for FLASH_SECWM2R2 register **************/ +#define FLASH_SECWM2R2_HDP2_PEND_Pos (16U) +#define FLASH_SECWM2R2_HDP2_PEND_Msk (0xFFUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */ +#define FLASH_SECWM2R2_HDP2EN_Pos (31U) +#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */ + +/****************** Bits definition for FLASH_WRP2AR register ***************/ +#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0U) +#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */ +#define FLASH_WRP2AR_WRP2A_PEND_Pos (16U) +#define FLASH_WRP2AR_WRP2A_PEND_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */ +#define FLASH_WRP2AR_UNLOCK_Pos (31U) +#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP2BR register ***************/ +#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0U) +#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */ +#define FLASH_WRP2BR_WRP2B_PEND_Pos (16U) +#define FLASH_WRP2BR_WRP2B_PEND_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */ +#define FLASH_WRP2BR_UNLOCK_Pos (31U) +#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0U) +#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */ +#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1U) +#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */ +#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0U) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1U) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************************************************************************/ +/* */ +/* Filter Mathematical ACcelerator unit (FMAC) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1_BASE_Pos (0U) +#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U) +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ +#define FMAC_X1BUFCFG_FULL_WM_Pos (24U) +#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ +#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ + +/***************** Bit definition for FMAC_X2BUFCFG register ****************/ +#define FMAC_X2BUFCFG_X2_BASE_Pos (0U) +#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U) +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ + +/***************** Bit definition for FMAC_YBUFCFG register *****************/ +#define FMAC_YBUFCFG_Y_BASE_Pos (0U) +#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ +#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U) +#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ +#define FMAC_YBUFCFG_EMPTY_WM_Pos (24U) +#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ +#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ + +/****************** Bit definition for FMAC_PARAM register ******************/ +#define FMAC_PARAM_P_Pos (0U) +#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ +#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ +#define FMAC_PARAM_Q_Pos (8U) +#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ +#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ +#define FMAC_PARAM_R_Pos (16U) +#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ +#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ +#define FMAC_PARAM_FUNC_Pos (24U) +#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ +#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ +#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ +#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ +#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ +#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ +#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ +#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ +#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ +#define FMAC_PARAM_START_Pos (31U) +#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ +#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ + +/******************** Bit definition for FMAC_CR register *******************/ +#define FMAC_CR_RIEN_Pos (0U) +#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ +#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ +#define FMAC_CR_WIEN_Pos (1U) +#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ +#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ +#define FMAC_CR_OVFLIEN_Pos (2U) +#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ +#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ +#define FMAC_CR_UNFLIEN_Pos (3U) +#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ +#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ +#define FMAC_CR_SATIEN_Pos (4U) +#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ +#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ +#define FMAC_CR_DMAREN_Pos (8U) +#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ +#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ +#define FMAC_CR_DMAWEN_Pos (9U) +#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ +#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ +#define FMAC_CR_CLIPEN_Pos (15U) +#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ +#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ +#define FMAC_CR_RESET_Pos (16U) +#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ +#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_SR register ********************/ +#define FMAC_SR_YEMPTY_Pos (0U) +#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ +#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ +#define FMAC_SR_X1FULL_Pos (1U) +#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ +#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ +#define FMAC_SR_OVFL_Pos (8U) +#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ +#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ +#define FMAC_SR_UNFL_Pos (9U) +#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ +#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ +#define FMAC_SR_SAT_Pos (10U) +#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ +#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ + +/****************** Bit definition for FMAC_WDATA register ******************/ +#define FMAC_WDATA_WDATA_Pos (0U) +#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ + +/****************** Bit definition for FMACX_RDATA register *****************/ +#define FMAC_RDATA_RDATA_Pos (0U) +#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20U) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk + +/******************** Bits definition for TAMP_COUNTR register ***************/ +#define TAMP_COUNTR_Pos (16U) +#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ +#define TAMP_COUNTR TAMP_COUNTR_Msk + +/******************** Bits definition for TAMP_ERCFGR register ***************/ +#define TAMP_ERCFGR0_Pos (0U) +#define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* Touch Sensing Controller (TSC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TSC_CR register *********************/ +#define TSC_CR_TSCE_Pos (0U) +#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ +#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32u5xx.h" /*!< STM32U5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ + uint32_t RESERVED3[246]; /*!< Reserved, */ + __IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */ + __IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; +} I2C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, 0x24 */ + __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FC */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FC */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFC */ +} DMA2D_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ + __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */ + __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */ + __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */ + __IO uint32_t SECBB1R5; /*!< FLASH secure block-based bank 1 register 5, Address offset: 0x90 */ + __IO uint32_t SECBB1R6; /*!< FLASH secure block-based bank 1 register 6, Address offset: 0x94 */ + __IO uint32_t SECBB1R7; /*!< FLASH secure block-based bank 1 register 7, Address offset: 0x98 */ + __IO uint32_t SECBB1R8; /*!< FLASH secure block-based bank 1 register 8, Address offset: 0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */ + __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */ + __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */ + __IO uint32_t SECBB2R5; /*!< FLASH secure block-based bank 2 register 5, Address offset: 0xB0 */ + __IO uint32_t SECBB2R6; /*!< FLASH secure block-based bank 2 register 6, Address offset: 0xB4 */ + __IO uint32_t SECBB2R7; /*!< FLASH secure block-based bank 2 register 7, Address offset: 0xB8 */ + __IO uint32_t SECBB2R8; /*!< FLASH secure block-based bank 2 register 8, Address offset: 0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */ + __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */ + __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */ + __IO uint32_t PRIVBB1R5; /*!< FLASH privilege block-based bank 1 register 5, Address offset: 0xE0 */ + __IO uint32_t PRIVBB1R6; /*!< FLASH privilege block-based bank 1 register 6, Address offset: 0xE4 */ + __IO uint32_t PRIVBB1R7; /*!< FLASH privilege block-based bank 1 register 7, Address offset: 0xE8 */ + __IO uint32_t PRIVBB1R8; /*!< FLASH privilege block-based bank 1 register 8, Address offset: 0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */ + __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */ + __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */ + __IO uint32_t PRIVBB2R5; /*!< FLASH privilege block-based bank 2 register 5, Address offset: 0x100 */ + __IO uint32_t PRIVBB2R6; /*!< FLASH privilege block-based bank 2 register 6, Address offset: 0x104 */ + __IO uint32_t PRIVBB2R7; /*!< FLASH privilege block-based bank 2 register 7, Address offset: 0x108 */ + __IO uint32_t PRIVBB2R8; /*!< FLASH privilege block-based bank 2 register 8, Address offset: 0x10C */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */ + __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */ + __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */ + __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */ + __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */ + __IO uint32_t MPCWM6ACFGR; /*!< TZSC memory 6 sub-region A watermark configuration register, Address offset: 0x90 */ + __IO uint32_t MPCWM6AR; /*!< TZSC memory 6 sub-region A watermark register, Address offset: 0x94 */ + __IO uint32_t MPCWM6BCFGR; /*!< TZSC memory 6 sub-region B watermark configuration register, Address offset: 0x98 */ + __IO uint32_t MPCWM6BR; /*!< TZSC memory 6 sub-region B watermark register, Address offset: 0x9C */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register 1, Address offset: 0x10 */ + __IO uint32_t CFGLOCKR2; /*!< MPCBBx Configuration lock register 2, Address offset: 0x14 */ + uint32_t RESERVED2[58]; /*!< Reserved2, Address offset: 0x18-0xFC */ + __IO uint32_t SECCFGR[52]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x1CC */ + uint32_t RESERVED3[12]; /*!< Reserved3, Address offset: 0x1D0-0x1FC */ + __IO uint32_t PRIVCFGR[52]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x2CC */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ + uint32_t RESERVED2[240]; /*!< Reserved, Address offset: 0x30-0x3EC */ + __IO uint32_t HWCFGR; /*!< ICACHE HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< ICACHE version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ICACHE IP identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ICACHE size identification register, Address offset: 0x3FC */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + + +/** + * @brief MDF/ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ +}MDF_TypeDef; + +/** + * @brief MDF/ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ + __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ + __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ + __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ + __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief HEXA and OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ + uint32_t RESERVED22[3]; /*!< Reserved, Address offset: 0x204-0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-cycle calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x210 */ + uint32_t RESERVED23; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL master calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x218 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI slave output calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x220 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI slave input calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x228 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + +typedef XSPI_TypeDef HSPI_TypeDef; + +/** + * @brief OTFDEC register + */ +typedef struct +{ + __IO uint32_t REG_CONFIGR; /*!< OTFDEC Region Configuration register, Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_START_ADDR; /*!< OTFDEC Region Start Address register, Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_END_ADDR; /*!< OTFDEC Region End Address register, Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER0; /*!< OTFDEC Region Nonce register 0, Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER1; /*!< OTFDEC Region Nonce register 1, Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR0; /*!< OTFDEC Region Key register 0, Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR1; /*!< OTFDEC Region Key register 1, Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR2; /*!< OTFDEC Region Key register 2, Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR3; /*!< OTFDEC Region Key register 3, Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4) */ +} OTFDEC_Region_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< OTFDEC Control register, Address offset: 0x000 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x004-0x00C */ + __IO uint32_t PRIVCFGR; /*!< OTFDEC Privileged access control Configuration register, Address offset: 0x010 */ + uint32_t RESERVED2[187]; /*!< Reserved, Address offset: 0x014-0x2FC */ + __IO uint32_t ISR; /*!< OTFDEC Interrupt Status register, Address offset: 0x300 */ + __IO uint32_t ICR; /*!< OTFDEC Interrupt Clear register, Address offset: 0x304 */ + __IO uint32_t IER; /*!< OTFDEC Interrupt Enable register, Address offset: 0x308 */ +} OTFDEC_TypeDef; + + +/** + * @brief Serial Peripheral Interface IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPIM IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[8]; /*!< OCTOSPIM IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ +} XSPIM_TypeDef; + +typedef XSPIM_TypeDef OCTOSPIM_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x20 */ + __IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Power USB Type-C and Power Delivery register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + __IO uint32_t BDSR; /*!< Power backup domain status register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */ + __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ + __IO uint32_t PUCRI; /*!< Power Port I pull-up control register, Address offset: 0x90 */ + __IO uint32_t PDCRI; /*!< Power Port I pull-down control register, Address offset: 0x94 */ + __IO uint32_t PUCRJ; /*!< Power Port J pull-up control register, Address offset: 0x98 */ + __IO uint32_t PDCRJ; /*!< Power Port J pull-down control register, Address offset: 0x9C */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x0A0-0x0A4 */ + __IO uint32_t CR4; /*!< Power power control register 4, Address offset: 0xA8 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */ + __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */ + __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */ + __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */ + __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */ + __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */ + __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */ + __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */ + __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */ + __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */ + __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */ + uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + uint32_t RESERVED2[17];/*!< RESERVED2, Address offset: 0x30 - 0x70 */ + __IO uint32_t OTGHSPHYCR; /*!< SYSCFG USB OTG_HS PHY register Address offset: 0x74 */ + uint32_t RESERVED3; /*!< RESERVED3, Address offset: 0x78 */ + __IO uint32_t OTGHSPHYTUNER2;/*!< SYSCFG USB OTG_HS PHY tune register 2 Address offset: 0x7C */ +} SYSCFG_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief Flexible Memory Controller + */ +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief ADC + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ /* Specific to ADC 14Bits*/ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t AWD1TR; /*!< ADC watchdog threshold register, Address offset: 0x20 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ /* Specific to ADC 12Bits*/ + __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x2C */ /* Specific to ADC 12Bits*/ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ /* Specific to ADC 14Bits*/ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ + uint32_t RESERVED1; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ /* Specific to ADC 14Bits*/ + __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED3[3]; /*!< Reserved, 0x074 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED4[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0xA8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0xAC */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ /* Specific to ADC 14Bits*/ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED5; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0xD0 */ /* Specific to ADC 12Bits*/ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode, Address offset: 0x310 */ +} ADC_Common_TypeDef; + + +/* Legacy registers naming */ +#define PW PWRR + +/** + * @brief CORDIC + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief Touch Sensing Controller (TSC) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ +} TSC_TypeDef; + +/** + * @brief WWDG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32U5xx_peripherals */ + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0xC0000UL) /*!< SRAM1=768k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ +#define SRAM3_SIZE (0xD0000UL) /*!< SRAM3=832k */ +#define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */ +#define SRAM5_SIZE (0xD0000UL) /*!< SRAM5=832k */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< OCTOSPI2 memories accessible over AHB base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ +#define HSPI1_BASE (0xA0000000UL) /*!< HSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (4 MB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (768 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x200C0000UL) /*!< SRAM2 (64 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x200D0000UL) /*!< SRAM3 (832 KB) non-secure base address */ +#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */ +#define SRAM5_BASE_NS (0x201A0000UL) /*!< SRAM5 (832 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define I2C5_BASE_NS (APB1PERIPH_BASE_NS + 0x9800UL) +#define I2C6_BASE_NS (APB1PERIPH_BASE_NS + 0x9C00UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) +#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) +#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x004UL) +#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x024UL) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) +#define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP2_BASE_NS (APB3PERIPH_BASE_NS + 0x5010UL) +#define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define RAMCFG_SRAM5_BASE_NS (RAMCFG_BASE_NS + 0x0140UL) +#define DMA2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0B000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define GTZC_MPCBB5_BASE_NS (AHB1PERIPH_BASE_NS + 0x13800UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define GPIOI_BASE_NS (AHB2PERIPH_BASE_NS + 0x02000UL) +#define GPIOJ_BASE_NS (AHB2PERIPH_BASE_NS + 0x02400UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define USB_OTG_HS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL) +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) +#define OCTOSPIM_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xA4000UL) /*!< OCTOSPIO Manager control registers base address */ +#define OTFDEC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5000UL) +#define OTFDEC1_REGION1_BASE_NS (OTFDEC1_BASE_NS + 0x20UL) +#define OTFDEC1_REGION2_BASE_NS (OTFDEC1_BASE_NS + 0x50UL) +#define OTFDEC1_REGION3_BASE_NS (OTFDEC1_BASE_NS + 0x80UL) +#define OTFDEC1_REGION4_BASE_NS (OTFDEC1_BASE_NS + 0xB0UL) +#define OTFDEC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5400UL) +#define OTFDEC2_REGION1_BASE_NS (OTFDEC2_BASE_NS + 0x20UL) +#define OTFDEC2_REGION2_BASE_NS (OTFDEC2_BASE_NS + 0x50UL) +#define OTFDEC2_REGION3_BASE_NS (OTFDEC2_BASE_NS + 0x80UL) +#define OTFDEC2_REGION4_BASE_NS (OTFDEC2_BASE_NS + 0xB0UL) +#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL) +#define SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL) +#define DLYB_SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF400UL) +#define FMC_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB0400UL) /*!< FMC control registers base address */ +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ +#define HSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB3400UL) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS) +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1300UL) +#define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL) +#define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL) +#define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL) +#define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL) +#define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL) +#define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL) +#define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL) +#define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL) +#define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (4 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (768 KB) secure base address */ +#define SRAM2_BASE_S (0x300C0000UL) /*!< SRAM2 (64 KB) secure base address */ +#define SRAM3_BASE_S (0x300D0000UL) /*!< SRAM3 (832 KB) secure base address */ +#define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */ +#define SRAM5_BASE_S (0x301A0000UL) /*!< SRAM5 (832 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define I2C5_BASE_S (APB1PERIPH_BASE_S + 0x9800UL) +#define I2C6_BASE_S (APB1PERIPH_BASE_S + 0x9C00UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) +#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) +#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x004UL) +#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x024UL) + +/*!< APB3 Secure peripherals */ +#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) +#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP2_BASE_S (APB3PERIPH_BASE_S + 0x5010UL) +#define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define COMP2_BASE_S (COMP12_BASE_S + 0x04UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define RAMCFG_SRAM5_BASE_S (RAMCFG_BASE_S + 0x0140UL) +#define DMA2D_BASE_S (AHB1PERIPH_BASE_S + 0x0B000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define GTZC_MPCBB5_BASE_S (AHB1PERIPH_BASE_S + 0x13800UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define GPIOI_BASE_S (AHB2PERIPH_BASE_S + 0x02000UL) +#define GPIOJ_BASE_S (AHB2PERIPH_BASE_S + 0x02400UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define USB_OTG_HS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL) +#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) +#define OTFDEC1_BASE_S (AHB2PERIPH_BASE_S + 0xA5000UL) +#define OTFDEC1_REGION1_BASE_S (OTFDEC1_BASE_S + 0x20UL) +#define OTFDEC1_REGION2_BASE_S (OTFDEC1_BASE_S + 0x50UL) +#define OTFDEC1_REGION3_BASE_S (OTFDEC1_BASE_S + 0x80UL) +#define OTFDEC1_REGION4_BASE_S (OTFDEC1_BASE_S + 0xB0UL) +#define OTFDEC2_BASE_S (AHB2PERIPH_BASE_S + 0xA5400UL) +#define OTFDEC2_REGION1_BASE_S (OTFDEC2_BASE_S + 0x20UL) +#define OTFDEC2_REGION2_BASE_S (OTFDEC2_BASE_S + 0x50UL) +#define OTFDEC2_REGION3_BASE_S (OTFDEC2_BASE_S + 0x80UL) +#define OTFDEC2_REGION4_BASE_S (OTFDEC2_BASE_S + 0xB0UL) +#define OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */ +#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) +#define SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) +#define DLYB_SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_S (AHB2PERIPH_BASE_S + 0xAF400UL) +#define FMC_R_BASE_S (AHB2PERIPH_BASE_S + 0xB0400UL) /*!< FMC control registers base address */ +#define HSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB3400UL) +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_S (AHB2PERIPH_BASE_S + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1300UL) +#define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) +#define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL) +#define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL) +#define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL) +#define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL) +#define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL) +#define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) +#define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) + + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0044000UL) +#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ +#define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */ + +/* USB OTG registers Base address */ +#define USB_OTG_GLOBAL_BASE (0x0000UL) +#define USB_OTG_DEVICE_BASE (0x0800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) +#define USB_OTG_EP_REG_SIZE (0x0020UL) +#define USB_OTG_HOST_BASE (0x0400UL) +#define USB_OTG_HOST_PORT_BASE (0x0440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) +#define USB_OTG_PCGCCTL_BASE (0x0E00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0U) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0U) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1U) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) +#define USART6_NS ((USART_TypeDef *) USART6_BASE_NS) +#define I2C5_NS ((I2C_TypeDef *) I2C5_BASE_NS) +#define I2C6_NS ((I2C_TypeDef *) I2C6_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) +#define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS) +#define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) +#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS) +#define RAMCFG_SRAM5_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GTZC_MPCBB5_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GPIOI_NS ((GPIO_TypeDef *) GPIOI_BASE_NS) +#define GPIOJ_NS ((GPIO_TypeDef *) GPIOJ_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define USB_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define OTFDEC1_NS ((OTFDEC_TypeDef *) OTFDEC1_BASE_NS) +#define OTFDEC1_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_NS) +#define OTFDEC1_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_NS) +#define OTFDEC1_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_NS) +#define OTFDEC1_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_NS) +#define OTFDEC2_NS ((OTFDEC_TypeDef *) OTFDEC2_BASE_NS) +#define OTFDEC2_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_NS) +#define OTFDEC2_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_NS) +#define OTFDEC2_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_NS) +#define OTFDEC2_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) +#define DLYB_OCTOSPI2_NS ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_NS) +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS) +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define OCTOSPI2_NS ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS) +#define HSPI1_NS ((HSPI_TypeDef *) HSPI1_R_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS) +#define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS) +#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) +#define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS) +#define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS) +#define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS) +#define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS) +#define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) +#define USART6_S ((USART_TypeDef *) USART6_BASE_S) +#define I2C5_S ((I2C_TypeDef *) I2C5_BASE_S) +#define I2C6_S ((I2C_TypeDef *) I2C6_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) + +/*!< APB2 Secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) +#define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S) +#define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S) + +/*!< APB3 secure peripherals */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) +#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) +#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S) +#define RAMCFG_SRAM5_S ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GTZC_MPCBB5_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_S) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GPIOI_S ((GPIO_TypeDef *) GPIOI_BASE_S) +#define GPIOJ_S ((GPIO_TypeDef *) GPIOJ_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define USB_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_S) +#define AES_S ((AES_TypeDef *) AES_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SAES_S ((AES_TypeDef *) SAES_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define OTFDEC1_S ((OTFDEC_TypeDef *) OTFDEC1_BASE_S) +#define OTFDEC1_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_S) +#define OTFDEC1_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_S) +#define OTFDEC1_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_S) +#define OTFDEC1_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_S) +#define OTFDEC2_S ((OTFDEC_TypeDef *) OTFDEC2_BASE_S) +#define OTFDEC2_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_S) +#define OTFDEC2_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_S) +#define OTFDEC2_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_S) +#define OTFDEC2_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) +#define DLYB_OCTOSPI2_S ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_S) +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S) +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define OCTOSPI2_S ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S) +#define HSPI1_S ((HSPI_TypeDef *) HSPI1_R_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S) +#define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S) +#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) +#define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S) +#define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S) +#define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S) +#define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S) +#define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S) + +/*!< DBGMCU peripheral */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define SRAM4_BASE SRAM4_BASE_S +#define SRAM5_BASE SRAM5_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define FMAC FMAC_S +#define FMAC_BASE FMAC_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define LPDMA1 LPDMA1_S +#define LPDMA1_BASE LPDMA1_BASE_S + +#define LPDMA1_Channel0 LPDMA1_Channel0_S +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S + +#define LPDMA1_Channel1 LPDMA1_Channel1_S +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S + +#define LPDMA1_Channel2 LPDMA1_Channel2_S +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S + +#define LPDMA1_Channel3 LPDMA1_Channel3_S +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define GPIOI GPIOI_S +#define GPIOI_BASE GPIOI_BASE_S + +#define GPIOJ GPIOJ_S +#define GPIOJ_BASE GPIOJ_BASE_S + +#define LPGPIO1 LPGPIO1_S +#define LPGPIO1_BASE LPGPIO1_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_S +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_S +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZSC2 GTZC_TZSC2_S +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_TZIC2 GTZC_TZIC2_S +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define GTZC_MPCBB4 GTZC_MPCBB4_S +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S + +#define GTZC_MPCBB5 GTZC_MPCBB5_S +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define I2C5 I2C5_S +#define I2C5_BASE I2C5_BASE_S + +#define I2C6 I2C6_S +#define I2C6_BASE I2C6_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define DAC DAC_S +#define DAC_BASE DAC_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define OPAMP OPAMP_S +#define OPAMP_BASE OPAMP_BASE_S + +#define OPAMP1 OPAMP1_S +#define OPAMP1_BASE OPAMP1_BASE_S + +#define OPAMP2 OPAMP2_S +#define OPAMP2_BASE OPAMP2_BASE_S + +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define COMP12 COMP12_S +#define COMP12_BASE COMP12_BASE_S + +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S + +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S + +#define COMP12_COMMON COMP12_COMMON_S +#define COMP12_COMMON_BASE COMP1_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + +#define SAI2 SAI2_S +#define SAI2_BASE SAI2_BASE_S + +#define SAI2_Block_A SAI2_Block_A_S +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S + +#define SAI2_Block_B SAI2_Block_B_S +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + + +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S + +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define AES AES_S +#define AES_BASE AES_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S + +#define OTFDEC1 OTFDEC1_S +#define OTFDEC1_BASE OTFDEC1_BASE_S + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_S +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_S + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_S +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_S + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_S +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_S + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_S +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_S + +#define OTFDEC2 OTFDEC2_S +#define OTFDEC2_BASE OTFDEC2_BASE_S + +#define OTFDEC2_REGION1 OTFDEC2_REGION1_S +#define OTFDEC2_REGION1_BASE OTFDEC2_REGION1_BASE_S + +#define OTFDEC2_REGION2 OTFDEC2_REGION2_S +#define OTFDEC2_REGION2_BASE OTFDEC2_REGION2_BASE_S + +#define OTFDEC2_REGION3 OTFDEC2_REGION3_S +#define OTFDEC2_REGION3_BASE OTFDEC2_REGION3_BASE_S + +#define OTFDEC2_REGION4 OTFDEC2_REGION4_S +#define OTFDEC2_REGION4_BASE OTFDEC2_REGION4_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + +#define SDMMC2 SDMMC2_S +#define SDMMC2_BASE SDMMC2_BASE_S + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define OCTOSPI2 OCTOSPI2_S +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_S + +#define OCTOSPIM OCTOSPIM_S +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_SDMMC2 DLYB_SDMMC2_S +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_S +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_S + +#define HSPI1 HSPI1_S +#define HSPI1_R_BASE HSPI1_R_BASE_S + +#define DMA2D DMA2D_S +#define DMA2D_BASE DMA2D_BASE_S + +#define USB_OTG_HS USB_OTG_HS_S +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_S + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM3_BASE SRAM3_BASE_NS +#define SRAM4_BASE SRAM4_BASE_NS +#define SRAM5_BASE SRAM5_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DMA2D DMA2D_NS +#define DMA2D_BASE DMA2D_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define FMAC FMAC_NS +#define FMAC_BASE FMAC_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define LPDMA1 LPDMA1_NS +#define LPDMA1_BASE LPDMA1_BASE_NS + +#define LPDMA1_Channel0 LPDMA1_Channel0_NS +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS + +#define LPDMA1_Channel1 LPDMA1_Channel1_NS +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS + +#define LPDMA1_Channel2 LPDMA1_Channel2_NS +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS + +#define LPDMA1_Channel3 LPDMA1_Channel3_NS +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define GPIOI GPIOI_NS +#define GPIOI_BASE GPIOI_BASE_NS +#define GPIOJ GPIOJ_NS +#define GPIOJ_BASE GPIOJ_BASE_NS + +#define LPGPIO1 LPGPIO1_NS +#define LPGPIO1_BASE LPGPIO1_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_NS +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_NS +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZSC2 GTZC_TZSC2_NS +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_TZIC2 GTZC_TZIC2_NS +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define GTZC_MPCBB4 GTZC_MPCBB4_NS +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS + +#define GTZC_MPCBB5 GTZC_MPCBB5_NS +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define I2C5 I2C5_NS +#define I2C5_BASE I2C5_BASE_NS + +#define I2C6 I2C6_NS +#define I2C6_BASE I2C6_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define OPAMP OPAMP_NS +#define OPAMP_BASE OPAMP_BASE_NS + +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS + +#define OPAMP2 OPAMP2_NS +#define OPAMP2_BASE OPAMP2_BASE_NS + +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define COMP12 COMP12_NS +#define COMP12_BASE COMP12_BASE_NS + +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS + +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS + +#define COMP12_COMMON COMP12_COMMON_NS +#define COMP12_COMMON_BASE COMP1_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + +#define SAI2 SAI2_NS +#define SAI2_BASE SAI2_BASE_NS + +#define SAI2_Block_A SAI2_Block_A_NS +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS + +#define SAI2_Block_B SAI2_Block_B_NS +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS + +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define AES AES_NS +#define AES_BASE AES_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS + +#define OTFDEC1 OTFDEC1_NS +#define OTFDEC1_BASE OTFDEC1_BASE_NS + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_NS +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_NS + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_NS +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_NS + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_NS +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_NS + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_NS +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_NS + +#define OTFDEC2 OTFDEC2_NS +#define OTFDEC2_BASE OTFDEC2_BASE_NS + +#define OTFDEC2_REGION1 OTFDEC2_REGION1_NS +#define OTFDEC2_REGION1_BASE OTFDEC2_REGION1_BASE_NS + +#define OTFDEC2_REGION2 OTFDEC2_REGION2_NS +#define OTFDEC2_REGION2_BASE OTFDEC2_REGION2_BASE_NS + +#define OTFDEC2_REGION3 OTFDEC2_REGION3_NS +#define OTFDEC2_REGION3_BASE OTFDEC2_REGION3_BASE_NS + +#define OTFDEC2_REGION4 OTFDEC2_REGION4_NS +#define OTFDEC2_REGION4_BASE OTFDEC2_REGION4_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + +#define SDMMC2 SDMMC2_NS +#define SDMMC2_BASE SDMMC2_BASE_NS + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define OCTOSPI2 OCTOSPI2_NS +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_NS + +#define OCTOSPIM OCTOSPIM_NS +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_SDMMC2 DLYB_SDMMC2_NS +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_NS +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_NS + +#define HSPI1 HSPI1_NS +#define HSPI1_R_BASE HSPI1_R_BASE_NS + +#define USB_OTG_HS USB_OTG_HS_NS +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_NS + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS +#endif + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +#define ADC_MULTIMODE_SUPPORT +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ +#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_ADCALLIN_Pos (16U) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ + +#define ADC_CR_CALINDEX_Pos (24U) +#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ +#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ +#define ADC_CR_CALINDEX0_Pos (24U) +#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ +#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ +#define ADC_CR_CALINDEX1_Pos (25U) +#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ +#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ +#define ADC_CR_CALINDEX2_Pos (26U) +#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ +#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ +#define ADC_CR_CALINDEX3_Pos (27U) +#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ +#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR1_DMNGT_Pos (0U) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC4_CFGR1_DMAEN_Pos (0U) +#define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC4_CFGR1_DMACFG_Pos (1U) +#define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC4_CFGR1_SCANDIR_Pos (4U) +#define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC4_CFGR1_ALIGN_Pos (5U) +#define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (5U) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ + +#define ADC_CFGR1_AUTDLY_Pos (14U) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC4_CFGR1_WAIT_Pos (14U) +#define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR1_DISCNUM_Pos (17U) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20U) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR1_JAWD1EN_Pos (24U) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR1_JAUTO_Pos (25U) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +/* Specific ADC4 */ +#define ADC4_CFGR1_EXTSEL_Pos (6U) +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ + +#define ADC4_CFGR1_CHSELRMOD_Pos (21U) +#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_BULB_Pos (13U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (27U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* Specific ADC4 */ +#define ADC4_CFGR2_OVSR_Pos (2U) +#define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC4_CFGR2_LFTRIG_Pos (29U) +#define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC4_SMPR_SMP1_Pos (0U) +#define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC4_SMPR_SMP2_Pos (4U) +#define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC4_SMPR_SMPSEL_Pos (8U) +#define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ +#define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ +#define ADC4_SMPR_SMPSEL0_Pos (8U) +#define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ +#define ADC4_SMPR_SMPSEL1_Pos (9U) +#define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ +#define ADC4_SMPR_SMPSEL2_Pos (10U) +#define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ +#define ADC4_SMPR_SMPSEL3_Pos (11U) +#define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ +#define ADC4_SMPR_SMPSEL4_Pos (12U) +#define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ +#define ADC4_SMPR_SMPSEL5_Pos (13U) +#define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ +#define ADC4_SMPR_SMPSEL6_Pos (14U) +#define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ +#define ADC4_SMPR_SMPSEL7_Pos (15U) +#define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ +#define ADC4_SMPR_SMPSEL8_Pos (16U) +#define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ +#define ADC4_SMPR_SMPSEL9_Pos (17U) +#define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ +#define ADC4_SMPR_SMPSEL10_Pos (18U) +#define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ +#define ADC4_SMPR_SMPSEL11_Pos (19U) +#define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ +#define ADC4_SMPR_SMPSEL12_Pos (20U) +#define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ +#define ADC4_SMPR_SMPSEL13_Pos (21U) +#define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ +#define ADC4_SMPR_SMPSEL14_Pos (22U) +#define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ +#define ADC4_SMPR_SMPSEL15_Pos (23U) +#define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ +#define ADC4_SMPR_SMPSEL16_Pos (24U) +#define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ +#define ADC4_SMPR_SMPSEL17_Pos (25U) +#define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ +#define ADC4_SMPR_SMPSEL18_Pos (26U) +#define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ +#define ADC4_SMPR_SMPSEL19_Pos (27U) +#define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ +#define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ +#define ADC4_SMPR_SMPSEL20_Pos (26U) +#define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ +#define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL21_Pos (26U) +#define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ +#define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL22_Pos (30U) +#define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ +#define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ +#define ADC4_SMPR_SMPSEL23_Pos (31U) +#define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ +#define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +#define ADC_HTR_AWDFILT_Pos (29U) +#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ +#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_PW register ********************/ +#define ADC4_PWRR_AUTOFF_Pos (0U) +#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ +#define ADC4_PWRR_DPD_Pos (1U) +#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ +#define ADC4_PWRR_VREFPROT_Pos (2U) +#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ +#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ +#define ADC4_PWRR_VREFSECSMP_Pos (3U) +#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ +#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ + +/* Legacy definitions */ +#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos +#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk +#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF +#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos +#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk +#define ADC4_PW_DPD ADC4_PWRR_DPD +#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos +#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk +#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT +#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos +#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk +#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_USAT_Pos (25U) +#define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_SSAT_Pos (26U) +#define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (27U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR2_USAT_Pos (25U) +#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR2_SSAT_Pos (26U) +#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (27U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR3_USAT_Pos (25U) +#define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR3_SSAT_Pos (26U) +#define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (27U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR4_USAT_Pos (25U) +#define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR4_SSAT_Pos (26U) +#define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (27U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_GCOMP register ********************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ +#define ADC_GCOMP_GCOMP_Pos (31U) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19U) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20U) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21U) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22U) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL23_Pos (23U) +#define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_I_APB_ADDR_Pos (0U) +#define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ +#define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ + +#define ADC_CALFACT_I_APB_DATA_Pos (08U) +#define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ +#define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ + +#define ADC_CALFACT_VALIDITY_Pos (16U) +#define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_LATCH_COEF_Pos (24U) +#define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CAPTURE_COEF_Pos (25U) +#define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ + +#define ADC4_CALFACT_CALFACT_Pos (0U) +#define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_CALFACT_Pos (0U) +#define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */ +#define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */ +#define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OR register ********************/ +#define ADC_OR_CHN0SEL_Pos (0U) +#define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ +#define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_LDORDY_MST_Pos (12U) +#define ADC_CSR_LDORDY_MST_Msk (0x1UL << ADC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADC_CSR_LDORDY_MST ADC_CSR_LDORDY_MST_Msk /*!< Voltage regulator ready flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_LDORDY_SLV_Pos (28U) +#define ADC_CSR_LDORDY_SLV_Msk (0x1UL << ADC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CSR_LDORDY_SLV ADC_CSR_LDORDY_SLV_Msk /*!< Voltage regulator ready flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DAMDF_Pos (14U) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_VSENSEEN_Pos (23U) +#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ +#define ADC_CCR_VDDCOREN_Pos (26U) +#define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ +#define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0U) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) + +#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ + +#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11U) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ1_Pos (12U) +#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */ +#define FLASH_ACR_PDREQ2_Pos (13U) +#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */ +#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14U) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0U) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1U) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3U) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4U) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5U) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6U) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7U) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13U) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16U) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17U) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18U) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19U) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD1_Pos (20U) +#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */ +#define FLASH_NSSR_PD2_Pos (21U) +#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */ +#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0U) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1U) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3U) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4U) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5U) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6U) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7U) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16U) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17U) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR register *****************/ +#define FLASH_NSCR_PG_Pos (0U) +#define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR_PER_Pos (1U) +#define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR_MER1_Pos (2U) +#define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */ +#define FLASH_NSCR_PNB_Pos (3U) +#define FLASH_NSCR_PNB_Msk (0xFFUL << FLASH_NSCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR_BKER_Pos (11U) +#define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */ +#define FLASH_NSCR_BWR_Pos (14U) +#define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR_MER2_Pos (15U) +#define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */ +#define FLASH_NSCR_STRT_Pos (16U) +#define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR_OPTSTRT_Pos (17U) +#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR_EOPIE_Pos (24U) +#define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR_ERRIE_Pos (25U) +#define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR_OBL_LAUNCH_Pos (27U) +#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR_OPTLOCK_Pos (30U) +#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR_LOCK_Pos (31U) +#define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR register ****************/ +#define FLASH_SECCR_PG_Pos (0U) +#define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR_PER_Pos (1U) +#define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR_MER1_Pos (2U) +#define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR_PNB_Pos (3U) +#define FLASH_SECCR_PNB_Msk (0xFFUL << FLASH_SECCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR_BKER_Pos (11U) +#define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */ +#define FLASH_SECCR_BWR_Pos (14U) +#define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR_MER2_Pos (15U) +#define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */ +#define FLASH_SECCR_STRT_Pos (16U) +#define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR_EOPIE_Pos (24U) +#define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR_ERRIE_Pos (25U) +#define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR_INV_Pos (29U) +#define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR_LOCK_Pos (31U) +#define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0x1FFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x001FFFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_BK_ECC_Pos (21U) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (22U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0x1FFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x001FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */ +#define FLASH_OPSR_BK_OP_Pos (21U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (22U) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8U) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_nRST_SHDW_Pos (14U) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ +#define FLASH_OPTR_SRAM_RST_Pos (15U) +#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SWAP_BANK_Pos (20U) +#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */ +#define FLASH_OPTR_DUALBANK_Pos (21U) +#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */ +#define FLASH_OPTR_BKPRAM_ECC_Pos (22U) +#define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTR_SRAM3_ECC_Pos (23U) +#define FLASH_OPTR_SRAM3_ECC_Msk (0x1UL << FLASH_OPTR_SRAM3_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_SRAM3_ECC FLASH_OPTR_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */ +#define FLASH_OPTR_SRAM2_ECC_Pos (24U) +#define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25U) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26U) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_PA15_PUPEN_Pos (28U) +#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */ +#define FLASH_OPTR_IO_VDD_HSLV_Pos (29U) +#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */ +#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30U) +#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */ +#define FLASH_OPTR_TZEN_Pos (31U) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7U) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7U) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0U) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7U) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWM1R1 register **************/ +#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0U) +#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16U) +#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWM1R2 register **************/ +#define FLASH_SECWM1R2_HDP1_PEND_Pos (16U) +#define FLASH_SECWM1R2_HDP1_PEND_Msk (0xFFUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWM1R2_HDP1EN_Pos (31U) +#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0U) +#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */ +#define FLASH_WRP1AR_WRP1A_PEND_Pos (16U) +#define FLASH_WRP1AR_WRP1A_PEND_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */ +#define FLASH_WRP1AR_UNLOCK_Pos (31U) +#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0U) +#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */ +#define FLASH_WRP1BR_WRP1B_PEND_Pos (16U) +#define FLASH_WRP1BR_WRP1B_PEND_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */ +#define FLASH_WRP1BR_UNLOCK_Pos (31U) +#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */ + +/***************** Bits definition for FLASH_SECWM2R1 register **************/ +#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0U) +#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */ +#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16U) +#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */ + +/***************** Bits definition for FLASH_SECWM2R2 register **************/ +#define FLASH_SECWM2R2_HDP2_PEND_Pos (16U) +#define FLASH_SECWM2R2_HDP2_PEND_Msk (0xFFUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */ +#define FLASH_SECWM2R2_HDP2EN_Pos (31U) +#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */ + +/****************** Bits definition for FLASH_WRP2AR register ***************/ +#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0U) +#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */ +#define FLASH_WRP2AR_WRP2A_PEND_Pos (16U) +#define FLASH_WRP2AR_WRP2A_PEND_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */ +#define FLASH_WRP2AR_UNLOCK_Pos (31U) +#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP2BR register ***************/ +#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0U) +#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */ +#define FLASH_WRP2BR_WRP2B_PEND_Pos (16U) +#define FLASH_WRP2BR_WRP2B_PEND_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */ +#define FLASH_WRP2BR_UNLOCK_Pos (31U) +#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0U) +#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */ +#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1U) +#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */ +#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0U) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1U) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************************************************************************/ +/* */ +/* Filter Mathematical ACcelerator unit (FMAC) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1_BASE_Pos (0U) +#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U) +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ +#define FMAC_X1BUFCFG_FULL_WM_Pos (24U) +#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ +#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ + +/***************** Bit definition for FMAC_X2BUFCFG register ****************/ +#define FMAC_X2BUFCFG_X2_BASE_Pos (0U) +#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U) +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ + +/***************** Bit definition for FMAC_YBUFCFG register *****************/ +#define FMAC_YBUFCFG_Y_BASE_Pos (0U) +#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ +#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U) +#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ +#define FMAC_YBUFCFG_EMPTY_WM_Pos (24U) +#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ +#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ + +/****************** Bit definition for FMAC_PARAM register ******************/ +#define FMAC_PARAM_P_Pos (0U) +#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ +#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ +#define FMAC_PARAM_Q_Pos (8U) +#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ +#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ +#define FMAC_PARAM_R_Pos (16U) +#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ +#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ +#define FMAC_PARAM_FUNC_Pos (24U) +#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ +#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ +#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ +#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ +#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ +#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ +#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ +#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ +#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ +#define FMAC_PARAM_START_Pos (31U) +#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ +#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ + +/******************** Bit definition for FMAC_CR register *******************/ +#define FMAC_CR_RIEN_Pos (0U) +#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ +#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ +#define FMAC_CR_WIEN_Pos (1U) +#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ +#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ +#define FMAC_CR_OVFLIEN_Pos (2U) +#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ +#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ +#define FMAC_CR_UNFLIEN_Pos (3U) +#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ +#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ +#define FMAC_CR_SATIEN_Pos (4U) +#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ +#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ +#define FMAC_CR_DMAREN_Pos (8U) +#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ +#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ +#define FMAC_CR_DMAWEN_Pos (9U) +#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ +#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ +#define FMAC_CR_CLIPEN_Pos (15U) +#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ +#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ +#define FMAC_CR_RESET_Pos (16U) +#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ +#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_SR register ********************/ +#define FMAC_SR_YEMPTY_Pos (0U) +#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ +#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ +#define FMAC_SR_X1FULL_Pos (1U) +#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ +#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ +#define FMAC_SR_OVFL_Pos (8U) +#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ +#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ +#define FMAC_SR_UNFL_Pos (9U) +#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ +#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ +#define FMAC_SR_SAT_Pos (10U) +#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ +#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ + +/****************** Bit definition for FMAC_WDATA register ******************/ +#define FMAC_WDATA_WDATA_Pos (0U) +#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ + +/****************** Bit definition for FMACX_RDATA register *****************/ +#define FMAC_RDATA_RDATA_Pos (0U) +#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20U) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk + +/******************** Bits definition for TAMP_COUNTR register ***************/ +#define TAMP_COUNTR_Pos (16U) +#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ +#define TAMP_COUNTR TAMP_COUNTR_Msk + +/******************** Bits definition for TAMP_ERCFGR register ***************/ +#define TAMP_ERCFGR0_Pos (0U) +#define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* Touch Sensing Controller (TSC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TSC_CR register *********************/ +#define TSC_CR_TSCE_Pos (0U) +#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ +#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/** @addtogroup STM32U5xx_Peripheral_Exported_macros + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S) || \ + ((INSTANCE) == ADC2_NS) || \ + ((INSTANCE) == ADC2_S) || \ + ((INSTANCE) == ADC4_NS) || \ + ((INSTANCE) == ADC4_S)) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)) + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \ + ((INSTANCE) == ADC12_COMMON_S) || \ + ((INSTANCE) == ADC4_COMMON_NS) || \ + ((INSTANCE) == ADC4_COMMON_S)) + +/******************************* AES Instances ********************************/ +#define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES_NS) || ((INSTANCE) == AES_S)) + +/******************************* PKA Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************** FDCAN Instances *****************************/ +#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S)) + +/******************************** COMP Instances ******************************/ +#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \ + ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S)) + +/******************** COMP Instances with window mode capability **************/ +#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \ + ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S)) + +/******************************* CORDIC Instances *****************************/ +#define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) + +/******************************* DAC Instances ********************************/ +#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) + +/******************************* DELAYBLOCK Instances *******************************/ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \ + ((INSTANCE) == DLYB_SDMMC2_NS) || \ + ((INSTANCE) == DLYB_SDMMC1_S) || \ + ((INSTANCE) == DLYB_SDMMC2_S) || \ + ((INSTANCE) == DLYB_OCTOSPI1_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI2_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI1_S) || \ + ((INSTANCE) == DLYB_OCTOSPI2_S )) + +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ + ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ + ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ + ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ + ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S) || \ + ((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ + ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ + ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ + ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) + +#define IS_GPDMA_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ + ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ + ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ + ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ + ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) + +#define IS_LPDMA_INSTANCE(INSTANCE) (((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ + ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ + ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ + ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) + +#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) + +/****************************** OTFDEC Instances ********************************/ +#define IS_OTFDEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OTFDEC1_NS) || ((INSTANCE) == OTFDEC1_S) || \ + ((INSTANCE) == OTFDEC2_NS) || ((INSTANCE) == OTFDEC2_S)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_SRAM4_NS) || ((INSTANCE) == RAMCFG_SRAM4_S) || \ + ((INSTANCE) == RAMCFG_SRAM5_NS) || ((INSTANCE) == RAMCFG_SRAM5_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG ECC Instances *****************************/ +#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG IT Instances ******************************/ +#define IS_RAMCFG_IT_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) + +/******************************** FMAC Instances ******************************/ +#define IS_FMAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FMAC_NS) || ((INSTANCE) == FMAC_S)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \ + ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \ + ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \ + ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \ + ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \ + ((INSTANCE) == GPIOF_NS) || ((INSTANCE) == GPIOF_S) || \ + ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \ + ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S) || \ + ((INSTANCE) == GPIOI_NS) || ((INSTANCE) == GPIOI_S) || \ + ((INSTANCE) == GPIOJ_NS) || ((INSTANCE) == GPIOJ_S) || \ + ((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) + +/******************************* LPGPIO Instances *****************************/ +#define IS_LPGPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) + +/******************************* DMA2D Instances *******************************/ +#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA2D_NS) || ((__INSTANCE__) == DMA2D_S)) + +/******************************* DCMI Instances *******************************/ +#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) + +/******************************* DCACHE Instances *****************************/ +#define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S)) + +/******************************* PSSI Instances *******************************/ +#define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) + +/******************************* GPIO AF Instances ****************************/ +/* On U5, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On U5, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************* I2C Instances : Group belongingness *********************/ +#define IS_I2C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +#define IS_I2C_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/****************************** OPAMP Instances *******************************/ +#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1_NS) || ((INSTANCE) == OPAMP1_S) || \ + ((INSTANCE) == OPAMP2_NS) || ((INSTANCE) == OPAMP2_S)) + +/******************************* OSPI Instances *******************************/ +#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S) || \ + ((INSTANCE) == OCTOSPI2_NS) || ((INSTANCE) == OCTOSPI2_S)) + +/******************************* HSPI Instances *******************************/ +#define IS_HSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HSPI1_NS) || ((INSTANCE) == HSPI1_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \ + ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S) || \ + ((INSTANCE) == SAI2_Block_A_NS) || ((INSTANCE) == SAI2_Block_A_S) || \ + ((INSTANCE) == SAI2_Block_B_NS) || ((INSTANCE) == SAI2_Block_B_S)) + +/****************************** SDMMC Instances *******************************/ +#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S) || \ + ((INSTANCE) == SDMMC2_NS) || ((INSTANCE) == SDMMC2_S)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +/******************* SMBUS Instances : Group belongingness *********************/ +#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) + +#define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) + +#define IS_SPI_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ +#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) ||\ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) ||\ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) ||\ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) ||\ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) ||\ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) ||\ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)||\ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : supporting HSE32 as input ********************/ +#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) ||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ + ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ + ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S) || \ + ((__INSTANCE__) == TIM4_NS) || ((__INSTANCE__) == TIM4_S) || \ + ((__INSTANCE__) == TIM5_NS) || ((__INSTANCE__) == TIM5_S) || \ + ((__INSTANCE__) == TIM6_NS) || ((__INSTANCE__) == TIM6_S) || \ + ((__INSTANCE__) == TIM7_NS) || ((__INSTANCE__) == TIM7_S) || \ + ((__INSTANCE__) == TIM8_NS) || ((__INSTANCE__) == TIM8_S) || \ + ((__INSTANCE__) == TIM15_NS) || ((__INSTANCE__) == TIM15_S)) + +/****************************** TSC Instances *********************************/ +#define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S))|| \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S))|| \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : AUTONOMOUS mode ***************************/ +#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +/****************************** UCPD Instances ********************************/ +#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S)) + +/******************************* OTG FS HCD Instances *************************/ +#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_HS_NS) || ((INSTANCE) == USB_OTG_HS_S)) + +/******************************* OTG FS PCD Instances *************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_HS_NS) || ((INSTANCE) == USB_OTG_HS_S)) + +/******************************* MDF/ADF Instances ****************************/ +#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_NS) || ((INSTANCE) == MDF1_Filter0_S) || \ + ((INSTANCE) == MDF1_Filter1_NS) || ((INSTANCE) == MDF1_Filter1_S) || \ + ((INSTANCE) == MDF1_Filter2_NS) || ((INSTANCE) == MDF1_Filter2_S) || \ + ((INSTANCE) == MDF1_Filter3_NS) || ((INSTANCE) == MDF1_Filter3_S) || \ + ((INSTANCE) == MDF1_Filter4_NS) || ((INSTANCE) == MDF1_Filter4_S) || \ + ((INSTANCE) == MDF1_Filter5_NS) || ((INSTANCE) == MDF1_Filter5_S) || \ + ((INSTANCE) == ADF1_Filter0_NS) || ((INSTANCE) == ADF1_Filter0_S)) + + +/** @} */ /* End of group STM32U5xx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32U5A5xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5A5xx_H */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u5a9xx.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u5a9xx.h new file mode 100644 index 00000000000..e74fc1d83ec --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u5a9xx.h @@ -0,0 +1,30309 @@ +/** + ****************************************************************************** + * @file stm32u5a9xx.h + * @author MCD Application Team + * @brief CMSIS STM32U5A9xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32U5A9xx_H +#define STM32U5A9xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32U5A9xx + * @{ + */ + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32U5A9xx Specific Interrupt Numbers ================================= */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + RTC_S_IRQn = 3, /*!< RTC secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ + GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + IWDG_IRQn = 27, /*!< IWDG global interrupt */ + SAES_IRQn = 28, /*!< Secure AES global interrupt */ + GPDMA1_Channel0_IRQn = 29, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 30, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 31, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 32, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 33, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 34, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 35, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 36, /*!< GPDMA1 Channel 7 global interrupt */ + ADC1_2_IRQn = 37, /*!< ADC1_2 global interrupt */ + DAC1_IRQn = 38, /*!< DAC1 global interrupt */ + FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ + TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 45, /*!< TIM2 global interrupt */ + TIM3_IRQn = 46, /*!< TIM3 global interrupt */ + TIM4_IRQn = 47, /*!< TIM4 global interrupt */ + TIM5_IRQn = 48, /*!< TIM5 global interrupt */ + TIM6_IRQn = 49, /*!< TIM6 global interrupt */ + TIM7_IRQn = 50, /*!< TIM7 global interrupt */ + TIM8_BRK_IRQn = 51, /*!< TIM8 Break interrupt */ + TIM8_UP_IRQn = 52, /*!< TIM8 Update interrupt */ + TIM8_TRG_COM_IRQn = 53, /*!< TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQn = 54, /*!< TIM8 Capture Compare interrupt */ + I2C1_EV_IRQn = 55, /*!< I2C1 Event interrupt */ + I2C1_ER_IRQn = 56, /*!< I2C1 Error interrupt */ + I2C2_EV_IRQn = 57, /*!< I2C2 Event interrupt */ + I2C2_ER_IRQn = 58, /*!< I2C2 Error interrupt */ + SPI1_IRQn = 59, /*!< SPI1 global interrupt */ + SPI2_IRQn = 60, /*!< SPI2 global interrupt */ + USART1_IRQn = 61, /*!< USART1 global interrupt */ + USART2_IRQn = 62, /*!< USART2 global interrupt */ + USART3_IRQn = 63, /*!< USART3 global interrupt */ + UART4_IRQn = 64, /*!< UART4 global interrupt */ + UART5_IRQn = 65, /*!< UART5 global interrupt */ + LPUART1_IRQn = 66, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 67, /*!< LPTIM1 global interrupt */ + LPTIM2_IRQn = 68, /*!< LPTIM2 global interrupt */ + TIM15_IRQn = 69, /*!< TIM15 global interrupt */ + TIM16_IRQn = 70, /*!< TIM16 global interrupt */ + TIM17_IRQn = 71, /*!< TIM17 global interrupt */ + COMP_IRQn = 72, /*!< COMP1 and COMP2 through EXTI Lines interrupts */ + OTG_HS_IRQn = 73, /*!< USB OTG HS global interrupt */ + CRS_IRQn = 74, /*!< CRS global interrupt */ + FMC_IRQn = 75, /*!< FSMC global interrupt */ + OCTOSPI1_IRQn = 76, /*!< OctoSPI1 global interrupt */ + PWR_S3WU_IRQn = 77, /*!< PWR wake up from Stop3 interrupt */ + SDMMC1_IRQn = 78, /*!< SDMMC1 global interrupt */ + SDMMC2_IRQn = 79, /*!< SDMMC2 global interrupt */ + GPDMA1_Channel8_IRQn = 80, /*!< GPDMA1 Channel 8 global interrupt */ + GPDMA1_Channel9_IRQn = 81, /*!< GPDMA1 Channel 9 global interrupt */ + GPDMA1_Channel10_IRQn = 82, /*!< GPDMA1 Channel 10 global interrupt */ + GPDMA1_Channel11_IRQn = 83, /*!< GPDMA1 Channel 11 global interrupt */ + GPDMA1_Channel12_IRQn = 84, /*!< GPDMA1 Channel 12 global interrupt */ + GPDMA1_Channel13_IRQn = 85, /*!< GPDMA1 Channel 13 global interrupt */ + GPDMA1_Channel14_IRQn = 86, /*!< GPDMA1 Channel 14 global interrupt */ + GPDMA1_Channel15_IRQn = 87, /*!< GPDMA1 Channel 15 global interrupt */ + I2C3_EV_IRQn = 88, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 89, /*!< I2C3 error interrupt */ + SAI1_IRQn = 90, /*!< Serial Audio Interface 1 global interrupt */ + SAI2_IRQn = 91, /*!< Serial Audio Interface 2 global interrupt */ + TSC_IRQn = 92, /*!< Touch Sense Controller global interrupt */ + AES_IRQn = 93, /*!< AES global interrupt */ + RNG_IRQn = 94, /*!< RNG global interrupt */ + FPU_IRQn = 95, /*!< FPU global interrupt */ + HASH_IRQn = 96, /*!< HASH global interrupt */ + PKA_IRQn = 97, /*!< PKA global interrupt */ + LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */ + SPI3_IRQn = 99, /*!< SPI3 global interrupt */ + I2C4_ER_IRQn = 100, /*!< I2C4 Error interrupt */ + I2C4_EV_IRQn = 101, /*!< I2C4 Event interrupt */ + MDF1_FLT0_IRQn = 102, /*!< MDF1 Filter 0 global interrupt */ + MDF1_FLT1_IRQn = 103, /*!< MDF1 Filter 1 global interrupt */ + MDF1_FLT2_IRQn = 104, /*!< MDF1 Filter 2 global interrupt */ + MDF1_FLT3_IRQn = 105, /*!< MDF1 Filter 3 global interrupt */ + UCPD1_IRQn = 106, /*!< UCPD1 global interrupt */ + ICACHE_IRQn = 107, /*!< Instruction cache global interrupt */ + OTFDEC1_IRQn = 108, /*!< OTFDEC1 global interrupt */ + OTFDEC2_IRQn = 109, /*!< OTFDEC2 global interrupt */ + LPTIM4_IRQn = 110, /*!< LPTIM4 global interrupt */ + DCACHE1_IRQn = 111, /*!< Data cache global interrupt */ + ADF1_IRQn = 112, /*!< ADF interrupt */ + ADC4_IRQn = 113, /*!< ADC4 (12bits) global interrupt */ + LPDMA1_Channel0_IRQn = 114, /*!< LPDMA1 SmartRun Channel 0 global interrupt */ + LPDMA1_Channel1_IRQn = 115, /*!< LPDMA1 SmartRun Channel 1 global interrupt */ + LPDMA1_Channel2_IRQn = 116, /*!< LPDMA1 SmartRun Channel 2 global interrupt */ + LPDMA1_Channel3_IRQn = 117, /*!< LPDMA1 SmartRun Channel 3 global interrupt */ + DMA2D_IRQn = 118, /*!< DMA2D global interrupt */ + DCMI_PSSI_IRQn = 119, /*!< DCMI/PSSI global interrupt */ + OCTOSPI2_IRQn = 120, /*!< OCTOSPI2 global interrupt */ + MDF1_FLT4_IRQn = 121, /*!< MDF1 Filter 4 global interrupt */ + MDF1_FLT5_IRQn = 122, /*!< MDF1 Filter 5 global interrupt */ + CORDIC_IRQn = 123, /*!< CORDIC global interrupt */ + FMAC_IRQn = 124, /*!< FMAC global interrupt */ + LSECSSD_IRQn = 125, /*!< LSECSSD and MSI_PLL_UNLOCK global interrupts */ + USART6_IRQn = 126, /*!< USART6 global interrupt */ + I2C5_ER_IRQn = 127, /*!< I2C5 Error interrupt */ + I2C5_EV_IRQn = 128, /*!< I2C5 Event interrupt */ + I2C6_ER_IRQn = 129, /*!< I2C6 Error interrupt */ + I2C6_EV_IRQn = 130, /*!< I2C6 Error interrupt */ + HSPI1_IRQn = 131, /*!< HSPI1 global interrupt */ + GPU2D_IRQn = 132, /*!< GPU2D global interrupt */ + GPU2D_ER_IRQn = 133, /*!< GPU2D Error interrupt */ + GFXMMU_IRQn = 134, /*!< GFXMMU global interrupt */ + LTDC_IRQn = 135, /*!< LCD-TFT global interrupt */ + LTDC_ER_IRQn = 136, /*!< LCD-TFT Error interrupt */ + DSI_IRQn = 137, /*!< DSIHOST global interrupt */ + DCACHE2_IRQn = 138, /*!< DCACHE2 Data cache global interrupt */ +} IRQn_Type; + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32u5xx.h" /*!< STM32U5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ + uint32_t RESERVED3[246]; /*!< Reserved, */ + __IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */ + __IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; +} I2C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, 0x24 */ + __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FC */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FC */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFC */ +} DMA2D_TypeDef; + +/** + * @brief DSI Controller + */ +typedef struct +{ + __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ + __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ + __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ + __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ + __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ + __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ + __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ + __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ + __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ + __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ + __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ + __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ + __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ + __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ + __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ + __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ + __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ + __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ + __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ + __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ + __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ + __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ + __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ + __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ + __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ + __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ + uint32_t RESERVED1; /*!< Reserved, 0x90 */ + __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ + __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ + __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ + __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ + __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ + __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ + __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ + __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ + uint32_t RESERVED2[2]; /*!< Reserved, 0xB4 - 0xBB */ + __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ + __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ + uint32_t RESERVED3[3]; /*!< Reserved, 0xD0 - 0xD7 */ + __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ + uint32_t RESERVED4[5]; /*!< Reserved, 0xE0 - 0xF3 */ + __IO uint32_t DLTRCR; /*!< DSI Host Data Lane Timer Read Configuration Register, Address offset: 0xF4 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0xF8 - 0xFF */ + __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x104 - 0x10B */ + __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ + __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ + uint32_t RESERVED7; /*!< Reserved, 0x114 */ + __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ + uint32_t RESERVED8[7]; /*!< Reserved, 0x11C - 0x137 */ + __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ + __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chunks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ + __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ + __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ + __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ + __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ + __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ + __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ + __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ + uint32_t RESERVED9; /*!< Reserved, 0x164 */ + __IO uint32_t FBSR; /*!< DSI Host FIFO and Buffer Status Register, Address offset: 0x168 */ + uint32_t RESERVED10[165];/*!< Reserved, 0x16C - 0x3FF */ + __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ + __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ + __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ + __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ + __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ + uint32_t RESERVED11; /*!< Reserved, 0x414 */ + __IO uint32_t WPCR[1]; /*!< DSI Wrapper PHY Configuration Register 0, Address offset: 0x418 */ + uint32_t RESERVED12[5]; /*!< Reserved, 0x41C - 0x42F */ + __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ + uint32_t WPTR; /*!< DSI Wrapper PLL tuning register, Address offset: 0x434 */ + uint32_t RESERVED13[244];/*!< Reserved, 0x43C - 0x804 */ + __IO uint32_t BCFGR; /*!< DSI Bias Configuration Register, Address offset: 0x808 */ + uint32_t RESERVED14[254];/*!< Reserved, 0x80C - 0xC00 */ + __IO uint32_t DPCBCR; /*!< D-PHY clock band control register, Address offset: 0xC04 */ + uint32_t RESERVED15[11]; /*!< Reserved, 0xC08 - 0xC30 */ + __IO uint32_t DPCSRCR; /*!< D-PHY clock slew rate control register, Address offset: 0xC34 */ + uint32_t RESERVED16[9]; /*!< Reserved, 0xC38 - 0xC58 */ + __IO uint32_t DPDL0HSOCR; /*!< D-PHY data Lane 0 HS offset control register, Address offset: 0x0C5C */ + __IO uint32_t DPDL0LPXOCR; /*!< D-PHY data Lane 0 HS LPX offset control register, Address offset: 0x0C60 */ + uint32_t RESERVED17[3]; /*!< Reserved, 0xC64-0xC6C */ + __IO uint32_t DPDL0BCR; /*!< D-PHY data Lane0 band control register, Address offset: 0x0C70 */ + uint32_t RESERVED18[11]; /*!< Reserved, 0xC74 - 0xC9C */ + __IO uint32_t DPDL0SRCR; /*!< D-PHY data Lane0 slew rate control register, Address offset: 0x0CA0 */ + uint32_t RESERVED19[20]; /*!< Reserved, 0xCA4 - 0xD04 */ + __IO uint32_t DPDL1HSOCR; /*!< D-PHY data Lane 1 HS offset control register, Address offset: 0x0CF4 */ + __IO uint32_t DPDL1LPXOCR; /*!< D-PHY data Lane 1 HS LPX offset control register, Address offset: 0x0CF8 */ + uint32_t RESERVED20[3]; /*!< Reserved, 0xCF8 - 0xD04 */ + __IO uint32_t DPDL1BCR; /*!< D-PHY data Lane1 band control register, Address offset: 0x0D08 */ + uint32_t RESERVED21[11]; /*!< Reserved, 0xD0C - 0xD34 */ + __IO uint32_t DPDL1SRCR; /*!< D-PHY data Lane1 slew rate control register, Address Offset: 0x0D38 */ +} DSI_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ + __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */ + __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */ + __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */ + __IO uint32_t SECBB1R5; /*!< FLASH secure block-based bank 1 register 5, Address offset: 0x90 */ + __IO uint32_t SECBB1R6; /*!< FLASH secure block-based bank 1 register 6, Address offset: 0x94 */ + __IO uint32_t SECBB1R7; /*!< FLASH secure block-based bank 1 register 7, Address offset: 0x98 */ + __IO uint32_t SECBB1R8; /*!< FLASH secure block-based bank 1 register 8, Address offset: 0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */ + __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */ + __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */ + __IO uint32_t SECBB2R5; /*!< FLASH secure block-based bank 2 register 5, Address offset: 0xB0 */ + __IO uint32_t SECBB2R6; /*!< FLASH secure block-based bank 2 register 6, Address offset: 0xB4 */ + __IO uint32_t SECBB2R7; /*!< FLASH secure block-based bank 2 register 7, Address offset: 0xB8 */ + __IO uint32_t SECBB2R8; /*!< FLASH secure block-based bank 2 register 8, Address offset: 0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */ + __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */ + __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */ + __IO uint32_t PRIVBB1R5; /*!< FLASH privilege block-based bank 1 register 5, Address offset: 0xE0 */ + __IO uint32_t PRIVBB1R6; /*!< FLASH privilege block-based bank 1 register 6, Address offset: 0xE4 */ + __IO uint32_t PRIVBB1R7; /*!< FLASH privilege block-based bank 1 register 7, Address offset: 0xE8 */ + __IO uint32_t PRIVBB1R8; /*!< FLASH privilege block-based bank 1 register 8, Address offset: 0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */ + __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */ + __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */ + __IO uint32_t PRIVBB2R5; /*!< FLASH privilege block-based bank 2 register 5, Address offset: 0x100 */ + __IO uint32_t PRIVBB2R6; /*!< FLASH privilege block-based bank 2 register 6, Address offset: 0x104 */ + __IO uint32_t PRIVBB2R7; /*!< FLASH privilege block-based bank 2 register 7, Address offset: 0x108 */ + __IO uint32_t PRIVBB2R8; /*!< FLASH privilege block-based bank 2 register 8, Address offset: 0x10C */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief GFXMMU registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */ + __IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */ + __IO uint32_t CCR; /*!< GFXMMU Cache Control Register, Address offset: 0x0C */ + __IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x14 to 0x1C */ + __IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */ + __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ + __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ + __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ + uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */ + __IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */ + __IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */ + __IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */ + __IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */ + __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC + For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ +} GFXMMU_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */ + __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */ + __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */ + __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */ + __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */ + __IO uint32_t MPCWM6ACFGR; /*!< TZSC memory 6 sub-region A watermark configuration register, Address offset: 0x90 */ + __IO uint32_t MPCWM6AR; /*!< TZSC memory 6 sub-region A watermark register, Address offset: 0x94 */ + __IO uint32_t MPCWM6BCFGR; /*!< TZSC memory 6 sub-region B watermark configuration register, Address offset: 0x98 */ + __IO uint32_t MPCWM6BR; /*!< TZSC memory 6 sub-region B watermark register, Address offset: 0x9C */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register 1, Address offset: 0x10 */ + __IO uint32_t CFGLOCKR2; /*!< MPCBBx Configuration lock register 2, Address offset: 0x14 */ + uint32_t RESERVED2[58]; /*!< Reserved2, Address offset: 0x18-0xFC */ + __IO uint32_t SECCFGR[52]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x1CC */ + uint32_t RESERVED3[12]; /*!< Reserved3, Address offset: 0x1D0-0x1FC */ + __IO uint32_t PRIVCFGR[52]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x2CC */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ + uint32_t RESERVED2[240]; /*!< Reserved, Address offset: 0x30-0x3EC */ + __IO uint32_t HWCFGR; /*!< ICACHE HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< ICACHE version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ICACHE IP identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ICACHE size identification register, Address offset: 0x3FC */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + + +/** + * @brief MDF/ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ +}MDF_TypeDef; + +/** + * @brief MDF/ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ + __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ + __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ + __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ + __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief HEXA and OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ + uint32_t RESERVED22[3]; /*!< Reserved, Address offset: 0x204-0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-cycle calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x210 */ + uint32_t RESERVED23; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL master calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x218 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI slave output calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x220 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI slave input calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x228 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + +typedef XSPI_TypeDef HSPI_TypeDef; + +/** + * @brief OTFDEC register + */ +typedef struct +{ + __IO uint32_t REG_CONFIGR; /*!< OTFDEC Region Configuration register, Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_START_ADDR; /*!< OTFDEC Region Start Address register, Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_END_ADDR; /*!< OTFDEC Region End Address register, Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER0; /*!< OTFDEC Region Nonce register 0, Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER1; /*!< OTFDEC Region Nonce register 1, Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR0; /*!< OTFDEC Region Key register 0, Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR1; /*!< OTFDEC Region Key register 1, Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR2; /*!< OTFDEC Region Key register 2, Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR3; /*!< OTFDEC Region Key register 3, Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4) */ +} OTFDEC_Region_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< OTFDEC Control register, Address offset: 0x000 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x004-0x00C */ + __IO uint32_t PRIVCFGR; /*!< OTFDEC Privileged access control Configuration register, Address offset: 0x010 */ + uint32_t RESERVED2[187]; /*!< Reserved, Address offset: 0x014-0x2FC */ + __IO uint32_t ISR; /*!< OTFDEC Interrupt Status register, Address offset: 0x300 */ + __IO uint32_t ICR; /*!< OTFDEC Interrupt Clear register, Address offset: 0x304 */ + __IO uint32_t IER; /*!< OTFDEC Interrupt Enable register, Address offset: 0x308 */ +} OTFDEC_TypeDef; + + +/** + * @brief Serial Peripheral Interface IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPIM IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[8]; /*!< OCTOSPIM IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ +} XSPIM_TypeDef; + +typedef XSPIM_TypeDef OCTOSPIM_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x20 */ + __IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Power USB Type-C and Power Delivery register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + __IO uint32_t BDSR; /*!< Power backup domain status register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */ + __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ + __IO uint32_t PUCRI; /*!< Power Port I pull-up control register, Address offset: 0x90 */ + __IO uint32_t PDCRI; /*!< Power Port I pull-down control register, Address offset: 0x94 */ + __IO uint32_t PUCRJ; /*!< Power Port J pull-up control register, Address offset: 0x98 */ + __IO uint32_t PDCRJ; /*!< Power Port J pull-down control register, Address offset: 0x9C */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x0A0-0x0A4 */ + __IO uint32_t CR4; /*!< Power power control register 4, Address offset: 0xA8 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */ + __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */ + __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */ + __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */ + __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */ + __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */ + __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */ + __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */ + __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */ + __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */ + __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */ + uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + uint32_t RESERVED2[17];/*!< RESERVED2, Address offset: 0x30 - 0x70 */ + __IO uint32_t OTGHSPHYCR; /*!< SYSCFG USB OTG_HS PHY register Address offset: 0x74 */ + uint32_t RESERVED3; /*!< RESERVED3, Address offset: 0x78 */ + __IO uint32_t OTGHSPHYTUNER2;/*!< SYSCFG USB OTG_HS PHY tune register 2 Address offset: 0x7C */ +} SYSCFG_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief Flexible Memory Controller + */ +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief ADC + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ /* Specific to ADC 14Bits*/ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t AWD1TR; /*!< ADC watchdog threshold register, Address offset: 0x20 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ /* Specific to ADC 12Bits*/ + __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x2C */ /* Specific to ADC 12Bits*/ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ /* Specific to ADC 14Bits*/ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ + uint32_t RESERVED1; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ /* Specific to ADC 14Bits*/ + __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED3[3]; /*!< Reserved, 0x074 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED4[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0xA8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0xAC */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ /* Specific to ADC 14Bits*/ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED5; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0xD0 */ /* Specific to ADC 12Bits*/ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode, Address offset: 0x310 */ +} ADC_Common_TypeDef; + + +/* Legacy registers naming */ +#define PW PWRR + +/** + * @brief CORDIC + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief Touch Sensing Controller (TSC) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ +} TSC_TypeDef; + +/** + * @brief WWDG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32U5xx_peripherals */ + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0xC0000UL) /*!< SRAM1=768k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ +#define SRAM3_SIZE (0xD0000UL) /*!< SRAM3=832k */ +#define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */ +#define SRAM5_SIZE (0xD0000UL) /*!< SRAM5=832k */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< OCTOSPI2 memories accessible over AHB base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ +#define HSPI1_BASE (0xA0000000UL) /*!< HSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (4 MB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (768 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x200C0000UL) /*!< SRAM2 (64 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x200D0000UL) /*!< SRAM3 (832 KB) non-secure base address */ +#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */ +#define SRAM5_BASE_NS (0x201A0000UL) /*!< SRAM5 (832 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define I2C5_BASE_NS (APB1PERIPH_BASE_NS + 0x9800UL) +#define I2C6_BASE_NS (APB1PERIPH_BASE_NS + 0x9C00UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) +#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) +#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x004UL) +#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x024UL) +#define LTDC_BASE_NS (APB2PERIPH_BASE_NS + 0x6800UL) +#define LTDC_Layer1_BASE_NS (LTDC_BASE_NS + 0x0084UL) +#define LTDC_Layer2_BASE_NS (LTDC_BASE_NS + 0x0104UL) +#define DSI_BASE_NS (APB2PERIPH_BASE_NS + 0x6C00UL) +#define REFBIAS_BASE_NS (DSI_BASE_NS + 0x800UL) +#define DPHY_BASE_NS (DSI_BASE_NS + 0xC00UL) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) +#define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP2_BASE_NS (APB3PERIPH_BASE_NS + 0x5010UL) +#define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define RAMCFG_SRAM5_BASE_NS (RAMCFG_BASE_NS + 0x0140UL) +#define DMA2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0B000UL) +#define GFXMMU_BASE_NS (AHB1PERIPH_BASE_NS + 0x0C000UL) +#define GPU2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0F000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define DCACHE2_BASE_NS (AHB1PERIPH_BASE_NS + 0x11800UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define GTZC_MPCBB5_BASE_NS (AHB1PERIPH_BASE_NS + 0x13800UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define GPIOI_BASE_NS (AHB2PERIPH_BASE_NS + 0x02000UL) +#define GPIOJ_BASE_NS (AHB2PERIPH_BASE_NS + 0x02400UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define USB_OTG_HS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL) +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) +#define OCTOSPIM_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xA4000UL) /*!< OCTOSPIO Manager control registers base address */ +#define OTFDEC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5000UL) +#define OTFDEC1_REGION1_BASE_NS (OTFDEC1_BASE_NS + 0x20UL) +#define OTFDEC1_REGION2_BASE_NS (OTFDEC1_BASE_NS + 0x50UL) +#define OTFDEC1_REGION3_BASE_NS (OTFDEC1_BASE_NS + 0x80UL) +#define OTFDEC1_REGION4_BASE_NS (OTFDEC1_BASE_NS + 0xB0UL) +#define OTFDEC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5400UL) +#define OTFDEC2_REGION1_BASE_NS (OTFDEC2_BASE_NS + 0x20UL) +#define OTFDEC2_REGION2_BASE_NS (OTFDEC2_BASE_NS + 0x50UL) +#define OTFDEC2_REGION3_BASE_NS (OTFDEC2_BASE_NS + 0x80UL) +#define OTFDEC2_REGION4_BASE_NS (OTFDEC2_BASE_NS + 0xB0UL) +#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL) +#define SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL) +#define DLYB_SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF400UL) +#define FMC_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB0400UL) /*!< FMC control registers base address */ +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ +#define HSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB3400UL) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS) +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1300UL) +#define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL) +#define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL) +#define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL) +#define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL) +#define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL) +#define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL) +#define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL) +#define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL) +#define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL) +/* GFXMMU non secure virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE_NS (0x24000000UL) +#define GFXMMU_VIRTUAL_BUFFER0_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS) +#define GFXMMU_VIRTUAL_BUFFER1_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0x400000UL) +#define GFXMMU_VIRTUAL_BUFFER2_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0x800000UL) +#define GFXMMU_VIRTUAL_BUFFER3_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0xC00000UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (4 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (768 KB) secure base address */ +#define SRAM2_BASE_S (0x300C0000UL) /*!< SRAM2 (64 KB) secure base address */ +#define SRAM3_BASE_S (0x300D0000UL) /*!< SRAM3 (832 KB) secure base address */ +#define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */ +#define SRAM5_BASE_S (0x301A0000UL) /*!< SRAM5 (832 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define I2C5_BASE_S (APB1PERIPH_BASE_S + 0x9800UL) +#define I2C6_BASE_S (APB1PERIPH_BASE_S + 0x9C00UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) +#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) +#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x004UL) +#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x024UL) +#define LTDC_BASE_S (APB2PERIPH_BASE_S + 0x6800UL) +#define LTDC_Layer1_BASE_S (LTDC_BASE_S + 0x0084UL) +#define LTDC_Layer2_BASE_S (LTDC_BASE_S + 0x0104UL) +#define DSI_BASE_S (APB2PERIPH_BASE_S + 0x6C00UL) +#define REFBIAS_BASE_S (DSI_BASE_S + 0x800UL) +#define DPHY_BASE_S (DSI_BASE_S + 0xC00UL) + +/*!< APB3 Secure peripherals */ +#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) +#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP2_BASE_S (APB3PERIPH_BASE_S + 0x5010UL) +#define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define COMP2_BASE_S (COMP12_BASE_S + 0x04UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define RAMCFG_SRAM5_BASE_S (RAMCFG_BASE_S + 0x0140UL) +#define DMA2D_BASE_S (AHB1PERIPH_BASE_S + 0x0B000UL) +#define GFXMMU_BASE_S (AHB1PERIPH_BASE_S + 0x0C000UL) +#define GPU2D_BASE_S (AHB1PERIPH_BASE_S + 0x0F000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define DCACHE2_BASE_S (AHB1PERIPH_BASE_S + 0x11800UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define GTZC_MPCBB5_BASE_S (AHB1PERIPH_BASE_S + 0x13800UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define GPIOI_BASE_S (AHB2PERIPH_BASE_S + 0x02000UL) +#define GPIOJ_BASE_S (AHB2PERIPH_BASE_S + 0x02400UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define USB_OTG_HS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL) +#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) +#define OTFDEC1_BASE_S (AHB2PERIPH_BASE_S + 0xA5000UL) +#define OTFDEC1_REGION1_BASE_S (OTFDEC1_BASE_S + 0x20UL) +#define OTFDEC1_REGION2_BASE_S (OTFDEC1_BASE_S + 0x50UL) +#define OTFDEC1_REGION3_BASE_S (OTFDEC1_BASE_S + 0x80UL) +#define OTFDEC1_REGION4_BASE_S (OTFDEC1_BASE_S + 0xB0UL) +#define OTFDEC2_BASE_S (AHB2PERIPH_BASE_S + 0xA5400UL) +#define OTFDEC2_REGION1_BASE_S (OTFDEC2_BASE_S + 0x20UL) +#define OTFDEC2_REGION2_BASE_S (OTFDEC2_BASE_S + 0x50UL) +#define OTFDEC2_REGION3_BASE_S (OTFDEC2_BASE_S + 0x80UL) +#define OTFDEC2_REGION4_BASE_S (OTFDEC2_BASE_S + 0xB0UL) +#define OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */ +#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) +#define SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) +#define DLYB_SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_S (AHB2PERIPH_BASE_S + 0xAF400UL) +#define FMC_R_BASE_S (AHB2PERIPH_BASE_S + 0xB0400UL) /*!< FMC control registers base address */ +#define HSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB3400UL) +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_S (AHB2PERIPH_BASE_S + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1300UL) +#define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) +#define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL) +#define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL) +#define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL) +#define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL) +#define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL) +#define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) +#define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) + +/* GFXMMU secure virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE_S (0x34000000UL) +#define GFXMMU_VIRTUAL_BUFFER0_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S) +#define GFXMMU_VIRTUAL_BUFFER1_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0x400000UL) +#define GFXMMU_VIRTUAL_BUFFER2_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0x800000UL) +#define GFXMMU_VIRTUAL_BUFFER3_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0xC00000UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0044000UL) +#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ +#define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */ + +/* USB OTG registers Base address */ +#define USB_OTG_GLOBAL_BASE (0x0000UL) +#define USB_OTG_DEVICE_BASE (0x0800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) +#define USB_OTG_EP_REG_SIZE (0x0020UL) +#define USB_OTG_HOST_BASE (0x0400UL) +#define USB_OTG_HOST_PORT_BASE (0x0440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) +#define USB_OTG_PCGCCTL_BASE (0x0E00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0U) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0U) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1U) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) +#define USART6_NS ((USART_TypeDef *) USART6_BASE_NS) +#define I2C5_NS ((I2C_TypeDef *) I2C5_BASE_NS) +#define I2C6_NS ((I2C_TypeDef *) I2C6_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) +#define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS) +#define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS) +#define LTDC_NS ((LTDC_TypeDef *) LTDC_BASE_NS) +#define LTDC_Layer1_NS ((LTDC_Layer_TypeDef *) LTDC_Layer1_BASE_NS) +#define LTDC_Layer2_NS ((LTDC_Layer_TypeDef *) LTDC_Layer2_BASE_NS) +#define DSI_NS ((DSI_TypeDef *) DSI_BASE_NS) +#define REFBIAS_NS ((REFBIAS_TypeDef *) REFBIAS_BASE_NS) +#define DPHY_NS ((DPHY_TypeDef *) DPHY_BASE_NS) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) +#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS) +#define RAMCFG_SRAM5_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define DCACHE2_NS ((DCACHE_TypeDef *) DCACHE2_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GTZC_MPCBB5_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_NS) +#define GFXMMU_NS ((GFXMMU_TypeDef *) GFXMMU_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GPIOI_NS ((GPIO_TypeDef *) GPIOI_BASE_NS) +#define GPIOJ_NS ((GPIO_TypeDef *) GPIOJ_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define USB_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define OTFDEC1_NS ((OTFDEC_TypeDef *) OTFDEC1_BASE_NS) +#define OTFDEC1_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_NS) +#define OTFDEC1_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_NS) +#define OTFDEC1_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_NS) +#define OTFDEC1_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_NS) +#define OTFDEC2_NS ((OTFDEC_TypeDef *) OTFDEC2_BASE_NS) +#define OTFDEC2_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_NS) +#define OTFDEC2_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_NS) +#define OTFDEC2_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_NS) +#define OTFDEC2_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) +#define DLYB_OCTOSPI2_NS ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_NS) +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS) +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define OCTOSPI2_NS ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS) +#define HSPI1_NS ((HSPI_TypeDef *) HSPI1_R_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS) +#define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS) +#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) +#define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS) +#define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS) +#define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS) +#define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS) +#define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) +#define USART6_S ((USART_TypeDef *) USART6_BASE_S) +#define I2C5_S ((I2C_TypeDef *) I2C5_BASE_S) +#define I2C6_S ((I2C_TypeDef *) I2C6_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) + +/*!< APB2 Secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) +#define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S) +#define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S) +#define LTDC_S ((LTDC_TypeDef *) LTDC_BASE_S) +#define LTDC_Layer1_S ((LTDC_Layer_TypeDef *) LTDC_Layer1_BASE_S) +#define LTDC_Layer2_S ((LTDC_Layer_TypeDef *) LTDC_Layer2_BASE_S) +#define DSI_S ((DSI_TypeDef *) DSI_BASE_S) +#define REFBIAS_S ((REFBIAS_TypeDef *) REFBIAS_BASE_S) +#define DPHY_S ((DPHY_TypeDef *) DPHY_BASE_S) + +/*!< APB3 secure peripherals */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) +#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) +#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S) +#define RAMCFG_SRAM5_S ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define DCACHE2_S ((DCACHE_TypeDef *) DCACHE2_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GTZC_MPCBB5_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_S) +#define GFXMMU_S ((GFXMMU_TypeDef *) GFXMMU_BASE_S) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GPIOI_S ((GPIO_TypeDef *) GPIOI_BASE_S) +#define GPIOJ_S ((GPIO_TypeDef *) GPIOJ_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define USB_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_S) +#define AES_S ((AES_TypeDef *) AES_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SAES_S ((AES_TypeDef *) SAES_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define OTFDEC1_S ((OTFDEC_TypeDef *) OTFDEC1_BASE_S) +#define OTFDEC1_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_S) +#define OTFDEC1_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_S) +#define OTFDEC1_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_S) +#define OTFDEC1_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_S) +#define OTFDEC2_S ((OTFDEC_TypeDef *) OTFDEC2_BASE_S) +#define OTFDEC2_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_S) +#define OTFDEC2_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_S) +#define OTFDEC2_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_S) +#define OTFDEC2_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) +#define DLYB_OCTOSPI2_S ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_S) +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S) +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define OCTOSPI2_S ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S) +#define HSPI1_S ((HSPI_TypeDef *) HSPI1_R_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S) +#define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S) +#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) +#define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S) +#define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S) +#define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S) +#define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S) +#define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S) + +/*!< DBGMCU peripheral */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define SRAM4_BASE SRAM4_BASE_S +#define SRAM5_BASE SRAM5_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define FMAC FMAC_S +#define FMAC_BASE FMAC_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define LPDMA1 LPDMA1_S +#define LPDMA1_BASE LPDMA1_BASE_S + +#define LPDMA1_Channel0 LPDMA1_Channel0_S +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S + +#define LPDMA1_Channel1 LPDMA1_Channel1_S +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S + +#define LPDMA1_Channel2 LPDMA1_Channel2_S +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S + +#define LPDMA1_Channel3 LPDMA1_Channel3_S +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define GPIOI GPIOI_S +#define GPIOI_BASE GPIOI_BASE_S + +#define GPIOJ GPIOJ_S +#define GPIOJ_BASE GPIOJ_BASE_S + +#define LPGPIO1 LPGPIO1_S +#define LPGPIO1_BASE LPGPIO1_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_S +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_S +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define DCACHE2 DCACHE2_S +#define DCACHE2_BASE DCACHE2_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZSC2 GTZC_TZSC2_S +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_TZIC2 GTZC_TZIC2_S +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define GTZC_MPCBB4 GTZC_MPCBB4_S +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S + +#define GTZC_MPCBB5 GTZC_MPCBB5_S +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define I2C5 I2C5_S +#define I2C5_BASE I2C5_BASE_S + +#define I2C6 I2C6_S +#define I2C6_BASE I2C6_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define DAC DAC_S +#define DAC_BASE DAC_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define OPAMP OPAMP_S +#define OPAMP_BASE OPAMP_BASE_S + +#define OPAMP1 OPAMP1_S +#define OPAMP1_BASE OPAMP1_BASE_S + +#define OPAMP2 OPAMP2_S +#define OPAMP2_BASE OPAMP2_BASE_S + +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define COMP12 COMP12_S +#define COMP12_BASE COMP12_BASE_S + +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S + +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S + +#define COMP12_COMMON COMP12_COMMON_S +#define COMP12_COMMON_BASE COMP1_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + +#define SAI2 SAI2_S +#define SAI2_BASE SAI2_BASE_S + +#define SAI2_Block_A SAI2_Block_A_S +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S + +#define SAI2_Block_B SAI2_Block_B_S +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + + +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S + +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define AES AES_S +#define AES_BASE AES_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S + +#define OTFDEC1 OTFDEC1_S +#define OTFDEC1_BASE OTFDEC1_BASE_S + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_S +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_S + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_S +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_S + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_S +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_S + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_S +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_S + +#define OTFDEC2 OTFDEC2_S +#define OTFDEC2_BASE OTFDEC2_BASE_S + +#define OTFDEC2_REGION1 OTFDEC2_REGION1_S +#define OTFDEC2_REGION1_BASE OTFDEC2_REGION1_BASE_S + +#define OTFDEC2_REGION2 OTFDEC2_REGION2_S +#define OTFDEC2_REGION2_BASE OTFDEC2_REGION2_BASE_S + +#define OTFDEC2_REGION3 OTFDEC2_REGION3_S +#define OTFDEC2_REGION3_BASE OTFDEC2_REGION3_BASE_S + +#define OTFDEC2_REGION4 OTFDEC2_REGION4_S +#define OTFDEC2_REGION4_BASE OTFDEC2_REGION4_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + +#define SDMMC2 SDMMC2_S +#define SDMMC2_BASE SDMMC2_BASE_S + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define OCTOSPI2 OCTOSPI2_S +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_S + +#define OCTOSPIM OCTOSPIM_S +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_SDMMC2 DLYB_SDMMC2_S +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_S +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_S + +#define HSPI1 HSPI1_S +#define HSPI1_R_BASE HSPI1_R_BASE_S + +#define DMA2D DMA2D_S +#define DMA2D_BASE DMA2D_BASE_S + +#define USB_OTG_HS USB_OTG_HS_S +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_S + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#define GFXMMU GFXMMU_S +#define GFXMMU_BASE GFXMMU_BASE_S +/* GFXMMU virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE GFXMMU_VIRTUAL_BUFFERS_BASE_S +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_S +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_S +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_S +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_S + +#define GPU2D GPU2D_BASE_S + +#define LTDC LTDC_S +#define LTDC_BASE LTDC_BASE_S + +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_S +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_S + +#define DSI DSI_S +#define DSI_BASE DSI_BASE_S + +#define REFBIAS REFBIAS_S +#define REFBIAS_BASE REFBIAS_BASE_S + +#define DPHY DPHY_S +#define DPHY_BASE DPHY_BASE_S + +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM3_BASE SRAM3_BASE_NS +#define SRAM4_BASE SRAM4_BASE_NS +#define SRAM5_BASE SRAM5_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DMA2D DMA2D_NS +#define DMA2D_BASE DMA2D_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define FMAC FMAC_NS +#define FMAC_BASE FMAC_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define LPDMA1 LPDMA1_NS +#define LPDMA1_BASE LPDMA1_BASE_NS + +#define LPDMA1_Channel0 LPDMA1_Channel0_NS +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS + +#define LPDMA1_Channel1 LPDMA1_Channel1_NS +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS + +#define LPDMA1_Channel2 LPDMA1_Channel2_NS +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS + +#define LPDMA1_Channel3 LPDMA1_Channel3_NS +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define GPIOI GPIOI_NS +#define GPIOI_BASE GPIOI_BASE_NS +#define GPIOJ GPIOJ_NS +#define GPIOJ_BASE GPIOJ_BASE_NS + +#define LPGPIO1 LPGPIO1_NS +#define LPGPIO1_BASE LPGPIO1_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_NS +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_NS +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define DCACHE2 DCACHE2_NS +#define DCACHE2_BASE DCACHE2_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZSC2 GTZC_TZSC2_NS +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_TZIC2 GTZC_TZIC2_NS +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define GTZC_MPCBB4 GTZC_MPCBB4_NS +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS + +#define GTZC_MPCBB5 GTZC_MPCBB5_NS +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define I2C5 I2C5_NS +#define I2C5_BASE I2C5_BASE_NS + +#define I2C6 I2C6_NS +#define I2C6_BASE I2C6_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define OPAMP OPAMP_NS +#define OPAMP_BASE OPAMP_BASE_NS + +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS + +#define OPAMP2 OPAMP2_NS +#define OPAMP2_BASE OPAMP2_BASE_NS + +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define COMP12 COMP12_NS +#define COMP12_BASE COMP12_BASE_NS + +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS + +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS + +#define COMP12_COMMON COMP12_COMMON_NS +#define COMP12_COMMON_BASE COMP1_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + +#define SAI2 SAI2_NS +#define SAI2_BASE SAI2_BASE_NS + +#define SAI2_Block_A SAI2_Block_A_NS +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS + +#define SAI2_Block_B SAI2_Block_B_NS +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS + +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define AES AES_NS +#define AES_BASE AES_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS + +#define OTFDEC1 OTFDEC1_NS +#define OTFDEC1_BASE OTFDEC1_BASE_NS + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_NS +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_NS + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_NS +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_NS + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_NS +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_NS + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_NS +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_NS + +#define OTFDEC2 OTFDEC2_NS +#define OTFDEC2_BASE OTFDEC2_BASE_NS + +#define OTFDEC2_REGION1 OTFDEC2_REGION1_NS +#define OTFDEC2_REGION1_BASE OTFDEC2_REGION1_BASE_NS + +#define OTFDEC2_REGION2 OTFDEC2_REGION2_NS +#define OTFDEC2_REGION2_BASE OTFDEC2_REGION2_BASE_NS + +#define OTFDEC2_REGION3 OTFDEC2_REGION3_NS +#define OTFDEC2_REGION3_BASE OTFDEC2_REGION3_BASE_NS + +#define OTFDEC2_REGION4 OTFDEC2_REGION4_NS +#define OTFDEC2_REGION4_BASE OTFDEC2_REGION4_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + +#define SDMMC2 SDMMC2_NS +#define SDMMC2_BASE SDMMC2_BASE_NS + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define OCTOSPI2 OCTOSPI2_NS +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_NS + +#define OCTOSPIM OCTOSPIM_NS +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_SDMMC2 DLYB_SDMMC2_NS +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_NS +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_NS + +#define HSPI1 HSPI1_NS +#define HSPI1_R_BASE HSPI1_R_BASE_NS + +#define USB_OTG_HS USB_OTG_HS_NS +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_NS + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS +#define GFXMMU GFXMMU_NS +#define GFXMMU_BASE GFXMMU_BASE_NS +/* GFXMMU virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE GFXMMU_VIRTUAL_BUFFERS_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_NS + +#define GPU2D GPU2D_BASE_NS + +#define LTDC LTDC_NS +#define LTDC_BASE LTDC_BASE_NS + +#define LTDC_Layer1 LTDC_Layer1_NS +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_NS + +#define LTDC_Layer2 LTDC_Layer2_NS +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_NS + +#define DSI DSI_NS +#define DSI_BASE DSI_BASE_NS + +#define REFBIAS REFBIAS_NS +#define REFBIAS_BASE REFBIAS_BASE_NS + +#define DPHY DPHY_NS +#define DPHY_BASE DPHY_BASE_NS + +#endif + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +#define ADC_MULTIMODE_SUPPORT +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ +#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_ADCALLIN_Pos (16U) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ + +#define ADC_CR_CALINDEX_Pos (24U) +#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ +#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ +#define ADC_CR_CALINDEX0_Pos (24U) +#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ +#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ +#define ADC_CR_CALINDEX1_Pos (25U) +#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ +#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ +#define ADC_CR_CALINDEX2_Pos (26U) +#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ +#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ +#define ADC_CR_CALINDEX3_Pos (27U) +#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ +#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR1_DMNGT_Pos (0U) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC4_CFGR1_DMAEN_Pos (0U) +#define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC4_CFGR1_DMACFG_Pos (1U) +#define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC4_CFGR1_SCANDIR_Pos (4U) +#define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC4_CFGR1_ALIGN_Pos (5U) +#define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (5U) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ + +#define ADC_CFGR1_AUTDLY_Pos (14U) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC4_CFGR1_WAIT_Pos (14U) +#define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR1_DISCNUM_Pos (17U) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20U) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR1_JAWD1EN_Pos (24U) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR1_JAUTO_Pos (25U) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +/* Specific ADC4 */ +#define ADC4_CFGR1_EXTSEL_Pos (6U) +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ + +#define ADC4_CFGR1_CHSELRMOD_Pos (21U) +#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_BULB_Pos (13U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (27U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* Specific ADC4 */ +#define ADC4_CFGR2_OVSR_Pos (2U) +#define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC4_CFGR2_LFTRIG_Pos (29U) +#define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC4_SMPR_SMP1_Pos (0U) +#define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC4_SMPR_SMP2_Pos (4U) +#define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC4_SMPR_SMPSEL_Pos (8U) +#define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ +#define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ +#define ADC4_SMPR_SMPSEL0_Pos (8U) +#define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ +#define ADC4_SMPR_SMPSEL1_Pos (9U) +#define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ +#define ADC4_SMPR_SMPSEL2_Pos (10U) +#define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ +#define ADC4_SMPR_SMPSEL3_Pos (11U) +#define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ +#define ADC4_SMPR_SMPSEL4_Pos (12U) +#define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ +#define ADC4_SMPR_SMPSEL5_Pos (13U) +#define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ +#define ADC4_SMPR_SMPSEL6_Pos (14U) +#define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ +#define ADC4_SMPR_SMPSEL7_Pos (15U) +#define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ +#define ADC4_SMPR_SMPSEL8_Pos (16U) +#define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ +#define ADC4_SMPR_SMPSEL9_Pos (17U) +#define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ +#define ADC4_SMPR_SMPSEL10_Pos (18U) +#define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ +#define ADC4_SMPR_SMPSEL11_Pos (19U) +#define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ +#define ADC4_SMPR_SMPSEL12_Pos (20U) +#define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ +#define ADC4_SMPR_SMPSEL13_Pos (21U) +#define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ +#define ADC4_SMPR_SMPSEL14_Pos (22U) +#define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ +#define ADC4_SMPR_SMPSEL15_Pos (23U) +#define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ +#define ADC4_SMPR_SMPSEL16_Pos (24U) +#define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ +#define ADC4_SMPR_SMPSEL17_Pos (25U) +#define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ +#define ADC4_SMPR_SMPSEL18_Pos (26U) +#define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ +#define ADC4_SMPR_SMPSEL19_Pos (27U) +#define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ +#define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ +#define ADC4_SMPR_SMPSEL20_Pos (26U) +#define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ +#define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL21_Pos (26U) +#define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ +#define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL22_Pos (30U) +#define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ +#define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ +#define ADC4_SMPR_SMPSEL23_Pos (31U) +#define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ +#define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +#define ADC_HTR_AWDFILT_Pos (29U) +#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ +#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_PW register ********************/ +#define ADC4_PWRR_AUTOFF_Pos (0U) +#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ +#define ADC4_PWRR_DPD_Pos (1U) +#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ +#define ADC4_PWRR_VREFPROT_Pos (2U) +#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ +#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ +#define ADC4_PWRR_VREFSECSMP_Pos (3U) +#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ +#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ + +/* Legacy definitions */ +#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos +#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk +#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF +#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos +#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk +#define ADC4_PW_DPD ADC4_PWRR_DPD +#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos +#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk +#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT +#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos +#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk +#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_USAT_Pos (25U) +#define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_SSAT_Pos (26U) +#define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (27U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR2_USAT_Pos (25U) +#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR2_SSAT_Pos (26U) +#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (27U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR3_USAT_Pos (25U) +#define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR3_SSAT_Pos (26U) +#define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (27U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR4_USAT_Pos (25U) +#define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR4_SSAT_Pos (26U) +#define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (27U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_GCOMP register ********************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ +#define ADC_GCOMP_GCOMP_Pos (31U) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19U) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20U) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21U) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22U) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL23_Pos (23U) +#define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_I_APB_ADDR_Pos (0U) +#define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ +#define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ + +#define ADC_CALFACT_I_APB_DATA_Pos (08U) +#define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ +#define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ + +#define ADC_CALFACT_VALIDITY_Pos (16U) +#define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_LATCH_COEF_Pos (24U) +#define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CAPTURE_COEF_Pos (25U) +#define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ + +#define ADC4_CALFACT_CALFACT_Pos (0U) +#define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_CALFACT_Pos (0U) +#define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */ +#define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */ +#define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OR register ********************/ +#define ADC_OR_CHN0SEL_Pos (0U) +#define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ +#define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_LDORDY_MST_Pos (12U) +#define ADC_CSR_LDORDY_MST_Msk (0x1UL << ADC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADC_CSR_LDORDY_MST ADC_CSR_LDORDY_MST_Msk /*!< Voltage regulator ready flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_LDORDY_SLV_Pos (28U) +#define ADC_CSR_LDORDY_SLV_Msk (0x1UL << ADC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CSR_LDORDY_SLV ADC_CSR_LDORDY_SLV_Msk /*!< Voltage regulator ready flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DAMDF_Pos (14U) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_VSENSEEN_Pos (23U) +#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ +#define ADC_CCR_VDDCOREN_Pos (26U) +#define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ +#define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0U) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) + +#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ + +#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11U) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ1_Pos (12U) +#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */ +#define FLASH_ACR_PDREQ2_Pos (13U) +#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */ +#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14U) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0U) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1U) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3U) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4U) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5U) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6U) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7U) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13U) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16U) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17U) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18U) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19U) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD1_Pos (20U) +#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */ +#define FLASH_NSSR_PD2_Pos (21U) +#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */ +#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0U) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1U) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3U) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4U) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5U) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6U) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7U) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16U) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17U) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR register *****************/ +#define FLASH_NSCR_PG_Pos (0U) +#define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR_PER_Pos (1U) +#define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR_MER1_Pos (2U) +#define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */ +#define FLASH_NSCR_PNB_Pos (3U) +#define FLASH_NSCR_PNB_Msk (0xFFUL << FLASH_NSCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR_BKER_Pos (11U) +#define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */ +#define FLASH_NSCR_BWR_Pos (14U) +#define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR_MER2_Pos (15U) +#define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */ +#define FLASH_NSCR_STRT_Pos (16U) +#define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR_OPTSTRT_Pos (17U) +#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR_EOPIE_Pos (24U) +#define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR_ERRIE_Pos (25U) +#define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR_OBL_LAUNCH_Pos (27U) +#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR_OPTLOCK_Pos (30U) +#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR_LOCK_Pos (31U) +#define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR register ****************/ +#define FLASH_SECCR_PG_Pos (0U) +#define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR_PER_Pos (1U) +#define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR_MER1_Pos (2U) +#define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR_PNB_Pos (3U) +#define FLASH_SECCR_PNB_Msk (0xFFUL << FLASH_SECCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR_BKER_Pos (11U) +#define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */ +#define FLASH_SECCR_BWR_Pos (14U) +#define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR_MER2_Pos (15U) +#define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */ +#define FLASH_SECCR_STRT_Pos (16U) +#define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR_EOPIE_Pos (24U) +#define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR_ERRIE_Pos (25U) +#define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR_INV_Pos (29U) +#define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR_LOCK_Pos (31U) +#define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0x1FFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x001FFFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_BK_ECC_Pos (21U) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (22U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0x1FFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x001FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */ +#define FLASH_OPSR_BK_OP_Pos (21U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (22U) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8U) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_nRST_SHDW_Pos (14U) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ +#define FLASH_OPTR_SRAM_RST_Pos (15U) +#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SWAP_BANK_Pos (20U) +#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */ +#define FLASH_OPTR_DUALBANK_Pos (21U) +#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */ +#define FLASH_OPTR_BKPRAM_ECC_Pos (22U) +#define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTR_SRAM3_ECC_Pos (23U) +#define FLASH_OPTR_SRAM3_ECC_Msk (0x1UL << FLASH_OPTR_SRAM3_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_SRAM3_ECC FLASH_OPTR_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */ +#define FLASH_OPTR_SRAM2_ECC_Pos (24U) +#define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25U) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26U) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_PA15_PUPEN_Pos (28U) +#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */ +#define FLASH_OPTR_IO_VDD_HSLV_Pos (29U) +#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */ +#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30U) +#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */ +#define FLASH_OPTR_TZEN_Pos (31U) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7U) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7U) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0U) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7U) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWM1R1 register **************/ +#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0U) +#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16U) +#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWM1R2 register **************/ +#define FLASH_SECWM1R2_HDP1_PEND_Pos (16U) +#define FLASH_SECWM1R2_HDP1_PEND_Msk (0xFFUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWM1R2_HDP1EN_Pos (31U) +#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0U) +#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */ +#define FLASH_WRP1AR_WRP1A_PEND_Pos (16U) +#define FLASH_WRP1AR_WRP1A_PEND_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */ +#define FLASH_WRP1AR_UNLOCK_Pos (31U) +#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0U) +#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */ +#define FLASH_WRP1BR_WRP1B_PEND_Pos (16U) +#define FLASH_WRP1BR_WRP1B_PEND_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */ +#define FLASH_WRP1BR_UNLOCK_Pos (31U) +#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */ + +/***************** Bits definition for FLASH_SECWM2R1 register **************/ +#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0U) +#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */ +#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16U) +#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */ + +/***************** Bits definition for FLASH_SECWM2R2 register **************/ +#define FLASH_SECWM2R2_HDP2_PEND_Pos (16U) +#define FLASH_SECWM2R2_HDP2_PEND_Msk (0xFFUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */ +#define FLASH_SECWM2R2_HDP2EN_Pos (31U) +#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */ + +/****************** Bits definition for FLASH_WRP2AR register ***************/ +#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0U) +#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */ +#define FLASH_WRP2AR_WRP2A_PEND_Pos (16U) +#define FLASH_WRP2AR_WRP2A_PEND_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */ +#define FLASH_WRP2AR_UNLOCK_Pos (31U) +#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP2BR register ***************/ +#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0U) +#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */ +#define FLASH_WRP2BR_WRP2B_PEND_Pos (16U) +#define FLASH_WRP2BR_WRP2B_PEND_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */ +#define FLASH_WRP2BR_UNLOCK_Pos (31U) +#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0U) +#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */ +#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1U) +#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */ +#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0U) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1U) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************************************************************************/ +/* */ +/* Filter Mathematical ACcelerator unit (FMAC) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1_BASE_Pos (0U) +#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U) +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ +#define FMAC_X1BUFCFG_FULL_WM_Pos (24U) +#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ +#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ + +/***************** Bit definition for FMAC_X2BUFCFG register ****************/ +#define FMAC_X2BUFCFG_X2_BASE_Pos (0U) +#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U) +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ + +/***************** Bit definition for FMAC_YBUFCFG register *****************/ +#define FMAC_YBUFCFG_Y_BASE_Pos (0U) +#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ +#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U) +#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ +#define FMAC_YBUFCFG_EMPTY_WM_Pos (24U) +#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ +#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ + +/****************** Bit definition for FMAC_PARAM register ******************/ +#define FMAC_PARAM_P_Pos (0U) +#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ +#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ +#define FMAC_PARAM_Q_Pos (8U) +#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ +#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ +#define FMAC_PARAM_R_Pos (16U) +#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ +#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ +#define FMAC_PARAM_FUNC_Pos (24U) +#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ +#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ +#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ +#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ +#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ +#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ +#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ +#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ +#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ +#define FMAC_PARAM_START_Pos (31U) +#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ +#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ + +/******************** Bit definition for FMAC_CR register *******************/ +#define FMAC_CR_RIEN_Pos (0U) +#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ +#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ +#define FMAC_CR_WIEN_Pos (1U) +#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ +#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ +#define FMAC_CR_OVFLIEN_Pos (2U) +#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ +#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ +#define FMAC_CR_UNFLIEN_Pos (3U) +#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ +#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ +#define FMAC_CR_SATIEN_Pos (4U) +#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ +#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ +#define FMAC_CR_DMAREN_Pos (8U) +#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ +#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ +#define FMAC_CR_DMAWEN_Pos (9U) +#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ +#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ +#define FMAC_CR_CLIPEN_Pos (15U) +#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ +#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ +#define FMAC_CR_RESET_Pos (16U) +#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ +#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_SR register ********************/ +#define FMAC_SR_YEMPTY_Pos (0U) +#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ +#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ +#define FMAC_SR_X1FULL_Pos (1U) +#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ +#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ +#define FMAC_SR_OVFL_Pos (8U) +#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ +#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ +#define FMAC_SR_UNFL_Pos (9U) +#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ +#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ +#define FMAC_SR_SAT_Pos (10U) +#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ +#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ + +/****************** Bit definition for FMAC_WDATA register ******************/ +#define FMAC_WDATA_WDATA_Pos (0U) +#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ + +/****************** Bit definition for FMACX_RDATA register *****************/ +#define FMAC_RDATA_RDATA_Pos (0U) +#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20U) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk + +/******************** Bits definition for TAMP_COUNTR register ***************/ +#define TAMP_COUNTR_Pos (16U) +#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ +#define TAMP_COUNTR TAMP_COUNTR_Msk + +/******************** Bits definition for TAMP_ERCFGR register ***************/ +#define TAMP_ERCFGR0_Pos (0U) +#define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* Touch Sensing Controller (TSC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TSC_CR register *********************/ +#define TSC_CR_TSCE_Pos (0U) +#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ +#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/** @addtogroup STM32U5xx_Peripheral_Exported_macros + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S) || \ + ((INSTANCE) == ADC2_NS) || \ + ((INSTANCE) == ADC2_S) || \ + ((INSTANCE) == ADC4_NS) || \ + ((INSTANCE) == ADC4_S)) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)) + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \ + ((INSTANCE) == ADC12_COMMON_S) || \ + ((INSTANCE) == ADC4_COMMON_NS) || \ + ((INSTANCE) == ADC4_COMMON_S)) + +/******************************* AES Instances ********************************/ +#define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES_NS) || ((INSTANCE) == AES_S)) + +/******************************* PKA Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************** FDCAN Instances *****************************/ +#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S)) + +/******************************** COMP Instances ******************************/ +#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \ + ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S)) + +/******************** COMP Instances with window mode capability **************/ +#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \ + ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S)) + +/******************************* CORDIC Instances *****************************/ +#define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) + +/******************************* DAC Instances ********************************/ +#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) + +/******************************* DELAYBLOCK Instances *******************************/ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \ + ((INSTANCE) == DLYB_SDMMC2_NS) || \ + ((INSTANCE) == DLYB_SDMMC1_S) || \ + ((INSTANCE) == DLYB_SDMMC2_S) || \ + ((INSTANCE) == DLYB_OCTOSPI1_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI2_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI1_S) || \ + ((INSTANCE) == DLYB_OCTOSPI2_S )) + +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ + ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ + ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ + ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ + ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S) || \ + ((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ + ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ + ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ + ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) + +#define IS_GPDMA_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ + ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ + ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ + ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ + ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) + +#define IS_LPDMA_INSTANCE(INSTANCE) (((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ + ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ + ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ + ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) + +#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) + +/****************************** OTFDEC Instances ********************************/ +#define IS_OTFDEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OTFDEC1_NS) || ((INSTANCE) == OTFDEC1_S) || \ + ((INSTANCE) == OTFDEC2_NS) || ((INSTANCE) == OTFDEC2_S)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_SRAM4_NS) || ((INSTANCE) == RAMCFG_SRAM4_S) || \ + ((INSTANCE) == RAMCFG_SRAM5_NS) || ((INSTANCE) == RAMCFG_SRAM5_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG ECC Instances *****************************/ +#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG IT Instances ******************************/ +#define IS_RAMCFG_IT_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) + +/******************************** FMAC Instances ******************************/ +#define IS_FMAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FMAC_NS) || ((INSTANCE) == FMAC_S)) + +/******************************* GFXMMU Instances *******************************/ +#define IS_GFXMMU_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GFXMMU_NS) || ((INSTANCE) == GFXMMU_S)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \ + ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \ + ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \ + ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \ + ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \ + ((INSTANCE) == GPIOF_NS) || ((INSTANCE) == GPIOF_S) || \ + ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \ + ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S) || \ + ((INSTANCE) == GPIOI_NS) || ((INSTANCE) == GPIOI_S) || \ + ((INSTANCE) == GPIOJ_NS) || ((INSTANCE) == GPIOJ_S) || \ + ((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) + +/******************************* LPGPIO Instances *****************************/ +#define IS_LPGPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) + +/****************************** LTDC Instances ********************************/ +#define IS_LTDC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == LTDC_NS) || ((__INSTANCE__) == LTDC_S)) + +/****************************** DSI Instances ********************************/ +#define IS_DSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DSI_NS) || ((__INSTANCE__) == DSI_S)) + +/******************************* DMA2D Instances *******************************/ +#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA2D_NS) || ((__INSTANCE__) == DMA2D_S)) + +/******************************* DCMI Instances *******************************/ +#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) + +/******************************* DCACHE Instances *****************************/ +#define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S) || \ + ((INSTANCE) == DCACHE2_NS) || ((INSTANCE) == DCACHE2_S)) + +/******************************* PSSI Instances *******************************/ +#define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) + +/******************************* GPIO AF Instances ****************************/ +/* On U5, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On U5, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************* I2C Instances : Group belongingness *********************/ +#define IS_I2C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +#define IS_I2C_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/****************************** OPAMP Instances *******************************/ +#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1_NS) || ((INSTANCE) == OPAMP1_S) || \ + ((INSTANCE) == OPAMP2_NS) || ((INSTANCE) == OPAMP2_S)) + +/******************************* OSPI Instances *******************************/ +#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S) || \ + ((INSTANCE) == OCTOSPI2_NS) || ((INSTANCE) == OCTOSPI2_S)) + +/******************************* HSPI Instances *******************************/ +#define IS_HSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HSPI1_NS) || ((INSTANCE) == HSPI1_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \ + ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S) || \ + ((INSTANCE) == SAI2_Block_A_NS) || ((INSTANCE) == SAI2_Block_A_S) || \ + ((INSTANCE) == SAI2_Block_B_NS) || ((INSTANCE) == SAI2_Block_B_S)) + +/****************************** SDMMC Instances *******************************/ +#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S) || \ + ((INSTANCE) == SDMMC2_NS) || ((INSTANCE) == SDMMC2_S)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +/******************* SMBUS Instances : Group belongingness *********************/ +#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) + +#define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) + +#define IS_SPI_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ +#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) ||\ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) ||\ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) ||\ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) ||\ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) ||\ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) ||\ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)||\ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : supporting HSE32 as input ********************/ +#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) ||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ + ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ + ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S) || \ + ((__INSTANCE__) == TIM4_NS) || ((__INSTANCE__) == TIM4_S) || \ + ((__INSTANCE__) == TIM5_NS) || ((__INSTANCE__) == TIM5_S) || \ + ((__INSTANCE__) == TIM6_NS) || ((__INSTANCE__) == TIM6_S) || \ + ((__INSTANCE__) == TIM7_NS) || ((__INSTANCE__) == TIM7_S) || \ + ((__INSTANCE__) == TIM8_NS) || ((__INSTANCE__) == TIM8_S) || \ + ((__INSTANCE__) == TIM15_NS) || ((__INSTANCE__) == TIM15_S)) + +/****************************** TSC Instances *********************************/ +#define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S))|| \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S))|| \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : AUTONOMOUS mode ***************************/ +#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +/****************************** UCPD Instances ********************************/ +#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S)) + +/******************************* OTG FS HCD Instances *************************/ +#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_HS_NS) || ((INSTANCE) == USB_OTG_HS_S)) + +/******************************* OTG FS PCD Instances *************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_HS_NS) || ((INSTANCE) == USB_OTG_HS_S)) + +/******************************* MDF/ADF Instances ****************************/ +#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_NS) || ((INSTANCE) == MDF1_Filter0_S) || \ + ((INSTANCE) == MDF1_Filter1_NS) || ((INSTANCE) == MDF1_Filter1_S) || \ + ((INSTANCE) == MDF1_Filter2_NS) || ((INSTANCE) == MDF1_Filter2_S) || \ + ((INSTANCE) == MDF1_Filter3_NS) || ((INSTANCE) == MDF1_Filter3_S) || \ + ((INSTANCE) == MDF1_Filter4_NS) || ((INSTANCE) == MDF1_Filter4_S) || \ + ((INSTANCE) == MDF1_Filter5_NS) || ((INSTANCE) == MDF1_Filter5_S) || \ + ((INSTANCE) == ADF1_Filter0_NS) || ((INSTANCE) == ADF1_Filter0_S)) + +/******************************* GPU2D Instances *******************************/ +#define IS_GPU2D_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPU2D_BASE_NS) || ((__INSTANCE__) == GPU2D_BASE_S)) + + +/** @} */ /* End of group STM32U5xx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32U5A9xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5A9xx_H */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u5xx.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u5xx.h index 5b47e6b403b..dc90f470c2a 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u5xx.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMSIS/stm32u5xx.h @@ -56,9 +56,18 @@ application */ -#if !defined (STM32U575xx) && !defined (STM32U585xx) - /* #define STM32U575xx */ /*!< STM32U575CIU6 STM32U575CIT6 STM32U575RIT6 STM32U575VIT6 STM32U575ZIT6 STM32U575QII6 STM32U575AII6 STM32U575CIU6Q STM32U575CIT6Q STM32U575OIY6Q STM32U575VIT6Q STM32U575QII6Q STM32U575ZIT6Q STM32U575RIT6Q STM32U575CGU6 STM32U575CGT6 STM32U575RGT6 STM32U575VGT6 STM32U575ZGT6 STM32U575QGI6 STM32U575AGI6 STM32U575CGU6Q STM32U575CGT6Q STM32U575OGY6Q STM32U575VGT6Q STM32U575QGI6Q STM32U575ZGT6Q STM32U575RGT6Q STM32U575AGI6Q Devices */ - /* #define STM32U585xx */ /*!< STM32U585CIU6 STM32U585CIT6 STM32U585RIT6 STM32U585VIT6 STM32U585AII6 STM32U585QII6 STM32U585ZIT6 STM32U585OIY6Q STM32U585VIT6Q STM32U585QEI6Q STM32U585RIT6Q STM32U585AII6Q STM32U585CIU6Q STM32U585CIT6Q STM32U585ZET6Q Devices */ +#if !defined (STM32U575xx) && !defined (STM32U585xx) \ + && !defined (STM32U595xx) && !defined (STM32U599xx) \ + && !defined (STM32U5A5xx) && !defined (STM32U5A9xx) \ + && !defined (STM32U535xx) && !defined (STM32U545xx) \ + /* #define STM32U575xx */ /*!< STM32U575CIU6 STM32U575CIT6 STM32U575RIT6 STM32U575VIT6 STM32U575ZIT6 STM32U575QII6 STM32U575AII6 STM32U575CIU6Q STM32U575CIT6Q STM32U575OIY6Q STM32U575VIT6Q STM32U575QII6Q STM32U575ZIT6Q STM32U575RIT6Q STM32U575CGU6 STM32U575CGT6 STM32U575RGT6 STM32U575VGT6 STM32U575ZGT6 STM32U575QGI6 STM32U575AGI6 STM32U575CGU6Q STM32U575CGT6Q STM32U575OGY6Q STM32U575VGT6Q STM32U575QGI6Q STM32U575ZGT6Q STM32U575RGT6Q STM32U575AGI6Q Devices */ + /* #define STM32U585xx */ /*!< STM32U585CIU6 STM32U585CIT6 STM32U585RIT6 STM32U585VIT6 STM32U585AII6 STM32U585QII6 STM32U585ZIT6 STM32U585OIY6Q STM32U585VIT6Q STM32U585QEI6Q STM32U585RIT6Q STM32U585AII6Q STM32U585CIU6Q STM32U585CIT6Q STM32U585ZET6Q Devices */ + /* #define STM32U595xx */ /*!< STM32U595ZJT6Q Device */ + /* #define STM32U599xx */ /*!< STM32U599NJH6Q STM32U599BJY6Q STM32U599NIH6Q Devices */ + /* #define STM32U5A5xx */ /*!< STM32U5A5ZJT6Q Device */ + /* #define STM32U5A9xx */ /*!< STM32U5A9NJH6Q STM32U5A9BJY6Q Devices */ + /* #define STM32U535xx */ /*!< STM32U535CET6 STM32U535CEU6 STM32U535RET6 STM32U535REI6 STM32U535VET6 STM32U535VEI6 STM32U535CET6Q STM32U535CEU6Q STM32U535RET6Q STM32U535REI6Q STM32U535VET6Q STM32U535VEI6Q STM32U535NEY6Q STM32U535JEY6Q Device */ + /* #define STM32U545xx */ /*!< STM32U545CET6 STM32U545CEU6 STM32U545RET6 STM32U545REI6 STM32U545VET6 STM32U545VEI6 STM32U545CET6Q STM32U545CEU6Q STM32U545RET6Q STM32U545REI6Q STM32U545VET6Q STM32U545VEI6Q STM32U545NEY6Q STM32U545JEY6Q Device */ #endif /* Tip: To avoid modifying this file each time you need to switch between these @@ -74,12 +83,12 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number 1.0.0 + * @brief CMSIS Device version number 1.2.0 */ -#define __STM32U5_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32U5_CMSIS_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __STM32U5_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32U5_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32U5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32U5_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ +#define __STM32U5_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32U5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32U5_CMSIS_VERSION ((__STM32U5_CMSIS_VERSION_MAIN << 24U)\ |(__STM32U5_CMSIS_VERSION_SUB1 << 16U)\ |(__STM32U5_CMSIS_VERSION_SUB2 << 8U )\ @@ -97,6 +106,18 @@ #include "stm32u575xx.h" #elif defined(STM32U585xx) #include "stm32u585xx.h" +#elif defined(STM32U595xx) + #include "stm32u595xx.h" +#elif defined(STM32U599xx) + #include "stm32u599xx.h" +#elif defined(STM32U5A5xx) + #include "stm32u5a5xx.h" +#elif defined(STM32U5A9xx) + #include "stm32u5a9xx.h" +#elif defined(STM32U535xx) + #include "stm32u535xx.h" +#elif defined(STM32U545xx) + #include "stm32u545xx.h" #else #error "Please select first the target STM32U5xx device used in your application (in stm32u5xx.h file)" #endif diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMakeLists.txt index 4e339f24521..2224289f80d 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/CMakeLists.txt @@ -22,12 +22,15 @@ target_sources(mbed-stm32u5cube-fw STM32U5xx_HAL_Driver/stm32u5xx_hal_dma.c STM32U5xx_HAL_Driver/stm32u5xx_hal_dma2d.c STM32U5xx_HAL_Driver/stm32u5xx_hal_dma_ex.c + STM32U5xx_HAL_Driver/stm32u5xx_hal_dsi.c STM32U5xx_HAL_Driver/stm32u5xx_hal_exti.c STM32U5xx_HAL_Driver/stm32u5xx_hal_fdcan.c STM32U5xx_HAL_Driver/stm32u5xx_hal_flash.c STM32U5xx_HAL_Driver/stm32u5xx_hal_flash_ex.c STM32U5xx_HAL_Driver/stm32u5xx_hal_fmac.c + STM32U5xx_HAL_Driver/stm32u5xx_hal_gfxmmu.c STM32U5xx_HAL_Driver/stm32u5xx_hal_gpio.c + STM32U5xx_HAL_Driver/stm32u5xx_hal_gpu2d.c STM32U5xx_HAL_Driver/stm32u5xx_hal_gtzc.c STM32U5xx_HAL_Driver/stm32u5xx_hal_hash.c STM32U5xx_HAL_Driver/stm32u5xx_hal_hash_ex.c @@ -38,6 +41,8 @@ target_sources(mbed-stm32u5cube-fw STM32U5xx_HAL_Driver/stm32u5xx_hal_irda.c STM32U5xx_HAL_Driver/stm32u5xx_hal_iwdg.c STM32U5xx_HAL_Driver/stm32u5xx_hal_lptim.c + STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc.c + STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc_ex.c STM32U5xx_HAL_Driver/stm32u5xx_hal_mdf.c STM32U5xx_HAL_Driver/stm32u5xx_hal_mmc.c STM32U5xx_HAL_Driver/stm32u5xx_hal_mmc_ex.c @@ -79,6 +84,7 @@ target_sources(mbed-stm32u5cube-fw STM32U5xx_HAL_Driver/stm32u5xx_hal_usart.c STM32U5xx_HAL_Driver/stm32u5xx_hal_usart_ex.c STM32U5xx_HAL_Driver/stm32u5xx_hal_wwdg.c + STM32U5xx_HAL_Driver/stm32u5xx_hal_xspi.c STM32U5xx_HAL_Driver/stm32u5xx_ll_adc.c STM32U5xx_HAL_Driver/stm32u5xx_ll_comp.c STM32U5xx_HAL_Driver/stm32u5xx_ll_cordic.c diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/Legacy/stm32_hal_legacy.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/Legacy/stm32_hal_legacy.h index 13c30a7c759..011fbcf2762 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/Legacy/stm32_hal_legacy.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/Legacy/stm32_hal_legacy.h @@ -37,14 +37,16 @@ extern "C" { #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR -#if defined(STM32U5) +#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1) #define CRYP_DATATYPE_32B CRYP_NO_SWAP #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP #define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#if defined(STM32U5) #define CRYP_CCF_CLEAR CRYP_CLEAR_CCF #define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF #endif /* STM32U5 */ +#endif /* STM32U5 || STM32H7 || STM32MP1 */ /** * @} */ @@ -104,6 +106,16 @@ extern "C" { #if defined(STM32H7) #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT #endif /* STM32H7 */ + +#if defined(STM32U5) +#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES +#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES +#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE +#endif /* STM32H5 */ /** * @} */ @@ -131,7 +143,8 @@ extern "C" { #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 #if defined(STM32L0) -#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM + input 1 for COMP1, LPTIM input 2 for COMP2 */ #endif #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) @@ -205,6 +218,11 @@ extern "C" { #endif #endif + +#if defined(STM32U5) +#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG +#endif + /** * @} */ @@ -213,6 +231,11 @@ extern "C" { * @{ */ #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +#if defined(STM32U5) +#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE +#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE +#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE +#endif /* STM32U5 */ /** * @} */ @@ -220,10 +243,12 @@ extern "C" { /** @defgroup CRC_Aliases CRC API aliases * @{ */ -#if defined(STM32WL) || defined(STM32WB) || defined(STM32L5) || defined(STM32L4) +#if defined(STM32H5) || defined(STM32C0) #else -#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ -#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for + inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for + inter STM32 series compatibility */ #endif /** * @} @@ -254,12 +279,25 @@ extern "C" { #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) +#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5) #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif -#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) +#if defined(STM32U5) +#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 +#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 +#endif + +#if defined(STM32H5) +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ + defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #endif @@ -324,7 +362,8 @@ extern "C" { #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING -#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ + defined(STM32L4S7xx) || defined(STM32L4S9xx) #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI #endif @@ -401,6 +440,10 @@ extern "C" { #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT #endif /* STM32H7 */ + +#if defined(STM32U5) +#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI +#endif /* STM32U5 */ /** * @} */ @@ -480,7 +523,7 @@ extern "C" { #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 -#if defined(STM32G0) +#if defined(STM32G0) || defined(STM32C0) #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH #else @@ -505,6 +548,9 @@ extern "C" { #define OB_USER_nBOOT0 OB_USER_NBOOT0 #define OB_nBOOT0_RESET OB_NBOOT0_RESET #define OB_nBOOT0_SET OB_NBOOT0_SET +#define OB_USER_SRAM134_RST OB_USER_SRAM_RST +#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE +#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE #endif /* STM32U5 */ /** @@ -549,6 +595,104 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32H5) +#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC +#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC +#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC +#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC +#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC +#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC + +#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC +#define SYSCFG_BREAK_PVD SBS_BREAK_PVD +#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC +#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP + +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 + +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE + +#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 +#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 +#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 +#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 + +#define SYSCFG_ETH_MII SBS_ETH_MII +#define SYSCFG_ETH_RMII SBS_ETH_RMII +#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG + +#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE +#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR +#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG + +#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG + +#define SYSCFG_MPU_NSEC SBS_MPU_NSEC +#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_SAU SBS_SAU +#define SYSCFG_MPU_SEC SBS_MPU_SEC +#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#else +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#endif /* __ARM_FEATURE_CMSE */ + +#define SYSCFG_CLK SBS_CLK +#define SYSCFG_CLASSB SBS_CLASSB +#define SYSCFG_FPU SBS_FPU +#define SYSCFG_ALL SBS_ALL + +#define SYSCFG_SEC SBS_SEC +#define SYSCFG_NSEC SBS_NSEC + +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE + +#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK +#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK +#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK + +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE + +#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS +#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS + +#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT +#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE +#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING +#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS +#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES +#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES +#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS + +#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig +#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig +#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig +#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF +#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster +#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect + +#define HAL_SYSCFG_Lock HAL_SBS_Lock +#define HAL_SYSCFG_GetLock HAL_SBS_GetLock + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes +#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes +#endif /* __ARM_FEATURE_CMSE */ + +#endif /* STM32H5 */ /** @@ -618,14 +762,16 @@ extern "C" { #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS -#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ + STM32H757xx */ #endif /* STM32H7 */ #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \ + defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH @@ -646,6 +792,42 @@ extern "C" { #endif /* STM32F0 || STM32F3 || STM32F1 */ #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 + +#if defined(STM32U5) || defined(STM32H5) +#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#endif /* STM32U5 || STM32H5 */ +#if defined(STM32U5) +#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP +#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose + * @{ + */ +#if defined(STM32U5) +#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB +#endif /* STM32U5 */ +#if defined(STM32H5) +#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 +#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC +#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB +#endif /* STM32H5 */ +#if defined(STM32H5) || defined(STM32U5) +#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX +#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX +#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED +#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED +#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC +#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC +#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV +#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV +#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF +#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON +#endif /* STM32H5 || STM32U5 */ /** * @} */ @@ -826,7 +1008,8 @@ extern "C" { #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE -#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ + defined(STM32L1) || defined(STM32F7) #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX @@ -883,9 +1066,19 @@ extern "C" { #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue +/** + * @} + */ + #if defined(STM32U5) #define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF #define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#define LPTIM_CHANNEL_ALL 0x00000000U #endif /* STM32U5 */ /** * @} @@ -954,7 +1147,7 @@ extern "C" { #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 -#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif @@ -1038,8 +1231,8 @@ extern "C" { #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE @@ -1050,15 +1243,42 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 +#if defined(STM32H5) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM +#endif /* STM32H5 */ + +#if defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2 +#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK +#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE +#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH +#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM +#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL +#endif /* STM32WBA */ + +#if defined(STM32H5) || defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL +#endif /* STM32H5 || STM32WBA */ + +#if defined(STM32F7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK +#endif /* STM32F7 */ + #if defined(STM32H7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT +#endif /* STM32H7 */ +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 -#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL -#endif /* STM32H7 */ +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP +#endif /* STM32F7 || STM32H7 || STM32L0 */ /** * @} @@ -1225,6 +1445,10 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif +#if defined(STM32U5) +#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS +#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK +#endif /** * @} */ @@ -1334,30 +1558,40 @@ extern "C" { #define ETH_MMCRFAECR 0x00000198U #define ETH_MMCRGUFCR 0x000001C4U -#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to + the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from + MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus + or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status + of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and + transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input + frame for transmission */ #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control + de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control + activate threshold */ #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ #if defined(STM32F1) #else #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status + (or time-stamp) */ #endif -#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and + status */ #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ @@ -1528,7 +1762,8 @@ extern "C" { #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ - )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ + HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) #if defined(STM32L0) @@ -1537,8 +1772,10 @@ extern "C" { #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ - )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) -#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ + HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode @@ -1572,16 +1809,21 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ - )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ + HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ + HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ + defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ + defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || + STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ + defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA @@ -1655,10 +1897,111 @@ extern "C" { #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL +#if defined (STM32U5) +#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP +#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP +#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP +#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP +#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP +#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP +#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP +#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP +#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP +#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP +#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP +#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP + +#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP +#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP + +#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP +#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP +#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP +#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP +#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP +#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP +#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP +#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP +#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP +#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP +#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP +#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP +#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP +#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP + +#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP + +#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP +#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP +#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP +#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP +#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP +#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP +#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP +#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP +#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP +#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP +#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP +#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP +#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP +#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP + +#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP +#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP +#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP +#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP +#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP +#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP +#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP +#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP +#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP + + +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP +#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP +#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP +#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP +#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP +#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP +#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP +#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP +#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP + + +#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY +#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY +#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY + +#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN +#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN +#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN +#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN +#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN +#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN + +#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK +#endif + /** * @} */ +/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined(STM32H5) || defined(STM32WBA) +#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey +#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock +#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock +#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets +#endif /* STM32H5 || STM32WBA */ + +/** + * @} + */ + /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ */ @@ -1684,7 +2027,8 @@ extern "C" { #define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ + defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback @@ -1941,7 +2285,8 @@ extern "C" { #define COMP_STOP __HAL_COMP_DISABLE #define COMP_LOCK __HAL_COMP_LOCK -#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ + defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) @@ -2113,8 +2458,10 @@ extern "C" { /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose * @{ */ -#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ /** * @} */ @@ -2273,7 +2620,9 @@ extern "C" { #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig -#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE @@ -2282,8 +2631,12 @@ extern "C" { #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) -#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ + HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ + } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ + HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ + } while(0) #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 @@ -2319,8 +2672,8 @@ extern "C" { #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ - )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ + HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE @@ -2824,6 +3177,11 @@ extern "C" { #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 +#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 #endif #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE @@ -3288,7 +3646,8 @@ extern "C" { #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ + defined(STM32WL) || defined(STM32C0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3401,8 +3760,8 @@ extern "C" { #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 #if defined(STM32U5) -#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL -#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL #define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE #define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE #define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE @@ -3413,7 +3772,112 @@ extern "C" { #define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE #define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE #define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT -#endif +#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK +#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 +#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 +#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 +#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE +#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE + +#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE +#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI +#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI +#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE +#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 +#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 +#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 +#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 +#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE +#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM + +#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE +#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE +#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE +#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE +#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE +#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE +#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE +#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE +#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE +#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE + +#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE +#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE +#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE +#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE +#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG +#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG +#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG +#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE +#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE +#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE +#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE +#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG + +#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE +#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE +#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE +#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE +#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG +#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG + +#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE +#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE +#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE +#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE +#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG +#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG + +#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 +#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 +#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 +#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 + +#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE +#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM + +#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE +#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI +#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI +#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE + +#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 +#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 +#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 +#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 + +#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE +#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM + +#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE +#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI +#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI +#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE + + +#endif /* STM32H5 */ + /** * @} */ @@ -3430,7 +3894,9 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ + defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3483,6 +3949,11 @@ extern "C" { #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE +#if defined (STM32H5) +#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE +#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE +#endif /* STM32H5 */ + /** * @} */ @@ -3494,12 +3965,14 @@ extern "C" { #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) #define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE #define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE #define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE #define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV #define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV +#endif #if defined(STM32F4) || defined(STM32F2) #define SD_SDMMC_DISABLED SD_SDIO_DISABLED @@ -3829,6 +4302,16 @@ extern "C" { * @} */ +/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32F7) +#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE +#endif /* STM32F7 */ +/** + * @} + */ + /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose * @{ */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal.c index 45a84599c37..6b4482818fa 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal.c @@ -52,10 +52,10 @@ * @{ */ /** - * @brief STM32U5xx HAL Driver version number 1.0.0 + * @brief STM32U5xx HAL Driver version number 1.2.0 */ #define __STM32U5xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32U5xx_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ +#define __STM32U5xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ #define __STM32U5xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32U5xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32U5xx_HAL_VERSION ((__STM32U5xx_HAL_VERSION_MAIN << 24U)\ @@ -346,7 +346,8 @@ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) /** * @brief Return tick frequency. - * @retval tick period in Hz + * @retval Tick frequency. + * Value of @ref HAL_TickFreqTypeDef. */ HAL_TickFreqTypeDef HAL_GetTickFreq(void) { @@ -439,6 +440,33 @@ uint32_t HAL_GetDEVID(void) return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID); } +/** + * @brief Return the first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return (READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Return the second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Return the third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + /** * @} */ @@ -620,6 +648,98 @@ void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void) CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); } +#if defined(SYSCFG_CFGR1_SRAMCACHED) +/** + * @brief Enable the Cacheability of internal SRAMx by DCACHE2 + * + * @retval None + */ +void HAL_SYSCFG_EnableSRAMCached(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED); +} + +/** + * @brief Disable the Cacheability of internal SRAMx by DCACHE2 + * + * @retval None + */ +void HAL_SYSCFG_DisableSRAMCached(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED); +} +#endif /* SYSCFG_CFGR1_SRAMCACHED */ + +/** + * @brief Enable the Compensation Cell of GPIO supplied by VDD + * @rmtoll CCCSR EN1 HAL_SYSCFG_EnableVddCompensationCell + * @note The vdd compensation cell can be used only when the device supply + * voltage ranges from 1.71 to 3.6 V + * @retval None + */ +void HAL_SYSCFG_EnableVddCompensationCell(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1); +} + +/** + * @brief Enable the Compensation Cell of GPIO supplied by VDDIO2 + * @rmtoll CCCSR EN2 HAL_SYSCFG_EnableVddIO2CompensationCell + * @note The Vdd I/O compensation cell can be used only when the device supply + * voltage ranges from 1.08 to 3.6 V + * @retval None + */ +void HAL_SYSCFG_EnableVddIO2CompensationCell(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2); +} + +#if defined(SYSCFG_CCCSR_EN3) +/** + * @brief Enable the Compensation Cell of HSPI IO supplied by VDD + * @rmtoll CCCSR EN3 HAL_SYSCFG_EnableVddHSPICompensationCell + * @retval None + */ +void HAL_SYSCFG_EnableVddHSPICompensationCell(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3); +} +#endif /* SYSCFG_CCCSR_EN3 */ +/** + * @brief Disable the Compensation Cell of GPIO supplied by VDD + * @rmtoll CCCSR EN1 HAL_SYSCFG_DisableVddCompensationCell + * @note The Vdd compensation cell can be used only when the device supply + * voltage ranges from 1.71 to 3.6 V + * @retval None + */ +void HAL_SYSCFG_DisableVddCompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1); +} + +/** + * @brief Disable the Compensation Cell of GPIO supplied by VDDIO2 + * @rmtoll CCCSR EN2 HAL_SYSCFG_DisableVddIO2CompensationCell + * @note The Vdd I/O compensation cell can be used only when the device supply + * voltage ranges from 1.08 to 3.6 V + * @retval None + */ +void HAL_SYSCFG_DisableVddIO2CompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2); +} + +#if defined(SYSCFG_CCCSR_EN3) +/** + * @brief Disable the Compensation Cell of HSPI IO supplied by VDD + * @rmtoll CCCSR EN3 HAL_SYSCFG_DisableVddHSPICompensationCell + * @retval None + */ +void HAL_SYSCFG_DisableVddHSPICompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3); +} +#endif /* SYSCFG_CCCSR_EN3 */ /** * @} */ @@ -779,6 +899,99 @@ HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttri #endif /* __ARM_FEATURE_CMSE */ +#ifdef SYSCFG_OTGHSPHYCR_EN +/** + * @brief Enable the OTG PHY . + * @param OTGPHYConfig Defines the OTG PHY configuration. + This parameter can be one of @ref SYSCFG_OTG_PHY_Enable + * @retval None + */ + +void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_CONFIG(OTGPHYConfig)); + + MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN, OTGPHYConfig); +} + +/** + * @brief Set the OTG PHY Power Down config. + * @param PowerDownConfig Defines the OTG PHY Power down configuration. + This parameter can be one of @ref SYSCFG_OTG_PHY_PowerDown + * @retval None + */ +void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(PowerDownConfig)); + + MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL, PowerDownConfig); +} + +/** + * @brief Set the OTG PHY reference clock selection. + * @param RefClkSelection Defines the OTG PHY reference clock selection. + This parameter can be one of the @ref SYSCFG_OTG_PHY_RefenceClockSelection + * @retval None + */ +void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClkSelection) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(RefClkSelection)); + + MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_CLKSEL, RefClkSelection); +} + +/** + * @brief Set the OTG PHY Disconnect Threshold. + * @param DisconnectThreshold Defines the voltage level for the threshold used to detect a disconnect event. + This parameter can be one of the @ref SYSCFG_OTG_PHYTUNER_DisconnectThreshold + * @retval None + */ + +void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_DISCONNECT(DisconnectThreshold)); + + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE, DisconnectThreshold); +} + +/** + * @brief Adjust the voltage level for the threshold used to detect valid high speed data. + * @param SquelchThreshold Defines the voltage level. + This parameter can be onez of the @ref SYSCFG_OTG_PHYTUNER_SquelchThreshold + + * @retval None + */ + +void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_SQUELCH(SquelchThreshold)); + + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_SQRXTUNE, SquelchThreshold); +} + +/** + * @brief Set the OTG PHY Current config. + * @param PreemphasisCurrent Defines the current configuration. + This parameter can be one of the @ref SYSCFG_OTG_PHYTUNER_PreemphasisCurrent + + * @retval None + */ + +void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_PREEMPHASIS(PreemphasisCurrent)); + + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE, PreemphasisCurrent); +} + +#endif /* SYSCFG_OTGHSPHYCR_EN */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal.h index 0c0fb8fbe18..376c4fee271 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal.h @@ -80,6 +80,8 @@ extern HAL_TickFreqTypeDef uwTickFreq; * @} */ + + /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants * @{ */ @@ -191,6 +193,85 @@ extern HAL_TickFreqTypeDef uwTickFreq; #endif /* __ARM_FEATURE_CMSE */ +#ifdef SYSCFG_OTGHSPHYCR_EN +/** @defgroup SYSCFG_OTG_PHY_RefenceClockSelection OTG PHY Reference Clock Selection + * @{ + */ + +/** @brief OTG HS PHY reference clock frequency selection + */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_1 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1) /*!< 16Mhz */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_2 SYSCFG_OTGHSPHYCR_CLKSEL_3 /*!< 19.2Mhz */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_3 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 20Mhz */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_4 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 24Mhz */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_5 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_2 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 26Mhz */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_6 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 32Mhz */ +/** + * @} + */ + +/** @defgroup SYSCFG_OTG_PHY_PowerDown OTG PHY Power Down + * @{ + */ + +/** @brief OTG HS PHY Power Down config + */ + +#define SYSCFG_OTG_HS_PHY_POWER_ON 0x00000000U /*!< PHY state machine, bias and OTG PHY PLL are powered down */ +#define SYSCFG_OTG_HS_PHY_POWER_DOWN SYSCFG_OTGHSPHYCR_PDCTRL /*!< PHY state machine, bias and OTG PHY PLL remain powered */ + +/** + * @} + */ + +/** @defgroup SYSCFG_OTG_PHY_Enable OTG PHY Enable + * @{ + */ + +#define SYSCFG_OTG_HS_PHY_UNDERRESET 0x00000000U /*!< PHY under reset */ +#define SYSCFG_OTG_HS_PHY_ENABLE SYSCFG_OTGHSPHYCR_EN /*!< PHY enabled */ + +/** @defgroup SYSCFG_OTG_PHYTUNER_PreemphasisCurrent OTG PHYTUNER Preemphasis Current + * @{ + */ + +/** @brief High-speed (HS) transmitter preemphasis current control + */ +#define SYSCFG_OTG_HS_PHY_PREEMP_DISABLED 0x00000000U /*!< HS transmitter preemphasis circuit disabled */ +#define SYSCFG_OTG_HS_PHY_PREEMP_1X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 /*!< HS transmitter preemphasis circuit sources 1x preemphasis current */ +#define SYSCFG_OTG_HS_PHY_PREEMP_2X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1 /*!< HS transmitter preemphasis circuit sources 2x preemphasis current */ +#define SYSCFG_OTG_HS_PHY_PREEMP_3X (SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 | SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1) /*!< HS transmitter preemphasis circuit sources 3x preemphasis current */ + +/** + * @} + */ + +/** @defgroup SYSCFG_OTG_PHYTUNER_SquelchThreshold OTG PHYTUNER Squelch Threshold + * @{ + */ + +/** @brief Squelch threshold adjustment + */ +#define SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT 0x00000000U /*!< +15% (recommended value) */ +#define SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT (SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_0 | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_1) /*!< 0% (default value) */ + +/** + * @} + */ + +/** @defgroup SYSCFG_OTG_PHYTUNER_DisconnectThreshold OTG PHYTUNER Disconnect Threshold + * @{ + */ + +/** @brief Disconnect threshold adjustment + */ +#define SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_1 /*!< +5.9% (recommended value) */ +#define SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_0 /*!< 0% (default value) */ + +/** + * @} + */ +#endif /* SYSCFG_OTGHSPHYCR_EN */ /** * @} */ @@ -258,16 +339,21 @@ extern HAL_TickFreqTypeDef uwTickFreq; #define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) #endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */ +#if defined(DBGMCU_APB1FZR2_DBG_I2C5_STOP) +#define __HAL_DBGMCU_FREEZE_I2C5() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C5_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C5() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C5_STOP) +#endif /* DBGMCU_APB1FZR2_DBG_I2C5_STOP */ + +#if defined(DBGMCU_APB1FZR2_DBG_I2C6_STOP) +#define __HAL_DBGMCU_FREEZE_I2C6() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C6_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C6() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C6_STOP) +#endif /* DBGMCU_APB1FZR2_DBG_I2C6_STOP */ + #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) #endif /* DBGMCU_APB1FZR2_DBG_LPTIM2_STOP */ -#if defined(DBGMCU_APB1FZR2_DBG_FDCAN_STOP) -#define __HAL_DBGMCU_FREEZE_FDCAN() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_FDCAN_STOP) -#define __HAL_DBGMCU_UNFREEZE_FDCAN() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_FDCAN_STOP) -#endif /* DBGMCU_APB1FZR2_DBG_FDCAN_STOP */ - #if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP) #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) @@ -555,6 +641,33 @@ extern HAL_TickFreqTypeDef uwTickFreq; #endif /* __ARM_FEATURE_CMSE */ + +#ifdef SYSCFG_OTGHSPHYCR_EN +#define IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_1) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_2) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_3) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_4) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_5) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_6)) + +#define IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_DOWN) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_ON)) + +#define IS_SYSCFG_OTGPHY_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_UNDERRESET) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_ENABLE)) + +#define IS_SYSCFG_OTGPHY_DISCONNECT(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT)) + +#define IS_SYSCFG_OTGPHY_SQUELCH(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT)) + +#define IS_SYSCFG_OTGPHY_PREEMPHASIS(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_DISABLED) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_1X) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_2X) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_3X)) +#endif /* SYSCFG_OTGHSPHYCR_EN */ + /** * @} */ @@ -605,6 +718,9 @@ void HAL_ResumeTick(void); uint32_t HAL_GetHalVersion(void); uint32_t HAL_GetREVID(void); uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); /** * @} @@ -636,10 +752,28 @@ void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); void HAL_SYSCFG_DisableVREFBUF(void); - +#ifdef SYSCFG_OTGHSPHYCR_EN +void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClkSelection); +void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig); +void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig); +void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold); +void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold); +void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent); +#endif /* SYSCFG_OTGHSPHYCR_EN */ void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); - +void HAL_SYSCFG_EnableSRAMCached(void); +void HAL_SYSCFG_DisableSRAMCached(void); +void HAL_SYSCFG_EnableVddCompensationCell(void); +void HAL_SYSCFG_EnableVddIO2CompensationCell(void); +#if defined(SYSCFG_CCCSR_EN3) +void HAL_SYSCFG_EnableVddHSPICompensationCell(void); +#endif /* SYSCFG_CCCSR_EN3 */ +void HAL_SYSCFG_DisableVddCompensationCell(void); +void HAL_SYSCFG_DisableVddIO2CompensationCell(void); +#if defined(SYSCFG_CCCSR_EN3) +void HAL_SYSCFG_DisableVddHSPICompensationCell(void); +#endif /* SYSCFG_CCCSR_EN3 */ /** * @} */ @@ -684,6 +818,10 @@ HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttri * @} */ +/** + * @} + */ + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_adc.c index 45c67fd196f..daa4b1445bc 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_adc.c @@ -442,6 +442,8 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) assert_param(IS_ADC4_VREF_PROT(hadc->Init.VrefProtection)); assert_param(IS_ADC4_EXTTRIG(hadc->Init.ExternalTrigConv)); assert_param(IS_ADC_TRIGGER_FREQ(hadc->Init.TriggerFrequencyMode)); + assert_param(IS_ADC4_SAMPLE_TIME(hadc->Init.SamplingTimeCommon1)); + assert_param(IS_ADC4_SAMPLE_TIME(hadc->Init.SamplingTimeCommon2)); } assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); @@ -489,6 +491,9 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */ hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */ hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */ + hadc->CalibrationCpltCallback = HAL_ADC_CalibrationCpltCallback; /* Legacy weak callback */ + hadc->VoltageRegulatorCallback = HAL_ADC_VoltageRegulatorCallback; /* Legacy weak callback */ + hadc->ADCReadyCallback = HAL_ADC_ADCReadyCallback; /* Legacy weak callback */ if (hadc->MspInitCallback == NULL) { @@ -606,9 +611,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) /* (set into HAL_ADC_ConfigChannel() ) */ /* Configuration of ADC resolution */ - MODIFY_REG(hadc->Instance->CFGR1, - ADC_CFGR1_RES, - __LL_ADC_RESOLUTION_ADC1_TO_ADC4(hadc->Init.Resolution)); /* Convert resolution for the ADC4 */ + LL_ADC_SetResolution(hadc->Instance, hadc->Init.Resolution); /* Configuration of ADC clock mode: clock source AHB or HSI with */ /* selectable prescaler. */ @@ -711,25 +714,26 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) } /* Update ADC configuration register with previous settings */ MODIFY_REG(hadc->Instance->CFGR1, - ADC_CFGR1_DISCEN | - ADC4_CFGR1_WAIT | - ADC_CFGR1_CONT | - ADC_CFGR1_OVRMOD | - ADC_CFGR1_EXTSEL | - ADC_CFGR1_EXTEN | - ADC4_CFGR1_ALIGN | - ADC4_CFGR1_SCANDIR | + ADC_CFGR1_DISCEN | + ADC4_CFGR1_CHSELRMOD | + ADC4_CFGR1_WAIT | + ADC_CFGR1_CONT | + ADC_CFGR1_OVRMOD | + ADC_CFGR1_EXTSEL | + ADC_CFGR1_EXTEN | + ADC4_CFGR1_ALIGN | + ADC4_CFGR1_SCANDIR | ADC4_CFGR1_DMACFG, tmpCFGR1); if (hadc->Init.LowPowerAutoPowerOff != ADC_LOW_POWER_NONE) { - SET_BIT(hadc->Instance->PW, hadc->Init.LowPowerAutoPowerOff); + SET_BIT(hadc->Instance->PWRR, hadc->Init.LowPowerAutoPowerOff); } if (hadc->Init.VrefProtection != ADC_VREF_PPROT_NONE) { - SET_BIT(hadc->Instance->PW, hadc->Init.VrefProtection); + SET_BIT(hadc->Instance->PWRR, hadc->Init.VrefProtection); } } @@ -751,7 +755,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) tmpCFGR1 = (ADC_CFGR_AUTODELAY((uint32_t)hadc->Init.LowPowerAutoWait) | ADC_CFGR_DMACONTREQ(hadc, (uint32_t)hadc->Init.ConversionDataManagement)); - MODIFY_REG(hadc->Instance->CFGR1, ADC4_CFGR_FIELDS_2, tmpCFGR1); + MODIFY_REG(hadc->Instance->CFGR1, ADC_CFGR1_AUTDLY | ADC_CFGR1_DMNGT, tmpCFGR1); if (hadc->Init.GainCompensation != 0UL) { LL_ADC_SetGainCompensation(hadc->Instance, hadc->Init.GainCompensation); @@ -760,7 +764,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) if (hadc->Init.OversamplingMode == ENABLE) { assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio)); - assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); + assert_param(IS_ADC12_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset)); @@ -820,20 +824,24 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) } else { - /* Configuration of ADC: */ - /* - oversampling enable */ - /* - oversampling ratio */ - /* - oversampling shift */ - /* - oversampling discontinuous mode (triggered mode) */ - /* - trigger frequency mode */ - tmpCFGR2 |= (hadc->Init.Oversampling.Ratio | - hadc->Init.Oversampling.RightBitShift | - hadc->Init.Oversampling.TriggeredMode | - hadc->Init.TriggerFrequencyMode - ); - if (hadc->Init.OversamplingMode == ENABLE) { + assert_param(IS_ADC4_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio)); + assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); + assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); + + /* Configuration of ADC: */ + /* - oversampling enable */ + /* - oversampling ratio */ + /* - oversampling shift */ + /* - oversampling discontinuous mode (triggered mode) */ + /* - trigger frequency mode */ + tmpCFGR2 |= (hadc->Init.Oversampling.Ratio | + hadc->Init.Oversampling.RightBitShift | + hadc->Init.Oversampling.TriggeredMode | + hadc->Init.TriggerFrequencyMode + ); + SET_BIT(tmpCFGR2, ADC_CFGR2_ROVSE); } MODIFY_REG(hadc->Instance->CFGR2, @@ -866,45 +874,24 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) } else if (hadc->Init.ScanConvMode == ADC4_SCAN_ENABLE) { - /* Count number of ranks available in HAL ADC handle variable */ - uint32_t ADCGroupRegularSequencerRanksCount; - - /* Parse all ranks from 1 to 8 */ - for (ADCGroupRegularSequencerRanksCount = 0UL; ADCGroupRegularSequencerRanksCount < (8UL); \ - ADCGroupRegularSequencerRanksCount++) - { - /* Check each sequencer rank until value of end of sequence */ - if (((hadc->ADCGroupRegularSequencerRanks >> (ADCGroupRegularSequencerRanksCount * 4UL)) & ADC_CHSELR_SQ1) == - ADC_CHSELR_SQ1) - { - break; - } - } - - if (ADCGroupRegularSequencerRanksCount == 1UL) - { - /* Set ADC group regular sequencer: */ - /* Set sequencer scan length by clearing ranks above rank 1 */ - /* and do not modify rank 1 value. */ - SET_BIT(hadc->Instance->CHSELR, ADC_CHSELR_SQ2_TO_SQ8); - } - else - { - /* Set ADC group regular sequencer: */ - /* - Set ADC group regular sequencer to value memorized */ - /* in HAL ADC handle */ - /* Note: This value maybe be initialized at a unknown value, */ - /* therefore after the first call of "HAL_ADC_Init()", */ - /* each rank corresponding to parameter "NbrOfConversion" */ - /* must be set using "HAL_ADC_ConfigChannel()". */ - /* - Set sequencer scan length by clearing ranks above maximum rank */ - /* and do not modify other ranks value. */ - MODIFY_REG(hadc->Instance->CHSELR, - ADC_CHSELR_SQ_ALL, - (ADC_CHSELR_SQ2_TO_SQ8 << (((hadc->Init.NbrOfConversion - 1UL) * ADC4_REGULAR_RANK_2) & 0x1FUL)) \ - | (hadc->ADCGroupRegularSequencerRanks) - ); - } + /* Set ADC group regular sequencer: */ + /* - Set ADC group regular sequencer to value memorized */ + /* in HAL ADC handle */ + /* Note: This value maybe be initialized at a unknown value, */ + /* therefore after the first call of "HAL_ADC_Init()", */ + /* each rank corresponding to parameter "NbrOfConversion" */ + /* must be set using "HAL_ADC_ConfigChannel()". */ + /* - Set sequencer scan length by clearing ranks above maximum rank */ + /* and do not modify other ranks value. */ + MODIFY_REG(hadc->Instance->CHSELR, + ADC_CHSELR_SQ_ALL, + (ADC_CHSELR_SQ2_TO_SQ8 << (((hadc->Init.NbrOfConversion - 1UL) * ADC4_REGULAR_RANK_2) & 0x1FUL)) \ + | (hadc->ADCGroupRegularSequencerRanks) + ); + } + else + { + /* Nothing to do */ } /* Check back that ADC registers have effectively been configured to */ @@ -1005,15 +992,15 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) /* Reset register IER */ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */ { - __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 | - ADC_IT_JQOVF | ADC_IT_OVR | + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | + ADC_IT_AWD1 | ADC_IT_OVR | ADC_IT_JEOS | ADC_IT_JEOC | ADC_IT_EOS | ADC_IT_EOC | ADC_IT_EOSMP | ADC_IT_RDY)); /* Reset register ISR */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 | - ADC_FLAG_JQOVF | ADC_FLAG_OVR | + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | + ADC_FLAG_AWD1 | ADC_FLAG_OVR | ADC_FLAG_JEOS | ADC_FLAG_JEOC | ADC_FLAG_EOS | ADC_FLAG_EOC | ADC_FLAG_EOSMP | ADC_FLAG_RDY)); @@ -1079,13 +1066,17 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) /* bits in access mode read only, no direct reset applicable*/ /* Reset register OFR1 */ - CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSAT | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1); + CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSETPOS | ADC_OFR1_USAT | ADC_OFR1_SSAT | ADC_OFR1_OFFSET1_CH | + ADC_OFR1_OFFSET1); /* Reset register OFR2 */ - CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSAT | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2); + CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSETPOS | ADC_OFR2_USAT | ADC_OFR2_SSAT | ADC_OFR2_OFFSET2_CH | + ADC_OFR2_OFFSET2); /* Reset register OFR3 */ - CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSAT | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3); + CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSETPOS | ADC_OFR3_USAT | ADC_OFR3_SSAT | ADC_OFR3_OFFSET3_CH | + ADC_OFR3_OFFSET3); /* Reset register OFR4 */ - CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSAT | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4); + CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSETPOS | ADC_OFR4_USAT | ADC_OFR4_SSAT | ADC_OFR4_OFFSET4_CH | + ADC_OFR4_OFFSET4); /* Reset register GCOMP */ CLEAR_BIT(hadc->Instance->GCOMP, ADC_GCOMP_GCOMP | ADC_GCOMP_GCOMPCOEFF); @@ -1127,7 +1118,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) /* Reset register CFGR1 */ hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN | - ADC4_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD | + ADC4_CFGR1_CHSELRMOD | ADC4_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC4_CFGR1_ALIGN | ADC_CFGR1_RES | ADC4_CFGR1_SCANDIR | ADC4_CFGR1_DMACFG | ADC4_CFGR1_DMAEN); @@ -1262,6 +1253,9 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID + * @arg @ref HAL_ADC_END_OF_CALIBRATION_CB_ID ADC end of calibration callback ID + * @arg @ref HAL_ADC_VOLTAGE_REGULATOR_CB_ID ADC voltage regulator (LDO) Ready callback ID + * @arg @ref HAL_ADC_ADC_READY_CB_ID ADC Ready callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID @@ -1325,6 +1319,48 @@ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Call hadc->MspInitCallback = pCallback; break; + case HAL_ADC_END_OF_CALIBRATION_CB_ID : + { + if (hadc->Instance == ADC4) + { + hadc->CalibrationCpltCallback = pCallback; + } + else + { + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + } + break; + } + + case HAL_ADC_VOLTAGE_REGULATOR_CB_ID : + { + if (hadc->Instance == ADC4) + { + hadc->VoltageRegulatorCallback = pCallback; + } + else + { + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + } + break; + } + + case HAL_ADC_ADC_READY_CB_ID : + { + if (hadc->Instance == ADC4) + { + hadc->ADCReadyCallback = pCallback; + } + else + { + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + } + break; + } + case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = pCallback; break; @@ -1379,6 +1415,9 @@ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Call * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID + * @arg @ref HAL_ADC_END_OF_CALIBRATION_CB_ID ADC end of calibration callback ID + * @arg @ref HAL_ADC_VOLTAGE_REGULATOR_CB_ID ADC voltage regulator (LDO) Ready callback ID + * @arg @ref HAL_ADC_ADC_READY_CB_ID ADC Ready callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID @@ -1429,6 +1468,18 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; break; + case HAL_ADC_END_OF_CALIBRATION_CB_ID : + hadc->CalibrationCpltCallback = HAL_ADC_CalibrationCpltCallback; + break; + + case HAL_ADC_VOLTAGE_REGULATOR_CB_ID : + hadc->VoltageRegulatorCallback = HAL_ADC_VoltageRegulatorCallback; + break; + + case HAL_ADC_ADC_READY_CB_ID : + hadc->ADCReadyCallback = HAL_ADC_ADCReadyCallback; + break; + case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ break; @@ -1510,6 +1561,10 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; +#if defined(ADC_MULTIMODE_SUPPORT) + const ADC_TypeDef *tmp_adc_master; + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif /* ADC_MULTIMODE_SUPPORT */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1534,6 +1589,17 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) if (hadc->Instance != ADC4) /* ADC1 or ADC2 */ { +#if defined(ADC_MULTIMODE_SUPPORT) + /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit + - by default if ADC is Master or Independent or if multimode feature is not available + - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + ) + { + CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + } +#endif /* ADC_MULTIMODE_SUPPORT */ /* Set ADC error code */ /* Check if a conversion is on going on ADC group injected */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) @@ -1573,10 +1639,42 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) if (hadc->Instance != ADC4) /* ADC1 or ADC2 */ { +#if defined(ADC_MULTIMODE_SUPPORT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) + { + /* Multimode feature is not available or ADC Instance is Independent or Master, + or is not Slave ADC with dual regular conversions enabled. + Then, set HAL_ADC_STATE_INJ_BUSY bit and reset HAL_ADC_STATE_INJ_EOC bit if JAUTO is set. */ + if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO) != 0UL) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); + } + else + { + SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + /* if Master ADC JAUTO bit is set, update Slave State in setting + HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */ + tmp_adc_master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); + if (READ_BIT(tmp_adc_master->CFGR1, ADC_CFGR1_JAUTO) != 0UL) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + + } +#else if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO) != 0UL) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } +#endif /* ADC_MULTIMODE_SUPPORT */ } /* Start ADC group regular conversion */ @@ -1660,6 +1758,10 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti uint32_t tickstart; uint32_t tmp_flag_end; uint32_t tmp_cfgr; +#if defined(ADC_MULTIMODE_SUPPORT) + const ADC_TypeDef *tmp_adc_master; + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif /* ADC_MULTIMODE_SUPPORT */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1681,6 +1783,37 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti if (hadc->Instance != ADC4) /* ADC1 or ADC2 */ { +#if defined(ADC_MULTIMODE_SUPPORT) + if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) + { + /* Check ADC DMA mode */ + if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT_0) != 0UL) + { + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + return HAL_ERROR; + } + else + { + tmp_flag_end = (ADC_FLAG_EOC); + } + } + else + { + /* Check ADC DMA mode in multimode */ + if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC) + { + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + return HAL_ERROR; + } + else + { + tmp_flag_end = (ADC_FLAG_EOC); + } + } +#else /* Check ADC DMA mode */ if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT_0) != 0UL) { @@ -1691,6 +1824,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti { tmp_flag_end = (ADC_FLAG_EOC); } +#endif /* ADC_MULTIMODE_SUPPORT */ } else { @@ -1755,9 +1889,29 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti } } +#if defined(ADC_MULTIMODE_SUPPORT) + /* Get relevant register CFGR in ADC instance of ADC master or slave */ + /* in function of multimode state (for devices with multimode */ + /* available). */ + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) + { + /* Retrieve handle ADC CFGR register */ + tmp_cfgr = READ_REG(hadc->Instance->CFGR1); + } + else + { + /* Retrieve Master ADC CFGR register */ + tmp_adc_master = ADC_MASTER_REGISTER(hadc); + tmp_cfgr = READ_REG(tmp_adc_master->CFGR1); + } +#else /* Retrieve handle ADC CFGR register */ tmp_cfgr = READ_REG(hadc->Instance->CFGR1); - +#endif /* ADC_MULTIMODE_SUPPORT */ /* Clear polled flag */ if (tmp_flag_end == ADC_FLAG_EOS) { @@ -1832,7 +1986,6 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, * not present on all STM32 families) * @arg @ref ADC_OVR_EVENT ADC Overrun event - * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event * @param Timeout Timeout value in millisecond. * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. * Indeed, the latter is reset only if hadc->Init.Overrun field is set @@ -1927,19 +2080,6 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventTy break; - /* Injected context queue overflow event */ - case ADC_JQOVF_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); - - /* Set ADC error code to Injected context queue overflow */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); - - /* Clear ADC Injected context queue overflow flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); - - break; - /* Overrun event */ default: /* Case ADC_OVR_EVENT */ /* If overrun is set to overwrite previous data, overrun event is not */ @@ -1993,6 +2133,10 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventTy HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; +#if defined(ADC_MULTIMODE_SUPPORT) + const ADC_TypeDef *tmp_adc_master; + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif /* ADC_MULTIMODE_SUPPORT */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -2014,6 +2158,17 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); +#if defined(ADC_MULTIMODE_SUPPORT) + /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit + - by default if ADC is Master or Independent or if multimode feature is not available + - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + ) + { + CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + } +#endif /* ADC_MULTIMODE_SUPPORT */ /* Set ADC error code */ /* Check if a conversion is on going on ADC group injected */ @@ -2069,6 +2224,70 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) /* enabled only (conversion is not started), */ /* - if ADC is master, ADC is enabled and conversion is started. */ /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */ +#if defined(ADC_MULTIMODE_SUPPORT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) + { + /* Multimode feature is not available or ADC Instance is Independent or Master, + or is not Slave ADC with dual regular conversions enabled. + Then set HAL_ADC_STATE_INJ_BUSY and reset HAL_ADC_STATE_INJ_EOC if JAUTO is set. */ + if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO) != 0UL) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + + /* Enable as well injected interruptions in case + HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This + allows to start regular and injected conversions when JAUTO is + set with a single call to HAL_ADC_Start_IT() */ + switch (hadc->Init.EOCSelection) + { + case ADC_EOC_SEQ_CONV: + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); + break; + /* case ADC_EOC_SINGLE_CONV */ + default: + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); + break; + } + } + + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); + } + else + { + /* hadc is the handle of a Slave ADC with dual regular conversions + enabled. Therefore, ADC_CR_ADSTART is NOT set */ + SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + /* if Master ADC JAUTO bit is set, Slave injected interruptions + are enabled nevertheless (for same reason as above) */ + tmp_adc_master = ADC_MASTER_REGISTER(hadc); + if (READ_BIT(tmp_adc_master->CFGR1, ADC_CFGR1_JAUTO) != 0UL) + { + /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit + and in resetting HAL_ADC_STATE_INJ_EOC bit */ + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + /* Next, set Slave injected interruptions */ + switch (hadc->Init.EOCSelection) + { + case ADC_EOC_SEQ_CONV: + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); + break; + /* case ADC_EOC_SINGLE_CONV */ + default: + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); + break; + } + } + } +#else if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO) != 0UL) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); @@ -2094,6 +2313,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); +#endif /* ADC_MULTIMODE_SUPPORT */ } else { @@ -2170,6 +2390,10 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pDa { HAL_StatusTypeDef tmp_hal_status; uint32_t LengthInBytes; + DMA_NodeConfTypeDef node_conf; +#if defined(ADC_MULTIMODE_SUPPORT) + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif /* ADC_MULTIMODE_SUPPORT */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -2179,107 +2403,174 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pDa { __HAL_LOCK(hadc); - tmp_hal_status = ADC_Enable(hadc); - - /* Start conversion if ADC is effectively enabled */ - if (tmp_hal_status == HAL_OK) +#if defined(ADC_MULTIMODE_SUPPORT) + /* Ensure that multimode regular conversions are not enabled. */ + /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */ + if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) +#endif /* ADC_MULTIMODE_SUPPORT */ { - /* Set ADC state */ - /* - Clear state bitfield related to regular group conversion results */ - /* - Set state bitfield related to regular operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, - HAL_ADC_STATE_REG_BUSY); + tmp_hal_status = ADC_Enable(hadc); - if (hadc->Instance != ADC4) /* ADC1 or ADC2 */ + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) { - /* Check if a conversion is on going on ADC group injected */ - if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); + + if (hadc->Instance != ADC4) /* ADC1 or ADC2 */ { - /* Reset ADC error code fields related to regular conversions only */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); +#if defined(ADC_MULTIMODE_SUPPORT) + /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit + - if ADC instance is master or if multimode feature is not available + - if multimode setting is disabled (ADC instance slave in independent mode) */ + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + ) + { + CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + } +#endif /* ADC_MULTIMODE_SUPPORT */ + /* Check if a conversion is on going on ADC group injected */ + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) + { + /* Reset ADC error code fields related to regular conversions only */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset all ADC error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } } else { /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); } - } - else - { - /* Reset all ADC error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - } - /* Set the DMA transfer complete callback */ - hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; + /* Set the DMA transfer complete callback */ + hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; - /* Set the DMA half transfer complete callback */ - hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; + /* Set the DMA half transfer complete callback */ + hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; - /* Set the DMA error callback */ - hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; + /* Set the DMA error callback */ + hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; - /* Manage ADC and DMA start: ADC overrun interruption, DMA start, */ - /* ADC start (in case of SW start): */ + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, */ + /* ADC start (in case of SW start): */ - /* Clear regular group conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC */ - /* operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC */ + /* operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - /* With DMA, overrun event is always considered as an error even if - hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, - ADC_IT_OVR is enabled. */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); - if (hadc->Instance == ADC4) - { - /* Enable ADC DMA mode */ - hadc->Instance->CFGR1 |= ADC4_CFGR1_DMAEN; - } + /* With DMA, overrun event is always considered as an error even if + hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, + ADC_IT_OVR is enabled. */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - /* Length should be converted to number of bytes */ - LengthInBytes = Length * 4U; + if (hadc->Instance == ADC4) + { + /* Enable ADC DMA mode */ + hadc->Instance->CFGR1 |= ADC4_CFGR1_DMAEN; + } - /* Start the DMA channel */ - if ((hadc->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL)) + /* Start the DMA channel */ + /* Check linkedlist mode */ + if ((hadc->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) { - hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t)LengthInBytes; - hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \ - (uint32_t)&hadc->Instance->DR; - hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; - tmp_hal_status = HAL_DMAEx_List_Start_IT(hadc->DMA_Handle); + if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL)) + { + /* Length should be converted to number of bytes */ + if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hadc->DMA_Handle->LinkedListQueue->Head) != HAL_OK) + { + return HAL_ERROR; + } + + /* Length should be converted to number of bytes */ + if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + /* Word -> Bytes */ + LengthInBytes = Length * 4U; + } + else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD) + { + /* Halfword -> Bytes */ + LengthInBytes = Length * 2U; + } + else /* Bytes */ + { + /* Same size already expressed in Bytes */ + LengthInBytes = Length; + } + + hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t)LengthInBytes; + hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \ + (uint32_t)&hadc->Instance->DR; + hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + tmp_hal_status = HAL_DMAEx_List_Start_IT(hadc->DMA_Handle); + } + else + { + tmp_hal_status = HAL_ERROR; + } } else { - tmp_hal_status = HAL_ERROR; + /* Length should be converted to number of bytes */ + if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + /* Word -> Bytes */ + LengthInBytes = Length * 4U; + } + else if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD) + { + /* Halfword -> Bytes */ + LengthInBytes = Length * 2U; + } + else /* Bytes */ + { + /* Same size already expressed in Bytes */ + LengthInBytes = Length; + } + + tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, \ + LengthInBytes); } + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); } else { - tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, \ - LengthInBytes); + __HAL_UNLOCK(hadc); } - - /* Enable conversion of regular group. */ - /* If software start has been selected, conversion starts immediately. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - /* Start ADC group regular conversion */ - LL_ADC_REG_StartConversion(hadc->Instance); } +#if defined(ADC_MULTIMODE_SUPPORT) else { + tmp_hal_status = HAL_ERROR; + /* Process unlocked */ __HAL_UNLOCK(hadc); } +#endif /* ADC_MULTIMODE_SUPPORT */ } else { @@ -2317,14 +2608,11 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { - if (hadc->Instance != ADC4) /* ADC1 or ADC2 */ + /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */ + /* Note: For ADC1 and ADC2, DMA configuration kept for potential next ADC start DMA action. */ + if (hadc->Instance == ADC4) { - /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */ - MODIFY_REG(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT_0 | ADC_CFGR1_DMNGT_1, 0UL); - } - else - { - /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */ + CLEAR_BIT(hadc->Instance->CFGR1, ADC4_CFGR1_DMAEN); } @@ -2397,7 +2685,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) * @param hadc ADC handle * @retval ADC group regular conversion data */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -2422,6 +2710,10 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) uint32_t tmp_adc_inj_is_trigger_source_sw_start; uint32_t tmp_adc_reg_is_trigger_source_sw_start; uint32_t tmp_cfgr; +#if defined(ADC_MULTIMODE_SUPPORT) + const ADC_TypeDef *tmp_adc_master; + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif /* ADC_MULTIMODE_SUPPORT */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -2469,7 +2761,25 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ +#if defined(ADC_MULTIMODE_SUPPORT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) + { + /* check CONT bit directly in handle ADC CFGR register */ + tmp_cfgr = READ_REG(hadc->Instance->CFGR1); + } + else + { + /* else need to check Master ADC CONT bit */ + tmp_adc_master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); + tmp_cfgr = READ_REG(tmp_adc_master->CFGR1); + } +#else tmp_cfgr = READ_REG(hadc->Instance->CFGR1); +#endif /* ADC_MULTIMODE_SUPPORT */ /* Carry on if continuous mode is disabled */ if (READ_BIT(tmp_cfgr, ADC_CFGR1_CONT) != ADC_CFGR1_CONT) @@ -2583,7 +2893,23 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) /* in function of multimode state (for devices with multimode */ /* available). */ +#if defined(ADC_MULTIMODE_SUPPORT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) + ) + { + tmp_cfgr = READ_REG(hadc->Instance->CFGR1); + } + else + { + tmp_adc_master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); + tmp_cfgr = READ_REG(tmp_adc_master->CFGR1); + } +#else tmp_cfgr = READ_REG(hadc->Instance->CFGR1); +#endif /* ADC_MULTIMODE_SUPPORT */ /* Disable interruption if no further conversion upcoming by injected */ /* external trigger or by automatic injected conversion with regular */ @@ -2641,7 +2967,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS); } - } /* Specific ADC1 only */ + } /* Specific ADC1 or ADC2 only */ /* ========== Check Analog watchdog 1 flag ========== */ if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) @@ -2712,11 +3038,32 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) /* Check DMA configuration */ if (hadc->Instance != ADC4) /* ADC1 or ADC2 */ { +#if defined(ADC_MULTIMODE_SUPPORT) + /* Check DMA configuration */ + if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT) + { + /* Multimode (when feature is available) is enabled, + Common Control Register MDMA bits must be checked. */ + if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC) + { + overrun_error = 1UL; + } + } + else + { + /* Multimode not set or feature not available or ADC independent */ + if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMNGT) != 0UL) + { + overrun_error = 1UL; + } + } +#else /* Multimode not set or feature not available or ADC independent */ if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMNGT) != 0UL) { overrun_error = 1UL; } +#endif /* ADC_MULTIMODE_SUPPORT */ } else { @@ -2752,29 +3099,57 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); } - if (hadc->Instance != ADC4) /* ADC1 or ADC2 */ + /* ========== Check ADC Ready flag ========== */ + if (((tmp_isr & ADC_FLAG_RDY) == ADC_FLAG_RDY) && ((tmp_ier & ADC_IT_RDY) == ADC_IT_RDY)) { - /* ========== Check Injected context queue overflow flag ========== */ - if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) + /* Update state machine on end of sampling status if not in error state */ + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) { - /* Change ADC state to overrun state */ - SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } - /* Set ADC error code to Injected context queue overflow */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); + /* ADC Ready callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ADCReadyCallback(hadc); +#else + HAL_ADC_ADCReadyCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - /* Clear the Injected context queue overflow flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); + /* Leave ADRDY flag up (used by HAL), disable interrupt source instead */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_RDY); + } - /* Injected context queue overflow callback */ + if (hadc->Instance == ADC4) /* ADC4 */ + { + /* ========== Check End of Calibration flag ========== */ + if (((tmp_isr & ADC_FLAG_EOCAL) == ADC_FLAG_EOCAL) && ((tmp_ier & ADC_IT_EOCAL) == ADC_IT_EOCAL)) + { + /* End Of Calibration callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->InjectedQueueOverflowCallback(hadc); + hadc->CalibrationCpltCallback(hadc); #else - HAL_ADCEx_InjectedQueueOverflowCallback(hadc); + HAL_ADC_CalibrationCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear end of calibration flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOCAL); } - } /* Speceific ADC1 only */ + /* ========== Check LDO ready flag ========== */ + if (((tmp_isr & ADC_FLAG_LDORDY) == ADC_FLAG_LDORDY) && ((tmp_ier & ADC_IT_LDORDY) == ADC_IT_LDORDY)) + { + /* Voltage Regulator (LDO) Ready callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->VoltageRegulatorCallback(hadc); +#else + HAL_ADC_VoltageRegulatorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Disable Voltage Regulator (LDO) Ready interrupt source */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_LDORDY); + } + } } /** @@ -2844,6 +3219,51 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) */ } +/** + * @brief Calibration complete callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_CalibrationCpltCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_CalibrationCpltCallback must be implemented in the user file. + */ +} + +/** + * @brief Voltage Regulator (LDO) Ready callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_VoltageRegulatorCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_VoltageRegulatorCallback must be implemented in the user file. + */ +} + +/** + * @brief ADC Ready callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_ADCReadyCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ADCReadyCallback must be implemented in the user file. + */ +} + /** * @} */ @@ -2911,12 +3331,16 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf } else { +#if defined(ADC2) + assert_param(IS_ADC12_DIFF_CHANNEL(pConfig->Channel)); +#else assert_param(IS_ADC1_DIFF_CHANNEL(pConfig->Channel)); +#endif /* ADC2 */ } } else { - assert_param(IS_ADC4_SAMPLE_TIME(pConfig->SamplingTime)); + assert_param(IS_ADC4_SAMPLE_TIME_COMMON(pConfig->SamplingTime)); if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) || (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD)) @@ -2973,35 +3397,57 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Set ADC selected offset number */ LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel, tmp_offset_shifted); assert_param(IS_ADC_OFFSET_SIGN(pConfig->OffsetSign)); + assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSaturation)); assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSignedSaturation)); /* Set ADC selected offset sign */ LL_ADC_SetOffsetSign(hadc->Instance, pConfig->OffsetNumber, pConfig->OffsetSign); - /* Set ADC selected offset signed saturation */ - LL_ADC_SetOffsetSignedSaturation(hadc->Instance, pConfig->OffsetNumber, \ - (pConfig->OffsetSignedSaturation == ENABLE) \ - ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE \ - : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); + + /* Configure offset saturation */ + if (pConfig->OffsetSaturation == ENABLE) + { + /* Set ADC selected offset unsigned/signed saturation */ + LL_ADC_SetOffsetUnsignedSaturation(hadc->Instance, pConfig->OffsetNumber, + (pConfig->OffsetSignedSaturation == DISABLE) + ? LL_ADC_OFFSET_UNSIGNED_SATURATION_ENABLE \ + : LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE); + + LL_ADC_SetOffsetSignedSaturation(hadc->Instance, pConfig->OffsetNumber, + (pConfig->OffsetSignedSaturation == ENABLE) + ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE \ + : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); + } + else + { + /* Disable ADC offset signed saturation */ + LL_ADC_SetOffsetUnsignedSaturation(hadc->Instance, pConfig->OffsetNumber, + LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE); + LL_ADC_SetOffsetSignedSaturation(hadc->Instance, pConfig->OffsetNumber, + LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); + } } else { /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled. - If this is the case, offset OFRx is disabled since - pConfig->OffsetNumber = ADC_OFFSET_NONE. */ - if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(pConfig->Channel)) + If this is the case, the corresponding offset is disabled since pConfig->OffsetNumber = ADC_OFFSET_NONE. */ + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) { - CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSAT); + LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_1, pConfig->Channel, 0x0); } - if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(pConfig->Channel)) + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) { - CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSAT); + LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_2, pConfig->Channel, 0x0); } - if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(pConfig->Channel)) + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) { - CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSAT); + LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_3, pConfig->Channel, 0x0); } - if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(pConfig->Channel)) + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) { - CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSAT); + LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, pConfig->Channel, 0x0); } } } @@ -3101,9 +3547,11 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf } else { - /* Remap Internal Channels for Cut1 vs Cut2 */ tmp_channel = pConfig->Channel; - if (HAL_GetREVID() == REV_ID_A) /* STM32U5 silicon Rev.A */ + + /* Remap internal channels on STM32U5-2M revA */ +#if defined (STM32U575xx) || defined (STM32U585xx) + if (HAL_GetREVID() == REV_ID_A) { if (pConfig->Channel == ADC4_CHANNEL_TEMPSENSOR) { @@ -3130,6 +3578,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf tmp_channel = pConfig->Channel; } } +#endif /* STM32U575xx || STM32U585xx */ /* Configure channel: depending on rank setting, add it or remove it from */ /* ADC sequencer. */ @@ -3169,6 +3618,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* To apply it, parameter'NbrOfConversion' must be increased. */ if (((pConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion) { +#if !defined (ADC2) if (HAL_GetREVID() <= REV_ID_A) /* STM32U5 silicon Rev.A */ { if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(tmp_channel) >= 20UL) @@ -3176,6 +3626,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf tmp_channel = (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(tmp_channel) - 9UL)); } } +#endif /* ADC2 */ LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, tmp_channel); } } @@ -3228,6 +3679,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf else if ((pConfig->Channel == ADC_CHANNEL_VCORE) \ && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) { +#if !defined (ADC2) if (ADC_VCORE_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), @@ -3237,13 +3689,15 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf SET_BIT((hadc->Instance->OR), ADC_OR_CHN0SEL); } } +#endif /* ADC2 */ } else { /* nothing to do */ } - /* If STM32U5 silicon Rev.B, ADC_CHANNEL_DAC1CH1 and ADC_CHANNEL_DAC1CH2 are both on Channel 21 + /* If STM32U5 silicon Rev.B (or 4M), ADC_CHANNEL_DAC1CH1 and ADC_CHANNEL_DAC1CH2 are both on Channel 21 and selection is done via ADC_OR[0] register */ +#if !defined (ADC2) if (HAL_GetREVID() == REV_ID_B) /* STM32U5 silicon Rev.B */ { if ((pConfig->Channel == ADC_CHANNEL_DAC1CH2_ADC4) \ @@ -3252,6 +3706,13 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf SET_BIT((hadc->Instance->OR), ADC_OR_CHN0SEL); } } +#else + if ((pConfig->Channel == ADC_CHANNEL_DAC1CH2_ADC4) \ + && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) + { + SET_BIT((hadc->Instance->OR), ADC_OR_CHN0SEL); + } +#endif /* ADC2 */ } } else @@ -3293,19 +3754,22 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf } else if (pConfig->Channel == ADC_CHANNEL_VCORE) { +#if !defined (ADC2) LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), ~LL_ADC_PATH_INTERNAL_VREFINT & tmp_config_internal_channel); if (HAL_GetREVID() <= REV_ID_A) /* STM32U5 silicon Rev.A */ { SET_BIT((hadc->Instance->OR), ADC_OR_CHN0SEL); } +#endif /* ADC2 */ } else { /* nothing to do */ } - /* If STM32U5 silicon Rev.B, ADC_CHANNEL_DAC1CH1 and ADC_CHANNEL_DAC1CH2 are both on Channel 21 + /* If STM32U5 2M silicon Rev.B (or 4M), ADC_CHANNEL_DAC1CH1 and ADC_CHANNEL_DAC1CH2 are both on Channel 21 and selection is done via ADC_OR[0] register */ +#if !defined (ADC2) if (HAL_GetREVID() == REV_ID_B) /* STM32U5 silicon Rev.B */ { if ((pConfig->Channel == ADC_CHANNEL_DAC1CH2_ADC4) \ @@ -3314,6 +3778,13 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf SET_BIT((hadc->Instance->OR), ADC_OR_CHN0SEL); } } +#else + if ((pConfig->Channel == ADC_CHANNEL_DAC1CH2_ADC4) \ + && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) + { + SET_BIT((hadc->Instance->OR), ADC_OR_CHN0SEL); + } +#endif /* ADC2 */ } } } @@ -3641,7 +4112,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG * @param hadc ADC handle * @retval ADC handle state (bitfield on 32 bits) */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -3655,7 +4126,7 @@ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) * @param hadc ADC handle * @retval ADC error code (bitfield on 32 bits) */ -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -3836,43 +4307,53 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) return HAL_ERROR; } + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_RDY); + LL_ADC_Enable(hadc->Instance); /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ /* performed automatically by hardware and flag ADC ready is not set. */ - if (hadc->Init.LowPowerAutoPowerOff == ADC_LOW_POWER_NONE) + if ((hadc->Init.LowPowerAutoPowerOff == ADC_LOW_POWER_NONE) || (hadc->Instance != ADC4)) { /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); /* Poll for ADC ready flag raised except case of multimode enabled and ADC slave selected. */ - while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) +#if defined(ADC_MULTIMODE_SUPPORT) + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + ) +#endif /* ADC_MULTIMODE_SUPPORT */ { - /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit - has been cleared (after a calibration), ADEN bit is reset by the - calibration logic. - The workaround is to continue setting ADEN until ADRDY is becomes 1. - Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this - 4 ADC clock cycle duration */ - /* Note: Test of ADC enabled required due to hardware constraint to */ - /* not enable ADC if already enabled. */ - if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) { - LL_ADC_Enable(hadc->Instance); - } + /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit + has been cleared (after a calibration), ADEN bit is reset by the + calibration logic. + The workaround is to continue setting ADEN until ADRDY is becomes 1. + Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this + 4 ADC clock cycle duration */ + /* Note: Test of ADC enabled required due to hardware constraint to */ + /* not enable ADC if already enabled. */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + LL_ADC_Enable(hadc->Instance); + } - if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) - { - /* New check to avoid false timeout detection in case of preemption */ - if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) + if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - return HAL_ERROR; + return HAL_ERROR; + } } } } diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_adc.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_adc.h index ca3e6f2e9c0..60cc15ca4aa 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_adc.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_adc.h @@ -49,7 +49,10 @@ extern "C" { typedef struct { uint32_t Ratio; /*!< Configures the oversampling ratio. - This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ + In case of ADC1 or ADC2 (if available), this parameter can be in the + range from 0 to 1023 + In case of ADC4, this parameter can be a value of + @ref ADC_HAL_EC_OVS_RATIO */ uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ @@ -393,9 +396,11 @@ typedef struct Conversion time is the addition of sampling time and processing time (14.5 ADC clock cycles at ADC resolution 14 bits, 12.5 cycles at 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). - This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME + For ADC1 and 2 (if available): This parameter can be a value of + @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. Caution: This parameter applies to a channel that can be used into regular and/or injected group. It overwrites the last setting. + For ADC4: This parameter can be a value of @ref ADC_HAL_EC_SAMPLINGTIME_COMMON. Note: On this STM32 family, two different sampling time settings are available (refer to parameters "SamplingTimeCommon1" and "SamplingTimeCommon2"), each channel can use one of these two settings. @@ -439,12 +444,16 @@ typedef struct continuous mode or external trigger that could launch a conversion). */ FunctionalState OffsetRightShift; /*!< Define the Right-shift data after Offset correction. - This parameter is applied only for 16-bit or 8-bit resolution. + This parameter is applied only for 14-bit or 8-bit resolution. This parameter can be set to ENABLE or DISABLE.*/ FunctionalState OffsetSignedSaturation; /*!< Specify whether the Signed saturation feature is used or not. - This parameter is applied only for 16-bit or 8-bit resolution. - This parameter can be set to ENABLE or DISABLE. */ + This parameter is only applied when OffsetSaturation is ENABLE. + This parameter is applied only for 14-bit or 8-bit resolution. + This parameter can be set to ENABLE or DISABLE. + Note: + - If OffsetSignedSaturation is set to DISABLE the unsigned + saturation feature is used */ FunctionalState OffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. This parameter value can be ENABLE or DISABLE. @@ -594,7 +603,6 @@ typedef struct low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ #define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */ -#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */ /* States of ADC analog watchdogs */ #define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ @@ -638,6 +646,9 @@ typedef struct void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ + void (* CalibrationCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of calibration callback */ + void (* VoltageRegulatorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC voltage regulator (LDO) Ready callback */ + void (* ADCReadyCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Ready callback */ void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ @@ -658,8 +669,11 @@ typedef enum HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ - HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ - HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ + HAL_ADC_END_OF_CALIBRATION_CB_ID = 0x09U, /*!< ADC end of calibration callback ID */ + HAL_ADC_VOLTAGE_REGULATOR_CB_ID = 0x0AU, /*!< ADC voltage regulator (LDO) Ready callback ID */ + HAL_ADC_ADC_READY_CB_ID = 0x0BU, /*!< ADC Ready callback ID */ + HAL_ADC_MSPINIT_CB_ID = 0x0CU, /*!< ADC Msp Init callback ID */ + HAL_ADC_MSPDEINIT_CB_ID = 0x0DU /*!< ADC Msp DeInit callback ID */ } HAL_ADC_CallbackIDTypeDef; /** @@ -688,7 +702,6 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to enable/disable, erroneous state, ...) */ #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ -#define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ @@ -718,17 +731,17 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution * @{ */ - -#define ADC_RESOLUTION_14B (LL_ADC_RESOLUTION_14B) /*!< ADC resolution 14 bits */ +#define ADC_RESOLUTION_14B (LL_ADC_RESOLUTION_14B) /*!< ADC resolution 14 bits (ADC1, ADC2 only) */ #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ -#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ -#define ADC_RESOLUTION_6B (0xFFFFFFFFUL) +#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ +#define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits (ADC4 only) */ -#define ADC4_RESOLUTION_12B (LL_ADC_RESOLUTION_12B_ADC4) /*!< ADC resolution 12 bits */ -#define ADC4_RESOLUTION_10B (LL_ADC_RESOLUTION_10B_ADC4) /*!< ADC resolution 10 bits */ -#define ADC4_RESOLUTION_8B (LL_ADC_RESOLUTION_8B_ADC4) /*!< ADC resolution 8 bits */ -#define ADC4_RESOLUTION_6B (LL_ADC_RESOLUTION_6B_ADC4) /*!< ADC resolution 6 bits */ +/* Legacy literals */ +#define ADC4_RESOLUTION_12B ADC_RESOLUTION_12B +#define ADC4_RESOLUTION_10B ADC_RESOLUTION_10B +#define ADC4_RESOLUTION_8B ADC_RESOLUTION_8B +#define ADC4_RESOLUTION_6B ADC_RESOLUTION_6B /** * @} */ @@ -782,10 +795,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_LowPower_DPD ADC low power and deep power down selection * @{ */ -#define ADC_LOW_POWER_NONE (0x00000000UL) /*!< Both Low Power Auto Off and Deep Power Down is Disabled*/ -#define ADC_LOW_POWER_AUTOFF (ADC4_PW_AUTOFF) /*!< Low Power Auto Off Enabled and Deep Power Down is Disabled*/ -#define ADC_LOW_POWER_DPD (ADC4_PW_DPD) /*!< Low Power Auto Off Disabled and Deep Power Down is Enabaled*/ -#define ADC_LOW_POWER_AUTOFF_DPD (ADC4_PW_AUTOFF | ADC4_PW_DPD) /*!< Low Power Auto Off Disabled and Deep Power Down is Enabaled*/ +#define ADC_LOW_POWER_NONE (0x00000000UL) /*!< Both Low Power Auto Off and Deep Power Down is disabled */ +#define ADC_LOW_POWER_AUTOFF (ADC4_PWRR_AUTOFF) /*!< Low Power Auto Off enabled and Deep Power Down is disabled */ +#define ADC_LOW_POWER_DPD (ADC4_PWRR_DPD) /*!< Low Power Auto Off disabled and Deep Power Down is enabled */ +#define ADC_LOW_POWER_AUTOFF_DPD (ADC4_PWRR_AUTOFF | ADC4_PWRR_DPD) /*!< Low Power Auto Off and Deep Power Down are enabled */ /** * @} */ @@ -793,10 +806,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_VrefProt ADC VREF+ protection mode selection * @{ */ -#define ADC_VREF_PPROT_NONE (0x00000000UL) /*!< No VREF protection is applied*/ -#define ADC_VREF_PPROT_VREFPROT (ADC4_PW_VREFPROT) /*!< VREF+ protection when multiple ADCs are working simultaneously and a clock divider is used.*/ -#define ADC_VREF_PPROT_VREFSECSMP (ADC4_PW_VREFSECSMP) /*!< VREF+ protection when multiple ADCs are working simultaneously and a clock divider of 1 is used.*/ -#define ADC_VREF_PPROT_VREF_VREFSECSMP (ADC4_PW_VREFPROT | ADC4_PW_VREFSECSMP) /*!< Both VREF+ protection when multiple ADCs are working simultaneously and VREF+ second sample protection.*/ +#define ADC_VREF_PPROT_NONE (0x00000000UL) /*!< No VREF protection is applied*/ +#define ADC_VREF_PPROT_VREFPROT (ADC4_PWRR_VREFPROT) /*!< VREF+ protection when multiple ADCs are working simultaneously and a clock divider is used.*/ +#define ADC_VREF_PPROT_VREFSECSMP (ADC4_PWRR_VREFSECSMP) /*!< VREF+ protection when multiple ADCs are working simultaneously and a clock divider of 1 is used.*/ +#define ADC_VREF_PPROT_VREF_VREFSECSMP (ADC4_PWRR_VREFPROT | ADC4_PWRR_VREFSECSMP) /*!< Both VREF+ protection when multiple ADCs are working simultaneously and VREF+ second sample protection.*/ /** * @} */ @@ -822,11 +835,11 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_EXT_IT15 (LL_ADC_REG_TRIG_EXT_EXTI_LINE15) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_LPTIM1_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 CH1 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_LPTIM2_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM2_CH1) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 CH1 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_LPTIM3_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM3_CH1) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 CH1 event. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_LPTIM4_OUT (LL_ADC_REG_TRIG_EXT_LPTIM4_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_EXT_IT15 (LL_ADC_REG_TRIG_EXT_EXTI_LINE15) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 15 event. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_LPTIM1_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 channel 1 event. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_LPTIM2_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM2_CH1) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 channel 1 event. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_LPTIM3_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM3_CH1) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 channel 1 event. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_LPTIM4_OUT (LL_ADC_REG_TRIG_EXT_LPTIM4_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM4 OUT event. Trigger edge set to rising edge (default setting). */ #define ADC4_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4_ADC4) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC4_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2_ADC4) @@ -935,13 +948,13 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time * @{ */ -#define ADC_SAMPLETIME_5CYCLE (LL_ADC_SAMPLINGTIME_5CYCLE) /*!< Sampling time 5 ADC clock cycles */ +#define ADC_SAMPLETIME_5CYCLES (LL_ADC_SAMPLINGTIME_5CYCLES) /*!< Sampling time 5 ADC clock cycles */ #define ADC_SAMPLETIME_6CYCLES (LL_ADC_SAMPLINGTIME_6CYCLES) /*!< Sampling time 6 ADC clock cycles */ #define ADC_SAMPLETIME_12CYCLES (LL_ADC_SAMPLINGTIME_12CYCLES) /*!< Sampling time 12 ADC clock cycles */ #define ADC_SAMPLETIME_20CYCLES (LL_ADC_SAMPLINGTIME_20CYCLES) /*!< Sampling time 20 ADC clock cycles */ #define ADC_SAMPLETIME_36CYCLES (LL_ADC_SAMPLINGTIME_36CYCLES) /*!< Sampling time 36 ADC clock cycles */ #define ADC_SAMPLETIME_68CYCLES (LL_ADC_SAMPLINGTIME_68CYCLES) /*!< Sampling time 68 ADC clock cycles */ -#define ADC_SAMPLETIME_391CYCLES_5 (LL_ADC_SAMPLINGTIME_391CYCLES_5)/*!< Sampling time 391.5 ADC clock cycles */ +#define ADC_SAMPLETIME_391CYCLES (LL_ADC_SAMPLINGTIME_391CYCLES) /*!< Sampling time 391 ADC clock cycles */ #define ADC_SAMPLETIME_814CYCLES (LL_ADC_SAMPLINGTIME_814CYCLES) /*!< Sampling time 814 ADC clock cycles */ /** * @} @@ -957,7 +970,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC4_SAMPLETIME_19CYCLES_5 (LL_ADC4_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */ #define ADC4_SAMPLETIME_39CYCLES_5 (LL_ADC4_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */ #define ADC4_SAMPLETIME_79CYCLES_5 (LL_ADC4_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */ -#define ADC4_SAMPLETIME_160CYCLES_5 (LL_ADC4_SAMPLINGTIME_160CYCLES_5) /*!< Sampling time 160.5 ADC clock cycles */ +#define ADC4_SAMPLETIME_814CYCLES_5 (LL_ADC4_SAMPLINGTIME_814CYCLES_5) /*!< Sampling time 814.5 ADC clock cycles */ /** * @} */ @@ -1055,14 +1068,14 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_analog_watchdog_filtering_config ADC Analog Watchdog filtering configuration * @{ */ -#define ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt */ -#define ADC_AWD_FILTERING_2SAMPLES ((ADC_HTR_AWDFILT_0)) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define ADC_AWD_FILTERING_3SAMPLES ((ADC_HTR_AWDFILT_1)) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define ADC_AWD_FILTERING_4SAMPLES ((ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0)) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define ADC_AWD_FILTERING_5SAMPLES ((ADC_HTR_AWDFILT_2)) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define ADC_AWD_FILTERING_6SAMPLES ((ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_0)) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define ADC_AWD_FILTERING_7SAMPLES ((ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1)) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define ADC_AWD_FILTERING_8SAMPLES ((ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0)) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */ +#define ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog watchdog no filtering, one out-of-window sample is needed to raise flag or interrupt */ +#define ADC_AWD_FILTERING_2SAMPLES ((ADC_HTR_AWDFILT_0)) /*!< ADC analog watchdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */ +#define ADC_AWD_FILTERING_3SAMPLES ((ADC_HTR_AWDFILT_1)) /*!< ADC analog watchdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */ +#define ADC_AWD_FILTERING_4SAMPLES ((ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0)) /*!< ADC analog watchdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */ +#define ADC_AWD_FILTERING_5SAMPLES ((ADC_HTR_AWDFILT_2)) /*!< ADC analog watchdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */ +#define ADC_AWD_FILTERING_6SAMPLES ((ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_0)) /*!< ADC analog watchdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */ +#define ADC_AWD_FILTERING_7SAMPLES ((ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1)) /*!< ADC analog watchdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */ +#define ADC_AWD_FILTERING_8SAMPLES ((ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0)) /*!< ADC analog watchdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */ /** * @} */ @@ -1174,7 +1187,6 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */ #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */ #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ -#define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ /** * @} */ @@ -1193,7 +1205,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ -#define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ +#define ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC End of Calibration interrupt source */ +#define ADC_IT_LDORDY ADC_IER_LDORDYIE /*!< ADC Voltage Regulator (LDO) Ready interrupt source */ #define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ @@ -1214,7 +1227,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ -#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC End of Calibration flag */ +#define ADC_FLAG_LDORDY ADC_ISR_LDORDY /*!< ADC Voltage Regulator (LDO) Ready flag */ /** * @} @@ -1485,13 +1499,13 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @param __TIME__ ADC conversions sampling time. * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) */ -#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_5CYCLE) || \ +#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_5CYCLES) || \ ((__TIME__) == ADC_SAMPLETIME_6CYCLES) || \ - ((__TIME__) == ADC_SAMPLETIME_12CYCLES) || \ + ((__TIME__) == ADC_SAMPLETIME_12CYCLES) || \ ((__TIME__) == ADC_SAMPLETIME_20CYCLES) || \ ((__TIME__) == ADC_SAMPLETIME_36CYCLES) || \ ((__TIME__) == ADC_SAMPLETIME_68CYCLES) || \ - ((__TIME__) == ADC_SAMPLETIME_391CYCLES_5) || \ + ((__TIME__) == ADC_SAMPLETIME_391CYCLES) || \ ((__TIME__) == ADC_SAMPLETIME_814CYCLES) ) #define IS_ADC4_SAMPLE_TIME(TIME) (((TIME) == ADC4_SAMPLETIME_1CYCLE_5) || \ @@ -1501,8 +1515,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to ((TIME) == ADC4_SAMPLETIME_19CYCLES_5) || \ ((TIME) == ADC4_SAMPLETIME_39CYCLES_5) || \ ((TIME) == ADC4_SAMPLETIME_79CYCLES_5) || \ - ((TIME) == ADC4_SAMPLETIME_160CYCLES_5) ) + ((TIME) == ADC4_SAMPLETIME_814CYCLES_5) ) +#define IS_ADC4_SAMPLE_TIME_COMMON(TIME) (((TIME) == ADC4_SAMPLINGTIME_COMMON_1) || \ + ((TIME) == ADC4_SAMPLINGTIME_COMMON_2) ) /** * @brief Verify the ADC regular channel setting. * @param __CHANNEL__ programmed ADC regular channel. @@ -1629,7 +1645,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. + * @arg @ref ADC_IT_EOCAL ADC End of Calibration interrupt source + * @arg @ref ADC_IT_LDORDY ADC Voltage Regulator (LDO) Ready interrupt source * @retval None */ #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ @@ -1650,7 +1667,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. + * @arg @ref ADC_IT_EOCAL ADC End of Calibration interrupt source + * @arg @ref ADC_IT_LDORDY ADC Voltage Regulator (LDO) Ready interrupt source * @retval None */ #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ @@ -1670,7 +1688,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. + * @arg @ref ADC_IT_EOCAL ADC End of Calibration interrupt source + * @arg @ref ADC_IT_LDORDY ADC Voltage Regulator (LDO) Ready interrupt source * @retval State of interruption (SET or RESET) */ #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ @@ -1691,7 +1710,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. + * @arg @ref ADC_FLAG_EOCAL ADC End of Calibration flag + * @arg @ref ADC_FLAG_LDORDY ADC Voltage Regulator (LDO) Ready flag * @retval State of flag (TRUE or FALSE). */ #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ @@ -1712,7 +1732,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. + * @arg @ref ADC_FLAG_EOCAL ADC End of Calibration flag + * @arg @ref ADC_FLAG_LDORDY ADC Voltage Regulator (LDO) Ready flag * @retval None */ /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ @@ -2324,7 +2345,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, const uint32_ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); @@ -2332,6 +2353,9 @@ void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_CalibrationCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_VoltageRegulatorCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_ADCReadyCallback(ADC_HandleTypeDef *hadc); /** * @} */ @@ -2352,8 +2376,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_Ana /** @addtogroup ADC_Exported_Functions_Group4 * @{ */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_adc_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_adc_ex.c index db2c63fc987..471e5d9cf96 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_adc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_adc_ex.c @@ -66,14 +66,13 @@ once the ADC is enabled */ /* Fixed timeout value for ADC calibration. */ -/* Values defined to be higher than worst cases: low clock frequency, */ -/* maximum prescalers. */ -/* Ex of profile low frequency : f_ADC at 4,577 Khz (minimum value */ -/* according to Data sheet), calibration_time MAX = 16384 / f_ADC */ -/* 16384 / 4577.63671875 = 3.58s */ -/* At maximum CPU speed (400 MHz), this means */ -/* 3.58 * 400 MHz = 1432000000 CPU cycles */ -#define ADC_CALIBRATION_TIMEOUT (1432000000U) /*!< ADC calibration time-out value */ +/* Values defined to be higher than worst cases: maximum ratio between ADC */ +/* and CPU clock frequencies. */ +/* Example of profile low frequency : ADC frequency minimum 140kHz (cf */ +/* datasheet for ADC4), CPU frequency 160MHz. */ +/* Calibration time max = 25502 / fADC (refer to datasheet) */ +/* = 29M CPU cycles */ +#define ADC_CALIBRATION_TIMEOUT (29000000U) /*!< ADC calibration time-out value */ /** * @} @@ -135,6 +134,8 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t { HAL_StatusTypeDef tmp_hal_status; __IO uint32_t wait_loop_index = 0UL; + uint32_t backup_setting_cfgr1; + uint32_t backup_setting_pwrr; UNUSED(SingleDiff); /* STM32U5 calibration is not making difference between Single and Diff ended */ /* We keep this to be inligne with old products API and for any further use */ @@ -156,28 +157,114 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); - /* Start ADC calibration in mode single-ended or differential */ - LL_ADC_StartCalibration(hadc->Instance, CalibrationMode); + if (hadc->Instance == ADC4) + { + /* Manage settings impacting calibration */ + /* - Disable ADC mode auto power-off */ + /* - Disable ADC DMA transfer request during calibration */ + /* Note: Specificity of this STM32 series: Calibration factor is */ + /* available in data register and also transferred by DMA. */ + /* To not insert ADC calibration factor among ADC conversion data */ + /* in array variable, DMA transfer must be disabled during */ + /* calibration. */ + backup_setting_pwrr = READ_BIT(hadc->Instance->PWRR, ADC4_PWRR_AUTOFF); + backup_setting_cfgr1 = READ_BIT(hadc->Instance->CFGR1, ADC4_CFGR1_DMAEN | ADC4_CFGR1_DMACFG); + CLEAR_BIT(hadc->Instance->CFGR1, ADC4_CFGR1_DMAEN | ADC4_CFGR1_DMACFG); + CLEAR_BIT(hadc->Instance->PWRR, ADC4_PWRR_AUTOFF); + + /* Start ADC calibration in mode single-ended */ + LL_ADC_StartCalibration(hadc->Instance, LL_ADC_CALIB_OFFSET); + + /* Wait for calibration completion */ + while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) + { + wait_loop_index++; + if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) + { + /* Update ADC state machine to error */ + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); + + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + } - /* Wait for calibration completion */ - while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) + /* Restore configuration after calibration */ + SET_BIT(hadc->Instance->CFGR1, backup_setting_cfgr1); + SET_BIT(hadc->Instance->PWRR, backup_setting_pwrr); + } + else /* ADC instance ADC1 or ADC2 */ { - wait_loop_index++; - if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) + /* Get device information */ + uint32_t dev_id = READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID); + uint32_t rev_id = READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos; + + /* Assess whether extended calibration is available on the selected device */ + if ((dev_id == 0x455UL) || (dev_id == 0x476UL) + || (((dev_id == 0x481UL) || (dev_id == 0x482UL)) && (rev_id >= 0x3000UL))) { - /* Update ADC state machine to error */ - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); + /* Perform extended calibration */ + /* Refer to ref manual for extended calibration procedure details */ + tmp_hal_status = ADC_Enable(hadc); - __HAL_UNLOCK(hadc); + if (tmp_hal_status == HAL_OK) + { + MODIFY_REG(hadc->Instance->CR, ADC_CR_CALINDEX, 0x9UL << ADC_CR_CALINDEX_Pos); + MODIFY_REG(hadc->Instance->CALFACT2, 0x00FF0000UL, 0x00020000UL); + SET_BIT(hadc->Instance->CALFACT, ADC_CALFACT_LATCH_COEF); - return HAL_ERROR; + tmp_hal_status = ADC_Disable(hadc); + + if (CalibrationMode == ADC_CALIB_OFFSET_LINEARITY) + { + MODIFY_REG(hadc->Instance->CR, ADC_CR_ADCALLIN | ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADCALLIN); + } + + MODIFY_REG(hadc->Instance->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADCAL); + + /* Wait for calibration completion */ + while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) + { + wait_loop_index++; + if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) + { + /* Update ADC state machine to error */ + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); + + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + } + } + } + else + { + /* Start ADC calibration in mode single-ended or differential */ + LL_ADC_StartCalibration(hadc->Instance, CalibrationMode); + + /* Wait for calibration completion */ + while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) + { + wait_loop_index++; + if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) + { + /* Update ADC state machine to error */ + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); + + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + } } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } - else + else /* ADC not disabled */ { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); @@ -200,18 +287,36 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t */ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff) { + uint32_t Calib_Val = 0UL; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); - /* Return the selected ADC calibration value */ - return LL_ADC_GetCalibrationOffsetFactor(hadc->Instance, SingleDiff); + if (hadc->Instance != ADC4) + { + tmp_hal_status = ADC_Enable(hadc); /* ADC need to be enabled to perform calibration for ADC1/2 and not for ADC4 */ + } + + if (tmp_hal_status == HAL_OK) + { + /* Return the selected ADC calibration value */ + Calib_Val = LL_ADC_GetCalibrationOffsetFactor(hadc->Instance, SingleDiff); + } + + if (hadc->Instance != ADC4) + { + tmp_hal_status = ADC_Disable(hadc); + UNUSED(tmp_hal_status); + } + return Calib_Val; } /** * @brief Get the calibration factor from automatic conversion result - * @param hadc ADC handle - * @param pLinearCalib_Buffer: Linear calibration factor + * @param hadc ADC handle + * @param pLinearCalib_Buffer Linear calibration factor (table of 9 elements) * @retval HAL state */ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t *pLinearCalib_Buffer) @@ -222,23 +327,33 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - /* Enable the ADC ADEN = 1 to be able to read the linear calibration factor */ - tmp_hal_status = ADC_Enable(hadc); - - if (tmp_hal_status == HAL_OK) + if (hadc->Instance != ADC4) { - SET_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CAPTURE_COEF); - CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_LATCH_COEF); - for (cnt = 0UL; cnt <= 8UL; cnt++) + /* Enable the ADC to be able to read the linear calibration factor */ + tmp_hal_status = ADC_Enable(hadc); + + if (tmp_hal_status == HAL_OK) { - MODIFY_REG(hadc->Instance->CR, - (ADC_CR_CALINDEX3 | ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1 | ADC_CR_CALINDEX0), - (cnt << ADC_CR_CALINDEX0_Pos)); /* LinearityWord == CalibIndex (1 to 8 for linearity reading)*/ - pLinearCalib_Buffer[cnt] = (uint32_t)(READ_BIT(hadc->Instance->CALFACT2, ADC_CALFACT2_CALFACT_Msk)); + /* Note: Bitfields ADC_CALFACT_LATCH_COEF and ADC_CALFACT_CAPTURE_COEF have property "wr1", + therefore they are not cleared in this function. */ + SET_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CAPTURE_COEF); + + for (cnt = 0UL; cnt <= 8UL; cnt++) + { + MODIFY_REG(hadc->Instance->CR, + (ADC_CR_CALINDEX), + (cnt << ADC_CR_CALINDEX_Pos)); + pLinearCalib_Buffer[cnt] = (uint32_t)(READ_BIT(hadc->Instance->CALFACT2, ADC_CALFACT2_CALFACT_Msk)); + } } + + tmp_hal_status = ADC_Disable(hadc); + } + else + { + /* ADC linear calibration not available on ADC4 */ + tmp_hal_status = HAL_ERROR; } - CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CAPTURE_COEF); - tmp_hal_status = ADC_Disable(hadc); return tmp_hal_status; } @@ -250,13 +365,13 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, * @param SingleDiff This parameter can be only: * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended - * @param CalibrationFactor Calibration factor (coded on 7 bits maximum) + * @param CalibrationFactor Calibration factor (range 0xFFFF for ADC1 and ADC2, range 0x7F for ADC4) * @retval HAL state */ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; + HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; @@ -272,13 +387,20 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) - && (tmp_adc_is_conversion_on_going_regular == 0UL) + if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { - /* Set the selected ADC calibration value */ - LL_ADC_SetCalibrationOffsetFactor(hadc->Instance, SingleDiff, CalibrationFactor); + /* Enable the ADC to be able to set the calibration factor */ + tmp_hal_status = ADC_Enable(hadc); + + if (tmp_hal_status == HAL_OK) + { + /* Set the selected ADC calibration value */ + LL_ADC_SetCalibrationOffsetFactor(hadc->Instance, SingleDiff, CalibrationFactor); + + tmp_hal_status = ADC_Disable(hadc); + } } else { @@ -298,80 +420,58 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32 /** * @brief Set the linear calibration factor - * @param hadc ADC handle - * @param pLinearCalib_Buffer: Linear calibration factor + * @param hadc ADC handle + * @param pLinearCalib_Buffer Linear calibration factor (table of 9 elements) * @retval HAL state */ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t *pLinearCalib_Buffer) { uint32_t cnt; - __IO uint32_t wait_loop_index; + HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - /* - Exit from deep-power-down mode and ADC voltage regulator enable */ - /* Exit deep power down mode if still in that state */ - if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_DEEPPWD)) + if (hadc->Instance != ADC4) { - /* Exit deep power down mode */ - CLEAR_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD); - - /* System was in deep power down mode, calibration must - be relaunched or a previously saved calibration factor - re-applied once the ADC voltage regulator is enabled */ - } + tmp_hal_status = ADC_Enable(hadc); - if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN)) - { - /* Enable ADC internal voltage regulator */ - SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN); - /* Delay for ADC stabilization time */ - /* Wait loop initialization and execution */ - /* Note: Variable divided by 2 to compensate partially */ - /* CPU processing cycles. */ - wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000UL * 2UL))); - while (wait_loop_index != 0UL) + if (tmp_hal_status == HAL_OK) { - wait_loop_index--; - } - } + /* Note: Bitfields ADC_CALFACT_LATCH_COEF and ADC_CALFACT_CAPTURE_COEF have property "wr1", + therefore they are not cleared in this function. */ + for (cnt = 0UL; cnt <= 7UL; cnt++) + { + MODIFY_REG(hadc->Instance->CR, + (ADC_CR_CALINDEX), + (cnt << ADC_CR_CALINDEX_Pos)); - /* Verification that ADC voltage regulator is correctly enabled, whether */ - /* or not ADC is coming from state reset (if any potential problem of */ - /* clocking, voltage regulator would not be enabled). */ - if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN)) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + if (cnt == 7UL) + { + /* Specific case for linearity factor 7 and internal offset: must be concatenated */ + MODIFY_REG(hadc->Instance->CALFACT2, + ADC_CALFACT2_CALFACT, + pLinearCalib_Buffer[cnt] | ((pLinearCalib_Buffer[cnt + 1UL] & 0xFF000000UL) >> 8UL)); + } + else + { + MODIFY_REG(hadc->Instance->CALFACT2, ADC_CALFACT2_CALFACT, pLinearCalib_Buffer[cnt]); + } + } - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + SET_BIT(hadc->Instance->CALFACT, ADC_CALFACT_LATCH_COEF); + CLEAR_BIT(hadc->Instance->CR, ADC_CR_CALINDEX); - return HAL_ERROR; + tmp_hal_status = ADC_Disable(hadc); + } } - if (ADC_Enable(hadc) == HAL_OK) + else { - /* We need to wait till ADC_ISR_ADRDY flag go up to set calibration values. */ - /* However this is already done by ADC_Enable(). */ - /* Therefore a simple check of the flag could help to ensure ADC is ready. */ - if ((hadc->Instance->ISR & ADC_ISR_ADRDY) == 0UL) - { - return HAL_ERROR; - } - - CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_LATCH_COEF | ADC_CALFACT_CAPTURE_COEF); - for (cnt = 0UL; cnt <= 8UL; cnt++) - { - MODIFY_REG(hadc->Instance->CR, - (ADC_CR_CALINDEX3 | ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1 | ADC_CR_CALINDEX0), - (cnt << ADC_CR_CALINDEX0_Pos)); /* LinearityWord == CalibIndex (1 to 8 for linearity reading)*/ - MODIFY_REG(hadc->Instance->CALFACT2, ADC_CALFACT2_CALFACT, pLinearCalib_Buffer[cnt]); - } + /* ADC linear calibration not available on ADC4 */ + tmp_hal_status = HAL_ERROR; } - SET_BIT(hadc->Instance->CALFACT, ADC_CALFACT_LATCH_COEF); - CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CAPTURE_COEF); - return HAL_OK; + + return tmp_hal_status; } /** @@ -417,16 +517,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc) /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { - /* Check if a regular conversion is ongoing */ - if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL) - { - /* Reset ADC error code field related to injected conversions only */ - CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); - } - else - { - ADC_CLEAR_ERRORCODE(hadc); - } + /* Clear ADC error code */ + ADC_CLEAR_ERRORCODE(hadc); /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ @@ -734,16 +826,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc) /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { - /* Check if a regular conversion is ongoing */ - if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL) - { - /* Reset ADC error code field related to injected conversions only */ - CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); - } - else - { - ADC_CLEAR_ERRORCODE(hadc); - } + /* Clear ADC error code */ + ADC_CLEAR_ERRORCODE(hadc); /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ @@ -870,7 +954,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) if (tmp_hal_status == HAL_OK) { /* Disable ADC end of conversion interrupt for injected channels */ - __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF)); + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS)); if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { @@ -920,6 +1004,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const ui ADC_HandleTypeDef tmp_hadc_slave; ADC_Common_TypeDef *tmp_adc_common; uint32_t LengthInBytes; + DMA_NodeConfTypeDef node_conf; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); @@ -954,6 +1039,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const ui tmp_hal_status = ADC_Enable(hadc); if (tmp_hal_status == HAL_OK) { + /* Reinitialize the LowPowerAutoPowerOff parameter from master to slave */ + tmp_hadc_slave.Init.LowPowerAutoPowerOff = hadc->Init.LowPowerAutoPowerOff; tmp_hal_status = ADC_Enable(&tmp_hadc_slave); } @@ -994,19 +1081,39 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const ui /* Enable ADC overrun interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - /* Length should be converted to number of bytes */ - LengthInBytes = Length * 4U; - /* Start the DMA channel */ + /* Check linkedlist mode */ if ((hadc->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) { if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL)) { + /* Length should be converted to number of bytes */ + if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hadc->DMA_Handle->LinkedListQueue->Head) != HAL_OK) + { + return HAL_ERROR; + } + + /* Length should be converted to number of bytes */ + if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + /* Word -> Bytes */ + LengthInBytes = Length * 4U; + } + else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD) + { + /* Halfword -> Bytes */ + LengthInBytes = Length * 2U; + } + else /* Bytes */ + { + /* Same size already expressed in Bytes */ + LengthInBytes = Length; + } + hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t)LengthInBytes; - hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \ + hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \ (uint32_t)&tmp_adc_common->CDR; hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; - tmp_hal_status = HAL_DMAEx_List_Start_IT(hadc->DMA_Handle); } else @@ -1016,7 +1123,24 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const ui } else { - tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmp_adc_common->CDR, (uint32_t)pData, \ + /* Length should be converted to number of bytes */ + if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + /* Word -> Bytes */ + LengthInBytes = Length * 4U; + } + else if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD) + { + /* Halfword -> Bytes */ + LengthInBytes = Length * 2U; + } + else /* Bytes */ + { + /* Same size already expressed in Bytes */ + LengthInBytes = Length; + } + + tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmp_adc_common->CDR, (uint32_t)pData, \ LengthInBytes); } @@ -1167,7 +1291,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used) * @retval The converted data values. */ -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc) { const ADC_Common_TypeDef *tmp_adc_common; @@ -1184,6 +1308,176 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) /* Return the multi mode conversion value */ return tmp_adc_common->CDR; } + +/** + * @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA. + * @note Multimode must have been previously configured using + * HAL_ADCEx_MultiModeConfigChannel() function. + * Interruptions enabled in this function: + * overrun, DMA half transfer, DMA transfer complete. + * Each of these interruptions has its dedicated callback function. + * @note State field of Slave ADC handle is not updated in this configuration: + * user should not rely on it for information related to Slave regular + * conversions. + * @param hadc ADC handle of ADC + * @note - Only ADC master could start the conversion. + * - Two ADC conversions (Master & Slave) per external trig and so two DMA requests. + * @param pData Destination Buffer address. + * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA_Data32(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length) +{ + HAL_StatusTypeDef tmp_hal_status; + ADC_HandleTypeDef tmp_hadc_slave; + ADC_Common_TypeDef *tmp_adc_common; + uint32_t LengthInBytes; + + /* Check the parameters */ + assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) + { + return HAL_BUSY; + } + else + { + __HAL_LOCK(hadc); + + /* Temporary handle minimum initialization */ + __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave); + ADC_CLEAR_ERRORCODE(&tmp_hadc_slave); + + /* Set a temporary handle of the ADC slave associated to the ADC master */ + ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave); + + if (tmp_hadc_slave.Instance == NULL) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + + /* Enable the ADC peripherals: master and slave (in case if not already */ + /* enabled previously) */ + tmp_hal_status = ADC_Enable(hadc); + if (tmp_hal_status == HAL_OK) + { + /* Reinitialize the LowPowerAutoPowerOff parameter from master to slave */ + tmp_hadc_slave.Init.LowPowerAutoPowerOff = hadc->Init.LowPowerAutoPowerOff; + tmp_hal_status = ADC_Enable(&tmp_hadc_slave); + } + + /* Start multimode conversion of ADCs pair */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR \ + | HAL_ADC_STATE_REG_EOSMP), + HAL_ADC_STATE_REG_BUSY); + + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Set the DMA transfer complete callback */ + hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; + + /* Set the DMA half transfer complete callback */ + hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; + + /* Set the DMA error callback */ + hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; + + /* Pointer to the common control register */ + tmp_adc_common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); + + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ + /* start (in case of SW start): */ + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Enable ADC overrun interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + + /* Length should be converted to number of bytes */ + LengthInBytes = (uint32_t)(Length * 4U); + + /* Start the DMA channel */ + if ((hadc->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL)) + { + hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (LengthInBytes * 2U); + hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \ + (uint32_t)&tmp_adc_common->CDR2; + hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + tmp_hal_status = HAL_DMAEx_List_Start_IT(hadc->DMA_Handle); + } + else + { + tmp_hal_status = HAL_ERROR; + }; + } + else + { + tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmp_adc_common->CDR2, (uint32_t)pData, \ + (LengthInBytes * 2U)); + } + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hadc); + } + + /* Return function status */ + return tmp_hal_status; + } +} + +/** + * @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration. + * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used) + * @retval The converted data values. + */ +uint32_t HAL_ADCEx_MultiModeGetValue_Data32(const ADC_HandleTypeDef *hadc) +{ + const ADC_Common_TypeDef *tmpADC_Common; + + /* Check the parameters */ + assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); + + /* Prevent unused argument(s) compilation warning if no assert_param check */ + /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */ + UNUSED(hadc); + + /* Pointer to the common control register */ + tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); + + /* Return the multi mode conversion value */ + return tmpADC_Common->CDR2; +} #endif /* ADC_MULTIMODE_SUPPORT */ /** @@ -1214,7 +1508,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4 * @retval ADC group injected conversion data */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank) +uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank) { uint32_t tmp_jdr; @@ -1748,7 +2042,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I { if (hadc->Instance != ADC4) /* ADC1 or ADC2 */ { +#if defined (ADC2) + assert_param(IS_ADC12_DIFF_CHANNEL(pConfigInjected->InjectedChannel)); +#else assert_param(IS_ADC1_DIFF_CHANNEL(pConfigInjected->InjectedChannel)); +#endif /* ADC2 */ } } @@ -1955,7 +2253,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I if (pConfigInjected->InjecOversamplingMode == ENABLE) { assert_param(IS_ADC_OVERSAMPLING_RATIO(pConfigInjected->InjecOversampling.Ratio)); - assert_param(IS_ADC_RIGHT_BIT_SHIFT(pConfigInjected->InjecOversampling.RightBitShift)); + assert_param(IS_ADC12_RIGHT_BIT_SHIFT(pConfigInjected->InjecOversampling.RightBitShift)); /* JOVSE must be reset in case of triggered regular mode */ assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) == @@ -1968,9 +2266,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* Enable OverSampling mode */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE | ADC_CFGR2_OVSR | ADC_CFGR2_OVSS, - ADC_CFGR2_JOVSE | pConfigInjected->InjecOversampling.Ratio | - pConfigInjected->InjecOversampling.RightBitShift - ); + ADC_CFGR2_JOVSE | (pConfigInjected->InjecOversampling.Ratio << ADC_CFGR2_OVSR_Pos) | + pConfigInjected->InjecOversampling.RightBitShift); } else { @@ -1995,39 +2292,53 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I tmp_offset_shifted); /* Set ADC selected offset sign */ LL_ADC_SetOffsetSign(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedOffsetSign); - /* Set ADC selected offset signed saturation */ - LL_ADC_SetOffsetSignedSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber, - (pConfigInjected->InjectedOffsetSignedSaturation == ENABLE) - ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE \ - : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); + + /* Configure offset saturation */ + if (pConfigInjected->InjectedOffsetSaturation == ENABLE) + { + /* Set ADC selected offset unsigned/signed saturation */ + LL_ADC_SetOffsetUnsignedSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber, + (pConfigInjected->InjectedOffsetSignedSaturation == DISABLE) + ? LL_ADC_OFFSET_UNSIGNED_SATURATION_ENABLE \ + : LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE); + + LL_ADC_SetOffsetSignedSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber, + (pConfigInjected->InjectedOffsetSignedSaturation == ENABLE) + ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE \ + : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); + } + else + { + /* Disable ADC offset signed saturation */ + LL_ADC_SetOffsetUnsignedSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber, + LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE); + LL_ADC_SetOffsetSignedSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber, + LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); + } } else { /* Scan each offset register to check if the selected channel is targeted. */ /* If this is the case, the corresponding offset number is disabled. */ - if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == - __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) { - LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_1, pConfigInjected->InjectedChannel, - LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); + LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_1, pConfigInjected->InjectedChannel, 0x0); } - if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == - __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) { - LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_2, pConfigInjected->InjectedChannel, - LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); + LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_2, pConfigInjected->InjectedChannel, 0x0); } - if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == - __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) { - LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, pConfigInjected->InjectedChannel, - LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); + LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_3, pConfigInjected->InjectedChannel, 0x0); } - if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == - __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) { - LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, pConfigInjected->InjectedChannel, - LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); + LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, pConfigInjected->InjectedChannel, 0x0); } } } @@ -2149,9 +2460,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *pMultimode) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - ADC_Common_TypeDef *tmpADC_Common; - ADC_HandleTypeDef tmphadcSlave; - uint32_t tmphadcSlave_conversion_on_going; + ADC_Common_TypeDef *tmp_adc_common; + ADC_HandleTypeDef tmp_hadc_slave; + uint32_t tmp_hadc_slave_conversion_on_going; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); @@ -2168,9 +2479,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_ __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave); ADC_CLEAR_ERRORCODE(&tmp_hadc_slave); - ADC_MULTI_SLAVE(hadc, &tmphadcSlave); + ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave); - if (tmphadcSlave.Instance == NULL) + if (tmp_hadc_slave.Instance == NULL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); @@ -2185,19 +2496,19 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_ /* conversion on going on regular group: */ /* - Multimode DMA configuration */ /* - Multimode DMA mode */ - tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); + tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - && (tmphadcSlave_conversion_on_going == 0UL)) + && (tmp_hadc_slave_conversion_on_going == 0UL)) { /* Pointer to the common control register */ - tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); + tmp_adc_common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); /* If multimode is selected, configure all pMultimode parameters. */ /* Otherwise, reset pMultimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ if (pMultimode->Mode != ADC_MODE_INDEPENDENT) { - MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, pMultimode->DualModeData); + MODIFY_REG(tmp_adc_common->CCR, ADC_CCR_DAMDF, pMultimode->DualModeData); /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ @@ -2211,20 +2522,20 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_ /* range */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) { - MODIFY_REG(tmpADC_Common->CCR, (ADC_CCR_DUAL | ADC_CCR_DELAY), \ + MODIFY_REG(tmp_adc_common->CCR, (ADC_CCR_DUAL | ADC_CCR_DELAY), \ (pMultimode->Mode | pMultimode->TwoSamplingDelay)); } } else /* ADC_MODE_INDEPENDENT */ { - CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF); + CLEAR_BIT(tmp_adc_common->CCR, ADC_CCR_DAMDF); /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) { - CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); + CLEAR_BIT(tmp_adc_common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); } } } diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_adc_ex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_adc_ex.h index a16a4af1989..5183309acbd 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_adc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_adc_ex.h @@ -46,7 +46,10 @@ extern "C" { typedef struct { uint32_t Ratio; /*!< Configures the oversampling ratio. - This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ + In case of ADC1 or ADC2 (if available), this parameter can be in the + range from 0 to 1023 + In case of ADC4, this parameter can be a value of + @ref ADC_HAL_EC_OVS_RATIO */ uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ @@ -58,13 +61,13 @@ typedef struct * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, * InjectedOffsetNumber, InjectedOffset * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, - * InjectedDiscontinuousConvMode, AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, + * InjectedDiscontinuousConvMode, AutoInjectedConv, ExternalTrigInjecConv, * ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling. * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. * ADC state can be either: * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter * 'InjectedSingleDiff') - * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': + * - For parameters 'InjectedDiscontinuousConvMode', 'InjecOversampling': * ADC enabled without conversion on going on injected group. * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': * ADC enabled without conversion on going on regular and injected groups. @@ -139,9 +142,14 @@ typedef struct without continuous mode or external trigger that could launch a conversion). */ - FunctionalState InjectedOffsetSignedSaturation; /*!< Specifies whether the Signed saturation feature is used or not. - This parameter is applied only for 14-bit or 8-bit resolution. - This parameter can be set to ENABLE or DISABLE. */ + FunctionalState InjectedOffsetSignedSaturation; /*!< Specify whether the Signed saturation feature is used or not. + This parameter is only applied when InjectedOffsetSaturation is + ENABLE. + This parameter is applied only for 14-bit or 8-bit resolution. + This parameter can be set to ENABLE or DISABLE. + Note: + - If InjectedOffsetSignedSaturation is set to DISABLE the unsigned + saturation feature is used */ uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. @@ -398,15 +406,22 @@ typedef struct /** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases * @{ */ -#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ -#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ -#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ +#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_13CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_14CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_15CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_16CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles */ /** * @} @@ -544,7 +559,7 @@ typedef struct * @retval SET (ADC is independent) or RESET (ADC is not). */ #define ADC_IS_INDEPENDENT(__HANDLE__) \ - ( ( ( ((__HANDLE__)->Instance) == ADC3) \ + ( ( ( ((__HANDLE__)->Instance) == ADC4) \ )? \ SET \ : \ @@ -597,7 +612,7 @@ typedef struct * @param _AUTOOFF_ Auto off bit enable or disable. * @retval None */ -#define ADC4_CFGR_AUTOOFF(_AUTOOFF_)((_AUTOOFF_) << ADC4_PW_AUTOOFF_Pos) +#define ADC4_CFGR_AUTOOFF(_AUTOOFF_)((_AUTOOFF_) << ADC4_PWRR_AUTOOFF_Pos) /** * @brief Configure the ADC auto delay mode. @@ -619,6 +634,15 @@ typedef struct * @param __DMACONTREQ_MODE__: DMA continuous request mode. * @retval None */ +#if defined (ADC2) +#define ADC_CFGR_DMACONTREQ(__HANDLE__,__DMACONTREQ_MODE__) \ + ( (((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2) \ + )? \ + ((__DMACONTREQ_MODE__)) \ + : \ + ((__DMACONTREQ_MODE__) << 1U) \ + ) +#else #define ADC_CFGR_DMACONTREQ(__HANDLE__,__DMACONTREQ_MODE__) \ ( (((__HANDLE__)->Instance == ADC1) \ )? \ @@ -626,7 +650,7 @@ typedef struct : \ ((__DMACONTREQ_MODE__) << 1U) \ ) - +#endif /*ADC2 */ /** * @brief Configure the channel number into offset OFRx register. @@ -666,6 +690,24 @@ typedef struct #define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL) #if defined(ADC_MULTIMODE_SUPPORT) + + +/** + * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode or multimode with + * handle of ADC master. + * @param __HANDLE__ ADC handle. + * @note Return SET if multimode feature is not available. + * @retval SET (non-multimode or Master handle) or RESET (handle of Slave ADC in multimode) + */ +#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ + ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC4) \ + )? \ + SET \ + : \ + (((__LL_ADC_COMMON_INSTANCE(__HANDLE__))->CCR & ADC_CCR_DUAL) == RESET) \ + ) + + /** * @brief Configure the ADC DMA continuous request for ADC multimode. * @param __DMACONTREQ_MODE__ DMA continuous request mode. @@ -906,11 +948,11 @@ typedef struct #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) /** - * @brief Calibration factor size verification (7 bits maximum). + * @brief Calibration factor size verification. * @param __CALIBRATION_FACTOR__ Calibration factor value. * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) */ -#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) +#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0xFFFFU)) /** @@ -950,7 +992,30 @@ typedef struct ((__CHANNEL__) == ADC4_CHANNEL_VBAT) || \ ((__CHANNEL__) == ADC_CHANNEL_VCORE) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT) ) - +#if defined (ADC2) +/** + * @brief Verify the ADC channel setting in differential mode for ADC1 and ADC2. + * @param __CHANNEL__: programmed ADC channel. + * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) + */ +#define IS_ADC12_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ + ((__CHANNEL__) == ADC_CHANNEL_2) || \ + ((__CHANNEL__) == ADC_CHANNEL_3) ||\ + ((__CHANNEL__) == ADC_CHANNEL_4) ||\ + ((__CHANNEL__) == ADC_CHANNEL_5) ||\ + ((__CHANNEL__) == ADC_CHANNEL_6) ||\ + ((__CHANNEL__) == ADC_CHANNEL_7) ||\ + ((__CHANNEL__) == ADC_CHANNEL_8) ||\ + ((__CHANNEL__) == ADC_CHANNEL_9) ||\ + ((__CHANNEL__) == ADC_CHANNEL_10) ||\ + ((__CHANNEL__) == ADC_CHANNEL_11) ||\ + ( (__CHANNEL__) == ADC_CHANNEL_12) ||\ + ((__CHANNEL__) == ADC_CHANNEL_13) ||\ + ((__CHANNEL__) == ADC_CHANNEL_14) ||\ + ((__CHANNEL__) == ADC_CHANNEL_15) ||\ + ((__CHANNEL__) == ADC_CHANNEL_16) ||\ + ((__CHANNEL__) == ADC_CHANNEL_17) ) +#else /** * @brief Verify the ADC channel setting in differential mode for ADC1. * @param __CHANNEL__: programmed ADC channel. @@ -973,6 +1038,7 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_15) ||\ ((__CHANNEL__) == ADC_CHANNEL_16) ||\ ((__CHANNEL__) == ADC_CHANNEL_17) ) +#endif /* ADC2 */ /** @@ -1084,7 +1150,16 @@ typedef struct ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) ) + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_16CYCLES) ) #endif /* ADC_MULTIMODE_SUPPORT */ /** @@ -1144,16 +1219,30 @@ typedef struct ((__EVENT__) == ADC_AWD_EVENT) || \ ((__EVENT__) == ADC_AWD2_EVENT) || \ ((__EVENT__) == ADC_AWD3_EVENT) || \ - ((__EVENT__) == ADC_OVR_EVENT) || \ - ((__EVENT__) == ADC_JQOVF_EVENT) ) + ((__EVENT__) == ADC_OVR_EVENT) ) /** * @brief Verify the ADC oversampling ratio. - * @param RATIO: programmed ADC oversampling ratio. + * @param __RATIO__: programmed ADC oversampling ratio. * @retval SET (RATIO is a valid value) or RESET (RATIO is invalid) */ -#define IS_ADC_OVERSAMPLING_RATIO(RATIO) ((RATIO) < 1024UL) +#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) \ + ((((__RATIO__) & ADC4_OVERSAMPLING_RATIO_PARAMETER) != ADC4_OVERSAMPLING_RATIO_PARAMETER) && \ + ((__RATIO__) < 1024UL)) +/** + * @brief Verify the ADC oversampling ratio. + * @param __RATIO__: programmed ADC oversampling ratio. + * @retval SET (RATIO is a valid value) or RESET (RATIO is invalid) + */ +#define IS_ADC4_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256)) /** * @brief Verify the ADC oversampling shift. * @param __SHIFT__ programmed ADC oversampling shift. @@ -1169,6 +1258,24 @@ typedef struct ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) +/** + * @brief Verify the ADC oversampling shift. + * @param __SHIFT__ programmed ADC oversampling shift. + * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) + */ +#define IS_ADC12_RIGHT_BIT_SHIFT( __SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_9 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_10 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_11 )) + /** * @brief Verify the ADC oversampling triggered mode. * @param __MODE__ programmed ADC oversampling triggered mode. @@ -1221,12 +1328,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); #if defined(ADC_MULTIMODE_SUPPORT) /* ADC multimode */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA_Data32(ADC_HandleTypeDef *hadc, const uint32_t *pData, + uint32_t Length); HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc); +uint32_t HAL_ADCEx_MultiModeGetValue_Data32(const ADC_HandleTypeDef *hadc); #endif /* ADC_MULTIMODE_SUPPORT */ /* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); +uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_comp.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_comp.c index ec4c3a721fe..19daf0cf20e 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_comp.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_comp.c @@ -29,7 +29,8 @@ [..] The STM32U5xx device family integrates two analog comparators instances: - COMP1, COMP2. + COMP1, COMP2 except for the products featuring only + one instance: COMP1 (in this case, all comments related to pair of comparators are not applicable) (#) Comparators input minus (inverting input) and input plus (non inverting input) can be set to internal references or to GPIO pins (refer to GPIO list in reference manual). @@ -40,7 +41,7 @@ (refer to GPIO list in reference manual). (#) The comparators have interrupt capability through the EXTI controller - with wake-up from sleep and stop modes: + with wake-up from sleep and stop modes. (++) COMP1 is internally connected to EXTI Line 20 (++) COMP2 is internally connected to EXTI Line 21 @@ -257,11 +258,15 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis)); assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce)); assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); +#if defined(COMP_WINDOW_MODE_SUPPORT) +#if defined(COMP2) assert_param(IS_COMP_WINDOWMODE(hcomp->Instance, hcomp->Init.WindowMode)); +#endif /* COMP2 */ if (hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE) { assert_param(IS_COMP_WINDOWOUTPUT(hcomp->Init.WindowOutput)); } +#endif /* COMP_WINDOW_MODE_SUPPORT */ if (hcomp->State == HAL_COMP_STATE_RESET) { @@ -271,7 +276,6 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) /* Set COMP error code to none */ COMP_CLEAR_ERRORCODE(hcomp); - #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) /* Init the COMP Callback settings */ hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */ @@ -316,6 +320,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) tmp_csr ); +#if defined(COMP_WINDOW_MODE_SUPPORT) /* Set window mode */ /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */ /* instances. Therefore, this function can update another COMP */ @@ -363,6 +368,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT); break; } +#endif /* COMP_WINDOW_MODE_SUPPORT */ /* Delay for COMP scaler bridge voltage stabilization */ /* Apply the delay if voltage scaler bridge is required and not already enabled */ @@ -410,7 +416,6 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) WRITE_REG(EXTI->RPR1, exti_line); WRITE_REG(EXTI->FPR1, exti_line); - /* Configure EXTI event mode */ if ((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL) { @@ -816,12 +821,16 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) { /* Get the EXTI line corresponding to the selected COMP instance */ uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); +#if defined(COMP_WINDOW_MODE_SUPPORT) + uint32_t comparator_window_mode = READ_BIT(hcomp->Instance->CSR, COMP_CSR_WINMODE); +#endif /* COMP_WINDOW_MODE_SUPPORT */ /* Check COMP EXTI flag */ if (READ_BIT(EXTI->RPR1, exti_line) != 0UL) { +#if defined(COMP_WINDOW_MODE_SUPPORT) /* Check whether comparator is in independent or window mode */ - if (READ_BIT(hcomp->Instance->CSR, COMP_CSR_WINMODE) != 0UL) + if (comparator_window_mode != 0UL) { /* Clear COMP EXTI line pending bit of the pair of comparators */ /* in window mode. */ @@ -833,6 +842,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) WRITE_REG(EXTI->RPR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2)); } else +#endif /* COMP_WINDOW_MODE_SUPPORT */ { /* Clear COMP EXTI line pending bit */ WRITE_REG(EXTI->RPR1, exti_line); @@ -845,10 +855,11 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) HAL_COMP_TriggerCallback(hcomp); #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ } - else + else if (READ_BIT(EXTI->FPR1, exti_line) != 0UL) { +#if defined(COMP_WINDOW_MODE_SUPPORT) /* Check whether comparator is in independent or window mode */ - if (READ_BIT(hcomp->Instance->CSR, COMP_CSR_WINMODE) != 0UL) + if (comparator_window_mode != 0UL) { /* Clear COMP EXTI line pending bit of the pair of comparators */ /* in window mode. */ @@ -860,6 +871,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) WRITE_REG(EXTI->FPR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2)); } else +#endif /* COMP_WINDOW_MODE_SUPPORT */ { /* Clear COMP EXTI line pending bit */ WRITE_REG(EXTI->FPR1, exti_line); @@ -872,16 +884,10 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) HAL_COMP_TriggerCallback(hcomp); #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ } - - /* Change COMP state */ - hcomp->State = HAL_COMP_STATE_READY; - - /* COMP trigger user callback */ -#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) - hcomp->TriggerCallback(hcomp); -#else - HAL_COMP_TriggerCallback(hcomp); -#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + else + { + /* nothing to do */ + } } /** @@ -968,7 +974,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) * @arg COMP_OUTPUT_LEVEL_HIGH * */ -uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) +uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp) { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); @@ -1016,7 +1022,7 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) * @param hcomp COMP handle * @retval HAL state */ -HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) +HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp) { /* Check the COMP handle allocation */ if (hcomp == NULL) @@ -1036,7 +1042,7 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) * @param hcomp COMP handle * @retval COMP error code */ -uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp) +uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp) { /* Check the parameters */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); @@ -1063,4 +1069,3 @@ uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp) /** * @} */ - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_comp.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_comp.h index b5c68740bc7..ce1aa45d658 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_comp.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_comp.h @@ -46,16 +46,18 @@ extern "C" { */ typedef struct { - +#if defined(COMP_WINDOW_MODE_SUPPORT) +#if defined(COMP2) uint32_t WindowMode; /*!< Set window mode of a pair of comparators instances (2 consecutive instances odd and even COMP and COMP). Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode. This parameter can be a value of @ref COMP_WindowMode */ +#endif /* COMP2 */ uint32_t WindowOutput; /*!< Set window mode output. This parameter can be a value of @ref COMP_WindowOutput */ - +#endif /* COMP_WINDOW_MODE_SUPPORT */ uint32_t Mode; /*!< Set comparator operating mode to adjust power and speed. Note: For the characteristics of comparator power modes (propagation delay and power consumption), refer to device datasheet. @@ -154,26 +156,74 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @} */ +#if defined(COMP_WINDOW_MODE_SUPPORT) +#if defined(COMP2) /** @defgroup COMP_WindowMode COMP Window Mode * @{ */ -#define COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */ -#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */ -#define COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | COMP_WINDOWMODE_COMP2) /*!< Window mode enable: if used from COMP1 or COMP2 instance, comparators instances pair COMP1 and COMP2 have their input plus connected together, the common input is COMP2 input plus (COMP1 input plus is no more accessible) */ +#define COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators + instances pair COMP1 and COMP2 are + independent */ +#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances + pair COMP1 and COMP2 have their input + plus connected together. + The common input is COMP1 input plus + (COMP2 input plus is no more accessible). + */ +#define COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WINMODE \ + | COMP_WINDOWMODE_COMP2) /*!< Window mode enable: if used from COMP1 or + COMP2 instance, comparators instances + pair COMP1 and COMP2 have their input + plus connected together, the common input + is COMP2 input plus (COMP1 input plus is + no more accessible). */ /** * @} */ +#endif /* COMP2 */ /** @defgroup COMP_WindowOutput COMP Window output * @{ */ -#define COMP_WINDOWOUTPUT_EACH_COMP (0x00000000UL) /*!< Window output default mode: Comparators output are indicating each their own state. To know window mode state: each comparator output must be read, if "((COMPx exclusive or COMPy) == 1)" then monitored signal is within comparators window. */ -#define COMP_WINDOWOUTPUT_COMP1 (COMP_CSR_WINOUT) /*!< Window output synthetized on COMP1 output: COMP1 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */ -#define COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT | COMP_WINDOWMODE_COMP2) /*!< Window output synthetized on COMP2 output: COMP2 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */ -#define COMP_WINDOWOUTPUT_BOTH (0x00000001UL) /*!< Window output synthetized on both comparators output of pair of comparator selected (COMP1 and COMP2): both comparators outputs are no more indicating their own state, but global window mode state (logical high means monitored signal is within comparators window). This is a specific configuration (technically possible but not relevant from application point of view: 2 comparators output used for the same signal level), standard configuration for window mode is one of the settings above. */ +#define COMP_WINDOWOUTPUT_EACH_COMP (0x00000000UL) /*!< Window output default mode: Comparators output are + indicating each their own state. + To know window mode state: each comparator output + must be read, if "((COMPx exclusive or COMPy) == 1)" + then monitored signal is within comparators window.*/ +#define COMP_WINDOWOUTPUT_COMP1 (COMP_CSR_WINOUT) /*!< Window output synthesized on COMP1 output: + COMP1 output is no more indicating its own state, but + global window mode state (logical high means + monitored signal is within comparators window). + Note: impacts only comparator output signal level + (COMPx_OUT propagated to GPIO, EXTI lines, + timers, ...), does not impact output digital state + of comparator (COMPx_VALUE) always reflecting each + comparator output state.*/ +#define COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT \ + | COMP_WINDOWMODE_COMP2) /*!< Window output synthesized on COMP2 output: + COMP2 output is no more indicating its own state, but + global window mode state (logical high means + monitored signal is within comparators window). + Note: impacts only comparator output signal level + (COMPx_OUT propagated to GPIO, EXTI lines, + timers, ...), does not impact output digital state + of comparator (COMPx_VALUE) always reflecting each + comparator output state.*/ +#define COMP_WINDOWOUTPUT_BOTH (0x00000001UL) /*!< Window output synthesized on both comparators output + of pair of comparator selected (COMP1 and COMP2: + both comparators outputs are no more indicating their + own state, but global window mode state (logical high + means monitored signal is within comparators window). + This is a specific configuration (technically + possible but not relevant from application + point of view: + 2 comparators output used for the same signal level), + standard configuration for window mode is one of the + settings above. */ /** * @} */ +#endif /* COMP_WINDOW_MODE_SUPPORT */ /** @defgroup COMP_PowerMode COMP power mode * @{ @@ -181,9 +231,9 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /* Note: For the characteristics of comparator power modes */ /* (propagation delay and power consumption), */ /* refer to device datasheet. */ -#define COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< High Speed */ -#define COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< Medium Speed */ -#define COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0) /*!< Ultra-low power */ +#define COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< High Speed */ +#define COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< Medium Speed */ +#define COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0) /*!< Ultra-low power */ /** * @} */ @@ -194,6 +244,11 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer #define COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */ #define COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */ #define COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA2 for COMP1) */ +#if defined(COMP_CSR_INPSEL_2) +#define COMP_INPUT_PLUS_IO4 (COMP_CSR_INPSEL_1 | COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO4 (pin PB3 for COMP1) */ +#define COMP_INPUT_PLUS_IO5 (COMP_CSR_INPSEL_2) /*!< Comparator input plus connected to IO5 (pin PB4 for COMP1) */ +#define COMP_INPUT_PLUS_IO6 (COMP_CSR_INPSEL_2 | COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO6 (pin PB6 for COMP1) */ +#endif /* COMP_CSR_INPSEL_2 */ /** * @} */ @@ -201,14 +256,14 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /** @defgroup COMP_InputMinus COMP input minus (inverting input) * @{ */ -#define COMP_INPUT_MINUS_1_4VREFINT ((uint32_t)0x00000000 ) /*!< Comparator input minus connected to 1/4 VrefInt */ -#define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt */ -#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to 3/4 VrefInt */ -#define COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to VrefInt */ -#define COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */ -#define COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */ -#define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB7 for COMP2) */ -#define COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB3 for COMP2) */ +#define COMP_INPUT_MINUS_1_4VREFINT (0x00000000UL) /*!< Comparator input minus connected to 1/4 VrefInt */ +#define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt */ +#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to 3/4 VrefInt */ +#define COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to VrefInt */ +#define COMP_INPUT_MINUS_DAC1_CH1 ( COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */ +#define COMP_INPUT_MINUS_DAC1_CH2 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */ +#define COMP_INPUT_MINUS_IO1 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB7 for COMP2) */ +#define COMP_INPUT_MINUS_IO2 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB3 for COMP2) */ /** * @} */ @@ -216,34 +271,33 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /** @defgroup COMP_Hysteresis COMP hysteresis * @{ */ -#define COMP_HYSTERESIS_NONE ((uint32_t)0x00000000) /*!< No hysteresis */ -#define COMP_HYSTERESIS_LOW (COMP_CSR_HYST_0) /*!< Hysteresis level low */ -#define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1) /*!< Hysteresis level medium */ -#define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST ) /*!< Hysteresis level high */ +#define COMP_HYSTERESIS_NONE (0x00000000UL) /*!< No hysteresis */ +#define COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0) /*!< Hysteresis level low */ +#define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 ) /*!< Hysteresis level medium */ +#define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */ /** * @} */ -/** @defgroup COMP_OutputPolarity COMP Output Polarity +/** @defgroup COMP_OutputPolarity COMP output Polarity * @{ */ -#define COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */ -#define COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus) */ +#define COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */ +#define COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus) */ /** * @} */ - -/** @defgroup COMP_BlankingSrce COMP Blanking Source +/** @defgroup COMP_BlankingSrce COMP blanking source * @{ */ -#define COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000) /*!< No blanking source */ -#define COMP_BLANKINGSRC_TIM1_OC5 (COMP_CSR_BLANKSEL_0) /*!< TIM1 OC5 selected as blanking source for COMP1 */ -#define COMP_BLANKINGSRC_TIM2_OC3 (COMP_CSR_BLANKSEL_1) /*!< TIM2 OC3 selected as blanking source for COMP1 */ -#define COMP_BLANKINGSRC_TIM3_OC3 (COMP_CSR_BLANKSEL_2) /*!< TIM3 OC3 selected as blanking source for COMP1 */ -#define COMP_BLANKINGSRC_TIM3_OC4 (COMP_CSR_BLANKSEL_0) /*!< TIM3 OC4 selected as blanking source for COMP2 */ -#define COMP_BLANKINGSRC_TIM8_OC5 (COMP_CSR_BLANKSEL_1) /*!< TIM8 OC5 selected as blanking source for COMP2 */ -#define COMP_BLANKINGSRC_TIM15_OC1 (COMP_CSR_BLANKSEL_2) /*!< TIM15 OC1 selected as blanking source for COMP2 */ +#define COMP_BLANKINGSRC_NONE (0x00000000UL) /*!Instance->CSR, COMP_CSR_EN) +#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN) /** * @brief Disable the specified comparator. * @param __HANDLE__ COMP handle * @retval None */ -#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN) +#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN) /** * @brief Lock the specified comparator configuration. @@ -336,15 +390,14 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @param __HANDLE__ COMP handle * @retval None */ -#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) +#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) /** * @brief Check whether the specified comparator is locked. * @param __HANDLE__ COMP handle * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked */ -#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)\ - == COMP_CSR_LOCK) +#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK) /** * @} @@ -412,13 +465,19 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer #define __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP1) /** - * @brief Enable the COMP1 EXTI Line in event mode. + * @brief Generate a software interrupt on the COMP1 EXTI line. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1) + +/** + * @brief Enable the COMP1 EXTI line in event mode. * @retval None */ #define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP1) /** - * @brief Disable the COMP1 EXTI Line in event mode. + * @brief Disable the COMP1 EXTI line in event mode. * @retval None */ #define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP1) @@ -436,10 +495,10 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer #define __HAL_COMP_COMP1_EXTI_GET_FALLING_FLAG() READ_BIT(EXTI->FPR1, COMP_EXTI_LINE_COMP1) /** - * @brief Clear the COMP1 EXTI rasing flag. + * @brief Clear the COMP1 EXTI raising flag. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG() WRITE_REG(EXTI->RPR1, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR1, COMP_EXTI_LINE_COMP1) /** * @brief Clear the COMP1 EXTI falling flag. @@ -447,14 +506,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer */ #define __HAL_COMP_COMP1_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR1, COMP_EXTI_LINE_COMP1) - -/** - * @brief Generate a software interrupt on the COMP1 EXTI line. - * @retval None - */ -#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1) - - +#if defined(COMP2) /** * @brief Enable the COMP2 EXTI line rising edge trigger. * @retval None @@ -521,7 +573,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer #define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP2) /** - * @brief Check whether the COMP2 EXTI line rasing flag is set or not. + * @brief Check whether the COMP2 EXTI line raising flag is set or not. * @retval RESET or SET */ #define __HAL_COMP_COMP2_EXTI_GET_RISING_FLAG() READ_BIT(EXTI->RPR1, COMP_EXTI_LINE_COMP2) @@ -534,7 +586,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /** - * @brief Clear the the COMP2 EXTI rasing flag. + * @brief Clear the the COMP2 EXTI raising flag. * @retval None */ #define __HAL_COMP_COMP2_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR1, COMP_EXTI_LINE_COMP2) @@ -550,6 +602,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @retval None */ #define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP2) +#endif /* COMP2 */ /** * @} @@ -578,10 +631,13 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @{ */ #define COMP_EXTI_LINE_COMP1 (EXTI_IMR1_IM17) /*!< EXTI line 17 connected to COMP1 output */ +#if defined(COMP2) #define COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM18) /*!< EXTI line 18 connected to COMP2 output */ +#endif /* COMP2 */ /** * @} */ + /** @defgroup COMP_ExtiLine COMP EXTI Lines * @{ */ @@ -610,8 +666,12 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @param __INSTANCE__ specifies the COMP instance. * @retval value of @ref COMP_ExtiLine */ -#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \ - COMP_EXTI_LINE_COMP2) +#if defined(COMP2) +#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \ + : COMP_EXTI_LINE_COMP2) +#else +#define COMP_GET_EXTI_LINE(__INSTANCE__) COMP_EXTI_LINE_COMP1 +#endif /* COMP2 */ /** * @} */ @@ -619,23 +679,32 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /** @defgroup COMP_IS_COMP_Private_Definitions COMP private macros to check input parameters * @{ */ -#define IS_COMP_WINDOWMODE(__INSTANCE__, __WINMODE__) (((__WINMODE__) == COMP_WINDOWMODE_DISABLE) ||\ - ((__WINMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)||\ - ((__WINMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON)) +#define IS_COMP_WINDOWMODE(__INSTANCE__, __WINDOWMODE__) \ + (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \ + ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)|| \ + ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) ) #define IS_COMP_WINDOWOUTPUT(__WINDOWOUTPUT__) (((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_EACH_COMP) || \ ((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_COMP1) || \ ((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_COMP2) || \ - ((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_BOTH)) - -#define IS_COMP_POWERMODE(__POWERMODE__) (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED) || \ - ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) || \ - ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER)) + ((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_BOTH) ) +#define IS_COMP_POWERMODE(__POWERMODE__) (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED) || \ + ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) || \ + ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER) ) +#if defined(COMP_CSR_INPSEL_2) +#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \ + ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \ + ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3) || \ + ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO4) || \ + ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO5) || \ + ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO6)) +#else #define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \ ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \ ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3)) +#endif /* COMP_CSR_INPSEL_2 */ #define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) ||\ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) ||\ @@ -663,7 +732,6 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer ((__SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5) || \ ((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1)) - #define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \ ((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \ ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING) || \ @@ -725,7 +793,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp); * @{ */ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp); -uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp); /* Callback in interrupt mode */ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); /** @@ -736,8 +804,8 @@ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); /** @addtogroup COMP_Exported_Functions_Group4 * @{ */ -HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); -uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp); +HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp); /** * @} */ @@ -759,4 +827,3 @@ uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp); #endif #endif /* STM32U5xx_HAL_COMP_H */ - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cordic.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cordic.c index 043a7314351..48505355456 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cordic.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cordic.c @@ -10,6 +10,7 @@ * + Callback functions * + IRQ handler management * + Peripheral State functions + * ****************************************************************************** * @attention * @@ -21,7 +22,7 @@ * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** - * @verbatim + @verbatim ================================================================================ ##### How to use this driver ##### ================================================================================ @@ -89,9 +90,9 @@ The compilation define USE_HAL_CORDIC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Function @ref HAL_CORDIC_RegisterCallback() to register an interrupt callback. + Use Function HAL_CORDIC_RegisterCallback() to register an interrupt callback. - Function @ref HAL_CORDIC_RegisterCallback() allows to register following callbacks: + Function HAL_CORDIC_RegisterCallback() allows to register following callbacks: (+) ErrorCallback : Error Callback. (+) CalculateCpltCallback : Calculate complete Callback. (+) MspInitCallback : CORDIC MspInit. @@ -99,9 +100,9 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_CORDIC_UnRegisterCallback() to reset a callback to the default + Use function HAL_CORDIC_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_CORDIC_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_CORDIC_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) ErrorCallback : Error Callback. @@ -111,11 +112,11 @@ By default, after the HAL_CORDIC_Init() and when the state is HAL_CORDIC_STATE_RESET, all callbacks are set to the corresponding weak functions: - examples @ref HAL_CORDIC_ErrorCallback(), @ref HAL_CORDIC_CalculateCpltCallback(). + examples HAL_CORDIC_ErrorCallback(), HAL_CORDIC_CalculateCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the HAL_CORDIC_Init()/ @ref HAL_CORDIC_DeInit() only when + reset to the legacy weak function in the HAL_CORDIC_Init()/ HAL_CORDIC_DeInit() only when these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the HAL_CORDIC_Init()/ @ref HAL_CORDIC_DeInit() + if not, MspInit or MspDeInit are not null, the HAL_CORDIC_Init()/ HAL_CORDIC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in HAL_CORDIC_STATE_READY state only. @@ -123,7 +124,7 @@ in HAL_CORDIC_STATE_READY or HAL_CORDIC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_CORDIC_RegisterCallback() before calling @ref HAL_CORDIC_DeInit() + using HAL_CORDIC_RegisterCallback() before calling HAL_CORDIC_DeInit() or HAL_CORDIC_Init() function. When The compilation define USE_HAL_CORDIC_REGISTER_CALLBACKS is set to 0 or @@ -131,6 +132,7 @@ are set to the corresponding weak functions. @endverbatim + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -157,8 +159,8 @@ /** @defgroup CORDIC_Private_Functions CORDIC Private Functions * @{ */ -static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppInBuff); -static void CORDIC_ReadOutDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff); +static void CORDIC_WriteInDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, const int32_t **ppInBuff); +static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff); static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma); static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma); static void CORDIC_DMAError(DMA_HandleTypeDef *hdma); @@ -553,7 +555,7 @@ HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, H * contains the CORDIC configuration information. * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_ConfigTypeDef *sConfig) +HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, const CORDIC_ConfigTypeDef *sConfig) { HAL_StatusTypeDef status = HAL_OK; @@ -600,12 +602,12 @@ HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_Con * @param Timeout Specify Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout) { uint32_t tickstart; uint32_t index; - int32_t *p_tmp_in_buff = pInBuff; + const int32_t *p_tmp_in_buff = pInBuff; int32_t *p_tmp_out_buff = pOutBuff; /* Check parameters setting */ @@ -694,12 +696,12 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *p * @param Timeout Specify Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout) { uint32_t tickstart; uint32_t index; - int32_t *p_tmp_in_buff = pInBuff; + const int32_t *p_tmp_in_buff = pInBuff; int32_t *p_tmp_out_buff = pOutBuff; /* Check parameters setting */ @@ -787,10 +789,10 @@ HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t * @param NbCalc Number of CORDIC calculation to process. * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc) { - int32_t *tmp_pInBuff = pInBuff; + const int32_t *tmp_pInBuff = pInBuff; /* Check parameters setting */ if ((pInBuff == NULL) || (pOutBuff == NULL) || (NbCalc == 0U)) @@ -879,14 +881,11 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t * DMA transfer to and from the Peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t DMADirection) { - HAL_StatusTypeDef status; uint32_t sizeinbuff; uint32_t sizeoutbuff; - uint32_t inputaddr; - uint32_t outputaddr; /* Check the parameters */ assert_param(IS_CORDIC_DMA_DIRECTION(DMADirection)); @@ -963,42 +962,13 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_ This is necessary as the DMA handles the data at byte-level. */ sizeoutbuff = 4U * sizeoutbuff; - outputaddr = (uint32_t)pOutBuff; - /* Enable the DMA stream managing CORDIC output data read */ - - if ((hcordic->hdmaOut->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if ((hcordic->hdmaOut->LinkedListQueue != NULL) && (hcordic->hdmaOut->LinkedListQueue->Head != NULL)) - { - /* Enable the DMA channel */ - hcordic->hdmaOut->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = - sizeoutbuff; /* Set DMA data size */ - hcordic->hdmaOut->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = - (uint32_t)&hcordic->Instance->RDATA; /* Set DMA source address */ - hcordic->hdmaOut->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = - outputaddr; /* Set DMA destination address */ - - status = HAL_DMAEx_List_Start_IT(hcordic->hdmaOut); - } - else - { - /* Update the error code */ - hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA; - - /* Return error status */ - return HAL_ERROR; - } - } - else - { - status = HAL_DMA_Start_IT(hcordic->hdmaOut, (uint32_t)&hcordic->Instance->RDATA, outputaddr, sizeoutbuff); - } - - if (status != HAL_OK) + if (HAL_DMA_Start_IT(hcordic->hdmaOut, (uint32_t)&hcordic->Instance->RDATA, (uint32_t) pOutBuff, sizeoutbuff) + != HAL_OK) { /* Update the error code */ hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA; + /* Return error status */ return HAL_ERROR; } @@ -1030,38 +1000,9 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_ This is necessary as the DMA handles the data at byte-level. */ sizeinbuff = 4U * sizeinbuff; - inputaddr = (uint32_t)pInBuff; - /* Enable the DMA stream managing CORDIC input data write */ - if ((hcordic->hdmaIn->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if ((hcordic->hdmaIn->LinkedListQueue != NULL) && (hcordic->hdmaIn->LinkedListQueue->Head != NULL)) - { - /* Enable the DMA channel */ - hcordic->hdmaIn->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = - sizeinbuff; /* Set DMA data size */ - hcordic->hdmaIn->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = - inputaddr; /* Set DMA source address */ - hcordic->hdmaIn->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = - (uint32_t)&hcordic->Instance->WDATA; /* Set DMA destination address */ - - status = HAL_DMAEx_List_Start_IT(hcordic->hdmaIn); - } - else - { - /* Update the error code */ - hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA; - - /* Return error status */ - return HAL_ERROR; - } - } - else - { - status = HAL_DMA_Start_IT(hcordic->hdmaIn, inputaddr, (uint32_t)&hcordic->Instance->WDATA, sizeinbuff); - } - - if (status != HAL_OK) + if (HAL_DMA_Start_IT(hcordic->hdmaIn, (uint32_t) pInBuff, (uint32_t)&hcordic->Instance->WDATA, sizeinbuff) + != HAL_OK) { /* Update the error code */ hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA; @@ -1069,6 +1010,7 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_ /* Return error status */ return HAL_ERROR; } + /* Enable input data Write DMA request */ SET_BIT(hcordic->Instance->CSR, CORDIC_DMA_WEN); } @@ -1231,7 +1173,7 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic) * the configuration information for CORDIC module * @retval HAL state */ -HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic) +HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic) { /* Return CORDIC handle state */ return hcordic->State; @@ -1244,7 +1186,7 @@ HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic) * @note The returned error is a bit-map combination of possible errors * @retval Error bit-map */ -uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic) +uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic) { /* Return CORDIC error code */ return hcordic->ErrorCode; @@ -1269,7 +1211,7 @@ uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic) * @param ppInBuff Pointer to pointer to input buffer. * @retval none */ -static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppInBuff) +static void CORDIC_WriteInDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, const int32_t **ppInBuff) { /* First write of input data in the Write Data register */ WRITE_REG(hcordic->Instance->WDATA, (uint32_t) **ppInBuff); @@ -1295,7 +1237,7 @@ static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_ * @param ppOutBuff Pointer to pointer to output buffer. * @retval none */ -static void CORDIC_ReadOutDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff) +static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff) { /* First read of output data from the Read Data register */ **ppOutBuff = (int32_t)READ_REG(hcordic->Instance->RDATA); diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cordic.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cordic.h index a03db89c138..f4892386429 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cordic.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cordic.h @@ -64,7 +64,7 @@ typedef struct { CORDIC_TypeDef *Instance; /*!< Register base address */ - int32_t *pInBuff; /*!< Pointer to CORDIC input data buffer */ + const int32_t *pInBuff; /*!< Pointer to CORDIC input data buffer */ int32_t *pOutBuff; /*!< Pointer to CORDIC output data buffer */ @@ -546,14 +546,14 @@ HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, H */ #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_ConfigTypeDef *sConfig); -HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, const CORDIC_ConfigTypeDef *sConfig); +HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout); -HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout); -HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc); -HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t DMADirection); /** * @} @@ -582,8 +582,8 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic); * @{ */ /* Peripheral State functions *************************************************/ -HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic); -uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic); +HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic); +uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cortex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cortex.c index 76e529ba497..db256e97d2d 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cortex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cortex.c @@ -627,8 +627,8 @@ static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const } else { - MPUx->RBAR = 0U; MPUx->RLAR = 0U; + MPUx->RBAR = 0U; } } diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cortex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cortex.h index 0cbe97f04ad..a36e2c1b503 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cortex.h @@ -203,9 +203,9 @@ typedef struct /** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes * @{ */ -#define MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ -#define MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ -#define MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ +#define MPU_DEVICE_NGNRNE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ +#define MPU_DEVICE_NGNRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ +#define MPU_DEVICE_NGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ #define MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ #define MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_crc.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_crc.h index a92999a8e5d..1a9dac024fd 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_crc.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_crc.h @@ -119,15 +119,15 @@ typedef struct uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format. Can be either @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes - (8-bit data) + (8-bit data) @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of - half-words (16-bit data) + half-words (16-bit data) @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words - (32-bit data) + (32-bit data) Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error must occur if InputBufferFormat is not one of the three values listed - above */ + above */ } CRC_HandleTypeDef; /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_crc_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_crc_ex.c index 62bac9e8c24..061ab922354 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_crc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_crc_ex.c @@ -94,44 +94,53 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol /* Check the parameters */ assert_param(IS_CRC_POL_LENGTH(PolyLength)); - /* check polynomial definition vs polynomial size: - * polynomial length must be aligned with polynomial - * definition. HAL_ERROR is reported if Pol degree is - * larger than that indicated by PolyLength. - * Look for MSB position: msb will contain the degree of - * the second to the largest polynomial member. E.g., for - * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ - while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) + /* Ensure that the generating polynomial is odd */ + if ((Pol & (uint32_t)(0x1U)) == 0U) { + status = HAL_ERROR; } - - switch (PolyLength) + else { - case CRC_POLYLENGTH_7B: - if (msb >= HAL_CRC_LENGTH_7B) - { - status = HAL_ERROR; - } - break; - case CRC_POLYLENGTH_8B: - if (msb >= HAL_CRC_LENGTH_8B) - { - status = HAL_ERROR; - } - break; - case CRC_POLYLENGTH_16B: - if (msb >= HAL_CRC_LENGTH_16B) - { - status = HAL_ERROR; - } - break; - - case CRC_POLYLENGTH_32B: - /* no polynomial definition vs. polynomial length issue possible */ - break; - default: - status = HAL_ERROR; - break; + /* check polynomial definition vs polynomial size: + * polynomial length must be aligned with polynomial + * definition. HAL_ERROR is reported if Pol degree is + * larger than that indicated by PolyLength. + * Look for MSB position: msb will contain the degree of + * the second to the largest polynomial member. E.g., for + * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ + while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) + { + } + + switch (PolyLength) + { + + case CRC_POLYLENGTH_7B: + if (msb >= HAL_CRC_LENGTH_7B) + { + status = HAL_ERROR; + } + break; + case CRC_POLYLENGTH_8B: + if (msb >= HAL_CRC_LENGTH_8B) + { + status = HAL_ERROR; + } + break; + case CRC_POLYLENGTH_16B: + if (msb >= HAL_CRC_LENGTH_16B) + { + status = HAL_ERROR; + } + break; + + case CRC_POLYLENGTH_32B: + /* no polynomial definition vs. polynomial length issue possible */ + break; + default: + status = HAL_ERROR; + break; + } } if (status == HAL_OK) { diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cryp.c index 8c5b070a3f4..f8f601db69a 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cryp.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cryp.c @@ -81,7 +81,7 @@ the CRYP peripheral is configured and processes the buffer in input. At second call, no need to Initialize the CRYP, user have to get current configuration via HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set - new parametres, finally user can start encryption/decryption. + new parameters, finally user can start encryption/decryption. (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. @@ -190,7 +190,7 @@ (##) To perform message payload encryption or decryption AES is configured in CTR mode. (##) For authentication two phases are performed : - Header phase: peripheral processes the Additional Authenticated Data (AAD) first, then the cleartext message - only cleartext payload (not the ciphertext payload) is used and no outpout. + only cleartext payload (not the ciphertext payload) is used and no output. (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data. HAL_CRYPEx_AESCCM_GenerateAuthTAG API used in this phase to generate 4 words which correspond to the Tag. user should consider only part of this 4 words, if Tag length is less than 128 bits @@ -305,6 +305,7 @@ /** @addtogroup CRYP_Private_Defines * @{ */ +#define CRYP_GENERAL_TIMEOUT 82U #define CRYP_TIMEOUT_KEYPREPARATION 82U /* The latency of key preparation operation is 82 clock cycles.*/ #define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/ @@ -435,6 +436,7 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp); HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) { uint32_t cr_value; + uint32_t tickstart; /* Check the CRYP handle allocation */ if (hcryp == NULL) @@ -486,6 +488,21 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) } else { + /* SAES is initializing, fetching random number from the RNG */ + tickstart = HAL_GetTick(); + while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CRYP_GENERAL_TIMEOUT) + { + __HAL_CRYP_DISABLE(hcryp); + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + + } cr_value = (uint32_t)(hcryp->Init.KeyMode | hcryp->Init.DataType | hcryp->Init.KeySize | \ hcryp->Init.Algorithm | hcryp->Init.KeySelect | hcryp->Init.KeyProtection); /* Set the key size, data type, algorithm, Key selection and key protection */ @@ -2314,6 +2331,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti else /*SAES*/ { /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_NORMAL); MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); /* we should re-write Key, in the case where we change key after first operation*/ @@ -4195,6 +4213,12 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) uint32_t npblb; uint32_t mode; uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + uint32_t headersize_in_bytes; + uint32_t tmp; + uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)) @@ -4288,7 +4312,16 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); - if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/ + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } + + if (headersize_in_bytes == 0U) /* Header phase is skipped */ { /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -4370,26 +4403,66 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } - else if ((hcryp->Init.HeaderSize) < 4U) /*HeaderSize < 4 */ + /* Enter header data */ + /* Check first whether header length is small enough to enter the full header in one shot */ + else if (headersize_in_bytes <= 16U) { /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++) + for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++) { hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; } - while (loopcounter < 4U) + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) { - /* pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0x0U; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + hcryp->CrypHeaderCount++; loopcounter++; + /* Pad the data with zeros to have a complete block */ + + while (loopcounter < 4U) + { + /* pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } else { - /* Write the input block in the IN FIFO */ + /* Write the first input header block in the Input FIFO, + the following header data will be fed after interrupt occurrence */ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); @@ -4398,7 +4471,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypHeaderCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; - } + }/* if (hcryp->Init.HeaderSize == 0U) */ /* Header phase is skipped*/ } /* end of if (dokeyivconfig == 1U) */ else /* Key and IV have already been configured, @@ -4473,6 +4546,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cryp_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cryp_ex.c index 4a82064aeab..7699b8a3f2b 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cryp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cryp_ex.c @@ -382,6 +382,7 @@ HAL_StatusTypeDef HAL_CRYPEx_WrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInput HAL_StatusTypeDef HAL_CRYPEx_UnwrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint32_t Timeout) { HAL_StatusTypeDef status; + uint32_t tickstart; if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -399,7 +400,25 @@ HAL_StatusTypeDef HAL_CRYPEx_UnwrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInp __HAL_CRYP_DISABLE(hcryp); /* Set the operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_WRAPPED); + MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KEYSEL, CRYP_KEYMODE_WRAPPED | CRYP_KEYSEL_HW); + + /* Wait for Valid KEY flag to set */ + tickstart = HAL_GetTick(); + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_KEYVALID)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } status = CRYPEx_KeyDecrypt(hcryp, Timeout); } @@ -417,14 +436,14 @@ HAL_StatusTypeDef HAL_CRYPEx_UnwrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInp * @} */ -/** @defgroup CRYPEx_Exported_Functions_Group3 Encrypt/Decrypt Shared key functions - * @brief Encrypt/Decrypt Shared key functions. +/** @defgroup CRYPEx_Exported_Functions_Group3 Encrypt and Decrypt Shared key functions + * @brief Encrypt and Decrypt Shared key functions. * @verbatim ============================================================================== - ##### Encrypt/Decrypt Shared key functions ##### + ##### Encrypt and Decrypt Shared key functions ##### ============================================================================== - [..] This section provides API allowing to Encrypt/Decrypt Shared key + [..] This section provides API allowing to Encrypt and Decrypt Shared key @endverbatim * @{ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cryp_ex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cryp_ex.h index 3cbd5f592e1..01bac232c97 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cryp_ex.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_cryp_ex.h @@ -68,7 +68,7 @@ HAL_StatusTypeDef HAL_CRYPEx_WrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInput * @} */ -/** @addtogroup CRYPEx_Exported_Functions_Group3 Encrypt/Decrypt Shared key functions +/** @addtogroup CRYPEx_Exported_Functions_Group3 Encrypt and Decrypt Shared key functions * @{ */ HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *pKey, uint32_t *pOutput, uint32_t ID, diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dac.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dac.c index d603ab6e441..c6e9ff3c754 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dac.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dac.c @@ -11,6 +11,17 @@ * + Peripheral State and Errors functions * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### DAC Peripheral features ##### @@ -229,7 +240,7 @@ The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback, + Use Functions HAL_DAC_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. @@ -244,8 +255,8 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default + weak (overridden) function. It allows to reset following callbacks: (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. @@ -259,12 +270,12 @@ (+) All Callbacks This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init - and @ref HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit + reset to the legacy weak (overridden) functions in the HAL_DAC_Init + and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -272,12 +283,12 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit - or @ref HAL_DAC_Init function. + using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit + or HAL_DAC_Init function. When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. *** DAC HAL driver macros list *** ============================================= @@ -293,16 +304,6 @@ (@) You can refer to the DAC HAL driver header file for more useful macros @endverbatim - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * ****************************************************************************** */ @@ -532,6 +533,7 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) { + __IO uint32_t wait_loop_index; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -544,7 +546,14 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); /* Ensure minimum wait before using peripheral after enabling it */ - HAL_Delay(1); + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed 32 */ + /* bits register capacity and handle low frequency. */ + wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } if (Channel == DAC_CHANNEL_1) { @@ -594,8 +603,6 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, Channel); - /* Ensure minimum wait before enabling peripheral after disabling it */ - HAL_Delay(1); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -621,13 +628,14 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, uint32_t Alignment) { HAL_StatusTypeDef status; uint32_t tmpreg; uint32_t LengthInBytes; DMA_NodeConfTypeDef node_conf; + __IO uint32_t wait_loop_index; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -703,8 +711,6 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u } } - - /* Enable the DMA channel */ if (Channel == DAC_CHANNEL_1) { /* Enable the DAC DMA underrun interrupt */ @@ -866,7 +872,15 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); /* Ensure minimum wait before using peripheral after enabling it */ - HAL_Delay(1); + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } } else { @@ -897,8 +911,6 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, Channel); - /* Ensure minimum wait before enabling peripheral after disabling it */ - HAL_Delay(1); /* Disable the DMA channel */ @@ -939,10 +951,13 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) */ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) { - if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1)) + uint32_t itsource = hdac->Instance->CR; + uint32_t itflag = hdac->Instance->SR; + + if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1) { /* Check underrun flag of DAC channel 1 */ - if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) + if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1) { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; @@ -954,7 +969,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1); /* Disable the selected DAC channel1 DMA request */ - CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); + __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1); /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) @@ -966,10 +981,10 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) } - if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2)) + if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2) { /* Check underrun flag of DAC channel 2 */ - if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2)) + if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2) { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; @@ -981,7 +996,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2); /* Disable the selected DAC channel2 DMA request */ - CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); + __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2); /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) @@ -1135,22 +1150,25 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval The selected DAC channel data output value. */ -uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel) +uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel) { + uint32_t result; + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); - /* Returns the DAC channel data output register value */ if (Channel == DAC_CHANNEL_1) { - return hdac->Instance->DOR1; + result = hdac->Instance->DOR1; } else { - return hdac->Instance->DOR2; + result = hdac->Instance->DOR2; } + /* Returns the DAC channel data output register value */ + return result; } /** @@ -1177,8 +1195,10 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel) * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, + const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpreg1; uint32_t tmpreg2; uint32_t tickstart; @@ -1240,7 +1260,6 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf } } } - HAL_Delay(1); hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; } @@ -1265,7 +1284,6 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf } } } - HAL_Delay(1U); hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; } @@ -1303,6 +1321,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf /* Clear DAC_MCR_MODEx bits */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ + + if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL) { connectOnChip = 0x00000000UL; @@ -1383,7 +1403,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf __HAL_UNLOCK(hdac); /* Return function status */ - return HAL_OK; + return status; } /** @@ -1412,7 +1432,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf * the configuration information for the specified DAC. * @retval HAL state */ -HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac) +HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac) { /* Return DAC handle state */ return hdac->State; @@ -1425,7 +1445,7 @@ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac) * the configuration information for the specified DAC. * @retval DAC Error Code */ -uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) +uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac) { return hdac->ErrorCode; } @@ -1448,7 +1468,9 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /** * @brief Register a User DAC Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (overridden) predefined callback + * @note The HAL_DAC_RegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to register + * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID * @param hdac DAC handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -1479,9 +1501,6 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hdac); - if (hdac->State == HAL_DAC_STATE_READY) { switch (CallbackID) @@ -1552,14 +1571,14 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hdac); return status; } /** * @brief Unregister a User DAC Callback - * DAC Callback is redirected to the weak (surcharged) predefined callback + * DAC Callback is redirected to the weak (overridden) predefined callback + * @note The HAL_DAC_UnRegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to un-register + * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID * @param hdac DAC handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -1580,9 +1599,6 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hdac); - if (hdac->State == HAL_DAC_STATE_READY) { switch (CallbackID) @@ -1667,8 +1683,6 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hdac); return status; } #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ @@ -1754,7 +1768,6 @@ void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) #endif /* DAC1 */ #endif /* HAL_DAC_MODULE_ENABLED */ - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dac.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dac.h index 20eb3c35e83..cb23c4d9c39 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dac.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dac.h @@ -122,7 +122,9 @@ typedef struct This parameter can be a value of @ref DAC_HighFrequency */ uint32_t DAC_AutonomousMode; /*!< Specifies whether the autonomous mode state - This parameter can be a value of @ref DACx_Autonomous_mode */ + This parameter can be a value of @ref DAC_AutonomousMode + Note: HAL_DACEx_SetConfigAutonomousMode() API allows to select and update + the autonomous mode state afterwards */ FunctionalState DAC_DMADoubleDataMode; /*!< Specifies if DMA double data mode should be enabled or not for the selected channel. This parameter can be ENABLE or DISABLE */ @@ -139,7 +141,7 @@ typedef struct uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of @ref DAC_output_buffer */ - uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral . + uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral. This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */ uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode @@ -218,8 +220,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); #define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM3 OUT TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_LPTIM1_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 CH1 selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_LPTIM3_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM3 CH1 selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ /** @@ -315,6 +317,27 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** * @} */ +/** @defgroup DAC_AutonomousMode DAC Autonomous Mode + * @brief DAC Autonomous mode + * @{ + */ +#define DAC_AUTONOMOUS_MODE_DISABLE 0x00000000U /*!< Autonomous mode disable */ +#define DAC_AUTONOMOUS_MODE_ENABLE DAC_AUTOCR_AUTOMODE /*!< Autonomous mode enable */ +/** + * @} + */ + +/** @defgroup DAC_Trigger_Stop_mode DAC Trigger Stop Mode + * @brief DAC Trigger stop mode + * @{ + */ +#define DAC_TRIGGER_STOP_LPTIM1_CH1 DAC_TRIGGER_LPTIM1_CH1 /*!< LPTIM1 output selected as DAC trigger in stop mode */ +#define DAC_TRIGGER_STOP_LPTIM3_CH1 DAC_TRIGGER_LPTIM3_CH1 /*!< LPTIM3 output selected as DAC trigger in stop mode */ +#define DAC_TRIGGER_STOP_EXT_IT9 DAC_TRIGGER_EXT_IT9 /*!< EXTI line 9 selected as DAC trigger in stop mode */ +/** + * @} + */ + /** @defgroup DAC_HighFrequency DAC high frequency interface mode * @{ */ @@ -331,6 +354,20 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @} */ +/* Delay for DAC channel voltage settling time from DAC channel startup */ +/* (transition from disable to enable). */ +/* Note: DAC channel startup time depends on board application environment: */ +/* impedance connected to DAC channel output. */ +/* The delay below is specified under conditions: */ +/* - voltage maximum transition (lowest to highest value) */ +/* - until voltage reaches final value +-1LSB */ +/* - DAC channel output buffer enabled */ +/* - load impedance of 5kOhm (min), 50pF (max) */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tWAKEUP"). */ +/* Unit: us */ +#define DAC_DELAY_STARTUP_US (15UL) /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ + /* Exported macro ------------------------------------------------------------*/ /** @defgroup DAC_Exported_Macros DAC Exported Macros @@ -495,7 +532,7 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac); /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, uint32_t Alignment); HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac); @@ -521,8 +558,9 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DA * @{ */ /* Peripheral Control functions ***********************************************/ -uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); +uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, + const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); /** * @} */ @@ -531,8 +569,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac); -uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); +HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac); +uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dac_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dac_ex.c index d027eb9dbdc..217ddf3e2da 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dac_ex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dac_ex.c @@ -7,12 +7,22 @@ * functionalities of the DAC peripheral. * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] - *** Dual mode IO operation *** ============================== [..] @@ -34,7 +44,6 @@ Use HAL_DACEx_DualGetValue() to get digital data to be converted and use HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2. - *** Signal generation operation *** =================================== [..] @@ -55,16 +64,6 @@ (+) Use HAL_DACx_ClearConfigAutonomousMode() to clear the configuration of the autonomous mode @endverbatim - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * ****************************************************************************** */ @@ -87,6 +86,16 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ + +/* Delay for DAC minimum trimming time. */ +/* Note: minimum time needed between two calibration steps */ +/* The delay below is specified under conditions: */ +/* - DAC channel output buffer enabled */ +/* Literal set to maximum value (refer to device datasheet, */ +/* electrical characteristics, parameter "tTRIM"). */ +/* Unit: us */ +#define DAC_DELAY_TRIM_US (50UL) /*!< Delay for DAC minimum trimming time */ + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -125,6 +134,7 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac) { uint32_t tmp_swtrig = 0UL; + __IO uint32_t wait_loop_index; /* Process locked */ @@ -137,7 +147,15 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac) __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1); __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2); /* Ensure minimum wait before using peripheral after enabling it */ - HAL_Delay(1); + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) @@ -173,8 +191,6 @@ HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac) /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1); __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2); - /* Ensure minimum wait before enabling peripheral after disabling it */ - HAL_Delay(1); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -200,11 +216,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac) * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @retval HAL status */ -HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, - uint32_t Alignment) +HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, + const uint32_t *pData, uint32_t Length, uint32_t Alignment) { HAL_StatusTypeDef status; - uint32_t tmpreg; + uint32_t tmpreg = 0UL; + __IO uint32_t wait_loop_index; uint32_t LengthInBytes; /* Check the parameters */ @@ -256,10 +273,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Chan /* Get DHR12L1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12LD; break; - default: /* case DAC_ALIGN_8B_R */ + case DAC_ALIGN_8B_R: /* Get DHR8R1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR8RD; break; + default: + break; } /* Enable the DMA channel */ @@ -347,7 +366,15 @@ HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Chan __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1); __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2); /* Ensure minimum wait before using peripheral after enabling it */ - HAL_Delay(1); + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } } else { @@ -379,8 +406,6 @@ HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Chann /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1); __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2); - /* Ensure minimum wait before enabling peripheral after disabling it */ - HAL_Delay(1); /* Disable the DMA channel */ @@ -650,6 +675,7 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo __IO uint32_t tmp; uint32_t trimmingvalue; uint32_t delta; + __IO uint32_t wait_loop_index; /* store/restore channel configuration structure purpose */ uint32_t oldmodeconfiguration; @@ -710,9 +736,15 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo /* Set candidate trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); - /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ - /* i.e. minimum time needed between two calibration steps */ - HAL_Delay(1); + /* Wait minimum time needed between two calibration steps (OTRIM) */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */ + /* 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) { @@ -732,9 +764,15 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo /* Set candidate trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); - /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ - /* i.e. minimum time needed between two calibration steps */ - HAL_Delay(1U); + /* Wait minimum time needed between two calibration steps (OTRIM) */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */ + /* 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL) { @@ -815,7 +853,7 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_Channel * @retval Trimming value : range: 0->31 * */ -uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel) +uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel) { /* Check the parameter */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -849,7 +887,7 @@ uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel) * the configuration information for the specified DAC. * @retval The selected DAC channel data output value. */ -uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac) +uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac) { uint32_t tmp = 0UL; @@ -873,7 +911,8 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac) * @param sConfig pointer to Autonomous mode structure parameters. * @retval HAL status */ -HAL_StatusTypeDef HAL_DACEx_SetConfigAutonomousMode(DAC_HandleTypeDef *hdac, DAC_AutonomousModeConfTypeDef *sConfig) +HAL_StatusTypeDef HAL_DACEx_SetConfigAutonomousMode(DAC_HandleTypeDef *hdac, + const DAC_AutonomousModeConfTypeDef *sConfig) { assert_param(IS_DAC_AUTONOMOUS(sConfig->AutonomousModeState)); @@ -911,7 +950,8 @@ HAL_StatusTypeDef HAL_DACEx_SetConfigAutonomousMode(DAC_HandleTypeDef *hdac, DAC * @param sConfig pointer to Autonomous mode structure parameters. * @retval HAL status */ -HAL_StatusTypeDef HAL_DACEx_GetConfigAutonomousMode(DAC_HandleTypeDef *hdac, DAC_AutonomousModeConfTypeDef *sConfig) +HAL_StatusTypeDef HAL_DACEx_GetConfigAutonomousMode(const DAC_HandleTypeDef *hdac, + DAC_AutonomousModeConfTypeDef *sConfig) { /* Fill Autonomous structure parameter */ sConfig->AutonomousModeState = READ_BIT(hdac->Instance->AUTOCR, DAC_AUTOCR_AUTOMODE); diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dac_ex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dac_ex.h index 0c978df06f0..d9240a1e349 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dac_ex.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dac_ex.h @@ -45,7 +45,7 @@ extern "C" { typedef struct { uint32_t AutonomousModeState; /*!< Specifies the autonomous mode state. - This parameter can be a value of @ref DACx_Autonomous_mode */ + This parameter can be a value of @ref DAC_AutonomousMode */ } DAC_AutonomousModeConfTypeDef; @@ -91,26 +91,6 @@ typedef struct * @} */ -/** @defgroup DACx_Autonomous_mode DACx Autonomous Mode - * @brief DAC Autonomous mode - * @{ - */ -#define DAC_AUTONOMOUS_MODE_DISABLE 0x00000000U /*!< Autonomous mode disable */ -#define DAC_AUTONOMOUS_MODE_ENABLE DAC_AUTOCR_AUTOMODE /*!< Autonomous mode enable */ -/** - * @} - */ - -/** @defgroup DACx_Trigger_Stop_mode DACx Trigger Stop Mode - * @brief DAC Trigger stop mode - * @{ - */ -#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_LPTIM1_OUT /*!< LPTIM1 output selected as DAC trigger in stop mode */ -#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_LPTIM3_OUT /*!< LPTIM3 output selected as DAC trigger in stop mode */ -#define DAC_TRIGGER_STOP_EXT_IT9 DAC_TRIGGER_EXT_IT9 /*!< EXTI line 9 selected as DAC trigger in stop mode */ -/** - * @} - */ /** * @} @@ -133,11 +113,11 @@ typedef struct ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \ - ((TRIGGER) == DAC_TRIGGER_LPTIM3_OUT) || \ + ((TRIGGER) == DAC_TRIGGER_LPTIM1_CH1) || \ + ((TRIGGER) == DAC_TRIGGER_LPTIM3_CH1) || \ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ - ((TRIGGER) == DAC_TRIGGER_STOP_LPTIM1_OUT) || \ - ((TRIGGER) == DAC_TRIGGER_STOP_LPTIM3_OUT) || \ + ((TRIGGER) == DAC_TRIGGER_STOP_LPTIM1_CH1) || \ + ((TRIGGER) == DAC_TRIGGER_STOP_LPTIM3_CH1) || \ ((TRIGGER) == DAC_TRIGGER_STOP_EXT_IT9) || \ ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) @@ -212,11 +192,11 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac); HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac); -HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, - uint32_t Alignment); +HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, + const uint32_t *pData, uint32_t Length, uint32_t Alignment); HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); -uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac); +uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac); void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac); void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac); @@ -236,11 +216,13 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac); HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue); -uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel); +uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel); /* Autonomous Mode Control functions **********************************************/ -HAL_StatusTypeDef HAL_DACEx_SetConfigAutonomousMode(DAC_HandleTypeDef *hdac, DAC_AutonomousModeConfTypeDef *sConfig); -HAL_StatusTypeDef HAL_DACEx_GetConfigAutonomousMode(DAC_HandleTypeDef *hdac, DAC_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_DACEx_SetConfigAutonomousMode(DAC_HandleTypeDef *hdac, + const DAC_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_DACEx_GetConfigAutonomousMode(const DAC_HandleTypeDef *hdac, + DAC_AutonomousModeConfTypeDef *sConfig); HAL_StatusTypeDef HAL_DACEx_ClearConfigAutonomousMode(DAC_HandleTypeDef *hdac); /** diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dcache.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dcache.c index fae4473f646..6a74c939a35 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dcache.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dcache.c @@ -25,12 +25,12 @@ =============================================================================== [..] (#) Configure and enable the MPU to override default config if needed, please refers - to ARM manual for default memory attribute. Then enable DCache. + to ARM manual for default memory attribute. Then enable DCACHE. [..] (+) Use HAL_DCACHE_Invalidate() to invalidate the full cache content: (++) Cache content is lost, and reloaded when needed. - (++) Used for complete invalidate of the dcache in case. + (++) Used for complete invalidate of the DCACHE in case. (++) Blocking call until operation is done. (+) Use HAL_DCACHE_InvalidateByAddr() to invalidate cache content for specific range: (++) Cache content for specific range is lost, and reloaded when needed. @@ -51,14 +51,14 @@ [..] (+) Configure the DCACHE interrupt priority using HAL_NVIC_SetPriority() (+) Enable the DCACHE IRQ handler using HAL_NVIC_EnableIRQ() - (+) Override weak definition for following callback (if needed): + (+) Override weak definition for following callbacks (if needed): (++)HAL_DCACHE_CleanAndInvalidateByAddrCallback() (++)HAL_DCACHE_InvalidateCompleteCallback() (++)HAL_DCACHE_InvalidateByAddrCallback() (++)HAL_DCACHE_CleanByAddrCallback() (++)HAL_DCACHE_ErrorCallback() - (+) Use HAL_DCACHE__IT() to start a DCache operation with IT enabled. - (+) Use HAL_DCACHE_IRQHandler() called under DCACHE_IRQHandler() Interrupt subroutine + (+) Use HAL_DCACHE__IT() to start a DCACHE operation with IT enabled. + (+) Use HAL_DCACHE_IRQHandler() called under DCACHEx_IRQHandler() Interrupt subroutine [..] Use HAL_DCACHE_GetState() function to return the DCACHE state and HAL_DCACHE_GetError() in case of error detection. @@ -66,7 +66,7 @@ *** DCACHE HAL driver macros list *** ============================================= [..] - Below the list of most used macros in DCACHE HAL driver. + Below the list of macros defined in the DCACHE HAL driver. (+) __HAL_DCACHE_ENABLE_IT : Enable DCACHE interrupts. (+) __HAL_DCACHE_DISABLE_IT : Disable DCACHE interrupts. @@ -94,6 +94,8 @@ * @brief HAL DCACHE module driver * @{ */ + +#if defined (DCACHE1) || defined (DCACHE2) #ifdef HAL_DCACHE_MODULE_ENABLED /* Private define ------------------------------------------------------------*/ @@ -142,13 +144,12 @@ static HAL_StatusTypeDef DCACHE_CommandByAddr(DCACHE_HandleTypeDef *hdcache, uin const uint32_t *const pAddr, uint32_t dSize, uint32_t mode); /* Exported functions --------------------------------------------------------*/ -/** @defgroup DCACHE_Exported_Functions DCACHE Exported Functions +/** @addtogroup DCACHE_Exported_Functions DCACHE Exported Functions * @{ */ -/** @defgroup DCACHE_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * +/** @addtogroup DCACHE_Exported_Functions_Group1 + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -179,7 +180,7 @@ static HAL_StatusTypeDef DCACHE_CommandByAddr(DCACHE_HandleTypeDef *hdcache, uin */ HAL_StatusTypeDef HAL_DCACHE_Init(DCACHE_HandleTypeDef *hdcache) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check the DCACHE handle allocation */ if (hdcache == NULL) @@ -209,28 +210,18 @@ HAL_StatusTypeDef HAL_DCACHE_Init(DCACHE_HandleTypeDef *hdcache) hdcache->MspInitCallback(hdcache); } - hdcache->State = HAL_DCACHE_STATE_BUSY; - - /* Disable the selected DCACHE peripheral */ - if (HAL_DCACHE_Disable(hdcache) != HAL_OK) - { - /* Return timeout status */ - status = HAL_TIMEOUT; - } - else - { - /* Set requested read burst type */ - MODIFY_REG(hdcache->Instance->CR, DCACHE_CR_HBURST, hdcache->Init.ReadBurstType); + /* Init the error code */ + hdcache->ErrorCode = HAL_DCACHE_ERROR_NONE; - /* Enable the selected DCACHE peripheral */ - if (HAL_DCACHE_Enable(hdcache) != HAL_OK) - { - /* Return error status */ - status = HAL_ERROR; - } - } + /* Init the DCACHE handle state */ hdcache->State = HAL_DCACHE_STATE_READY; + /* Set requested read burst type */ + MODIFY_REG(hdcache->Instance->CR, DCACHE_CR_HBURST, hdcache->Init.ReadBurstType); + + /* Enable the selected DCACHE peripheral */ + status = HAL_DCACHE_Enable(hdcache); + return status; } @@ -242,7 +233,7 @@ HAL_StatusTypeDef HAL_DCACHE_Init(DCACHE_HandleTypeDef *hdcache) */ HAL_StatusTypeDef HAL_DCACHE_DeInit(DCACHE_HandleTypeDef *hdcache) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check the dcache handle allocation */ if (hdcache == NULL) @@ -253,43 +244,32 @@ HAL_StatusTypeDef HAL_DCACHE_DeInit(DCACHE_HandleTypeDef *hdcache) /* Check the parameters */ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance)); - /* Before the lunch of the disable operation check first whether or not DCACHE clock is enabled */ - if (hdcache->State != HAL_DCACHE_STATE_RESET) - { - /* Disable cache with reset value */ - if (HAL_DCACHE_Disable(hdcache) != HAL_OK) - { - /* Update error code */ - hdcache->ErrorCode = HAL_DCACHE_ERROR_TIMEOUT; - - /* Change the DCACHE state */ - hdcache->State = HAL_DCACHE_STATE_ERROR; - - /* Return error status */ - status = HAL_ERROR; - } + /* Update the error code */ + hdcache->ErrorCode = HAL_DCACHE_ERROR_NONE; - /* reset monitor values */ - (void)HAL_DCACHE_Monitor_Reset(hdcache, DCACHE_MONITOR_ALL); + /* Return to the reset state */ + hdcache->State = HAL_DCACHE_STATE_RESET; - /* Reset all remaining bit */ - WRITE_REG(hdcache->Instance->CR, 0U); - WRITE_REG(hdcache->Instance->CMDRSADDRR, 0U); - WRITE_REG(hdcache->Instance->CMDREADDRR, 0U); - WRITE_REG(hdcache->Instance->FCR, DCACHE_FCR_CCMDENDF | DCACHE_FCR_CERRF | DCACHE_FCR_CBSYENDF); + /* Disable cache */ + status = HAL_DCACHE_Disable(hdcache); - if (hdcache->MspDeInitCallback == NULL) - { - hdcache->MspDeInitCallback = HAL_DCACHE_MspDeInit; - } + /* reset monitor values */ + (void)HAL_DCACHE_Monitor_Reset(hdcache, DCACHE_MONITOR_ALL); - /* DeInit the low level hardware */ - hdcache->MspDeInitCallback(hdcache); + /* Reset all remaining bit */ + WRITE_REG(hdcache->Instance->CR, 0U); + WRITE_REG(hdcache->Instance->CMDRSADDRR, 0U); + WRITE_REG(hdcache->Instance->CMDREADDRR, 0U); + WRITE_REG(hdcache->Instance->FCR, DCACHE_FCR_CCMDENDF | DCACHE_FCR_CERRF | DCACHE_FCR_CBSYENDF); - /* Return to the reset state */ - hdcache->State = HAL_DCACHE_STATE_RESET; + if (hdcache->MspDeInitCallback == NULL) + { + hdcache->MspDeInitCallback = HAL_DCACHE_MspDeInit; } + /* DeInitialize the low level hardware */ + hdcache->MspDeInitCallback(hdcache); + return status; } @@ -324,9 +304,11 @@ __weak void HAL_DCACHE_MspDeInit(DCACHE_HandleTypeDef *hdcache) the HAL_DCACHE_MspDeInit can be implemented in the user file */ } +/** + * @} + */ -/** @defgroup DCACHE_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions +/** @addtogroup DCACHE_Exported_Functions_Group2 * @verbatim ============================================================================== @@ -344,6 +326,13 @@ __weak void HAL_DCACHE_MspDeInit(DCACHE_HandleTypeDef *hdcache) (+) Clean the Data cache by Addr with interrupt. (+) Invalidate the Data cache by Addr with interrupt. (+) Clean and Invalidate the Data cache by Addr with interrupt. + (+) Start the Data Cache performance monitoring. + (+) Stop the Data Cache performance monitoring. + (+) Reset the Data Cache performance monitoring values. + (+) Get the Data Cache performance Read Hit monitoring value. + (+) Get the Data Cache performance Read Miss monitoring value. + (+) Get the Data Cache performance Write Hit monitoring value. + (+) Get the Data Cache performance Write Miss monitoring value. @endverbatim * @{ */ @@ -370,16 +359,18 @@ HAL_StatusTypeDef HAL_DCACHE_Enable(DCACHE_HandleTypeDef *hdcache) /* Check no ongoing operation */ if (READ_BIT(hdcache->Instance->SR, (DCACHE_SR_BUSYF | DCACHE_SR_BUSYCMDF)) != 0U) { - /* Return error status */ - status = HAL_ERROR; + /* Return busy status */ + status = HAL_BUSY; } else { + /* Update the error code */ + hdcache->ErrorCode = HAL_DCACHE_ERROR_NONE; + + /* Enable the selected DCACHE peripheral */ SET_BIT(hdcache->Instance->CR, DCACHE_CR_EN); } - hdcache->State = HAL_DCACHE_STATE_READY; - return status; } @@ -395,41 +386,63 @@ HAL_StatusTypeDef HAL_DCACHE_Disable(DCACHE_HandleTypeDef *hdcache) uint32_t tickstart; + /* Check the dcache handle allocation */ + if (hdcache == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance)); - /* Change DCACHE state */ - hdcache->State = HAL_DCACHE_STATE_BUSY; + /* Check DCACHE handle status */ + if (HAL_DCACHE_IsEnabled(hdcache) != 0U) + { + /* Update the error code */ + hdcache->ErrorCode = HAL_DCACHE_ERROR_NONE; - /* Get timeout */ - tickstart = HAL_GetTick(); + /* Change DCACHE handle state */ + hdcache->State = HAL_DCACHE_STATE_READY; - /* Before disable check first whether or not DCACHE clock is enabled */ - if (hdcache->State != HAL_DCACHE_STATE_RESET) - { + /* Disable the selected DCACHE peripheral */ CLEAR_BIT(hdcache->Instance->CR, DCACHE_CR_EN); + /* Get timeout */ + tickstart = HAL_GetTick(); + /* Wait for end of data cache disabling */ while (READ_BIT(hdcache->Instance->SR, (DCACHE_SR_BUSYF | DCACHE_SR_BUSYCMDF)) != 0U) { if ((HAL_GetTick() - tickstart) > DCACHE_DISABLE_TIMEOUT_VALUE) { - /* Update error code */ - hdcache->ErrorCode = HAL_DCACHE_ERROR_TIMEOUT; + if (READ_BIT(hdcache->Instance->SR, (DCACHE_SR_BUSYF | DCACHE_SR_BUSYCMDF)) != 0U) + { + /* Update error code */ + hdcache->ErrorCode = HAL_DCACHE_ERROR_TIMEOUT; - /* Change the DCACHE state */ - hdcache->State = HAL_DCACHE_STATE_ERROR; + /* Change the DCACHE handle state */ + hdcache->State = HAL_DCACHE_STATE_READY; - /* Return error status */ - status = HAL_ERROR; + /* Return error status */ + status = HAL_ERROR; + break; + } } } - - hdcache->State = HAL_DCACHE_STATE_RESET; } return status; } +/** + * @brief Check whether the Data Cache is enabled or not. + * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains + * the configuration information for the specified DCACHEx peripheral. + * @retval Status (0: disabled, 1: enabled) + */ +uint32_t HAL_DCACHE_IsEnabled(const DCACHE_HandleTypeDef *hdcache) +{ + return ((READ_BIT(hdcache->Instance->CR, DCACHE_CR_EN) != 0U) ? 1UL : 0UL); +} /** * @brief Set Read Burst Type. @@ -453,21 +466,17 @@ HAL_StatusTypeDef HAL_DCACHE_SetReadBurstType(DCACHE_HandleTypeDef *hdcache, uin assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance)); assert_param(IS_DCACHE_READ_BURST_TYPE(ReadBurstType)); - /* check DCACHE state */ - if (hdcache->State == HAL_DCACHE_STATE_RESET) + /* check DCACHE status */ + if (HAL_DCACHE_IsEnabled(hdcache) == 0U) { /* Set requested read burst type */ - if (ReadBurstType == DCACHE_READ_BURST_WRAP) - { - CLEAR_BIT(hdcache->Instance->CR, DCACHE_CR_HBURST); - } - else - { - SET_BIT(hdcache->Instance->CR, DCACHE_CR_HBURST); - } + MODIFY_REG(hdcache->Instance->CR, DCACHE_CR_HBURST, ReadBurstType); } else { + /* Update the error code */ + hdcache->ErrorCode = HAL_DCACHE_ERROR_INVALID_OPERATION; + /* Return error status */ status = HAL_ERROR; } @@ -499,29 +508,46 @@ HAL_StatusTypeDef HAL_DCACHE_Invalidate(DCACHE_HandleTypeDef *hdcache) /* Check no ongoing operation */ if (READ_BIT(hdcache->Instance->SR, (DCACHE_SR_BUSYF | DCACHE_SR_BUSYCMDF)) != 0U) { - /* Return error status */ - status = HAL_ERROR; + /* Return busy status */ + status = HAL_BUSY; } else { + /* Update the error code */ + hdcache->ErrorCode = HAL_DCACHE_ERROR_NONE; + + /* Change DCACHE Handle state */ + hdcache->State = HAL_DCACHE_STATE_READY; + /* Make sure flags are reset */ WRITE_REG(hdcache->Instance->FCR, (DCACHE_FCR_CBSYENDF | DCACHE_FCR_CCMDENDF)); /* Set no operation on address range */ MODIFY_REG(hdcache->Instance->CR, DCACHE_CR_CACHECMD, 0U); - /* Get timeout */ - tickstart = HAL_GetTick(); - /* Launch cache invalidation */ SET_BIT(hdcache->Instance->CR, DCACHE_CR_CACHEINV); + /* Get timeout */ + tickstart = HAL_GetTick(); + /* Wait for end of cache invalidation */ - while (READ_BIT(hdcache->Instance->SR, DCACHE_FCR_CBSYENDF) != 0U) + while (READ_BIT(hdcache->Instance->SR, DCACHE_SR_BUSYF) != 0U) { if ((HAL_GetTick() - tickstart) > DCACHE_COMMAND_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + if (READ_BIT(hdcache->Instance->SR, DCACHE_SR_BUSYF) != 0U) + { + /* Update error code */ + hdcache->ErrorCode = HAL_DCACHE_ERROR_TIMEOUT; + + /* Change the DCACHE state */ + hdcache->State = HAL_DCACHE_STATE_ERROR; + + /* Return error status */ + status = HAL_ERROR; + break; + } } } } @@ -640,12 +666,17 @@ HAL_StatusTypeDef HAL_DCACHE_Invalidate_IT(DCACHE_HandleTypeDef *hdcache) /* Check no ongoing operation */ if (READ_BIT(hdcache->Instance->SR, (DCACHE_SR_BUSYF | DCACHE_SR_BUSYCMDF)) != 0U) { - - /* Return error status */ - status = HAL_ERROR; + /* Return busy status */ + status = HAL_BUSY; } else { + /* Update the error code */ + hdcache->ErrorCode = HAL_DCACHE_ERROR_NONE; + + /* Change DCACHE Handle state */ + hdcache->State = HAL_DCACHE_STATE_READY; + /* Make sure BSYENDF is reset */ WRITE_REG(hdcache->Instance->FCR, (DCACHE_FCR_CBSYENDF | DCACHE_FCR_CCMDENDF)); @@ -756,208 +787,235 @@ HAL_StatusTypeDef HAL_DCACHE_CleanInvalidByAddr_IT(DCACHE_HandleTypeDef *hdcache } /** - * @brief Handle the Data Cache interrupt request. + * @brief Start the Data Cache performance monitoring. * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains * the configuration information for the specified DCACHEx peripheral. - * @note This API should be called under the DCACHE_IRQHandler(). - * @retval None + * @param MonitorType Monitoring type + * This parameter can be a combination of the following values: + * @arg DCACHE_MONITOR_READ_HIT + * @arg DCACHE_MONITOR_READ_MISS + * @arg DCACHE_MONITOR_WRITE_HIT + * @arg DCACHE_MONITOR_WRITE_MISS + * @arg DCACHE_MONITOR_ALL + * @retval HAL status */ -void HAL_DCACHE_IRQHandler(DCACHE_HandleTypeDef *hdcache) +HAL_StatusTypeDef HAL_DCACHE_Monitor_Start(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType) { - /* Get current interrupt flags and interrupt sources value */ - uint32_t itflags = READ_REG(hdcache->Instance->SR); - uint32_t itsources = READ_REG(hdcache->Instance->IER); + /* Check the dcache handle allocation */ + if (hdcache == NULL) + { + return HAL_ERROR; + } /* Check the parameters */ assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance)); + assert_param(IS_DCACHE_MONITOR_TYPE(MonitorType)); - /* Check Data cache Error interrupt flag */ - if (((itflags & itsources) & DCACHE_FLAG_ERROR) != 0U) - { - /* Clear DCACHE error pending flag */ - __HAL_DCACHE_CLEAR_FLAG(hdcache, DCACHE_FLAG_ERROR); - - /* Data cache error interrupt user callback */ - hdcache->ErrorCallback(hdcache); - } + SET_BIT(hdcache->Instance->CR, MonitorType); - if (READ_BIT(hdcache->Instance->CR, DCACHE_CR_CACHECMD) == 0U) /* no operation by range */ - { - /* Clear DCACHE busyend pending flag */ - __HAL_DCACHE_CLEAR_FLAG(hdcache, DCACHE_FLAG_BUSYEND); + return HAL_OK; +} - /* Data cache invalidate complete interrupt user callback */ - hdcache->InvalidateCompleteCallback(hdcache); - } - else if (READ_BIT(hdcache->Instance->CR, DCACHE_CR_CACHECMD_1 | DCACHE_CR_CACHECMD_0) == \ - (DCACHE_CR_CACHECMD_1 | DCACHE_CR_CACHECMD_0)) +/** + * @brief Stop the Data Cache performance monitoring. + * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains + * the configuration information for the specified DCACHEx peripheral. + * @note Stopping the monitoring does not reset the values. + * @param MonitorType Monitoring type + * This parameter can be a combination of the following values: + * @arg DCACHE_MONITOR_READ_HIT + * @arg DCACHE_MONITOR_READ_MISS + * @arg DCACHE_MONITOR_WRITE_HIT + * @arg DCACHE_MONITOR_WRITE_MISS + * @arg DCACHE_MONITOR_ALL + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCACHE_Monitor_Stop(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType) +{ + /* Check the dcache handle allocation */ + if (hdcache == NULL) { - /* Clear DCACHE cmdend pending flag */ - __HAL_DCACHE_CLEAR_FLAG(hdcache, DCACHE_FLAG_CMDEND); - - /* Data cache clean and invalidate range cmdend interrupt user callback */ - hdcache->CleanAndInvalidateByAddrCallback(hdcache); + return HAL_ERROR; } - else if (READ_BIT(hdcache->Instance->CR, DCACHE_CR_CACHECMD_0) == DCACHE_CR_CACHECMD_0) - { - /* Clear DCACHE cmdend pending flag */ - __HAL_DCACHE_CLEAR_FLAG(hdcache, DCACHE_FLAG_CMDEND); - /* Data cache clean range cmdend interrupt user callback */ - hdcache->CleanByAddrCallback(hdcache); - } - else - { - /* Clear DCACHE cmdend pending flag */ - __HAL_DCACHE_CLEAR_FLAG(hdcache, DCACHE_FLAG_CMDEND); + /* Check the parameters */ + assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance)); + assert_param(IS_DCACHE_MONITOR_TYPE(MonitorType)); - /* Data cache Invalidate range cmdend interrupt user callback */ - hdcache->InvalidateByAddrCallback(hdcache); - } + CLEAR_BIT(hdcache->Instance->CR, MonitorType); + return HAL_OK; } /** - * @brief Cache clean command by address callback. + * @brief Reset the Data Cache performance monitoring values. * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains * the configuration information for the specified DCACHEx peripheral. - * @retval None + * @param MonitorType Monitoring type + * This parameter can be a combination of the following values: + * @arg DCACHE_MONITOR_READ_HIT + * @arg DCACHE_MONITOR_READ_MISS + * @arg DCACHE_MONITOR_WRITE_HIT + * @arg DCACHE_MONITOR_WRITE_MISS + * @arg DCACHE_MONITOR_ALL + * @retval HAL status */ -__weak void HAL_DCACHE_CleanByAddrCallback(DCACHE_HandleTypeDef *hdcache) +HAL_StatusTypeDef HAL_DCACHE_Monitor_Reset(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdcache); + /* Check the dcache handle allocation */ + if (hdcache == NULL) + { + return HAL_ERROR; + } - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DCACHE_CleanByAddrCallback() should be implemented in the user file - */ + /* Check the parameters */ + assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance)); + assert_param(IS_DCACHE_MONITOR_TYPE(MonitorType)); + + /* Force/Release reset */ + SET_BIT(hdcache->Instance->CR, (MonitorType << 2U)); + CLEAR_BIT(hdcache->Instance->CR, (MonitorType << 2U)); + + return HAL_OK; } /** - * @brief Cache Invalidate command by address callback. + * @brief Get the Data Cache performance Read Hit monitoring value. * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains * the configuration information for the specified DCACHEx peripheral. - * @retval None + * @note Upon reaching the 32-bit maximum value, monitor does not wrap. + * @retval Read Hit monitoring value */ -__weak void HAL_DCACHE_InvalidateByAddrCallback(DCACHE_HandleTypeDef *hdcache) +uint32_t HAL_DCACHE_Monitor_GetReadHitValue(const DCACHE_HandleTypeDef *hdcache) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdcache); + /* Check the parameters */ + assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance)); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DCACHE_InvalidateByAddrCallback() should be implemented in the user file - */ + /*return the Read Hit monitor value*/ + return hdcache->Instance->RHMONR; } /** - * @brief Cache clean and Invalidate command by address callback. + * @brief Get the Data Cache performance Read Miss monitoring value. * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains * the configuration information for the specified DCACHEx peripheral. - * @retval None + * @note Upon reaching the 16-bit maximum value, monitor does not wrap. + * @retval Read Miss monitoring value */ -__weak void HAL_DCACHE_CleanAndInvalidateByAddrCallback(DCACHE_HandleTypeDef *hdcache) +uint32_t HAL_DCACHE_Monitor_GetReadMissValue(const DCACHE_HandleTypeDef *hdcache) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdcache); + /* Check the parameters */ + assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance)); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DCACHE_CleanAndInvalidateByAddrCallback() should be implemented in the user file - */ + /*return the Read Miss monitor value*/ + return hdcache->Instance->RMMONR; } /** - * @brief Cache full invalidation complete callback. + * @brief Get the Data Cache performance Write Hit monitoring value. * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains * the configuration information for the specified DCACHEx peripheral. - * @retval None + * @note Upon reaching the 32-bit maximum value, monitor does not wrap. + * @retval Write Hit monitoring value */ -__weak void HAL_DCACHE_InvalidateCompleteCallback(DCACHE_HandleTypeDef *hdcache) +uint32_t HAL_DCACHE_Monitor_GetWriteHitValue(const DCACHE_HandleTypeDef *hdcache) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdcache); + /* Check the parameters */ + assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance)); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DCACHE_InvalidateCompleteCallback() should be implemented in the user file - */ + /*return the Write Hit monitor value*/ + return hdcache->Instance->WHMONR; } /** - * @brief Error callback. + * @brief Get the Data Cache performance Write Miss monitoring value. * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains * the configuration information for the specified DCACHEx peripheral. - * @retval None + * @note Upon reaching the 16-bit maximum value, monitor does not wrap. + * @retval Write Miss monitoring value */ -__weak void HAL_DCACHE_ErrorCallback(DCACHE_HandleTypeDef *hdcache) +uint32_t HAL_DCACHE_Monitor_GetWriteMissValue(const DCACHE_HandleTypeDef *hdcache) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdcache); + /* Check the parameters */ + assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance)); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DCACHE_ErrorCallback() should be implemented in the user file - */ + /*return the Write Miss monitor value*/ + return hdcache->Instance->WMMONR; } /** - * @} - */ - -/** @defgroup DCACHE_Exported_Functions_Group3 Peripheral State, - * @brief Peripheral State, - * -@verbatim - =============================================================================== - ##### Peripheral State ##### - =============================================================================== - [..] - This subsection permit to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the DCACHE handle state. + * @brief Handle the Data Cache interrupt request. * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains * the configuration information for the specified DCACHEx peripheral. - * @retval HAL state + * @note This API should be called under the DCACHEx_IRQHandler(). + * @retval None */ -HAL_DCACHE_StateTypeDef HAL_DCACHE_GetState(DCACHE_HandleTypeDef *hdcache) +void HAL_DCACHE_IRQHandler(DCACHE_HandleTypeDef *hdcache) { - /* Return DCACHE handle state */ - return hdcache->State; -} + uint32_t itflags; + uint32_t itsources; -/** - * @} - */ + /* Check the parameters */ + assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance)); -/** - * @brief Return the DCACHE error code - * @param hdcache pointer to a DCACHE_HandleTypeDef structure that contains - * the configuration information for the specified DCACHE. - * @retval DCACHE Error Code - */ -uint32_t HAL_DCACHE_GetError(DCACHE_HandleTypeDef *hdcache) -{ - return hdcache->ErrorCode; -} + /* Get current interrupt flags and interrupt sources value */ + itflags = READ_REG(hdcache->Instance->SR); + itsources = READ_REG(hdcache->Instance->IER); -/** - * @} - */ + /* Check Data cache Error interrupt flag */ + if (((itflags & itsources) & DCACHE_FLAG_ERROR) != 0U) + { + /* Clear DCACHE error pending flag */ + __HAL_DCACHE_CLEAR_FLAG(hdcache, DCACHE_FLAG_ERROR); -/** - * @} - */ + /* Update data cache error code */ + hdcache->ErrorCode = HAL_DCACHE_ERROR_EVICTION_CLEAN; -/** @addtogroup DCACHE_Exported_Functions - * @{ - */ + /* Data cache error interrupt user callback */ + hdcache->ErrorCallback(hdcache); + } -/** @addtogroup DCACHE_Exported_Functions_Group1 - * @{ - */ + /* Check for end of full invalidate operation */ + if (READ_BIT(hdcache->Instance->CR, DCACHE_CR_CACHECMD) == 0U) + { + /* Clear DCACHE busyend pending flag */ + __HAL_DCACHE_CLEAR_FLAG(hdcache, DCACHE_FLAG_BUSYEND); + + /* Data cache invalidate complete interrupt user callback */ + hdcache->InvalidateCompleteCallback(hdcache); + } + + /* Check for end of clean and invalidate by address operation */ + else if (READ_BIT(hdcache->Instance->CR, DCACHE_COMMAND_CLEAN_INVALIDATE) == \ + (DCACHE_COMMAND_CLEAN_INVALIDATE)) + { + /* Clear DCACHE cmdend pending flag */ + __HAL_DCACHE_CLEAR_FLAG(hdcache, DCACHE_FLAG_CMDEND); + + /* Data cache clean and invalidate range cmdend interrupt user callback */ + hdcache->CleanAndInvalidateByAddrCallback(hdcache); + } + + /* Check for end of clean by address operation */ + else if (READ_BIT(hdcache->Instance->CR, DCACHE_COMMAND_CLEAN) == DCACHE_COMMAND_CLEAN) + { + /* Clear DCACHE cmdend pending flag */ + __HAL_DCACHE_CLEAR_FLAG(hdcache, DCACHE_FLAG_CMDEND); + + /* Data cache clean range cmdend interrupt user callback */ + hdcache->CleanByAddrCallback(hdcache); + } + + /* Check for end of invalidate by address operation */ + else + { + /* Clear DCACHE cmdend pending flag */ + __HAL_DCACHE_CLEAR_FLAG(hdcache, DCACHE_FLAG_CMDEND); + + /* Data cache Invalidate range cmdend interrupt user callback */ + hdcache->InvalidateByAddrCallback(hdcache); + } +} /** * @brief Register a User DCACHE Callback @@ -981,15 +1039,22 @@ HAL_StatusTypeDef HAL_DCACHE_RegisterCallback(DCACHE_HandleTypeDef *hdcache, HAL { HAL_StatusTypeDef status = HAL_OK; + /* Check the dcache handle allocation */ + if (hdcache == NULL) + { + return HAL_ERROR; + } + if (pCallback == NULL) { /* Update the error code */ hdcache->ErrorCode |= HAL_DCACHE_ERROR_INVALID_CALLBACK; + /* Return error status */ return HAL_ERROR; } - if (HAL_DCACHE_STATE_READY == hdcache->State) + if (hdcache->State == HAL_DCACHE_STATE_READY) { switch (CallbackID) { @@ -1030,7 +1095,7 @@ HAL_StatusTypeDef HAL_DCACHE_RegisterCallback(DCACHE_HandleTypeDef *hdcache, HAL break; } } - else if (HAL_DCACHE_STATE_RESET == hdcache->State) + else if (hdcache->State == HAL_DCACHE_STATE_RESET) { switch (CallbackID) { @@ -1083,7 +1148,13 @@ HAL_StatusTypeDef HAL_DCACHE_UnRegisterCallback(DCACHE_HandleTypeDef *hdcache, H { HAL_StatusTypeDef status = HAL_OK; - if (HAL_DCACHE_STATE_READY == hdcache->State) + /* Check the dcache handle allocation */ + if (hdcache == NULL) + { + return HAL_ERROR; + } + + if (hdcache->State == HAL_DCACHE_STATE_READY) { switch (CallbackID) { @@ -1099,7 +1170,7 @@ HAL_StatusTypeDef HAL_DCACHE_UnRegisterCallback(DCACHE_HandleTypeDef *hdcache, H case HAL_DCACHE_CLEAN_AND_INVALIDATE_BY_ADDRESS_CB_ID : /* Legacy weak Clean and Invalidate By Addr Callback */ - hdcache->InvalidateByAddrCallback = HAL_DCACHE_CleanAndInvalidateByAddrCallback; + hdcache->CleanAndInvalidateByAddrCallback = HAL_DCACHE_CleanAndInvalidateByAddrCallback; break; case HAL_DCACHE_INVALIDATE_COMPLETE_CB_ID : @@ -1167,174 +1238,146 @@ HAL_StatusTypeDef HAL_DCACHE_UnRegisterCallback(DCACHE_HandleTypeDef *hdcache, H } /** - * @brief Start the Data Cache performance monitoring. + * @brief Cache clean command by address callback. * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains * the configuration information for the specified DCACHEx peripheral. - * @param MonitorType Monitoring type - * This parameter can be a combination of the following values: - * @arg DCACHE_MONITOR_READ_HIT - * @arg DCACHE_MONITOR_READ_MISS - * @arg DCACHE_MONITOR_WRITE_HIT - * @arg DCACHE_MONITOR_WRITE_MISS - * @arg DCACHE_MONITOR_ALL - * @retval HAL status + * @retval None */ -HAL_StatusTypeDef HAL_DCACHE_Monitor_Start(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType) +__weak void HAL_DCACHE_CleanByAddrCallback(DCACHE_HandleTypeDef *hdcache) { - /* Check the dcache handle allocation */ - if (hdcache == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance)); - assert_param(IS_DCACHE_MONITOR_TYPE(MonitorType)); - - SET_BIT(hdcache->Instance->CR, MonitorType); + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdcache); - return HAL_OK; + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DCACHE_CleanByAddrCallback() should be implemented in the user file + */ } /** - * @brief Stop the Data Cache performance monitoring. + * @brief Cache Invalidate command by address callback. * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains * the configuration information for the specified DCACHEx peripheral. - * @note Stopping the monitoring does not reset the values. - * @param MonitorType Monitoring type - * This parameter can be a combination of the following values: - * @arg DCACHE_MONITOR_READ_HIT - * @arg DCACHE_MONITOR_READ_MISS - * @arg DCACHE_MONITOR_WRITE_HIT - * @arg DCACHE_MONITOR_WRITE_MISS - * @arg DCACHE_MONITOR_ALL - * @retval HAL status + * @retval None */ -HAL_StatusTypeDef HAL_DCACHE_Monitor_Stop(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType) +__weak void HAL_DCACHE_InvalidateByAddrCallback(DCACHE_HandleTypeDef *hdcache) { - /* Check the dcache handle allocation */ - if (hdcache == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance)); - assert_param(IS_DCACHE_MONITOR_TYPE(MonitorType)); - - CLEAR_BIT(hdcache->Instance->CR, MonitorType); + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdcache); - return HAL_OK; + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DCACHE_InvalidateByAddrCallback() should be implemented in the user file + */ } /** - * @brief Reset the Data Cache performance monitoring values. + * @brief Cache clean and Invalidate command by address callback. * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains * the configuration information for the specified DCACHEx peripheral. - * @param MonitorType Monitoring type - * This parameter can be a combination of the following values: - * @arg DCACHE_MONITOR_READ_HIT - * @arg DCACHE_MONITOR_READ_MISS - * @arg DCACHE_MONITOR_WRITE_HIT - * @arg DCACHE_MONITOR_WRITE_MISS - * @arg DCACHE_MONITOR_ALL - * @retval HAL status + * @retval None */ -HAL_StatusTypeDef HAL_DCACHE_Monitor_Reset(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType) +__weak void HAL_DCACHE_CleanAndInvalidateByAddrCallback(DCACHE_HandleTypeDef *hdcache) { - /* Check the dcache handle allocation */ - if (hdcache == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance)); - assert_param(IS_DCACHE_MONITOR_TYPE(MonitorType)); - - /* Force/Release reset */ - SET_BIT(hdcache->Instance->CR, (MonitorType << 2U)); - CLEAR_BIT(hdcache->Instance->CR, (MonitorType << 2U)); + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdcache); - return HAL_OK; + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DCACHE_CleanAndInvalidateByAddrCallback() should be implemented in the user file + */ } /** - * @brief Get the Data Cache performance Read Hit monitoring value. + * @brief Cache full invalidation complete callback. * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains * the configuration information for the specified DCACHEx peripheral. - * @note Upon reaching the maximum value, monitor does not wrap. - * @retval Read Hit monitoring value + * @retval None */ -uint32_t HAL_DCACHE_Monitor_GetReadHitValue(DCACHE_HandleTypeDef *hdcache) +__weak void HAL_DCACHE_InvalidateCompleteCallback(DCACHE_HandleTypeDef *hdcache) { - /* Check the parameters */ - assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance)); + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdcache); - /*return the Read Hit monitor value*/ - return hdcache->Instance->RHMONR; + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DCACHE_InvalidateCompleteCallback() should be implemented in the user file + */ } /** - * @brief Get the Data Cache performance Read Miss monitoring value. + * @brief Error callback. * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains * the configuration information for the specified DCACHEx peripheral. - * @note Upon reaching the maximum value, monitor does not wrap. - * @retval Read Miss monitoring value + * @retval None */ -uint32_t HAL_DCACHE_Monitor_GetReadMissValue(DCACHE_HandleTypeDef *hdcache) +__weak void HAL_DCACHE_ErrorCallback(DCACHE_HandleTypeDef *hdcache) { - /* Check the parameters */ - assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance)); + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdcache); - /*return the Read Miss monitor value*/ - return hdcache->Instance->RMMONR; + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DCACHE_ErrorCallback() should be implemented in the user file + */ } /** - * @brief Get the Data Cache performance Write Hit monitoring value. - * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains - * the configuration information for the specified DCACHEx peripheral. - * @note Upon reaching the maximum value, monitor does not wrap. - * @retval Write Hit monitoring value + * @} */ -uint32_t HAL_DCACHE_Monitor_GetWriteHitValue(DCACHE_HandleTypeDef *hdcache) -{ - /* Check the parameters */ - assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance)); - /*return the Write Hit monitor value*/ - return hdcache->Instance->WHMONR; -} +/** @addtogroup DCACHE_Exported_Functions_Group3 + * +@verbatim + =============================================================================== + ##### Peripheral State ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ /** - * @brief Get the Data Cache performance Write Miss monitoring value. + * @brief Return the DCACHE handle state. * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains * the configuration information for the specified DCACHEx peripheral. - * @note Upon reaching the maximum value, monitor does not wrap. - * @retval Write Miss monitoring value + * @retval HAL state */ -uint32_t HAL_DCACHE_Monitor_GetWriteMissValue(DCACHE_HandleTypeDef *hdcache) +HAL_DCACHE_StateTypeDef HAL_DCACHE_GetState(const DCACHE_HandleTypeDef *hdcache) { - /* Check the parameters */ - assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance)); + /* Return DCACHE handle state */ + return hdcache->State; +} - /*return the Write Miss monitor value*/ - return hdcache->Instance->WMMONR; +/** + * @brief Return the DCACHE error code + * @param hdcache pointer to a DCACHE_HandleTypeDef structure that contains + * the configuration information for the specified DCACHE. + * @retval DCACHE Error Code + */ +uint32_t HAL_DCACHE_GetError(const DCACHE_HandleTypeDef *hdcache) +{ + /* Return DCACHE handle error code */ + return hdcache->ErrorCode; } + /** * @} */ +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup DCACHE_Private_Functions DCACHE Private Functions + * @brief DCACHE Private Functions + * @{ + */ + /** - * @brief launch dcache command Clean, Invalidate or clean and invalidate by Addr. + * @brief Launch DCACHE command Clean, Invalidate or clean and invalidate by Addr. * @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains * the configuration information for the specified DCACHEx peripheral. - * @param Command command to be applied for the dcache + * @param Command command to be applied for the DCACHE * DCACHE_COMMAND_INVALIDATE, DCACHE_COMMAND_CLEAN, DCACHE_COMMAND_CLEAN_INVALIDATE * @param pAddr Start address of region to be Cleaned, Invalidated or Cleaned and Invalidated. * @param dSize Size of the region to be Cleaned, Invalidated or Cleaned and Invalidated (in bytes). - * @param mode mode to be applied for the dcache + * @param mode mode to be applied for the DCACHE * DCACHE_IT_MODE, DCACHE_POLLING_MODE. * @retval HAL status */ @@ -1345,22 +1388,23 @@ static HAL_StatusTypeDef DCACHE_CommandByAddr(DCACHE_HandleTypeDef *hdcache, uin uint32_t op_addr = (uint32_t)pAddr; uint32_t tickstart; - /* Set HAL_DCACHE_STATE_BUSY */ - hdcache->State = HAL_DCACHE_STATE_BUSY; - /* Check no ongoing operation */ if (READ_BIT(hdcache->Instance->SR, (DCACHE_SR_BUSYF | DCACHE_SR_BUSYCMDF)) != 0U) { - return HAL_ERROR; + /* Return busy status */ + status = HAL_BUSY; } else { + /* Update the error code */ + hdcache->ErrorCode = HAL_DCACHE_ERROR_NONE; + + /* Update the DCACHE handle State */ + hdcache->State = HAL_DCACHE_STATE_READY; + /* Make sure flags are reset */ WRITE_REG(hdcache->Instance->FCR, (DCACHE_FCR_CBSYENDF | DCACHE_FCR_CCMDENDF)); - /* Get timeout */ - tickstart = HAL_GetTick(); - /* Fill area start address */ WRITE_REG(hdcache->Instance->CMDRSADDRR, op_addr); @@ -1381,45 +1425,47 @@ static HAL_StatusTypeDef DCACHE_CommandByAddr(DCACHE_HandleTypeDef *hdcache, uin } else { - /* Make sure that end of cache command interrupt is disabled */ CLEAR_BIT(hdcache->Instance->IER, DCACHE_IER_CMDENDIE); /* Launch cache command */ SET_BIT(hdcache->Instance->CR, DCACHE_CR_STARTCMD); + /* Get timeout */ + tickstart = HAL_GetTick(); + /* Wait for end of cache command */ while (READ_BIT(hdcache->Instance->SR, DCACHE_SR_CMDENDF) == 0U) { if ((HAL_GetTick() - tickstart) > DCACHE_COMMAND_TIMEOUT_VALUE) { - /* Update error code */ - hdcache->ErrorCode = HAL_DCACHE_ERROR_TIMEOUT; - - /* Change the DCACHE state */ - hdcache->State = HAL_DCACHE_STATE_ERROR; - - /* Return error status */ - status = HAL_ERROR; + if (READ_BIT(hdcache->Instance->SR, DCACHE_SR_CMDENDF) == 0U) + { + /* Update error code */ + hdcache->ErrorCode = HAL_DCACHE_ERROR_TIMEOUT; + + /* Change the DCACHE state */ + hdcache->State = HAL_DCACHE_STATE_ERROR; + + /* Return error status */ + status = HAL_ERROR; + break; + } } } } } - /* Set HAL_DCACHE_STATE_READY */ - hdcache->State = HAL_DCACHE_STATE_READY; - return status; } - -#endif /* HAL_DCACHE_MODULE_ENABLED */ - - /** * @} */ +#endif /* HAL_DCACHE_MODULE_ENABLED */ +#endif /* DCACHE1 || DCACHE2 */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dcache.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dcache.h index 8450ec18bf0..6d5e8c6290d 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dcache.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dcache.h @@ -31,6 +31,8 @@ extern "C" { * @{ */ +#if defined (DCACHE1) || defined (DCACHE2) + /** @addtogroup DCACHE * @{ */ @@ -45,7 +47,8 @@ extern "C" { */ typedef struct { - uint32_t ReadBurstType; /*!< Burst type to be applied for Data Cache */ + uint32_t ReadBurstType; /*!< Burst type to be applied for Data Cache + This parameter can be a value of @ref DCACHE_Read_Burst_Type*/ } DCACHE_InitTypeDef; /** @@ -53,12 +56,11 @@ typedef struct */ typedef enum { - HAL_DCACHE_STATE_RESET = 0x00U, /* !< DCACHE not yet initialized or disabled */ - HAL_DCACHE_STATE_READY = 0x01U, /* !< Peripheral initialized and ready for use */ - HAL_DCACHE_STATE_BUSY = 0x02U, /* !< An internal process is ongoing */ - HAL_DCACHE_STATE_TIMEOUT = 0x05U, /* !< Timeout state */ - HAL_DCACHE_STATE_ERROR = 0x06U, /* !< DCACHE state error */ - + HAL_DCACHE_STATE_RESET = 0x00U, /*!< DCACHE not yet initialized or disabled */ + HAL_DCACHE_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ + HAL_DCACHE_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_DCACHE_STATE_TIMEOUT = 0x05U, /*!< Timeout state */ + HAL_DCACHE_STATE_ERROR = 0x06U, /*!< DCACHE state error */ } HAL_DCACHE_StateTypeDef; /** @defgroup DCACHE_Configuration_Structure_definition DCACHE Configuration Structure definition @@ -81,7 +83,6 @@ typedef struct __DCACHE_HandleTypeDef __IO HAL_DCACHE_StateTypeDef State; __IO uint32_t ErrorCode; - } DCACHE_HandleTypeDef; /** @@ -103,7 +104,6 @@ typedef enum HAL_DCACHE_MSPINIT_CB_ID = 0x05U, /*!< DCACHE Msp Init callback ID */ HAL_DCACHE_MSPDEINIT_CB_ID = 0x06U /*!< DCACHE Msp DeInit callback ID */ - } HAL_DCACHE_CallbackIDTypeDef; /** @@ -122,9 +122,12 @@ typedef enum /** @defgroup DCACHE_Error_Code DCACHE Error Code * @{ */ -#define HAL_DCACHE_ERROR_NONE 0x00000000U /*!< No error */ -#define HAL_DCACHE_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */ -#define HAL_DCACHE_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid callback error */ +#define HAL_DCACHE_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DCACHE_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */ +#define HAL_DCACHE_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid callback error */ +#define HAL_DCACHE_ERROR_EVICTION_CLEAN 0x00000040U /*!< Eviction or clean operation write-back error */ +#define HAL_DCACHE_ERROR_INVALID_OPERATION 0x00000080U /*!< Invalid operation */ + /** * @} */ @@ -246,18 +249,31 @@ typedef enum /* Exported functions -------------------------------------------------------*/ /** @defgroup DCACHE_Exported_Functions DCACHE Exported Functions + * @brief DCACHE Exported functions + * @{ + */ + +/** @defgroup DCACHE_Exported_Functions_Group1 Initialization and De-Initialization Functions + * @brief Initialization and De-Initialization Functions * @{ */ -/* Initialization and de-initialization functions ***/ HAL_StatusTypeDef HAL_DCACHE_Init(DCACHE_HandleTypeDef *hdcache); HAL_StatusTypeDef HAL_DCACHE_DeInit(DCACHE_HandleTypeDef *hdcache); void HAL_DCACHE_MspInit(DCACHE_HandleTypeDef *hdcache); void HAL_DCACHE_MspDeInit(DCACHE_HandleTypeDef *hdcache); +/** + * @} + */ +/** @defgroup DCACHE_Exported_Functions_Group2 I/O Operation Functions + * @brief I/O Operation Functions + * @{ + */ /* Peripheral Control functions ***/ HAL_StatusTypeDef HAL_DCACHE_Enable(DCACHE_HandleTypeDef *hdcache); HAL_StatusTypeDef HAL_DCACHE_Disable(DCACHE_HandleTypeDef *hdcache); -HAL_StatusTypeDef HAL_DCACHE_SetReadBurstType(DCACHE_HandleTypeDef *hdcache, uint32_t ReadBrustType); +uint32_t HAL_DCACHE_IsEnabled(const DCACHE_HandleTypeDef *hdcache); +HAL_StatusTypeDef HAL_DCACHE_SetReadBurstType(DCACHE_HandleTypeDef *hdcache, uint32_t ReadBurstType); /*** Cache maintenance in blocking mode (Polling) ***/ HAL_StatusTypeDef HAL_DCACHE_Invalidate(DCACHE_HandleTypeDef *hdcache); @@ -290,30 +306,44 @@ HAL_StatusTypeDef HAL_DCACHE_RegisterCallback(DCACHE_HandleTypeDef *hdcache, HAL HAL_StatusTypeDef HAL_DCACHE_UnRegisterCallback(DCACHE_HandleTypeDef *hdcache, HAL_DCACHE_CallbackIDTypeDef CallbackID); /*** Performance instruction cache monitoring functions ***/ -uint32_t HAL_DCACHE_Monitor_GetReadHitValue(DCACHE_HandleTypeDef *hdcache); -uint32_t HAL_DCACHE_Monitor_GetReadMissValue(DCACHE_HandleTypeDef *hdcache); -uint32_t HAL_DCACHE_Monitor_GetWriteHitValue(DCACHE_HandleTypeDef *hdcache); -uint32_t HAL_DCACHE_Monitor_GetWriteMissValue(DCACHE_HandleTypeDef *hdcache); +uint32_t HAL_DCACHE_Monitor_GetReadHitValue(const DCACHE_HandleTypeDef *hdcache); +uint32_t HAL_DCACHE_Monitor_GetReadMissValue(const DCACHE_HandleTypeDef *hdcache); +uint32_t HAL_DCACHE_Monitor_GetWriteHitValue(const DCACHE_HandleTypeDef *hdcache); +uint32_t HAL_DCACHE_Monitor_GetWriteMissValue(const DCACHE_HandleTypeDef *hdcache); HAL_StatusTypeDef HAL_DCACHE_Monitor_Reset(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType); HAL_StatusTypeDef HAL_DCACHE_Monitor_Start(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType); HAL_StatusTypeDef HAL_DCACHE_Monitor_Stop(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType); +/** + * @} + */ + +/** @defgroup DCACHE_Exported_Functions_Group3 State and Error Functions + * @brief State and Error Functions + * @{ + */ +HAL_DCACHE_StateTypeDef HAL_DCACHE_GetState(const DCACHE_HandleTypeDef *hdcache); +uint32_t HAL_DCACHE_GetError(const DCACHE_HandleTypeDef *hdcache); +/** + * @} + */ -/* Peripheral State functions ***************************************************/ -HAL_DCACHE_StateTypeDef HAL_DCACHE_GetState(DCACHE_HandleTypeDef *hdcache); -uint32_t HAL_DCACHE_GetError(DCACHE_HandleTypeDef *hdcache); /** * @} */ + /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ /** * @} */ +#endif /* DCACHE1 || DCACHE2 */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dcmi.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dcmi.c index cc8e295cdf8..30ce86bb768 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dcmi.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dcmi.c @@ -73,9 +73,9 @@ The compilation define USE_HAL_DCMI_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use functions @ref HAL_DCMI_RegisterCallback() to register a user callback. + Use functions HAL_DCMI_RegisterCallback() to register a user callback. - Function @ref HAL_DCMI_RegisterCallback() allows to register following callbacks: + Function HAL_DCMI_RegisterCallback() allows to register following callbacks: (+) FrameEventCallback : callback for DCMI Frame Event. (+) VsyncEventCallback : callback for DCMI Vsync Event. (+) LineEventCallback : callback for DCMI Line Event. @@ -85,9 +85,9 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_DCMI_UnRegisterCallback() to reset a callback to the default + Use function HAL_DCMI_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_DCMI_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_DCMI_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the callback ID. This function allows to reset following callbacks: (+) FrameEventCallback : callback for DCMI Frame Event. @@ -97,13 +97,13 @@ (+) MspInitCallback : callback for DCMI MspInit. (+) MspDeInitCallback : callback for DCMI MspDeInit. - By default, after the @ref HAL_DCMI_Init and if the state is HAL_DCMI_STATE_RESET + By default, after the HAL_DCMI_Init and if the state is HAL_DCMI_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions: - examples @ref FrameEventCallback(), @ref HAL_DCMI_ErrorCallback(). + examples FrameEventCallback(), HAL_DCMI_ErrorCallback(). Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_DCMI_Init - and @ref HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_DCMI_Init and @ref HAL_DCMI_DeInit + reset to the legacy weak (surcharged) functions in the HAL_DCMI_Init + and HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_DCMI_Init and HAL_DCMI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). Callbacks can be registered/unregistered in READY state only. @@ -111,8 +111,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_DCMI_RegisterCallback before calling @ref HAL_DCMI_DeInit - or @ref HAL_DCMI_Init function. + using HAL_DCMI_RegisterCallback before calling HAL_DCMI_DeInit + or HAL_DCMI_Init function. When the compilation define USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -1049,7 +1049,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_Syn * the configuration information for DCMI. * @retval HAL state */ -HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi) +HAL_DCMI_StateTypeDef HAL_DCMI_GetState(const DCMI_HandleTypeDef *hdcmi) { return hdcmi->State; } @@ -1060,7 +1060,7 @@ HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi) * the configuration information for DCMI. * @retval DCMI Error Code */ -uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi) +uint32_t HAL_DCMI_GetError(const DCMI_HandleTypeDef *hdcmi) { return hdcmi->ErrorCode; } @@ -1163,7 +1163,7 @@ HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_ /** * @brief Unregister a DCMI Callback - * DCMI callabck is redirected to the weak predefined callback + * DCMI callback is redirected to the weak predefined callback * @param hdcmi DCMI handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -1250,6 +1250,11 @@ HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCM /** * @} */ + +/** + * @} + */ + /* Private functions ---------------------------------------------------------*/ /** @defgroup DCMI_Private_Functions DCMI Private Functions * @{ @@ -1355,10 +1360,6 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma) } -/** - * @} - */ - /** * @} */ @@ -1371,4 +1372,3 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma) /** * @} */ - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dcmi.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dcmi.h index d0bf18c8872..e3c9cbd57bf 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dcmi.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dcmi.h @@ -584,8 +584,8 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_ * @{ */ /* Peripheral State functions *************************************************/ -HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi); -uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); +HAL_DCMI_StateTypeDef HAL_DCMI_GetState(const DCMI_HandleTypeDef *hdcmi); +uint32_t HAL_DCMI_GetError(const DCMI_HandleTypeDef *hdcmi); /** * @} */ @@ -696,4 +696,3 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); #endif #endif /* STM32U5xx_HAL_DCMI_H */ - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_def.h index e5a72691501..043f0df60af 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_def.h @@ -70,7 +70,9 @@ typedef enum (__DMA_HANDLE__).Parent = (__HANDLE__); \ } while(0) -#define UNUSED(x) ((void)(x)) +#if !defined(UNUSED) +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ +#endif /* UNUSED */ /** @brief Reset the Handle's State field. * @param __HANDLE__: specifies the Peripheral Handle. diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma.c index 597058474b7..181aa6fe019 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma.c @@ -884,9 +884,17 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) { DMA_TypeDef *p_dma_instance = GET_DMA_INSTANCE(hdma); uint32_t global_it_flag = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + uint32_t global_active_flag_ns = IS_DMA_GLOBAL_ACTIVE_FLAG_NS(p_dma_instance, global_it_flag); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t global_active_flag_s = IS_DMA_GLOBAL_ACTIVE_FLAG_S(p_dma_instance, global_it_flag); +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Global Interrupt Flag management *********************************************************************************/ - if (IS_DMA_GLOBAL_ACTIVE_FLAG(p_dma_instance, global_it_flag) == 0U) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if ((global_active_flag_s == 0U) && (global_active_flag_ns == 0U)) +#else + if (global_active_flag_ns == 0U) +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ { return; /* the global interrupt flag for the current channel is down , nothing to do */ } @@ -999,6 +1007,9 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) { /* Update the linked-list queue state */ hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + + /* Clear remaining data size to ensure loading linked-list from memory next start */ + hdma->Instance->CBR1 = 0U; } /* Process Unlocked */ @@ -1113,6 +1124,8 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) /** * @brief Register callback according to specified ID. + * @note The HAL_DMA_RegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET + * to register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID. * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the * specified DMA Channel. * @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enumeration. @@ -1131,9 +1144,6 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hdma); - /* Check DMA channel state */ if (hdma->State == HAL_DMA_STATE_READY) { @@ -1177,6 +1187,8 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, default: { + /* Update error status */ + status = HAL_ERROR; break; } } @@ -1187,14 +1199,13 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hdma); - return status; } /** * @brief Unregister callback according to specified ID. + * @note The HAL_DMA_UnRegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET + * to un-register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID. * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the * specified DMA Channel. * @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enum. @@ -1211,9 +1222,6 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hdma); - /* Check DMA channel state */ if (hdma->State == HAL_DMA_STATE_READY) { @@ -1280,9 +1288,6 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hdma); - return status; } /** @@ -1542,7 +1547,7 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons uint32_t channel_idx; /* Check the DMA peripheral handle and lock state parameters */ - if (hdma == NULL) + if ((hdma == NULL) || (pLockState == NULL)) { return HAL_ERROR; } diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma.h index 0e8d5f5cfbc..7f7954a3c56 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma.h @@ -277,8 +277,10 @@ typedef struct __DMA_HandleTypeDef #define GPDMA1_REQUEST_I2C4_EVC (23U) /*!< GPDMA1 HW request is I2C4_EVC */ #define GPDMA1_REQUEST_USART1_RX (24U) /*!< GPDMA1 HW request is USART1_RX */ #define GPDMA1_REQUEST_USART1_TX (25U) /*!< GPDMA1 HW request is USART1_TX */ +#if defined (USART2) #define GPDMA1_REQUEST_USART2_RX (26U) /*!< GPDMA1 HW request is USART2_RX */ #define GPDMA1_REQUEST_USART2_TX (27U) /*!< GPDMA1 HW request is USART2_TX */ +#endif /* USART2 */ #define GPDMA1_REQUEST_USART3_RX (28U) /*!< GPDMA1 HW request is USART3_RX */ #define GPDMA1_REQUEST_USART3_TX (29U) /*!< GPDMA1 HW request is USART3_TX */ #define GPDMA1_REQUEST_UART4_RX (30U) /*!< GPDMA1 HW request is UART4_RX */ @@ -289,10 +291,14 @@ typedef struct __DMA_HandleTypeDef #define GPDMA1_REQUEST_LPUART1_TX (35U) /*!< GPDMA1 HW request is LPUART1_TX */ #define GPDMA1_REQUEST_SAI1_A (36U) /*!< GPDMA1 HW request is SAI1_A */ #define GPDMA1_REQUEST_SAI1_B (37U) /*!< GPDMA1 HW request is SAI1_B */ +#if defined (SAI2) #define GPDMA1_REQUEST_SAI2_A (38U) /*!< GPDMA1 HW request is SAI2_A */ #define GPDMA1_REQUEST_SAI2_B (39U) /*!< GPDMA1 HW request is SAI2_B */ +#endif /* SAI2 */ #define GPDMA1_REQUEST_OCTOSPI1 (40U) /*!< GPDMA1 HW request is OCTOSPI1 */ +#if defined (OCTOSPI2) #define GPDMA1_REQUEST_OCTOSPI2 (41U) /*!< GPDMA1 HW request is OCTOSPI2 */ +#endif /* OCTOSPI2 */ #define GPDMA1_REQUEST_TIM1_CH1 (42U) /*!< GPDMA1 HW request is TIM1_CH1 */ #define GPDMA1_REQUEST_TIM1_CH2 (43U) /*!< GPDMA1 HW request is TIM1_CH2 */ #define GPDMA1_REQUEST_TIM1_CH3 (44U) /*!< GPDMA1 HW request is TIM1_CH3 */ @@ -337,12 +343,14 @@ typedef struct __DMA_HandleTypeDef #define GPDMA1_REQUEST_TIM16_UP (83U) /*!< GPDMA1 HW request is TIM16_UP */ #define GPDMA1_REQUEST_TIM17_CH1 (84U) /*!< GPDMA1 HW request is TIM17_CH1 */ #define GPDMA1_REQUEST_TIM17_UP (85U) /*!< GPDMA1 HW request is TIM17_UP */ -#define GPDMA1_REQUEST_DCMI (86U) /*!< GPDMA1 HW request is DCMI */ +#define GPDMA1_REQUEST_DCMI_PSSI (86U) /*!< GPDMA1 HW request is DCMI_PSSI */ #define GPDMA1_REQUEST_AES_IN (87U) /*!< GPDMA1 HW request is AES_IN */ #define GPDMA1_REQUEST_AES_OUT (88U) /*!< GPDMA1 HW request is AES_OUT */ #define GPDMA1_REQUEST_HASH_IN (89U) /*!< GPDMA1 HW request is HASH_IN */ +#if defined (UCPD1) #define GPDMA1_REQUEST_UCPD1_TX (90U) /*!< GPDMA1 HW request is UCPD1_TX */ #define GPDMA1_REQUEST_UCPD1_RX (91U) /*!< GPDMA1 HW request is UCPD1_RX */ +#endif /* UCPD1 */ #define GPDMA1_REQUEST_MDF1_FLT0 (92U) /*!< GPDMA1 HW request is MDF1_FLT0 */ #define GPDMA1_REQUEST_MDF1_FLT1 (93U) /*!< GPDMA1 HW request is MDF1_FLT1 */ #define GPDMA1_REQUEST_MDF1_FLT2 (94U) /*!< GPDMA1 HW request is MDF1_FLT2 */ @@ -365,6 +373,26 @@ typedef struct __DMA_HandleTypeDef #define GPDMA1_REQUEST_LPTIM3_IC1 (111U) /*!< GPDMA1 HW request is LPTIM3_IC1 */ #define GPDMA1_REQUEST_LPTIM3_IC2 (112U) /*!< GPDMA1 HW request is LPTIM3_IC2 */ #define GPDMA1_REQUEST_LPTIM3_UE (113U) /*!< GPDMA1 HW request is LPTIM3_UE */ +#if defined (HSPI1_BASE) +#define GPDMA1_REQUEST_HSPI1 (114U) /*!< GPDMA1 HW request is HSPI1 */ +#endif /* defined (HSPI1_BASE) */ +#if defined (I2C5) +#define GPDMA1_REQUEST_I2C5_RX (115U) /*!< GPDMA1 HW request is I2C5_RX */ +#define GPDMA1_REQUEST_I2C5_TX (116U) /*!< GPDMA1 HW request is I2C5_TX */ +#define GPDMA1_REQUEST_I2C5_EVC (117U) /*!< GPDMA1 HW request is I2C5_EVC */ +#endif /* defined (I2C5) */ +#if defined (I2C6) +#define GPDMA1_REQUEST_I2C6_RX (118U) /*!< GPDMA1 HW request is I2C6_RX */ +#define GPDMA1_REQUEST_I2C6_TX (119U) /*!< GPDMA1 HW request is I2C6_TX */ +#define GPDMA1_REQUEST_I2C6_EVC (120U) /*!< GPDMA1 HW request is I2C6_EVC */ +#endif /* defined (I2C6) */ +#if defined (USART6) +#define GPDMA1_REQUEST_USART6_RX (121U) /*!< GPDMA1 HW request is USART6_RX */ +#define GPDMA1_REQUEST_USART6_TX (122U) /*!< GPDMA1 HW request is USART6_TX */ +#endif /* defined (USART6) */ +#if defined (ADC2) +#define GPDMA1_REQUEST_ADC2 (123U) /*!< GPDMA1 HW request is ADC2 */ +#endif /* defined (ADC2) */ /* LPDMA1 requests */ #define LPDMA1_REQUEST_LPUART1_RX (0U) /*!< LPDMA1 HW request is LPUART1_RX */ @@ -759,7 +787,8 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons #define DMA_CHANNEL_ATTR_SEC_MASK (0x00000020U) /* DMA channel secure mask */ #define DMA_CHANNEL_ATTR_SEC_SRC_MASK (0x00000040U) /* DMA channel source secure mask */ #define DMA_CHANNEL_ATTR_SEC_DEST_MASK (0x00000080U) /* DMA channel destination secure mask */ -#define DMA_CHANNEL_ATTR_MASK (0xFFFFFFF0U) /* DMA channel attributes mask */ +#define DMA_CHANNEL_ATTR_VALUE_MASK (0x0000000FU) /* DMA channel attributes value mask */ +#define DMA_CHANNEL_ATTR_ITEM_MASK (0x000000F0U) /* DMA channel attributes item mask */ #define DMA_CHANNEL_BURST_MIN (0x00000001U) /* DMA channel minimum burst size */ #define DMA_CHANNEL_BURST_MAX (0x00000040U) /* DMA channel maximum burst size */ /** @@ -821,9 +850,11 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons #define IS_DMA_TRANSFER_ALLOCATED_PORT(ALLOCATED_PORT) \ (((ALLOCATED_PORT) & (~(DMA_CTR1_SAP | DMA_CTR1_DAP))) == 0U) -#define IS_DMA_REQUEST(REQUEST) \ - (((REQUEST) == DMA_REQUEST_SW) || \ - ((REQUEST) <= GPDMA1_REQUEST_LPTIM3_UE)) +#if defined (GPDMA1_REQUEST_ADC2) +#define IS_DMA_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_SW) || ((REQUEST) <= GPDMA1_REQUEST_ADC2)) +#else +#define IS_DMA_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_SW) || ((REQUEST) <= GPDMA1_REQUEST_LPTIM3_UE)) +#endif /* GPDMA1_REQUEST_ADC2 */ #define IS_DMA_BLOCK_HW_REQUEST(MODE) \ (((MODE) == DMA_BREQ_SINGLE_BURST) || \ @@ -839,9 +870,10 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons (((SIZE) > 0U) && ((SIZE) <= DMA_CBR1_BNDT)) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ - (((((~((ATTRIBUTE) & DMA_CHANNEL_ATTR_MASK)) >> 4U) & ((ATTRIBUTE) & DMA_CHANNEL_ATTR_MASK)) == 0U) && \ - ((ATTRIBUTE) != 0U)) +#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ + (((ATTRIBUTE) != 0U) && (((ATTRIBUTE) & (~(DMA_CHANNEL_ATTR_VALUE_MASK | DMA_CHANNEL_ATTR_ITEM_MASK))) == 0U) && \ + (((((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U) | ((ATTRIBUTE) & DMA_CHANNEL_ATTR_VALUE_MASK)) == \ + (((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U))) #else #define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ (((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \ @@ -849,12 +881,11 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define IS_DMA_GLOBAL_ACTIVE_FLAG(INSTANCE, GLOBAL_FLAG) \ +#define IS_DMA_GLOBAL_ACTIVE_FLAG_S(INSTANCE, GLOBAL_FLAG) \ (((INSTANCE)->SMISR & (GLOBAL_FLAG))) -#else -#define IS_DMA_GLOBAL_ACTIVE_FLAG(INSTANCE, GLOBAL_FLAG) \ - (((INSTANCE)->MISR & (GLOBAL_FLAG))) #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#define IS_DMA_GLOBAL_ACTIVE_FLAG_NS(INSTANCE, GLOBAL_FLAG) \ + (((INSTANCE)->MISR & (GLOBAL_FLAG))) /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma2d.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma2d.c index b47cc6e28c4..9379fbbf2bc 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma2d.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma2d.c @@ -1788,6 +1788,13 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted)); assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap)); +#if defined(DMA2D_FGPFCCR_CSS) + if ((LayerIdx == DMA2D_FOREGROUND_LAYER) && (hdma2d->LayerCfg[LayerIdx].InputColorMode == DMA2D_INPUT_YCBCR)) + { + assert_param(IS_DMA2D_CHROMA_SUB_SAMPLING(hdma2d->LayerCfg[LayerIdx].ChromaSubSampling)); + } + +#endif /* DMA2D_FGPFCCR_CSS */ /* Process locked */ __HAL_LOCK(hdma2d); @@ -1831,6 +1838,13 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La else { +#if defined(DMA2D_FGPFCCR_CSS) + if (pLayerCfg->InputColorMode == DMA2D_INPUT_YCBCR) + { + regValue |= (pLayerCfg->ChromaSubSampling << DMA2D_FGPFCCR_CSS_Pos); + regMask |= DMA2D_FGPFCCR_CSS; + } +#endif /* DMA2D_FGPFCCR_CSS */ /* Write DMA2D FGPFCCR register */ MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue); @@ -2052,7 +2066,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t * the configuration information for the DMA2D. * @retval HAL state */ -HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d) +HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d) { return hdma2d->State; } @@ -2063,7 +2077,7 @@ HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d) * the configuration information for DMA2D. * @retval DMA2D Error Code */ -uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d) +uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d) { return hdma2d->ErrorCode; } @@ -2173,4 +2187,3 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ */ #endif /* DMA2D */ #endif /* HAL_DMA2D_MODULE_ENABLED */ - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma2d.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma2d.h index c12d8b34b82..0c527072b51 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma2d.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma2d.h @@ -121,6 +121,10 @@ typedef struct uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR). This parameter can be one value of @ref DMA2D_RB_Swap. */ +#if defined(DMA2D_FGPFCCR_CSS) + uint32_t ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode + This parameter can be one value of @ref DMA2D_Chroma_Sub_Sampling */ +#endif /* DMA2D_FGPFCCR_CSS */ } DMA2D_LayerCfgTypeDef; @@ -240,6 +244,9 @@ typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointe #define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */ #define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */ #define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */ +#if defined(DMA2D_FGPFCCR_CSS) +#define DMA2D_INPUT_YCBCR 0x0000000BU /*!< YCbCr color mode */ +#endif /* DMA2D_FGPFCCR_CSS */ /** * @} */ @@ -293,6 +300,17 @@ typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointe * @} */ +#if defined(DMA2D_FGPFCCR_CSS) +/** @defgroup DMA2D_Chroma_Sub_Sampling DMA2D Chroma Sub Sampling + * @{ + */ +#define DMA2D_NO_CSS 0x00000000U /*!< No chroma sub-sampling 4:4:4 */ +#define DMA2D_CSS_422 0x00000001U /*!< chroma sub-sampling 4:2:2 */ +#define DMA2D_CSS_420 0x00000002U /*!< chroma sub-sampling 4:2:0 */ +/** + * @} + */ +#endif /* DMA2D_FGPFCCR_CSS */ /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode * @{ @@ -538,8 +556,8 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t */ /* Peripheral State functions ***************************************************/ -HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); -uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); +HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d); +uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d); /** * @} @@ -640,6 +658,20 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) +#if defined(DMA2D_FGPFCCR_CSS) +#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \ + ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ + ((INPUT_CM) == DMA2D_INPUT_RGB565) || \ + ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ + ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \ + ((INPUT_CM) == DMA2D_INPUT_L8) || \ + ((INPUT_CM) == DMA2D_INPUT_AL44) || \ + ((INPUT_CM) == DMA2D_INPUT_AL88) || \ + ((INPUT_CM) == DMA2D_INPUT_L4) || \ + ((INPUT_CM) == DMA2D_INPUT_A8) || \ + ((INPUT_CM) == DMA2D_INPUT_A4) || \ + ((INPUT_CM) == DMA2D_INPUT_YCBCR)) +#else #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \ ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ ((INPUT_CM) == DMA2D_INPUT_RGB565) || \ @@ -651,6 +683,7 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); ((INPUT_CM) == DMA2D_INPUT_L4) || \ ((INPUT_CM) == DMA2D_INPUT_A8) || \ ((INPUT_CM) == DMA2D_INPUT_A4)) +#endif /* DMA2D_FGPFCCR_CSS */ #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ @@ -668,6 +701,11 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); #define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \ ((BYTES_SWAP) == DMA2D_BYTES_SWAP)) +#if defined(DMA2D_FGPFCCR_CSS) +#define IS_DMA2D_CHROMA_SUB_SAMPLING(CSS) (((CSS) == DMA2D_NO_CSS) || \ + ((CSS) == DMA2D_CSS_422) || \ + ((CSS) == DMA2D_CSS_420)) +#endif /* DMA2D_FGPFCCR_CSS */ #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) @@ -697,5 +735,3 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); #endif #endif /* STM32U5xx_HAL_DMA2D_H */ - - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma_ex.c index 6da399b33cc..4975fe2e6ff 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma_ex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma_ex.c @@ -162,6 +162,8 @@ in memory. Placing DMA linked-list in SRAM must be done in accordance to product specification to ensure that the link access port can access to the specified SRAM. + (++) The DMA linked-list node parameter address should be 32bit aligned and should not exceed the 64 KByte + addressable space. (+) Use HAL_DMAEx_List_GetNodeConfig() to get the specified configuration parameter on building node. This API can be used when need to change few parameter to build new node. @@ -376,7 +378,7 @@ In order to avoid some CPU data processing in several cases, the DMA channel provides some features related to FIFO capabilities titled data handling. (++) Padding pattern - Padding selected patter (zero padding or sign extension) when the source data width is smaller than + Padding selected pattern (zero padding or sign extension) when the source data width is smaller than the destination data width at single level. Zero padding (Source : 0xABAB ------> Destination : 0xABAB0000) Sign bit extension (Source : 0x0ABA ------> Destination : 0x00000ABA) @@ -536,12 +538,10 @@ static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, DMA_NodeTypeDef const *const pNode); static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, DMA_NodeTypeDef const *const pNode2, - DMA_NodeTypeDef const *const pNode3, - DMA_NodeTypeDef const *const pNode4); + DMA_NodeTypeDef const *const pNode3); static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, DMA_NodeTypeDef const *const pNode2, - DMA_NodeTypeDef const *const pNode3, - DMA_NodeTypeDef const *const pNode4); + DMA_NodeTypeDef const *const pNode3); static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode, uint32_t *const cllr_mask, uint32_t *const cllr_offset); @@ -743,9 +743,10 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) hdma->XferAbortCallback = NULL; hdma->XferSuspendCallback = NULL; - /* Update the queue state and error code */ - if(hdma->LinkedListQueue != NULL) + /* Check the linked-list queue */ + if (hdma->LinkedListQueue != NULL) { + /* Update the queue state and error code */ hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; @@ -781,7 +782,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) * @verbatim ====================================================================================================================== - ############### Linked-List I/O Operation Functions ############### + ############### Linked-List IO Operation Functions ############### ====================================================================================================================== [..] This section provides functions allowing to : @@ -1031,6 +1032,8 @@ HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma) * specified DMA linked-list Node. * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers * configurations. + * @note The DMA linked-list node parameter address should be 32bit aligned and should not exceed the 64 KByte + * addressable space. * @retval HAL status. */ HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, @@ -1155,7 +1158,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList, } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pPrevNode, pNewNode, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pPrevNode, pNewNode) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -1164,7 +1167,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList, } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pQList->Head, pPrevNode, pNewNode, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pQList->Head, pPrevNode, pNewNode) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -1283,7 +1286,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList, } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -1292,7 +1295,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList, } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -1363,7 +1366,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList, } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -1372,7 +1375,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList, } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -1793,7 +1796,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList, } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pOldNode, pNewNode, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pOldNode, pNewNode) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -1802,7 +1805,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList, } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pQList->Head, pOldNode, pNewNode, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pQList->Head, pOldNode, pNewNode) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -1955,7 +1958,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -1964,7 +1967,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -2235,7 +2238,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList, } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pPrevNode, pDestQList->Head, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U) { /* Update the source queue error code */ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -2247,7 +2250,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList, } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pSrcQList->Head, pPrevNode, pDestQList->Head, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U) { /* Update the source queue error code */ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -2433,7 +2436,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList, } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U) { /* Update the source queue error code */ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -2445,7 +2448,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList, } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U) { /* Update the source queue error code */ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -2570,7 +2573,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList, } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U) { /* Update the source queue error code */ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -2582,7 +2585,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList, } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U) { /* Update the source queue error code */ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -3495,7 +3498,7 @@ HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma) hdma->Instance->CCR |= DMA_CCR_SUSP; /* Check if the DMA channel is suspended */ - while ((hdma->Instance->CSR & DMA_CSR_SUSPF) != 0U) + while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U) { /* Check for the timeout */ if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) @@ -3511,10 +3514,10 @@ HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma) return HAL_ERROR; } - - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_SUSPEND; } + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_SUSPEND; } return HAL_OK; @@ -3650,7 +3653,13 @@ static void DMA_List_Init(DMA_HandleTypeDef const *const hdma) uint32_t tmpreg; /* Prepare DMA Channel Control Register (CCR) value */ - tmpreg = hdma->InitLinkedList.Priority | hdma->InitLinkedList.LinkStepMode | hdma->InitLinkedList.LinkAllocatedPort; + tmpreg = hdma->InitLinkedList.Priority | hdma->InitLinkedList.LinkStepMode; + + /* Check DMA channel instance */ + if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U) + { + tmpreg |= hdma->InitLinkedList.LinkAllocatedPort; + } /* Write DMA Channel Control Register (CCR) */ MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg); @@ -4070,15 +4079,13 @@ static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, * @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations. * @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations. * @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations. - * @param pNode4 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 4 registers configurations. * @retval Return 0 when nodes addresses are compatible, 1 otherwise. */ static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, DMA_NodeTypeDef const *const pNode2, - DMA_NodeTypeDef const *const pNode3, - DMA_NodeTypeDef const *const pNode4) + DMA_NodeTypeDef const *const pNode3) { - uint32_t temp = (((uint32_t)pNode1 | (uint32_t)pNode2 | (uint32_t)pNode3 | (uint32_t)pNode4) & DMA_CLBAR_LBA); + uint32_t temp = (((uint32_t)pNode1 | (uint32_t)pNode2 | (uint32_t)pNode3) & DMA_CLBAR_LBA); uint32_t ref = 0U; /* Check node 1 address */ @@ -4096,11 +4103,6 @@ static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pN { ref = (uint32_t)pNode3; } - /* Check node 4 address */ - else if ((uint32_t)pNode4 != 0U) - { - ref = (uint32_t)pNode4; - } else { /* Prevent MISRA-C2012-Rule-15.7 */ @@ -4120,13 +4122,11 @@ static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pN * @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations. * @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations. * @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations. - * @param pNode4 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 4 registers configurations. * @retval Return 0 when nodes types are compatible, otherwise nodes types are not compatible. */ static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, DMA_NodeTypeDef const *const pNode2, - DMA_NodeTypeDef const *const pNode3, - DMA_NodeTypeDef const *const pNode4) + DMA_NodeTypeDef const *const pNode3) { uint32_t ref = 0U; @@ -4145,26 +4145,11 @@ static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, { ref = pNode3->NodeInfo & NODE_TYPE_MASK; } - /* Check node 4 parameter */ - else if (pNode4 != NULL) - { - ref = pNode4->NodeInfo & NODE_TYPE_MASK; - } else { /* Prevent MISRA-C2012-Rule-15.7 */ } - /* Check node 1 parameter */ - if (pNode1 != NULL) - { - /* Check node type compatibility */ - if (ref != (pNode1->NodeInfo & NODE_TYPE_MASK)) - { - return 1U; - } - } - /* Check node 2 parameter */ if (pNode2 != NULL) { @@ -4185,16 +4170,6 @@ static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, } } - /* Check node 4 parameter */ - if (pNode4 != NULL) - { - /* Check node type compatibility */ - if (ref != (pNode4->NodeInfo & NODE_TYPE_MASK)) - { - return 4U; - } - } - return 0U; } diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma_ex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma_ex.h index 41e7026fa23..3454c1448b1 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma_ex.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dma_ex.h @@ -327,6 +327,33 @@ typedef struct __DMA_QListTypeDef #define GPDMA1_TRIGGER_LPDMA1_CH3_TCF (41U) /*!< GPDMA1 HW Trigger signal is LPDMA1_CH3_TCF */ #define GPDMA1_TRIGGER_TIM2_TRGO (42U) /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */ #define GPDMA1_TRIGGER_TIM15_TRGO (43U) /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */ +#if defined (TIM3_TRGO_TRIGGER_SUPPORT) +#define GPDMA1_TRIGGER_TIM3_TRGO (44U) /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ +#endif /* defined (TRIGGER_TIM3_TRGO_SUPPORT) */ +#if defined (TIM4_TRGO_TRIGGER_SUPPORT) +#define GPDMA1_TRIGGER_TIM4_TRGO (45U) /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */ +#endif /* defined (TRIGGER_TIM4_TRGO_SUPPORT) */ +#if defined (TIM5_TRGO_TRIGGER_SUPPORT) +#define GPDMA1_TRIGGER_TIM5_TRGO (46U) /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */ +#endif /* defined (TRIGGER_TIM5_TRGO_SUPPORT) */ +#if defined (LTDC) +#define GPDMA1_TRIGGER_LTDC_LI (47U) /*!< GPDMA1 HW Trigger signal is LTDC_LI */ +#endif /* defined (LTDC) */ +#if defined (DSI) +#define GPDMA1_TRIGGER_DSI_TE (48U) /*!< GPDMA1 HW Trigger signal is DSI_TE */ +#define GPDMA1_TRIGGER_DSI_ER (49U) /*!< GPDMA1 HW Trigger signal is DSI_ER */ +#endif /* defined (DSI) */ +#if defined (DMA2D_TRIGGER_SUPPORT) +#define GPDMA1_TRIGGER_DMA2D_TC (50U) /*!< GPDMA1 HW Trigger signal is DMA2D_TC */ +#define GPDMA1_TRIGGER_DMA2D_CTC (51U) /*!< GPDMA1 HW Trigger signal is DMA2D_CTC */ +#define GPDMA1_TRIGGER_DMA2D_TW (52U) /*!< GPDMA1 HW Trigger signal is DMA2D_TW */ +#endif /* defined (DMA2D_TRIGGER_SUPPORT) */ +#if defined (GPU2D) +#define GPDMA1_TRIGGER_GPU2D_FLAG0 (53U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG0 */ +#define GPDMA1_TRIGGER_GPU2D_FLAG1 (54U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG1 */ +#define GPDMA1_TRIGGER_GPU2D_FLAG2 (55U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG2 */ +#define GPDMA1_TRIGGER_GPU2D_FLAG3 (56U) /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG3 */ +#endif /* defined (GPU2D) */ #define GPDMA1_TRIGGER_ADC4_AWD1 (57U) /*!< GPDMA1 HW Trigger signal is ADC4_AWD1 */ #define GPDMA1_TRIGGER_ADC1_AWD1 (58U) /*!< GPDMA1 HW Trigger signal is ADC1_AWD1 */ @@ -418,8 +445,8 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma); * @} */ -/** @defgroup DMAEx_Exported_Functions_Group2 Linked-List I/O Operation Functions - * @brief Linked-List I/O Operation Functions +/** @defgroup DMAEx_Exported_Functions_Group2 Linked-List IO Operation Functions + * @brief Linked-List IO Operation Functions * @{ */ HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma); @@ -645,8 +672,7 @@ typedef struct ((POLARITY) == DMA_TRIG_POLARITY_RISING) || \ ((POLARITY) == DMA_TRIG_POLARITY_FALLING)) -#define IS_DMA_TRIGGER_SELECTION(TRIGGER) \ - ((TRIGGER) <= GPDMA1_TRIGGER_ADC1_AWD1) +#define IS_DMA_TRIGGER_SELECTION(TRIGGER) ((TRIGGER) <= GPDMA1_TRIGGER_ADC1_AWD1) #define IS_DMA_NODE_TYPE(TYPE) \ (((TYPE) == DMA_LPDMA_LINEAR_NODE) || \ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dsi.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dsi.c new file mode 100644 index 00000000000..58bb66f4b84 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dsi.c @@ -0,0 +1,2864 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_dsi.c + * @author MCD Application Team + * @brief DSI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the DSI peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The DSI HAL driver can be used as follows: + + (#) Declare a DSI_HandleTypeDef handle structure, for example: DSI_HandleTypeDef hdsi; + + (#) Initialize the DSI low level resources by implementing the HAL_DSI_MspInit() API: + (##) Enable the DSI interface clock + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the DSI interrupt priority + (+++) Enable the NVIC DSI IRQ Channel + + (#) Initialize the DSI Host peripheral, the required PLL parameters, number of lances and + TX Escape clock divider by calling the HAL_DSI_Init() API which calls HAL_DSI_MspInit(). + + *** Configuration *** + ========================= + [..] + (#) Use HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted + command mode. + + (#) When operating in video mode , use HAL_DSI_ConfigVideoMode() to configure the DSI host. + + (#) Function HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode. + + (#) To configure the DSI PHY timings parameters, use function HAL_DSI_ConfigPhyTimer(). + + (#) The DSI Host can be started/stopped using respectively functions HAL_DSI_Start() and HAL_DSI_Stop(). + Functions HAL_DSI_ShortWrite(), HAL_DSI_LongWrite() and HAL_DSI_Read() allows respectively + to write DSI short packets, long packets and to read DSI packets. + + (#) The DSI Host Offers two Low power modes : + (++) Low Power Mode on data lanes only: Only DSI data lanes are shut down. + It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPMData() + and HAL_DSI_ExitULPMData() + + (++) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes. + It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPM() + and HAL_DSI_ExitULPM() + + (#) To control DSI state you can use the following function: HAL_DSI_GetState() + + *** Error management *** + ======================== + [..] + (#) User can select the DSI errors to be reported/monitored using function HAL_DSI_ConfigErrorMonitor() + When an error occurs, the callback HAL_DSI_ErrorCallback() is asserted and then user can retrieve + the error code by calling function HAL_DSI_GetError() + + *** DSI HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DSI HAL driver. + + (+) __HAL_DSI_ENABLE: Enable the DSI Host. + (+) __HAL_DSI_DISABLE: Disable the DSI Host. + (+) __HAL_DSI_WRAPPER_ENABLE: Enables the DSI wrapper. + (+) __HAL_DSI_WRAPPER_DISABLE: Disable the DSI wrapper. + (+) __HAL_DSI_PLL_ENABLE: Enables the DSI PLL. + (+) __HAL_DSI_PLL_DISABLE: Disables the DSI PLL. + (+) __HAL_DSI_REG_ENABLE: Enables the DSI regulator. + (+) __HAL_DSI_REG_DISABLE: Disables the DSI regulator. + (+) __HAL_DSI_GET_FLAG: Get the DSI pending flags. + (+) __HAL_DSI_CLEAR_FLAG: Clears the DSI pending flags. + (+) __HAL_DSI_ENABLE_IT: Enables the specified DSI interrupts. + (+) __HAL_DSI_DISABLE_IT: Disables the specified DSI interrupts. + (+) __HAL_DSI_GET_IT_SOURCE: Checks whether the specified DSI interrupt source is enabled or not. + + [..] + (@) You can refer to the DSI HAL driver header file for more useful macros + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_DSI_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function HAL_DSI_RegisterCallback() to register a callback. + + [..] + Function HAL_DSI_RegisterCallback() allows to register following callbacks: + (+) TearingEffectCallback : DSI Tearing Effect Callback. + (+) EndOfRefreshCallback : DSI End Of Refresh Callback. + (+) ErrorCallback : DSI Error Callback + (+) MspInitCallback : DSI MspInit. + (+) MspDeInitCallback : DSI MspDeInit. + [..] + This function takes as parameters the HAL peripheral handle, the callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_DSI_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the callback ID. + [..] + This function allows to reset following callbacks: + (+) TearingEffectCallback : DSI Tearing Effect Callback. + (+) EndOfRefreshCallback : DSI End Of Refresh Callback. + (+) ErrorCallback : DSI Error Callback + (+) MspInitCallback : DSI MspInit. + (+) MspDeInitCallback : DSI MspDeInit. + + [..] + By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_DSI_TearingEffectCallback(), HAL_DSI_EndOfRefreshCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (surcharged) functions in the HAL_DSI_Init() + and HAL_DSI_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_DSI_Init() and HAL_DSI_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_DSI_RegisterCallback() before calling HAL_DSI_DeInit() + or HAL_DSI_Init() function. + + [..] + When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +#ifdef HAL_DSI_MODULE_ENABLED + +#if defined(DSI) + +/** @addtogroup DSI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @addtogroup DSI_Private_Constants + * @{ + */ +#define DSI_TIMEOUT_VALUE ((uint32_t)100U) /* 100ms */ + +#define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \ + DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \ + DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \ + DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15) +#define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4) +#define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX +#define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX +#define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME) +#define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE +#define DSI_ERROR_PSE_MASK DSI_ISR1_PSE +#define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE +#define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE +#define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE) +#define DSI_ERROR_PBU_MASK DSI_ISR1_PBUE +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, + uint32_t Data1); + +static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t Param1, + uint32_t Param2); +static void DSI_ConfigBandControl(DSI_HandleTypeDef *hdsi); +static void DSI_SetWrapperPLLTuning(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit); +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DSI_Private_Functions DSI Private Functions + * @{ + */ +/** + * @brief Generic DSI packet header configuration + * @param DSIx Pointer to DSI register base + * @param ChannelID Virtual channel ID of the header packet + * @param DataType Packet data type of the header packet + * This parameter can be any value of : + * @arg DSI_SHORT_WRITE_PKT_Data_Type + * @arg DSI_LONG_WRITE_PKT_Data_Type + * @arg DSI_SHORT_READ_PKT_Data_Type + * @arg DSI_MAX_RETURN_PKT_SIZE + * @param Data0 Word count LSB + * @param Data1 Word count MSB + * @retval None + */ +static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, + uint32_t ChannelID, + uint32_t DataType, + uint32_t Data0, + uint32_t Data1) +{ + /* Update the DSI packet header with new information */ + DSIx->GHCR = (DataType | (ChannelID << 6U) | (Data0 << 8U) | (Data1 << 16U)); +} + +/** + * @brief write short DCS or short Generic command + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ChannelID Virtual channel ID. + * @param Mode DSI short packet data type. + * This parameter can be any value of @arg DSI_SHORT_WRITE_PKT_Data_Type. + * @param Param1 DSC command or first generic parameter. + * This parameter can be any value of @arg DSI_DCS_Command or a + * generic command code. + * @param Param2 DSC parameter or second generic parameter. + * @retval HAL status + */ +static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t Param1, + uint32_t Param2) +{ + uint32_t tickstart; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for Command FIFO Empty */ + while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the packet to send a short DCS command with 0 or 1 parameter */ + /* Update the DSI packet header with new information */ + hdsi->Instance->GHCR = (Mode | (ChannelID << 6U) | (Param1 << 8U) | (Param2 << 16U)); + + return HAL_OK; +} + +/** + * @brief Configure Band Control Frequency and LPX Offset + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +static void DSI_ConfigBandControl(DSI_HandleTypeDef *hdsi) +{ + + /* Set Band Control Frequency for clock lane */ + hdsi->Instance->DPCBCR &= ~DSI_DPCBCR; + hdsi->Instance->DPCBCR |= (hdsi->Init.PHYFrequencyRange << DSI_DPCBCR_Pos); + + /* Set the slew rate for clock lane */ + hdsi->Instance->DPCSRCR = DSI_DPHY_SLEW_HS_TX_SPEED; + + /* Set Band Control Frequency for Data Lane0 */ + hdsi->Instance->DPDL0BCR &= ~DSI_DPDL0BCR; + hdsi->Instance->DPDL0BCR = (hdsi->Init.PHYFrequencyRange << DSI_DPDL0BCR_Pos); + + /* Set the slew rate for data Lane0 */ + hdsi->Instance->DPDL0SRCR = DSI_DPHY_SLEW_HS_TX_SPEED; + + /* Set Band Control Frequency for Data Lane1 */ + hdsi->Instance->DPDL1BCR &= ~DSI_DPDL1BCR; + hdsi->Instance->DPDL1BCR = (hdsi->Init.PHYFrequencyRange << DSI_DPDL1BCR_Pos); + + /* Set Slew rate for data Lane1 */ + hdsi->Instance->DPDL1SRCR = DSI_DPHY_SLEW_HS_TX_SPEED; + + /* Set HS prepare offset for data lanes */ + hdsi->Instance->DPDL0HSOCR &= ~DSI_DPDL0HSOCR; + hdsi->Instance->DPDL1HSOCR &= ~DSI_DPDL1HSOCR; + + if ((hdsi->Init.PHYFrequencyRange == DSI_DPHY_FRANGE_100MHZ_120MHZ) || \ + (hdsi->Init.PHYFrequencyRange == DSI_DPHY_FRANGE_120MHZ_160MHZ) || \ + (hdsi->Init.PHYFrequencyRange == DSI_DPHY_FRANGE_240MHZ_320MHZ)) + { + hdsi->Instance->DPDL0HSOCR = (DSI_HS_PREPARE_OFFSET0 << DSI_DPDL0HSOCR_Pos); + hdsi->Instance->DPDL1HSOCR = (DSI_HS_PREPARE_OFFSET0 << DSI_DPDL1HSOCR_Pos); + } + else if ((hdsi->Init.PHYFrequencyRange == DSI_DPHY_FRANGE_80MHZ_100MHZ) || \ + (hdsi->Init.PHYFrequencyRange == DSI_DPHY_FRANGE_160MHZ_200MHZ) || \ + (hdsi->Init.PHYFrequencyRange == DSI_DPHY_FRANGE_200MHZ_240MHZ) || \ + (hdsi->Init.PHYFrequencyRange == DSI_DPHY_FRANGE_320MHZ_390MHZ)) + { + hdsi->Instance->DPDL0HSOCR = (DSI_HS_PREPARE_OFFSET1 << DSI_DPDL0HSOCR_Pos); + hdsi->Instance->DPDL1HSOCR = (DSI_HS_PREPARE_OFFSET1 << DSI_DPDL1HSOCR_Pos); + } + else if ((hdsi->Init.PHYFrequencyRange == DSI_DPHY_FRANGE_390MHZ_450MHZ) || \ + (hdsi->Init.PHYFrequencyRange == DSI_DPHY_FRANGE_450MHZ_510MHZ)) + { + hdsi->Instance->DPDL0HSOCR = (DSI_HS_PREPARE_OFFSET2 << DSI_DPDL0HSOCR_Pos); + hdsi->Instance->DPDL1HSOCR = (DSI_HS_PREPARE_OFFSET2 << DSI_DPDL1HSOCR_Pos); + } + else + { + /* Nothing to do */ + } + + /* Set LPXO value for data lanes */ + hdsi->Instance->DPDL0LPXOCR &= ~DSI_DPDL0LPXOCR; + hdsi->Instance->DPDL1LPXOCR &= ~DSI_DPDL1LPXOCR; + + hdsi->Instance->DPDL0LPXOCR = hdsi->Init.PHYLowPowerOffset; + hdsi->Instance->DPDL1LPXOCR = hdsi->Init.PHYLowPowerOffset; + +} + +/** + * @brief Set Wrapper PLL Tuning and Charge Pump + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param PLLInit pointer to a DSI_PLLInitTypeDef structure that contains + * the PLL Clock structure definition for the DSI. + * @retval HAL status + */ +static void DSI_SetWrapperPLLTuning(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit) +{ + /* Set the VCO Frequency */ + hdsi->Instance->WRPCR &= ~(DSI_WRPCR_BC); + hdsi->Instance->WRPCR |= (PLLInit->PLLVCORange << DSI_WRPCR_BC_Pos); + + hdsi->Instance->WPTR &= ~(DSI_WPTR_LPF | DSI_WPTR_CP); + + /* Set PLL Tuning */ + hdsi->Instance->WPTR |= (PLLInit->PLLTuning << DSI_WPTR_LPF_Pos); + + /* Set PLL_Charge Value */ + hdsi->Instance->WPTR |= (PLLInit->PLLChargePump << DSI_WPTR_CP_Pos); + +} +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DSI_Exported_Functions + * @{ + */ + +/** @defgroup DSI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the DSI + (+) De-initialize the DSI + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the DSI according to the specified + * parameters in the DSI_InitTypeDef and create the associated handle. + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param PLLInit pointer to a DSI_PLLInitTypeDef structure that contains + * the PLL Clock structure definition for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit) +{ + uint32_t tickstart; + + /* Check the DSI handle allocation */ + if (hdsi == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV)); + assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF)); + assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF)); + assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl)); + assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes)); + assert_param(IS_DSI_DPHY_BAND_CTL_FRANGE(hdsi->Init.PHYFrequencyRange)); + assert_param(IS_DSI_DPHY_LOW_POWER_OFFSET(hdsi->Init.PHYLowPowerOffset)); + assert_param(IS_DSI_DPHY_VCO_FREQUENCY_RANGE(PLLInit->PLLVCORange)); + assert_param(IS_DSI_PLL_TUNING(PLLInit->PLLTuning)); + assert_param(IS_DSI_PLL_CHARGEPUMP(PLLInit->PLLChargePump)); + +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + if (hdsi->State == HAL_DSI_STATE_RESET) + { + /* Reset the DSI callback to the legacy weak callbacks */ + hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */ + hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */ + hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hdsi->MspInitCallback == NULL) + { + hdsi->MspInitCallback = HAL_DSI_MspInit; + } + /* Initialize the low level hardware */ + hdsi->MspInitCallback(hdsi); + } +#else + if (hdsi->State == HAL_DSI_STATE_RESET) + { + /* Initialize the low level hardware */ + HAL_DSI_MspInit(hdsi); + } +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ + + /* Change DSI peripheral state */ + hdsi->State = HAL_DSI_STATE_BUSY; + + /**************** Turn on the Reference Bias and enable the DSI PLL ****************/ + /* bias power up */ + hdsi->Instance->BCFGR |= DSI_BCFGR_PWRUP; + + /* Requires min of 2ms delay, 2ms delay is inserted */ + HAL_Delay(2); + + + /* Set the PLL division factors */ + hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); + hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << DSI_WRPCR_PLL_NDIV_Pos) | \ + ((PLLInit->PLLIDF) << DSI_WRPCR_PLL_IDF_Pos) | \ + ((PLLInit->PLLODF) << DSI_WRPCR_PLL_ODF_Pos)); + + /************************ Set D-PHY Band Control registers ******************************/ + /* Set Band Control Frequency and LPX Offset */ + DSI_ConfigBandControl(hdsi); + + /* Set PLL Tuning */ + DSI_SetWrapperPLLTuning(hdsi, PLLInit); + + /* Enable the DSI PLL */ + __HAL_DSI_PLL_ENABLE(hdsi); + + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /*************************** Set the PHY parameters ***************************/ + + /* D-PHY clock and digital enable*/ + hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN); + + /* Clock lane configuration */ + hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR); + hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl); + + /* Configure the number of active data lanes */ + hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL; + hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes; + + /************************ Set the DSI clock parameters ************************/ + + /* Set the TX escape clock division factor */ + hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; + hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv; + + + /****************************** Error management *****************************/ + + /* Disable all error interrupts and reset the Error Mask */ + hdsi->Instance->IER[0U] = 0U; + hdsi->Instance->IER[1U] = 0U; + hdsi->ErrorMsk = 0U; + + /* Initialize the error code */ + hdsi->ErrorCode = HAL_DSI_ERROR_NONE; + + /* Initialize the DSI state*/ + hdsi->State = HAL_DSI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-initializes the DSI peripheral registers to their default reset + * values. + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi) +{ + /* Check the DSI handle allocation */ + if (hdsi == NULL) + { + return HAL_ERROR; + } + + /* Change DSI peripheral state */ + hdsi->State = HAL_DSI_STATE_BUSY; + + /* Disable the DSI wrapper */ + __HAL_DSI_WRAPPER_DISABLE(hdsi); + + /* Disable the DSI host */ + __HAL_DSI_DISABLE(hdsi); + + /* D-PHY clock and digital disable */ + hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN); + + /* Turn off the DSI PLL */ + __HAL_DSI_PLL_DISABLE(hdsi); + + /* Disable the reference bias */ + hdsi->Instance->BCFGR &= ~DSI_BCFGR_PWRUP; + +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + if (hdsi->MspDeInitCallback == NULL) + { + hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; + } + /* DeInit the low level hardware */ + hdsi->MspDeInitCallback(hdsi); +#else + /* DeInit the low level hardware */ + HAL_DSI_MspDeInit(hdsi); +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ + + /* Initialize the error code */ + hdsi->ErrorCode = HAL_DSI_ERROR_NONE; + + /* Initialize the DSI state*/ + hdsi->State = HAL_DSI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Enable the error monitor flags + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ActiveErrors indicates which error interrupts will be enabled. + * This parameter can be any combination of @arg DSI_Error_Data_Type. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + hdsi->Instance->IER[0U] = 0U; + hdsi->Instance->IER[1U] = 0U; + + /* Store active errors to the handle */ + hdsi->ErrorMsk = ActiveErrors; + + if ((ActiveErrors & HAL_DSI_ERROR_ACK) != 0U) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK; + } + + if ((ActiveErrors & HAL_DSI_ERROR_PHY) != 0U) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK; + } + + if ((ActiveErrors & HAL_DSI_ERROR_TX) != 0U) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK; + } + + if ((ActiveErrors & HAL_DSI_ERROR_RX) != 0U) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK; + } + + if ((ActiveErrors & HAL_DSI_ERROR_ECC) != 0U) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK; + } + + if ((ActiveErrors & HAL_DSI_ERROR_CRC) != 0U) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK; + } + + if ((ActiveErrors & HAL_DSI_ERROR_PSE) != 0U) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK; + } + + if ((ActiveErrors & HAL_DSI_ERROR_EOT) != 0U) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK; + } + + if ((ActiveErrors & HAL_DSI_ERROR_OVF) != 0U) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK; + } + + if ((ActiveErrors & HAL_DSI_ERROR_GEN) != 0U) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK; + } + + if ((ActiveErrors & HAL_DSI_ERROR_PBU) != 0U) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_PBU_MASK; + } + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Initializes the DSI MSP. + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-initializes the DSI MSP. + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User DSI Callback + * To be used instead of the weak predefined callback + * @param hdsi dsi handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID + * @arg HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID + * @arg HAL_DSI_ERROR_CB_ID Error Callback ID + * @arg HAL_DSI_MSPINIT_CB_ID MspInit callback ID + * @arg HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID, + pDSI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hdsi); + + if (hdsi->State == HAL_DSI_STATE_READY) + { + switch (CallbackID) + { + case HAL_DSI_TEARING_EFFECT_CB_ID : + hdsi->TearingEffectCallback = pCallback; + break; + + case HAL_DSI_ENDOF_REFRESH_CB_ID : + hdsi->EndOfRefreshCallback = pCallback; + break; + + case HAL_DSI_ERROR_CB_ID : + hdsi->ErrorCallback = pCallback; + break; + + case HAL_DSI_MSPINIT_CB_ID : + hdsi->MspInitCallback = pCallback; + break; + + case HAL_DSI_MSPDEINIT_CB_ID : + hdsi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hdsi->State == HAL_DSI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DSI_MSPINIT_CB_ID : + hdsi->MspInitCallback = pCallback; + break; + + case HAL_DSI_MSPDEINIT_CB_ID : + hdsi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdsi); + + return status; +} + +/** + * @brief Unregister a DSI Callback + * DSI callback is redirected to the weak predefined callback + * @param hdsi dsi handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID + * @arg HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID + * @arg HAL_DSI_ERROR_CB_ID Error Callback ID + * @arg HAL_DSI_MSPINIT_CB_ID MspInit callback ID + * @arg HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdsi); + + if (hdsi->State == HAL_DSI_STATE_READY) + { + switch (CallbackID) + { + case HAL_DSI_TEARING_EFFECT_CB_ID : + hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */ + break; + + case HAL_DSI_ENDOF_REFRESH_CB_ID : + hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */ + break; + + case HAL_DSI_ERROR_CB_ID : + hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_DSI_MSPINIT_CB_ID : + hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legacy weak MspInit Callback */ + break; + + case HAL_DSI_MSPDEINIT_CB_ID : + hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legacy weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hdsi->State == HAL_DSI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DSI_MSPINIT_CB_ID : + hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legacy weak MspInit Callback */ + break; + + case HAL_DSI_MSPDEINIT_CB_ID : + hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legacy weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdsi); + + return status; +} +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup DSI_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides function allowing to: + (+) Handle DSI interrupt request + +@endverbatim + * @{ + */ +/** + * @brief Handles DSI interrupt request. + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi) +{ + uint32_t ErrorStatus0; + uint32_t ErrorStatus1; + + /* Tearing Effect Interrupt management ***************************************/ + if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != 0U) + { + if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != 0U) + { + /* Clear the Tearing Effect Interrupt Flag */ + __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE); + + /* Tearing Effect Callback */ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + /*Call registered Tearing Effect callback */ + hdsi->TearingEffectCallback(hdsi); +#else + /*Call legacy Tearing Effect callback*/ + HAL_DSI_TearingEffectCallback(hdsi); +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ + } + } + + /* End of Refresh Interrupt management ***************************************/ + if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != 0U) + { + if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != 0U) + { + /* Clear the End of Refresh Interrupt Flag */ + __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER); + + /* End of Refresh Callback */ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + /*Call registered End of refresh callback */ + hdsi->EndOfRefreshCallback(hdsi); +#else + /*Call Legacy End of refresh callback */ + HAL_DSI_EndOfRefreshCallback(hdsi); +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ + } + } + + /* Error Interrupts management ***********************************************/ + if (hdsi->ErrorMsk != 0U) + { + ErrorStatus0 = hdsi->Instance->ISR[0U]; + ErrorStatus0 &= hdsi->Instance->IER[0U]; + ErrorStatus1 = hdsi->Instance->ISR[1U]; + ErrorStatus1 &= hdsi->Instance->IER[1U]; + + if ((ErrorStatus0 & DSI_ERROR_ACK_MASK) != 0U) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_ACK; + } + + if ((ErrorStatus0 & DSI_ERROR_PHY_MASK) != 0U) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_PHY; + } + + if ((ErrorStatus1 & DSI_ERROR_TX_MASK) != 0U) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_TX; + } + + if ((ErrorStatus1 & DSI_ERROR_RX_MASK) != 0U) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_RX; + } + + if ((ErrorStatus1 & DSI_ERROR_ECC_MASK) != 0U) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_ECC; + } + + if ((ErrorStatus1 & DSI_ERROR_CRC_MASK) != 0U) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_CRC; + } + + if ((ErrorStatus1 & DSI_ERROR_PSE_MASK) != 0U) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_PSE; + } + + if ((ErrorStatus1 & DSI_ERROR_EOT_MASK) != 0U) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_EOT; + } + + if ((ErrorStatus1 & DSI_ERROR_OVF_MASK) != 0U) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_OVF; + } + + if ((ErrorStatus1 & DSI_ERROR_GEN_MASK) != 0U) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_GEN; + } + + if ((ErrorStatus1 & DSI_ERROR_PBU_MASK) != 0U) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_PBU; + } + /* Check only selected errors */ + if (hdsi->ErrorCode != HAL_DSI_ERROR_NONE) + { + /* DSI error interrupt callback */ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + /*Call registered Error callback */ + hdsi->ErrorCallback(hdsi); +#else + /*Call Legacy Error callback */ + HAL_DSI_ErrorCallback(hdsi); +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Tearing Effect DSI callback. + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_TearingEffectCallback could be implemented in the user file + */ +} + +/** + * @brief End of Refresh DSI callback. + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_EndOfRefreshCallback could be implemented in the user file + */ +} + +/** + * @brief Operation Error DSI callback. + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup DSI_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the Generic interface read-back Virtual Channel ID + (+) Select video mode and configure the corresponding parameters + (+) Configure command transmission mode: High-speed or Low-power + (+) Configure the flow control + (+) Configure the DSI PHY timer + (+) Configure the DSI HOST timeout + (+) Configure the DSI HOST timeout + (+) Start/Stop the DSI module + (+) Refresh the display in command mode + (+) Controls the display color mode in Video mode + (+) Control the display shutdown in Video mode + (+) write short DCS or short Generic command + (+) write long DCS or long Generic command + (+) Read command (DCS or generic) + (+) Enter/Exit the Ultra Low Power Mode on data only (D-PHY PLL running) + (+) Enter/Exit the Ultra Low Power Mode on data only and clock (D-PHY PLL turned off) + (+) Start/Stop test pattern generation + (+) Slew-Rate And Delay Tuning + (+) Low-Power Reception Filter Tuning + (+) Activate an additional current path on all lanes to meet the SDDTx parameter + (+) Custom lane pins configuration + (+) Set custom timing for the PHY + (+) Force the Clock/Data Lane in TX Stop Mode + (+) Force LP Receiver in Low-Power Mode + (+) Force Data Lanes in RX Mode after a BTA + (+) Enable a pull-down on the lanes to prevent from floating states when unused + (+) Switch off the contention detection on data lanes + +@endverbatim + * @{ + */ + +/** + * @brief Configure the Generic interface read-back Virtual Channel ID. + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param VirtualChannelIdRx Virtual channel ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetGenericVCIDRX(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelIdRx) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Update the GVCID register */ + hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCIDRX; + hdsi->Instance->GVCIDR |= VirtualChannelIdRx << DSI_GVCIDR_VCIDRX_Pos; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure the Virtual channel ID for transmission. + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param VirtualChannelIdTx Virtual channel ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetGenericVCIDTX(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelIdTx) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Update the GVCID register */ + hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCIDTX; + hdsi->Instance->GVCIDR |= VirtualChannelIdTx << DSI_GVCIDR_VCIDTX_Pos; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} +/** + * @brief Configure the Generic interface read-back Virtual Channel ID. + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param VirtualChannelID Virtual channel ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Update the GVCIDR register with the Tx and Rx Virtual channel ID */ + hdsi->Instance->GVCIDR &= ~(DSI_GVCIDR_VCIDRX | DSI_GVCIDR_VCIDTX); + hdsi->Instance->GVCIDR |= ((VirtualChannelID << DSI_GVCIDR_VCIDRX_Pos) | \ + (VirtualChannelID << DSI_GVCIDR_VCIDTX_Pos)); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Select video mode and configure the corresponding parameters + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains + * the DSI video mode configuration parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding)); + assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode)); + assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable)); + assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable)); + assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable)); + assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable)); + assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable)); + assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable)); + assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable)); + assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable)); + assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity)); + assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity)); + assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity)); + /* Check the LooselyPacked variant only in 18-bit mode */ + if (VidCfg->ColorCoding == DSI_RGB666) + { + assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked)); + } + + /* Select video mode by resetting CMDM and DSIM bits */ + hdsi->Instance->MCR &= ~DSI_MCR_CMDM; + hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM; + + /* Configure the video mode transmission type */ + hdsi->Instance->VMCR &= ~DSI_VMCR_VMT; + hdsi->Instance->VMCR |= VidCfg->Mode; + + /* Configure the video packet size */ + hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE; + hdsi->Instance->VPCR |= VidCfg->PacketSize; + + /* Set the chunks number to be transmitted through the DSI link */ + hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC; + hdsi->Instance->VCCR |= VidCfg->NumberOfChunks; + + /* Set the size of the null packet */ + hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE; + hdsi->Instance->VNPCR |= VidCfg->NullPacketSize; + + /* Select the virtual channel for the LTDC interface traffic */ + hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID; + hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID; + + /* Configure the polarity of control signals */ + hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP); + hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity); + + /* Select the color coding for the host */ + hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC; + hdsi->Instance->LCOLCR |= VidCfg->ColorCoding; + + /* Select the color coding for the wrapper */ + hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; + hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding) << 1U); + + /* Enable/disable the loosely packed variant to 18-bit configuration */ + if (VidCfg->ColorCoding == DSI_RGB666) + { + hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE; + hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked; + } + + /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */ + hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA; + hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive; + + /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */ + hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP; + hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch; + + /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */ + hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE; + hdsi->Instance->VLCR |= VidCfg->HorizontalLine; + + /* Set the Vertical Synchronization Active (VSA) */ + hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA; + hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive; + + /* Set the Vertical Back Porch (VBP)*/ + hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP; + hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch; + + /* Set the Vertical Front Porch (VFP)*/ + hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP; + hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch; + + /* Set the Vertical Active period*/ + hdsi->Instance->VVACR &= ~DSI_VVACR_VA; + hdsi->Instance->VVACR |= VidCfg->VerticalActive; + + /* Configure the command transmission mode */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE; + hdsi->Instance->VMCR |= VidCfg->LPCommandEnable; + + /* Low power largest packet size */ + hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE; + hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize) << 16U); + + /* Low power VACT largest packet size */ + hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE; + hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize; + + /* Enable LP transition in HFP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE; + hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable; + + /* Enable LP transition in HBP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE; + hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable; + + /* Enable LP transition in VACT period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable; + + /* Enable LP transition in VFP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable; + + /* Enable LP transition in VBP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable; + + /* Enable LP transition in vertical sync period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable; + + /* Enable the request for an acknowledge response at the end of a frame */ + hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE; + hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Select adapted command mode and configure the corresponding parameters + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains + * the DSI command mode configuration parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding)); + assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource)); + assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity)); + assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh)); + assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol)); + assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest)); + assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity)); + assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity)); + assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity)); + + /* Select command mode by setting CMDM and DSIM bits */ + hdsi->Instance->MCR |= DSI_MCR_CMDM; + hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM; + hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM; + + /* Select the virtual channel for the LTDC interface traffic */ + hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID; + hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID; + + /* Configure the polarity of control signals */ + hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP); + hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity); + + /* Select the color coding for the host */ + hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC; + hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding; + + /* Select the color coding for the wrapper */ + hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; + hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding) << 1U); + + /* Configure the maximum allowed size for write memory command */ + hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE; + hdsi->Instance->LCCR |= CmdCfg->CommandSize; + + /* Configure the tearing effect source and polarity and select the refresh mode */ + hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL); + hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | + CmdCfg->VSyncPol); + + /* Configure the tearing effect acknowledge request */ + hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE; + hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest; + + /* Enable the Tearing Effect interrupt */ + __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE); + + /* Enable the End of Refresh interrupt */ + __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure command transmission mode: High-speed or Low-power + * and enable/disable acknowledge request after packet transmission + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param LPCmd pointer to a DSI_LPCmdTypeDef structure that contains + * the DSI command transmission mode configuration parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP)); + assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP)); + assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP)); + assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP)); + assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP)); + assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP)); + assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite)); + assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP)); + assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP)); + assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP)); + assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite)); + assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket)); + assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest)); + + /* Select High-speed or Low-power for command transmission */ + hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX | \ + DSI_CMCR_GSW1TX | \ + DSI_CMCR_GSW2TX | \ + DSI_CMCR_GSR0TX | \ + DSI_CMCR_GSR1TX | \ + DSI_CMCR_GSR2TX | \ + DSI_CMCR_GLWTX | \ + DSI_CMCR_DSW0TX | \ + DSI_CMCR_DSW1TX | \ + DSI_CMCR_DSR0TX | \ + DSI_CMCR_DLWTX | \ + DSI_CMCR_MRDPS); + hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP | \ + LPCmd->LPGenShortWriteOneP | \ + LPCmd->LPGenShortWriteTwoP | \ + LPCmd->LPGenShortReadNoP | \ + LPCmd->LPGenShortReadOneP | \ + LPCmd->LPGenShortReadTwoP | \ + LPCmd->LPGenLongWrite | \ + LPCmd->LPDcsShortWriteNoP | \ + LPCmd->LPDcsShortWriteOneP | \ + LPCmd->LPDcsShortReadNoP | \ + LPCmd->LPDcsLongWrite | \ + LPCmd->LPMaxReadPacket); + + /* Configure the acknowledge request after each packet transmission */ + hdsi->Instance->CMCR &= ~DSI_CMCR_ARE; + hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure the flow control parameters + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param FlowControl flow control feature(s) to be enabled. + * This parameter can be any combination of @arg DSI_FlowControl. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_FLOW_CONTROL(FlowControl)); + + /* Set the DSI Host Protocol Configuration Register */ + hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL; + hdsi->Instance->PCR |= FlowControl; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure the DSI PHY timer parameters + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param PhyTimers DSI_PHY_TimerTypeDef structure that contains + * the DSI PHY timing parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers) +{ + uint32_t maxTime; + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Insert LPX Offset into the timings */ + PhyTimers->ClockLaneHS2LPTime = PhyTimers->ClockLaneHS2LPTime + hdsi->Init.PHYLowPowerOffset; + PhyTimers->ClockLaneLP2HSTime = PhyTimers->ClockLaneLP2HSTime + (3U * hdsi->Init.PHYLowPowerOffset); + PhyTimers->DataLaneLP2HSTime = PhyTimers->DataLaneLP2HSTime + (2U * hdsi->Init.PHYLowPowerOffset); + + maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime) ? PhyTimers->ClockLaneLP2HSTime : + PhyTimers->ClockLaneHS2LPTime; + + /* Clock lane timer configuration */ + + /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two + High-Speed transmission. + To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed + to Low-Power and from Low-Power to High-Speed. + This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration + Register (DSI_CLTCR). + But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME. + + Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME. + */ + hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME); + hdsi->Instance->CLTCR |= (maxTime | ((maxTime) << 16U)); + + /* Data lane timer configuration */ + hdsi->Instance->DLTCR &= ~(DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME); + hdsi->Instance->DLTCR |= (PhyTimers->DataLaneLP2HSTime | ((PhyTimers->DataLaneHS2LPTime) << 16U)); + hdsi->Instance->DLTRCR &= ~DSI_DLTRCR_MRD_TIME; + hdsi->Instance->DLTRCR |= PhyTimers->DataLaneMaxReadTime; + + /* Configure the wait period to request HS transmission after a stop state */ + hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME; + hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime) << 8U); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure the DSI HOST timeout parameters + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param HostTimeouts DSI_HOST_TimeoutTypeDef structure that contains + * the DSI host timeout parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Set the timeout clock division factor */ + hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV; + hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv) << 8U); + + /* High-speed transmission timeout */ + hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT; + hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout) << 16U); + + /* Low-power reception timeout */ + hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT; + hdsi->Instance->TCCR[0U] |= HostTimeouts->LowPowerReceptionTimeout; + + /* High-speed read timeout */ + hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT; + hdsi->Instance->TCCR[1U] |= HostTimeouts->HighSpeedReadTimeout; + + /* Low-power read timeout */ + hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT; + hdsi->Instance->TCCR[2U] |= HostTimeouts->LowPowerReadTimeout; + + /* High-speed write timeout */ + hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT; + hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWriteTimeout; + + /* High-speed write presp mode */ + hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM; + hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWritePrespMode; + + /* Low-speed write timeout */ + hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT; + hdsi->Instance->TCCR[4U] |= HostTimeouts->LowPowerWriteTimeout; + + /* BTA timeout */ + hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT; + hdsi->Instance->TCCR[5U] |= HostTimeouts->BTATimeout; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Start the DSI module + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Enable the DSI host */ + __HAL_DSI_ENABLE(hdsi); + + /* Enable the DSI wrapper */ + __HAL_DSI_WRAPPER_ENABLE(hdsi); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Stop the DSI module + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Disable the DSI host */ + __HAL_DSI_DISABLE(hdsi); + + /* Disable the DSI wrapper */ + __HAL_DSI_WRAPPER_DISABLE(hdsi); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Refresh the display in command mode + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Update the display */ + hdsi->Instance->WCR |= DSI_WCR_LTDCEN; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Controls the display color mode in Video mode + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ColorMode Color mode (full or 8-colors). + * This parameter can be any value of @arg DSI_Color_Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_COLOR_MODE(ColorMode)); + + /* Update the display color mode */ + hdsi->Instance->WCR &= ~DSI_WCR_COLM; + hdsi->Instance->WCR |= ColorMode; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Control the display shutdown in Video mode + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Shutdown Shut-down (Display-ON or Display-OFF). + * This parameter can be any value of @arg DSI_ShutDown + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_SHUT_DOWN(Shutdown)); + + /* Update the display Shutdown */ + hdsi->Instance->WCR &= ~DSI_WCR_SHTDN; + hdsi->Instance->WCR |= Shutdown; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief write short DCS or short Generic command + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ChannelID Virtual channel ID. + * @param Mode DSI short packet data type. + * This parameter can be any value of @arg DSI_SHORT_WRITE_PKT_Data_Type. + * @param Param1 DSC command or first generic parameter. + * This parameter can be any value of @arg DSI_DCS_Command or a + * generic command code. + * @param Param2 DSC parameter or second generic parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t Param1, + uint32_t Param2) +{ + HAL_StatusTypeDef status; + /* Check the parameters */ + assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode)); + + /* Process locked */ + __HAL_LOCK(hdsi); + + status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return status; +} + +/** + * @brief write long DCS or long Generic command + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ChannelID Virtual channel ID. + * @param Mode DSI long packet data type. + * This parameter can be any value of @arg DSI_LONG_WRITE_PKT_Data_Type. + * @param NbParams Number of parameters. + * @param Param1 DSC command or first generic parameter. + * This parameter can be any value of @arg DSI_DCS_Command or a + * generic command code + * @param ParametersTable Pointer to parameter values table. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t NbParams, + uint32_t Param1, + uint8_t *ParametersTable) +{ + uint32_t uicounter; + uint32_t nbBytes; + uint32_t count; + uint32_t tickstart; + uint32_t fifoword; + uint8_t *pparams = ParametersTable; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode)); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for Command FIFO Empty */ + while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Set the DCS code on payload byte 1, and the other parameters on the write FIFO command*/ + fifoword = Param1; + nbBytes = (NbParams < 3U) ? NbParams : 3U; + + for (count = 0U; count < nbBytes; count++) + { + fifoword |= (((uint32_t)(*(pparams + count))) << (8U + (8U * count))); + } + hdsi->Instance->GPDR = fifoword; + + uicounter = NbParams - nbBytes; + pparams += nbBytes; + /* Set the Next parameters on the write FIFO command*/ + while (uicounter != 0U) + { + nbBytes = (uicounter < 4U) ? uicounter : 4U; + fifoword = 0U; + for (count = 0U; count < nbBytes; count++) + { + fifoword |= (((uint32_t)(*(pparams + count))) << (8U * count)); + } + hdsi->Instance->GPDR = fifoword; + + uicounter -= nbBytes; + pparams += nbBytes; + } + + /* Configure the packet to send a long DCS command */ + DSI_ConfigPacketHeader(hdsi->Instance, + ChannelID, + Mode, + ((NbParams + 1U) & 0x00FFU), + (((NbParams + 1U) & 0xFF00U) >> 8U)); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Read command (DCS or generic) + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ChannelNbr Virtual channel ID + * @param Array pointer to a buffer to store the payload of a read back operation. + * @param Size Data size to be read (in byte). + * @param Mode DSI read packet data type. + * This parameter can be any value of @arg DSI_SHORT_READ_PKT_Data_Type. + * @param DCSCmd DCS get/read command. + * @param ParametersTable Pointer to parameter values table. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, + uint32_t ChannelNbr, + uint8_t *Array, + uint32_t Size, + uint32_t Mode, + uint32_t DCSCmd, + uint8_t *ParametersTable) +{ + uint32_t tickstart; + uint8_t *pdata = Array; + uint32_t datasize = Size; + uint32_t fifoword; + uint32_t nbbytes; + uint32_t count; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_READ_PACKET_TYPE(Mode)); + + if (datasize > 2U) + { + /* set max return packet size */ + if (DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize) & 0xFFU), + (((datasize) >> 8U) & 0xFFU)) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + + /* Configure the packet to read command */ + if (Mode == DSI_DCS_SHORT_PKT_READ) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0U); + } + else if (Mode == DSI_GEN_SHORT_PKT_READ_P0) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0U, 0U); + } + else if (Mode == DSI_GEN_SHORT_PKT_READ_P1) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], 0U); + } + else if (Mode == DSI_GEN_SHORT_PKT_READ_P2) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], ParametersTable[1U]); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* If DSI fifo is not empty, read requested bytes */ + while (((int32_t)(datasize)) > 0) + { + if ((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U) + { + fifoword = hdsi->Instance->GPDR; + nbbytes = (datasize < 4U) ? datasize : 4U; + + for (count = 0U; count < nbbytes; count++) + { + *pdata = (uint8_t)(fifoword >> (8U * count)); + pdata++; + datasize--; + } + } + + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + + /* Software workaround to avoid HAL_TIMEOUT when a DSI read command is */ + /* issued to the panel and the read data is not captured by the DSI Host */ + /* which returns Packet Size Error. */ + /* Need to ensure that the Read command has finished before checking PSE */ + if ((hdsi->Instance->GPSR & DSI_GPSR_RCB) == 0U) + { + if ((hdsi->Instance->ISR[1U] & DSI_ISR1_PSE) == DSI_ISR1_PSE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running + * (only data lanes are in ULPM) + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Verify the initial status of the DSI Host */ + + /* Verify that the clock lane and the digital section of the D-PHY are enabled */ + if ((hdsi->Instance->PCTLR & (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) != (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that the D-PHY PLL and the reference bias are enabled */ + if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + else if ((hdsi->Instance->BCFGR & DSI_BCFGR_PWRUP) != DSI_BCFGR_PWRUP) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Verify that there are no ULPS exit or request on data lanes */ + if ((hdsi->Instance->PUCR & (DSI_PUCR_UEDL | DSI_PUCR_URDL)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that there are no Transmission trigger */ + if ((hdsi->Instance->PTTCR & DSI_PTTCR_TX_TRIG) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Verify that D-PHY PLL is locked */ + tickstart = HAL_GetTick(); + + while ((__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Verify that all active lanes are in Stop state */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* ULPS Request on Data Lanes */ + hdsi->Instance->PUCR |= DSI_PUCR_URDL; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until the D-PHY active lanes enter into ULPM */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running + * (only data lanes are in ULPM) + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Verify that all active lanes are in ULPM */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* Turn on the DSI PLL */ + __HAL_DSI_PLL_ENABLE(hdsi); + + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Exit ULPS on Data Lanes */ + hdsi->Instance->PUCR |= DSI_PUCR_UEDL; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until all active lanes exit ULPM */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* wait for 1 ms*/ + HAL_Delay(1U); + + /* De-assert the ULPM requests and the ULPM exit bits */ + hdsi->Instance->PUCR = 0U; + + /* Verify that D-PHY PLL is enabled */ + if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that all active lanes are in Stop state */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that D-PHY PLL is locked */ + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off + * (both data and clock lanes are in ULPM) + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Verify the initial status of the DSI Host */ + + /* Verify that the clock lane and the digital section of the D-PHY are enabled */ + if ((hdsi->Instance->PCTLR & (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) != (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that the D-PHY PLL and the reference bias are enabled */ + if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + else if ((hdsi->Instance->BCFGR & DSI_BCFGR_PWRUP) != DSI_BCFGR_PWRUP) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Verify that there are no ULPS exit or request on both data and clock lanes */ + if ((hdsi->Instance->PUCR & (DSI_PUCR_UEDL | DSI_PUCR_URDL | DSI_PUCR_UECL | DSI_PUCR_URCL)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that there are no Transmission trigger */ + if ((hdsi->Instance->PTTCR & DSI_PTTCR_TX_TRIG) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Verify that D-PHY PLL is locked */ + tickstart = HAL_GetTick(); + + while ((__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Verify that all active lanes are in Stop state */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | \ + DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_UAN1)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Clock lane configuration: no more HS request */ + hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC; + + /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */ + __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLL3); + + /* ULPS Request on Clock and Data Lanes */ + hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until all active lanes enter ULPM */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* Turn off the DSI PLL */ + __HAL_DSI_PLL_DISABLE(hdsi); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off + * (both data and clock lanes are in ULPM) + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Verify that all active lanes are in ULPM */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & (DSI_PSR_RUE0 | DSI_PSR_UAN0 | DSI_PSR_PSS0 | \ + DSI_PSR_UANC | DSI_PSR_PSSC | DSI_PSR_PD)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_RUE0 | DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_UAN1 | \ + DSI_PSR_PSS1 | DSI_PSR_UANC | DSI_PSR_PSSC | DSI_PSR_PD)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* Turn on the DSI PLL */ + __HAL_DSI_PLL_ENABLE(hdsi); + + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Exit ULPS on Clock and Data Lanes */ + hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until all active lanes exit ULPM */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC)) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | + DSI_PSR_UANC)) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* wait for 1 ms */ + HAL_Delay(1U); + + /* De-assert the ULPM requests and the ULPM exit bits */ + hdsi->Instance->PUCR = 0U; + + /* Switch the lane byte clock source in the RCC from system PLL to D-PHY */ + __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY); + + /* Restore clock lane configuration to HS */ + hdsi->Instance->CLCR |= DSI_CLCR_DPCC; + + /* Verify that D-PHY PLL is enabled */ + if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that all active lanes are in Stop state */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | \ + DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_UAN1)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that D-PHY PLL is locked */ + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Start test pattern generation + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Mode Pattern generator mode + * This parameter can be one of the following values: + * 0 : Color bars (horizontal or vertical) + * 1 : BER pattern (vertical only) + * @param Orientation Pattern generator orientation + * This parameter can be one of the following values: + * 0 : Vertical color bars + * 1 : Horizontal color bars + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Configure pattern generator mode and orientation */ + hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO); + hdsi->Instance->VMCR |= ((Mode << 20U) | (Orientation << 24U)); + + /* Enable pattern generator by setting PGE bit */ + hdsi->Instance->VMCR |= DSI_VMCR_PGE; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Stop test pattern generation + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Disable pattern generator by clearing PGE bit */ + hdsi->Instance->VMCR &= ~DSI_VMCR_PGE; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + + +/** + * @brief Custom lane pins configuration + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param CustomLane Function to be applied on selected lane. + * This parameter can be any value of @arg DSI_CustomLane + * @param Lane select between clock or data lane 0 or data lane 1. + * This parameter can be any value of @arg DSI_Lane_Select + * @param State ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, + FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_DSI_LANE(Lane)); + assert_param(IS_FUNCTIONAL_STATE(State)); + + switch (CustomLane) + { + case DSI_SWAP_LANE_PINS: + if (Lane == DSI_CLK_LANE) + { + /* Swap pins on clock lane */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U); + } + else if (Lane == DSI_DATA_LANE0) + { + /* Swap pins on data lane 0 */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U); + } + else if (Lane == DSI_DATA_LANE1) + { + /* Swap pins on data lane 1 */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + break; + default: + break; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + + +/** + * @brief Force the Clock/Data Lane in TX Stop Mode + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Lane select between clock or data lanes. + * This parameter can be any value of @arg DSI_Lane_Group + * @param State ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + if (Lane == DSI_CLOCK_LANE) + { + /* Force/Unforce the Clock Lane in TX Stop Mode */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 12U); + } + else if (Lane == DSI_DATA_LANES) + { + /* Force/Unforce the Data Lanes in TX Stop Mode */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 13U); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + + +/** + * @} + */ + +/** @defgroup DSI_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DSI state. + (+) Get error code. + +@endverbatim + * @{ + */ + +/** + * @brief Return the DSI state + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL state + */ +HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi) +{ + return hdsi->State; +} + +/** + * @brief Return the DSI error code + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval DSI Error Code + */ +uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi) +{ + /* Get the error code */ + return hdsi->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DSI */ + +#endif /* HAL_DSI_MODULE_ENABLED */ + +/** + * @} + */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dsi.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dsi.h new file mode 100644 index 00000000000..29a8e549ec4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_dsi.h @@ -0,0 +1,1445 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_dsi.h + * @author MCD Application Team + * @brief Header file of DSI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_DSI_H +#define STM32U5xx_HAL_DSI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +#if defined(DSI) + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup DSI DSI + * @brief DSI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DSI_Exported_Types DSI Exported Types + * @{ + */ +/** + * @brief DSI Init Structure definition + */ +typedef struct +{ + uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control + This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */ + + uint32_t TXEscapeCkdiv; /*!< TX Escape clock division + The values 0 and 1 stop the TX_ESC clock generation */ + + uint32_t NumberOfLanes; /*!< Number of lanes + This parameter can be any value of @ref DSI_Number_Of_Lanes */ + uint32_t PHYFrequencyRange; /*!< PHY Frequency Range + This parameter can be any value of @arg DSI_PHYFrequencyRange */ + + uint32_t PHYLowPowerOffset; /*!< PHY Low Power Offset + This parameter can be any value of @arg PHYLowPowerOffset */ + +} DSI_InitTypeDef; + +/** + * @brief DSI PLL Clock structure definition + */ +typedef struct +{ + uint32_t PLLNDIV; /*!< PLL Loop Division Factor + This parameter must be a value between 10 and 125 */ + + uint32_t PLLIDF; /*!< PLL Input Division Factor + This parameter can be any value of @ref DSI_PLL_IDF */ + + uint32_t PLLODF; /*!< PLL Output Division Factor + This parameter can be any value of @ref DSI_PLL_ODF */ + + uint32_t PLLVCORange; /*!< PLLVCORange + This parameter can be any value of @ref DSI_DPHY_VCO_Frequency_RANGE */ + + uint32_t PLLChargePump; /*!< PLLChargePump + This parameter can be any value of @ref DSI_PLL_Charge_Pump */ + + uint32_t PLLTuning; /*!< PLLTuning + This parameter can be any value of @ref DSI_PLL_Tuning */ + + +} DSI_PLLInitTypeDef; + +/** + * @brief DSI Video mode configuration + */ +typedef struct +{ + uint32_t VirtualChannelID; /*!< Virtual channel ID */ + + uint32_t ColorCoding; /*!< Color coding for LTDC interface + This parameter can be any value of @ref DSI_Color_Coding */ + + uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using + 18-bit configuration). + This parameter can be any value of @ref DSI_LooselyPacked */ + + uint32_t Mode; /*!< Video mode type + This parameter can be any value of @ref DSI_Video_Mode_Type */ + + uint32_t PacketSize; /*!< Video packet size */ + + uint32_t NumberOfChunks; /*!< Number of chunks */ + + uint32_t NullPacketSize; /*!< Null packet size */ + + uint32_t HSPolarity; /*!< HSYNC pin polarity + This parameter can be any value of @ref DSI_HSYNC_Polarity */ + + uint32_t VSPolarity; /*!< VSYNC pin polarity + This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ + + uint32_t DEPolarity; /*!< Data Enable pin polarity + This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ + + uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */ + + uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */ + + uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */ + + uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */ + + uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */ + + uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */ + + uint32_t VerticalActive; /*!< Vertical active duration */ + + uint32_t LPCommandEnable; /*!< Low-power command enable + This parameter can be any value of @ref DSI_LP_Command */ + + uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that + can fit in a line during VSA, VBP and VFP regions */ + + uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that + can fit in a line during VACT region */ + + uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable + This parameter can be any value of @ref DSI_LP_HFP */ + + uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable + This parameter can be any value of @ref DSI_LP_HBP */ + + uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable + This parameter can be any value of @ref DSI_LP_VACT */ + + uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable + This parameter can be any value of @ref DSI_LP_VFP */ + + uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable + This parameter can be any value of @ref DSI_LP_VBP */ + + uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable + This parameter can be any value of @ref DSI_LP_VSYNC */ + + uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable + This parameter can be any value of @ref DSI_FBTA_acknowledge */ + +} DSI_VidCfgTypeDef; + +/** + * @brief DSI Adapted command mode configuration + */ +typedef struct +{ + uint32_t VirtualChannelID; /*!< Virtual channel ID */ + + uint32_t ColorCoding; /*!< Color coding for LTDC interface + This parameter can be any value of @ref DSI_Color_Coding */ + + uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in + pixels. This parameter can be any value between 0x00 and 0xFFFFU */ + + uint32_t TearingEffectSource; /*!< Tearing effect source + This parameter can be any value of @ref DSI_TearingEffectSource */ + + uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity + This parameter can be any value of @ref DSI_TearingEffectPolarity */ + + uint32_t HSPolarity; /*!< HSYNC pin polarity + This parameter can be any value of @ref DSI_HSYNC_Polarity */ + + uint32_t VSPolarity; /*!< VSYNC pin polarity + This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ + + uint32_t DEPolarity; /*!< Data Enable pin polarity + This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ + + uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted + This parameter can be any value of @ref DSI_Vsync_Polarity */ + + uint32_t AutomaticRefresh; /*!< Automatic refresh mode + This parameter can be any value of @ref DSI_AutomaticRefresh */ + + uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable + This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */ + +} DSI_CmdCfgTypeDef; + +/** + * @brief DSI command transmission mode configuration + */ +typedef struct +{ + uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */ + + uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */ + + uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */ + + uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */ + + uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */ + + uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */ + + uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission + This parameter can be any value of @ref DSI_LP_LPGenLongWrite */ + + uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */ + + uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission + This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */ + + uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */ + + uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission + This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */ + + uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission + This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */ + + uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable + This parameter can be any value of @ref DSI_AcknowledgeRequest */ + +} DSI_LPCmdTypeDef; + +/** + * @brief DSI PHY Timings definition + */ +typedef struct +{ + uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed + to low-power transmission */ + + uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power + to high-speed transmission */ + + uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed + to low-power transmission */ + + uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power + to high-speed transmission */ + + uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */ + + uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the + Stop state */ + +} DSI_PHY_TimerTypeDef; + +/** + * @brief DSI HOST Timeouts definition + */ +typedef struct +{ + uint32_t TimeoutCkdiv; /*!< Time-out clock division */ + + uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out */ + + uint32_t LowPowerReceptionTimeout; /*!< Low-power reception time-out */ + + uint32_t HighSpeedReadTimeout; /*!< High-speed read time-out */ + + uint32_t LowPowerReadTimeout; /*!< Low-power read time-out */ + + uint32_t HighSpeedWriteTimeout; /*!< High-speed write time-out */ + + uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode + This parameter can be any value of @ref DSI_HS_PrespMode */ + + uint32_t LowPowerWriteTimeout; /*!< Low-speed write time-out */ + + uint32_t BTATimeout; /*!< BTA time-out */ + +} DSI_HOST_TimeoutTypeDef; + +/** + * @brief DSI States Structure definition + */ +typedef enum +{ + HAL_DSI_STATE_RESET = 0x00U, + HAL_DSI_STATE_READY = 0x01U, + HAL_DSI_STATE_ERROR = 0x02U, + HAL_DSI_STATE_BUSY = 0x03U, + HAL_DSI_STATE_TIMEOUT = 0x04U +} HAL_DSI_StateTypeDef; + +/** + * @brief DSI Handle Structure definition + */ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) +typedef struct __DSI_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ +{ + DSI_TypeDef *Instance; /*!< Register base address */ + DSI_InitTypeDef Init; /*!< DSI required parameters */ + HAL_LockTypeDef Lock; /*!< DSI peripheral status */ + __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */ + __IO uint32_t ErrorCode; /*!< DSI Error code */ + uint32_t ErrorMsk; /*!< DSI Error monitoring mask */ + +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + void (* TearingEffectCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Tearing Effect Callback */ + void (* EndOfRefreshCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI End Of Refresh Callback */ + void (* ErrorCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Error Callback */ + + void (* MspInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp Init callback */ + void (* MspDeInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp DeInit callback */ + +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ + +} DSI_HandleTypeDef; + +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) +/** + * @brief HAL DSI Callback ID enumeration definition + */ +typedef enum +{ + HAL_DSI_MSPINIT_CB_ID = 0x00U, /*!< DSI MspInit callback ID */ + HAL_DSI_MSPDEINIT_CB_ID = 0x01U, /*!< DSI MspDeInit callback ID */ + + HAL_DSI_TEARING_EFFECT_CB_ID = 0x02U, /*!< DSI Tearing Effect Callback ID */ + HAL_DSI_ENDOF_REFRESH_CB_ID = 0x03U, /*!< DSI End Of Refresh Callback ID */ + HAL_DSI_ERROR_CB_ID = 0x04U /*!< DSI Error Callback ID */ + +} HAL_DSI_CallbackIDTypeDef; + +/** + * @brief HAL DSI Callback pointer definition + */ +typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to an DSI callback function */ + +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DSI_Exported_Constants DSI Exported Constants + * @{ + */ +/** @defgroup DSI_DCS_Command DSI DCS Command + * @{ + */ +#define DSI_ENTER_IDLE_MODE 0x39U +#define DSI_ENTER_INVERT_MODE 0x21U +#define DSI_ENTER_NORMAL_MODE 0x13U +#define DSI_ENTER_PARTIAL_MODE 0x12U +#define DSI_ENTER_SLEEP_MODE 0x10U +#define DSI_EXIT_IDLE_MODE 0x38U +#define DSI_EXIT_INVERT_MODE 0x20U +#define DSI_EXIT_SLEEP_MODE 0x11U +#define DSI_GET_3D_CONTROL 0x3FU +#define DSI_GET_ADDRESS_MODE 0x0BU +#define DSI_GET_BLUE_CHANNEL 0x08U +#define DSI_GET_DIAGNOSTIC_RESULT 0x0FU +#define DSI_GET_DISPLAY_MODE 0x0DU +#define DSI_GET_GREEN_CHANNEL 0x07U +#define DSI_GET_PIXEL_FORMAT 0x0CU +#define DSI_GET_POWER_MODE 0x0AU +#define DSI_GET_RED_CHANNEL 0x06U +#define DSI_GET_SCANLINE 0x45U +#define DSI_GET_SIGNAL_MODE 0x0EU +#define DSI_NOP 0x00U +#define DSI_READ_DDB_CONTINUE 0xA8U +#define DSI_READ_DDB_START 0xA1U +#define DSI_READ_MEMORY_CONTINUE 0x3EU +#define DSI_READ_MEMORY_START 0x2EU +#define DSI_SET_3D_CONTROL 0x3DU +#define DSI_SET_ADDRESS_MODE 0x36U +#define DSI_SET_COLUMN_ADDRESS 0x2AU +#define DSI_SET_DISPLAY_OFF 0x28U +#define DSI_SET_DISPLAY_ON 0x29U +#define DSI_SET_GAMMA_CURVE 0x26U +#define DSI_SET_PAGE_ADDRESS 0x2BU +#define DSI_SET_PARTIAL_COLUMNS 0x31U +#define DSI_SET_PARTIAL_ROWS 0x30U +#define DSI_SET_PIXEL_FORMAT 0x3AU +#define DSI_SET_SCROLL_AREA 0x33U +#define DSI_SET_SCROLL_START 0x37U +#define DSI_SET_TEAR_OFF 0x34U +#define DSI_SET_TEAR_ON 0x35U +#define DSI_SET_TEAR_SCANLINE 0x44U +#define DSI_SET_VSYNC_TIMING 0x40U +#define DSI_SOFT_RESET 0x01U +#define DSI_WRITE_LUT 0x2DU +#define DSI_WRITE_MEMORY_CONTINUE 0x3CU +#define DSI_WRITE_MEMORY_START 0x2CU +/** + * @} + */ + +/** @defgroup DSI_Video_Mode_Type DSI Video Mode Type + * @{ + */ +#define DSI_VID_MODE_NB_PULSES 0U +#define DSI_VID_MODE_NB_EVENTS 1U +#define DSI_VID_MODE_BURST 2U +/** + * @} + */ + +/** @defgroup DSI_Color_Mode DSI Color Mode + * @{ + */ +#define DSI_COLOR_MODE_FULL 0x00000000U +#define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM +/** + * @} + */ + +/** @defgroup DSI_ShutDown DSI ShutDown + * @{ + */ +#define DSI_DISPLAY_ON 0x00000000U +#define DSI_DISPLAY_OFF DSI_WCR_SHTDN +/** + * @} + */ + +/** @defgroup DSI_LP_Command DSI LP Command + * @{ + */ +#define DSI_LP_COMMAND_DISABLE 0x00000000U +#define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE +/** + * @} + */ + +/** @defgroup DSI_LP_HFP DSI LP HFP + * @{ + */ +#define DSI_LP_HFP_DISABLE 0x00000000U +#define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE +/** + * @} + */ + +/** @defgroup DSI_LP_HBP DSI LP HBP + * @{ + */ +#define DSI_LP_HBP_DISABLE 0x00000000U +#define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE +/** + * @} + */ + +/** @defgroup DSI_LP_VACT DSI LP VACT + * @{ + */ +#define DSI_LP_VACT_DISABLE 0x00000000U +#define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE +/** + * @} + */ + +/** @defgroup DSI_LP_VFP DSI LP VFP + * @{ + */ +#define DSI_LP_VFP_DISABLE 0x00000000U +#define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE +/** + * @} + */ + +/** @defgroup DSI_LP_VBP DSI LP VBP + * @{ + */ +#define DSI_LP_VBP_DISABLE 0x00000000U +#define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE +/** + * @} + */ + +/** @defgroup DSI_LP_VSYNC DSI LP VSYNC + * @{ + */ +#define DSI_LP_VSYNC_DISABLE 0x00000000U +#define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE +/** + * @} + */ + +/** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge + * @{ + */ +#define DSI_FBTAA_DISABLE 0x00000000U +#define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE +/** + * @} + */ + +/** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source + * @{ + */ +#define DSI_TE_DSILINK 0x00000000U +#define DSI_TE_EXTERNAL DSI_WCFGR_TESRC +/** + * @} + */ + +/** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity + * @{ + */ +#define DSI_TE_RISING_EDGE 0x00000000U +#define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL +/** + * @} + */ + +/** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity + * @{ + */ +#define DSI_VSYNC_FALLING 0x00000000U +#define DSI_VSYNC_RISING DSI_WCFGR_VSPOL +/** + * @} + */ + +/** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh + * @{ + */ +#define DSI_AR_DISABLE 0x00000000U +#define DSI_AR_ENABLE DSI_WCFGR_AR +/** + * @} + */ + +/** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request + * @{ + */ +#define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U +#define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE +/** + * @} + */ + +/** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request + * @{ + */ +#define DSI_ACKNOWLEDGE_DISABLE 0x00000000U +#define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP + * @{ + */ +#define DSI_LP_GSW0P_DISABLE 0x00000000U +#define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP + * @{ + */ +#define DSI_LP_GSW1P_DISABLE 0x00000000U +#define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP + * @{ + */ +#define DSI_LP_GSW2P_DISABLE 0x00000000U +#define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP + * @{ + */ +#define DSI_LP_GSR0P_DISABLE 0x00000000U +#define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP + * @{ + */ +#define DSI_LP_GSR1P_DISABLE 0x00000000U +#define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP + * @{ + */ +#define DSI_LP_GSR2P_DISABLE 0x00000000U +#define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite + * @{ + */ +#define DSI_LP_GLW_DISABLE 0x00000000U +#define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP + * @{ + */ +#define DSI_LP_DSW0P_DISABLE 0x00000000U +#define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP + * @{ + */ +#define DSI_LP_DSW1P_DISABLE 0x00000000U +#define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP + * @{ + */ +#define DSI_LP_DSR0P_DISABLE 0x00000000U +#define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write + * @{ + */ +#define DSI_LP_DLW_DISABLE 0x00000000U +#define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX +/** + * @} + */ + +/** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet + * @{ + */ +#define DSI_LP_MRDP_DISABLE 0x00000000U +#define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS +/** + * @} + */ + +/** @defgroup DSI_HS_PrespMode DSI HS Presp Mode + * @{ + */ +#define DSI_HS_PM_DISABLE 0x00000000U +#define DSI_HS_PM_ENABLE DSI_TCCR3_PM +/** + * @} + */ + + +/** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control + * @{ + */ +#define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U +#define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR +/** + * @} + */ + +/** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes + * @{ + */ +#define DSI_ONE_DATA_LANE 0U +#define DSI_TWO_DATA_LANES 1U +/** + * @} + */ + +/** @defgroup DSI_FlowControl DSI Flow Control + * @{ + */ +#define DSI_FLOW_CONTROL_EOTP_TX_LP DSI_PCR_ETTXLPE +#define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE +#define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE +#define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE +#define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE +#define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE +#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \ + DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \ + DSI_FLOW_CONTROL_EOTP_TX | DSI_FLOW_CONTROL_EOTP_TX_LP) +/** + * @} + */ + +/** @defgroup DSI_Color_Coding DSI Color Coding + * @{ + */ +#define DSI_RGB565 0x00000000U /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */ +#define DSI_RGB666 0x00000003U /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */ +#define DSI_RGB888 0x00000005U +/** + * @} + */ + +/** @defgroup DSI_LooselyPacked DSI Loosely Packed + * @{ + */ +#define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE +#define DSI_LOOSELY_PACKED_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity + * @{ + */ +#define DSI_HSYNC_ACTIVE_HIGH 0x00000000U +#define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP +/** + * @} + */ + +/** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity + * @{ + */ +#define DSI_VSYNC_ACTIVE_HIGH 0x00000000U +#define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP +/** + * @} + */ + +/** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity + * @{ + */ +#define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U +#define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP +/** + * @} + */ + +/** @defgroup DSI_PLL_IDF DSI PLL IDF + * @{ + */ +#define DSI_PLL_IN_DIV1 0x00000001U +#define DSI_PLL_IN_DIV2 0x00000002U +#define DSI_PLL_IN_DIV3 0x00000003U +#define DSI_PLL_IN_DIV4 0x00000004U +#define DSI_PLL_IN_DIV5 0x00000005U +#define DSI_PLL_IN_DIV6 0x00000006U +#define DSI_PLL_IN_DIV7 0x00000007U +/** + * @} + */ + +/** @defgroup DSI_PLL_ODF DSI PLL ODF + * @{ + */ +#define DSI_PLL_OUT_DIV1 0x00000001U +#define DSI_PLL_OUT_DIV2 0x00000002U +#define DSI_PLL_OUT_DIV3 0x00000003U +#define DSI_PLL_OUT_DIV4 0x00000004U +#define DSI_PLL_OUT_DIV5 0x00000005U +#define DSI_PLL_OUT_DIV6 0x00000006U +#define DSI_PLL_OUT_DIV7 0x00000007U +#define DSI_PLL_OUT_DIV8 0x00000008U +#define DSI_PLL_OUT_DIV9 0x00000009U +/** + * @} + */ + +/** @defgroup DSI_Flags DSI Flags + * @{ + */ +#define DSI_FLAG_TE DSI_WISR_TEIF +#define DSI_FLAG_ER DSI_WISR_ERIF +#define DSI_FLAG_BUSY DSI_WISR_BUSY +#define DSI_FLAG_PLLLS DSI_WISR_PLLLS +#define DSI_FLAG_PLLL DSI_WISR_PLLLIF +#define DSI_FLAG_PLLU DSI_WISR_PLLUIF +/** + * @} + */ + +/** @defgroup DSI_Interrupts DSI Interrupts + * @{ + */ +#define DSI_IT_TE DSI_WIER_TEIE +#define DSI_IT_ER DSI_WIER_ERIE +#define DSI_IT_PLLL DSI_WIER_PLLLIE +#define DSI_IT_PLLU DSI_WIER_PLLUIE +/** + * @} + */ + +/** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type + * @{ + */ +#define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U /*!< DCS short write, no parameters */ +#define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U /*!< DCS short write, one parameter */ +#define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U /*!< Generic short write, no parameters */ +#define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U /*!< Generic short write, one parameter */ +#define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U /*!< Generic short write, two parameters */ +/** + * @} + */ + +/** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type + * @{ + */ +#define DSI_DCS_LONG_PKT_WRITE 0x00000039U /*!< DCS long write */ +#define DSI_GEN_LONG_PKT_WRITE 0x00000029U /*!< Generic long write */ +/** + * @} + */ + +/** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type + * @{ + */ +#define DSI_DCS_SHORT_PKT_READ 0x00000006U /*!< DCS short read */ +#define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U /*!< Generic short read, no parameters */ +#define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U /*!< Generic short read, one parameter */ +#define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U /*!< Generic short read, two parameters */ +/** + * @} + */ + +/** @defgroup DSI_Error_Data_Type DSI Error Data Type + * @{ + */ +#define HAL_DSI_ERROR_NONE 0U +#define HAL_DSI_ERROR_ACK 0x00000001U /*!< Acknowledge errors */ +#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */ +#define HAL_DSI_ERROR_TX 0x00000004U /*!< Transmission error */ +#define HAL_DSI_ERROR_RX 0x00000008U /*!< Reception error */ +#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */ +#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */ +#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */ +#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */ +#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */ +#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */ +#define HAL_DSI_ERROR_PBU 0x00000400U /*!< Payload Buffer Underflow error */ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) +#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000800U /*!< DSI Invalid Callback error */ +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup DSI_Lane_Group DSI Lane Group + * @{ + */ +#define DSI_CLOCK_LANE 0x00000000U +#define DSI_DATA_LANES 0x00000001U +/** + * @} + */ + + +/** @defgroup DSI_CustomLane DSI CustomLane + * @{ + */ +#define DSI_SWAP_LANE_PINS 0x00000000U +/** + * @} + */ + +/** @defgroup DSI_Lane_Select DSI Lane Select + * @{ + */ +#define DSI_CLK_LANE 0x00000000U +#define DSI_DATA_LANE0 0x00000001U +#define DSI_DATA_LANE1 0x00000002U +/** + * @} + */ + + +/** @defgroup DSI_DPHY_VCO_Frequency_RANGE DSI DPHY VCO Frequency Range + * @{ + */ +#define DSI_DPHY_VCO_FRANGE_500MHZ_800MHZ 0x00000000U /*!< 500-800 MHz */ +#define DSI_DPHY_VCO_FRANGE_800MHZ_1GHZ 0x00000001U /*!< 800-1000 MHz */ +/** + * @} + */ + + +/** @defgroup DSI_PHYFrequencyRange DSI DPHY Frequency Range + * @{ + */ +#define DSI_DPHY_FRANGE_80MHZ_100MHZ 0x00000000U /*!< 80-100 MHz */ +#define DSI_DPHY_FRANGE_100MHZ_120MHZ 0x00000001U /*!< 100-120 MHz */ +#define DSI_DPHY_FRANGE_120MHZ_160MHZ 0x00000002U /*!< 120-160 MHz */ +#define DSI_DPHY_FRANGE_160MHZ_200MHZ 0x00000003U /*!< 160-200 MHz */ +#define DSI_DPHY_FRANGE_200MHZ_240MHZ 0x00000004U /*!< 200-240 MHz */ +#define DSI_DPHY_FRANGE_240MHZ_320MHZ 0x00000005U /*!< 240-320 MHz */ +#define DSI_DPHY_FRANGE_320MHZ_390MHZ 0x00000006U /*!< 320-390 MHz */ +#define DSI_DPHY_FRANGE_390MHZ_450MHZ 0x00000007U /*!< 390-450 MHz */ +#define DSI_DPHY_FRANGE_450MHZ_510MHZ 0x00000008U /*!< 450-510 MHz */ + +/** + * @} + */ + +/** @defgroup DSI_DPHY_Slew_Rate DSI D-PHY Slew rate + * @{ + */ +#define DSI_DPHY_SLEW_HS_TX_SPEED 0x0000000EU /*!< 80-750Mbits/s */ +/** + * @} + */ + +/** @defgroup DSI_HS_PREPARE_Offset DSI HS Prepare Offset + * @{ + */ +#define DSI_HS_PREPARE_OFFSET0 0x00000000U /*!< 100-120 & 120-160 & 240-320 MHz */ +#define DSI_HS_PREPARE_OFFSET1 0x00000001U /*!< 80-100 & 160-200 & 200-240 & 320-390 MHz */ +#define DSI_HS_PREPARE_OFFSET2 0x00000002U /*!< 390-450 & 450-510 MHz */ +/** + * @} + */ + +/** @defgroup DSI_PHYLowPowerOffset DSI PHY Low Power Offset + * @{ + */ +#define PHY_LP_OFFSSET_0_CLKP 0x00000000U +#define PHY_LP_OFFSSET_1_CLKP 0x00000001U +#define PHY_LP_OFFSSET_2_CLKP 0x00000002U +#define PHY_LP_OFFSSET_3_CLKP 0x00000003U +#define PHY_LP_OFFSSET_4_CLKP 0x00000004U +#define PHY_LP_OFFSSET_5_CLKP 0x00000005U +#define PHY_LP_OFFSSET_6_CLKP 0x00000006U +#define PHY_LP_OFFSSET_7_CLKP 0x00000007U +#define PHY_LP_OFFSSET_MINUS_1_CLKP 0x00000008U +#define PHY_LP_OFFSSET_MINUS_2_CLKP 0x00000009U +#define PHY_LP_OFFSSET_MINUS_3_CLKP 0x0000000AU +#define PHY_LP_OFFSSET_MINUS_4_CLKP 0x0000000BU +#define PHY_LP_OFFSSET_MINUS_5_CLKP 0x0000000CU +#define PHY_LP_OFFSSET_MINUS_6_CLKP 0x0000000DU +#define PHY_LP_OFFSSET_MINUS_7_CLKP 0x0000000EU +#define PHY_LP_OFFSSET_MINUS_8_CLKP 0x0000000FU +/** + * @} + */ + + +/** @defgroup DSI_PLL_Tuning DSI PLL Tuning + * @{ + */ +#define DSI_PLL_LOOP_FILTER_2000HZ_4400HZ 0x00000000U /*!< 2.0 to 4.4 MHz */ +#define DSI_PLL_LOOP_FILTER_4400HZ_30900HZ 0x00000001U /*!< 4.4 to 30.9 MHz */ +#define DSI_PLL_LOOP_FILTER_30900HZ_50000HZ 0x00000002U /*!< 30.9 to 50 MHz */ + +/** + * @} + */ + +/** @defgroup DSI_PLL_Charge_Pump DSI PLL Charge pump + * @{ + */ +#define DSI_PLL_CHARGE_PUMP_2000HZ_4400HZ 0x00000000U /*!< 2.0 to 4.4 MHz */ +#define DSI_PLL_CHARGE_PUMP_4400HZ_14100HZ 0x00000001U /*!< 4.4 to 14.1 MHz */ +#define DSI_PLL_CHARGE_PUMP_14100HZ_30900HZ 0x00000000U /*!< 14.1 to 30.9 MHz */ +#define DSI_PLL_CHARGE_PUMP_30900HZ_45700HZ 0x00000003U /*!< 30.9 to 45.7 MHz */ +#define DSI_PLL_CHARGE_PUMP_45700HZ_50000HZ 0x00000002U /*!< 45.7 to 50 MHz */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup DSI_Exported_Macros DSI Exported Macros + * @{ + */ + +/** + * @brief Reset DSI handle state. + * @param __HANDLE__ DSI handle + * @retval None + */ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) +#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_DSI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET) +#endif /*USE_HAL_DSI_REGISTER_CALLBACKS */ + +/** + * @brief Enables the DSI host. + * @param __HANDLE__ DSI handle + * @retval None. + */ +#define __HAL_DSI_ENABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + /* Delay after an DSI Host enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + UNUSED(tmpreg); \ + } while(0U) + +/** + * @brief Disables the DSI host. + * @param __HANDLE__ DSI handle + * @retval None. + */ +#define __HAL_DSI_DISABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + /* Delay after an DSI Host disabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + UNUSED(tmpreg); \ + } while(0U) + +/** + * @brief Enables the DSI wrapper. + * @param __HANDLE__ DSI handle + * @retval None. + */ +#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + /* Delay after an DSI wrapper enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + UNUSED(tmpreg); \ + } while(0U) + +/** + * @brief Disable the DSI wrapper. + * @param __HANDLE__ DSI handle + * @retval None. + */ +#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + /* Delay after an DSI wrapper disabling*/ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + UNUSED(tmpreg); \ + } while(0U) + +/** + * @brief Enables the DSI PLL. + * @param __HANDLE__ DSI handle + * @retval None. + */ +#define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + /* Delay after an DSI PLL enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + UNUSED(tmpreg); \ + } while(0U) + +/** + * @brief Disables the DSI PLL. + * @param __HANDLE__ DSI handle + * @retval None. + */ +#define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + /* Delay after an DSI PLL disabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + UNUSED(tmpreg); \ + } while(0U) + + +/** + * @brief Get the DSI pending flags. + * @param __HANDLE__ DSI handle. + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag + * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag + * @arg DSI_FLAG_BUSY : Busy Flag + * @arg DSI_FLAG_PLLLS: PLL Lock Status + * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag + * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag + * @arg DSI_FLAG_RRS : Regulator Ready Flag + * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__)) + +/** + * @brief Clears the DSI pending flags. + * @param __HANDLE__ DSI handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag + * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag + * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag + * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag + * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag + * @retval None + */ +#define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__)) + +/** + * @brief Enables the specified DSI interrupts. + * @param __HANDLE__ DSI handle. + * @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg DSI_IT_TE : Tearing Effect Interrupt + * @arg DSI_IT_ER : End of Refresh Interrupt + * @arg DSI_IT_PLLL: PLL Lock Interrupt + * @arg DSI_IT_PLLU: PLL Unlock Interrupt + * @arg DSI_IT_RR : Regulator Ready Interrupt + * @retval None + */ +#define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified DSI interrupts. + * @param __HANDLE__ DSI handle + * @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg DSI_IT_TE : Tearing Effect Interrupt + * @arg DSI_IT_ER : End of Refresh Interrupt + * @arg DSI_IT_PLLL: PLL Lock Interrupt + * @arg DSI_IT_PLLU: PLL Unlock Interrupt + * @arg DSI_IT_RR : Regulator Ready Interrupt + * @retval None + */ +#define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified DSI interrupt source is enabled or not. + * @param __HANDLE__ DSI handle + * @param __INTERRUPT__ specifies the DSI interrupt source to check. + * This parameter can be one of the following values: + * @arg DSI_IT_TE : Tearing Effect Interrupt + * @arg DSI_IT_ER : End of Refresh Interrupt + * @arg DSI_IT_PLLL: PLL Lock Interrupt + * @arg DSI_IT_PLLU: PLL Unlock Interrupt + * @arg DSI_IT_RR : Regulator Ready Interrupt + * @retval The state of INTERRUPT (SET or RESET). + */ +#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DSI_Exported_Functions DSI Exported Functions + * @{ + */ +/** @defgroup DSI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * @{ + */ +HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit); +HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi); +void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi); +void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID, + pDSI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup DSI_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi); +void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi); +void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi); +void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi); +/** + * @} + */ + +/** @defgroup DSI_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_DSI_SetGenericVCIDRX(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelIdRx); +HAL_StatusTypeDef HAL_DSI_SetGenericVCIDTX(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelIdTx); +HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID); +HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg); +HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg); +HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd); +HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl); +HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers); +HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts); +HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode); +HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown); +HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t Param1, + uint32_t Param2); +HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t NbParams, + uint32_t Param1, + uint8_t *ParametersTable); +HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, + uint32_t ChannelNbr, + uint8_t *Array, + uint32_t Size, + uint32_t Mode, + uint32_t DCSCmd, + uint8_t *ParametersTable); +HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi); + +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation); +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi); + +HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, + FunctionalState State); +HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State); + +/** + * @} + */ + +/** @defgroup DSI_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * @{ + */ +uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi); +HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DSI_Private_Constants DSI Private Constants + * @{ + */ +#define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /*!< Maximum return packet configuration */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DSI_Private_Macros DSI Private Macros + * @{ + */ +#define IS_DSI_PLL_NDIV(NDIV) ((NDIV) <= 511U) +#define IS_DSI_PLL_IDF(IDF) ((IDF) <= 511U) +#define IS_DSI_PLL_ODF(ODF) ((ODF) <= 511U) +#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE)\ + || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE)) +#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE)\ + || ((NumberOfLanes) == DSI_TWO_DATA_LANES)) +#define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL) +#define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U) +#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE)\ + || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE)) +#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH)\ + || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW)) +#define IS_DSI_VSYNC_POLARITY(Vsync) (((Vsync) == DSI_VSYNC_ACTIVE_HIGH)\ + || ((Vsync) == DSI_VSYNC_ACTIVE_LOW)) +#define IS_DSI_HSYNC_POLARITY(Hsync) (((Hsync) == DSI_HSYNC_ACTIVE_HIGH)\ + || ((Hsync) == DSI_HSYNC_ACTIVE_LOW)) +#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \ + ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \ + ((VideoModeType) == DSI_VID_MODE_BURST)) +#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL)\ + || ((ColorMode) == DSI_COLOR_MODE_EIGHT)) +#define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF)) +#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE)\ + || ((LPCommand) == DSI_LP_COMMAND_ENABLE)) +#define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE)) +#define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE)) +#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE)\ + || ((LPVActive) == DSI_LP_VACT_ENABLE)) +#define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE)) +#define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE)) +#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE)\ + || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE)) +#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE)\ + || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE)) +#define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL)) +#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE)\ + || ((TEPolarity) == DSI_TE_FALLING_EDGE)) +#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE)\ + || ((AutomaticRefresh) == DSI_AR_ENABLE)) +#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING)\ + || ((VSPolarity) == DSI_VSYNC_RISING)) +#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE)\ + || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE)) +#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE)\ + || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE)) +#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE)\ + || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE)) +#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE)\ + || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE)) +#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE)\ + || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE)) +#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE)\ + || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE)) +#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE)\ + || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE)) +#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE)\ + || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE)) +#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE)\ + || ((LP_GLW) == DSI_LP_GLW_ENABLE)) +#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE)\ + || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE)) +#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE)\ + || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE)) +#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE)\ + || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE)) +#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE)\ + || ((LP_DLW) == DSI_LP_DLW_ENABLE)) +#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE)\ + || ((LP_MRDP) == DSI_LP_MRDP_ENABLE)) +#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \ + ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \ + ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \ + ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \ + ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2)) +#define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \ + ((MODE) == DSI_GEN_LONG_PKT_WRITE)) +#define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \ + ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \ + ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \ + ((MODE) == DSI_GEN_SHORT_PKT_READ_P2)) +#define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES)) +#define IS_DSI_CUSTOM_LANE(CustomLane) ((CustomLane) == DSI_SWAP_LANE_PINS) +#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || \ + ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1)) + +#define IS_DSI_DPHY_VCO_FREQUENCY_RANGE(VCOFreqRange) (((VCOFreqRange) == DSI_DPHY_VCO_FRANGE_500MHZ_800MHZ) ||\ + ((VCOFreqRange) == DSI_DPHY_VCO_FRANGE_800MHZ_1GHZ)) + +#define IS_DSI_DPHY_BAND_CTL_FRANGE(PHYFrequencyRange) (((PHYFrequencyRange) == DSI_DPHY_FRANGE_80MHZ_100MHZ) ||\ + ((PHYFrequencyRange) == DSI_DPHY_FRANGE_100MHZ_120MHZ) ||\ + ((PHYFrequencyRange) == DSI_DPHY_FRANGE_120MHZ_160MHZ) ||\ + ((PHYFrequencyRange) == DSI_DPHY_FRANGE_160MHZ_200MHZ) ||\ + ((PHYFrequencyRange) == DSI_DPHY_FRANGE_200MHZ_240MHZ) ||\ + ((PHYFrequencyRange) == DSI_DPHY_FRANGE_240MHZ_320MHZ) ||\ + ((PHYFrequencyRange) == DSI_DPHY_FRANGE_320MHZ_390MHZ) ||\ + ((PHYFrequencyRange) == DSI_DPHY_FRANGE_390MHZ_450MHZ) ||\ + ((PHYFrequencyRange) == DSI_DPHY_FRANGE_450MHZ_510MHZ)) +#define IS_DSI_DPHY_LOW_POWER_OFFSET(PHYLowPowerOffset)(((PHYLowPowerOffset) == PHY_LP_OFFSSET_0_CLKP) ||\ + ((PHYLowPowerOffset) == PHY_LP_OFFSSET_1_CLKP) ||\ + ((PHYLowPowerOffset) == PHY_LP_OFFSSET_2_CLKP) ||\ + ((PHYLowPowerOffset) == PHY_LP_OFFSSET_3_CLKP) ||\ + ((PHYLowPowerOffset) == PHY_LP_OFFSSET_4_CLKP) ||\ + ((PHYLowPowerOffset) == PHY_LP_OFFSSET_5_CLKP) ||\ + ((PHYLowPowerOffset) == PHY_LP_OFFSSET_6_CLKP) ||\ + ((PHYLowPowerOffset) == PHY_LP_OFFSSET_7_CLKP) ||\ + ((PHYLowPowerOffset) == PHY_LP_OFFSSET_MINUS_1_CLKP) ||\ + ((PHYLowPowerOffset) == PHY_LP_OFFSSET_MINUS_2_CLKP) ||\ + ((PHYLowPowerOffset) == PHY_LP_OFFSSET_MINUS_3_CLKP) ||\ + ((PHYLowPowerOffset) == PHY_LP_OFFSSET_MINUS_4_CLKP) ||\ + ((PHYLowPowerOffset) == PHY_LP_OFFSSET_MINUS_5_CLKP) ||\ + ((PHYLowPowerOffset) == PHY_LP_OFFSSET_MINUS_6_CLKP) ||\ + ((PHYLowPowerOffset) == PHY_LP_OFFSSET_MINUS_7_CLKP) ||\ + ((PHYLowPowerOffset) == PHY_LP_OFFSSET_MINUS_8_CLKP)) +#define IS_DSI_PLL_TUNING(PllTuning) (((PllTuning) == DSI_PLL_LOOP_FILTER_2000HZ_4400HZ) || \ + ((PllTuning) == DSI_PLL_LOOP_FILTER_4400HZ_30900HZ) || \ + ((PllTuning) == DSI_PLL_LOOP_FILTER_30900HZ_50000HZ)) + + +#define IS_DSI_PLL_CHARGEPUMP(PllChargePump) (((PllChargePump) == DSI_PLL_CHARGE_PUMP_2000HZ_4400HZ) || \ + ((PllChargePump) == DSI_PLL_CHARGE_PUMP_4400HZ_14100HZ) || \ + ((PllChargePump) == DSI_PLL_CHARGE_PUMP_14100HZ_30900HZ) || \ + ((PllChargePump) == DSI_PLL_CHARGE_PUMP_30900HZ_45700HZ) || \ + ((PllChargePump) == DSI_PLL_CHARGE_PUMP_45700HZ_50000HZ)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* DSI */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_DSI_H */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_exti.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_exti.c index c1954d35455..f629c3b1679 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_exti.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_exti.c @@ -259,7 +259,7 @@ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT */ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) { - __IO uint32_t *regaddr; + const __IO uint32_t *regaddr; uint32_t regval; uint32_t linepos; uint32_t maskline; @@ -351,7 +351,7 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT * @param hexti Exti handle. * @retval HAL Status. */ -HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t regval; @@ -494,7 +494,7 @@ HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLin * @param hexti Exti handle. * @retval none. */ -void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t regval; @@ -548,9 +548,9 @@ void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) * @arg @ref EXTI_TRIGGER_FALLING * @retval 1 if interrupt is pending else 0. */ -uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) { - __IO uint32_t *regaddr; + const __IO uint32_t *regaddr; uint32_t regval; uint32_t linepos; uint32_t maskline; @@ -592,7 +592,7 @@ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) * @arg @ref EXTI_TRIGGER_FALLING * @retval None. */ -void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) { __IO uint32_t *regaddr; uint32_t maskline; @@ -628,7 +628,7 @@ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) * @param hexti Exti handle. * @retval None. */ -void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t maskline; @@ -754,7 +754,7 @@ void HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes) */ HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes) { - __IO uint32_t *regaddr; + const __IO uint32_t *regaddr; uint32_t linepos; uint32_t maskline; uint32_t offset; @@ -807,6 +807,25 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t * return HAL_OK; } +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock the secure and privilege configuration registers. + * @retval None + */ +void HAL_EXTI_LockAttributes(void) +{ + SET_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK); +} + +/** + * @brief Return the secure and privilege configuration registers LOCK status + * @retval 1 if the secure and privilege configuration registers have been locked else 0. + */ +uint32_t HAL_EXTI_GetLockAttributes(void) +{ + return READ_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK); +} +#endif /* __ARM_FEATURE_CMSE */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_exti.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_exti.h index 7fd63183018..13afdd2da3d 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_exti.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_exti.h @@ -104,12 +104,21 @@ typedef struct #define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0EU) #define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0FU) #define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10U) -#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | 0x11U) -#define EXTI_LINE_18 (EXTI_DIRECT | EXTI_REG1 | 0x12U) -#define EXTI_LINE_19 (EXTI_DIRECT | EXTI_REG1 | 0x13U) -#define EXTI_LINE_20 (EXTI_DIRECT | EXTI_REG1 | 0x14U) +#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11U) +#if defined(EXTI_IMR1_IM18) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | 0x12U) +#endif /* EXTI_IMR1_IM18 */ +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | 0x13U) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14U) #define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | 0x15U) #define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | 0x16U) +#define EXTI_LINE_23 (EXTI_CONFIG | EXTI_REG1 | 0x17U) +#if defined(EXTI_IMR1_IM24) +#define EXTI_LINE_24 (EXTI_CONFIG | EXTI_REG1 | 0x18U) +#endif /* EXTI_IMR1_IM24 */ +#if defined(EXTI_IMR1_IM25) +#define EXTI_LINE_25 (EXTI_CONFIG | EXTI_REG1 | 0x19U) +#endif /* EXTI_IMR1_IM25 */ /** * @} */ @@ -144,10 +153,18 @@ typedef struct #define EXTI_GPIOC 0x00000002U #define EXTI_GPIOD 0x00000003U #define EXTI_GPIOE 0x00000004U +#if defined(GPIOF) #define EXTI_GPIOF 0x00000005U +#endif /* GPIOF */ #define EXTI_GPIOG 0x00000006U #define EXTI_GPIOH 0x00000007U +#if defined(GPIOI) #define EXTI_GPIOI 0x00000008U +#endif /* GPIOI */ +#if defined(GPIOJ) +#define EXTI_GPIOJ 0x00000009U +#endif /* GPIOJ */ + /** * @} */ @@ -213,7 +230,11 @@ typedef struct /** * @brief EXTI Line number */ -#define EXTI_LINE_NB 23U +#if defined(EXTI_IMR1_IM24) && defined(EXTI_IMR1_IM25) +#define EXTI_LINE_NB 26U +#else +#define EXTI_LINE_NB 24U +#endif /* defined(EXTI_IMR1_IM24) && defined(EXTI_IMR1_IM25) */ /** * @brief EXTI Mask for secure & privilege attributes @@ -246,6 +267,18 @@ typedef struct #define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U) +#if defined(GPIOJ) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI) || \ + ((__PORT__) == EXTI_GPIOJ)) +#elif defined(GPIOF) && defined (GPIOI) #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ ((__PORT__) == EXTI_GPIOB) || \ ((__PORT__) == EXTI_GPIOC) || \ @@ -255,6 +288,15 @@ typedef struct ((__PORT__) == EXTI_GPIOG) || \ ((__PORT__) == EXTI_GPIOH) || \ ((__PORT__) == EXTI_GPIOI)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH)) +#endif /* GPIOJ */ #define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U) @@ -294,7 +336,7 @@ typedef struct /* Configuration functions ****************************************************/ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); -HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti); HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); @@ -307,10 +349,10 @@ HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLin * @{ */ /* IO operation functions *****************************************************/ -void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); -uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); -void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); -void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti); /** * @} @@ -323,6 +365,10 @@ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); /* EXTI line attributes management functions **********************************/ void HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes); HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +void HAL_EXTI_LockAttributes(void); +uint32_t HAL_EXTI_GetLockAttributes(void); +#endif /* __ARM_FEATURE_CMSE */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_fdcan.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_fdcan.c index 7c0fc47c0cd..4eabe7c6a36 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_fdcan.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_fdcan.c @@ -10,7 +10,6 @@ * + IO operation functions * + Peripheral Configuration and Control functions * + Peripheral State and Error functions - * ****************************************************************************** * @attention * @@ -97,12 +96,12 @@ *** Callback registration *** ============================================= - The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1 + The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Function @ref HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback() + Use Function HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback() to register an interrupt callback. - Function @ref HAL_FDCAN_RegisterCallback() allows to register following callbacks: + Function HAL_FDCAN_RegisterCallback() allows to register following callbacks: (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. (+) HighPriorityMessageCallback : High Priority Message Callback. (+) TimestampWraparoundCallback : Timestamp Wraparound Callback. @@ -115,14 +114,14 @@ For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback, TxBufferCompleteCallback, TxBufferAbortCallback and ErrorStatusCallback use dedicated - register callbacks : respectively @ref HAL_FDCAN_RegisterTxEventFifoCallback(), - @ref HAL_FDCAN_RegisterRxFifo0Callback(), @ref HAL_FDCAN_RegisterRxFifo1Callback(), - @ref HAL_FDCAN_RegisterTxBufferCompleteCallback(), @ref HAL_FDCAN_RegisterTxBufferAbortCallback() - and @ref HAL_FDCAN_RegisterErrorStatusCallback(). + register callbacks: respectively HAL_FDCAN_RegisterTxEventFifoCallback(), + HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(), + HAL_FDCAN_RegisterTxBufferCompleteCallback(), HAL_FDCAN_RegisterTxBufferAbortCallback() + and HAL_FDCAN_RegisterErrorStatusCallback(). - Use function @ref HAL_FDCAN_UnRegisterCallback() to reset a callback to the default + Use function HAL_FDCAN_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. @@ -135,18 +134,18 @@ For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback, TxBufferCompleteCallback and TxBufferAbortCallback, use dedicated - unregister callbacks : respectively @ref HAL_FDCAN_UnRegisterTxEventFifoCallback(), - @ref HAL_FDCAN_UnRegisterRxFifo0Callback(), @ref HAL_FDCAN_UnRegisterRxFifo1Callback(), - @ref HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), @ref HAL_FDCAN_UnRegisterTxBufferAbortCallback() - and @ref HAL_FDCAN_UnRegisterErrorStatusCallback(). + unregister callbacks: respectively HAL_FDCAN_UnRegisterTxEventFifoCallback(), + HAL_FDCAN_UnRegisterRxFifo0Callback(), HAL_FDCAN_UnRegisterRxFifo1Callback(), + HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), HAL_FDCAN_UnRegisterTxBufferAbortCallback() + and HAL_FDCAN_UnRegisterErrorStatusCallback(). - By default, after the @ref HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET, + By default, after the HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET, all callbacks are set to the corresponding weak functions: - examples @ref HAL_FDCAN_ErrorCallback(). + examples HAL_FDCAN_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit() only when + reset to the legacy weak function in the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() only when these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit() + if not, MspInit or MspDeInit are not null, the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only. @@ -154,8 +153,8 @@ in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_FDCAN_RegisterCallback() before calling @ref HAL_FDCAN_DeInit() - or @ref HAL_FDCAN_Init() function. + using HAL_FDCAN_RegisterCallback() before calling HAL_FDCAN_DeInit() + or HAL_FDCAN_Init() function. When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks @@ -250,9 +249,15 @@ static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, */ /* Private function prototypes -----------------------------------------------*/ +/** @addtogroup FDCAN_Private_Functions_Prototypes + * @{ + */ static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan); -static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, - uint32_t BufferIndex); +static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData, uint32_t BufferIndex); +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ /** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions @@ -325,22 +330,17 @@ HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan) hfdcan->Lock = HAL_UNLOCKED; /* Reset callbacks to legacy functions */ - hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback */ - hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback */ - hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback */ - hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ - hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak - TxBufferCompleteCallback */ - hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak - TxBufferAbortCallback */ - hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* Legacy weak - HighPriorityMessageCallback */ - hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* Legacy weak - TimestampWraparoundCallback */ - hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; /* Legacy weak - TimeoutOccurredCallback */ - hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; /* Legacy weak ErrorCallback */ - hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback */ + hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* TxEventFifoCallback */ + hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* RxFifo0Callback */ + hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* RxFifo1Callback */ + hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; /* TxFifoEmptyCallback */ + hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* TxBufferCompleteCallback */ + hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* TxBufferAbortCallback */ + hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* HighPriorityMessageCallback */ + hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* TimestampWraparoundCallback */ + hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; /* TimeoutOccurredCallback */ + hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; /* ErrorCallback */ + hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* ErrorStatusCallback */ if (hfdcan->MspInitCallback == NULL) { @@ -576,7 +576,7 @@ __weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hfdcan); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_MspInit could be implemented in the user file */ } @@ -591,7 +591,7 @@ __weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hfdcan); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_MspDeInit could be implemented in the user file */ } @@ -1286,7 +1286,7 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *h * contains the filter configuration information * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig) +HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig) { uint32_t FilterElementW1; uint32_t FilterElementW2; @@ -1411,7 +1411,7 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. * @param Mask Extended ID Mask. - This parameter must be a number between 0 and 0x1FFFFFFF + * This parameter must be a number between 0 and 0x1FFFFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask) @@ -1601,7 +1601,7 @@ HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan) * the configuration information for the specified FDCAN. * @retval Timestamp counter value */ -uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan) +uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan) { return (uint16_t)(hfdcan->Instance->TSCV); } @@ -1724,7 +1724,7 @@ HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) * the configuration information for the specified FDCAN. * @retval Timeout counter value */ -uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) +uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan) { return (uint16_t)(hfdcan->Instance->TOCV); } @@ -2097,8 +2097,8 @@ HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan) * @param pTxData pointer to a buffer containing the payload of the Tx frame. * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, - uint8_t *pTxData) +HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData) { uint32_t PutIndex; @@ -2165,7 +2165,7 @@ HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDC * - Any value of @arg FDCAN_Tx_location if Tx request has been submitted. * - 0 if no Tx FIFO/Queue request have been submitted. */ -uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan) +uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan) { /* Return Last Tx FIFO/Queue Request Buffer */ return hfdcan->LatestTxFifoQRequest; @@ -2217,7 +2217,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R uint32_t *RxAddress; uint8_t *pData; uint32_t ByteCounter; - uint32_t GetIndex; + uint32_t GetIndex = 0; HAL_FDCAN_StateTypeDef state = hfdcan->State; /* Check function parameters */ @@ -2237,8 +2237,20 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R } else { + /* Check that the Rx FIFO 0 is full & overwrite mode is on */ + if (((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0F) >> FDCAN_RXF0S_F0F_Pos) == 1U) + { + if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F0OM) >> FDCAN_RXGFC_F0OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) + { + /* When overwrite status is on discard first message in FIFO */ + GetIndex = 1U; + } + } + + /* Calculate Rx FIFO 0 element index */ + GetIndex += ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos); + /* Calculate Rx FIFO 0 element address */ - GetIndex = ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos); RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * SRAMCAN_RF0_SIZE)); } } @@ -2254,8 +2266,19 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R } else { + /* Check that the Rx FIFO 1 is full & overwrite mode is on */ + if (((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1F) >> FDCAN_RXF1S_F1F_Pos) == 1U) + { + if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F1OM) >> FDCAN_RXGFC_F1OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) + { + /* When overwrite status is on discard first message in FIFO */ + GetIndex = 1U; + } + } + + /* Calculate Rx FIFO 1 element index */ + GetIndex += ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos); /* Calculate Rx FIFO 1 element address */ - GetIndex = ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos); RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * SRAMCAN_RF1_SIZE)); } } @@ -2286,7 +2309,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS); /* Retrieve DataLength */ - pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC); + pRxHeader->DataLength = ((*RxAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U); /* Retrieve BitRateSwitch */ pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS); @@ -2305,7 +2328,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R /* Retrieve Rx payload */ pData = (uint8_t *)RxAddress; - for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16U]; ByteCounter++) + for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength]; ByteCounter++) { pRxData[ByteCounter] = pData[ByteCounter]; } @@ -2387,7 +2410,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEven pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS); /* Retrieve DataLength */ - pTxEvent->DataLength = (*TxEventAddress & FDCAN_ELEMENT_MASK_DLC); + pTxEvent->DataLength = ((*TxEventAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U); /* Retrieve BitRateSwitch */ pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS); @@ -2423,7 +2446,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEven * @param HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, +HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus) { HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos); @@ -2442,7 +2465,8 @@ HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hf * @param ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus) +HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ProtocolStatusTypeDef *ProtocolStatus) { uint32_t StatusReg; @@ -2473,7 +2497,8 @@ HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN * @param ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters) +HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ErrorCountersTypeDef *ErrorCounters) { uint32_t CountersReg; @@ -2497,10 +2522,10 @@ HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ * @param TxBufferIndex Tx buffer index. * This parameter can be any combination of @arg FDCAN_Tx_location. * @retval Status - * - 0 : No pending transmission request on TxBufferIndex list + * - 0 : No pending transmission request on TxBufferIndex list. * - 1 : Pending transmission request on TxBufferIndex. */ -uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex) +uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex) { /* Check function parameters */ assert_param(IS_FDCAN_TX_LOCATION_LIST(TxBufferIndex)); @@ -2523,7 +2548,7 @@ uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_ * @arg FDCAN_RX_FIFO1: Rx FIFO 1 * @retval Rx FIFO fill level. */ -uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo) +uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo) { uint32_t FillLevel; @@ -2550,7 +2575,7 @@ uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFi * the configuration information for the specified FDCAN. * @retval Tx FIFO free level. */ -uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan) +uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan) { uint32_t FreeLevel; @@ -2568,7 +2593,7 @@ uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan) * - 0 : Normal FDCAN operation. * - 1 : Restricted Operation Mode active. */ -uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan) +uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan) { uint32_t OperationMode; @@ -2879,6 +2904,8 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) uint32_t ErrorStatusITs; uint32_t TransmittedBuffers; uint32_t AbortedBuffers; + uint32_t itsource; + uint32_t itflag; TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK; TxEventFifoITs &= hfdcan->Instance->IE; @@ -2890,11 +2917,13 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) Errors &= hfdcan->Instance->IE; ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK; ErrorStatusITs &= hfdcan->Instance->IE; + itsource = hfdcan->Instance->IE; + itflag = hfdcan->Instance->IR; /* High Priority Message interrupt management *******************************/ - if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != 0U) + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != RESET) { - if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != 0U) + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != RESET) { /* Clear the High Priority Message flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG); @@ -2910,9 +2939,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) } /* Transmission Abort interrupt management **********************************/ - if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE) != 0U) + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_ABORT_COMPLETE) != RESET) { - if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_ABORT_COMPLETE) != 0U) + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_ABORT_COMPLETE) != RESET) { /* List of aborted monitored buffers */ AbortedBuffers = hfdcan->Instance->TXBCF; @@ -2977,9 +3006,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) } /* Tx FIFO empty interrupt management ***************************************/ - if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY) != 0U) + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_FIFO_EMPTY) != RESET) { - if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_FIFO_EMPTY) != 0U) + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_FIFO_EMPTY) != RESET) { /* Clear the Tx FIFO empty flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY); @@ -2995,9 +3024,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) } /* Transmission Complete interrupt management *******************************/ - if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE) != 0U) + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_COMPLETE) != RESET) { - if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_COMPLETE) != 0U) + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_COMPLETE) != RESET) { /* List of transmitted monitored buffers */ TransmittedBuffers = hfdcan->Instance->TXBTO; @@ -3017,9 +3046,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) } /* Timestamp Wraparound interrupt management ********************************/ - if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != 0U) + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != RESET) { - if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMESTAMP_WRAPAROUND) != 0U) + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TIMESTAMP_WRAPAROUND) != RESET) { /* Clear the Timestamp Wraparound flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND); @@ -3035,9 +3064,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) } /* Timeout Occurred interrupt management ************************************/ - if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED) != 0U) + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TIMEOUT_OCCURRED) != RESET) { - if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMEOUT_OCCURRED) != 0U) + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TIMEOUT_OCCURRED) != RESET) { /* Clear the Timeout Occurred flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED); @@ -3053,9 +3082,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) } /* Message RAM access failure interrupt management **************************/ - if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE) != 0U) + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_RAM_ACCESS_FAILURE) != RESET) { - if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RAM_ACCESS_FAILURE) != 0U) + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_RAM_ACCESS_FAILURE) != RESET) { /* Clear the Message RAM access failure flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE); @@ -3135,7 +3164,7 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) * @brief Tx Event callback. * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. - * @param TxEventFifoITs indicates which Tx Event FIFO interrupts are signalled. + * @param TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled. * This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts. * @retval None */ @@ -3145,7 +3174,7 @@ __weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t UNUSED(hfdcan); UNUSED(TxEventFifoITs); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file */ } @@ -3154,7 +3183,7 @@ __weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t * @brief Rx FIFO 0 callback. * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. - * @param RxFifo0ITs indicates which Rx FIFO 0 interrupts are signalled. + * @param RxFifo0ITs indicates which Rx FIFO 0 interrupts are signaled. * This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts. * @retval None */ @@ -3164,7 +3193,7 @@ __weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFi UNUSED(hfdcan); UNUSED(RxFifo0ITs); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_RxFifo0Callback could be implemented in the user file */ } @@ -3173,7 +3202,7 @@ __weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFi * @brief Rx FIFO 1 callback. * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. - * @param RxFifo1ITs indicates which Rx FIFO 1 interrupts are signalled. + * @param RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled. * This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts. * @retval None */ @@ -3183,7 +3212,7 @@ __weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFi UNUSED(hfdcan); UNUSED(RxFifo1ITs); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_RxFifo1Callback could be implemented in the user file */ } @@ -3199,7 +3228,7 @@ __weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan) /* Prevent unused argument(s) compilation warning */ UNUSED(hfdcan); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file */ } @@ -3218,7 +3247,7 @@ __weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint UNUSED(hfdcan); UNUSED(BufferIndexes); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file */ } @@ -3237,7 +3266,7 @@ __weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_ UNUSED(hfdcan); UNUSED(BufferIndexes); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file */ } @@ -3253,7 +3282,7 @@ __weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan) /* Prevent unused argument(s) compilation warning */ UNUSED(hfdcan); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file */ } @@ -3269,7 +3298,7 @@ __weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan) /* Prevent unused argument(s) compilation warning */ UNUSED(hfdcan); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file */ } @@ -3285,7 +3314,7 @@ __weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan) /* Prevent unused argument(s) compilation warning */ UNUSED(hfdcan); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file */ } @@ -3301,7 +3330,7 @@ __weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan) /* Prevent unused argument(s) compilation warning */ UNUSED(hfdcan); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_ErrorCallback could be implemented in the user file */ } @@ -3320,7 +3349,7 @@ __weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t UNUSED(hfdcan); UNUSED(ErrorStatusITs); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file */ } @@ -3350,7 +3379,7 @@ __weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t * the configuration information for the specified FDCAN. * @retval HAL state */ -HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan) +HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan) { /* Return FDCAN state */ return hfdcan->State; @@ -3362,7 +3391,7 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan) * the configuration information for the specified FDCAN. * @retval FDCAN Error Code */ -uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan) +uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan) { /* Return FDCAN error code */ return hfdcan->ErrorCode; @@ -3431,8 +3460,8 @@ static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan) * @param BufferIndex index of the buffer to be configured. * @retval none */ -static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, - uint32_t BufferIndex) +static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData, uint32_t BufferIndex) { uint32_t TxElementW1; uint32_t TxElementW2; @@ -3460,7 +3489,7 @@ static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTy pTxHeader->TxEventFifoControl | pTxHeader->FDFormat | pTxHeader->BitRateSwitch | - pTxHeader->DataLength); + (pTxHeader->DataLength << 16U)); /* Calculate Tx element address */ TxAddress = (uint32_t *)(hfdcan->msgRam.TxFIFOQSA + (BufferIndex * SRAMCAN_TFQ_SIZE)); @@ -3472,7 +3501,7 @@ static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTy TxAddress++; /* Write Tx payload to the message RAM */ - for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16U]; ByteCounter += 4U) + for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength]; ByteCounter += 4U) { *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24U) | ((uint32_t)pTxData[ByteCounter + 2U] << 16U) | @@ -3495,4 +3524,3 @@ static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTy */ #endif /* FDCAN1 */ - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_fdcan.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_fdcan.h index 4cf16d6b7a6..9a8741bbbf0 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_fdcan.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_fdcan.h @@ -230,12 +230,15 @@ typedef struct uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element. This parameter must be a number between: - 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID - - 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID */ + - 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID + When the frame is a Non-Filter matching frame, this parameter + is unused. */ uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter. - Acceptance of non-matching frames may be enabled via - HAL_FDCAN_ConfigGlobalFilter(). - This parameter can be 0 or 1 */ + Acceptance of non-matching frames may be enabled via + HAL_FDCAN_ConfigGlobalFilter(). + This parameter takes 0 if the frame matched an Rx filter or + 1 if it did not match any Rx filter */ } FDCAN_RxHeaderTypeDef; @@ -315,53 +318,55 @@ typedef struct typedef struct { uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus. - This parameter can be a value of @ref FDCAN_protocol_error_code */ + This parameter can be a value of @ref FDCAN_protocol_error_code */ uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. - This parameter can be a value of @ref FDCAN_protocol_error_code */ + This parameter can be a value of @ref FDCAN_protocol_error_code */ uint32_t Activity; /*!< Specifies the FDCAN module communication state. - This parameter can be a value of @ref FDCAN_communication_state */ + This parameter can be a value of @ref FDCAN_communication_state */ uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status. This parameter can be: - 0 : The FDCAN is in Error_Active state - - 1 : The FDCAN is in Error_Passive state */ + - 1 : The FDCAN is in Error_Passive state */ uint32_t Warning; /*!< Specifies the FDCAN module warning status. This parameter can be: - - 0 : error counters (RxErrorCnt and TxErrorCnt) - are below the Error_Warning limit of 96 - - 1 : at least one of error counters has reached the Error_Warning limit of 96 */ + - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the + Error_Warning limit of 96 + - 1 : at least one of error counters has reached the Error_Warning + limit of 96 */ uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status. This parameter can be: - 0 : The FDCAN is not in Bus_Off state - - 1 : The FDCAN is in Bus_Off state */ + - 1 : The FDCAN is in Bus_Off state */ uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message. This parameter can be: - 0 : Last received CAN FD message did not have its ESI flag set - - 1 : Last received CAN FD message had its ESI flag set */ + - 1 : Last received CAN FD message had its ESI flag set */ uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message. This parameter can be: - 0 : Last received CAN FD message did not have its BRS flag set - - 1 : Last received CAN FD message had its BRS flag set */ + - 1 : Last received CAN FD message had its BRS flag set */ uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received - since last protocol status.This parameter can be: + since last protocol status. + This parameter can be: - 0 : No CAN FD message received - - 1 : CAN FD message received */ + - 1 : CAN FD message received */ uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status. This parameter can be: - 0 : No protocol exception event occurred since last read access - - 1 : Protocol exception event occurred */ + - 1 : Protocol exception event occurred */ uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value. - This parameter can be a number between 0 and 127 */ + This parameter can be a number between 0 and 127 */ } FDCAN_ProtocolStatusTypeDef; @@ -371,22 +376,24 @@ typedef struct typedef struct { uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value. - This parameter can be a number between 0 and 255 */ + This parameter can be a number between 0 and 255 */ uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value. - This parameter can be a number between 0 and 127 */ + This parameter can be a number between 0 and 127 */ uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status. This parameter can be: - - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128 - - 1 : The Receive Error Counter (RxErrorCnt) - has reached the error passive level of 128 */ + - 0 : The Receive Error Counter (RxErrorCnt) is below the error + passive level of 128 + - 1 : The Receive Error Counter (RxErrorCnt) has reached the error + passive level of 128 */ uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value. This parameter can be a number between 0 and 255. - This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt - or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of - TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */ + This counter is incremented each time when a FDCAN protocol error causes + the TxErrorCnt or the RxErrorCnt to be incremented. The counter stops at 255; + the next increment of TxErrorCnt or RxErrorCnt sets interrupt flag + FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */ } FDCAN_ErrorCountersTypeDef; @@ -601,21 +608,21 @@ typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, * @{ */ #define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */ -#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /*!< 1 bytes data field */ -#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /*!< 2 bytes data field */ -#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /*!< 3 bytes data field */ -#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /*!< 4 bytes data field */ -#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /*!< 5 bytes data field */ -#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /*!< 6 bytes data field */ -#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /*!< 7 bytes data field */ -#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /*!< 8 bytes data field */ -#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */ -#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */ -#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */ -#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */ -#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */ -#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */ -#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */ +#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00000001U) /*!< 1 bytes data field */ +#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00000002U) /*!< 2 bytes data field */ +#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00000003U) /*!< 3 bytes data field */ +#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00000004U) /*!< 4 bytes data field */ +#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00000005U) /*!< 5 bytes data field */ +#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00000006U) /*!< 6 bytes data field */ +#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00000007U) /*!< 7 bytes data field */ +#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00000008U) /*!< 8 bytes data field */ +#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00000009U) /*!< 12 bytes data field */ +#define FDCAN_DLC_BYTES_16 ((uint32_t)0x0000000AU) /*!< 16 bytes data field */ +#define FDCAN_DLC_BYTES_20 ((uint32_t)0x0000000BU) /*!< 20 bytes data field */ +#define FDCAN_DLC_BYTES_24 ((uint32_t)0x0000000CU) /*!< 24 bytes data field */ +#define FDCAN_DLC_BYTES_32 ((uint32_t)0x0000000DU) /*!< 32 bytes data field */ +#define FDCAN_DLC_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */ +#define FDCAN_DLC_BYTES_64 ((uint32_t)0x0000000FU) /*!< 64 bytes data field */ /** * @} */ @@ -1037,7 +1044,7 @@ typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, * @retval None */ #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 -#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ +#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ @@ -1164,7 +1171,7 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *h * @{ */ /* Configuration functions ****************************************************/ -HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig); +HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig); HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt); @@ -1174,13 +1181,13 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint3 HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler); HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation); HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan); -uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); +uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod); HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); -uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); +uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter); @@ -1200,21 +1207,23 @@ HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); /* Control functions **********************************************************/ HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan); -HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, - uint8_t *pTxData); -uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData); +uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex); HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData); HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent); -HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, +HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus); -HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus); -HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters); -uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex); -uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo); -uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan); -uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ProtocolStatusTypeDef *ProtocolStatus); +HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ErrorCountersTypeDef *ErrorCounters); +uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex); +uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo); +uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan); +uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); /** * @} @@ -1256,8 +1265,8 @@ void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorSt * @{ */ /* Peripheral State functions *************************************************/ -uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan); -HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan); +uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan); +HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan); /** * @} */ @@ -1406,6 +1415,10 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan); ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \ ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0 ) || \ ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1 )) + +#define FDCAN_CHECK_IT_SOURCE(__IE__, __IT__) ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET) + +#define FDCAN_CHECK_FLAG(__IR__, __FLAG__) ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) /** * @} */ @@ -1427,5 +1440,3 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan); #endif #endif /* STM32U5xx_HAL_FDCAN_H */ - - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_flash.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_flash.h index f83f65ea005..1a003f2d79f 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_flash.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_flash.h @@ -81,7 +81,7 @@ typedef struct uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, - @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM134_RST, + @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM_RST, @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK, @@ -324,7 +324,7 @@ typedef struct #define OB_USER_NRST_STOP 0x00000002U /*!< Reset generated when entering the stop mode */ #define OB_USER_NRST_STDBY 0x00000004U /*!< Reset generated when entering the standby mode */ #define OB_USER_NRST_SHDW 0x00000008U /*!< Reset generated when entering the shutdown mode */ -#define OB_USER_SRAM134_RST 0x00000010U /*!< SRAM1, SRAM3 and SRAM4 erase upon system reset */ +#define OB_USER_SRAM_RST 0x00000010U /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ #define OB_USER_IWDG_SW 0x00000020U /*!< Independent watchdog selection */ #define OB_USER_IWDG_STOP 0x00000040U /*!< Independent watchdog counter freeze in stop mode */ #define OB_USER_IWDG_STDBY 0x00000080U /*!< Independent watchdog counter freeze in standby mode */ @@ -332,7 +332,9 @@ typedef struct #define OB_USER_SWAP_BANK 0x00000200U /*!< Swap banks */ #define OB_USER_DUALBANK 0x00000400U /*!< Dual-Bank on 1MB/512kB Flash memory devices */ #define OB_USER_BKPRAM_ECC 0x00000800U /*!< Backup RAM ECC detection and correction enable */ +#if defined(SRAM3_BASE) #define OB_USER_SRAM3_ECC 0x00001000U /*!< SRAM3 ECC detection and correction enable */ +#endif /* SRAM3_BASE */ #define OB_USER_SRAM2_ECC 0x00002000U /*!< SRAM2 ECC detection and correction enable */ #define OB_USER_SRAM2_RST 0x00004000U /*!< SRAM2 Erase when system reset */ #define OB_USER_NSWBOOT0 0x00008000U /*!< Software BOOT0 */ @@ -389,13 +391,13 @@ typedef struct * @} */ -/** @defgroup FLASH_OB_USER_SRAM134_RST FLASH Option Bytes User SRAM134 Erase On Reset Type +/** @defgroup FLASH_OB_USER_SRAM_RST FLASH Option Bytes User SRAM Erase On Reset Type * @{ */ -#define OB_SRAM134_RST_ERASE 0x00000000U /*!< SRAM1, SRAM3 and SRAM4 erased - when a system reset occurs */ -#define OB_SRAM134_RST_NOT_ERASE FLASH_OPTR_SRAM134_RST /*!< SRAM1, SRAM3 and SRAM4 are not erased - when a system reset occurs */ +#define OB_SRAM_RST_ERASE 0x00000000U /*!< All SRAMs (except SRAM2 and BKPSRAM) erased + when a system reset occurs */ +#define OB_SRAM_RST_NOT_ERASE FLASH_OPTR_SRAM_RST /*!< All SRAMs (except SRAM2 and BKPSRAM) not erased + when a system reset occurs */ /** * @} */ @@ -1020,7 +1022,7 @@ extern FLASH_ProcessTypeDef pFlash; #define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST)) -#define IS_OB_USER_SRAM134_RST(VALUE) (((VALUE) == OB_SRAM134_RST_ERASE) || ((VALUE) == OB_SRAM134_RST_NOT_ERASE)) +#define IS_OB_USER_SRAM_RST(VALUE) (((VALUE) == OB_SRAM_RST_ERASE) || ((VALUE) == OB_SRAM_RST_NOT_ERASE)) #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_flash_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_flash_ex.c index bb61832d29c..df267a7062e 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_flash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_flash_ex.c @@ -1081,7 +1081,7 @@ static void FLASH_OB_RDPKeyConfig(uint32_t RDPKeyType, uint32_t RDPKey1, uint32_ * @param UserConfig The selected User Option Bytes values. * This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, - * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM134_RST, + * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM_RST, * @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP, * @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW, * @ref OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK, @@ -1140,14 +1140,14 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) optr_reg_mask |= FLASH_OPTR_nRST_SHDW; } - if ((UserType & OB_USER_SRAM134_RST) != 0U) + if ((UserType & OB_USER_SRAM_RST) != 0U) { - /* SRAM134_RST option byte should be modified */ - assert_param(IS_OB_USER_SRAM134_RST(UserConfig & FLASH_OPTR_SRAM134_RST)); + /* SRAM_RST option byte should be modified */ + assert_param(IS_OB_USER_SRAM_RST(UserConfig & FLASH_OPTR_SRAM_RST)); - /* Set value and mask for SRAM134_RST option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM134_RST); - optr_reg_mask |= FLASH_OPTR_SRAM134_RST; + /* Set value and mask for SRAM_RST option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM_RST); + optr_reg_mask |= FLASH_OPTR_SRAM_RST; } if ((UserType & OB_USER_IWDG_SW) != 0U) @@ -1219,7 +1219,7 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) optr_reg_val |= (UserConfig & FLASH_OPTR_BKPRAM_ECC); optr_reg_mask |= FLASH_OPTR_BKPRAM_ECC; } - +#if defined(SRAM3_BASE) if ((UserType & OB_USER_SRAM3_ECC) != 0U) { /* SRAM3_ECC option byte should be modified */ @@ -1229,7 +1229,7 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM3_ECC); optr_reg_mask |= FLASH_OPTR_SRAM3_ECC; } - +#endif /* SRAM3_BASE */ if ((UserType & OB_USER_SRAM2_ECC) != 0U) { /* SRAM2_ECC option byte should be modified */ @@ -1550,7 +1550,7 @@ static uint32_t FLASH_OB_GetRDP(void) * @retval The FLASH User Option Bytes values. * The return value can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, - * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM134_RST, + * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM_RST, * @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP, * @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW, * @ref OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK, diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_fmac.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_fmac.c index b5fde295428..b64e538bdeb 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_fmac.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_fmac.c @@ -30,17 +30,17 @@ [..] The FMAC HAL driver can be used as follows: - (#) Initialize the FMAC low level resources by implementing the @ref HAL_FMAC_MspInit(): - (++) Enable the FMAC interface clock using @ref __HAL_RCC_FMAC_CLK_ENABLE(). + (#) Initialize the FMAC low level resources by implementing the HAL_FMAC_MspInit(): + (++) Enable the FMAC interface clock using __HAL_RCC_FMAC_CLK_ENABLE(). (++) In case of using interrupts (e.g. access configured as FMAC_BUFFER_ACCESS_IT): - (+++) Configure the FMAC interrupt priority using @ref HAL_NVIC_SetPriority(). - (+++) Enable the FMAC IRQ handler using @ref HAL_NVIC_EnableIRQ(). - (+++) In FMAC IRQ handler, call @ref HAL_FMAC_IRQHandler(). + (+++) Configure the FMAC interrupt priority using HAL_NVIC_SetPriority(). + (+++) Enable the FMAC IRQ handler using HAL_NVIC_EnableIRQ(). + (+++) In FMAC IRQ handler, call HAL_FMAC_IRQHandler(). (++) In case of using DMA to control data transfer (e.g. access configured as FMAC_BUFFER_ACCESS_DMA): - (+++) Enable the DMA interface clock using @ref __HAL_RCC_DMA1_CLK_ENABLE() - or @ref __HAL_RCC_DMA2_CLK_ENABLE() depending on the used DMA instance. - (+++) Enable the DMAMUX1 interface clock using @ref __HAL_RCC_DMAMUX1_CLK_ENABLE(). + (+++) Enable the DMA interface clock using __HAL_RCC_DMA1_CLK_ENABLE() + or __HAL_RCC_DMA2_CLK_ENABLE() depending on the used DMA instance. + (+++) Enable the DMAMUX1 interface clock using __HAL_RCC_DMAMUX1_CLK_ENABLE(). (+++) If the initialization of the internal buffers (coefficients, input, output) is done via DMA, configure and enable one DMA channel for managing data transfer from memory to memory (preload channel). @@ -51,16 +51,16 @@ one DMA channel for managing data transfer from peripheral to memory (output channel). (+++) Associate the initialized DMA handle(s) to the FMAC DMA handle(s) - using @ref __HAL_LINKDMA(). + using __HAL_LINKDMA(). (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the enabled DMA channel(s) using @ref HAL_NVIC_SetPriority() - and @ref HAL_NVIC_EnableIRQ(). + interrupt on the enabled DMA channel(s) using HAL_NVIC_SetPriority() + and HAL_NVIC_EnableIRQ(). - (#) Initialize the FMAC HAL using @ref HAL_FMAC_Init(). This function - resorts to @ref HAL_FMAC_MspInit() for low-level initialization. + (#) Initialize the FMAC HAL using HAL_FMAC_Init(). This function + resorts to HAL_FMAC_MspInit() for low-level initialization. - (#) Configure the FMAC processing (filter) using @ref HAL_FMAC_FilterConfig() - or @ref HAL_FMAC_FilterConfig_DMA(). + (#) Configure the FMAC processing (filter) using HAL_FMAC_FilterConfig() + or HAL_FMAC_FilterConfig_DMA(). This function: (++) Defines the memory area within the FMAC internal memory (input, coefficients, output) and the associated threshold (input, output). @@ -73,61 +73,61 @@ (++) Enable the error interruptions in the input access and/or the output access is done through IT/DMA. If an error occurs, the interruption will be triggered in loop. In order to recover, the user will have - to reset the IP with the sequence @ref HAL_FMAC_DeInit / @ref HAL_FMAC_Init. - Optionally, he can also disable the interrupt using @ref __HAL_FMAC_DISABLE_IT; + to reset the IP with the sequence HAL_FMAC_DeInit / HAL_FMAC_Init. + Optionally, he can also disable the interrupt using __HAL_FMAC_DISABLE_IT; the error status will be kept, but no more interrupt will be triggered. (++) Write the provided coefficients into the internal memory using polling - mode ( @ref HAL_FMAC_FilterConfig() ) or DMA ( @ref HAL_FMAC_FilterConfig_DMA() ). - In the DMA case, @ref HAL_FMAC_FilterConfigCallback() is called when + mode ( HAL_FMAC_FilterConfig() ) or DMA ( HAL_FMAC_FilterConfig_DMA() ). + In the DMA case, HAL_FMAC_FilterConfigCallback() is called when the handling is over. (#) Optionally, the user can enable the error interruption related to - saturation by calling @ref __HAL_FMAC_ENABLE_IT. This helps in debugging the + saturation by calling __HAL_FMAC_ENABLE_IT. This helps in debugging the filter. If a saturation occurs, the interruption will be triggered in loop. In order to recover, the user will have to: - (++) Disable the interruption by calling @ref __HAL_FMAC_DISABLE_IT if + (++) Disable the interruption by calling __HAL_FMAC_DISABLE_IT if the user wishes to continue all the same. - (++) Reset the IP with the sequence @ref HAL_FMAC_DeInit / @ref HAL_FMAC_Init. + (++) Reset the IP with the sequence HAL_FMAC_DeInit / HAL_FMAC_Init. (#) Optionally, preload input (FIR, IIR) and output (IIR) data using - @ref HAL_FMAC_FilterPreload() or @ref HAL_FMAC_FilterPreload_DMA(). - In the DMA case, @ref HAL_FMAC_FilterPreloadCallback() is called when + HAL_FMAC_FilterPreload() or HAL_FMAC_FilterPreload_DMA(). + In the DMA case, HAL_FMAC_FilterPreloadCallback() is called when the handling is over. This step is optional as the filter can be started without preloaded data. - (#) Start the FMAC processing (filter) using @ref HAL_FMAC_FilterStart(). + (#) Start the FMAC processing (filter) using HAL_FMAC_FilterStart(). This function also configures the output buffer that will be filled from the circular internal output buffer. The function returns immediately without updating the provided buffer. The IP processing will be active until - @ref HAL_FMAC_FilterStop() is called. + HAL_FMAC_FilterStop() is called. - (#) If the input internal buffer is accessed via DMA, @ref HAL_FMAC_HalfGetDataCallback() + (#) If the input internal buffer is accessed via DMA, HAL_FMAC_HalfGetDataCallback() will be called to indicate that half of the input buffer has been handled. - (#) If the input internal buffer is accessed via DMA or interrupt, @ref HAL_FMAC_GetDataCallback() + (#) If the input internal buffer is accessed via DMA or interrupt, HAL_FMAC_GetDataCallback() will be called to require new input data. It will be provided through - @ref HAL_FMAC_AppendFilterData() if the DMA isn't in circular mode. + HAL_FMAC_AppendFilterData() if the DMA isn't in circular mode. - (#) If the output internal buffer is accessed via DMA, @ref HAL_FMAC_HalfOutputDataReadyCallback() + (#) If the output internal buffer is accessed via DMA, HAL_FMAC_HalfOutputDataReadyCallback() will be called to indicate that half of the output buffer has been handled. (#) If the output internal buffer is accessed via DMA or interrupt, - @ref HAL_FMAC_OutputDataReadyCallback() will be called to require a new output - buffer. It will be provided through @ref HAL_FMAC_ConfigFilterOutputBuffer() + HAL_FMAC_OutputDataReadyCallback() will be called to require a new output + buffer. It will be provided through HAL_FMAC_ConfigFilterOutputBuffer() if the DMA isn't in circular mode. - (#) In all modes except none, provide new input data to be processed via @ref HAL_FMAC_AppendFilterData(). + (#) In all modes except none, provide new input data to be processed via HAL_FMAC_AppendFilterData(). This function should only be called once the previous input data has been handled (the preloaded input data isn't concerned). (#) In all modes except none, provide a new output buffer to be filled via - @ref HAL_FMAC_ConfigFilterOutputBuffer(). This function should only be called once the previous + HAL_FMAC_ConfigFilterOutputBuffer(). This function should only be called once the previous user's output buffer has been filled. - (#) In polling mode, handle the input and output data using @ref HAL_FMAC_PollFilterData(). + (#) In polling mode, handle the input and output data using HAL_FMAC_PollFilterData(). This function: - (++) Write the user's input data (provided via @ref HAL_FMAC_AppendFilterData()) + (++) Write the user's input data (provided via HAL_FMAC_AppendFilterData()) into the FMAC input memory area. (++) Read the FMAC output memory area and write it into the user's output buffer. It will return either when: @@ -137,10 +137,10 @@ The user will have to use the updated input and output sizes to keep track of them. - (#) Stop the FMAC processing (filter) using @ref HAL_FMAC_FilterStop(). + (#) Stop the FMAC processing (filter) using HAL_FMAC_FilterStop(). - (#) Call @ref HAL_FMAC_DeInit() to de-initialize the FMAC peripheral. This function - resorts to @ref HAL_FMAC_MspDeInit() for low-level de-initialization. + (#) Call HAL_FMAC_DeInit() to de-initialize the FMAC peripheral. This function + resorts to HAL_FMAC_MspDeInit() for low-level de-initialization. ##### Callback registration ##### ================================== @@ -150,8 +150,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_FMAC_RegisterCallback() to register a user callback. - Function @ref HAL_FMAC_RegisterCallback() allows to register following callbacks: + Use Function HAL_FMAC_RegisterCallback() to register a user callback. + Function HAL_FMAC_RegisterCallback() allows to register following callbacks: (+) ErrorCallback : Error Callback. (+) HalfGetDataCallback : Get Half Data Callback. (+) GetDataCallback : Get Data Callback. @@ -165,9 +165,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_FMAC_UnRegisterCallback() to reset a callback to the default + Use function HAL_FMAC_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_FMAC_UnRegisterCallback() takes as parameters the HAL peripheral handle + HAL_FMAC_UnRegisterCallback() takes as parameters the HAL peripheral handle and the Callback ID. This function allows to reset following callbacks: (+) ErrorCallback : Error Callback. @@ -181,13 +181,13 @@ (+) MspDeInitCallback : FMAC MspDeInit. [..] - By default, after the @ref HAL_FMAC_Init() and when the state is HAL_FMAC_STATE_RESET + By default, after the HAL_FMAC_Init() and when the state is HAL_FMAC_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref GetDataCallback(), @ref OutputDataReadyCallback(). + examples GetDataCallback(), OutputDataReadyCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_FMAC_Init() - and @ref HAL_FMAC_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_FMAC_Init() and @ref HAL_FMAC_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_FMAC_Init() + and HAL_FMAC_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_FMAC_Init() and HAL_FMAC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -196,8 +196,8 @@ in HAL_FMAC_STATE_READY or HAL_FMAC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_FMAC_RegisterCallback() before calling @ref HAL_FMAC_DeInit() - or @ref HAL_FMAC_Init() function. + using HAL_FMAC_RegisterCallback() before calling HAL_FMAC_DeInit() + or HAL_FMAC_Init() function. [..] When the compilation define USE_HAL_FMAC_REGISTER_CALLBACKS is set to 0 or @@ -528,6 +528,8 @@ __weak void HAL_FMAC_MspDeInit(FMAC_HandleTypeDef *hfmac) /** * @brief Register a User FMAC Callback. * @note The User FMAC Callback is to be used instead of the weak predefined callback. + * @note The HAL_FMAC_RegisterCallback() may be called before HAL_FMAC_Init() in HAL_FMAC_STATE_RESET to register + * callbacks for HAL_FMAC_MSPINIT_CB_ID and HAL_FMAC_MSPDEINIT_CB_ID. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. * @param CallbackID ID of the callback to be registered. @@ -562,7 +564,6 @@ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_ return HAL_ERROR; } - __HAL_LOCK(hfmac); if (hfmac->State == HAL_FMAC_STATE_READY) { @@ -643,14 +644,14 @@ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_ status = HAL_ERROR; } - __HAL_UNLOCK(hfmac); - return status; } /** * @brief Unregister a FMAC CallBack. * @note The FMAC callback is redirected to the weak predefined callback. + * @note The HAL_FMAC_UnRegisterCallback() may be called before HAL_FMAC_Init() in HAL_FMAC_STATE_RESET to register + * callbacks for HAL_FMAC_MSPINIT_CB_ID and HAL_FMAC_MSPDEINIT_CB_ID. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module * @param CallbackID ID of the callback to be unregistered. @@ -676,8 +677,6 @@ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMA return HAL_ERROR; } - __HAL_LOCK(hfmac); - if (hfmac->State == HAL_FMAC_STATE_READY) { switch (CallbackID) @@ -760,8 +759,6 @@ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMA status = HAL_ERROR; } - __HAL_UNLOCK(hfmac); - return status; } #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */ @@ -1530,7 +1527,7 @@ void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac) * the configuration information for FMAC module. * @retval HAL_FMAC_StateTypeDef FMAC state */ -HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac) +HAL_FMAC_StateTypeDef HAL_FMAC_GetState(const FMAC_HandleTypeDef *hfmac) { /* Return FMAC state */ return hfmac->State; @@ -1543,7 +1540,7 @@ HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac) * @note The returned error is a bit-map combination of possible errors. * @retval uint32_t Error bit-map based on @ref FMAC_Error_Code */ -uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac) +uint32_t HAL_FMAC_GetError(const FMAC_HandleTypeDef *hfmac) { /* Return FMAC error code */ return hfmac->ErrorCode; @@ -1972,7 +1969,7 @@ static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t * hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hfmac->Instance->WDATA; /* Set DMA destination address */ - status = HAL_DMAEx_List_Start_IT(hfmac->hdmaPreload); + return (HAL_DMAEx_List_Start_IT(hfmac->hdmaPreload)); } else { @@ -1982,14 +1979,8 @@ static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t * } else { - status = HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pInput, \ - (uint32_t)&hfmac->Instance->WDATA, (uint32_t)(2UL * InputSize)); - } - - if (status != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; + return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pInput, \ + (uint32_t)&hfmac->Instance->WDATA, (uint32_t)(2UL * InputSize))); } } } @@ -2038,7 +2029,7 @@ static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t * hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hfmac->Instance->WDATA; /* Set DMA destination address */ - status = HAL_DMAEx_List_Start_IT(hfmac->hdmaPreload); + return (HAL_DMAEx_List_Start_IT(hfmac->hdmaPreload)); } else { @@ -2048,14 +2039,8 @@ static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t * } else { - status = HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pOutput, \ - (uint32_t)&hfmac->Instance->WDATA, (uint32_t)(2UL * OutputSize)); - } - - if (status != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; + return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pOutput, \ + (uint32_t)&hfmac->Instance->WDATA, (uint32_t)(2UL * OutputSize))); } } } diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_fmac.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_fmac.h index 4e9bb73d5f5..fd3cc3eaae4 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_fmac.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_fmac.h @@ -69,10 +69,12 @@ typedef struct uint32_t FilterParam; /*!< Filter configuration (operation and parameters). Set to 0 if no valid configuration was applied. */ - uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMA, IT, Polling, None. + uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): + DMA, IT, Polling, None. This parameter can be a value of @ref FMAC_Buffer_Access. */ - uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): DMA, IT, Polling, None. + uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): + DMA, IT, Polling, None. This parameter can be a value of @ref FMAC_Buffer_Access. */ int16_t *pInput; /*!< Pointer to FMAC input data buffer */ @@ -95,7 +97,8 @@ typedef struct DMA_HandleTypeDef *hdmaOut; /*!< FMAC peripheral output data DMA handle parameters */ - DMA_HandleTypeDef *hdmaPreload; /*!< FMAC peripheral preloaded data (X1, X2 and Y) DMA handle parameters */ + DMA_HandleTypeDef *hdmaPreload; /*!< FMAC peripheral preloaded data (X1, X2 and Y) DMA handle + parameters */ #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1) void (* ErrorCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC error callback */ @@ -164,37 +167,39 @@ typedef void (*pFMAC_CallbackTypeDef)(FMAC_HandleTypeDef *hfmac); /*!< pointer */ typedef struct { - uint8_t InputBaseAddress; /*!< Base address of the input buffer (X1) within the internal memory (0x00 to 0xFF). - Ignored if InputBufferSize is set to 0 + uint8_t InputBaseAddress; /*!< Base address of the input buffer (X1) within the internal memory + (0x00 to 0xFF). Ignored if InputBufferSize is set to 0 (previous configuration kept). Note: the buffers can overlap or even coincide exactly. */ - uint8_t InputBufferSize; /*!< Number of 16-bit words allocated to the input buffer (including the optional "headroom"). + uint8_t InputBufferSize; /*!< Number of 16-bit words allocated to the input buffer + (including the optional "headroom"). 0 if a previous configuration should be kept. */ - uint32_t InputThreshold; /*!< Input threshold: the buffer full flag will be set if the number of free spaces - in the buffer is lower than this threshold. + uint32_t InputThreshold; /*!< Input threshold: the buffer full flag will be set if the number + of free spaces in the buffer is lower than this threshold. This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */ - uint8_t CoeffBaseAddress; /*!< Base address of the coefficient buffer (X2) within the internal memory (0x00 to 0xFF). - Ignored if CoeffBufferSize is set to 0 + uint8_t CoeffBaseAddress; /*!< Base address of the coefficient buffer (X2) within the internal + memory (0x00 to 0xFF). Ignored if CoeffBufferSize is set to 0 (previous configuration kept). Note: the buffers can overlap or even coincide exactly. */ uint8_t CoeffBufferSize; /*!< Number of 16-bit words allocated to the coefficient buffer. 0 if a previous configuration should be kept. */ - uint8_t OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal memory (0x00 to 0xFF). - Ignored if OuputBufferSize is set to 0 + uint8_t OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal + memory (0x00 to 0xFF). Ignored if OuputBufferSize is set to 0 (previous configuration kept). Note: the buffers can overlap or even coincide exactly. */ - uint8_t OutputBufferSize; /*!< Number of 16-bit words allocated to the output buffer (including the optional "headroom"). + uint8_t OutputBufferSize; /*!< Number of 16-bit words allocated to the output buffer + (including the optional "headroom"). 0 if a previous configuration should be kept. */ - uint32_t OutputThreshold; /*!< Output threshold: the buffer empty flag will be set if the number of unread values - in the buffer is lower than this threshold. + uint32_t OutputThreshold; /*!< Output threshold: the buffer empty flag will be set if the number + of unread values in the buffer is lower than this threshold. This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */ @@ -209,14 +214,16 @@ typedef struct uint8_t CoeffBSize; /*!< Size of the coefficient vector B. */ - uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMA, IT, Polling, None. + uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): + DMA, IT, Polling, None. This parameter can be a value of @ref FMAC_Buffer_Access. */ - uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): DMA, IT, Polling, None. + uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): + DMA, IT, Polling, None. This parameter can be a value of @ref FMAC_Buffer_Access. */ - uint32_t Clip; /*!< Enable or disable the clipping feature. If the q1.15 range is exceeded, wrapping - is done when the clipping feature is disabled + uint32_t Clip; /*!< Enable or disable the clipping feature. If the q1.15 range + is exceeded, wrapping is done when the clipping feature is disabled and saturation is done when the clipping feature is enabled. This parameter can be a value of @ref FMAC_Clip_State. */ @@ -266,11 +273,11 @@ typedef struct /** @defgroup FMAC_Functions FMAC Functions * @{ */ -#define FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */ -#define FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */ -#define FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */ -#define FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */ -#define FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */ +#define FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */ +#define FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */ +#define FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */ +#define FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */ +#define FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */ /** * @} */ @@ -279,18 +286,22 @@ typedef struct * @{ * @note This parameter sets a watermark for buffer full (input) or buffer empty (output). */ -#define FMAC_THRESHOLD_1 0x00000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 1. - Output: Buffer empty flag set if the number - of unread values in the buffer is less than 1. */ -#define FMAC_THRESHOLD_2 0x01000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 2. - Output: Buffer empty flag set if the number - of unread values in the buffer is less than 2. */ -#define FMAC_THRESHOLD_4 0x02000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 4. - Output: Buffer empty flag set if the number - of unread values in the buffer is less than 4. */ -#define FMAC_THRESHOLD_8 0x03000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 8. - Output: Buffer empty flag set if the number - of unread values in the buffer is less than 8. */ +#define FMAC_THRESHOLD_1 0x00000000U /*!< Input: Buffer full flag set if the number of free spaces + in the buffer is less than 1. + Output: Buffer empty flag set if the number + of unread values in the buffer is less than 1. */ +#define FMAC_THRESHOLD_2 0x01000000U /*!< Input: Buffer full flag set if the number of free spaces + in the buffer is less than 2. + Output: Buffer empty flag set if the number + of unread values in the buffer is less than 2. */ +#define FMAC_THRESHOLD_4 0x02000000U /*!< Input: Buffer full flag set if the number of free spaces + in the buffer is less than 4. + Output: Buffer empty flag set if the number + of unread values in the buffer is less than 4. */ +#define FMAC_THRESHOLD_8 0x03000000U /*!< Input: Buffer full flag set if the number of free spaces + in the buffer is less than 8. + Output: Buffer empty flag set if the number + of unread values in the buffer is less than 8. */ #define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFU /*!< The configured threshold value shouldn't be changed */ /** * @} @@ -323,7 +334,8 @@ typedef struct #define FMAC_FLAG_X1FULL FMAC_SR_X1FULL /*!< X1 Buffer Full Flag */ #define FMAC_FLAG_OVFL FMAC_SR_OVFL /*!< Overflow Error Flag */ #define FMAC_FLAG_UNFL FMAC_SR_UNFL /*!< Underflow Error Flag */ -#define FMAC_FLAG_SAT FMAC_SR_SAT /*!< Saturation Error Flag (this helps in debugging a filter) */ +#define FMAC_FLAG_SAT FMAC_SR_SAT /*!< Saturation Error Flag + (this helps in debugging a filter) */ /** * @} */ @@ -335,7 +347,8 @@ typedef struct #define FMAC_IT_WIEN FMAC_CR_WIEN /*!< Write Interrupt Enable */ #define FMAC_IT_OVFLIEN FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */ #define FMAC_IT_UNFLIEN FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */ -#define FMAC_IT_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable (this helps in debugging a filter) */ +#define FMAC_IT_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable + (this helps in debugging a filter) */ /** * @} */ @@ -345,8 +358,8 @@ typedef struct */ -/* External variables --------------------------------------------------------*/ -/** @defgroup FMAC_External_variables FMAC External variables +/* Exported variables --------------------------------------------------------*/ +/** @defgroup FMAC_Exported_variables FMAC Exported variables * @{ */ /** @@ -358,7 +371,8 @@ typedef struct * @{ */ -/** @brief Reset FMAC handle state. +/** + * @brief Reset FMAC handle state. * @param __HANDLE__ FMAC handle. * @retval None */ @@ -402,7 +416,8 @@ typedef struct #define __HAL_FMAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) -/** @brief Check whether the specified FMAC interrupt occurred or not. +/** + * @brief Check whether the specified FMAC interrupt occurred or not. * @param __HANDLE__ FMAC handle. * @param __INTERRUPT__ FMAC interrupt to check. * This parameter can be any combination of the following values: @@ -416,7 +431,8 @@ typedef struct #define __HAL_FMAC_GET_IT(__HANDLE__, __INTERRUPT__) \ (((__HANDLE__)->Instance->SR) &= ~(__INTERRUPT__)) -/** @brief Clear specified FMAC interrupt status. Dummy macro as the +/** + * @brief Clear specified FMAC interrupt status. Dummy macro as the interrupt status flags are read-only. * @param __HANDLE__ FMAC handle. * @param __INTERRUPT__ FMAC interrupt to clear. @@ -424,7 +440,8 @@ typedef struct */ #define __HAL_FMAC_CLEAR_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */ -/** @brief Check whether the specified FMAC status flag is set or not. +/** + * @brief Check whether the specified FMAC status flag is set or not. * @param __HANDLE__ FMAC handle. * @param __FLAG__ FMAC flag to check. * This parameter can be any combination of the following values: @@ -438,7 +455,8 @@ typedef struct #define __HAL_FMAC_GET_FLAG(__HANDLE__, __FLAG__) \ ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) -/** @brief Clear specified FMAC status flag. Dummy macro as no +/** + * @brief Clear specified FMAC status flag. Dummy macro as no flag can be cleared. * @param __HANDLE__ FMAC handle. * @param __FLAG__ FMAC flag to clear. @@ -446,7 +464,8 @@ typedef struct */ #define __HAL_FMAC_CLEAR_FLAG(__HANDLE__, __FLAG__) /* Dummy macro */ -/** @brief Check whether the specified FMAC interrupt is enabled or not. +/** + * @brief Check whether the specified FMAC interrupt is enabled or not. * @param __HANDLE__ FMAC handle. * @param __INTERRUPT__ FMAC interrupt to check. * This parameter can be one of the following values: @@ -663,8 +682,8 @@ void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac); * @{ */ /* Peripheral State functions *************************************************/ -HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac); -uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac); +HAL_FMAC_StateTypeDef HAL_FMAC_GetState(const FMAC_HandleTypeDef *hfmac); +uint32_t HAL_FMAC_GetError(const FMAC_HandleTypeDef *hfmac); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gfxmmu.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gfxmmu.c new file mode 100644 index 00000000000..6657ac84bc2 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gfxmmu.c @@ -0,0 +1,977 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_gfxmmu.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Graphic MMU (GFXMMU) peripheral: + * + Initialization and De-initialization. + * + LUT configuration. + * + Force flush and/or invalidate of cache. + * + Modify physical buffer addresses. + * + Modify cache and pre-fetch parameters. + * + Error management. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + *** Initialization *** + ====================== + [..] + (#) As prerequisite, fill in the HAL_GFXMMU_MspInit() : + (++) Enable GFXMMU clock interface with __HAL_RCC_GFXMMU_CLK_ENABLE(). + (++) If interrupts are used, enable and configure GFXMMU global + interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + (#) Configure the number of blocks per line, default value, physical + buffer addresses, cache and pre-fetch parameters and interrupts + using the HAL_GFXMMU_Init() function. + + *** LUT configuration *** + ========================= + [..] + (#) Use HAL_GFXMMU_DisableLutLines() to deactivate all LUT lines (or a + range of lines). + (#) Use HAL_GFXMMU_ConfigLut() to copy LUT from flash to look up RAM. + (#) Use HAL_GFXMMU_ConfigLutLine() to configure one line of LUT. + + *** Force flush and/or invalidate of cache *** + ============================================== + [..] + (#) Use HAL_GFXMMU_ConfigForceCache() to flush and/or invalidate cache. + + *** Modify physical buffer addresses *** + ======================================= + [..] + (#) Use HAL_GFXMMU_ModifyBuffers() to modify physical buffer addresses. + + *** Modify cache and pre-fetch parameters *** + ============================================= + [..] + (#) Use HAL_GFXMMU_ModifyCachePrefetch() to modify cache and pre-fetch + parameters. + + *** Modify address cache parameters *** + ========================================= + [..] + NOTE : This feature is only available on STM32U5F9/STM32U5G9 devices. + (#) Use HAL_GFXMMU_ModifyAddressCache() to modify address cache parameters. + + *** Error management *** + ======================== + [..] + (#) If interrupts are used, HAL_GFXMMU_IRQHandler() will be called when + an error occurs. This function will call HAL_GFXMMU_ErrorCallback(). + Use HAL_GFXMMU_GetError() to get the error code. + + *** De-initialization *** + ========================= + [..] + (#) As prerequisite, fill in the HAL_GFXMMU_MspDeInit() : + (++) Disable GFXMMU clock interface with __HAL_RCC_GFXMMU_CLK_ENABLE(). + (++) If interrupts has been used, disable GFXMMU global interrupt with + HAL_NVIC_DisableIRQ(). + (#) De-initialize GFXMMU using the HAL_GFXMMU_DeInit() function. + + *** Callback registration *** + ============================= + [..] + The compilation define USE_HAL_GFXMMU_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use functions HAL_GFXMMU_RegisterCallback() to register a user callback. + + [..] + Function HAL_GFXMMU_RegisterCallback() allows to register following callbacks: + (+) ErrorCallback : GFXMMU error. + (+) MspInitCallback : GFXMMU MspInit. + (+) MspDeInitCallback : GFXMMU MspDeInit. + [..] + This function takes as parameters the HAL peripheral handle, the callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_GFXMMU_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + HAL_GFXMMU_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the callback ID. + [..] + This function allows to reset following callbacks: + (+) ErrorCallback : GFXMMU error. + (+) MspInitCallback : GFXMMU MspInit. + (+) MspDeInitCallback : GFXMMU MspDeInit. + + [..] + By default, after the HAL_GFXMMU_Init and if the state is HAL_GFXMMU_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions: + examples HAL_GFXMMU_ErrorCallback(). + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the HAL_GFXMMU_Init + and HAL_GFXMMU_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_GFXMMU_Init and HAL_GFXMMU_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_GFXMMU_RegisterCallback before calling HAL_GFXMMU_DeInit + or HAL_GFXMMU_Init function. + + [..] + When the compilation define USE_HAL_GFXMMU_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ +#ifdef HAL_GFXMMU_MODULE_ENABLED +#if defined(GFXMMU) +/** @defgroup GFXMMU GFXMMU + * @brief GFXMMU HAL driver module + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup GFXMMU_Private_Constants GFXMMU Private Constants + * @{ + */ +#define GFXMMU_LUTXL_FVB_OFFSET 8U +#define GFXMMU_LUTXL_LVB_OFFSET 16U +#define GFXMMU_CR_ITS_MASK 0x1FU +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GFXMMU_Exported_Functions GFXMMU Exported Functions + * @{ + */ + +/** @defgroup GFXMMU_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the GFXMMU. + (+) De-initialize the GFXMMU. +@endverbatim + * @{ + */ + +/** + * @brief Initialize the GFXMMU according to the specified parameters in the + * GFXMMU_InitTypeDef structure and initialize the associated handle. + * @param hgfxmmu GFXMMU handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check GFXMMU handle */ + if (hgfxmmu == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + assert_param(IS_GFXMMU_BLOCKS_PER_LINE(hgfxmmu->Init.BlocksPerLine)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf0Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf1Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf2Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf3Address)); +#if defined(GFXMMU_CR_CE) + assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.CachePrefetch.Activation)); +#endif /* GFXMMU_CR_CE */ + assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.Interrupts.Activation)); +#if defined (GFXMMU_CR_ACE) + assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.AddressCache.Activation)); +#endif /* GFXMMU_CR_ACE */ + +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) + /* Reset callback pointers to the weak predefined callbacks */ + hgfxmmu->ErrorCallback = HAL_GFXMMU_ErrorCallback; + + /* Call GFXMMU MSP init function */ + if (hgfxmmu->MspInitCallback == NULL) + { + hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit; + } + hgfxmmu->MspInitCallback(hgfxmmu); +#else + /* Call GFXMMU MSP init function */ + HAL_GFXMMU_MspInit(hgfxmmu); +#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */ + + /* Configure blocks per line, cache and interrupts parameters on GFXMMU_CR register */ + hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0OIE | GFXMMU_CR_B1OIE | GFXMMU_CR_B2OIE | GFXMMU_CR_B3OIE | + GFXMMU_CR_AMEIE | GFXMMU_CR_192BM); +#if defined(GFXMMU_CR_CE) + hgfxmmu->Instance->CR &= ~(GFXMMU_CR_CE | GFXMMU_CR_CL | GFXMMU_CR_CLB | GFXMMU_CR_FC | + GFXMMU_CR_PD | GFXMMU_CR_OC | GFXMMU_CR_OB); +#endif /* GFXMMU_CR_CE */ + +#if defined (GFXMMU_CR_ACE) + hgfxmmu->Instance->CR &= ~(GFXMMU_CR_ACE | GFXMMU_CR_ACLB); +#endif /* GFXMMU_CR_ACE */ + + hgfxmmu->Instance->CR |= (hgfxmmu->Init.BlocksPerLine); +#if defined(GFXMMU_CR_CE) + if (hgfxmmu->Init.CachePrefetch.Activation == ENABLE) + { + assert_param(IS_GFXMMU_CACHE_LOCK(hgfxmmu->Init.CachePrefetch.CacheLock)); + assert_param(IS_GFXMMU_PREFETCH(hgfxmmu->Init.CachePrefetch.Prefetch)); + assert_param(IS_GFXMMU_OUTTER_BUFFERABILITY(hgfxmmu->Init.CachePrefetch.OutterBufferability)); + assert_param(IS_GFXMMU_OUTTER_CACHABILITY(hgfxmmu->Init.CachePrefetch.OutterCachability)); + hgfxmmu->Instance->CR |= (GFXMMU_CR_CE | + hgfxmmu->Init.CachePrefetch.CacheLock | + hgfxmmu->Init.CachePrefetch.Prefetch | + hgfxmmu->Init.CachePrefetch.OutterBufferability | + hgfxmmu->Init.CachePrefetch.OutterCachability); + if (hgfxmmu->Init.CachePrefetch.CacheLock == GFXMMU_CACHE_LOCK_ENABLE) + { + assert_param(IS_GFXMMU_CACHE_LOCK_BUFFER(hgfxmmu->Init.CachePrefetch.CacheLockBuffer)); + assert_param(IS_GFXMMU_CACHE_FORCE(hgfxmmu->Init.CachePrefetch.CacheForce)); + hgfxmmu->Instance->CR |= (hgfxmmu->Init.CachePrefetch.CacheLockBuffer | + hgfxmmu->Init.CachePrefetch.CacheForce); + } + } +#endif /* GFXMMU_CR_CE */ + if (hgfxmmu->Init.Interrupts.Activation == ENABLE) + { + assert_param(IS_GFXMMU_INTERRUPTS(hgfxmmu->Init.Interrupts.UsedInterrupts)); + hgfxmmu->Instance->CR |= hgfxmmu->Init.Interrupts.UsedInterrupts; + } + + /* Configure default value on GFXMMU_DVR register */ + hgfxmmu->Instance->DVR = hgfxmmu->Init.DefaultValue; + + /* Configure physical buffer addresses on GFXMMU_BxCR registers */ + hgfxmmu->Instance->B0CR = hgfxmmu->Init.Buffers.Buf0Address; + hgfxmmu->Instance->B1CR = hgfxmmu->Init.Buffers.Buf1Address; + hgfxmmu->Instance->B2CR = hgfxmmu->Init.Buffers.Buf2Address; + hgfxmmu->Instance->B3CR = hgfxmmu->Init.Buffers.Buf3Address; + +#if defined(GFXMMU_CR_CE) + /* Force invalidate cache if cache is enabled */ + if (hgfxmmu->Init.CachePrefetch.Activation == ENABLE) + { + hgfxmmu->Instance->CCR |= GFXMMU_CACHE_FORCE_INVALIDATE; + } +#endif /* GFXMMU_CR_CE */ +#if defined (GFXMMU_CR_ACE) + if (hgfxmmu->Init.AddressCache.Activation == ENABLE) + { + assert_param(IS_GFXMMU_ADDRESSCACHE_LOCK_BUFFER(hgfxmmu->Init.AddressCache.AddressCacheLockBuffer)); + hgfxmmu->Instance->CR |= GFXMMU_CR_ACE | + hgfxmmu->Init.AddressCache.AddressCacheLockBuffer; + } +#endif /* GFXMMU_CR_ACE */ + + /* Reset GFXMMU error code */ + hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE; + + /* Set GFXMMU to ready state */ + hgfxmmu->State = HAL_GFXMMU_STATE_READY; + } + /* Return function status */ + return status; +} + +/** + * @brief De-initialize the GFXMMU. + * @param hgfxmmu GFXMMU handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check GFXMMU handle */ + if (hgfxmmu == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + + /* Disable all interrupts on GFXMMU_CR register */ + hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0OIE | GFXMMU_CR_B1OIE | GFXMMU_CR_B2OIE | GFXMMU_CR_B3OIE | + GFXMMU_CR_AMEIE); + + /* Call GFXMMU MSP de-init function */ +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) + if (hgfxmmu->MspDeInitCallback == NULL) + { + hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit; + } + hgfxmmu->MspDeInitCallback(hgfxmmu); +#else + HAL_GFXMMU_MspDeInit(hgfxmmu); +#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */ + + /* Set GFXMMU to reset state */ + hgfxmmu->State = HAL_GFXMMU_STATE_RESET; + } + /* Return function status */ + return status; +} + +/** + * @brief Initialize the GFXMMU MSP. + * @param hgfxmmu GFXMMU handle. + * @retval None. + */ +__weak void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxmmu); + + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXMMU_MspInit could be implemented in the user file. + */ +} + +/** + * @brief De-initialize the GFXMMU MSP. + * @param hgfxmmu GFXMMU handle. + * @retval None. + */ +__weak void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxmmu); + + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXMMU_MspDeInit could be implemented in the user file. + */ +} + +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) +/** + * @brief Register a user GFXMMU callback + * to be used instead of the weak predefined callback. + * @param hgfxmmu GFXMMU handle. + * @param CallbackID ID of the callback to be registered. + * This parameter can be one of the following values: + * @arg @ref HAL_GFXMMU_ERROR_CB_ID error callback ID. + * @arg @ref HAL_GFXMMU_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_GFXMMU_MSPDEINIT_CB_ID MSP de-init callback ID. + * @param pCallback pointer to the callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu, + HAL_GFXMMU_CallbackIDTypeDef CallbackID, + pGFXMMU_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + else + { + if (HAL_GFXMMU_STATE_READY == hgfxmmu->State) + { + switch (CallbackID) + { + case HAL_GFXMMU_ERROR_CB_ID : + hgfxmmu->ErrorCallback = pCallback; + break; + case HAL_GFXMMU_MSPINIT_CB_ID : + hgfxmmu->MspInitCallback = pCallback; + break; + case HAL_GFXMMU_MSPDEINIT_CB_ID : + hgfxmmu->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_GFXMMU_STATE_RESET == hgfxmmu->State) + { + switch (CallbackID) + { + case HAL_GFXMMU_MSPINIT_CB_ID : + hgfxmmu->MspInitCallback = pCallback; + break; + case HAL_GFXMMU_MSPDEINIT_CB_ID : + hgfxmmu->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief Unregister a user GFXMMU callback. + * GFXMMU callback is redirected to the weak predefined callback. + * @param hgfxmmu GFXMMU handle. + * @param CallbackID ID of the callback to be unregistered. + * This parameter can be one of the following values: + * @arg @ref HAL_GFXMMU_ERROR_CB_ID error callback ID. + * @arg @ref HAL_GFXMMU_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_GFXMMU_MSPDEINIT_CB_ID MSP de-init callback ID. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu, + HAL_GFXMMU_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_GFXMMU_STATE_READY == hgfxmmu->State) + { + switch (CallbackID) + { + case HAL_GFXMMU_ERROR_CB_ID : + hgfxmmu->ErrorCallback = HAL_GFXMMU_ErrorCallback; + break; + case HAL_GFXMMU_MSPINIT_CB_ID : + hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit; + break; + case HAL_GFXMMU_MSPDEINIT_CB_ID : + hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit; + break; + default : + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_GFXMMU_STATE_RESET == hgfxmmu->State) + { + switch (CallbackID) + { + case HAL_GFXMMU_MSPINIT_CB_ID : + hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit; + break; + case HAL_GFXMMU_MSPDEINIT_CB_ID : + hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit; + break; + default : + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + return status; +} +#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup GFXMMU_Exported_Functions_Group2 Operations functions + * @brief GFXMMU operation functions + * +@verbatim + ============================================================================== + ##### Operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure LUT. + (+) Force flush and/or invalidate of cache. + (+) Modify physical buffer addresses. + (+) Modify cache and pre-fetch parameters. + (+) Manage error. +@endverbatim + * @{ + */ + +/** + * @brief This function allows to copy LUT from flash to look up RAM. + * @param hgfxmmu GFXMMU handle. + * @param FirstLine First line enabled on LUT. + * This parameter must be a number between Min_Data = 0 and Max_Data = 1023. + * @param LinesNumber Number of lines enabled on LUT. + * This parameter must be a number between Min_Data = 1 and Max_Data = 1024. + * @param Address Start address of LUT in flash. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, + uint32_t FirstLine, + uint32_t LinesNumber, + uint32_t Address) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + assert_param(IS_GFXMMU_LUT_LINE(FirstLine)); + assert_param(IS_GFXMMU_LUT_LINES_NUMBER(LinesNumber)); + + /* Check GFXMMU state and coherent parameters */ + if ((hgfxmmu->State != HAL_GFXMMU_STATE_READY) || ((FirstLine + LinesNumber) > 1024U)) + { + status = HAL_ERROR; + } + else + { + uint32_t current_address; + uint32_t current_line; + uint32_t lutxl_address; + uint32_t lutxh_address; + + /* Initialize local variables */ + current_address = Address; + current_line = 0U; + lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * FirstLine]); + lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * FirstLine) + 1U]); + + /* Copy LUT from flash to look up RAM */ + while (current_line < LinesNumber) + { + *((uint32_t *)lutxl_address) = *((uint32_t *)current_address); + current_address += 4U; + *((uint32_t *)lutxh_address) = *((uint32_t *)current_address); + current_address += 4U; + lutxl_address += 8U; + lutxh_address += 8U; + current_line++; + } + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to disable a range of LUT lines. + * @param hgfxmmu GFXMMU handle. + * @param FirstLine First line to disable on LUT. + * This parameter must be a number between Min_Data = 0 and Max_Data = 1023. + * @param LinesNumber Number of lines to disable on LUT. + * This parameter must be a number between Min_Data = 1 and Max_Data = 1024. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, + uint32_t FirstLine, + uint32_t LinesNumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + assert_param(IS_GFXMMU_LUT_LINE(FirstLine)); + assert_param(IS_GFXMMU_LUT_LINES_NUMBER(LinesNumber)); + + /* Check GFXMMU state and coherent parameters */ + if ((hgfxmmu->State != HAL_GFXMMU_STATE_READY) || ((FirstLine + LinesNumber) > 1024U)) + { + status = HAL_ERROR; + } + else + { + uint32_t current_line; + uint32_t lutxl_address; + uint32_t lutxh_address; + + /* Initialize local variables */ + current_line = 0U; + lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * FirstLine]); + lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * FirstLine) + 1U]); + + /* Disable LUT lines */ + while (current_line < LinesNumber) + { + *((uint32_t *)lutxl_address) = 0U; + *((uint32_t *)lutxh_address) = 0U; + lutxl_address += 8U; + lutxh_address += 8U; + current_line++; + } + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to configure one line of LUT. + * @param hgfxmmu GFXMMU handle. + * @param lutLine LUT line parameters. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + assert_param(IS_GFXMMU_LUT_LINE(lutLine->LineNumber)); + assert_param(IS_GFXMMU_LUT_LINE_STATUS(lutLine->LineStatus)); + assert_param(IS_GFXMMU_LUT_BLOCK(lutLine->FirstVisibleBlock)); + assert_param(IS_GFXMMU_LUT_BLOCK(lutLine->LastVisibleBlock)); + assert_param(IS_GFXMMU_LUT_LINE_OFFSET(lutLine->LineOffset)); + + /* Check GFXMMU state */ + if (hgfxmmu->State != HAL_GFXMMU_STATE_READY) + { + status = HAL_ERROR; + } + else + { + uint32_t lutxl_address; + uint32_t lutxh_address; + + /* Initialize local variables */ + lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * lutLine->LineNumber]); + lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * lutLine->LineNumber) + 1U]); + + /* Configure LUT line */ + if (lutLine->LineStatus == GFXMMU_LUT_LINE_ENABLE) + { + /* Enable and configure LUT line */ + *((uint32_t *)lutxl_address) = (lutLine->LineStatus | + (lutLine->FirstVisibleBlock << GFXMMU_LUTXL_FVB_OFFSET) | + (lutLine->LastVisibleBlock << GFXMMU_LUTXL_LVB_OFFSET)); + *((uint32_t *)lutxh_address) = (uint32_t) lutLine->LineOffset; + } + else + { + /* Disable LUT line */ + *((uint32_t *)lutxl_address) = 0U; + *((uint32_t *)lutxh_address) = 0U; + } + } + /* Return function status */ + return status; +} + +#if defined(GFXMMU_CR_CE) +/** + * @brief This function allows to force flush and/or invalidate of cache. + * @param hgfxmmu GFXMMU handle. + * @param ForceParam Force cache parameter. + * This parameter can be a values combination of @ref GFXMMU_CacheForceParam. + * @retval HAL status. + * @note This function is only available on STM32U599/STM32U5A9 devices. + */ +HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + assert_param(IS_GFXMMU_CACHE_FORCE_ACTION(ForceParam)); + + /* Check GFXMMU state and cache status */ + if (((hgfxmmu->Instance->CR & GFXMMU_CR_CE) != GFXMMU_CR_CE) || (hgfxmmu->State != HAL_GFXMMU_STATE_READY)) + { + status = HAL_ERROR; + } + else + { + /* Force flush and/or invalidate cache on GFXMMU_CCR register */ + hgfxmmu->Instance->CCR |= ForceParam; + } + /* Return function status */ + return status; +} +#endif /* GFXMMU_CR_CE */ + +/** + * @brief This function allows to modify physical buffer addresses. + * @param hgfxmmu GFXMMU handle. + * @param Buffers Buffers parameters. + * @retval HAL status. + * @note This function is only available on STM32U599/STM32U5A9 devices. + */ +HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf0Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf1Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf2Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf3Address)); + + /* Check GFXMMU state */ + if (hgfxmmu->State != HAL_GFXMMU_STATE_READY) + { + status = HAL_ERROR; + } + else + { + /* Modify physical buffer addresses on GFXMMU_BxCR registers */ + hgfxmmu->Instance->B0CR = Buffers->Buf0Address; + hgfxmmu->Instance->B1CR = Buffers->Buf1Address; + hgfxmmu->Instance->B2CR = Buffers->Buf2Address; + hgfxmmu->Instance->B3CR = Buffers->Buf3Address; + } + /* Return function status */ + return status; +} + +#if defined(GFXMMU_CR_CE) +/** + * @brief This function allows to modify cache and pre-fetch parameters. + * @param hgfxmmu GFXMMU handle. + * @param CachePrefetch Cache and pre-fetch parameters. + * @retval HAL status. + * @note This function is only available on STM32U599/STM32U5A9 devices. + */ +HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch(GFXMMU_HandleTypeDef *hgfxmmu, + GFXMMU_CachePrefetchTypeDef *CachePrefetch) +{ + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_FUNCTIONAL_STATE(CachePrefetch->Activation)); + + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + + /* Check GFXMMU state */ + if (hgfxmmu->State != HAL_GFXMMU_STATE_READY) + { + status = HAL_ERROR; + } + else + { + /* Modify cache and pre-fetch parameters on GFXMMU_CR register */ + hgfxmmu->Instance->CR &= ~(GFXMMU_CR_CE | GFXMMU_CR_CL | GFXMMU_CR_CLB | GFXMMU_CR_FC | + GFXMMU_CR_PD | GFXMMU_CR_OC | GFXMMU_CR_OB); + if (CachePrefetch->Activation == ENABLE) + { + assert_param(IS_GFXMMU_CACHE_LOCK(CachePrefetch->CacheLock)); + assert_param(IS_GFXMMU_PREFETCH(CachePrefetch->Prefetch)); + assert_param(IS_GFXMMU_OUTTER_BUFFERABILITY(CachePrefetch->OutterBufferability)); + assert_param(IS_GFXMMU_OUTTER_CACHABILITY(CachePrefetch->OutterCachability)); + hgfxmmu->Instance->CR |= (GFXMMU_CR_CE | + CachePrefetch->CacheLock | + CachePrefetch->Prefetch | + CachePrefetch->OutterBufferability | + CachePrefetch->OutterCachability); + if (CachePrefetch->CacheLock == GFXMMU_CACHE_LOCK_ENABLE) + { + assert_param(IS_GFXMMU_CACHE_LOCK_BUFFER(CachePrefetch->CacheLockBuffer)); + assert_param(IS_GFXMMU_CACHE_FORCE(CachePrefetch->CacheForce)); + hgfxmmu->Instance->CR |= (CachePrefetch->CacheLockBuffer | + CachePrefetch->CacheForce); + } + } + } + /* Return function status */ + return status; +} +#endif /* GFXMMU_CR_CE */ + +#if defined (GFXMMU_CR_ACE) +/** + * @brief This function allows to modify address cache parameters. + * @param hgfxmmu GFXMMU handle. + * @param address cache parameters. + * @retval HAL status. + * @note This function is only available on STM32U5F9/STM32U5G9 devices. + */ +HAL_StatusTypeDef HAL_GFXMMU_ModifyAddressCache(GFXMMU_HandleTypeDef *hgfxmmu, + GFXMMU_AddressCacheTypeDef *AddressCache) +{ + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_FUNCTIONAL_STATE(AddressCache->Activation)); + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + /* Check GFXMMU state */ + if (hgfxmmu->State != HAL_GFXMMU_STATE_READY) + { + status = HAL_ERROR; + } + else + { + /* Modify Address cache parameters on GFXMMU_CR register */ + hgfxmmu->Instance->CR &= ~(GFXMMU_CR_ACE | GFXMMU_CR_ACLB); + if (AddressCache->Activation == ENABLE) + { + assert_param(IS_GFXMMU_ADDRESSCACHE_LOCK_BUFFER(AddressCache->AddressCacheLockBuffer)); + hgfxmmu->Instance->CR |= (GFXMMU_CR_ACE | + AddressCache->AddressCacheLockBuffer); + } + } + /* Return function status */ + return status; +} +#endif /* GFXMMU_CR_ACE */ + +/** + * @brief This function handles the GFXMMU interrupts. + * @param hgfxmmu GFXMMU handle. + * @retval None. + */ +void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu) +{ + uint32_t flags, interrupts, error; + + /* Read current flags and interrupts and determine which error occurs */ + flags = hgfxmmu->Instance->SR; + interrupts = (hgfxmmu->Instance->CR & GFXMMU_CR_ITS_MASK); + error = (flags & interrupts); + + if (error != 0U) + { + /* Clear flags on GFXMMU_FCR register */ + hgfxmmu->Instance->FCR = error; + + /* Update GFXMMU error code */ + hgfxmmu->ErrorCode |= error; + + /* Call GFXMMU error callback */ +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) + hgfxmmu->ErrorCallback(hgfxmmu); +#else + HAL_GFXMMU_ErrorCallback(hgfxmmu); +#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */ + } +} + +/** + * @brief Error callback. + * @param hgfxmmu GFXMMU handle. + * @retval None. + */ +__weak void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxmmu); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_GFXMMU_ErrorCallback could be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup GFXMMU_Exported_Functions_Group3 State functions + * @brief GFXMMU state functions + * +@verbatim + ============================================================================== + ##### State functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Get GFXMMU handle state. + (+) Get GFXMMU error code. +@endverbatim + * @{ + */ + +/** + * @brief This function allows to get the current GFXMMU handle state. + * @param hgfxmmu GFXMMU handle. + * @retval GFXMMU state. + */ +HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu) +{ + /* Return GFXMMU handle state */ + return hgfxmmu->State; +} + +/** + * @brief This function allows to get the current GFXMMU error code. + * @param hgfxmmu GFXMMU handle. + * @retval GFXMMU error code. + */ +uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu) +{ + uint32_t error_code; + + /* Enter in critical section */ + __disable_irq(); + + /* Store and reset GFXMMU error code */ + error_code = hgfxmmu->ErrorCode; + hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE; + + /* Exit from critical section */ + __enable_irq(); + + /* Return GFXMMU error code */ + return error_code; +} + +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ +#endif /* GFXMMU */ +#endif /* HAL_GFXMMU_MODULE_ENABLED */ +/** + * @} + */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gfxmmu.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gfxmmu.h new file mode 100644 index 00000000000..6806565e8a8 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gfxmmu.h @@ -0,0 +1,504 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_gfxmmu.h + * @author MCD Application Team + * @brief Header file of GFXMMU HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_GFXMMU_H +#define STM32U5xx_HAL_GFXMMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +#if defined(GFXMMU) + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup GFXMMU + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup GFXMMU_Exported_Types GFXMMU Exported Types + * @{ + */ + +/** + * @brief HAL GFXMMU states definition + */ +typedef enum +{ + HAL_GFXMMU_STATE_RESET = 0x00U, /*!< GFXMMU not initialized */ + HAL_GFXMMU_STATE_READY = 0x01U, /*!< GFXMMU initialized and ready for use */ +} HAL_GFXMMU_StateTypeDef; + +/** + * @brief GFXMMU buffers structure definition + */ +typedef struct +{ + uint32_t Buf0Address; /*!< Physical address of buffer 0. */ + uint32_t Buf1Address; /*!< Physical address of buffer 1. */ + uint32_t Buf2Address; /*!< Physical address of buffer 2. */ + uint32_t Buf3Address; /*!< Physical address of buffer 3. */ +} GFXMMU_BuffersTypeDef; + +#if defined (GFXMMU_CR_CE) +/** + * @brief GFXMMU cache and pre-fetch structure definition + */ +typedef struct +{ + FunctionalState Activation; /*!< Cache and pre-fetch enable/disable. + @note: All following parameters are useful only if cache + and pre-fetch are enabled. */ + uint32_t CacheLock; /*!< Locking the cache to a buffer. + This parameter can be a value of @ref GFXMMU_CacheLock. */ + uint32_t CacheLockBuffer; /*!< Buffer on which the cache is locked. + This parameter can be a value of @ref GFXMMU_CacheLockBuffer. + @note: Useful only when lock of the cache is enabled. */ + uint32_t CacheForce; /*!< Forcing the cache regardless MPU attributes. + This parameter can be a value of @ref GFXMMU_CacheForce. + @note: Useful only when lock of the cache is enabled. */ + uint32_t OutterBufferability; /*!< Bufferability of an access generated by the GFXMMU cache. + This parameter can be a value of @ref GFXMMU_OutterBufferability. */ + uint32_t OutterCachability; /*!< Cachability of an access generated by the GFXMMU cache. + This parameter can be a value of @ref GFXMMU_OutterCachability. */ + uint32_t Prefetch; /*!< Pre-fetch enable/disable. + This parameter can be a value of @ref GFXMMU_Prefetch. */ +} GFXMMU_CachePrefetchTypeDef; +#endif /* GFXMMU_CR_CE */ + +#if defined (GFXMMU_CR_ACE) +/** + * @brief GFXMMU address cache structure definition + */ +typedef struct +{ + FunctionalState Activation; /*!< Address Cache and enable/disable. + @note: All following parameters are useful only if address + cache is enabled. */ + uint32_t AddressCacheLockBuffer; /*!< Buffer on which the address cache is locked. + This parameter can be a value of @ref GFXMMU_AddressCacheLockBuffer. + @note: Useful only when lock of the address cache is enabled. */ +} GFXMMU_AddressCacheTypeDef; +#endif /* GFXMMU_CR_ACE */ + +/** + * @brief GFXMMU interrupts structure definition + */ +typedef struct +{ + FunctionalState Activation; /*!< Interrupts enable/disable */ + uint32_t UsedInterrupts; /*!< Interrupts used. + This parameter can be a values combination of @ref GFXMMU_Interrupts. + @note: Useful only when interrupts are enabled. */ +} GFXMMU_InterruptsTypeDef; + +/** + * @brief GFXMMU init structure definition + */ +typedef struct +{ + uint32_t BlocksPerLine; /*!< Number of blocks of 16 bytes per line. + This parameter can be a value of @ref GFXMMU_BlocksPerLine. */ + uint32_t DefaultValue; /*!< Value returned when virtual memory location not physically mapped. */ + GFXMMU_BuffersTypeDef Buffers; /*!< Physical buffers addresses. */ +#if defined (GFXMMU_CR_CE) + GFXMMU_CachePrefetchTypeDef CachePrefetch; /*!< Cache and pre-fetch parameters. */ +#endif /* GFXMMU_CR_CE */ +#if defined (GFXMMU_CR_ACE) + GFXMMU_AddressCacheTypeDef AddressCache; /*!< Address Cache parameters. */ +#endif /* GFXMMU_CR_ACE */ + GFXMMU_InterruptsTypeDef Interrupts; /*!< Interrupts parameters. */ + +} GFXMMU_InitTypeDef; + +/** + * @brief GFXMMU handle structure definition + */ +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) +typedef struct __GFXMMU_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */ +{ + GFXMMU_TypeDef *Instance; /*!< GFXMMU instance */ + GFXMMU_InitTypeDef Init; /*!< GFXMMU init parameters */ + HAL_GFXMMU_StateTypeDef State; /*!< GFXMMU state */ + __IO uint32_t ErrorCode; /*!< GFXMMU error code */ +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) + void (*ErrorCallback)(struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU error callback */ + void (*MspInitCallback)(struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP init callback */ + void (*MspDeInitCallback)(struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP de-init callback */ +#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */ +} GFXMMU_HandleTypeDef; + +/** + * @brief GFXMMU LUT line structure definition + */ +typedef struct +{ + uint32_t LineNumber; /*!< LUT line number. + This parameter must be a number between Min_Data = 0 and Max_Data = 1023. */ + uint32_t LineStatus; /*!< LUT line enable/disable. + This parameter can be a value of @ref GFXMMU_LutLineStatus. */ + uint32_t FirstVisibleBlock; /*!< First visible block on this line. + This parameter must be a number between Min_Data = 0 and Max_Data = 255. */ + uint32_t LastVisibleBlock; /*!< Last visible block on this line. + This parameter must be a number between Min_Data = 0 and Max_Data = 255. */ + int32_t LineOffset; /*!< Offset of block 0 of the current line in physical buffer. + This parameter must be a number between Min_Data = -4080 and Max_Data = 4190208. + @note: Line offset has to be computed with the following formula: + LineOffset = [(Blocks already used) - (1st visible block)]*BlockSize. */ +} GFXMMU_LutLineTypeDef; + +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) +/** + * @brief GFXMMU callback ID enumeration definition + */ +typedef enum +{ + HAL_GFXMMU_ERROR_CB_ID = 0x00U, /*!< GFXMMU error callback ID */ + HAL_GFXMMU_MSPINIT_CB_ID = 0x01U, /*!< GFXMMU MSP init callback ID */ + HAL_GFXMMU_MSPDEINIT_CB_ID = 0x02U /*!< GFXMMU MSP de-init callback ID */ +} HAL_GFXMMU_CallbackIDTypeDef; + +/** + * @brief GFXMMU callback pointer definition + */ +typedef void (*pGFXMMU_CallbackTypeDef)(GFXMMU_HandleTypeDef *hgfxmmu); +#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */ + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GFXMMU_Exported_Constants GFXMMU Exported Constants + * @{ + */ + +/** @defgroup GFXMMU_BlocksPerLine GFXMMU blocks per line + * @{ + */ +#define GFXMMU_256BLOCKS 0x00000000U /*!< 256 blocks of 16 bytes per line */ +#define GFXMMU_192BLOCKS GFXMMU_CR_192BM /*!< 192 blocks of 16 bytes per line */ +/** + * @} + */ + +/** @defgroup GFXMMU_CacheLock GFXMMU cache lock + * @{ + */ +#define GFXMMU_CACHE_LOCK_DISABLE 0x00000000U /*!< Cache not locked to a buffer */ +#define GFXMMU_CACHE_LOCK_ENABLE GFXMMU_CR_CL /*!< Cache locked to a buffer */ +/** + * @} + */ + +/** @defgroup GFXMMU_CacheLockBuffer GFXMMU cache lock buffer + * @{ + */ +#define GFXMMU_CACHE_LOCK_BUFFER0 0x00000000U /*!< Cache locked to buffer 0 */ +#define GFXMMU_CACHE_LOCK_BUFFER1 GFXMMU_CR_CLB_0 /*!< Cache locked to buffer 1 */ +#define GFXMMU_CACHE_LOCK_BUFFER2 GFXMMU_CR_CLB_1 /*!< Cache locked to buffer 2 */ +#define GFXMMU_CACHE_LOCK_BUFFER3 GFXMMU_CR_CLB /*!< Cache locked to buffer 3 */ +/** + * @} + */ + +/** @defgroup GFXMMU_CacheForce GFXMMU cache force + * @{ + */ +#define GFXMMU_CACHE_FORCE_DISABLE 0x00000000U /*!< Caching not forced */ +#define GFXMMU_CACHE_FORCE_ENABLE GFXMMU_CR_FC /*!< Caching forced */ +/** + * @} + */ + +/** @defgroup GFXMMU_OutterBufferability GFXMMU outer bufferability + * @{ + */ +#define GFXMMU_OUTTER_BUFFERABILITY_DISABLE 0x00000000U /*!< No bufferable */ +#define GFXMMU_OUTTER_BUFFERABILITY_ENABLE GFXMMU_CR_OB /*!< Bufferable */ +/** + * @} + */ + +/** @defgroup GFXMMU_OutterCachability GFXMMU outer cachability + * @{ + */ +#define GFXMMU_OUTTER_CACHABILITY_DISABLE 0x00000000U /*!< No cacheable */ +#define GFXMMU_OUTTER_CACHABILITY_ENABLE GFXMMU_CR_OC /*!< Cacheable */ +/** + * @} + */ + +/** @defgroup GFXMMU_Prefetch GFXMMU pre-fetch + * @{ + */ +#define GFXMMU_PREFETCH_DISABLE GFXMMU_CR_PD /*!< Pre-fetch disable */ +#define GFXMMU_PREFETCH_ENABLE 0x00000000U /*!< Pre-fetch enable */ +/** + * @} + */ + +/** @defgroup GFXMMU_Interrupts GFXMMU interrupts + * @{ + */ +#define GFXMMU_AHB_MASTER_ERROR_IT GFXMMU_CR_AMEIE /*!< AHB master error interrupt */ +#define GFXMMU_BUFFER0_OVERFLOW_IT GFXMMU_CR_B0OIE /*!< Buffer 0 overflow interrupt */ +#define GFXMMU_BUFFER1_OVERFLOW_IT GFXMMU_CR_B1OIE /*!< Buffer 1 overflow interrupt */ +#define GFXMMU_BUFFER2_OVERFLOW_IT GFXMMU_CR_B2OIE /*!< Buffer 2 overflow interrupt */ +#define GFXMMU_BUFFER3_OVERFLOW_IT GFXMMU_CR_B3OIE /*!< Buffer 3 overflow interrupt */ +/** + * @} + */ + +/** @defgroup GFXMMU_Error_Code GFXMMU Error Code + * @{ + */ +#define GFXMMU_ERROR_NONE 0x00000000U /*!< No error */ +#define GFXMMU_ERROR_BUFFER0_OVERFLOW GFXMMU_SR_B0OF /*!< Buffer 0 overflow */ +#define GFXMMU_ERROR_BUFFER1_OVERFLOW GFXMMU_SR_B1OF /*!< Buffer 1 overflow */ +#define GFXMMU_ERROR_BUFFER2_OVERFLOW GFXMMU_SR_B2OF /*!< Buffer 2 overflow */ +#define GFXMMU_ERROR_BUFFER3_OVERFLOW GFXMMU_SR_B3OF /*!< Buffer 3 overflow */ +#define GFXMMU_ERROR_AHB_MASTER GFXMMU_SR_AMEF /*!< AHB master error */ +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) +#define GFXMMU_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */ +#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */ +/** + * @} + */ + +/** @defgroup GFXMMU_LutLineStatus GFXMMU LUT line status + * @{ + */ +#define GFXMMU_LUT_LINE_DISABLE 0x00000000U /*!< LUT line disabled */ +#define GFXMMU_LUT_LINE_ENABLE GFXMMU_LUTxL_EN /*!< LUT line enabled */ +/** + * @} + */ + +/** @defgroup GFXMMU_CacheForceParam GFXMMU cache force parameter + * @{ + */ +#define GFXMMU_CACHE_FORCE_FLUSH GFXMMU_CCR_FF /*!< Force cache flush */ +#define GFXMMU_CACHE_FORCE_INVALIDATE GFXMMU_CCR_FI /*!< Force cache invalidate */ +/** + * @} + */ + +#if defined (GFXMMU_CR_ACE) +/** @defgroup GFXMMU_CacheLockBuffer GFXMMU address cache lock buffer + * @{ + */ +#define GFXMMU_ADDRESSCACHE_LOCK_BUFFER0 0x00000000U /*!< Address Cache locked to buffer 0 */ +#define GFXMMU_ADDRESSCACHE_LOCK_BUFFER1 GFXMMU_CR_ACLB_0 /*!< Address Cache locked to buffer 1 */ +#define GFXMMU_ADDRESSCACHE_LOCK_BUFFER2 GFXMMU_CR_ACLB_1 /*!< Address Cache locked to buffer 2 */ +#define GFXMMU_ADDRESSCACHE_LOCK_BUFFER3 GFXMMU_CR_ACLB /*!< Address Cache locked to buffer 3 */ +/** + * @} + */ +#endif /* GFXMMU_CR_ACE */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup GFXMMU_Exported_Macros GFXMMU Exported Macros + * @{ + */ + +/** @brief Reset GFXMMU handle state. + * @param __HANDLE__ GFXMMU handle. + * @retval None + */ +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) +#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_GFXMMU_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GFXMMU_STATE_RESET) +#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */ + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GFXMMU_Exported_Functions GFXMMU Exported Functions + * @{ + */ + +/** @addtogroup GFXMMU_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu); +HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu); +void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu); +void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu); +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) +/* GFXMMU callbacks register/unregister functions *****************************/ +HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu, + HAL_GFXMMU_CallbackIDTypeDef CallbackID, + pGFXMMU_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu, + HAL_GFXMMU_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */ +/** + * @} + */ + +/** @addtogroup GFXMMU_Exported_Functions_Group2 Operations functions + * @{ + */ +/* Operation functions ********************************************************/ +HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, + uint32_t FirstLine, + uint32_t LinesNumber, + uint32_t Address); + +HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, + uint32_t FirstLine, + uint32_t LinesNumber); + +HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine); + +#if defined (GFXMMU_CR_CE) +HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam); +#endif /* GFXMMU_CR_CE */ + +HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers); + +#if defined (GFXMMU_CR_CE) +HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch(GFXMMU_HandleTypeDef *hgfxmmu, + GFXMMU_CachePrefetchTypeDef *CachePrefetch); +#endif /* GFXMMU_CR_CE */ + +#if defined (GFXMMU_CR_ACE) +HAL_StatusTypeDef HAL_GFXMMU_ModifyAddressCache(GFXMMU_HandleTypeDef *hgfxmmu, + GFXMMU_AddressCacheTypeDef *AddressCache); +#endif /* GFXMMU_CR_ACE */ + +void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu); + +void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu); +/** + * @} + */ + +/** @defgroup GFXMMU_Exported_Functions_Group3 State functions + * @{ + */ +/* State function *************************************************************/ +HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu); + +uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GFXMMU_Private_Macros GFXMMU Private Macros + * @{ + */ +#define IS_GFXMMU_BLOCKS_PER_LINE(VALUE) (((VALUE) == GFXMMU_256BLOCKS) || \ + ((VALUE) == GFXMMU_192BLOCKS)) + +#define IS_GFXMMU_BUFFER_ADDRESS(VALUE) (((VALUE) & 0xFU) == 0U) + +#define IS_GFXMMU_CACHE_LOCK(VALUE) (((VALUE) == GFXMMU_CACHE_LOCK_DISABLE) || \ + ((VALUE) == GFXMMU_CACHE_LOCK_ENABLE)) + +#define IS_GFXMMU_CACHE_LOCK_BUFFER(VALUE) (((VALUE) == GFXMMU_CACHE_LOCK_BUFFER0) || \ + ((VALUE) == GFXMMU_CACHE_LOCK_BUFFER1) || \ + ((VALUE) == GFXMMU_CACHE_LOCK_BUFFER2) || \ + ((VALUE) == GFXMMU_CACHE_LOCK_BUFFER3)) + +#define IS_GFXMMU_CACHE_FORCE(VALUE) (((VALUE) == GFXMMU_CACHE_FORCE_DISABLE) || \ + ((VALUE) == GFXMMU_CACHE_FORCE_ENABLE)) + +#define IS_GFXMMU_OUTTER_BUFFERABILITY(VALUE) (((VALUE) == GFXMMU_OUTTER_BUFFERABILITY_DISABLE) || \ + ((VALUE) == GFXMMU_OUTTER_BUFFERABILITY_ENABLE)) + +#define IS_GFXMMU_OUTTER_CACHABILITY(VALUE) (((VALUE) == GFXMMU_OUTTER_CACHABILITY_DISABLE) || \ + ((VALUE) == GFXMMU_OUTTER_CACHABILITY_ENABLE)) + +#define IS_GFXMMU_PREFETCH(VALUE) (((VALUE) == GFXMMU_PREFETCH_DISABLE) || \ + ((VALUE) == GFXMMU_PREFETCH_ENABLE)) + +#if defined (GFXMMU_CR_ACE) +#define IS_GFXMMU_ADDRESSCACHE_LOCK_BUFFER(VALUE) (((VALUE) == GFXMMU_ADDRESSCACHE_LOCK_BUFFER0) || \ + ((VALUE) == GFXMMU_ADDRESSCACHE_LOCK_BUFFER1) || \ + ((VALUE) == GFXMMU_ADDRESSCACHE_LOCK_BUFFER2) || \ + ((VALUE) == GFXMMU_ADDRESSCACHE_LOCK_BUFFER3)) +#endif /* GFXMMU_CR_ACE */ + +#define IS_GFXMMU_INTERRUPTS(VALUE) (((VALUE) & 0x1FU) != 0U) + +#define IS_GFXMMU_LUT_LINE(VALUE) ((VALUE) < 1024U) + +#define IS_GFXMMU_LUT_LINES_NUMBER(VALUE) (((VALUE) > 0U) && ((VALUE) <= 1024U)) + +#define IS_GFXMMU_LUT_LINE_STATUS(VALUE) (((VALUE) == GFXMMU_LUT_LINE_DISABLE) || \ + ((VALUE) == GFXMMU_LUT_LINE_ENABLE)) + +#define IS_GFXMMU_LUT_BLOCK(VALUE) ((VALUE) < 256U) + +#define IS_GFXMMU_LUT_LINE_OFFSET(VALUE) (((VALUE) >= -4080) && ((VALUE) <= 4190208)) + +#define IS_GFXMMU_CACHE_FORCE_ACTION(VALUE) (((VALUE) == GFXMMU_CACHE_FORCE_FLUSH) || \ + ((VALUE) == GFXMMU_CACHE_FORCE_INVALIDATE) || \ + ((VALUE) == (GFXMMU_CACHE_FORCE_FLUSH | GFXMMU_CACHE_FORCE_INVALIDATE))) +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ +#endif /* GFXMMU */ +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_GFXMMU_H */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpio.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpio.c index 3402acdbc8d..ab482de361b 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpio.c @@ -83,7 +83,10 @@ (#) To set/reset the level of a pin configured in output mode use HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). - (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + (#) To set the level of several pins and reset level of several other pins in + same cycle, use HAL_GPIO_WriteMultipleStatePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). (#) During and just after reset, the alternate functions are not active and the GPIO pins are configured in input floating mode (except JTAG @@ -238,7 +241,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) /* Configure Alternate function mapped with the current IO */ tmp = p_gpio->AFR[(pin_position) >> 3U]; tmp &= ~(0x0FUL << (((pin_position) & 0x07U) * 4U)); - tmp |= ((GPIO_AF11_LPGPIO & 0x0FUL) << (((pin_position) & 0x07U) * 4U)); + tmp |= ((GPIO_AF11_LPGPIO1 & 0x0FUL) << (((pin_position) & 0x07U) * 4U)); p_gpio->AFR[(pin_position) >> 3U] = tmp; /* Configure IO Direction mode (Alternate) */ @@ -319,39 +322,39 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) tmp |= (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U))); EXTI->EXTICR[position >> 2U] = tmp; - /* Clear EXTI line configuration */ - tmp = EXTI->IMR1; + /* Clear Rising Falling edge configuration */ + tmp = EXTI->RTSR1; tmp &= ~((uint32_t)iocurrent); - if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + if ((pGPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) { tmp |= iocurrent; } - EXTI->IMR1 = tmp; + EXTI->RTSR1 = tmp; - tmp = EXTI->EMR1; + tmp = EXTI->FTSR1; tmp &= ~((uint32_t)iocurrent); - if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + if ((pGPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) { tmp |= iocurrent; } - EXTI->EMR1 = tmp; + EXTI->FTSR1 = tmp; - /* Clear Rising Falling edge configuration */ - tmp = EXTI->RTSR1; + /* Clear EXTI line configuration */ + tmp = EXTI->EMR1; tmp &= ~((uint32_t)iocurrent); - if ((pGPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) { tmp |= iocurrent; } - EXTI->RTSR1 = tmp; + EXTI->EMR1 = tmp; - tmp = EXTI->FTSR1; + tmp = EXTI->IMR1; tmp &= ~((uint32_t)iocurrent); - if ((pGPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) { tmp |= iocurrent; } - EXTI->FTSR1 = tmp; + EXTI->IMR1 = tmp; } } position++; @@ -468,7 +471,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { GPIO_PinState bitstatus; @@ -518,6 +521,34 @@ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin } } +/** + * @brief Set and clear several pins of a dedicated port in same cycle. + * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + * accesses. + * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding + * peripheral for STM32U5 family + * @param PinReset specifies the port bits to be reset + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero. + * @param PinSet specifies the port bits to be set + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero. + * @note Both PinReset and PinSet combinations shall not get any common bit, else + * assert would be triggered. + * @note At least one of the two parameters used to set or reset shall be different from zero. + * @retval None + */ +void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet) +{ + uint32_t tmp; + + /* Check the parameters */ + /* Make sure at least one parameter is different from zero and that there is no common pin */ + assert_param(IS_GPIO_PIN((uint32_t)PinReset | (uint32_t)PinSet)); + assert_param(IS_GPIO_COMMON_PIN(PinReset, PinSet)); + + tmp = (((uint32_t)PinReset << 16) | PinSet); + GPIOx->BSRR = tmp; +} + /** * @brief Toggle the specified GPIO pin. * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding @@ -875,12 +906,13 @@ void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32 * @param pPinAttributes: pointer to return the pin attributes. * @retval HAL Status. */ -HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t *pPinAttributes) +HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, + uint32_t *pPinAttributes) { uint32_t iocurrent; uint32_t pin_position; uint32_t position = 0U; - GPIO_TypeDef *p_gpio; + const GPIO_TypeDef *p_gpio; /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpio.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpio.h index bf9d576e9a0..da12432b5d9 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpio.h @@ -278,6 +278,9 @@ typedef enum #define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) +#define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \ + (((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u) + #define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ @@ -339,8 +342,9 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); */ /* IO operation functions *****************************************************/ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet); void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_EnableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); @@ -361,7 +365,8 @@ void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin); /* IO attributes management functions *****************************************/ void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes); -HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t *pPinAttributes); +HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, + uint32_t *pPinAttributes); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpio_ex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpio_ex.h index 7b84dc0fb0b..a71871bab6e 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpio_ex.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpio_ex.h @@ -50,7 +50,6 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ - /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants * @{ */ @@ -59,176 +58,236 @@ typedef struct * @{ */ -#if (defined(STM32U575xx) || defined(STM32U585xx)) -/*--------------STM32U575xx/STM32U585xx---------------------------*/ /** * @brief AF 0 selection */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_RTC_50HZ ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ #define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /* LPTIM1 Alternate Function mapping */ #define GPIO_AF0_CSLEEP ((uint8_t)0x00) /* CSLEEP Alternate Function mapping */ #define GPIO_AF0_CSTOP ((uint8_t)0x00) /* CSTOP Alternate Function mapping */ -#define GPIO_AF0_SRDSTOP ((uint8_t)0x00) /* SRDSTOP Alternate Function mapping */ #define GPIO_AF0_CRS ((uint8_t)0x00) /* CRS Alternate Function mapping */ +#define GPIO_AF0_SRDSTOP ((uint8_t)0x00) /* SRDSTOP Alternate Function mapping */ /** * @brief AF 1 selection */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */ -#define GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */ -#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */ +#define GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */ /** * @brief AF 2 selection */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ -#define GPIO_AF2_LPTIM2 ((uint8_t)0x02) /* LPTIM2 Alternate Function mapping */ -#define GPIO_AF2_LPTIM3 ((uint8_t)0x02) /* LPTIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_LPTIM2 ((uint8_t)0x02) /* LPTIM2 Alternate Function mapping */ +#define GPIO_AF2_LPTIM3 ((uint8_t)0x02) /* LPTIM3 Alternate Function mapping */ +#if defined(I2C5) +#define GPIO_AF2_I2C5 ((uint8_t)0x02) /* I2C5 Alternate Function mapping */ +#endif /* I2C5 */ +#if defined(I2C6) +#define GPIO_AF2_I2C6 ((uint8_t)0x02) /* I2C6 Alternate Function mapping */ +#endif /* I2C6 */ +#if defined(GFXTIM) +#define GPIO_AF2_GFXTIM ((uint8_t)0x02) /* GFXTIM Alternate Function mapping */ +#endif /* GFXTIM */ /** * @brief AF 3 selection */ -#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */ -#define GPIO_AF3_OCTOSPI1 ((uint8_t)0x03) /* OCTOSPI1 Alternate Function mapping */ -#define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */ -#define GPIO_AF3_SPI2 ((uint8_t)0x03) /* SPI2 Alternate Function mapping */ -#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF3_TIM8_COMP1 ((uint8_t)0x03) /* TIM8/COMP1 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM8_COMP2 ((uint8_t)0x03) /* TIM8/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM1 ((uint8_t)0x03) /* TIM1 Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */ -#define GPIO_AF3_ADF1 ((uint8_t)0x03) /* ADF1 Alternate Function mapping */ +#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */ +#define GPIO_AF3_OCTOSPI1 ((uint8_t)0x03) /* OCTOSPI1 Alternate Function mapping */ +#define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */ +#define GPIO_AF3_SPI2 ((uint8_t)0x03) /* SPI2 Alternate Function mapping */ +#define GPIO_AF3_TIM1 ((uint8_t)0x03) /* TIM1 Alternate Function mapping */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM8_COMP1 ((uint8_t)0x03) /* TIM8/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF3_TIM8_COMP2 ((uint8_t)0x03) /* TIM8/COMP2 Break in Alternate Function mapping */ +#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */ +#if defined(USART2) +#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */ +#endif /* USART2 */ +#define GPIO_AF3_ADF1 ((uint8_t)0x03) /* ADF1 Alternate Function mapping */ +#if defined(USB_OTG_HS) +#define GPIO_AF3_USB_HS ((uint8_t)0x03) /* USB_HS Alternate Function mapping */ +#endif /* USB_OTG_HS */ /** * @brief AF 4 selection */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ -#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ -#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ -#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */ -#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */ -#define GPIO_AF4_LPTIM3 ((uint8_t)0x04) /* LPTIM3 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ +#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ +#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */ +#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */ +#define GPIO_AF4_LPTIM3 ((uint8_t)0x04) /* LPTIM3 Alternate Function mapping */ +#if defined (I2C5) +#define GPIO_AF4_I2C5 ((uint8_t)0x04) /* I2C5 Alternate Function mapping */ +#endif /* I2C5 */ /** * @brief AF 5 selection */ -#define GPIO_AF5_DFSDM1 ((uint8_t)0x05) /* DFSDM1 Alternate Function mapping */ -#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */ -#define GPIO_AF5_PSSI ((uint8_t)0x05) /* PSSI Alternate Function mapping */ -#define GPIO_AF5_OCTOSPI1 ((uint8_t)0x05) /* OCTOSPI1 Alternate Function mapping */ -#define GPIO_AF5_OCTOSPI2 ((uint8_t)0x05) /* OCTOSPI2 Alternate Function mapping */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ -#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */ -#define GPIO_AF5_DCMI ((uint8_t)0x05) /* DCMI Alternate Function mapping */ -#define GPIO_AF5_MDF1 ((uint8_t)0x05) /* MDF1 Alternate Function mapping */ +#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */ +#define GPIO_AF5_OCTOSPI1 ((uint8_t)0x05) /* OCTOSPI1 Alternate Function mapping */ +#if defined(OCTOSPI2) +#define GPIO_AF5_OCTOSPI2 ((uint8_t)0x05) /* OCTOSPI2 Alternate Function mapping */ +#endif /* OCTOSPI2 */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */ +#define GPIO_AF5_DCMI ((uint8_t)0x05) /* DCMI Alternate Function mapping */ +#define GPIO_AF5_MDF1 ((uint8_t)0x05) /* MDF1 Alternate Function mapping */ +#define GPIO_AF5_PSSI ((uint8_t)0x05) /* PSSI Alternate Function mapping */ +#if defined(GFXTIM) +#define GPIO_AF5_GFXTIM ((uint8_t)0x05) /* GFXTIM Alternate Function mapping */ +#endif /* GFXTIM */ /** * @brief AF 6 selection */ -#define GPIO_AF6_OCTOSPI1 ((uint8_t)0x06) /* OCTOSPI1 Alternate Function mapping */ -#define GPIO_AF6_OCTOSPI2 ((uint8_t)0x06) /* OCTOSPI2 Alternate Function mapping */ -#define GPIO_AF6_MDF1 ((uint8_t)0x06) /* MDF1 Alternate Function mapping */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ +#define GPIO_AF6_OCTOSPI1 ((uint8_t)0x06) /* OCTOSPI1 Alternate Function mapping */ +#if defined(OCTOSPI2) +#define GPIO_AF6_OCTOSPI2 ((uint8_t)0x06) /* OCTOSPI2 Alternate Function mapping */ +#endif /* OCTOPSI2 */ +#define GPIO_AF6_MDF1 ((uint8_t)0x06) /* MDF1 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ +#define GPIO_AF6_I2C3 ((uint8_t)0x06) /* I2C3 Alternate Function mapping */ /** * @brief AF 7 selection */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#if defined(USART2) +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#endif /* USART2 */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#if defined(USART6) +#define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */ +#endif /* USART6 */ +#if defined(LTDC) +#define GPIO_AF7_LTDC ((uint8_t)0x07) /* LTDC Alternate Function mapping */ +#endif /* LTDC */ /** * @brief AF 8 selection */ -#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */ +#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */ +#if defined(LTDC) +#define GPIO_AF8_LTDC ((uint8_t)0x08) /* LTDC Alternate Function mapping */ +#endif /* LTDC */ +#if defined(HSPI1) +#define GPIO_AF8_HSPI1 ((uint8_t)0x08) /* HSPI1 Alternate Function mapping */ +#endif /* HSPI1 */ /** * @brief AF 9 selection */ -#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */ -#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */ +#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */ +#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */ /** * @brief AF 10 selection */ -#define GPIO_AF10_DCMI ((uint8_t)0x0A) /* DCMI Alternate Function mapping */ -#define GPIO_AF10_PSSI ((uint8_t)0x0A) /* PSSI Alternate Function mapping */ -#define GPIO_AF10_USB ((uint8_t)0x0A) /* USB Alternate Function mapping */ -#define GPIO_AF10_OCTOSPI1 ((uint8_t)0x0A) /* OCTOSPI1 Alternate Function mapping */ -#define GPIO_AF10_OCTOSPI2 ((uint8_t)0x0A) /* OCTOSPI2 Alternate Function mapping */ -#define GPIO_AF10_CRS ((uint8_t)0x0A) /* CRS Alternate Function mapping */ +#define GPIO_AF10_DCMI ((uint8_t)0x0A) /* DCMI Alternate Function mapping */ +#define GPIO_AF10_PSSI ((uint8_t)0x0A) /* PSSI Alternate Function mapping */ +#define GPIO_AF10_USB ((uint8_t)0x0A) /* USB Alternate Function mapping */ +#define GPIO_AF10_OCTOSPI1 ((uint8_t)0x0A) /* OCTOSPI1 Alternate Function mapping */ +#if defined(OCTOSPI2) +#define GPIO_AF10_OCTOSPI2 ((uint8_t)0x0A) /* OCTOSPI2 Alternate Function mapping */ +#endif /* OCTOSPI2 */ +#define GPIO_AF10_CRS ((uint8_t)0x0A) /* CRS Alternate Function mapping */ +#if defined(USB_OTG_HS) +#define GPIO_AF10_USB_HS ((uint8_t)0x0A) /* USB_HS Alternate Function mapping */ +#endif /* USB_OTG_HS */ +#if defined(GFXTIM) +#define GPIO_AF10_GFXTIM ((uint8_t)0x0A) /* GFXTIM Alternate Function mapping */ +#endif /* GFXTIM */ /** * @brief AF 11 selection */ -#define GPIO_AF11_UCPD1 ((uint8_t)0x0B) /*!< UCPD1 Alternate Function mapping */ -#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /*!< SDMMC2 Alternate Function mapping */ -#define GPIO_AF11_LPGPIO ((uint8_t)0x0B) /*!< LPGPIO Alternate Function mapping */ -#define GPIO_AF11_FMC_NBL1 ((uint8_t)0x0B) /*!< FMC_NBL1 Alternate Function mapping */ +#if defined(UCPD1) +#define GPIO_AF11_UCPD1 ((uint8_t)0x0B) /* UCPD1 Alternate Function mapping */ +#endif /* UCPD1 */ +#if defined(SDMMC2) +#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */ +#endif /* SDMMC2 */ +#define GPIO_AF11_LPGPIO1 ((uint8_t)0x0B) /* LPGPIO1 Alternate Function mapping */ +#if defined(FMC_BASE) +#define GPIO_AF11_FMC ((uint8_t)0x0B) /* FMC Alternate Function mapping */ +#endif /* FMC_BASE */ +#if defined(DSI) +#define GPIO_AF11_DSI ((uint8_t)0x0B) /* DSI Alternate Function mapping */ +#endif /* DSI */ +#if defined(GFXTIM) +#define GPIO_AF11_GFXTIM ((uint8_t)0x0B) /* GFXTIM Alternate Function mapping */ +#endif /* GFXTIM */ /** * @brief AF 12 selection */ -#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ -#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ -#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ -#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */ -#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF12_TIM8_COMP2 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ -#define GPIO_AF12_SDMMC2 ((uint8_t)0x0C) /* SDMMC2 Alternate Function mapping */ +#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ +#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ +#if defined(FMC_BASE) +#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#endif /* FMC_BASE */ +#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */ +#define GPIO_AF12_TIM8_COMP2 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */ +#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ +#if defined(SDMMC2) +#define GPIO_AF12_SDMMC2 ((uint8_t)0x0C) /* SDMMC2 Alternate Function mapping */ +#endif /* SDMMC2 */ /** * @brief AF 13 selection */ -#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */ -#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */ -#define GPIO_AF13_TIM8_COMP1 ((uint8_t)0x0D) /* TIM8/COMP1 Break in Alternate Function mapping */ -#define GPIO_AF13_LPTIM4 ((uint8_t)0x0D) /* LPTIM4 Alternate Function mapping */ -#define GPIO_AF13_LPTIM2 ((uint8_t)0x0D) /* LPTIM2 Alternate Function mapping */ +#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */ +#if defined(SAI2) +#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */ +#endif /* SAI2 */ +#define GPIO_AF13_LPTIM4 ((uint8_t)0x0D) /* LPTIM4 Alternate Function mapping */ +#define GPIO_AF13_LPTIM2 ((uint8_t)0x0D) /* LPTIM2 Alternate Function mapping */ +#if defined(GFXTIM) +#define GPIO_AF13_GFXTIM ((uint8_t)0x0D) /* GFXTIM Alternate Function mapping */ +#endif /* GFXTIM */ /** * @brief AF 14 selection */ -#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */ -#define GPIO_AF14_LPTIM3 ((uint8_t)0x0E) /* LPTIM3 Alternate Function mapping */ -#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */ -#define GPIO_AF14_TIM8_COMP2 ((uint8_t)0x0E) /* TIM8/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */ -#define GPIO_AF14_TIM15_COMP1 ((uint8_t)0x0E) /* TIM15/COMP1 Alternate Function mapping */ -#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */ -#define GPIO_AF14_TIM16_COMP1 ((uint8_t)0x0E) /* TIM16/COMP1 Alternate Function mapping */ -#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */ -#define GPIO_AF14_TIM17_COMP1 ((uint8_t)0x0E) /* TIM17/COMP1 Alternate Function mapping */ -#define GPIO_AF14_SDMMC2 ((uint8_t)0x0E) /* SDMMC2 Alternate Function mapping */ - +#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */ +#define GPIO_AF14_LPTIM3 ((uint8_t)0x0E) /* LPTIM3 Alternate Function mapping */ +#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */ +#define GPIO_AF14_TIM15_COMP1 ((uint8_t)0x0E) /* TIM15/COMP1 Alternate Function mapping */ +#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */ +#define GPIO_AF14_TIM16_COMP1 ((uint8_t)0x0E) /* TIM16/COMP1 Alternate Function mapping */ +#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */ +#define GPIO_AF14_TIM17_COMP1 ((uint8_t)0x0E) /* TIM17/COMP1 Alternate Function mapping */ /** * @brief AF 15 selection */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) -#endif /* (defined(STM32U575xx) || defined(STM32U585xx)) */ /** * @} */ @@ -245,11 +304,10 @@ typedef struct /** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index * @{ */ -#if (defined(STM32U575xx) || defined(STM32U585xx)) +/* GPIO_Peripheral_Memory_Mapping Peripheral Memory Mapping */ #define GPIO_GET_INDEX(__GPIOx__) (((uint32_t )(__GPIOx__) & (~GPIOA_BASE)) >> 10) -#endif /* (defined(STM32U575xx) || defined(STM32U585xx)) */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpu2d.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpu2d.c new file mode 100644 index 00000000000..632d3415781 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpu2d.c @@ -0,0 +1,750 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_gpu2d.c + * @author MCD Application Team + * @brief GPU2D HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the GPU2D peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Peripheral control is exclusively done by the accompanying middleware library. + + *** Interrupt mode IO operation *** + =================================== + [..] + (#) Configure the GPU2D hardware to perform graphics operation using the Third Party MW + Library APIs. + (#) Submit command List to the hardware. + (#) Wait indefinitely for the completion of submitted Command List by GPU2D hardware. + (#) Use HAL_GPU2D_IRQHandler() called under GPU2D_IRQHandler() interrupt subroutine. + (#) At the end of Command List execution HAL_GPU2D_IRQHandler() function is executed + and user can add his own function by customization of function pointer + (#) CommandListCpltCallback (member of GPU2D handle structure) to notify the upper level + about the completion of Command List execution. + + (#) Callback HAL_GPU2D_CommandListCpltCallback is invoked when the GPU2D hardware executes + the programmed command list (Command List execution completion). + + (++) This callback is called when the compilation defines USE_HAL_GPU2D_REGISTER_CALLBACKS + is set to 0 or not defined. + + (++) This callback should be implemented in the application side. It should notify + the upper level that the programmed command list is completed. + + (#) To control the GPU2D state, use the following function: HAL_GPU2D_GetState(). + + (#) To read the GPU2D error code, use the following function: HAL_GPU2D_GetError(). + + *** GPU2D HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in GPU2D HAL driver : + + (+) __HAL_GPU2D_RESET_HANDLE_STATE: Reset GPU2D handle state. + (+) __HAL_GPU2D_GET_FLAG: Get the GPU2D pending flags. + (+) __HAL_GPU2D_CLEAR_FLAG: Clear the GPU2D pending flags. + (+) __HAL_GPU2D_GET_IT_SOURCE: Check whether the specified GPU2D interrupt is enabled or not. + + *** Callback registration *** + =================================== + [..] + (#) The compilation define USE_HAL_GPU2D_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use function @ref HAL_GPU2D_RegisterCallback() to register a user callback. + + (#) Function @ref HAL_GPU2D_RegisterCallback() allows to register following callbacks: + (+) CommandListCpltCallback : callback for Command List completion. + (+) MspInitCallback : GPU2D MspInit. + (+) MspDeInitCallback : GPU2D MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + (#) Use function @ref HAL_GPU2D_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_GPU2D_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) CommandListCpltCallback : callback for Command List completion. + (+) MspInitCallback : GPU2D MspInit. + (+) MspDeInitCallback : GPU2D MspDeInit. + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_GPU2D_RegisterCallback before calling @ref HAL_GPU2D_DeInit + or @ref HAL_GPU2D_Init function. + + When The compilation define USE_HAL_GPU2D_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + [..] + (@) You can refer to the GPU2D HAL driver header file for more useful macros + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +#ifdef HAL_GPU2D_MODULE_ENABLED +#if defined (GPU2D) + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup GPU2D GPU2D + * @brief GPU2D HAL module driver + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup GPU2D_Private_Macros GPU2D Private Macros + * @{ + */ + +/** @defgroup GPU2D_Write_Read Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPU2D register + * @param __INSTANCE__ GPU2D Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define GPU2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(*(__IO uint32_t *)(__INSTANCE__\ + + __REG__), __VALUE__) + +/** + * @brief Read a value in GPU2D register + * @param __INSTANCE__ GPU2D Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define GPU2D_ReadReg(__INSTANCE__, __REG__) READ_REG(*(__IO uint32_t *)(__INSTANCE__ + __REG__)) +/** + * @} + */ + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPU2D_Exported_Functions GPU2D Exported Functions + * @{ + */ + +/** @defgroup GPU2D_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the GPU2D + (+) De-initialize the GPU2D + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the GPU2D according to the specified + * parameters in the GPU2D_InitTypeDef and create the associated handle. + * @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for the GPU2D. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_GPU2D_Init(GPU2D_HandleTypeDef *hgpu2d) +{ + /* Check the GPU2D handle validity */ + if (hgpu2d == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance)); + + if (hgpu2d->State == HAL_GPU2D_STATE_RESET) + { +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) + /* Reset Callback pointers in HAL_GPU2D_STATE_RESET only */ + hgpu2d->CommandListCpltCallback = HAL_GPU2D_CommandListCpltCallback; + if (hgpu2d->MspInitCallback == NULL) + { + hgpu2d->MspInitCallback = HAL_GPU2D_MspInit; + } + + /* Init the low level hardware */ + hgpu2d->MspInitCallback(hgpu2d); +#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */ + /* Init the low level hardware */ + HAL_GPU2D_MspInit(hgpu2d); +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ + + /* Allocate lock resource and initialize it */ + hgpu2d->Lock = HAL_UNLOCKED; + } + + /* Process locked */ + __HAL_LOCK(hgpu2d); + +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) + /* Reset the CommandListCpltCallback handler */ + hgpu2d->CommandListCpltCallback = NULL; +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ + + /* Update error code */ + hgpu2d->ErrorCode = HAL_GPU2D_ERROR_NONE; + + /* Initialize the GPU2D state*/ + hgpu2d->State = HAL_GPU2D_STATE_READY; + + /* Release Lock */ + __HAL_UNLOCK(hgpu2d); + + return HAL_OK; +} + +/** + * @brief Deinitializes the GPU2D peripheral registers to their default reset + * values. + * @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for the GPU2D. + * @retval None + */ +HAL_StatusTypeDef HAL_GPU2D_DeInit(GPU2D_HandleTypeDef *hgpu2d) +{ + /* Check the GPU2D handle validity */ + if (hgpu2d == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance)); + + /* Process locked */ + __HAL_LOCK(hgpu2d); + + if (hgpu2d->State == HAL_GPU2D_STATE_READY) + { +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) + if (hgpu2d->MspDeInitCallback == NULL) + { + hgpu2d->MspDeInitCallback = HAL_GPU2D_MspDeInit; + } + + /* DeInit the low level hardware */ + hgpu2d->MspDeInitCallback(hgpu2d); +#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */ + /* Carry on with de-initialization of low level hardware */ + HAL_GPU2D_MspDeInit(hgpu2d); +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ + } + +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) + /* Reset the CommandListCpltCallback handler */ + hgpu2d->CommandListCpltCallback = NULL; +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ + + /* Update error code */ + hgpu2d->ErrorCode = HAL_GPU2D_ERROR_NONE; + + /* Reset the GPU2D state*/ + hgpu2d->State = HAL_GPU2D_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hgpu2d); + + return HAL_OK; +} + +/** + * @brief Initializes the GPU2D MSP. + * @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for the GPU2D. + * @retval None + */ +__weak void HAL_GPU2D_MspInit(GPU2D_HandleTypeDef *hgpu2d) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgpu2d); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_GPU2D_MspInit can be implemented in the user file. + */ +} + +/** + * @brief DeInitializes the GPU2D MSP. + * @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for the GPU2D. + * @retval None + */ +__weak void HAL_GPU2D_MspDeInit(GPU2D_HandleTypeDef *hgpu2d) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgpu2d); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_GPU2D_MspDeInit can be implemented in the user file. + */ +} + +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User GPU2D callback + * To be used instead of the weak (surcharged) predefined callback + * @param hgpu2d GPU2D handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_GPU2D_MSPINIT_CB_ID GPU2D MspInit callback ID + * @arg @ref HAL_GPU2D_MSPDEINIT_CB_ID GPU2D MspDeInit callback ID + * @param pCallback pointer to the callback function + * @note Weak predefined callback is defined for HAL_GPU2D_MSPINIT_CB_ID and HAL_GPU2D_MSPDEINIT_CB_ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_GPU2D_RegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID, + pGPU2D_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the GPU2D handle validity */ + if (hgpu2d == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hgpu2d); + + /* Check the pCallback parameter is valid or not */ + if (pCallback == NULL) + { + /* Update the error code */ + hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + } + else + { + if ((hgpu2d->State == HAL_GPU2D_STATE_READY) + || (hgpu2d->State == HAL_GPU2D_STATE_RESET)) + { + switch (CallbackID) + { + case HAL_GPU2D_MSPINIT_CB_ID: + hgpu2d->MspInitCallback = pCallback; + break; + + case HAL_GPU2D_MSPDEINIT_CB_ID: + hgpu2d->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + } + + /* Release lock */ + __HAL_UNLOCK(hgpu2d); + + return status; +} + +/** + * @brief Unregister a GPU2D callback + * GPU2D Callback is redirected to the weak (surcharged) predefined callback + * @param hgpu2d GPU2D handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_GPU2D_MSPINIT_CB_ID GPU2D MspInit callback ID + * @arg @ref HAL_GPU2D_MSPDEINIT_CB_ID GPU2D MspDeInit callback ID + * @note Callback pointers will be set to legacy weak predefined callbacks for HAL_GPU2D_MSPINIT_CB_ID and + * HAL_GPU2D_MSPDEINIT_CB_ID + * @retval status + */ +HAL_StatusTypeDef HAL_GPU2D_UnRegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the GPU2D handle validity */ + if (hgpu2d == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hgpu2d); + + if ((HAL_GPU2D_STATE_READY == hgpu2d->State) + || (HAL_GPU2D_STATE_RESET == hgpu2d->State)) + { + switch (CallbackID) + { + case HAL_GPU2D_MSPINIT_CB_ID: + hgpu2d->MspInitCallback = HAL_GPU2D_MspInit; /* Legacy weak Msp Init */ + break; + + case HAL_GPU2D_MSPDEINIT_CB_ID: + hgpu2d->MspDeInitCallback = HAL_GPU2D_MspDeInit; /* Legacy weak Msp DeInit */ + break; + + default : + /* Update the error code */ + hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release lock */ + __HAL_UNLOCK(hgpu2d); + + return status; +} + +/** + * @brief Register GPU2D Command List Complete Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hgpu2d GPU2D handle + * @param pCallback pointer to the Command List Complete Callback function + * @note Weak predefined callback is defined for Command List Complete + * @retval status + */ +HAL_StatusTypeDef HAL_GPU2D_RegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d, + pGPU2D_CommandListCpltCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the GPU2D handle validity */ + if (hgpu2d == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hgpu2d); + + /* Check the CallbackID is valid or not */ + if (pCallback == NULL) + { + /* Update the error code */ + hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + } + else + { + if ((HAL_GPU2D_STATE_READY == hgpu2d->State) + || (HAL_GPU2D_STATE_RESET == hgpu2d->State)) + { + hgpu2d->CommandListCpltCallback = pCallback; + } + else + { + status = HAL_ERROR; + } + } + + /* Release lock */ + __HAL_UNLOCK(hgpu2d); + + return status; +} + +/** + * @brief Unregister a GPU2D Command List Complete Callback + * GPU2D Command List Complete Callback is redirected to the weak (surcharged) predefined callback + * @param hgpu2d GPU2D handle + * @note Callback pointer will be invalidate (NULL value) + * @retval status + */ +HAL_StatusTypeDef HAL_GPU2D_UnRegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the GPU2D handle validity */ + if (hgpu2d == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hgpu2d); + + if ((hgpu2d->State == HAL_GPU2D_STATE_READY) + || (hgpu2d->State == HAL_GPU2D_STATE_RESET)) + { + hgpu2d->CommandListCpltCallback = NULL; /* Invalidate the Callback pointer */ + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hgpu2d); + + return status; +} +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ + +/** + * @} + */ + + +/** @defgroup GPU2D_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Read GPU2D Register value. + (+) Write a value to GPU2D Register. + (+) handle GPU2D interrupt request. + (+) Command List Complete Transfer Complete callback. + + +@endverbatim + * @{ + */ + +/** + * @brief Read GPU2D Register. Helper function for the higher-level library. + * @param hgpu2d Pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for the GPU2D. + * @param offset The register offset from GPU2D base address to read. + * @retval Register value + */ +uint32_t HAL_GPU2D_ReadRegister(GPU2D_HandleTypeDef *hgpu2d, uint32_t offset) +{ + uint32_t value; + + /* Check the GPU2D handle validity */ + assert_param(hgpu2d != NULL); + + /* Check the parameters */ + assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance)); + assert_param(IS_GPU2D_OFFSET(offset)); + + /* No locking is required since reading a register is an atomic operation + * and doesn't incur a state change in hal_gpu2d. */ + value = GPU2D_ReadReg(hgpu2d->Instance, offset); + + return value; +} + +/** + * @brief Write a value to GPU2D Register. Helper function for the higher-level library. + * @param hgpu2d Pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for the GPU2D. + * @param offset The register offset from GPU2D base address to write. + * @param value The value to be written to provided register. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_GPU2D_WriteRegister(GPU2D_HandleTypeDef *hgpu2d, uint32_t offset, uint32_t value) +{ + /* Check the GPU2D handle validity */ + assert_param(hgpu2d != NULL); + + /* Check the parameters */ + assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance)); + assert_param(IS_GPU2D_OFFSET(offset)); + + /* No locking is required since writing a register is an atomic operation + * and doesn't incur a state change in hal_gpu2d. */ + GPU2D_WriteReg(hgpu2d->Instance, offset, value); + + return HAL_OK; +} + +/** + * @brief Handle GPU2D interrupt request. + * @param hgpu2d Pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for the GPU2D. + * @retval None + */ +void HAL_GPU2D_IRQHandler(GPU2D_HandleTypeDef *hgpu2d) +{ + uint32_t isr_flags = GPU2D_ReadReg(hgpu2d->Instance, GPU2D_ITCTRL); + + /* Command List Complete Interrupt management */ + if ((isr_flags & GPU2D_FLAG_CLC) != 0U) + { + uint32_t last_cl_id; + + /* Clear the completion flag */ + __HAL_GPU2D_CLEAR_FLAG(hgpu2d, GPU2D_FLAG_CLC); + + last_cl_id = GPU2D_ReadReg(hgpu2d->Instance, GPU2D_CLID); + + /* Command List Complete Callback */ +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) + if (hgpu2d->CommandListCpltCallback != NULL) + { + hgpu2d->CommandListCpltCallback(hgpu2d, last_cl_id); + } +#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */ + HAL_GPU2D_CommandListCpltCallback(hgpu2d, last_cl_id); +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ + } +} + +/** + * @brief Handle GPU2D Error interrupt request. + * @param hgpu2d Pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for the GPU2D. + * @retval None + */ +void HAL_GPU2D_ER_IRQHandler(GPU2D_HandleTypeDef *hgpu2d) +{ + HAL_GPU2D_ErrorCallback(hgpu2d); +} + +/** + * @brief Command List Complete callback. + * @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for the GPU2D. + * @param CmdListID Command list ID that got completed. + * @retval None + */ +__weak void HAL_GPU2D_CommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdListID) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgpu2d); + UNUSED(CmdListID); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_GPU2D_CommandListCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Error handler callback. + * @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for the GPU2D. + * @retval None + */ +__weak void HAL_GPU2D_ErrorCallback(GPU2D_HandleTypeDef *hgpu2d) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgpu2d); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_GPU2D_ErrorCallback can be implemented in the user file. + The default implementation stops the execution as an error is considered + fatal and non recoverable. + */ + + for (;;) + { + /* infinite loop */ + } +} + +/** + * @} + */ + + +/** @defgroup GPU2D_Exported_Functions_Group3 Peripheral State and Error functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to: + (+) Get the GPU2D state + (+) Get the GPU2D error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the GPU2D state + * @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for the GPU2D. + * @retval GPU2D state + */ +HAL_GPU2D_StateTypeDef HAL_GPU2D_GetState(GPU2D_HandleTypeDef const *const hgpu2d) +{ + return hgpu2d->State; +} + +/** + * @brief Return the GPU2D error code + * @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for GPU2D. + * @retval GPU2D Error Code + */ +uint32_t HAL_GPU2D_GetError(GPU2D_HandleTypeDef const *const hgpu2d) +{ + return hgpu2d->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* GPU2D */ +#endif /* HAL_GPU2D_MODULE_ENABLED */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpu2d.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpu2d.h new file mode 100644 index 00000000000..a9ec4fade72 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gpu2d.h @@ -0,0 +1,320 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_gpu2d.h + * @author MCD Application Team + * @brief Header file of GPU2D HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_GPU2D_H +#define STM32U5xx_HAL_GPU2D_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +#if defined (GPU2D) + +/** @addtogroup GPU2D GPU2D + * @brief GPU2D HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup GPU2D_Exported_Types GPU2D Exported Types + * @{ + */ +/** + * @brief HAL GPU2D State enumeration definition + */ +typedef enum +{ + HAL_GPU2D_STATE_RESET = 0x00U, /*!< GPU2D not yet initialized or disabled */ + HAL_GPU2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_GPU2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_GPU2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_GPU2D_STATE_ERROR = 0x04U +} HAL_GPU2D_StateTypeDef; + +/** + * @brief GPU2D_TypeDef definition + */ +typedef uint32_t GPU2D_TypeDef; + +/** + * @brief GPU2D handle Structure definition + */ +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) +typedef struct __GPU2D_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ +{ + GPU2D_TypeDef Instance; /*!< GPU2D register base address. */ + + HAL_LockTypeDef Lock; /*!< GPU2D lock. */ + + HAL_GPU2D_StateTypeDef State; /*!< GPU2D transfer state. */ + + uint32_t ErrorCode; /*!< GPU2D error code. */ + +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) + void (* CommandListCpltCallback)(struct __GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdListID); /*!< GPU2D Command Complete Callback */ + + void (* MspInitCallback)(struct __GPU2D_HandleTypeDef *hgpu2d); /*!< GPU2D Msp Init callback */ + + void (* MspDeInitCallback)(struct __GPU2D_HandleTypeDef *hgpu2d); /*!< GPU2D Msp DeInit callback */ +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ +} GPU2D_HandleTypeDef; + +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) +/** + * @brief HAL GPU2D Callback ID enumeration definition + */ +typedef enum +{ + HAL_GPU2D_MSPINIT_CB_ID = 0x00U, /*!< GPU2D MspInit callback ID */ + HAL_GPU2D_MSPDEINIT_CB_ID = 0x01U, /*!< GPU2D MspDeInit callback ID */ +} HAL_GPU2D_CallbackIDTypeDef; + +/** @defgroup HAL_GPU2D_Callback_pointer_definition HAL GPU2D Callback pointer definition + * @brief HAL GPU2D Callback pointer definition + * @{ + */ +typedef void (*pGPU2D_CallbackTypeDef)(GPU2D_HandleTypeDef *hgpu2d); /*!< pointer to an GPU2D Callback function */ +typedef void (*pGPU2D_CommandListCpltCallbackTypeDef)(GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdID); /*!< pointer to an GPU2D Command List Complete Callback function */ +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPU2D_Exported_Constants GPU2D Exported Constants + * @{ + */ + +/** @defgroup GPU2D_Error_Code_definition GPU2D Error Code definition + * @brief GPU2D Error Code definition + * @{ + */ +#define HAL_GPU2D_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_GPU2D_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */ +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) +#define HAL_GPU2D_ERROR_INVALID_CALLBACK (0x00000002U) /*!< Invalid callback error */ +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ +/** + * @} + */ + +/** @defgroup GPU2D_Interrupt_configuration_definition GPU2D Interrupt configuration definition + * @brief GPU2D Interrupt definition + * @{ + */ +#define GPU2D_IT_CLC 0x00000001U /*!< Command List Complete Interrupt */ +/** + * @} + */ + +/** @defgroup GPU2D_Flag_definition GPU2D Flag definition + * @brief GPU2D Flags definition + * @{ + */ +#define GPU2D_FLAG_CLC 0x00000001U /*!< Command List Complete Interrupt Flag */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ +/** @defgroup GPU2D_Exported_Macros GPU2D Exported Macros + * @{ + */ + +/** @brief Reset GPU2D handle state + * @param __HANDLE__: specifies the GPU2D handle. + * @retval None + */ +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) +#define __HAL_GPU2D_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_GPU2D_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + (__HANDLE__)->CommandListCpltCallback = NULL; \ + } while(0) +#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */ +#define __HAL_GPU2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GPU2D_STATE_RESET) +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ + +/* Interrupt & Flag management */ +/** + * @brief Get the GPU2D pending flags. + * @param __HANDLE__: GPU2D handle + * @param __FLAG__: flag to check. + * This parameter can be one of the following values: + * @arg GPU2D_FLAG_CLC: Command List Complete interrupt mask + * @retval The state of FLAG. + */ +#define __HAL_GPU2D_GET_FLAG(__HANDLE__, __FLAG__) (READ_REG(*(__IO uint32_t *)((uint32_t)(__HANDLE__)->Instance\ + + GPU2D_ITCTRL)) & (__FLAG__)) + +/** + * @brief Clear the GPU2D pending flags. + * @param __HANDLE__: GPU2D handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg GPU2D_FLAG_CLC: Command List Complete interrupt mask + * @retval None + */ +#define __HAL_GPU2D_CLEAR_FLAG(__HANDLE__, __FLAG__) do { \ + __IO uint32_t *tmpreg = \ + (__IO uint32_t *)((uint32_t)(__HANDLE__)->Instance\ + + GPU2D_ITCTRL); \ + CLEAR_BIT(*tmpreg, __FLAG__); \ + } while(0U) + +/** + * @brief Check whether the specified GPU2D interrupt source is enabled or not. + * @param __HANDLE__: GPU2D handle + * @param __INTERRUPT__: specifies the GPU2D interrupt source to check. + * This parameter can be one of the following values: + * @arg GPU2D_IT_CLC: Command List Complete interrupt mask + * @retval The state of INTERRUPT source. + */ +#define __HAL_GPU2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_REG(*(__IO uint32_t *)\ + ((uint32_t)(__HANDLE__)->Instance\ + + GPU2D_ITCTRL)) & (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPU2D_Exported_Functions GPU2D Exported Functions + * @{ + */ + +/** @addtogroup GPU2D_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions *******************************/ +HAL_StatusTypeDef HAL_GPU2D_Init(GPU2D_HandleTypeDef *hgpu2d); +HAL_StatusTypeDef HAL_GPU2D_DeInit(GPU2D_HandleTypeDef *hgpu2d); +void HAL_GPU2D_MspInit(GPU2D_HandleTypeDef *hgpu2d); +void HAL_GPU2D_MspDeInit(GPU2D_HandleTypeDef *hgpu2d); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_GPU2D_RegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID, + pGPU2D_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_GPU2D_UnRegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_GPU2D_RegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d, + pGPU2D_CommandListCpltCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_GPU2D_UnRegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d); +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ + +/** + * @} + */ + + +/** @addtogroup GPU2D_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *******************************************************/ +uint32_t HAL_GPU2D_ReadRegister(GPU2D_HandleTypeDef *hgpu2d, uint32_t offset); +HAL_StatusTypeDef HAL_GPU2D_WriteRegister(GPU2D_HandleTypeDef *hgpu2d, uint32_t offset, uint32_t value); +void HAL_GPU2D_IRQHandler(GPU2D_HandleTypeDef *hgpu2d); +void HAL_GPU2D_ER_IRQHandler(GPU2D_HandleTypeDef *hgpu2d); +void HAL_GPU2D_CommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdListID); +void HAL_GPU2D_ErrorCallback(GPU2D_HandleTypeDef *hgpu2d); + +/** + * @} + */ + +/** @addtogroup GPU2D_Exported_Functions_Group3 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State functions ***************************************************/ +HAL_GPU2D_StateTypeDef HAL_GPU2D_GetState(GPU2D_HandleTypeDef const *const hgpu2d); +uint32_t HAL_GPU2D_GetError(GPU2D_HandleTypeDef const *const hgpu2d); + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ + +/** @addtogroup GPU2D_Private_Constants GPU2D Private Constants + * @{ + */ + +#define GPU2D_ITCTRL (0x0F8U) /*!< GPU2D Interrupt Control Register Offset */ +#define GPU2D_CLID (0x148U) /*!< GPU2D Last Command List Identifier Register Offset */ +#define GPU2D_BREAKPOINT (0x080U) /*!< GPU2D Breakpoint Register Offset */ +#define GPU2D_SYS_INTERRUPT (0xff8U) /*!< GPU2D System Interrupt Register Offset */ + +/** @defgroup GPU2D_Offset GPU2D Last Register Offset + * @{ + */ +#define GPU2D_OFFSET 0x1000U /*!< Last GPU2D Register Offset */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPU2D_Private_Macros GPU2D Private Macros + * @{ + */ +#define IS_GPU2D_OFFSET(OFFSET) ((OFFSET) < GPU2D_OFFSET) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPU2D) */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_GPU2D_H */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gtzc.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gtzc.c index 8dd13d3a16e..93e33d8bf3b 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gtzc.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gtzc.c @@ -123,9 +123,50 @@ #define TZSC_MPCWM3_MEM_SIZE 0x10000000U /* 256MB max size */ #define TZSC_MPCWM4_MEM_SIZE 0x00000800U /* 2KB max size */ #define TZSC_MPCWM5_MEM_SIZE 0x10000000U /* 256MB max size */ +#if defined (HSPI1) +#define TZSC_MPCWM6_MEM_SIZE 0x10000000U /* 256MB max size */ +#endif /* HSPI1 */ /* Definitions for GTZC TZSC & TZIC ALL register values */ /* TZSC1 / TZIC1 instances */ +#if defined(STM32U599xx) || defined(STM32U595xx) || defined(STM32U5A9xx) || defined (STM32U5A5xx) +#define TZSC1_SECCFGR1_ALL (0x00EFFFFFUL) +#define TZSC1_SECCFGR2_ALL (0x000007FFUL) +#define TZSC1_SECCFGR3_ALL (0x0FFFFFFFUL) + +#define TZSC1_PRIVCFGR1_ALL (0x00EFFFFFUL) +#define TZSC1_PRIVCFGR2_ALL (0x000007FFUL) +#define TZSC1_PRIVCFGR3_ALL (0x0FFFFFFFUL) + +#define TZIC1_IER1_ALL (0x00EFFFFFUL) +#define TZIC1_IER2_ALL (0x000007FFUL) +#define TZIC1_IER3_ALL (0x0FFFFFFFUL) +#define TZIC1_IER4_ALL (0xFF1FC01FUL) + +#define TZIC1_FCR1_ALL (0x00EFFFFFUL) +#define TZIC1_FCR2_ALL (0x000007FFUL) +#define TZIC1_FCR3_ALL (0x0FFFFFFFUL) +#define TZIC1_FCR4_ALL (0xFF1FC01FUL) + +#elif defined(STM32U5F9xx) || defined(STM32U5G9xx) +#define TZSC1_SECCFGR1_ALL (0x00EFFFFFUL) +#define TZSC1_SECCFGR2_ALL (0x00000FFFUL) +#define TZSC1_SECCFGR3_ALL (0x1FFFFFFFUL) + +#define TZSC1_PRIVCFGR1_ALL (0x00EFFFFFUL) +#define TZSC1_PRIVCFGR2_ALL (0x00000FFFUL) +#define TZSC1_PRIVCFGR3_ALL (0x1FFFFFFFUL) + +#define TZIC1_IER1_ALL (0x00EFFFFFUL) +#define TZIC1_IER2_ALL (0x00000FFFUL) +#define TZIC1_IER3_ALL (0x1FFFFFFFUL) +#define TZIC1_IER4_ALL (0xFFDFC01FUL) + +#define TZIC1_FCR1_ALL (0x00EFFFFFUL) +#define TZIC1_FCR2_ALL (0x00000FFFUL) +#define TZIC1_FCR3_ALL (0x1FFFFFFFUL) +#define TZIC1_FCR4_ALL (0xFFDFC01FUL) +#else #define TZSC1_SECCFGR1_ALL (0x001FFFFFUL) #define TZSC1_SECCFGR2_ALL (0x000001FFUL) #define TZSC1_SECCFGR3_ALL (0x007FFFFFUL) @@ -143,6 +184,7 @@ #define TZIC1_FCR2_ALL (0x000001FFUL) #define TZIC1_FCR3_ALL (0x007FFFFFUL) #define TZIC1_FCR4_ALL (0x3F0FC01FUL) +#endif /* STM32U599xx || STM32U595xx || STM32U5A9xx || STM32U5A5xx */ /* TZSC2 / TZIC2 instances */ #define TZSC2_SECCFGR1_ALL (0x00001BFFUL) @@ -526,9 +568,8 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, * The structure description is available in @ref GTZC_Exported_Types. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes( - uint32_t MemBaseAddress, - MPCWM_ConfigTypeDef *pMPCWM_Desc) +HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress, + const MPCWM_ConfigTypeDef *pMPCWM_Desc) { uint32_t register_address; uint32_t reg_value; @@ -538,11 +579,15 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes( GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1; /* check entry parameters */ - if ((pMPCWM_Desc->AreaId > GTZC_TZSC_MPCWM_ID2) - || (((MemBaseAddress == FMC_BANK3) || (MemBaseAddress == BKPSRAM_BASE)) - && (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2)) - || ((pMPCWM_Desc->Offset % granularity) != 0U) - || ((pMPCWM_Desc->Length % granularity) != 0U)) + if ((pMPCWM_Desc->AreaId > GTZC_TZSC_MPCWM_ID2) || +#if defined (FMC_BANK3) + (((MemBaseAddress == BKPSRAM_BASE) || (MemBaseAddress == FMC_BANK3)) && +#else + ((MemBaseAddress == BKPSRAM_BASE) && +#endif /* FMC_BANK3 */ + (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2)) || + ((pMPCWM_Desc->Offset % granularity) != 0U) || + ((pMPCWM_Desc->Length % granularity) != 0U)) { return HAL_ERROR; } @@ -564,6 +609,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes( register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR); } break; +#if defined (FMC_BANK1) case FMC_BANK1: size = TZSC_MPCWM1_MEM_SIZE; if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1) @@ -578,6 +624,8 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes( register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR); } break; +#endif /* FMC_BANK1 */ +#if defined (FMC_BANK3) case FMC_BANK3: /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1 * (Parameter already checked) @@ -585,6 +633,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes( size = TZSC_MPCWM3_MEM_SIZE; register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM3AR); break; +#endif /* FMC_BANK3 */ case BKPSRAM_BASE: /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1 * (Parameter already checked) @@ -592,6 +641,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes( size = TZSC_MPCWM4_MEM_SIZE; register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM4AR); break; +#if defined (OCTOSPI2_BASE) case OCTOSPI2_BASE: size = TZSC_MPCWM5_MEM_SIZE; if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1) @@ -606,15 +656,30 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes( register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5BR); } break; +#endif /* OCTOSPI2_BASE */ +#if defined (HSPI1) + case HSPI1_BASE: + size = TZSC_MPCWM6_MEM_SIZE; + if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1) + { + register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM6AR); + } + else + { + /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2 + * (Parameter already checked) + */ + register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM6BR); + } + break; +#endif /* HSPI1 */ default: return HAL_ERROR; break; } - if ((pMPCWM_Desc->Offset > size) - || ((pMPCWM_Desc->Offset - + pMPCWM_Desc->Length) - > size)) + if ((pMPCWM_Desc->Offset > size) || + ((pMPCWM_Desc->Offset + pMPCWM_Desc->Length) > size)) { return HAL_ERROR; } @@ -642,12 +707,13 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes( * @brief Get a TZSC-MPCWM area configuration. * @param MemBaseAddress WM identifier. * @param pMPCWM_Desc pointer to a TZSC-MPCWM descriptor. + * When the WaterMark memory supports two sub-regions A and B. pMPCWM_Desc argument must point to an array of + * two MPCWM_ConfigTypeDef structures. * The structure description is available in @ref GTZC_Exported_Types. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes( - uint32_t MemBaseAddress, - MPCWM_ConfigTypeDef *pMPCWM_Desc) +HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, + MPCWM_ConfigTypeDef *pMPCWM_Desc) { uint32_t register_address; uint32_t reg_value; @@ -660,18 +726,29 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes( case OCTOSPI1_BASE: register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1AR); break; +#if defined (FMC_BANK1) case FMC_BANK1: register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2AR); break; +#endif /* FMC_BANK1 */ +#if defined (FMC_BANK3) case FMC_BANK3: register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM3AR); break; +#endif /* FMC_BANK3 */ case BKPSRAM_BASE: register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM4AR); break; +#if defined (OCTOSPI2_BASE) case OCTOSPI2_BASE: register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5AR); break; +#endif /* OCTOSPI2_BASE */ +#if defined (HSPI1) + case HSPI1_BASE: + register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM6AR); + break; +#endif /* HSPI1 */ default: return HAL_ERROR; break; @@ -692,10 +769,17 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes( pMPCWM_Desc[0].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK; pMPCWM_Desc[0].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN; - if ((MemBaseAddress != FMC_BANK3) && (MemBaseAddress != BKPSRAM_BASE)) - { - /* Here MemBaseAddress = OCTOSPI1_BASE, OCTOSPI2_BASE - * or FMC_BANK1 (already checked) + if ((MemBaseAddress != BKPSRAM_BASE) +#if defined (FMC_BANK3) + && (MemBaseAddress != FMC_BANK3) +#endif /* FMC_BANK3 */ + ) + { + /* Here MemBaseAddress = OCTOSPI1_BASE, and the following memories if applicable : + * - OCTOSPI2_BASE + * - FMC_BANK1 + * - FMC_BANK3 + * - HSPI1 * Now take care of the second area, present on these sub-blocks */ switch (MemBaseAddress) @@ -703,12 +787,21 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes( case OCTOSPI1_BASE: register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR); break; +#if defined (FMC_BANK1) case FMC_BANK1: register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR); break; +#endif /* FMC_BANK1 */ +#if defined (OCTOSPI2_BASE) case OCTOSPI2_BASE: register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5BR); break; +#endif /* OCTOSPI2_BASE */ +#if defined (HSPI1) + case HSPI1_BASE: + register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM6BR); + break; +#endif /* HSPI1 */ default: return HAL_ERROR; break; @@ -724,8 +817,8 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes( /* read configuration register and update the descriptor for second area*/ reg_value = READ_REG(*(__IO uint32_t *)(register_address - 4U)); - pMPCWM_Desc[1].Attribute = reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \ - GTZC_TZSC_MPCWM_CFGR_SEC); + pMPCWM_Desc[1].Attribute = (reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \ + GTZC_TZSC_MPCWM_CFGR_SEC)) >> GTZC_TZSC_MPCWM_CFGR_SEC_Pos; pMPCWM_Desc[1].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK; pMPCWM_Desc[1].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN; } @@ -767,7 +860,7 @@ void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance) * @param TZSC_Instance TZSC sub-block instance. * @retval Lock State (GTZC_TZSC_LOCK_OFF or GTZC_TZSC_LOCK_ON) */ -uint32_t HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef *TZSC_Instance) +uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance) { return READ_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk); } @@ -799,10 +892,9 @@ uint32_t HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef *TZSC_Instance) * @retval HAL status. */ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, - MPCBB_ConfigTypeDef *pMPCBB_desc) + const MPCBB_ConfigTypeDef *pMPCBB_desc) { GTZC_MPCBB_TypeDef *mpcbb_ptr; - uint32_t reg_value; uint32_t mem_size; uint32_t size_in_superblocks; uint32_t i; @@ -810,24 +902,25 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, /* check entry parameters */ if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)) +#if defined (SRAM3_BASE) && !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) - && !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))) - || ((pMPCBB_desc->SecureRWIllegalMode - != GTZC_MPCBB_SRWILADIS_ENABLE) - && (pMPCBB_desc->SecureRWIllegalMode - != GTZC_MPCBB_SRWILADIS_DISABLE)) - || ((pMPCBB_desc->InvertSecureState - != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED) - && (pMPCBB_desc->InvertSecureState - != GTZC_MPCBB_INVSECSTATE_INVERTED))) +#endif /* SRAM3_BASE */ + && !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) +#if defined (SRAM5_BASE) + && !(IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + && !(IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) +#endif /* SRAM6_BASE */ + ) + || ((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE) + && (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE)) + || ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED) + && (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED))) { return HAL_ERROR; } - /* write InvertSecureState and SecureRWIllegalMode properties */ - /* assume their Position/Mask is identical for all sub-blocks */ - reg_value = pMPCBB_desc->InvertSecureState; - reg_value |= pMPCBB_desc->SecureRWIllegalMode; if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) { mpcbb_ptr = GTZC_MPCBB1; @@ -838,52 +931,80 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, mpcbb_ptr = GTZC_MPCBB2; mem_size = GTZC_MEM_SIZE(SRAM2); } +#if defined (SRAM3_BASE) else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) { mpcbb_ptr = GTZC_MPCBB3; mem_size = GTZC_MEM_SIZE(SRAM3); } - else +#endif /* SRAM3_BASE */ + else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) { - /* Here MemBaseAddress is inside SRAM4 (parameter already checked) */ mpcbb_ptr = GTZC_MPCBB4; mem_size = GTZC_MEM_SIZE(SRAM4); } +#if defined (SRAM5_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB5; + mem_size = GTZC_MEM_SIZE(SRAM5); + } +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB6; + mem_size = GTZC_MEM_SIZE(SRAM6); + } +#endif /* SRAM6_BASE */ + else + { + return HAL_ERROR; + } /* translate mem_size in number of super-blocks */ size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE); + /* write PRIVCFGR register information */ + for (i = 0U; i < size_in_superblocks; i++) + { + WRITE_REG(mpcbb_ptr->PRIVCFGR[i], + pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i]); + } + #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) uint32_t size_mask; + uint32_t reg_value; - /* write configuration and lock register information */ - MODIFY_REG(mpcbb_ptr->CR, - GTZC_MPCBB_CR_INVSECSTATE_Msk | GTZC_MPCBB_CR_SRWILADIS_Msk, reg_value); - if (size_in_superblocks == 32U) + /* write SECCFGR register information */ + for (i = 0U; i < size_in_superblocks; i++) + { + WRITE_REG(mpcbb_ptr->SECCFGR[i], + pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i]); + } + +#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk) + if (size_in_superblocks >= 32U) { size_mask = 0xFFFFFFFFU; + MODIFY_REG(mpcbb_ptr->CFGLOCKR2, 0x000FFFFFUL, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[1]); } else +#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */ { - size_mask = (1UL << size_in_superblocks) - 1U; + size_mask = (1UL << (size_in_superblocks & 0x1FU)) - 1U; } /* limitation: code not portable with memory > 512K */ MODIFY_REG(mpcbb_ptr->CFGLOCKR1, size_mask, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0]); - /* write SECCFGR register information */ - for (i = 0U; i < size_in_superblocks; i++) - { - WRITE_REG(mpcbb_ptr->SECCFGR[i], - pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i]); - } -#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + /* write InvertSecureState and SecureRWIllegalMode properties */ + reg_value = pMPCBB_desc->InvertSecureState; + reg_value |= pMPCBB_desc->SecureRWIllegalMode; - /* write PRIVCFGR register information */ - for (i = 0U; i < size_in_superblocks; i++) - { - WRITE_REG(mpcbb_ptr->PRIVCFGR[i], - pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i]); - } + /* write configuration and lock register information */ + MODIFY_REG(mpcbb_ptr->CR, + GTZC_MPCBB_CR_INVSECSTATE_Msk | GTZC_MPCBB_CR_SRWILADIS_Msk, reg_value); +#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ return HAL_OK; } @@ -906,8 +1027,17 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, /* check entry parameters */ if (!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)) +#if defined (SRAM3_BASE) && !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) - && !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))) +#endif /* SRAM3_BASE */ + && !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) +#if defined (SRAM5_BASE) + && !(IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + && !(IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) +#endif /* SRAM6_BASE */ + ) { return HAL_ERROR; } @@ -924,16 +1054,36 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, mpcbb_ptr = GTZC_MPCBB2; mem_size = GTZC_MEM_SIZE(SRAM2); } +#if defined (SRAM3_BASE) else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) { mpcbb_ptr = GTZC_MPCBB3; mem_size = GTZC_MEM_SIZE(SRAM3); } - else +#endif /* SRAM3_BASE */ + else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) { mpcbb_ptr = GTZC_MPCBB4; mem_size = GTZC_MEM_SIZE(SRAM4); } +#if defined (SRAM5_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB5; + mem_size = GTZC_MEM_SIZE(SRAM5); + } +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB6; + mem_size = GTZC_MEM_SIZE(SRAM6); + } +#endif /* SRAM6_BASE */ + else + { + return HAL_ERROR; + } /* translate mem_size in number of super-blocks */ size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE); @@ -946,9 +1096,13 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, reg_value = READ_REG(mpcbb_ptr->CR); pMPCBB_desc->InvertSecureState = (reg_value & GTZC_MPCBB_CR_INVSECSTATE_Msk); pMPCBB_desc->SecureRWIllegalMode = (reg_value & GTZC_MPCBB_CR_SRWILADIS_Msk); - if (size_in_superblocks == 32U) + if (size_in_superblocks >= 32U) { size_mask = 0xFFFFFFFFU; +#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk) + pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[1] = READ_REG(mpcbb_ptr->CFGLOCKR2) + & 0x000FFFFFUL; +#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */ } else { @@ -977,13 +1131,13 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, * @param NbBlocks Number of blocks to configure * (Block size is 512 Bytes). * @param pMemAttributes pointer to an array (containing "NbBlocks" elements), - * with each element must be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC, - * and GTZC_MCPBB_BLOCK_NPRIV or GTZC_MCPBB_BLOCK_PRIV. + * with each element must be GTZC_MPCBB_BLOCK_NSEC or GTZC_MPCBB_BLOCK_SEC, + * and GTZC_MPCBB_BLOCK_NPRIV or GTZC_MPCBB_BLOCK_PRIV. * @retval HAL status. */ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, uint32_t NbBlocks, - uint32_t *pMemAttributes) + const uint32_t *pMemAttributes) { GTZC_MPCBB_TypeDef *mpcbb_ptr; uint32_t base_address; @@ -1026,6 +1180,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, mpcbb_ptr = GTZC_MPCBB2; base_address = SRAM2_BASE_S; } +#if defined (SRAM3_BASE) else if (((IS_ADDRESS_IN_NS(SRAM3, MemAddress)) && (IS_ADDRESS_IN_NS(SRAM3, end_address))) != 0U) { @@ -1038,6 +1193,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, mpcbb_ptr = GTZC_MPCBB3; base_address = SRAM3_BASE_S; } +#endif /* SRAM3_BASE */ else if (((IS_ADDRESS_IN_NS(SRAM4, MemAddress)) && (IS_ADDRESS_IN_NS(SRAM4, end_address))) != 0U) { @@ -1050,6 +1206,34 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, mpcbb_ptr = GTZC_MPCBB4; base_address = SRAM4_BASE_S; } +#if defined (SRAM5_BASE) + else if (((IS_ADDRESS_IN_NS(SRAM5, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM5, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB5; + base_address = SRAM5_BASE_NS; + } + else if (((IS_ADDRESS_IN_S(SRAM5, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM5, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB5; + base_address = SRAM5_BASE_S; + } +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + else if (((IS_ADDRESS_IN_NS(SRAM6, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM6, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB6; + base_address = SRAM6_BASE_NS; + } + else if (((IS_ADDRESS_IN_S(SRAM6, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM6, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB6; + base_address = SRAM6_BASE_S; + } +#endif /* SRAM6_BASE */ else { return HAL_ERROR; @@ -1067,13 +1251,13 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /* secure configuration */ - if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_SEC) == GTZC_MCPBB_BLOCK_SEC) + if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_SEC) == GTZC_MPCBB_BLOCK_SEC) { SET_BIT(mpcbb_ptr->SECCFGR[offset_reg_start], 1UL << (offset_bit_start % 32U)); do_attr_change = 1U; } - else if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_NSEC) == GTZC_MCPBB_BLOCK_NSEC) + else if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_NSEC) == GTZC_MPCBB_BLOCK_NSEC) { CLEAR_BIT(mpcbb_ptr->SECCFGR[offset_reg_start], 1UL << (offset_bit_start % 32U)); @@ -1086,12 +1270,12 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* privilege configuration */ - if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_PRIV) == GTZC_MCPBB_BLOCK_PRIV) + if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_PRIV) == GTZC_MPCBB_BLOCK_PRIV) { SET_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start], 1UL << (offset_bit_start % 32U)); } - else if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_NPRIV) == GTZC_MCPBB_BLOCK_NPRIV) + else if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_NPRIV) == GTZC_MPCBB_BLOCK_NPRIV) { CLEAR_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start], 1UL << (offset_bit_start % 32U)); @@ -1129,8 +1313,8 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, * (must be 512 Bytes aligned). * @param NbBlocks Number of blocks to get configuration. * @param pMemAttributes pointer to an array (containing "NbBlocks" elements), - * with each element will be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC, - * and GTZC_MCPBB_BLOCK_NPRIV or GTZC_MCPBB_BLOCK_PRIV. + * with each element will be GTZC_MPCBB_BLOCK_NSEC or GTZC_MPCBB_BLOCK_SEC, + * and GTZC_MPCBB_BLOCK_NPRIV or GTZC_MPCBB_BLOCK_PRIV. * @retval HAL status. */ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, @@ -1177,6 +1361,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, mpcbb_ptr = GTZC_MPCBB2_S; base_address = SRAM2_BASE_S; } +#if defined (SRAM3_BASE) else if ((IS_ADDRESS_IN_NS(SRAM3, MemAddress)) && (IS_ADDRESS_IN_NS(SRAM3, end_address))) { @@ -1189,6 +1374,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, mpcbb_ptr = GTZC_MPCBB3_S; base_address = SRAM3_BASE_S; } +#endif /* SRAM3_BASE */ else if ((IS_ADDRESS_IN_NS(SRAM4, MemAddress)) && (IS_ADDRESS_IN_NS(SRAM4, end_address))) { @@ -1201,6 +1387,34 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, mpcbb_ptr = GTZC_MPCBB4_S; base_address = SRAM4_BASE_S; } +#if defined (SRAM5_BASE) + else if ((IS_ADDRESS_IN_NS(SRAM5, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM5, end_address))) + { + mpcbb_ptr = GTZC_MPCBB5_NS; + base_address = SRAM5_BASE_NS; + } + else if ((IS_ADDRESS_IN_S(SRAM5, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM5, end_address))) + { + mpcbb_ptr = GTZC_MPCBB5_S; + base_address = SRAM5_BASE_S; + } +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + else if ((IS_ADDRESS_IN_NS(SRAM6, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM6, end_address))) + { + mpcbb_ptr = GTZC_MPCBB6_NS; + base_address = SRAM6_BASE_NS; + } + else if ((IS_ADDRESS_IN_S(SRAM6, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM6, end_address))) + { + mpcbb_ptr = GTZC_MPCBB6_S; + base_address = SRAM6_BASE_S; + } +#endif /* SRAM6_BASE */ else { return HAL_ERROR; @@ -1216,9 +1430,9 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, pMemAttributes[i] = (READ_BIT(mpcbb_ptr->SECCFGR[offset_reg_start], 1UL << (offset_bit_start % 32U)) >> (offset_bit_start % 32U)) | GTZC_ATTR_SEC_MASK; - pMemAttributes[i] |= (READ_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start], - 1UL << (offset_bit_start % 32U)) - >> (offset_bit_start % 32U)) | GTZC_ATTR_PRIV_MASK; + pMemAttributes[i] |= ((READ_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start], + 1UL << (offset_bit_start % 32U)) + >> (offset_bit_start % 32U)) << 1U) | GTZC_ATTR_PRIV_MASK; offset_bit_start++; if (offset_bit_start == 32U) @@ -1240,19 +1454,19 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements), * with for each element: * value 0 super-block is unlocked, value 1 super-block is locked - * (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and - * GTZC_MCPBB_SUPERBLOCK_LOCKED values). + * (corresponds to GTZC_MPCBB_SUPERBLOCK_UNLOCKED and + * GTZC_MPCBB_SUPERBLOCK_LOCKED values). * @retval HAL status. */ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, uint32_t NbSuperBlocks, - uint32_t *pLockAttributes) + const uint32_t *pLockAttributes) { __IO uint32_t *reg_mpcbb; uint32_t base_address; uint32_t superblock_start; uint32_t offset_bit_start; - uint32_t i; + uint32_t i = 0U; /* firstly check that MemAddress is well 16KBytes aligned */ if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U) @@ -1267,7 +1481,6 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, - 1U)))) { base_address = GTZC_BASE_ADDRESS(SRAM1); - /* limitation: code not portable with memory > 512K */ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->CFGLOCKR1; } else if ((IS_ADDRESS_IN(SRAM2, MemAddress)) @@ -1276,28 +1489,46 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, - 1U)))) { base_address = GTZC_BASE_ADDRESS(SRAM2); - /* limitation: code not portable with memory > 512K */ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCKR1; } +#if defined (SRAM3_BASE) else if ((IS_ADDRESS_IN(SRAM3, MemAddress)) && (IS_ADDRESS_IN(SRAM3, (MemAddress + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) - 1U)))) { base_address = GTZC_BASE_ADDRESS(SRAM3); - /* limitation: code not portable with memory > 512K */ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB3_S->CFGLOCKR1; } - +#endif /* SRAM3_BASE */ else if ((IS_ADDRESS_IN(SRAM4, MemAddress)) && (IS_ADDRESS_IN(SRAM4, (MemAddress + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) - 1U)))) { base_address = GTZC_BASE_ADDRESS(SRAM4); - /* limitation: code not portable with memory > 512K */ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB4_S->CFGLOCKR1; } +#if defined (SRAM5_BASE) + else if ((IS_ADDRESS_IN(SRAM5, MemAddress)) + && (IS_ADDRESS_IN(SRAM5, (MemAddress + + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM5); + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB5_S->CFGLOCKR1; + } +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + else if ((IS_ADDRESS_IN(SRAM6, MemAddress)) + && (IS_ADDRESS_IN(SRAM6, (MemAddress + + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM6); + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB6_S->CFGLOCKR1; + } +#endif /* SRAM6_BASE */ else { return HAL_ERROR; @@ -1307,13 +1538,14 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE; offset_bit_start = superblock_start % 32U; - for (i = 0U; i < NbSuperBlocks; i++) + /* First 32 super-blocks */ + while ((i < NbSuperBlocks) && (i < 32U) && (superblock_start < 32U)) { - if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_LOCKED) + if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_LOCKED) { SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U)); } - else if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_UNLOCKED) + else if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_UNLOCKED) { CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U)); } @@ -1323,8 +1555,36 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, } offset_bit_start++; + i++; } +#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk) + if ((NbSuperBlocks > 32U) || (superblock_start >= 32U)) + { + /* Point to second configuration lock register */ + reg_mpcbb++; + + /* Remaining super-blocks */ + for (; i < NbSuperBlocks; i++) + { + if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_LOCKED) + { + SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U)); + } + else if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_UNLOCKED) + { + CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U)); + } + else + { + break; + } + + offset_bit_start++; + } + } +#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */ + /* an unexpected value in pLockAttributes array leads to an error status */ if (i != NbSuperBlocks) { @@ -1342,19 +1602,19 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements), * with for each element: * value 0 super-block is unlocked, value 1 super-block is locked - * (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and - * GTZC_MCPBB_SUPERBLOCK_LOCKED values). + * (corresponds to GTZC_MPCBB_SUPERBLOCK_UNLOCKED and + * GTZC_MPCBB_SUPERBLOCK_LOCKED values). * @retval HAL status. */ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, uint32_t NbSuperBlocks, uint32_t *pLockAttributes) { - uint32_t reg_mpcbb; + __IO uint32_t *reg_mpcbb; uint32_t base_address; uint32_t superblock_start; uint32_t offset_bit_start; - uint32_t i; + uint32_t i = 0U; /* firstly check that MemAddress is well 16KBytes aligned */ if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U) @@ -1369,8 +1629,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, - 1U)))) { base_address = GTZC_BASE_ADDRESS(SRAM1); - /* limitation: code not portable with memory > 512K */ - reg_mpcbb = GTZC_MPCBB1_S->CFGLOCKR1; + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->CFGLOCKR1; } else if ((IS_ADDRESS_IN(SRAM2, MemAddress)) && (IS_ADDRESS_IN(SRAM2, (MemAddress @@ -1379,9 +1638,9 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, - 1U)))) { base_address = GTZC_BASE_ADDRESS(SRAM2); - /* limitation: code not portable with memory > 512K */ - reg_mpcbb = GTZC_MPCBB2_S->CFGLOCKR1; + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCKR1; } +#if defined (SRAM3_BASE) else if ((IS_ADDRESS_IN(SRAM3, MemAddress)) && (IS_ADDRESS_IN(SRAM3, (MemAddress + (NbSuperBlocks @@ -1389,9 +1648,9 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, - 1U)))) { base_address = GTZC_BASE_ADDRESS(SRAM3); - /* limitation: code not portable with memory > 512K */ - reg_mpcbb = GTZC_MPCBB3_S->CFGLOCKR1; + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB3_S->CFGLOCKR1; } +#endif /* SRAM3_BASE */ else if ((IS_ADDRESS_IN(SRAM4, MemAddress)) && (IS_ADDRESS_IN(SRAM4, (MemAddress + (NbSuperBlocks @@ -1399,24 +1658,63 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, - 1U)))) { base_address = GTZC_BASE_ADDRESS(SRAM4); - /* limitation: code not portable with memory > 512K */ - reg_mpcbb = GTZC_MPCBB4_S->CFGLOCKR1; + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB4_S->CFGLOCKR1; } +#if defined (SRAM5_BASE) + else if ((IS_ADDRESS_IN(SRAM5, MemAddress)) + && (IS_ADDRESS_IN(SRAM5, (MemAddress + + (NbSuperBlocks + * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM5); + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB5_S->CFGLOCKR1; + } +#endif /* SRAM5_BASE */ + +#if defined (SRAM6_BASE) + else if ((IS_ADDRESS_IN(SRAM6, MemAddress)) + && (IS_ADDRESS_IN(SRAM6, (MemAddress + + (NbSuperBlocks + * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM6); + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB6_S->CFGLOCKR1; + } +#endif /* SRAM6_BASE */ else { return HAL_ERROR; } - /* get start coordinates of the configuration */ + /* Get start coordinates of the configuration */ superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE; offset_bit_start = superblock_start % 32U; - for (i = 0U; i < NbSuperBlocks; i++) + while ((i < NbSuperBlocks) && (i < 32U) && (superblock_start < 32U)) { - pLockAttributes[i] = (reg_mpcbb & (1UL << (offset_bit_start % 32U))) + pLockAttributes[i] = ((*reg_mpcbb) & (1UL << (offset_bit_start % 32U))) >> (offset_bit_start % 32U); offset_bit_start++; + i++; + } + +#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk) + if ((NbSuperBlocks > 32U) || (superblock_start >= 32U)) + { + /* Point to second configuration lock register */ + reg_mpcbb++; + + /* Remaining super-blocks */ + for (; i < NbSuperBlocks; i++) + { + pLockAttributes[i] = ((*reg_mpcbb) & (1UL << (offset_bit_start % 32U))) + >> (offset_bit_start % 32U); + offset_bit_start++; + } } +#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */ return HAL_OK; } @@ -1438,14 +1736,28 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress) { SET_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } +#if defined (SRAM3_BASE) else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) { SET_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } +#endif /* SRAM3_BASE*/ else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) { SET_BIT(GTZC_MPCBB4_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } +#if defined (SRAM5_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) + { + SET_BIT(GTZC_MPCBB5_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) + { + SET_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } +#endif /* SRAM6_BASE */ else { return HAL_ERROR; @@ -1457,7 +1769,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress) /** * @brief Get MPCBB configuration lock state on the SRAM base address passed as parameter. * @param MemBaseAddress MPCBB identifier. - * @param pLockState pointer to Lock State (GTZC_MCPBB_LOCK_OFF or GTZC_MCPBB_LOCK_ON). + * @param pLockState pointer to Lock State (GTZC_MPCBB_LOCK_OFF or GTZC_MPCBB_LOCK_ON). * @retval HAL status. */ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress, @@ -1472,14 +1784,28 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress, { *pLockState = READ_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } +#if defined (SRAM3_BASE) else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) { *pLockState = READ_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } +#endif /* SRAM3_BASE */ else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) { *pLockState = READ_BIT(GTZC_MPCBB4_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } +#if defined (SRAM5_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) + { + *pLockState = READ_BIT(GTZC_MPCBB5_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } +#endif /* SRAM5_BASE */ +#if defined (SRAM6_BASE) + else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) + { + *pLockState = READ_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } +#endif /* SRAM6_BASE */ else { return HAL_ERROR; @@ -1629,7 +1955,7 @@ HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag) } reg_value = READ_REG(GTZC_TZIC1->SR3); - for (i = 64; i < 96U; i++) + for (i = 64U; i < 96U; i++) { pFlag[i] = (reg_value & (1UL << (i - 64U))) >> (i - 64U); } diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gtzc.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gtzc.h index 0c2b9201a5c..10749e0a1c8 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gtzc.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_gtzc.h @@ -41,19 +41,25 @@ extern "C" { */ /*!< Values needed for MPCBB_Attribute_ConfigTypeDef structure sizing */ -#define GTZC_MCPBB_NB_VCTR_REG_MAX (32U) -#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX (1U) +#if defined (SRAM5_BASE) +#define GTZC_MPCBB_NB_VCTR_REG_MAX (52U) /* Up to 52 super-blocks */ +#define GTZC_MPCBB_NB_LCK_VCTR_REG_MAX (2U) /* More than one 32-bit needed */ +#else +#define GTZC_MPCBB_NB_VCTR_REG_MAX (32U) /* Up to 32 super-blocks */ +#define GTZC_MPCBB_NB_LCK_VCTR_REG_MAX (1U) /* One 32-bit needed */ +#endif /* SRAM5_BASE */ + typedef struct { - uint32_t MPCBB_SecConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX]; /*!< Each element specifies secure access mode for + uint32_t MPCBB_SecConfig_array[GTZC_MPCBB_NB_VCTR_REG_MAX]; /*!< Each element specifies secure access mode for a super-block. Each bit corresponds to a block inside the super-block. 0 means non-secure, 1 means secure */ - uint32_t MPCBB_PrivConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX]; /*!< Each element specifies privilege access mode for + uint32_t MPCBB_PrivConfig_array[GTZC_MPCBB_NB_VCTR_REG_MAX]; /*!< Each element specifies privilege access mode for a super-block. Each bit corresponds to a block inside the super-block. 0 means non-privilege, 1 means privilege */ - uint32_t MPCBB_LockConfig_array[GTZC_MCPBB_NB_LCK_VCTR_REG_MAX]; /*!< Each bit specifies the lock configuration of + uint32_t MPCBB_LockConfig_array[GTZC_MPCBB_NB_LCK_VCTR_REG_MAX]; /*!< Each bit specifies the lock configuration of a super-block (32 blocks). 0 means unlocked, 1 means locked */ } MPCBB_Attribute_ConfigTypeDef; @@ -190,7 +196,9 @@ typedef struct #define GTZC_PERIPH_WWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_WWDG_Pos) #define GTZC_PERIPH_IWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_IWDG_Pos) #define GTZC_PERIPH_SPI2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_SPI2_Pos) +#if defined (USART2) #define GTZC_PERIPH_USART2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART2_Pos) +#endif /* USART2 */ #define GTZC_PERIPH_USART3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART3_Pos) #define GTZC_PERIPH_UART4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART4_Pos) #define GTZC_PERIPH_UART5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART5_Pos) @@ -200,7 +208,18 @@ typedef struct #define GTZC_PERIPH_I2C4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C4_Pos) #define GTZC_PERIPH_LPTIM2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_LPTIM2_Pos) #define GTZC_PERIPH_FDCAN1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_FDCAN1_Pos) +#if defined (UCPD1) #define GTZC_PERIPH_UCPD1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UCPD1_Pos) +#endif /* UCPD1 */ +#if defined (USART6) +#define GTZC_PERIPH_USART6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART6_Pos) +#endif /* USART6 */ +#if defined (I2C5) +#define GTZC_PERIPH_I2C5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C5_Pos) +#endif /* I2C5 */ +#if defined (I2C6) +#define GTZC_PERIPH_I2C6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C6_Pos) +#endif /* I2C6 */ #define GTZC_PERIPH_TIM1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM1_Pos) #define GTZC_PERIPH_SPI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos) #define GTZC_PERIPH_TIM8 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM8_Pos) @@ -209,47 +228,113 @@ typedef struct #define GTZC_PERIPH_TIM16 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM16_Pos) #define GTZC_PERIPH_TIM17 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM17_Pos) #define GTZC_PERIPH_SAI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI1_Pos) +#if defined (SAI2) #define GTZC_PERIPH_SAI2 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI2_Pos) +#endif /* SAI2 */ +#if defined (LTDC) || defined (USB_DRD_FS) +#define GTZC_PERIPH_LTDCUSB (GTZC1_PERIPH_REG2 | GTZC_CFGR2_LTDCUSB_Pos) +#endif /* LTDC || USB_DRD_FS */ +#if defined (DSI) +#define GTZC_PERIPH_DSI (GTZC1_PERIPH_REG2 | GTZC_CFGR2_DSI_Pos) +#endif /* DSI */ +#if defined (GFXTIM) +#define GTZC_PERIPH_GFXTIM (GTZC1_PERIPH_REG2 | GTZC_CFGR2_GFXTIM_Pos) +#endif /* GFXTIM */ #define GTZC_PERIPH_MDF1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_MDF1_Pos) #define GTZC_PERIPH_CORDIC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CORDIC_Pos) #define GTZC_PERIPH_FMAC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FMAC_Pos) #define GTZC_PERIPH_CRC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CRC_Pos) #define GTZC_PERIPH_TSC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_TSC_Pos) +#if defined (DMA2D) #define GTZC_PERIPH_DMA2D (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DMA2D_Pos) +#endif /* DMA2D */ #define GTZC_PERIPH_ICACHE_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ICACHE_REG_Pos) #define GTZC_PERIPH_DCACHE1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCACHE1_REG_Pos) #define GTZC_PERIPH_ADC12 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ADC12_Pos) -#define GTZC_PERIPH_DCMI (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCMI_Pos) +#define GTZC_PERIPH_DCMI_PSSI (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCMI_Pos) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) #define GTZC_PERIPH_OTG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OTG_Pos) +#endif /* (USB_OTG_FS) || (USB_OTG_HS) */ +#if defined (AES) #define GTZC_PERIPH_AES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_AES_Pos) +#endif /* AES */ #define GTZC_PERIPH_HASH (GTZC1_PERIPH_REG3 | GTZC_CFGR3_HASH_Pos) #define GTZC_PERIPH_RNG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RNG_Pos) +#if defined (PKA) #define GTZC_PERIPH_PKA (GTZC1_PERIPH_REG3 | GTZC_CFGR3_PKA_Pos) +#endif /* PKA */ +#if defined (SAES) #define GTZC_PERIPH_SAES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SAES_Pos) +#endif /* SAES */ +#if defined (OCTOSPIM) #define GTZC_PERIPH_OCTOSPIM (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPIM_Pos) +#endif /* OCTOSPIM */ #define GTZC_PERIPH_SDMMC1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC1_Pos) +#if defined (SDMMC2) #define GTZC_PERIPH_SDMMC2 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC2_Pos) +#endif /* SDMMC2 */ +#if defined (FMC_BASE) #define GTZC_PERIPH_FSMC_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FSMC_REG_Pos) +#endif /* FMC_BASE */ #define GTZC_PERIPH_OCTOSPI1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI1_REG_Pos) +#if defined (OCTOSPI2) #define GTZC_PERIPH_OCTOSPI2_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI2_REG_Pos) +#endif /* OCTOSPI2 */ #define GTZC_PERIPH_RAMCFG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RAMCFG_Pos) +#if defined (GPU2D) +#define GTZC_PERIPH_GPU2D (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GPU2D_Pos) +#endif /* GPU2D */ +#if defined (GFXMMU) +#define GTZC_PERIPH_GFXMMU (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GFXMMU_Pos) +#define GTZC_PERIPH_GFXMMU_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GFXMMU_REG_Pos) +#endif /* GFXMMU */ +#if defined (HSPI1) +#define GTZC_PERIPH_HSPI1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_HSPI1_REG_Pos) +#endif /* HSPI1 */ +#if defined (DCACHE2) +#define GTZC_PERIPH_DCACHE2_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCACHE2_REG_Pos) +#endif /* DCACHE2 */ +#if defined (JPEG) +#define GTZC_PERIPH_JPEG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_JPEG_Pos) +#endif /* JPEG */ #define GTZC_PERIPH_GPDMA1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_GPDMA1_Pos) #define GTZC_PERIPH_FLASH_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_REG_Pos) #define GTZC_PERIPH_FLASH (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_Pos) +#if defined (OTFDEC2) #define GTZC_PERIPH_OTFDEC2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC2_Pos) +#endif /* OTFDEC2 */ +#if defined (OTFDEC1) #define GTZC_PERIPH_OTFDEC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC1_Pos) +#endif /* OTFDEC1 */ #define GTZC_PERIPH_TZSC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZSC1_Pos) #define GTZC_PERIPH_TZIC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZIC1_Pos) #define GTZC_PERIPH_OCTOSPI1_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OCTOSPI1_MEM_Pos) +#if defined (FMC_BASE) #define GTZC_PERIPH_FSMC_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FSMC_MEM_Pos) +#endif /* FMC_BASE */ #define GTZC_PERIPH_BKPSRAM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_BKPSRAM_Pos) +#if defined (OCTOSPI2) #define GTZC_PERIPH_OCTOSPI2_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OCTOSPI2_MEM_Pos) +#endif /* OCTOSPI2 */ +#if defined (HSPI1) +#define GTZC_PERIPH_HSPI1_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_HSPI1_MEM_Pos) +#endif /* HSPI1 */ +#if defined (SRAM6_BASE) +#define GTZC_PERIPH_SRAM6 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM6_Pos) +#define GTZC_PERIPH_MPCBB6_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB6_REG_Pos) +#endif /* SRAM6_BASE */ #define GTZC_PERIPH_SRAM1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM1_Pos) #define GTZC_PERIPH_MPCBB1_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB1_REG_Pos) #define GTZC_PERIPH_SRAM2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM2_Pos) #define GTZC_PERIPH_MPCBB2_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB2_REG_Pos) +#if defined (SRAM3_BASE) #define GTZC_PERIPH_SRAM3 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM3_Pos) +#endif /* SRAM3_BASE */ #define GTZC_PERIPH_MPCBB3_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB3_REG_Pos) +#if defined (SRAM5_BASE) +#define GTZC_PERIPH_SRAM5 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM5_Pos) +#define GTZC_PERIPH_MPCBB5_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB5_REG_Pos) +#endif /* SRAM5_BASE */ /* GTZC2 */ #define GTZC_PERIPH_SPI3 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_SPI3_Pos) @@ -365,17 +450,17 @@ typedef struct /* user-oriented definitions for MPCBB */ #define GTZC_MPCBB_BLOCK_SIZE 0x200U /* 512 Bytes */ #define GTZC_MPCBB_SUPERBLOCK_SIZE (GTZC_MPCBB_BLOCK_SIZE * 32U) /* 16 KBytes */ -#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED (0U) -#define GTZC_MCPBB_SUPERBLOCK_LOCKED (1U) +#define GTZC_MPCBB_SUPERBLOCK_UNLOCKED (0U) +#define GTZC_MPCBB_SUPERBLOCK_LOCKED (1U) -#define GTZC_MCPBB_BLOCK_NSEC (GTZC_ATTR_SEC_MASK | 0U) -#define GTZC_MCPBB_BLOCK_SEC (GTZC_ATTR_SEC_MASK | 1U) -#define GTZC_MCPBB_BLOCK_NPRIV (GTZC_ATTR_PRIV_MASK | 0U) -#define GTZC_MCPBB_BLOCK_PRIV (GTZC_ATTR_PRIV_MASK | 2U) +#define GTZC_MPCBB_BLOCK_NSEC (GTZC_ATTR_SEC_MASK | 0U) +#define GTZC_MPCBB_BLOCK_SEC (GTZC_ATTR_SEC_MASK | 1U) +#define GTZC_MPCBB_BLOCK_NPRIV (GTZC_ATTR_PRIV_MASK | 0U) +#define GTZC_MPCBB_BLOCK_PRIV (GTZC_ATTR_PRIV_MASK | 2U) /* user-oriented definitions for HAL_GTZC_MPCBB_GetLock() returned value */ -#define GTZC_MCPBB_LOCK_OFF (0U) -#define GTZC_MCPBB_LOCK_ON (1U) +#define GTZC_MPCBB_LOCK_OFF (0U) +#define GTZC_MPCBB_LOCK_ON (1U) /** * @} @@ -481,7 +566,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, * @} */ -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** @addtogroup GTZC_Exported_Functions_Group2 * @brief MPCWM Initialization and Configuration functions @@ -489,7 +574,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, */ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress, - MPCWM_ConfigTypeDef *pMPCWM_Desc); + const MPCWM_ConfigTypeDef *pMPCWM_Desc); HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, MPCWM_ConfigTypeDef *pMPCWM_Desc); /** @@ -502,45 +587,45 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAdd */ void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance); -uint32_t HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef *TZSC_Instance); +uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance); /** * @} */ -#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** @addtogroup GTZC_Exported_Functions_Group4 * @brief MPCBB Initialization and Configuration functions * @{ */ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, - MPCBB_ConfigTypeDef *pMPCBB_desc); + const MPCBB_ConfigTypeDef *pMPCBB_desc); HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, MPCBB_ConfigTypeDef *pMPCBB_desc); HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, uint32_t NbBlocks, - uint32_t *pMemAttributes); + const uint32_t *pMemAttributes); HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, uint32_t NbBlocks, uint32_t *pMemAttributes); -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, uint32_t NbSuperBlocks, - uint32_t *pLockAttributes); + const uint32_t *pLockAttributes); HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, uint32_t NbSuperBlocks, uint32_t *pLockAttributes); HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress); HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress, uint32_t *pLockState); -#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @} */ -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** @addtogroup GTZC_Exported_Functions_Group5 * @brief TZIC functions @@ -568,7 +653,7 @@ void HAL_GTZC_TZIC_Callback(uint32_t PeriphId); * @} */ -#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hash.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hash.c index e37ae59f2ea..aeb5a7ea98b 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hash.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hash.c @@ -123,7 +123,7 @@ (#) HAL in interruption mode (interruptions driven) (##)Due to HASH peripheral hardware design, the peripheral interruption is triggered every 64 bytes. - This is why, for driver implementation simplicity’s sake, user is requested to enter a message the + This is why, for driver implementation simplicity's sake, user is requested to enter a message the length of which is a multiple of 4 bytes. (##) When the message length (in bytes) is not a multiple of words, a specific field exists in HASH_STR @@ -158,9 +158,9 @@ [..] (#) The compilation define USE_HAL_HASH_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use function @ref HAL_HASH_RegisterCallback() to register a user callback. + Use function HAL_HASH_RegisterCallback() to register a user callback. - (#) Function @ref HAL_HASH_RegisterCallback() allows to register following callbacks: + (#) Function HAL_HASH_RegisterCallback() allows to register following callbacks: (+) InCpltCallback : callback for input completion. (+) DgstCpltCallback : callback for digest computation completion. (+) ErrorCallback : callback for error. @@ -169,9 +169,9 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - (#) Use function @ref HAL_HASH_UnRegisterCallback() to reset a callback to the default + (#) Use function HAL_HASH_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) InCpltCallback : callback for input completion. @@ -180,13 +180,13 @@ (+) MspInitCallback : HASH MspInit. (+) MspDeInitCallback : HASH MspDeInit. - (#) By default, after the @ref HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET + (#) By default, after the HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions: - examples @ref HAL_HASH_InCpltCallback(), @ref HAL_HASH_DgstCpltCallback() + examples HAL_HASH_InCpltCallback(), HAL_HASH_DgstCpltCallback() Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_HASH_Init - and @ref HAL_HASH_DeInit only when these callbacks are null (not registered beforehand) - If not, MspInit or MspDeInit are not null, the @ref HAL_HASH_Init and @ref HAL_HASH_DeInit + reset to the legacy weak (surcharged) functions in the HAL_HASH_Init + and HAL_HASH_DeInit only when these callbacks are null (not registered beforehand) + If not, MspInit or MspDeInit are not null, the HAL_HASH_Init and HAL_HASH_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). Callbacks can be registered/unregistered in READY state only. @@ -194,8 +194,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_HASH_RegisterCallback before calling @ref HAL_HASH_DeInit - or @ref HAL_HASH_Init function. + using HAL_HASH_RegisterCallback before calling HAL_HASH_DeInit + or HAL_HASH_Init function. When The compilation define USE_HAL_HASH_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -2941,6 +2941,14 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u return HAL_OK; } } /* if (polling_step == 1) */ + else + { + /* otherwise, carry on in interrupt-mode */ + hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data + to be fed to the Peripheral */ + hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Points at data which will be fed to the Peripheral at + the next interruption */ + } /* Process Unlock */ @@ -3556,3 +3564,4 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /** * @} */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hash.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hash.h index 2f02a3f6758..c0b144a03a2 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hash.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hash.h @@ -627,3 +627,4 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, #endif /* STM32U5xx_HAL_HASH_H */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hash_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hash_ex.c index 8215c1549de..ed34f233ecb 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hash_ex.c @@ -1037,3 +1037,4 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 /** * @} */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hash_ex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hash_ex.h index 3e26a61c467..df88733a216 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hash_ex.h @@ -172,3 +172,4 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 #endif /* STM32U5xx_HAL_HASH_EX_H */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hcd.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hcd.c index 162c44b7392..9fb1d07d336 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hcd.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hcd.c @@ -37,7 +37,9 @@ (##) Enable the HCD/USB Low Level interface clock using the following macros (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) + (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode) + (+++) __HAL_RCC_USB_CLK_ENABLE(); (##) Initialize the related GPIO clocks (##) Configure HCD pin-out (##) Configure HCD NVIC interrupt @@ -154,7 +156,7 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) hhcd->State = HAL_HCD_STATE_BUSY; #if defined (STM32U575xx) || defined (STM32U585xx) /* Disable DMA mode for FS instance */ - if ((USBx->CID & (0x1U << 8)) == 0U) + if ((USBx->CID & (0x1U << 14)) == 0U) { hhcd->Init.dma_enable = 0U; } @@ -200,24 +202,22 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) * This parameter can be a value from 0 to32K * @retval HAL status */ -HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps) +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, + uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps) { HAL_StatusTypeDef status; + uint32_t HostCoreSpeed; + uint32_t HCcharMps = mps; __HAL_LOCK(hhcd); hhcd->hc[ch_num].do_ping = 0U; hhcd->hc[ch_num].dev_addr = dev_address; - hhcd->hc[ch_num].max_packet = mps; hhcd->hc[ch_num].ch_num = ch_num; hhcd->hc[ch_num].ep_type = ep_type; hhcd->hc[ch_num].ep_num = epnum & 0x7FU; + (void)HAL_HCD_HC_ClearHubInfo(hhcd, ch_num); + if ((epnum & 0x80U) == 0x80U) { hhcd->hc[ch_num].ep_is_in = 1U; @@ -227,15 +227,27 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, hhcd->hc[ch_num].ep_is_in = 0U; } + HostCoreSpeed = USB_GetHostSpeed(hhcd->Instance); + + if (ep_type == EP_TYPE_ISOC) + { + /* FS device plugged to HS HUB */ + if ((speed == HCD_DEVICE_SPEED_FULL) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED)) + { + if (HCcharMps > ISO_SPLT_MPS) + { + /* ISO Max Packet Size for Split mode */ + HCcharMps = ISO_SPLT_MPS; + } + } + } + hhcd->hc[ch_num].speed = speed; + hhcd->hc[ch_num].max_packet = (uint16_t)HCcharMps; + + status = USB_HC_Init(hhcd->Instance, ch_num, epnum, + dev_address, speed, ep_type, (uint16_t)HCcharMps); - status = USB_HC_Init(hhcd->Instance, - ch_num, - epnum, - dev_address, - speed, - ep_type, - mps); __HAL_UNLOCK(hhcd); return status; @@ -253,7 +265,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num) HAL_StatusTypeDef status = HAL_OK; __HAL_LOCK(hhcd); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + (void)USB_HC_Halt(hhcd->Instance, ch_num); __HAL_UNLOCK(hhcd); return status; @@ -392,24 +404,41 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, switch (ep_type) { case EP_TYPE_CTRL: - if ((token == 1U) && (direction == 0U)) /*send data */ + if (token == 1U) /* send data */ { - if (length == 0U) + if (direction == 0U) { - /* For Status OUT stage, Length==0, Status Out PID = 1 */ - hhcd->hc[ch_num].toggle_out = 1U; - } + if (length == 0U) + { + /* For Status OUT stage, Length == 0U, Status Out PID = 1 */ + hhcd->hc[ch_num].toggle_out = 1U; + } - /* Set the Data Toggle bit as per the Flag */ - if (hhcd->hc[ch_num].toggle_out == 0U) - { - /* Put the PID 0 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } } else { - /* Put the PID 1 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + if (hhcd->hc[ch_num].do_ssplit == 1U) + { + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } } } break; @@ -544,8 +573,11 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) (void)USB_FlushTxFifo(USBx, 0x10U); (void)USB_FlushRxFifo(USBx); - /* Restore FS Clock */ - (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) + { + /* Restore FS Clock */ + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + } /* Handle Host Port Disconnect Interrupt */ #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) @@ -574,16 +606,6 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF); } - /* Handle Rx Queue Level Interrupts */ - if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) - { - USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); - - HCD_RXQLVL_IRQHandler(hhcd); - - USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); - } - /* Handle Host channel Interrupt */ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) { @@ -604,6 +626,16 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) } __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT); } + + /* Handle Rx Queue Level Interrupts */ + if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) + { + USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + + HCD_RXQLVL_IRQHandler(hhcd); + + USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + } } } @@ -1155,6 +1187,54 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) return (USB_GetHostSpeed(hhcd->Instance)); } +/** + * @brief Set host channel Hub information. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param addr Hub address + * @param PortNbr Hub port number + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t addr, uint8_t PortNbr) +{ + uint32_t HostCoreSpeed = USB_GetHostSpeed(hhcd->Instance); + + /* LS/FS device plugged to HS HUB */ + if ((hhcd->hc[ch_num].speed != HCD_DEVICE_SPEED_HIGH) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED)) + { + hhcd->hc[ch_num].do_ssplit = 1U; + + if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) && (hhcd->hc[ch_num].ep_is_in != 0U)) + { + hhcd->hc[ch_num].toggle_in = 1U; + } + } + + hhcd->hc[ch_num].hub_addr = addr; + hhcd->hc[ch_num].hub_port_nbr = PortNbr; + + return HAL_OK; +} + + +/** + * @brief Clear host channel hub information. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + hhcd->hc[ch_num].do_ssplit = 0U; + hhcd->hc[ch_num].do_csplit = 0U; + hhcd->hc[ch_num].hub_addr = 0U; + hhcd->hc[ch_num].hub_port_nbr = 0U; + + return HAL_OK; +} /** * @} */ @@ -1177,99 +1257,84 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t ch_num = (uint32_t)chnum; - uint32_t tmpreg; - if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) - { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR) + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR); - hhcd->hc[ch_num].state = HC_BBLERR; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_BBERR)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_BBERR); + hhcd->hc[chnum].state = HC_BBLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL)) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - hhcd->hc[ch_num].state = HC_STALL; - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); + hhcd->hc[chnum].state = HC_STALL; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR)) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - hhcd->hc[ch_num].state = HC_DATATGLERR; - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); + hhcd->hc[chnum].state = HC_DATATGLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR)) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - hhcd->hc[ch_num].state = HC_XACTERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } else { /* ... */ } - if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR)) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC)) { - if (hhcd->Init.dma_enable != 0U) + /* Clear any pending ACK IT */ + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + + if (hhcd->hc[chnum].do_csplit == 1U) { - hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].XferSize - \ - (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); } - hhcd->hc[ch_num].state = HC_XFRC; - hhcd->hc[ch_num].ErrCnt = 0U; - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); - - if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || - (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) + if (hhcd->Init.dma_enable != 0U) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].XferSize - (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); } - else if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) - { - USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; - hhcd->hc[ch_num].urb_state = URB_DONE; -#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); -#else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); -#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + hhcd->hc[chnum].state = HC_XFRC; + hhcd->hc[chnum].ErrCnt = 0U; + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); } - else if (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC) + else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) || + (hhcd->hc[chnum].ep_type == EP_TYPE_ISOC)) { - hhcd->hc[ch_num].urb_state = URB_DONE; - hhcd->hc[ch_num].toggle_in ^= 1U; + USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; + hhcd->hc[chnum].urb_state = URB_DONE; #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else @@ -1279,95 +1344,220 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if (hhcd->Init.dma_enable == 1U) { - if (((hhcd->hc[ch_num].XferSize / hhcd->hc[ch_num].max_packet) & 1U) != 0U) + if ((((hhcd->hc[chnum].xfer_count + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet) & 1U) != 0U) { - hhcd->hc[ch_num].toggle_in ^= 1U; + hhcd->hc[chnum].toggle_in ^= 1U; } } else { - hhcd->hc[ch_num].toggle_in ^= 1U; + hhcd->hc[chnum].toggle_in ^= 1U; + } + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + + if (hhcd->hc[chnum].do_ssplit == 1U) + { + hhcd->hc[chnum].do_csplit = 1U; + hhcd->hc[chnum].state = HC_ACK; + + (void)USB_HC_Halt(hhcd->Instance, chnum); } } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH)) { - __HAL_HCD_MASK_HALT_HC_INT(ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); - if (hhcd->hc[ch_num].state == HC_XFRC) + if (hhcd->hc[chnum].state == HC_XFRC) { - hhcd->hc[ch_num].urb_state = URB_DONE; + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_DONE; } - else if (hhcd->hc[ch_num].state == HC_STALL) + else if (hhcd->hc[chnum].state == HC_STALL) { - hhcd->hc[ch_num].urb_state = URB_STALL; + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_STALL; } - else if ((hhcd->hc[ch_num].state == HC_XACTERR) || - (hhcd->hc[ch_num].state == HC_DATATGLERR)) + else if ((hhcd->hc[chnum].state == HC_XACTERR) || + (hhcd->hc[chnum].state == HC_DATATGLERR)) { - hhcd->hc[ch_num].ErrCnt++; - if (hhcd->hc[ch_num].ErrCnt > 2U) + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) { - hhcd->hc[ch_num].ErrCnt = 0U; - hhcd->hc[ch_num].urb_state = URB_ERROR; + hhcd->hc[chnum].ErrCnt = 0U; + + if (hhcd->hc[chnum].do_ssplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + hhcd->hc[chnum].ep_ss_schedule = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } + + hhcd->hc[chnum].urb_state = URB_ERROR; } else { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + } + else if (hhcd->hc[chnum].state == HC_NYET) + { + hhcd->hc[chnum].state = HC_HALTED; + + if (hhcd->hc[chnum].do_csplit == 1U) + { + if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR) + { + hhcd->hc[chnum].NyetErrCnt++; + if (hhcd->hc[chnum].NyetErrCnt > 2U) + { + hhcd->hc[chnum].NyetErrCnt = 0U; + hhcd->hc[chnum].do_csplit = 0U; + + if (hhcd->hc[chnum].ErrCnt < 3U) + { + hhcd->hc[chnum].ep_ss_schedule = 1U; + } + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + hhcd->hc[chnum].urb_state = URB_ERROR; + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + } + else if (hhcd->hc[chnum].state == HC_ACK) + { + hhcd->hc[chnum].state = HC_HALTED; + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + /* Set Complete split and re-activate the channel */ + USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; + USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_NYET; + USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINT_ACK; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + } + else if (hhcd->hc[chnum].state == HC_NAK) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { /* re-activate the channel */ - tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg = USBx_HC(chnum)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; + USBx_HC(chnum)->HCCHAR = tmpreg; } } - else if (hhcd->hc[ch_num].state == HC_NAK) + else if (hhcd->hc[chnum].state == HC_BBLERR) { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; - - /* re-activate the channel */ - tmpreg = USBx_HC(ch_num)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + hhcd->hc[chnum].urb_state = URB_ERROR; } - else if (hhcd->hc[ch_num].state == HC_BBLERR) + else { - hhcd->hc[ch_num].ErrCnt++; - hhcd->hc[ch_num].urb_state = URB_ERROR; + if (hhcd->hc[chnum].state == HC_HALTED) + { + return; + } } - else + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); + hhcd->hc[chnum].state = HC_NYET; + + if (hhcd->hc[chnum].do_ssplit == 0U) { - /* ... */ + hhcd->hc[chnum].ErrCnt = 0U; } - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK)) { - if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) + if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR) { - hhcd->hc[ch_num].ErrCnt = 0U; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].state = HC_NAK; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || - (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) + else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) { - hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[chnum].ErrCnt = 0U; - if (hhcd->Init.dma_enable == 0U) + if ((hhcd->Init.dma_enable == 0U) || (hhcd->hc[chnum].do_csplit == 1U)) { - hhcd->hc[ch_num].state = HC_NAK; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[chnum].state = HC_NAK; + (void)USB_HC_Halt(hhcd->Instance, chnum); } } else { /* ... */ } - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + __HAL_HCD_UNMASK_ACK_HC_INT(chnum); + } + + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); } else { @@ -1386,183 +1576,229 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t ch_num = (uint32_t)chnum; uint32_t tmpreg; uint32_t num_packets; - if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); - if (hhcd->hc[ch_num].do_ping == 1U) + if (hhcd->hc[chnum].do_ping == 1U) { - hhcd->hc[ch_num].do_ping = 0U; - hhcd->hc[ch_num].urb_state = URB_NOTREADY; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[chnum].do_ping = 0U; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + hhcd->hc[chnum].state = HC_ACK; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + + if ((hhcd->hc[chnum].do_ssplit == 1U) && (hhcd->hc[chnum].do_csplit == 0U)) + { + if (hhcd->hc[chnum].ep_type != EP_TYPE_ISOC) + { + hhcd->hc[chnum].do_csplit = 1U; + } + + hhcd->hc[chnum].state = HC_ACK; + (void)USB_HC_Halt(hhcd->Instance, chnum); + + /* reset error_count */ + hhcd->hc[chnum].ErrCnt = 0U; } } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR)) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC)) { - hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[chnum].ErrCnt = 0U; /* transaction completed with NYET state, update do ping state */ - if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) + { + hhcd->hc[chnum].do_ping = 1U; + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); + } + + if (hhcd->hc[chnum].do_csplit != 0U) { - hhcd->hc[ch_num].do_ping = 1U; - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); } - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); - hhcd->hc[ch_num].state = HC_XFRC; + + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); + hhcd->hc[chnum].state = HC_XFRC; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) { - hhcd->hc[ch_num].state = HC_NYET; - hhcd->hc[ch_num].do_ping = 1U; - hhcd->hc[ch_num].ErrCnt = 0U; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); + hhcd->hc[chnum].state = HC_NYET; + + if (hhcd->hc[chnum].do_ssplit == 0U) + { + hhcd->hc[chnum].do_ping = 1U; + } + + hhcd->hc[chnum].ErrCnt = 0U; + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - hhcd->hc[ch_num].state = HC_STALL; + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); + hhcd->hc[chnum].state = HC_STALL; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK)) { - hhcd->hc[ch_num].ErrCnt = 0U; - hhcd->hc[ch_num].state = HC_NAK; + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].state = HC_NAK; - if (hhcd->hc[ch_num].do_ping == 0U) + if (hhcd->hc[chnum].do_ping == 0U) { - if (hhcd->hc[ch_num].speed == HCD_DEVICE_SPEED_HIGH) + if (hhcd->hc[chnum].speed == HCD_DEVICE_SPEED_HIGH) { - hhcd->hc[ch_num].do_ping = 1U; + hhcd->hc[chnum].do_ping = 1U; } } - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR)) { if (hhcd->Init.dma_enable == 0U) { - hhcd->hc[ch_num].state = HC_XACTERR; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } else { - hhcd->hc[ch_num].ErrCnt++; - if (hhcd->hc[ch_num].ErrCnt > 2U) + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) { - hhcd->hc[ch_num].ErrCnt = 0U; - hhcd->hc[ch_num].urb_state = URB_ERROR; - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, - hhcd->hc[ch_num].urb_state); + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].urb_state = URB_ERROR; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; + hhcd->hc[chnum].urb_state = URB_NOTREADY; } } - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR)) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); - hhcd->hc[ch_num].state = HC_DATATGLERR; + hhcd->hc[chnum].state = HC_DATATGLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH)) { - __HAL_HCD_MASK_HALT_HC_INT(ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); - if (hhcd->hc[ch_num].state == HC_XFRC) + if (hhcd->hc[chnum].state == HC_XFRC) { - hhcd->hc[ch_num].urb_state = URB_DONE; - if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) || - (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)) + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_DONE; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) || + (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)) { if (hhcd->Init.dma_enable == 0U) { - hhcd->hc[ch_num].toggle_out ^= 1U; + hhcd->hc[chnum].toggle_out ^= 1U; } - if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[ch_num].xfer_len > 0U)) + if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[chnum].xfer_len > 0U)) { - num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet; + num_packets = (hhcd->hc[chnum].xfer_len + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet; if ((num_packets & 1U) != 0U) { - hhcd->hc[ch_num].toggle_out ^= 1U; + hhcd->hc[chnum].toggle_out ^= 1U; } } } } - else if (hhcd->hc[ch_num].state == HC_NAK) + else if (hhcd->hc[chnum].state == HC_ACK) { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; + hhcd->hc[chnum].state = HC_HALTED; + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + } + else if (hhcd->hc[chnum].state == HC_NAK) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } } - else if (hhcd->hc[ch_num].state == HC_NYET) + else if (hhcd->hc[chnum].state == HC_NYET) { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; } - else if (hhcd->hc[ch_num].state == HC_STALL) + else if (hhcd->hc[chnum].state == HC_STALL) { - hhcd->hc[ch_num].urb_state = URB_STALL; + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_STALL; } - else if ((hhcd->hc[ch_num].state == HC_XACTERR) || - (hhcd->hc[ch_num].state == HC_DATATGLERR)) + else if ((hhcd->hc[chnum].state == HC_XACTERR) || + (hhcd->hc[chnum].state == HC_DATATGLERR)) { - hhcd->hc[ch_num].ErrCnt++; - if (hhcd->hc[ch_num].ErrCnt > 2U) + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) { - hhcd->hc[ch_num].ErrCnt = 0U; - hhcd->hc[ch_num].urb_state = URB_ERROR; + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].urb_state = URB_ERROR; } else { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; + hhcd->hc[chnum].urb_state = URB_NOTREADY; /* re-activate the channel */ - tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg = USBx_HC(chnum)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; + USBx_HC(chnum)->HCCHAR = tmpreg; } } else { - /* ... */ + return; } - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else { - /* ... */ + return; } } @@ -1580,10 +1816,10 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) uint32_t GrxstspReg; uint32_t xferSizePktCnt; uint32_t tmpreg; - uint32_t ch_num; + uint32_t chnum; GrxstspReg = hhcd->Instance->GRXSTSP; - ch_num = GrxstspReg & USB_OTG_GRXSTSP_EPNUM; + chnum = GrxstspReg & USB_OTG_GRXSTSP_EPNUM; pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17; pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4; @@ -1591,33 +1827,33 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) { case GRXSTS_PKTSTS_IN: /* Read the data into the host buffer. */ - if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0)) + if ((pktcnt > 0U) && (hhcd->hc[chnum].xfer_buff != (void *)0)) { - if ((hhcd->hc[ch_num].xfer_count + pktcnt) <= hhcd->hc[ch_num].xfer_len) + if ((hhcd->hc[chnum].xfer_count + pktcnt) <= hhcd->hc[chnum].xfer_len) { (void)USB_ReadPacket(hhcd->Instance, - hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt); + hhcd->hc[chnum].xfer_buff, (uint16_t)pktcnt); /* manage multiple Xfer */ - hhcd->hc[ch_num].xfer_buff += pktcnt; - hhcd->hc[ch_num].xfer_count += pktcnt; + hhcd->hc[chnum].xfer_buff += pktcnt; + hhcd->hc[chnum].xfer_count += pktcnt; /* get transfer size packet count */ - xferSizePktCnt = (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19; + xferSizePktCnt = (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19; - if ((hhcd->hc[ch_num].max_packet == pktcnt) && (xferSizePktCnt > 0U)) + if ((hhcd->hc[chnum].max_packet == pktcnt) && (xferSizePktCnt > 0U)) { /* re-activate the channel when more packets are expected */ - tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg = USBx_HC(chnum)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; - hhcd->hc[ch_num].toggle_in ^= 1U; + USBx_HC(chnum)->HCCHAR = tmpreg; + hhcd->hc[chnum].toggle_in ^= 1U; } } else { - hhcd->hc[ch_num].urb_state = URB_ERROR; + hhcd->hc[chnum].urb_state = URB_ERROR; } } break; @@ -1672,7 +1908,7 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA) { - if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) + if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) { if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) { @@ -1687,7 +1923,7 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) { if (hhcd->Init.speed == HCD_SPEED_FULL) { - USBx_HOST->HFIR = 60000U; + USBx_HOST->HFIR = HFIR_60_MHZ; } } #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) @@ -1726,6 +1962,2806 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) + +/** @defgroup HCD HCD + * @brief HCD HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function ----------------------------------------------------------*/ +/** @defgroup HCD_Private_Functions HCD Private Functions + * @{ + */ +static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); +static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); +static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); +static void HAL_HCD_ClearPhyChannel(HCD_HandleTypeDef *hhcd); +static uint8_t HAL_HCD_GetLogical_Channel(HCD_HandleTypeDef *hhcd, uint8_t phy_chnum, uint8_t dir); +static uint8_t HAL_HCD_Check_usedChannel(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +static uint8_t HAL_HCD_Get_FreePhyChannel(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t ep_type); + +#if (USE_USB_DOUBLE_BUFFER == 1U) +static void HCD_HC_IN_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t phy_chnum, uint32_t regvalue); +static void HCD_HC_OUT_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t phy_chnum, uint32_t regvalue); +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + +static uint16_t HAL_HCD_GetFreePMA(HCD_HandleTypeDef *hhcd, uint16_t mps); +static HAL_StatusTypeDef HAL_HCD_PMAFree(HCD_HandleTypeDef *hhcd, uint32_t pma_base, uint16_t mps); +static void inline HCD_HC_IN_ISO(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t phy_chnum, uint32_t regvalue); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup HCD_Exported_Functions HCD Exported Functions + * @{ + */ + +/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== +##### Initialization and de-initialization functions ##### +=============================================================================== +[..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) +{ + /* Check the HCD handle allocation */ + if (hhcd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance)); + + if (hhcd->State == HAL_HCD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hhcd->Lock = HAL_UNLOCKED; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->SOFCallback = HAL_HCD_SOF_Callback; + hhcd->ConnectCallback = HAL_HCD_Connect_Callback; + hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback; + hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback; + hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback; + hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; + + if (hhcd->MspInitCallback == NULL) + { + hhcd->MspInitCallback = HAL_HCD_MspInit; + } + + /* Init the low level hardware */ + hhcd->MspInitCallback(hhcd); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_HCD_MspInit(hhcd); +#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */ + } + hhcd->State = HAL_HCD_STATE_BUSY; + + /* Disable the Interrupts */ + (void)__HAL_HCD_DISABLE(hhcd); + + /* Dma not supported, force to zero */ + hhcd->Init.dma_enable = 0U; + + /* Init the Core (common init.) */ + (void)USB_CoreInit(hhcd->Instance, hhcd->Init); + + /* Force Host Mode */ + (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE); + + /* Init Host */ + (void)USB_HostInit(hhcd->Instance, hhcd->Init); + + /* Deactivate the power down */ + hhcd->Instance->CNTR &= ~USB_CNTR_PDWN; + + hhcd->State = HAL_HCD_STATE_READY; + + /* Host Port State */ + hhcd->HostState = HCD_HCD_STATE_DISCONNECTED; + + /* Init PMA Address */ + (void)HAL_HCD_PMAReset(hhcd); + + hhcd->State = HAL_HCD_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initialize a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param epnum Endpoint number. + * This parameter can be a value from 1 to 15 + * @param dev_address Current device address + * This parameter can be a value from 0 to 255 + * @param speed Current device speed. + * This parameter can be one of these values: + * HCD_DEVICE_SPEED_HIGH High speed mode, + * HCD_DEVICE_SPEED_FULL Full speed mode, + * HCD_DEVICE_SPEED_LOW Low speed mode + * @param ep_type Endpoint Type. + * This parameter can be one of these values: + * USBH_EP_CONTROL Control type, + * USBH_EP_ISO Isochronous type, + * USBH_EP_BULK Bulk type, + * USBH_EP_INTERRUPT Interrupt type + * @param mps Max Packet Size. + * This parameter can be a value from 0 to32K + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, + uint8_t speed, uint8_t ep_type, uint16_t mps) +{ + HAL_StatusTypeDef status; + uint8_t used_channel; + uint8_t ep0_virtual_channel; + + __HAL_LOCK(hhcd); + + /* Check if the logical channel are already allocated */ + used_channel = HAL_HCD_Check_usedChannel(hhcd, ch_num); + + /* Check if the channel is not already opened */ + if (used_channel == 0U) + { + /* Allocate New Physical channel */ + hhcd->hc[ch_num & 0xFU].phy_ch_num = HAL_HCD_Get_FreePhyChannel(hhcd, ch_num, epnum, ep_type); + + /* No free Channel available, return error */ + if (hhcd->hc[ch_num & 0xFU].phy_ch_num == HCD_FREE_CH_NOT_FOUND) + { + return HAL_ERROR; + } + } + /* Channel already opened */ + else + { + /* Get Physical Channel number */ + hhcd->hc[ch_num & 0xFU].phy_ch_num = (used_channel & 0xF0U) >> 4U; + } + + if ((epnum & 0x80U) != 0U) + { + hhcd->hc[ch_num & 0xFU].ch_dir = CH_IN_DIR; + } + else + { + hhcd->hc[ch_num & 0xFU].ch_dir = CH_OUT_DIR; + } + + hhcd->hc[ch_num & 0xFU].dev_addr = dev_address; + hhcd->hc[ch_num & 0xFU].max_packet = mps; + hhcd->hc[ch_num & 0xFU].ep_type = ep_type; + hhcd->hc[ch_num & 0xFU].ep_num = epnum & 0x7FU; + hhcd->hc[ch_num & 0xFU].speed = speed; + + /* Check if the channel is not already opened */ + if (used_channel == 0U) + { + if (((ep_type == EP_TYPE_ISOC) && (hhcd->Init.iso_singlebuffer_enable == 0U)) || + ((ep_type == EP_TYPE_BULK) && (hhcd->Init.bulk_doublebuffer_enable == 1U))) + { + /* PMA Dynamic Allocation */ + status = HAL_HCD_PMAlloc(hhcd, ch_num, HCD_DBL_BUF, mps); + + if (status == HAL_ERROR) + { + return HAL_ERROR; + } + + /* Clear Channel DTOG_TX */ + HCD_CLEAR_TX_DTOG(hhcd->Instance, hhcd->hc[ch_num & 0xFU].phy_ch_num); + + /* Clear Channel DTOG RX */ + HCD_CLEAR_RX_DTOG(hhcd->Instance, hhcd->hc[ch_num & 0xFU].phy_ch_num); + + } + else + { + if (hhcd->hc[ch_num & 0xFU].ep_num != 0U) + { + status = HAL_HCD_PMAlloc(hhcd, ch_num, HCD_SNG_BUF, mps); + + if (status == HAL_ERROR) + { + return HAL_ERROR; + } + } + else + { + if (ch_num == 0U) + { + ep0_virtual_channel = (uint8_t)(hhcd->ep0_PmaAllocState & 0xFU); + + if ((ep0_virtual_channel != 0U) && (((hhcd->ep0_PmaAllocState & 0xF0U) >> 4) == CH_IN_DIR)) + { + if (hhcd->hc[ch_num & 0xFU].ch_dir == CH_OUT_DIR) + { + status = HAL_HCD_PMAlloc(hhcd, ch_num, HCD_SNG_BUF, 64U); + + if (status == HAL_ERROR) + { + return HAL_ERROR; + } + } + else + { + return HAL_ERROR; + } + } + else + { + /* PMA Dynamic Allocation for EP0 OUT direction */ + hhcd->hc[ch_num & 0xFU].ch_dir = CH_OUT_DIR; + status = HAL_HCD_PMAlloc(hhcd, ch_num, HCD_SNG_BUF, 64U); + + if (status == HAL_ERROR) + { + return HAL_ERROR; + } + + /* PMA Dynamic Allocation for EP0 IN direction */ + hhcd->hc[ch_num & 0xFU].ch_dir = CH_IN_DIR; + status = HAL_HCD_PMAlloc(hhcd, ch_num, HCD_SNG_BUF, 64U); + + if (status == HAL_ERROR) + { + return HAL_ERROR; + } + } + } + else + { + if (((hhcd->ep0_PmaAllocState & 0xF00U) >> 8) == 1U) + { + ep0_virtual_channel = (uint8_t)(hhcd->ep0_PmaAllocState & 0xFU); + + if (((hhcd->ep0_PmaAllocState & 0xF0U) >> 4) == CH_IN_DIR) + { + hhcd->hc[ch_num & 0xFU].pmaaddr1 = hhcd->hc[ep0_virtual_channel & 0xFU].pmaaddr1; + } + else + { + hhcd->hc[ch_num & 0xFU].pmaaddr0 = hhcd->hc[ep0_virtual_channel & 0xFU].pmaaddr0; + } + } + else + { + status = HAL_HCD_PMAlloc(hhcd, ch_num, HCD_SNG_BUF, 64U); + + if (status == HAL_ERROR) + { + return HAL_ERROR; + } + } + } + } + } + } + + if ((epnum & 0x80U) != 0U) + { + hhcd->hc[ch_num & 0xFU].ch_dir = CH_IN_DIR; + + if (hhcd->hc[ch_num & 0xFU].ep_num == 0U) + { + hhcd->hc[ch_num & 0xFU].pmaadress = hhcd->hc[ch_num & 0xFU].pmaaddr1; + } + } + else + { + hhcd->hc[ch_num & 0xFU].ch_dir = CH_OUT_DIR; + + if (hhcd->hc[ch_num & 0xFU].ep_num == 0U) + { + hhcd->hc[ch_num & 0xFU].pmaadress = hhcd->hc[ch_num & 0xFU].pmaaddr0; + } + } + + /* Init the USB Channel CHEPRx */ + status = USB_HC_Init(hhcd->Instance, hhcd->hc[ch_num & 0xFU].phy_ch_num, + epnum, dev_address, speed, ep_type, mps); + + /* check single buffer for isochronous channel */ + if (ep_type == EP_TYPE_ISOC) + { + if (hhcd->Init.iso_singlebuffer_enable == 1U) + { + (void)USB_HC_DoubleBuffer(hhcd->Instance, hhcd->hc[ch_num & 0xFU].phy_ch_num, + USB_DRD_ISOC_DBUFF_DISABLE); + } + } + + /* Bulk double buffer check */ + if (ep_type == EP_TYPE_BULK) + { + if (hhcd->Init.bulk_doublebuffer_enable == 1U) + { + (void)USB_HC_DoubleBuffer(hhcd->Instance, hhcd->hc[ch_num & 0xFU].phy_ch_num, + USB_DRD_BULK_DBUFF_ENBALE); + } + } + + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief HAL_HCD_HC_Close Pipe + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Close(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + /* Stop the channel */ + (void) HAL_HCD_HC_Halt(hhcd, ch_num); + + HAL_Delay(3U); + + if (hhcd->hc[ch_num & 0xFU].ch_dir == CH_IN_DIR) + { + /* Free Allocated Channel */ + hhcd->phy_chin_state[hhcd->hc[ch_num & 0xFU].phy_ch_num] = 0U; + } + else + { + /* Free Allocated Channel */ + hhcd->phy_chout_state[hhcd->hc[ch_num & 0xFU].phy_ch_num] = 0U; + } + + /* Reset PMA Channel_Allocation */ + (void)HAL_HCD_PMADeAlloc(hhcd, ch_num); + + return HAL_OK; +} + +/** + * @brief Halt a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + HAL_StatusTypeDef status = HAL_OK; + + __HAL_LOCK(hhcd); + if (hhcd->hc[ch_num & 0xFU].ch_dir == CH_IN_DIR) + { + (void)USB_HC_IN_Halt(hhcd->Instance, (uint8_t) hhcd->hc[ch_num & 0xFU].phy_ch_num); + } + else + { + (void)USB_HC_OUT_Halt(hhcd->Instance, (uint8_t) hhcd->hc[ch_num & 0xFU].phy_ch_num); + } + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief DeInitialize the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd) +{ + uint8_t idx; + + /* Check the HCD handle allocation */ + if (hhcd == NULL) + { + return HAL_ERROR; + } + + /* Host Port State */ + hhcd->HostState = HCD_HCD_STATE_DISCONNECTED; + + /* Reset PMA Address */ + (void)HAL_HCD_PMAReset(hhcd); + + for (idx = 0U; idx < hhcd->Init.Host_channels; idx++) + { + hhcd->phy_chin_state[idx] = 0U; + hhcd->phy_chout_state[idx] = 0U; + } + + /* reset Ep0 Pma allocation state */ + hhcd->ep0_PmaAllocState = 0U; + + hhcd->State = HAL_HCD_STATE_BUSY; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + if (hhcd->MspDeInitCallback == NULL) + { + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hhcd->MspDeInitCallback(hhcd); +#else + /* DeInit the low level hardware: CLOCK, NVIC. */ + HAL_HCD_MspDeInit(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + hhcd->State = HAL_HCD_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initialize the HCD MSP. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_HCD_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the HCD MSP. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_HCD_MspDeInit could be implemented in the user file + */ +} + +__weak void HAL_HCD_SuspendCallback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_HCD_SuspendCallback could be implemented in the user file + */ + +} + +__weak void HAL_HCD_ResumeCallback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_HCD_ResumeCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions + * @brief HCD IO operation functions + * +@verbatim +=============================================================================== +##### IO operation functions ##### +=============================================================================== +[..] This subsection provides a set of functions allowing to manage the USB Host Data +Transfer + +@endverbatim + * @{ + */ + +/** + * @brief Submit a new URB for processing. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param direction Channel number. + * This parameter can be one of these values: + * 0 : Output / 1 : Input + * @param ep_type Endpoint Type. + * This parameter can be one of these values: + * USBH_EP_CONTROL : Control type/ + * USBH_EP_ISO : Isochronous type/ + * USBH_EP_BULK : Bulk type/ + * USBH_EP_INTERRUPT : Interrupt type/ + * @param token Endpoint Type. + * This parameter can be one of these values: + * 0: HC_PID_SETUP / 1: HC_PID_DATA1 + * @param pbuff pointer to URB data + * @param length Length of URB data + * @param do_ping activate do ping protocol (for high speed only). + * This parameter can be one of these values: + * 0 : do ping inactive / 1 : do ping active + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t direction, uint8_t ep_type, + uint8_t token, uint8_t *pbuff, + uint16_t length, uint8_t do_ping) +{ + UNUSED(do_ping); + + if (token == 0U) + { + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_SETUP; + } + else + { + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA1; + } + + /* Manage Data Toggle */ + switch (ep_type) + { + case EP_TYPE_CTRL: + if ((token == 1U) && (direction == 0U)) /* send data */ + { + if (length == 0U) + { + /* For Status OUT stage, Length==0, Status Out PID = 1 */ + hhcd->hc[ch_num & 0xFU].toggle_out = 1U; + } + + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num & 0xFU].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA1; + } + } + break; + + case EP_TYPE_BULK: + if (direction == 0U) + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num & 0xFU].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA1; + } + } + else + { + if (hhcd->hc[ch_num & 0xFU].toggle_in == 0U) + { + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA1; + } + } + break; + + case EP_TYPE_INTR: + if (direction == 0U) + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num & 0xFU].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA1; + } + } + else + { + if (hhcd->hc[ch_num & 0xFU].toggle_in == 0U) + { + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA1; + } + } + break; + + case EP_TYPE_ISOC: + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA0; + break; + + default: + break; + } + + hhcd->hc[ch_num & 0xFU].xfer_buff = pbuff; + hhcd->hc[ch_num & 0xFU].xfer_len = length; + hhcd->hc[ch_num & 0xFU].xfer_len_db = length; + hhcd->hc[ch_num & 0xFU].urb_state = URB_IDLE; + hhcd->hc[ch_num & 0xFU].xfer_count = 0U; + hhcd->hc[ch_num & 0xFU].state = HC_IDLE; + + return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num & 0xFU]); +} +/** + * @brief Handle HCD interrupt request. + * @param hhcd HCD handle + * @retval None + */ +void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + uint8_t phy_chnum; + uint8_t chnum; + uint32_t epch_reg; + uint32_t wIstr = USB_ReadInterrupts(hhcd->Instance); + + /* Port Change Detected (Connection/Disconnection) */ + if ((wIstr & USB_ISTR_DCON) == USB_ISTR_DCON) + { + /* Clear Flag */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_ISTR_DCON); + + /* Call Port IRQHandler */ + HCD_Port_IRQHandler(hhcd); + + return; + } + + /* Correct Transaction Detected -------*/ + if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR) + { + /* Handle Host channel Interrupt */ + for (phy_chnum = 0U; phy_chnum < hhcd->Init.Host_channels; phy_chnum++) + { + if ((HCD_GET_CHANNEL(hhcd->Instance, phy_chnum) & USB_CH_VTRX) != 0U) + { + /* Get Logical channel to check if the channel is already opened */ + chnum = HAL_HCD_GetLogical_Channel(hhcd, phy_chnum, 1U); + + if (chnum != HCD_LOGICAL_CH_NOT_OPENED) + { + /* Call Channel_IN_IRQ() */ + HCD_HC_IN_IRQHandler(hhcd, chnum); + } + else + { + /*Channel was not closed correctly still have interrupt */ + epch_reg = HCD_GET_CHANNEL(hhcd->Instance, phy_chnum); + epch_reg = (epch_reg & (USB_CHEP_REG_MASK & (~USB_CH_ERRRX) & (~USB_CH_VTRX))) | + (USB_CH_VTTX | USB_CH_ERRTX); + + HCD_SET_CHANNEL(hhcd->Instance, phy_chnum, epch_reg); + } + } + + if ((HCD_GET_CHANNEL(hhcd->Instance, phy_chnum) & USB_CH_VTTX) != 0U) + { + /* Get Logical channel to check if the channel is already opened */ + chnum = HAL_HCD_GetLogical_Channel(hhcd, phy_chnum, 0U); + + if (chnum != HCD_LOGICAL_CH_NOT_OPENED) + { + /*Call Channel_OUT_IRQ()*/ + HCD_HC_OUT_IRQHandler(hhcd, chnum); + } + else + { + /* Clear Error & unwanted VTTX or Channel was not closed correctly */ + epch_reg = HCD_GET_CHANNEL(hhcd->Instance, phy_chnum); + epch_reg = (epch_reg & (USB_CHEP_REG_MASK & (~USB_CH_ERRTX) & (~USB_CH_VTTX))) | + (USB_CH_VTRX | USB_CH_ERRRX); + + HCD_SET_CHANNEL(hhcd->Instance, phy_chnum, epch_reg); + } + } + } + + return; + } + + /* Wakeup Flag Detected */ + if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP) + { + if (hhcd->HostState == HCD_HCD_STATE_SUSPEND) + { + /* Set The L2Resume bit */ + hhcd->Instance->CNTR |= USB_CNTR_L2RES; + + /* Clear the wake-up flag */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_ISTR_WKUP); + + /* Update the USB Software state machine */ + HAL_HCD_ResumeCallback(hhcd); + hhcd->HostState = HCD_HCD_STATE_RESUME; + } + else + { + /* Clear the wake-up flag */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_ISTR_WKUP); + } + + return; + } + + /* Global Error Flag Detected */ + if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR) + { + __HAL_HCD_CLEAR_FLAG(hhcd, USB_ISTR_ERR); + + return; + } + + /* PMA Overrun detected */ + if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR) + { + __HAL_HCD_CLEAR_FLAG(hhcd, USB_ISTR_PMAOVR); + + return; + } + + /* Suspend Detected */ + if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP) + { + /* Set HAL State to Suspend */ + hhcd->HostState = HCD_HCD_STATE_SUSPEND; + + /* Force low-power mode in the macrocell */ + hhcd->Instance->CNTR |= USB_CNTR_SUSPEN; + + /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_ISTR_SUSP); + + /* Call suspend Callback */ + HAL_HCD_SuspendCallback(hhcd); + + return; + } + + /* Start Of Frame Detected */ + if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF) + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->SOFCallback(hhcd); +#else + HAL_HCD_SOF_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + __HAL_HCD_CLEAR_FLAG(hhcd, USB_ISTR_SOF); + + /* when first SOF is detected after USB_RESET is asserted */ + if (hhcd->HostState == HCD_HCD_STATE_RESETED) + { + /* HAL State */ + hhcd->HostState = HCD_HCD_STATE_RUN; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->PortEnabledCallback(hhcd); +#else + HAL_HCD_PortEnabled_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + + return; + } +} + +/** + * @brief SOF callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_HCD_SOF_Callback could be implemented in the user file + */ +} + +/** + * @brief Connection Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_HCD_Connect_Callback could be implemented in the user file + */ +} + +/** + * @brief Disconnection Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} +/** + * @brief Port Enabled Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} +/** + * @brief Port Disabled Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Notify URB state change callback. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @param urb_state + * This parameter can be one of these values: + * URB_IDLE/ + * URB_DONE/ + * URB_NOTREADY/ + * URB_NYET/ + * URB_ERROR/ + * URB_STALL/ + * @retval None + */ +__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, + uint8_t chnum, HCD_URBStateTypeDef urb_state) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + UNUSED(chnum); + UNUSED(urb_state); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file + */ +} +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User USB HCD Callback + * To be used instead of the weak predefined callback + * @param hhcd USB HCD handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID + * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID + * @arg @ref HAL_HCD_DISCONNECT_CB_ID HCD Disconnect callback ID + * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID + * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID + * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID, + pHCD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_HCD_SOF_CB_ID : + hhcd->SOFCallback = pCallback; + break; + + case HAL_HCD_CONNECT_CB_ID : + hhcd->ConnectCallback = pCallback; + break; + + case HAL_HCD_DISCONNECT_CB_ID : + hhcd->DisconnectCallback = pCallback; + break; + + case HAL_HCD_PORT_ENABLED_CB_ID : + hhcd->PortEnabledCallback = pCallback; + break; + + case HAL_HCD_PORT_DISABLED_CB_ID : + hhcd->PortDisabledCallback = pCallback; + break; + + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = pCallback; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hhcd->State == HAL_HCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = pCallback; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + return status; +} + +/** + * @brief Unregister an USB HCD Callback + * USB HCD callback is redirected to the weak predefined callback + * @param hhcd USB HCD handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID + * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID + * @arg @ref HAL_HCD_DISCONNECT_CB_ID DRD HCD Disconnect callback ID + * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID + * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID + * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hhcd); + + /* Setup Legacy weak Callbacks */ + if (hhcd->State == HAL_HCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_HCD_SOF_CB_ID : + hhcd->SOFCallback = HAL_HCD_SOF_Callback; + break; + + case HAL_HCD_CONNECT_CB_ID : + hhcd->ConnectCallback = HAL_HCD_Connect_Callback; + break; + + case HAL_HCD_DISCONNECT_CB_ID : + hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback; + break; + + case HAL_HCD_PORT_ENABLED_CB_ID : + hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback; + break; + + case HAL_HCD_PORT_DISABLED_CB_ID : + hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback; + break; + + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = HAL_HCD_MspInit; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hhcd->State == HAL_HCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = HAL_HCD_MspInit; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + return status; +} + +/** + * @brief Register USB HCD Host Channel Notify URB Change Callback + * To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback + * @param hhcd HCD handle + * @param pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, + pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + hhcd->HC_NotifyURBChangeCallback = pCallback; + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief Unregister the USB HCD Host Channel Notify URB Change Callback + * USB HCD Host Channel Notify URB Change Callback is redirected + * to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback */ + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + + return status; +} +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions + * @brief Management functions + * +@verbatim +=============================================================================== +##### Peripheral Control functions ##### +=============================================================================== +[..] +This subsection provides a set of functions allowing to control the HCD data +transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) +{ + __HAL_LOCK(hhcd); + + /*Set the PullDown on the PHY */ + hhcd->Instance->BCDR |= USB_BCDR_DPPD; + + /* Clear Reset */ + hhcd->Instance->CNTR &= ~USB_CNTR_USBRST; + + /*Remove PowerDown */ + hhcd->Instance->CNTR &= ~USB_CNTR_PDWN; + + __HAL_UNLOCK(hhcd); + + return HAL_OK; +} + +/** + * @brief Stop the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) +{ + __HAL_LOCK(hhcd); + /*Stop the Host IP: setting powerdown */ + (void)USB_StopHost(hhcd->Instance); + + /* clear all allocated virtual channel */ + HAL_HCD_ClearPhyChannel(hhcd); + + /* Reset the PMA current pointer */ + (void)HAL_HCD_PMAReset(hhcd); + + /* reset Ep0 Pma allocation state */ + hhcd->ep0_PmaAllocState = 0U; + + __HAL_UNLOCK(hhcd); + return HAL_OK; +} + +/** + * @brief Put the Device in suspend mode + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Suspend(HCD_HandleTypeDef *hhcd) +{ + __IO uint32_t count = 0U; + + /* Set Suspend Mode */ + hhcd->Instance->CNTR |= USB_CNTR_SUSPEN; + + /* wait for Suspend Ready */ + while ((hhcd->Instance->CNTR & USB_CNTR_SUSPRDY) == 0U) + { + if (++count > 0xFFFFFFU) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Resume host port + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Resume(HCD_HandleTypeDef *hhcd) +{ + /* Set Resume bit */ + hhcd->Instance->CNTR |= USB_CNTR_L2RES; + + return HAL_OK; +} + +/** + * @brief Reset the host port. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) +{ + __HAL_LOCK(hhcd); + + /* Reset the USB Port by inserting an SE0 on the bus */ + (void)USB_ResetPort(hhcd->Instance); + + if (hhcd->HostState == HCD_HCD_STATE_CONNECTED) + { + hhcd->HostState = HCD_HCD_STATE_RESETED; + } + __HAL_UNLOCK(hhcd); + + return HAL_OK; +} + +/** + * @brief Resme the host port. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_ResumePort(HCD_HandleTypeDef *hhcd) +{ + /* Set Resume bit */ + hhcd->Instance->CNTR |= USB_CNTR_L2RES; + HAL_Delay(30U); + + /* Clear Resume bit */ + hhcd->Instance->CNTR &= ~USB_CNTR_L2RES; + + return HAL_OK; +} + + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim +=============================================================================== +##### Peripheral State functions ##### +=============================================================================== +[..] +This subsection permits to get in run-time the status of the peripheral +and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the HCD handle state. + * @param hhcd HCD handle + * @retval HAL state + */ +HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd) +{ + return hhcd->State; +} + +/** + * @brief Return URB state for a channel. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval URB state. + * This parameter can be one of these values: + * URB_IDLE/ + * URB_DONE/ + * URB_NOTREADY/ + * URB_NYET/ + * URB_ERROR/ + * URB_STALL + */ +HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].urb_state; +} + + +/** + * @brief Return the last host transfer size. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval last transfer size in byte + */ +uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].xfer_count; +} + +/** + * @brief Return the Host Channel state. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval Host channel state + * This parameter can be one of these values: + * HC_IDLE/ + * HC_XFRC/ + * HC_HALTED/ + * HC_NYET/ + * HC_NAK/ + * HC_STALL/ + * HC_XACTERR/ + * HC_BBLERR/ + * HC_DATATGLERR + */ +HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].state; +} + +/** + * @brief Return the current Host frame number. + * @param hhcd HCD handle + * @retval Current Host frame number + */ +uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) +{ + return (USB_GetCurrentFrame(hhcd->Instance)); +} + +/** + * @brief Return the Host enumeration speed. + * @param hhcd HCD handle + * @retval speed : Device speed after Host enumeration + * This parameter can be one of these values: + * @arg HCD_DEVICE_SPEED_HIGH: High speed mode + * @arg HCD_DEVICE_SPEED_FULL: Full speed mode + * @arg HCD_DEVICE_SPEED_LOW: Low speed mode + */ +uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) +{ + return (USB_GetHostSpeed(hhcd->Instance)); +} + +/** + * @brief Set host channel Hub Information. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param addr Hub address + * @param PortNbr Hub port number + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t addr, uint8_t PortNbr) +{ + hhcd->hc[ch_num].hub_addr = addr; + hhcd->hc[ch_num].hub_port_nbr = PortNbr; + + return HAL_OK; +} + + +/** + * @brief Clear host channel hub information. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + hhcd->hc[ch_num].hub_addr = 0U; + hhcd->hc[ch_num].hub_port_nbr = 0U; + + return HAL_OK; +} + +#if (USE_USB_DOUBLE_BUFFER == 1U) +/** + * @brief Handle Host Channel OUT Double Buffer Bulk requests. + * @param hhcd HCD handle + * @param ch_num Channel number This parameter can be a value from 1 to 15 + * @param phy_chnum Physical Channel number [0..7] + * @param regvalue contain Snapshot of the EPCHn register when ISR is detected + * @retval none + */ +static void HCD_HC_OUT_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t phy_chnum, uint32_t regvalue) +{ + uint16_t data_xfr; + uint16_t len; + + /* Send Buffer0 */ + if ((regvalue & USB_CH_DTOG_TX) != 0U) + { + data_xfr = (uint16_t)(((USB_DRD_PMA_BUFF + phy_chnum)->TXBD & 0x03FF0000U) >> 16U); + + if (hhcd->hc[ch_num & 0xFU].xfer_len >= data_xfr) + { + hhcd->hc[ch_num & 0xFU].xfer_len -= data_xfr; + } + else + { + hhcd->hc[ch_num & 0xFU].xfer_len = 0U; + } + + /* Transfer no yet finished only one packet of mps is transferred and ACKed from device */ + if (hhcd->hc[ch_num & 0xFU].xfer_len != 0U) + { + /* manage multiple Xfer */ + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + + /* check if we need to free user buffer */ + if ((regvalue & USB_CH_DTOG_RX) != 0U) + { + /* Toggle SwBuff */ + HCD_CLEAR_TX_DTOG(hhcd->Instance, phy_chnum); + HCD_CLEAR_RX_DTOG(hhcd->Instance, phy_chnum); + HCD_TX_DTOG(hhcd->Instance, phy_chnum); + } + + /* hhcd->hc[ch_num&0xFU].xfer_len_db==0 ==> when all data are written in the PMA to yet transferred */ + if (hhcd->hc[ch_num & 0xFU].xfer_len_db > 0U) /* Still data to fill in the buffer */ + { + hhcd->hc[ch_num & 0xFU].xfer_buff += data_xfr; + + /* calculate len of new buffer to fill */ + if (hhcd->hc[ch_num & 0xFU].xfer_len_db > hhcd->hc[ch_num & 0xFU].max_packet) + { + len = (uint16_t)hhcd->hc[ch_num & 0xFU].max_packet; + hhcd->hc[ch_num & 0xFU].xfer_len_db -= len; + } + else + { + len = (uint16_t)hhcd->hc[ch_num & 0xFU].xfer_len_db; + hhcd->hc[ch_num & 0xFU].xfer_len_db = 0U; /* end of fill buffer */ + } + + /* Write remaining data to Buffer0 */ + HCD_SET_CH_DBUF0_CNT(hhcd->Instance, phy_chnum, 1U, (uint16_t)len); + USB_WritePMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff, + hhcd->hc[ch_num & 0xFU].pmaaddr0, (uint16_t)len); + } + /* start a new transfer */ + HCD_SET_CH_TX_STATUS(hhcd->Instance, phy_chnum, USB_CH_TX_VALID); + } + else + { + /* Transfer complete state */ + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + hhcd->hc[ch_num & 0xFU].state = HC_XFRC; + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; + hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; + /* Close the Channel */ + HCD_SET_CH_TX_STATUS(hhcd->Instance, phy_chnum, USB_CH_TX_DIS); + } + } + else + { + /* Send Buffer1 */ + data_xfr = (uint16_t)(((USB_DRD_PMA_BUFF + phy_chnum)->RXBD & 0x03FF0000U) >> 16U); + + if (hhcd->hc[ch_num & 0xFU].xfer_len >= data_xfr) /* updated */ + { + hhcd->hc[ch_num & 0xFU].xfer_len -= data_xfr; + } + + /* Transfer no yet finished only one packet of mps is transferred and ACKed from device */ + if (hhcd->hc[ch_num & 0xFU].xfer_len != 0U) + { + /* manage multiple Xfer */ + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + + /* check if we need to free user buffer */ + if ((regvalue & USB_CH_DTOG_RX) == 0U) + { + /* Toggle SwBuff */ + HCD_CLEAR_TX_DTOG(hhcd->Instance, phy_chnum); + HCD_CLEAR_RX_DTOG(hhcd->Instance, phy_chnum); + HCD_RX_DTOG(hhcd->Instance, phy_chnum); + } + + /* hhcd->hc[ch_num&0xFU].xfer_len_db==0 ==> when all data are written in the PMA to yet transferred */ + if (hhcd->hc[ch_num & 0xFU].xfer_len_db > 0U) /* Still data to fill in the buffer */ + { + hhcd->hc[ch_num & 0xFU].xfer_buff += data_xfr; + + /* calculate len of new buffer to fill */ + if (hhcd->hc[ch_num & 0xFU].xfer_len_db > hhcd->hc[ch_num & 0xFU].max_packet) + { + len = hhcd->hc[ch_num & 0xFU].max_packet; + hhcd->hc[ch_num & 0xFU].xfer_len_db -= len; + } + else + { + len = (uint16_t)hhcd->hc[ch_num & 0xFU].xfer_len_db; + hhcd->hc[ch_num & 0xFU].xfer_len_db = 0U; /* end of fill buffer */ + } + + /* Write remaining data to Buffer0 */ + HCD_SET_CH_DBUF1_CNT(hhcd->Instance, phy_chnum, 1U, (uint16_t)len); + + USB_WritePMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff, + hhcd->hc[ch_num & 0xFU].pmaaddr1, (uint16_t)len); + } + + /* start a new transfer */ + HCD_SET_CH_TX_STATUS(hhcd->Instance, phy_chnum, USB_CH_TX_VALID); + } + else + { + /* Transfer complete state */ + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + hhcd->hc[ch_num & 0xFU].state = HC_XFRC; + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; + hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; + + /* Close the channel */ + HCD_SET_CH_TX_STATUS(hhcd->Instance, phy_chnum, USB_CH_TX_DIS); + } + } +} + + +/** + * @brief Handle Host Channel IN Double Buffer Bulk requests. + * @param hhcd HCD handle + * @param ch_num Channel number: This parameter can be a value from 1 to 15 + * @param phy_chnum Physical Channel number [0..7] + * @param regvalue contain Snapshot of the EPCHn register when ISR is detected + * @retval none + */ +static void HCD_HC_IN_BulkDb(HCD_HandleTypeDef *hhcd, + uint8_t ch_num, uint8_t phy_chnum, uint32_t regvalue) +{ + uint16_t received_bytes; + + /* Read from Buffer 0 */ + if ((regvalue & USB_CH_DTOG_RX) != 0U) + { + received_bytes = (uint16_t)HCD_GET_CH_DBUF0_CNT(hhcd->Instance, phy_chnum); + + if (hhcd->hc[ch_num & 0xFU].xfer_len <= received_bytes) + { + hhcd->hc[ch_num & 0xFU].xfer_len = 0U; + } + else + { + hhcd->hc[ch_num & 0xFU].xfer_len -= received_bytes; + } + + /* Check if we Need to free the other buffer for the IP */ + if ((hhcd->hc[ch_num & 0xFU].xfer_len != 0U) && ((regvalue & USB_CH_DTOG_TX) != 0U)) + { + /* Toggle SwBuff to Allow the IP to submit a new IN */ + HCD_FREE_USER_BUFFER(hhcd->Instance, phy_chnum, 0U); + } + + /* Read the byte from PMA to user Buffer(System Memory) */ + USB_ReadPMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff, + hhcd->hc[ch_num & 0xFU].pmaaddr0, (uint16_t)received_bytes); + } + else + { + /* Read from Buffer 1 */ + received_bytes = (uint16_t) HCD_GET_CH_DBUF1_CNT(hhcd->Instance, phy_chnum); + + if (hhcd->hc[ch_num & 0xFU].xfer_len <= received_bytes) + { + hhcd->hc[ch_num & 0xFU].xfer_len = 0U; + } + else + { + hhcd->hc[ch_num & 0xFU].xfer_len -= received_bytes; + } + + /* Check if we Need to free the other buffer for the IP */ + if ((hhcd->hc[ch_num & 0xFU].xfer_len != 0U) && ((regvalue & USB_CH_DTOG_TX) == 0U)) + { + /* Toggle SwBuff */ + HCD_FREE_USER_BUFFER(hhcd->Instance, phy_chnum, 0U); + } + + /* Read the byte from PMA to user Buffer(System Memory) */ + USB_ReadPMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff, + hhcd->hc[ch_num & 0xFU].pmaaddr1, (uint16_t)received_bytes); + } + + /* update the global number of all received bytes */ + hhcd->hc[ch_num & 0xFU].xfer_count += received_bytes; + + /* Transfer complete state */ + hhcd->hc[ch_num & 0xFU].state = HC_ACK; + hhcd->hc[ch_num & 0xFU].ErrCnt = 0U; + + if ((hhcd->hc[ch_num & 0xFU].xfer_len == 0U) || + ((received_bytes < hhcd->hc[ch_num & 0xFU].max_packet))) + { + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; + hhcd->hc[ch_num & 0xFU].state = HC_XFRC; + + /* disable channel */ + HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_DIS); + } + else + { + hhcd->hc[ch_num & 0xFU].xfer_buff += received_bytes; + + /* Reactivate the Channel Submit an other URB since the Transfer is not yet completed */ + HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_STRX); + } +} +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + +/** + * @brief Handle Host Channel IN Isochronous Transaction + * @param hhcd HCD handle + * @param ch_num Channel number: This parameter can be a value from 1 to 15 + * @param phy_chnum Physical Channel number [0..7] + * @param regvalue contain Snapshot of the EPCHn register when ISR is detected + * @retval none + */ +static void inline HCD_HC_IN_ISO(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t phy_chnum, uint32_t regvalue) +{ + /* Check if Double buffer isochronous */ + if ((regvalue & USB_CH_KIND) != 0U) + { + /* Get Data IN Packet */ + hhcd->hc[ch_num & 0xFU].xfer_count = HCD_GET_CH_RX_CNT(hhcd->Instance, phy_chnum); + if (hhcd->hc[ch_num & 0xFU].xfer_count != 0U) + { + USB_ReadPMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff, + hhcd->hc[ch_num & 0xFU].pmaadress, + (uint16_t)hhcd->hc[ch_num & 0xFU].xfer_count); + + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; + } + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + else /* double buffer isochronous */ + { + /* Read from Buffer0 */ + if ((regvalue & USB_CH_DTOG_RX) != 0U) + { + /* Get number of Received byte in buffer0 */ + hhcd->hc[ch_num & 0xFU].xfer_count = HCD_GET_CH_DBUF0_CNT(hhcd->Instance, phy_chnum); + + if (hhcd->hc[ch_num & 0xFU].xfer_count != 0U) + { + /* Read from Buffer0 */ + USB_ReadPMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff, + hhcd->hc[ch_num & 0xFU].pmaaddr0, + (uint16_t)hhcd->hc[ch_num & 0xFU].xfer_count); + + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; + } + } + else + { + /* Get number of Received byte in buffer1 */ + hhcd->hc[ch_num & 0xFU].xfer_count = HCD_GET_CH_DBUF1_CNT(hhcd->Instance, phy_chnum); + + if (hhcd->hc[ch_num & 0xFU].xfer_count != 0U) + { + /* Read from Buffer1 */ + USB_ReadPMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff, + hhcd->hc[ch_num & 0xFU].pmaaddr1, + (uint16_t)hhcd->hc[ch_num & 0xFU].xfer_count); + + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; + } + } + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + /* Transfer complete state */ + hhcd->hc[ch_num & 0xFU].state = HC_XFRC; + + /* Clear VTRX */ + HCD_CLEAR_RX_CH_CTR(hhcd->Instance, phy_chnum); +} + +/** + * @brief Handle Host Channel IN interrupt requests. + * @param hhcd HCD handle + * @param ch_num Channel number + * This parameter can be a value from 1 to 15 + * @retval none + */ +static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + uint16_t received_bytes; + uint8_t phy_chnum = (uint8_t)__HAL_HCD_GET_CHNUM(hhcd); + + /*Take a Flag snapshot from the CHEP register, due to STRX bits are used for both control and status */ + uint32_t ch_reg = HCD_GET_CHANNEL(hhcd->Instance, phy_chnum); + + /* Manage Correct Transaction */ + if ((ch_reg & USB_CH_ERRRX) == 0U) + { + /* Isochronous Channel */ + if ((ch_reg & USB_CH_UTYPE) == USB_EP_ISOCHRONOUS) + { + HCD_HC_IN_ISO(hhcd, ch_num, phy_chnum, ch_reg); + } + else + { + /* manage ACK response single buffer */ + if (((ch_reg) & USB_CH_RX_STRX) == USB_CH_RX_ACK_SBUF) + { + /* Get Control Data OUT Packet */ + received_bytes = (uint16_t)HCD_GET_CH_RX_CNT(hhcd->Instance, phy_chnum); + + /* Read the byte from PMA to user Buffer(System Memory) */ + USB_ReadPMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff, + hhcd->hc[ch_num & 0xFU].pmaadress, (uint16_t)received_bytes); + + /* update the global number of all received bytes */ + hhcd->hc[ch_num & 0xFU].xfer_count += received_bytes; + + /* Transfer complete state */ + hhcd->hc[ch_num & 0xFU].state = HC_ACK; + hhcd->hc[ch_num & 0xFU].ErrCnt = 0U; + + if (hhcd->hc[ch_num & 0xFU].xfer_len <= received_bytes) + { + hhcd->hc[ch_num & 0xFU].xfer_len = 0U; + } + else + { + hhcd->hc[ch_num & 0xFU].xfer_len -= received_bytes; + } + + if ((hhcd->hc[ch_num & 0xFU].xfer_len == 0U) || + ((received_bytes < hhcd->hc[ch_num & 0xFU].max_packet))) + { + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; + hhcd->hc[ch_num & 0xFU].state = HC_XFRC; + } + else + { + hhcd->hc[ch_num & 0xFU].xfer_buff += received_bytes; + + /* Reactivate the Channel to Submit another URB since the Transfer is not yet completed */ + HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_STRX); + } + + if ((hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_BULK) || + (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR)) + { + hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; + } + } + /* manage NACK Response */ + else if (((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_NAK) + && (hhcd->hc[ch_num & 0xFU].urb_state != URB_DONE)) + { + hhcd->hc[ch_num & 0xFU].urb_state = URB_NOTREADY; + hhcd->hc[ch_num & 0xFU].ErrCnt = 0U; + hhcd->hc[ch_num & 0xFU].state = HC_NAK; + } + /* manage STALL Response */ + else if ((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_STALL) + { + (void)HAL_HCD_HC_Halt(hhcd, ch_num); + hhcd->hc[ch_num & 0xFU].state = HC_STALL; + hhcd->hc[ch_num & 0xFU].urb_state = URB_STALL; + + /* Close the channel */ + HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_DIS); + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + /* Double Buffer Management in case of Bulk Transaction */ + else if (((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_ACK_DBUF) + && ((ch_reg & USB_CH_KIND) != 0U)) + { + /* Bulk IN Double Buffer ISR */ + HCD_HC_IN_BulkDb(hhcd, ch_num, phy_chnum, ch_reg); + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + else + { + /*....*/ + /* not defined state: STRX=11 in single buffer no iso is not defined */ + } + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, ch_num, hhcd->hc[ch_num & 0xFU].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, ch_num, hhcd->hc[ch_num & 0xFU].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + /*Clear VTRX */ + HCD_CLEAR_RX_CH_CTR(hhcd->Instance, phy_chnum); + } + } + else /* Error detected during last transaction */ + { + /* Set URB Error State */ + hhcd->hc[ch_num & 0xFU].urb_state = URB_NOTREADY; + hhcd->hc[ch_num & 0xFU].ErrCnt++; + hhcd->hc[ch_num & 0xFU].state = HC_XACTERR; + + /* Clear VTTRX & ERR_RX */ + HCD_CLEAR_RX_CH_ERR(hhcd->Instance, phy_chnum); + + /* Check Error number */ + if (hhcd->hc[ch_num & 0xFU].ErrCnt > 3U) + { + hhcd->hc[ch_num & 0xFU].urb_state = URB_ERROR; + HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_DIS); + + /* Clear pending err_tx */ + HCD_CLEAR_RX_CH_ERR(hhcd->Instance, phy_chnum); + } + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, ch_num, hhcd->hc[ch_num & 0xFU].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, ch_num, hhcd->hc[ch_num & 0xFU].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } +} + + +/** + * @brief Handle Host Channel OUT interrupt requests. + * @param hhcd HCD handle + * @param chnum Channel number + * This parameter can be a value from 1 to 15 + * @retval none + */ +static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + uint16_t data_xfr; + __IO uint32_t WregCh; + + /* Get Physical Channel number */ + uint32_t phy_chnum = (uint8_t)__HAL_HCD_GET_CHNUM(hhcd); + + /* Take a Flag snapshot from the CHEP register, due to STRX bits are used for both control &status */ + uint32_t ch_reg = *(__IO uint32_t *)(&(hhcd->Instance->CHEP0R) + phy_chnum); + + /*------ Manage Correct Transaction ------*/ + if ((ch_reg & USB_CH_ERRTX) == 0U) + { + /* Handle Isochronous channel */ + if ((ch_reg & USB_CH_UTYPE) == USB_EP_ISOCHRONOUS) + { + /* correct transaction */ + if ((hhcd->Instance->ISTR & USB_ISTR_ERR) == 0U) + { + /* Double buffer isochronous out */ + if ((ch_reg & USB_CH_KIND) != 0U) + { + HCD_SET_CH_TX_CNT(hhcd->Instance, phy_chnum, 0U); + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + else /* double buffer isochronous out */ + { + /* Odd Transaction */ + if ((ch_reg & USB_CH_DTOG_TX) != 0U) + { + HCD_SET_CH_TX_CNT(hhcd->Instance, phy_chnum, 0U); + } + /* Even Transaction */ + else + { + HCD_SET_CH_RX_CNT(hhcd->Instance, phy_chnum, 0U); + } + + USB_DRD_SET_CHEP_TX_STATUS(hhcd->Instance, phy_chnum, USB_CH_TX_DIS); + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + /* Transfer complete state */ + hhcd->hc[chnum & 0xFU].state = HC_XFRC; + hhcd->hc[chnum & 0xFU].urb_state = URB_DONE; + } + + /*Clear Correct Transfer */ + HCD_CLEAR_TX_CH_CTR(hhcd->Instance, phy_chnum); + + /*TX COMPLETE*/ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + } + else /* Manage all Non Isochronous Transaction */ + { + /* Check ACK response */ + if ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_ACK_SBUF) + { + data_xfr = (uint16_t)(((USB_DRD_PMA_BUFF + phy_chnum)->TXBD & 0x03FF0000U) >> 16U); + + if (hhcd->hc[chnum & 0xFU].xfer_len >= data_xfr) + { + hhcd->hc[chnum & 0xFU].xfer_len -= data_xfr; + } + else + { + hhcd->hc[chnum & 0xFU].xfer_len = 0U; + } + + /* Transfer no yet finished only one packet of mps is transferred and ACKed from device */ + if (hhcd->hc[chnum & 0xFU].xfer_len != 0U) + { + /* manage multiple Xfer */ + hhcd->hc[chnum & 0xFU].xfer_buff += data_xfr; + hhcd->hc[chnum & 0xFU].xfer_count += data_xfr; + + /* start a new transfer */ + (void) USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[chnum & 0xFU]); + } + else + { + /* Transfer complete */ + hhcd->hc[chnum & 0xFU].xfer_count += data_xfr; + hhcd->hc[chnum & 0xFU].state = HC_XFRC; + hhcd->hc[chnum & 0xFU].urb_state = URB_DONE; + + if ((hhcd->hc[chnum & 0xFU].ep_type == EP_TYPE_BULK) || + (hhcd->hc[chnum & 0xFU].ep_type == EP_TYPE_INTR)) + { + hhcd->hc[chnum & 0xFU].toggle_out ^= 1U; + } + } + } + /* Check NACK Response */ + else if (((ch_reg & USB_CHEP_NAK) == USB_CHEP_NAK) || + ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_NAK)) + { + /* Update Channel status */ + hhcd->hc[chnum & 0xFU].state = HC_NAK; + hhcd->hc[chnum & 0xFU].urb_state = URB_NOTREADY; + hhcd->hc[chnum & 0xFU].ErrCnt = 0U; + + /* Get Channel register value */ + WregCh = *(__IO uint32_t *)(&(hhcd->Instance->CHEP0R) + phy_chnum); + + /*clear NAK status*/ + WregCh &= ~USB_CHEP_NAK & USB_CHEP_REG_MASK; + + /* Update channel register Value */ + HCD_SET_CHANNEL(hhcd->Instance, phy_chnum, WregCh); + + if (hhcd->hc[chnum & 0xFU].doublebuffer == 0U) + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + } + /* Check STALL Response */ + else if ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_STALL) + { + (void) HAL_HCD_HC_Halt(hhcd, (uint8_t)chnum); + hhcd->hc[chnum & 0xFU].state = HC_STALL; + hhcd->hc[chnum & 0xFU].urb_state = URB_STALL; + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + /* Check double buffer ACK in case of bulk transaction */ + else if ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_ACK_DBUF) + { + /* Double buffer management Bulk Out */ + (void) HCD_HC_OUT_BulkDb(hhcd, chnum, (uint8_t)phy_chnum, ch_reg); + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + else + { + /*...*/ + } + + if ((ch_reg & USB_CH_TX_STTX) != USB_CH_TX_NAK) + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + + HCD_CLEAR_TX_CH_CTR(hhcd->Instance, phy_chnum); + } /* end no isochronous */ + } + /*------ Manage Transaction Error------*/ + else + { + hhcd->hc[chnum & 0xFU].ErrCnt++; + if (hhcd->hc[chnum & 0xFU].ErrCnt > 3U) + { + HCD_SET_CH_TX_STATUS(hhcd->Instance, phy_chnum, USB_CH_TX_DIS); + hhcd->hc[chnum & 0xFU].urb_state = URB_ERROR; + } + else + { + hhcd->hc[chnum & 0xFU].urb_state = URB_NOTREADY; + } + + hhcd->hc[chnum & 0xFU].state = HC_XACTERR; + + /*Clear ERR_TX*/ + HCD_CLEAR_TX_CH_ERR(hhcd->Instance, phy_chnum); + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } +} + + +/** + * @brief Handle Host Port interrupt requests. + * @param hhcd HCD handle + * @retval None + */ +static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + uint32_t FnrReg = hhcd->Instance->FNR; + uint32_t IstrReg = hhcd->Instance->ISTR; + + /* SE0 detected USB Disconnected state */ + if ((FnrReg & (USB_FNR_RXDP | USB_FNR_RXDM)) == 0U) + { + /* Host Port State */ + hhcd->HostState = HCD_HCD_STATE_DISCONNECTED; + + /* clear all allocated virtual channel */ + HAL_HCD_ClearPhyChannel(hhcd); + + /* Reset the PMA current pointer */ + (void)HAL_HCD_PMAReset(hhcd); + + /* reset Ep0 Pma allocation state */ + hhcd->ep0_PmaAllocState = 0U; + + /* Disconnection Callback */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->DisconnectCallback(hhcd); +#else + HAL_HCD_Disconnect_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + return; + } + + if ((hhcd->HostState == HCD_HCD_STATE_DISCONNECTED) != 0U) + { + /* J-state or K-state detected & LastState=Disconnected */ + if (((FnrReg & USB_FNR_RXDP) != 0U) || ((IstrReg & USB_ISTR_LS_DCONN) != 0U)) + { + hhcd->HostState = HCD_HCD_STATE_CONNECTED; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->ConnectCallback(hhcd); +#else + HAL_HCD_Connect_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + } + else + { + /* J-state or K-state detected & lastState=Connected: a Missed disconnection is detected */ + if (((FnrReg & USB_FNR_RXDP) != 0U) || ((IstrReg & USB_ISTR_LS_DCONN) != 0U)) + { + /* Host Port State */ + hhcd->HostState = HCD_HCD_STATE_DISCONNECTED; + + /* clear all allocated virtual channel */ + HAL_HCD_ClearPhyChannel(hhcd); + + /* Reset the PMA current pointer */ + (void)HAL_HCD_PMAReset(hhcd); + + /* reset Ep0 PMA allocation state */ + hhcd->ep0_PmaAllocState = 0U; + + /* Disconnection Callback */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->DisconnectCallback(hhcd); +#else + HAL_HCD_Disconnect_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + } +} + + +/** + * @brief Check if the ch_num are already reserved to a physical channel + * @param hhcd HCD handle + * @param ch_num Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +static uint8_t HAL_HCD_Check_usedChannel(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + uint8_t idx; + + /* Check if the logical channel are already opened */ + for (idx = 0U; idx < hhcd->Init.Host_channels; idx++) + { + if ((((hhcd->phy_chin_state[idx] & 0xF0U) >> 4U) == ((uint16_t)ch_num + 1U)) && + (hhcd->phy_chin_state[idx] != 0U)) + { + return (1U | (idx << 4U)); + } + + if ((((hhcd->phy_chout_state[idx] & 0xF0U) >> 4U) == ((uint16_t)ch_num + 1U)) && + (hhcd->phy_chout_state[idx] != 0U)) + { + return (1U | (idx << 4U)); + } + } + + return 0U; +} + + +/** + * @brief Get a Logical Channel number from physical Channel + * @param hhcd HCD handle + * @param phy_chnum + * This parameter can be a value from 1 to 15 + * @param dir Channel direction + * -0 OUT_Channel + * -1 IN_Channel + * @retval HAL status + */ +static uint8_t HAL_HCD_GetLogical_Channel(HCD_HandleTypeDef *hhcd, + uint8_t phy_chnum, uint8_t dir) +{ + /* Out Channel Direction */ + if (dir == 0U) + { + if (((hhcd->phy_chout_state[phy_chnum & 0x7U] & 0x00F0U) >> 4U) != 0U) + { + return ((uint8_t)((hhcd->phy_chout_state[phy_chnum & 0x7U] & 0x00F0U) >> 4U) - 1U); + } + else + { + /* Channel not registered Error */ + return HCD_LOGICAL_CH_NOT_OPENED; + } + } + /* IN Channel Direction */ + else + { + if (((hhcd->phy_chin_state[phy_chnum & 0x7U] & 0x00F0U) >> 4U) != 0U) + { + return ((uint8_t)((hhcd->phy_chin_state[phy_chnum & 0x7U] & 0x00F0U) >> 4U) - 1U); + } + else + { + /* Channel not registered Error */ + return HCD_LOGICAL_CH_NOT_OPENED; + } + } +} + + +/** + * @brief Get a free physical Channel number according to the direction + * @param hhcd HCD handle + * @param ch_num Channel number + * This parameter can be a value from 1 to 15 + * @param epnum Endpoint number + * This parameter can be a value from 1 to 15 + * @param ep_type Endpoint Type + * This parameter can be one of these values: + * EP_TYPE_CTRL Control type, + * EP_TYPE_ISOC Isochronous type, + * EP_TYPE_BULK Bulk type, + * EP_TYPE_INTR Interrupt type + * @retval if physical channel is available return Phy_channel number + else return HCD_FREE_CH_NOT_FOUND + */ +static uint8_t HAL_HCD_Get_FreePhyChannel(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t epnum, uint8_t ep_type) +{ + uint8_t idx; + + if ((epnum & 0x7FU) == 0U) + { + idx = 0U; + + if (ch_num == 0U) + { + if (hhcd->phy_chin_state[idx] == 0U) + { + /* chin_state to store the ep_type to be used for the same channel in OUT direction + * adding + 1 to ep_type avoid starting with a 0 value. ep_type take by default (0/1/2/3) */ + hhcd->phy_chin_state[idx] = (((uint16_t)ch_num + 1U) << 4U) | + ((uint16_t)ep_type + 1U) | + (((uint16_t)epnum & 0x0FU) << 8U); + } + + if (hhcd->phy_chout_state[idx] == 0U) + { + /* chout_state will store the ep_type to be used for the same channel in IN direction + * adding + 1 to ep_type avoid starting with a 0 value. ep_type take by default (0/1/2/3) */ + hhcd->phy_chout_state[idx] = (((uint16_t)ch_num + 1U) << 4U) | + ((uint16_t)ep_type + 1U) | + (((uint16_t)epnum & 0x0FU) << 8U); + } + } + else + { + if ((epnum & 0x80U) != 0U) + { + if (((hhcd->phy_chin_state[idx] & 0xF0U) >> 4U) != ((uint16_t)ch_num + 1U)) + { + /* chin_state to store the ep_type to be used for the same channel in OUT direction + * adding + 1 to ep_type avoid starting with a 0 value. ep_type take by default (0/1/2/3) */ + hhcd->phy_chin_state[idx] = (((uint16_t)ch_num + 1U) << 4U) | + ((uint16_t)ep_type + 1U) | + (((uint16_t)epnum & 0x0FU) << 8U); + } + } + else + { + if (((hhcd->phy_chout_state[idx] & 0xF0U) >> 4U) != ((uint16_t)ch_num + 1U)) + { + /* chout_state will store the ep_type to be used for the same channel in IN direction + * adding + 1 to ep_type avoid starting with a 0 value. ep_type take by default (0/1/2/3) */ + hhcd->phy_chout_state[idx] = (((uint16_t)ch_num + 1U) << 4U) | + ((uint16_t)ep_type + 1U) | + (((uint16_t)epnum & 0x0FU) << 8U); + } + } + } + + return idx; + } + + if ((epnum & 0x80U) != 0U) + { + /* Find a new available physical in channel */ + for (idx = 1U; idx < hhcd->Init.Host_channels; idx++) + { + /* Check if the same epnum is allocated then allocate the same physical channel OUT for IN Logical Channel */ + if ((hhcd->phy_chin_state[idx] == 0U) && + ((((hhcd->phy_chout_state[idx] & 0x000FU) == ((uint16_t)ep_type + 1U)) && + (((hhcd->phy_chout_state[idx] & 0x0F00U) == ((uint16_t)epnum & 0x0FU)))) || + (hhcd->phy_chout_state[idx] == 0U))) + { + /* chin_state to store the ep_type to be used for the same channel in OUT direction + * adding + 1 to ep_type avoid starting with a 0 value. ep_type take by default (0/1/2/3) */ + hhcd->phy_chin_state[idx] = (((uint16_t)ch_num + 1U) << 4U) | + ((uint16_t)ep_type + 1U) | + (((uint16_t)epnum & 0x0FU) << 8U); + + return idx; + } + } + } + else + { + /* Find a new available physical out channel */ + for (idx = 1U; idx < hhcd->Init.Host_channels; idx++) + { + /* Check if the same epnum is allocated then allocate the same physical channel IN for OUT Logical Channel */ + if ((hhcd->phy_chout_state[idx] == 0U) && + ((((hhcd->phy_chin_state[idx] & 0x0FU) == ((uint16_t)ep_type + 1U)) && + ((hhcd->phy_chin_state[idx] & 0x0F00U) == ((uint16_t)epnum & 0x0FU))) || + (hhcd->phy_chin_state[idx] == 0U))) + { + /* chout_state will store the ep_type to be used for the same channel in IN direction + * adding + 1 to ep_type avoid starting with a 0 value. ep_type take by default (0/1/2/3) */ + hhcd->phy_chout_state[idx] = (((uint16_t)ch_num + 1U) << 4U) | + ((uint16_t)ep_type + 1U) | + (((uint16_t)epnum & 0x0FU) << 8U); + + return idx; + } + } + } + + /* in case of Error */ + return HCD_FREE_CH_NOT_FOUND; +} + +/** + * @brief Free All Channel allocation + * @param hhcd HCD handle + * @retval HAL status + */ +static void HAL_HCD_ClearPhyChannel(HCD_HandleTypeDef *hhcd) +{ + uint8_t idx; + + for (idx = 0U; idx < hhcd->Init.Host_channels; idx++) + { + /*Reset channel allocation value */ + hhcd->phy_chout_state[idx] = 0U; + hhcd->phy_chin_state[idx] = 0U; + } +} + +/*---------------------- PMA Allocation Section --------------------- */ +/* + __col31________________col0__ Column-- > + lin0 | entry31.|....... | entry0 | Line + |---------|---------|--------| | + line1| entry63.|....... | entry32| | + |---------|---------|--------| \|/ + | entry127|....... | entry64| + |---------|---------|--------| + | entry256|...... |entry128| + ---------------------------- + an allocation space of 64byte need 8 Free contiguous Entry in the Matrix + - a Free Entry is a bit with 0 Value/ a busy entry is a bit with 1 value. */ + +/** + * @brief Fetch in the PMA_LockupTable free space of number of mps byte + * @param hhcd Host instance + * @param mps Channel Max Packet Size + * @retval PMA_Address of the first free block containing mps byte + 0xFFFF in case of no space available + */ +static uint16_t HAL_HCD_GetFreePMA(HCD_HandleTypeDef *hhcd, uint16_t mps) +{ + uint32_t Entry; + uint32_t FreeBlocks = 0U; + uint8_t FirstFreeBlock_col = 0U; + uint8_t FirstFreeBlock_line = 0U; + uint8_t ColIndex; + uint16_t NbrReqBlocks; + uint16_t mps_t = mps; + + /* since PMA buffer descriptor RXBD allocate address according to BLSIZE, BLSIZE=1==> mps>64 + allocation in PMA is done in 32Bytes each entry */ + if ((mps_t > 64U) && ((mps_t % 32U) != 0U)) + { + /* Align the mps to 32byte block to match the allocation in PMA, + check Definition of allocation buffer memory in usb user spec */ + mps_t = (uint16_t)(((mps_t / 32U) + 1U) * 32U); + } + + /* calculate the number of block(8byte) to allocate */ + NbrReqBlocks = mps_t / 8U; + + /* check if we need remaining Block */ + if ((mps_t % 8U) != 0U) + { + NbrReqBlocks++; + } + + /* Look For NbrReqBlocks * Empty Block */ + for (uint8_t i = 0U; ((i < PMA_BLOCKS) && (FreeBlocks != NbrReqBlocks)); i++) + { + Entry = hhcd->PMALookupTable[i]; + + /* when parse is in progress, check the first col to look for a contiguous block */ + if ((FreeBlocks != 0U) && ((Entry & (uint32_t)1U) != 0U)) + { + FreeBlocks = 0U; + } + uint8_t j = 0U; + while ((j <= 31U) && (FreeBlocks != NbrReqBlocks)) + { + /* check if block j is free */ + if ((Entry & ((uint32_t)1U << j)) == 0U) + { + if (FreeBlocks == 0U) + { + FirstFreeBlock_col = j; + FirstFreeBlock_line = i; + FreeBlocks++; + } + j++; + + /* Parse Column PMALockTable */ + while ((j <= 31U) && ((Entry & ((uint32_t)1U << j)) == 0U) && (FreeBlocks < NbrReqBlocks)) + { + FreeBlocks++; + j++; + } + + /* Free contiguous Blocks not found */ + if (((FreeBlocks < NbrReqBlocks) && (j < 31U)) || + ((j == 31U) && ((Entry & ((uint32_t)1U << j)) != 0U))) + { + FreeBlocks = 0U; + } + } + j++; + } /* end for j */ + } /* end for i */ + + /* Free block found */ + if (FreeBlocks >= NbrReqBlocks) + { + ColIndex = FirstFreeBlock_col; + + for (uint8_t i = FirstFreeBlock_line; ((i < PMA_BLOCKS) && (FreeBlocks > 0U)); i++) + { + for (uint8_t j = ColIndex; j <= 31U; j++) + { + hhcd->PMALookupTable[i] |= ((uint32_t)1U << j); + if (--FreeBlocks == 0U) + { + break; + } + } + ColIndex = 0U; + } + + return (uint16_t)((FirstFreeBlock_line * (uint16_t)256U) + (FirstFreeBlock_col * (uint16_t)8U)); + } + else + { + return 0xFFFFU; + } +} + +/** + * @brief Allocate PMA buffer for Channel + * This API will fetch a free space + * @param hhcd Host instance + * @param ch_num Channel number + * @param ch_kind endpoint Kind + * USB_SNG_BUF Single Buffer used + * USB_DBL_BUF Double Buffer used + * @param mps Channel Max Packet Size + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint16_t ch_kind, uint16_t mps) +{ + uint16_t pma_addr0; +#if (USE_USB_DOUBLE_BUFFER == 1U) + uint16_t pma_addr1; /* used for double buffer mode if enabled */ +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + /* Host Channel */ + HCD_HCTypeDef *hc = &(hhcd->hc[ch_num]); + + /* Get a FreePMA Address */ + pma_addr0 = HAL_HCD_GetFreePMA(hhcd, mps); + + /* if there is no free space to allocate */ + if (pma_addr0 == 0xFFFFU) + { + return HAL_ERROR; + } + else + { + /* Here we check if the endpoint is single or double Buffer */ + if (ch_kind == HCD_SNG_BUF) + { + /* Single Buffer */ + hc->doublebuffer = 0U; + + if (hc->ep_num == 0U) + { + hhcd->ep0_PmaAllocState = ch_num; + hhcd->ep0_PmaAllocState |= (1U << 8); + } + + /* Configure the PMA */ + if (hc->ch_dir == CH_IN_DIR) + { + hc->pmaaddr1 = pma_addr0; + (USB_DRD_PMA_BUFF + hc->phy_ch_num)->RXBD = hc->pmaaddr1; + + if (hc->ep_num == 0U) + { + hhcd->ep0_PmaAllocState |= (CH_IN_DIR << 4); + } + } + else + { + hc->pmaaddr0 = pma_addr0; + (USB_DRD_PMA_BUFF + hc->phy_ch_num)->TXBD = hc->pmaaddr0; + } + + /* Set the PmaAddress */ + hc->pmaadress = pma_addr0; + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + else /* USB_DBL_BUF */ + { + /* Double Buffer Endpoint */ + hc->doublebuffer = 1U; + + /* Get a FreePMA Address for buffer 2 */ + pma_addr1 = HAL_HCD_GetFreePMA(hhcd, mps); + + if (pma_addr1 == 0xFFFFU) + { + /* Free the first buffer */ + (void)HAL_HCD_PMAFree(hhcd, pma_addr0, mps); + return HAL_ERROR; + } + else + { + /* Configure the PMA */ + hc->pmaaddr0 = (uint16_t)(pma_addr0); + hc->pmaaddr1 = (uint16_t)(pma_addr1); + + /* Set Buffer0 pma address */ + (USB_DRD_PMA_BUFF + hc->phy_ch_num)->TXBD = pma_addr0; + + /* Set Buffer1 pma address */ + (USB_DRD_PMA_BUFF + hc->phy_ch_num)->RXBD = pma_addr1; + + /* Used for Bulk DB MPS < 64bytes */ + if (hc->ch_dir == CH_IN_DIR) + { + hc->pmaadress = hc->pmaaddr1; + } + else + { + hc->pmaadress = hc->pmaaddr0; + } + } + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + } + + return HAL_OK; +} + +/** + * @brief PMA De-Allocation for Channel Free the reserved block in the PMA-LookupTable + * @param hhcd Host instance + * @param ch_num Channel number + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_PMADeAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + HAL_StatusTypeDef status; + +#if (USE_USB_DOUBLE_BUFFER == 1U) + uint8_t Err = 0U; +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + /* Host Channel */ + HCD_HCTypeDef *hc = &(hhcd->hc[ch_num]); + + /* Single Buffer */ + if (hc->doublebuffer == 0U) + { + status = HAL_HCD_PMAFree(hhcd, hc->pmaadress, hc->max_packet); + } + else /* Double buffer */ + { +#if (USE_USB_DOUBLE_BUFFER == 1U) + status = HAL_HCD_PMAFree(hhcd, hc->pmaaddr0, hc->max_packet); + if (status != HAL_OK) + { + Err++; + } + + status = HAL_HCD_PMAFree(hhcd, hc->pmaaddr1, hc->max_packet); + if (status != HAL_OK) + { + Err++; + } + + if (Err != 0U) + { + return HAL_ERROR; + } +#else + status = HAL_ERROR; +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + } + + return status; +} + + +/** + * @brief PMA Reset + * @param hhcd Host instance + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd) +{ + /* Reset All PMA Entry */ + for (uint8_t i = 0U; i < PMA_BLOCKS; i++) + { + hhcd->PMALookupTable[i] = 0U; + } + + /* Allocate a Space for buffer descriptor table depending on the Host channel number */ + for (uint8_t i = 0U; i < hhcd->Init.Host_channels; i++) + { + hhcd->PMALookupTable[0] |= ((uint32_t)1U << i); + } + + return HAL_OK; +} + +/** + * @brief PMA Free + * @param hhcd Host instance + * @param pma_base PMA base offset stored in hhcd->hc.pmaaddr + * @param mps Max Packet Size + * @retval HAL status + */ +static HAL_StatusTypeDef HAL_HCD_PMAFree(HCD_HandleTypeDef *hhcd, uint32_t pma_base, uint16_t mps) +{ + uint32_t block_nbr; + uint8_t ColIndex; + uint8_t LineIndex; + uint16_t mps_t = mps; + + /* since PMA buffer descriptor RXBD allocate address according to BLSIZE, BLSIZE=1==> mps>64 + allocation in PMA is done in 32Bytes each entry */ + if ((mps_t > 64U) && ((mps_t % 32U) != 0U)) + { + /* Align the mps to 32byte block to match the allocation in PMA, + check Definition of allocation buffer memory in usb user spec */ + mps_t = (uint16_t)(((mps_t / 32U) + 1U) * 32U); + } + + /* Calculate the number of needed block to Free */ + if ((mps_t / 8U) != 0U) + { + block_nbr = ((uint32_t)mps_t / 8U); + + if ((mps_t % 8U) != 0U) + { + block_nbr++; + } + } + else + { + block_nbr = 1U; + } + + /* Decode Col/Line of PMA_Base position in the PMA_LookupTable */ + if (pma_base > 256U) + { + LineIndex = (uint8_t)(pma_base / 256U); + ColIndex = (uint8_t)((pma_base - ((uint32_t)LineIndex * 256U)) / 8U); + } + else + { + LineIndex = 0U; + ColIndex = (uint8_t)(pma_base / 8U); + } + + /* Reset the corresponding bit in the lookupTable */ + for (uint8_t i = LineIndex; ((i < PMA_BLOCKS) && (block_nbr > 0U)); i++) + { + for (uint8_t j = ColIndex; j <= 31U; j++) + { + /* Check if the block is not already reserved or it was already closed */ + if ((hhcd->PMALookupTable[i] & ((uint32_t)1U << j)) == 0U) + { + return HAL_ERROR; + } + /* Free the reserved block by resetting the corresponding bit */ + hhcd->PMALookupTable[i] &= ~(1U << j); + + if (--block_nbr == 0U) + { + break; + } + } + ColIndex = 0U; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_DRD_FS) */ #endif /* HAL_HCD_MODULE_ENABLED */ /** diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hcd.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hcd.h index 7f87724b77f..25cc14c72b1 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hcd.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_hcd.h @@ -27,7 +27,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32u5xx_ll_usb.h" -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) /** @addtogroup STM32U5xx_HAL_Driver * @{ */ @@ -53,11 +53,35 @@ typedef enum HAL_HCD_STATE_TIMEOUT = 0x04 } HCD_StateTypeDef; +#if defined (USB_DRD_FS) +typedef USB_DRD_TypeDef HCD_TypeDef; +typedef USB_DRD_CfgTypeDef HCD_InitTypeDef; +typedef USB_DRD_HCTypeDef HCD_HCTypeDef; +typedef USB_DRD_URBStateTypeDef HCD_URBStateTypeDef; +typedef USB_DRD_HCStateTypeDef HCD_HCStateTypeDef; +#else typedef USB_OTG_GlobalTypeDef HCD_TypeDef; typedef USB_OTG_CfgTypeDef HCD_InitTypeDef; typedef USB_OTG_HCTypeDef HCD_HCTypeDef; typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef; typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef; +#endif /* defined (USB_DRD_FS) */ +#if defined (USB_DRD_FS) +typedef enum +{ + HCD_HCD_STATE_DISCONNECTED = 0x00U, + HCD_HCD_STATE_CONNECTED = 0x01U, + HCD_HCD_STATE_RESETED = 0x02U, + HCD_HCD_STATE_RUN = 0x03U, + HCD_HCD_STATE_SUSPEND = 0x04U, + HCD_HCD_STATE_RESUME = 0x05U, +} HCD_HostStateTypeDef; + +/* PMA lookup Table size depending on PMA Size + * 8Bytes each Block 32Bit in each word + */ +#define PMA_BLOCKS ((USB_DRD_PMA_SIZE) / (8U * 32U)) +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -74,6 +98,13 @@ typedef struct HCD_TypeDef *Instance; /*!< Register base address */ HCD_InitTypeDef Init; /*!< HCD required parameters */ HCD_HCTypeDef hc[16]; /*!< Host channels parameters */ +#if defined (USB_DRD_FS) + uint32_t ep0_PmaAllocState; /*!< EP0 PMA allocation State (allocated, virtual Ch, EP0 direction) */ + uint16_t phy_chin_state[8]; /*!< Physical Channel in State (Used/Free) */ + uint16_t phy_chout_state[8]; /*!< Physical Channel out State (Used/Free)*/ + uint32_t PMALookupTable[PMA_BLOCKS]; /*PMA LookUp Table */ + HCD_HostStateTypeDef HostState; /*!< USB current state DICONNECT/CONNECT/RUN/SUSPEND/RESUME */ +#endif /* defined (USB_DRD_FS) */ HAL_LockTypeDef Lock; /*!< HCD peripheral status */ __IO HCD_StateTypeDef State; /*!< HCD communication state */ __IO uint32_t ErrorCode; /*!< HCD Error code */ @@ -159,14 +190,29 @@ typedef struct #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\ & (__INTERRUPT__)) == (__INTERRUPT__)) +#if defined (USB_DRD_FS) +#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__)) +#else +#define __HAL_HCD_GET_CH_FLAG(__HANDLE__, __chnum__, __INTERRUPT__) \ + ((USB_ReadChInterrupts((__HANDLE__)->Instance, (__chnum__)) & (__INTERRUPT__)) == (__INTERRUPT__)) + #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) +#endif /* defined (USB_DRD_FS) */ #define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) +#if defined (USB_DRD_FS) +#define __HAL_HCD_GET_CHNUM(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_IDN) +#define __HAL_HCD_GET_CHDIR(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_DIR) +#else #define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) #define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) #define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) #define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) #define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) +#define __HAL_HCD_SET_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT) +#define __HAL_HCD_CLEAR_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_COMPLSPLT) +#define __HAL_HCD_CLEAR_HC_SSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_SPLITEN) +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -186,6 +232,9 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t speed, uint8_t ep_type, uint16_t mps); HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +#if defined (USB_DRD_FS) +HAL_StatusTypeDef HAL_HCD_HC_Close(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +#endif /* defined (USB_DRD_FS) */ void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); @@ -248,6 +297,11 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_n uint8_t token, uint8_t *pbuff, uint16_t length, uint8_t do_ping); +HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t addr, uint8_t PortNbr); + +HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num); + /* Non-Blocking mode: Interrupt */ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd); void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd); @@ -255,6 +309,10 @@ void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd); +#if defined (USB_DRD_FS) +void HAL_HCD_SuspendCallback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_ResumeCallback(HCD_HandleTypeDef *hhcd); +#endif /* defined (USB_DRD_FS) */ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state); /** @@ -268,6 +326,11 @@ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd); HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd); HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd); +#if defined (USB_DRD_FS) +HAL_StatusTypeDef HAL_HCD_Suspend(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_Resume(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_ResumePort(HCD_HandleTypeDef *hhcd); +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -283,9 +346,21 @@ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd); uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); +#if defined (USB_DRD_FS) +/* PMA Allocation functions **********************************************/ +/** @addtogroup PMA Allocation + * @{ + */ +HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint16_t ch_kind, uint16_t mps); + +HAL_StatusTypeDef HAL_HCD_PMADeAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd); + /** * @} */ +#endif /* defined (USB_DRD_FS) */ /** * @} @@ -295,6 +370,238 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); /** @defgroup HCD_Private_Macros HCD Private Macros * @{ */ +#if defined (USB_DRD_FS) +#define HCD_MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define HCD_MAX(a, b) (((a) > (b)) ? (a) : (b)) + +/** @defgroup HCD_LOGICAL_CHANNEL HCD Logical Channel + * @{ + */ +#define HCD_LOGICAL_CH_NOT_OPENED 0xFFU +#define HCD_FREE_CH_NOT_FOUND 0xFFU +/** + * @} + */ + +/** @defgroup HCD_ENDP_Kind HCD Endpoint Kind + * @{ + */ +#define HCD_SNG_BUF 0U +#define HCD_DBL_BUF 1U +/** + * @} + */ + +/* Set Channel */ +#define HCD_SET_CHANNEL USB_DRD_SET_CHEP + +/* Get Channel Register */ +#define HCD_GET_CHANNEL USB_DRD_GET_CHEP + + +/** + * @brief free buffer used from the application realizing it to the line + * toggles bit SW_BUF in the double buffered endpoint register + * @param USBx USB device. + * @param bChNum, bDir + * @retval None + */ +#define HCD_FREE_USER_BUFFER USB_DRD_FREE_USER_BUFFER + +/** + * @brief Set the Setup bit in the corresponding channel, when a Setup + transaction is needed. + * @param USBx USB device. + * @param bChNum + * @retval None + */ +#define HAC_SET_CH_TX_SETUP USB_DRD_CHEP_TX_SETUP + +/** + * @brief sets the status for tx transfer (bits STAT_TX[1:0]). + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define HCD_SET_CH_TX_STATUS USB_DRD_SET_CHEP_TX_STATUS + +/** + * @brief sets the status for rx transfer (bits STAT_TX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define HCD_SET_CH_RX_STATUS USB_DRD_SET_CHEP_RX_STATUS +/** + * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] + * /STAT_RX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval status + */ +#define HCD_GET_CH_TX_STATUS USB_DRD_GET_CHEP_TX_STATUS +#define HCD_GET_CH_RX_STATUS USB_DRD_GET_CHEP_RX_STATUS +/** + * @brief Sets/clears CH_KIND bit in the Channel register. + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define HCD_SET_CH_KIND USB_DRD_SET_CH_KIND +#define HCD_CLEAR_CH_KIND USB_DRD_CLEAR_CH_KIND +#define HCD_SET_BULK_CH_DBUF HCD_SET_CH_KIND +#define HCD_CLEAR_BULK_CH_DBUF HCD_CLEAR_CH_KIND + +/** + * @brief Clears bit ERR_RX in the Channel register + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define HCD_CLEAR_RX_CH_ERR USB_DRD_CLEAR_CHEP_RX_ERR + +/** + * @brief Clears bit ERR_TX in the Channel register + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define HCD_CLEAR_TX_CH_ERR USB_DRD_CLEAR_CHEP_TX_ERR +/** + * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define HCD_CLEAR_RX_CH_CTR USB_DRD_CLEAR_RX_CHEP_CTR +#define HCD_CLEAR_TX_CH_CTR USB_DRD_CLEAR_TX_CHEP_CTR + +/** + * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define HCD_RX_DTOG USB_DRD_RX_DTOG +#define HCD_TX_DTOG USB_DRD_TX_DTOG +/** + * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define HCD_CLEAR_RX_DTOG USB_DRD_CLEAR_RX_DTOG +#define HCD_CLEAR_TX_DTOG USB_DRD_CLEAR_TX_DTOG + +/** + * @brief sets counter for the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @param wCount Counter value. + * @retval None + */ +#define HCD_SET_CH_TX_CNT USB_DRD_SET_CHEP_TX_CNT +#define HCD_SET_CH_RX_CNT USB_DRD_SET_CHEP_RX_CNT + +/** + * @brief gets counter of the tx buffer. + * @param USBx USB peripheral instance register address. + * @param bChNum channel Number. + * @retval Counter value + */ +#define HCD_GET_CH_TX_CNT USB_DRD_GET_CHEP_TX_CNT + +/** + * @brief gets counter of the rx buffer. + * @param Instance USB peripheral instance register address. + * @param bChNum channel Number. + * @retval Counter value + */ +__STATIC_INLINE uint16_t HCD_GET_CH_RX_CNT(HCD_TypeDef *Instance, uint16_t bChNum) +{ + uint32_t HostCoreSpeed; + __IO uint32_t count = 10U; + + /* Get Host core Speed */ + HostCoreSpeed = USB_GetHostSpeed(Instance); + + /* Count depends on device LS */ + if (HostCoreSpeed == USB_DRD_SPEED_LS) + { + count = (70U * (HAL_RCC_GetHCLKFreq() / 1000000U)) / 100U; + } + + if (count > 15U) + { + count = HCD_MAX(10U, (count - 15U)); + } + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_RX_CNT((Instance), (bChNum)); +} + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @param bDir endpoint dir EP_DBUF_OUT = OUT + * EP_DBUF_IN = IN + * @param wCount: Counter value + * @retval None + */ +#define HCD_SET_CH_DBUF0_CNT USB_DRD_SET_CHEP_DBUF0_CNT +#define HCD_SET_CH_DBUF1_CNT USB_DRD_SET_CHEP_DBUF1_CNT +#define HCD_SET_CH_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT + + +/** + * @brief gets counter of the rx buffer0. + * @param Instance USB peripheral instance register address. + * @param bChNum channel Number. + * @retval Counter value + */ +__STATIC_INLINE uint16_t HCD_GET_CH_DBUF0_CNT(const HCD_TypeDef *Instance, uint16_t bChNum) +{ + UNUSED(Instance); + __IO uint32_t count = 10U; + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_DBUF0_CNT((Instance), (bChNum)); +} + +/** + * @brief gets counter of the rx buffer1. + * @param Instance USB peripheral instance register address. + * @param bChNum channel Number. + * @retval Counter value + */ +__STATIC_INLINE uint16_t HCD_GET_CH_DBUF1_CNT(const HCD_TypeDef *Instance, uint16_t bChNum) +{ + UNUSED(Instance); + __IO uint32_t count = 10U; + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bChNum)); +} +#endif /* defined (USB_DRD_FS) */ + /** * @} */ @@ -306,7 +613,10 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); /** * @} */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_i2c.c index 7476853770c..b90965bedce 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_i2c.c @@ -30,7 +30,7 @@ (#) Declare a I2C_HandleTypeDef handle structure, for example: I2C_HandleTypeDef hi2c; - (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API: + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: (##) Enable the I2Cx interface clock (##) I2C pins configuration (+++) Enable the clock for the I2C GPIOs @@ -39,7 +39,8 @@ (+++) Configure the I2Cx interrupt priority (+++) Enable the NVIC I2C IRQ Channel (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel + (+++) Declare a DMA_HandleTypeDef handle structure for + the transmit or receive channel (+++) Enable the DMAx interface clock using (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx channel @@ -50,49 +51,49 @@ (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. - (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API. + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. - (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady() + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : *** Polling mode IO operation *** ================================= [..] - (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit() - (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive() - (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit() - (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive() + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() *** Polling mode IO MEM operation *** ===================================== [..] - (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write() - (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read() + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() *** Interrupt mode IO operation *** =================================== [..] - (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT() - (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT() - (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT() - (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT() - (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() - (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. @@ -103,16 +104,16 @@ when a direction change during transfer [..] (+) A specific option field manage the different steps of a sequential transfer - (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: - (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential - mode + (+) Option field values are defined through I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in + no sequential mode (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition - (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start - condition, address and data to transfer without a final stop condition, an then permit - a call the same master sequential interface several times - (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT() - or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA()) + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with + start condition, address and data to transfer without a final stop condition, + an then permit a call the same master sequential interface several times + (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT() + or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA()) (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address and with new data to transfer if the direction change or manage only the new data to transfer @@ -122,115 +123,116 @@ transfer if no direction change and with a final stop condition in both cases (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition - after several call of the same master sequential - interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). - Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT - (option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) - or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) - or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) - or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). - Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence - permit to call the opposite interface Receive or Transmit without stopping - the communication and so generate a restart condition. + after several call of the same master sequential interface several times + (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME. + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or + Receive sequence permit to call the opposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential interface. Usage can, transfer several bytes one by one with a restart with slave address between - each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) - or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) - or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) - or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). + each bytes using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_FRAME then I2C_OTHER_FRAME. Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. (+) Different sequential I2C interfaces are listed below: (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using - @ref HAL_I2C_Master_Seq_Transmit_IT() or using @ref HAL_I2C_Master_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using - @ref HAL_I2C_Master_Seq_Receive_IT() or using @ref HAL_I2C_Master_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() - (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() - (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() - (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() - @ref HAL_I2C_DisableListen_IT() - (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can - add his own code to check the Address Match Code and the transmission direction request by master + HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() + HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction request by master (Write/Read). - (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback() + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_ListenCpltCallback() (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using - @ref HAL_I2C_Slave_Seq_Transmit_IT() - or using @ref HAL_I2C_Slave_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using - @ref HAL_I2C_Slave_Seq_Receive_IT() - or using @ref HAL_I2C_Slave_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() - (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() - (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. *** Interrupt mode IO MEM operation *** ======================================= [..] (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using - @ref HAL_I2C_Mem_Write_IT() - (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using - @ref HAL_I2C_Mem_Read_IT() - (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() *** DMA mode IO operation *** ============================== [..] (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Master_Transmit_DMA() - (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() (+) Receive in master mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Master_Receive_DMA() - (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Slave_Transmit_DMA() - (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Slave_Receive_DMA() - (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() - (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. *** DMA mode IO MEM operation *** ================================= [..] (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using - @ref HAL_I2C_Mem_Write_DMA() - (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using - @ref HAL_I2C_Mem_Read_DMA() - (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() *** I2C HAL driver macros list *** @@ -238,23 +240,23 @@ [..] Below the list of most used macros in I2C HAL driver. - (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral - (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral - (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode - (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not - (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag - (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt - (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt *** Callback registration *** ============================================= [..] The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() + Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() to register an interrupt callback. [..] - Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: + Function HAL_I2C_RegisterCallback() allows to register following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer. (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. @@ -269,11 +271,11 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback(). + For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback(). [..] - Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default + Use function HAL_I2C_UnRegisterCallback to reset a callback to the default weak function. - @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. @@ -288,24 +290,24 @@ (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. [..] - For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback(). + For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). [..] - By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET + By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). + examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when + reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() + If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, + in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() - or @ref HAL_I2C_Init() function. + using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() + or HAL_I2C_Init() function. [..] When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks @@ -349,46 +351,48 @@ #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ #define MAX_NBYTE_SIZE 255U -#define SLAVE_ADDR_SHIFT 7U -#define SLAVE_ADDR_MSK 0x06U +#define SLAVE_ADDR_SHIFT 7U +#define SLAVE_ADDR_MSK 0x06U /* Private define for @ref PreviousState usage */ -/*!< Mask State define, keep only RX and TX bits */ #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \ (uint32_t)HAL_I2C_STATE_BUSY_RX) & \ (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) -/*!< Default Value */ +/*!< Mask State define, keep only RX and TX bits */ #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) -/*!< Master Busy TX, combinaison of State LSB and Mode enum */ +/*!< Default Value */ #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ (uint32_t)HAL_I2C_MODE_MASTER)) -/*!< Master Busy RX, combinaison of State LSB and Mode enum */ +/*!< Master Busy TX, combinaison of State LSB and Mode enum */ #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ (uint32_t)HAL_I2C_MODE_MASTER)) -/*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +/*!< Master Busy RX, combinaison of State LSB and Mode enum */ #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ (uint32_t)HAL_I2C_MODE_SLAVE)) -/*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +/*!< Slave Busy TX, combinaison of State LSB and Mode enum */ #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ (uint32_t)HAL_I2C_MODE_SLAVE)) -/*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +/*!< Slave Busy RX, combinaison of State LSB and Mode enum */ #define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ (uint32_t)HAL_I2C_MODE_MEM)) -/*!< Memory Busy RX, combinaison of State LSB and Mode enum */ +/*!< Memory Busy TX, combinaison of State LSB and Mode enum */ #define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy RX, combinaison of State LSB and Mode enum */ /* Private define to centralize the enable/disable of Interrupts */ -#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ -#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ -#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */ -#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error and NACK treatment */ -#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */ -#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */ /* Private define Sequential Transfer Options default/reset value */ #define I2C_NO_OPTION_FRAME (0xFFFF0000U) @@ -396,13 +400,25 @@ * @} */ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup I2C_Private_Macro + * @{ + */ +#if defined(HAL_DMA_MODULE_ENABLED) +/* Macro to get remaining data to transfer on DMA side */ +#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) (__HAL_DMA_GET_COUNTER(__HANDLE__) + HAL_DMAEx_GetFifoLevel(__HANDLE__)) +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup I2C_Private_Functions I2C Private Functions * @{ */ +#if defined(HAL_DMA_MODULE_ENABLED) /* Private functions to handle DMA transfer */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); @@ -411,6 +427,8 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); static void I2C_DMAError(DMA_HandleTypeDef *hdma); static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); +#endif /* HAL_DMA_MODULE_ENABLED */ + /* Private functions to handle IT transfer */ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); @@ -421,24 +439,40 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); /* Private functions to handle IT transfer */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); /* Private functions for I2C transfer IRQ handler */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +#if defined(HAL_DMA_MODULE_ENABLED) +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +#endif /* HAL_DMA_MODULE_ENABLED */ /* Private functions to handle flags during polling transfer */ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); /* Private functions to centralize the enable/disable of Interrupts */ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); @@ -590,7 +624,8 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; /* Configure I2Cx: Dual mode and Own Address2 */ - hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8)); + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + (hi2c->Init.OwnAddress2Masks << 8)); /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ @@ -689,6 +724,8 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) /** * @brief Register a User I2C Callback * To be used instead of the weak predefined callback + * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param CallbackID ID of the callback to be registered @@ -719,8 +756,6 @@ HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Call return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hi2c); if (HAL_I2C_STATE_READY == hi2c->State) { @@ -809,14 +844,14 @@ HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hi2c); return status; } /** * @brief Unregister an I2C Callback * I2C callback is redirected to the weak predefined callback + * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param CallbackID ID of the callback to be unregistered @@ -839,9 +874,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hi2c); - if (HAL_I2C_STATE_READY == hi2c->State) { switch (CallbackID) @@ -929,8 +961,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hi2c); return status; } @@ -953,8 +983,6 @@ HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_Add return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hi2c); if (HAL_I2C_STATE_READY == hi2c->State) { @@ -969,8 +997,6 @@ HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_Add status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hi2c); return status; } @@ -985,9 +1011,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hi2c); - if (HAL_I2C_STATE_READY == hi2c->State) { hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ @@ -1001,8 +1024,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hi2c); return status; } @@ -1096,8 +1117,8 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -1128,12 +1149,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_WRITE); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); } while (hi2c->XferCount > 0U) @@ -1163,12 +1186,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); } } } @@ -1211,8 +1236,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -1243,12 +1268,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); } while (hi2c->XferCount > 0U) @@ -1279,12 +1306,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); } } } @@ -1325,7 +1354,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; @@ -1362,6 +1392,19 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData return HAL_ERROR; } + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); @@ -1407,22 +1450,27 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->XferCount--; } + /* Wait until AF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + /* Wait until STOP flag is set */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Normal use case for Transmitter mode */ - /* A NACK is generated to confirm the end of transfer */ - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } - else - { - return HAL_ERROR; - } + return HAL_ERROR; } /* Clear STOP flag */ @@ -1462,7 +1510,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; @@ -1486,6 +1535,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; hi2c->XferISR = NULL; /* Enable Address Acknowledge */ @@ -1528,6 +1578,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, hi2c->pBuffPtr++; hi2c->XferCount--; + hi2c->XferSize--; } return HAL_ERROR; @@ -1540,6 +1591,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, hi2c->pBuffPtr++; hi2c->XferCount--; + hi2c->XferSize--; } /* Wait until STOP flag is set */ @@ -1645,7 +1697,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; @@ -1723,7 +1776,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); return HAL_OK; @@ -1763,6 +1817,20 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_IT; + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1772,7 +1840,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); return HAL_OK; @@ -1821,7 +1890,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); return HAL_OK; @@ -1832,6 +1902,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa } } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Transmit in master mode an amount of data in non-blocking mode with DMA * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -1953,7 +2024,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /* Check if the Autonomous mode is enabled */ if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN) { - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_NO_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, + I2C_GENERATE_NO_START_WRITE); } else { @@ -1997,7 +2069,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2007,7 +2080,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } @@ -2140,7 +2214,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Check if the Autonomous mode is enabled */ if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN) { - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_NO_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, + I2C_GENERATE_NO_START_READ); } else { @@ -2184,7 +2259,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2194,7 +2270,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } @@ -2239,72 +2316,121 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_DMA; - if (hi2c->hdmatx != NULL) + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; + hi2c->XferCount--; + hi2c->XferSize--; + } - /* Enable the DMA channel */ - if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + if (hi2c->XferCount != 0U) + { + if (hi2c->hdmatx != NULL) { - if (hi2c->hdmatx->LinkedListQueue != NULL) + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) { - /* Set DMA data size */ - hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; - /* Set DMA source address */ - hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr; - /* Set DMA destination address */ - hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ - = (uint32_t)&hi2c->Instance->TXDR; + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->TXDR; - dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } } else { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, + (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } + return HAL_ERROR; } - else + + if (dmaxferstatus == HAL_OK) { - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, - hi2c->XferSize); + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; } - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } - - if (dmaxferstatus == HAL_OK) + else { /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; @@ -2313,27 +2439,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ + to avoid the risk of I2C interrupt handle execution before current + process unlock */ /* Enable ERR, STOP, NACK, ADDR interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; } return HAL_OK; @@ -2481,6 +2590,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD return HAL_BUSY; } } +#endif /* HAL_DMA_MODULE_ENABLED */ + /** * @brief Write an amount of data in blocking mode to a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -2578,12 +2689,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); } } @@ -2678,12 +2791,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); } do @@ -2714,12 +2829,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); } } } while (hi2c->XferCount > 0U); @@ -2765,9 +2882,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; - /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -2787,9 +2901,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Process Locked */ __HAL_LOCK(hi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -2798,29 +2909,29 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; - if (hi2c->XferCount > MAX_NBYTE_SIZE) + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ else { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2831,7 +2942,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; @@ -2857,9 +2969,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; - /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -2879,9 +2988,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Process Locked */ __HAL_LOCK(hi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -2890,29 +2996,29 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; - if (hi2c->XferCount > MAX_NBYTE_SIZE) + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ else { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2923,8 +3029,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT)); return HAL_OK; } @@ -2933,6 +3040,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre return HAL_BUSY; } } + +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -2948,8 +3057,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -2971,9 +3078,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Process Locked */ __HAL_LOCK(hi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -2982,27 +3086,36 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; } - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } if (hi2c->hdmatx != NULL) { @@ -3071,12 +3184,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd if (dmaxferstatus == HAL_OK) { - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3084,11 +3193,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } else { @@ -3128,8 +3237,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -3151,9 +3258,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Process Locked */ __HAL_LOCK(hi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -3162,25 +3266,35 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; } - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); } if (hi2c->hdmarx != NULL) @@ -3250,11 +3364,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr if (dmaxferstatus == HAL_OK) { - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3262,11 +3373,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } else { @@ -3290,6 +3401,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr return HAL_BUSY; } } +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Checks if target device is ready for communication. @@ -3302,7 +3414,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout) { uint32_t tickstart; @@ -3482,7 +3595,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3507,6 +3621,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; @@ -3517,6 +3635,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 } } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. * @note This interface allow to manage repeated start condition when a direction change during transfer @@ -3569,7 +3688,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3694,7 +3814,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3704,7 +3825,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } @@ -3715,6 +3837,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 return HAL_BUSY; } } +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt @@ -3767,7 +3890,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_ /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3802,6 +3926,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_ } } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA * @note This interface allow to manage repeated start condition when a direction change during transfer @@ -3854,7 +3979,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3978,7 +4104,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3988,7 +4115,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } @@ -3999,6 +4127,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 return HAL_BUSY; } } +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt @@ -4013,6 +4142,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -4037,6 +4169,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +#if defined(HAL_DMA_MODULE_ENABLED) /* Abort DMA Xfer if any */ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) { @@ -4056,6 +4189,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t } } } +#endif /* HAL_DMA_MODULE_ENABLED */ } hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; @@ -4072,7 +4206,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4096,6 +4231,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t } } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA * @note This interface allow to manage repeated start condition when a direction change during transfer @@ -4109,6 +4245,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -4143,7 +4281,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; /* Abort DMA RX */ @@ -4165,7 +4303,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ if (hi2c->hdmatx != NULL) { /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; /* Abort DMA TX */ @@ -4284,7 +4422,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ return HAL_ERROR; } - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4294,15 +4433,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ /* Process Unlocked */ __HAL_UNLOCK(hi2c); + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR, STOP, NACK, ADDR interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - return HAL_OK; } else @@ -4310,6 +4449,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ return HAL_ERROR; } } +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt @@ -4324,6 +4464,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -4348,6 +4491,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +#if defined(HAL_DMA_MODULE_ENABLED) if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; @@ -4367,6 +4511,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t } } } +#endif /* HAL_DMA_MODULE_ENABLED */ } hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; @@ -4383,7 +4528,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4407,6 +4553,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t } } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA * @note This interface allow to manage repeated start condition when a direction change during transfer @@ -4420,6 +4567,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -4595,7 +4744,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t return HAL_ERROR; } - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4605,15 +4755,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t /* Process Unlocked */ __HAL_UNLOCK(hi2c); + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* REnable ADDR interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - return HAL_OK; } else @@ -4621,6 +4771,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t return HAL_ERROR; } } +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Enable the Address listen mode with Interrupt. @@ -4773,7 +4924,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) uint32_t tmperror; /* I2C Bus error interrupt occurred ------------------------------------*/ - if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; @@ -4782,7 +4934,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; @@ -4791,7 +4944,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; @@ -4997,7 +5151,7 @@ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) * the configuration information for the specified I2C. * @retval HAL state */ -HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c) { /* Return I2C handle state */ return hi2c->State; @@ -5009,7 +5163,7 @@ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) * the configuration information for I2C module * @retval HAL mode */ -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c) { return hi2c->Mode; } @@ -5020,7 +5174,7 @@ HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) * the configuration information for the specified I2C. * @retval I2C Error Code */ -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c) { return hi2c->ErrorCode; } @@ -5045,7 +5199,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) { uint16_t devaddress; uint32_t tmpITFlags = ITFlags; @@ -5053,7 +5208,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Process Locked */ __HAL_LOCK(hi2c); - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -5110,11 +5266,13 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin hi2c->XferSize = hi2c->XferCount; if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { - I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + hi2c->XferOptions, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } } @@ -5134,7 +5292,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin } } } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { if (hi2c->XferCount == 0U) { @@ -5165,7 +5324,145 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Nothing to do */ } - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + if (hi2c->Memaddress == 0xFFFFFFFFU) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, tmpITFlags); @@ -5185,7 +5482,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) { uint32_t tmpoptions = hi2c->XferOptions; uint32_t tmpITFlags = ITFlags; @@ -5194,13 +5492,15 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint __HAL_LOCK(hi2c); /* Check if STOPF is set */ - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, tmpITFlags); } - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -5315,6 +5615,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint return HAL_OK; } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -5323,7 +5624,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) { uint16_t devaddress; uint32_t xfermode; @@ -5331,7 +5633,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Process Locked */ __HAL_LOCK(hi2c); - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -5347,7 +5650,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { /* Disable TC interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); @@ -5408,7 +5712,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui } } } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { if (hi2c->XferCount == 0U) { @@ -5451,6 +5756,145 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui return HAL_OK; } +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Enable only Error interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + if (hi2c->XferCount != 0U) + { + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -5459,7 +5903,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) { uint32_t tmpoptions = hi2c->XferOptions; uint32_t treatdmanack = 0U; @@ -5469,13 +5914,15 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin __HAL_LOCK(hi2c); /* Check if STOPF is set */ - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); } - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -5489,7 +5936,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin { if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) { - if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) { treatdmanack = 1U; } @@ -5501,7 +5948,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin { if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) { - if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U) + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) { treatdmanack = 1U; } @@ -5573,7 +6020,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); } } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) { I2C_ITAddrCplt(hi2c, ITFlags); } @@ -5587,6 +6035,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin return HAL_OK; } +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Master sends target device address followed by internal memory address for write request. @@ -5600,8 +6049,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) { I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); @@ -5654,8 +6104,9 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) { I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); @@ -5857,6 +6308,7 @@ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; +#if defined(HAL_DMA_MODULE_ENABLED) /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) { @@ -5872,6 +6324,7 @@ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) { /* Do nothing */ } +#endif /* HAL_DMA_MODULE_ENABLED */ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { @@ -5928,7 +6381,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmperror; uint32_t tmpITFlags = ITFlags; - __IO uint32_t tmp; + __IO uint32_t tmpreg; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); @@ -5969,9 +6422,8 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) { /* Read data from RXDR */ - tmp = (uint8_t)hi2c->Instance->RXDR; - - UNUSED(tmp); + tmpreg = (uint8_t)hi2c->Instance->RXDR; + UNUSED(tmpreg); } /* Flush TX register */ @@ -6102,6 +6554,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Flush TX register */ I2C_Flush_TXDR(hi2c); +#if defined(HAL_DMA_MODULE_ENABLED) /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) { @@ -6110,7 +6563,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) if (hi2c->hdmatx != NULL) { - hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx); + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx); } } else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) @@ -6120,13 +6573,14 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) if (hi2c->hdmarx != NULL) { - hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx); + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx); } } else { /* Do nothing */ } +#endif /* HAL_DMA_MODULE_ENABLED */ /* Store Last receive data if any */ if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) @@ -6281,7 +6735,10 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { HAL_I2C_StateTypeDef tmpstate = hi2c->State; + +#if defined(HAL_DMA_MODULE_ENABLED) uint32_t tmppreviousstate; +#endif /* HAL_DMA_MODULE_ENABLED */ /* Reset handle parameters */ hi2c->Mode = HAL_I2C_MODE_NONE; @@ -6308,18 +6765,37 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + /* If state is an abort treatment on going, don't change state */ /* This change will be do later */ if (hi2c->State != HAL_I2C_STATE_ABORT) { /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + } hi2c->XferISR = NULL; } +#if defined(HAL_DMA_MODULE_ENABLED) /* Abort DMA TX transfer if any */ tmppreviousstate = hi2c->PreviousState; + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) { @@ -6380,6 +6856,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) } } else +#endif /* HAL_DMA_MODULE_ENABLED */ { I2C_TreatErrorCallback(hi2c); } @@ -6444,6 +6921,7 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) } } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief DMA I2C master transmit process complete callback. * @param hdma DMA handle @@ -6521,6 +6999,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA I2C slave transmit process complete callback. * @param hdma DMA handle @@ -6549,6 +7028,7 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA I2C master receive process complete callback. * @param hdma DMA handle @@ -6626,6 +7106,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA I2C slave receive process complete callback. * @param hdma DMA handle @@ -6637,7 +7118,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tmpoptions = hi2c->XferOptions; - if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \ + if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \ (tmpoptions != I2C_NO_OPTION_FRAME)) { /* Disable DMA Request */ @@ -6654,6 +7135,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA I2C communication error callback. * @param hdma DMA handle @@ -6671,6 +7153,7 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); } + /** * @brief DMA I2C communication abort callback * (To be called at end of DMA Abort procedure). @@ -6695,12 +7178,15 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) I2C_TreatErrorCallback(hi2c); } +#endif /* HAL_DMA_MODULE_ENABLED */ + /** - * @brief This function handles I2C Communication Timeout. + * @brief This function handles I2C Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param Flag Specifies the I2C flag to check. - * @param Status The new Flag status (SET or RESET). + * @param Status The actual Flag status (SET or RESET). * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status @@ -6715,13 +7201,16 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } } } } @@ -6736,12 +7225,13 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -6751,14 +7241,17 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -6773,12 +7266,13 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -6786,14 +7280,17 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } return HAL_OK; @@ -6807,12 +7304,13 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -6830,13 +7328,22 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, } else { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + } + else + { + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; @@ -6850,80 +7357,149 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } return HAL_OK; } /** - * @brief This function handles Acknowledge failed detection during an I2C Communication. + * @brief This function handles errors detection during an I2C Communication. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + HAL_StatusTypeDef status = HAL_OK; + uint32_t itflag = hi2c->Instance->ISR; + uint32_t error_code = 0; + uint32_t tickstart = Tickstart; + uint32_t tmp1; + HAL_I2C_ModeTypeDef tmp2; + + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF)) { - /* In case of Soft End condition, generate the STOP condition */ - if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - } + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Wait until STOP Flag is reset */ + /* Wait until STOP Flag is set or timeout occurred */ /* AutoEnd should be initiate after AF */ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP); + tmp2 = hi2c->Mode; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* In case of I2C still busy, try to regenerate a STOP manually */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \ + (tmp1 != I2C_CR2_STOP) && \ + (tmp2 != HAL_I2C_MODE_SLAVE)) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; - return HAL_ERROR; + /* Update Tick with new reference */ + tickstart = HAL_GetTick(); + } + + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) + { + error_code |= HAL_I2C_ERROR_TIMEOUT; + + status = HAL_ERROR; + + break; + } + } } } } - /* Clear NACKF Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + /* In case STOP Flag is detected, clear it */ + if (status == HAL_OK) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + error_code |= HAL_I2C_ERROR_AF; + + status = HAL_ERROR; + } + + /* Refresh Content of Status register */ + itflag = hi2c->Instance->ISR; + + /* Then verify if an additional errors occurs */ + /* Check if a Bus error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR)) + { + error_code |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + + status = HAL_ERROR; + } + /* Check if an Over-Run/Under-Run error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR)) + { + error_code |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + + status = HAL_ERROR; + } + + /* Check if an Arbitration Loss error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO)) + { + error_code |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + + status = HAL_ERROR; + } + + if (status != HAL_OK) + { /* Flush TX register */ I2C_Flush_TXDR(hi2c); /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + hi2c->ErrorCode |= error_code; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); - - return HAL_ERROR; } - return HAL_OK; + + return status; } /** @@ -6953,13 +7529,16 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uin assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + /* update CR2 register */ - MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ - (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ - I2C_CR2_START | I2C_CR2_STOP)), \ - (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request)); + MODIFY_REG(hi2c->Instance->CR2, \ + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP)), tmp); } /** @@ -6973,15 +7552,30 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) { uint32_t tmpisr = 0U; - if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ - (hi2c->XferISR == I2C_Slave_ISR_DMA)) +#if defined(HAL_DMA_MODULE_ENABLED) + if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ + (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ + (hi2c->XferISR != I2C_Mem_ISR_DMA)) +#endif /* HAL_DMA_MODULE_ENABLED */ { if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { - /* Enable ERR, STOP, NACK and ADDR interrupts */ + /* Enable ERR, STOP, NACK, and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + if (InterruptRequest == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ @@ -6991,20 +7585,16 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ - tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); - } - - if (InterruptRequest == I2C_XFER_RELOAD_IT) - { - /* Enable TC interrupts */ - tmpisr |= I2C_IT_TCI; + tmpisr |= I2C_IT_STOPI; } } + +#if defined(HAL_DMA_MODULE_ENABLED) else { if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { - /* Enable ERR, STOP, NACK, and ADDR interrupts */ + /* Enable ERR, STOP, NACK and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } @@ -7020,12 +7610,25 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); + } + + if ((hi2c->XferISR != I2C_Mem_ISR_DMA) && (InterruptRequest == I2C_XFER_RELOAD_IT)) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; } } +#endif /* HAL_DMA_MODULE_ENABLED */ /* Enable interrupts only at the end */ /* to avoid the risk of I2C interrupt handle execution before */ @@ -7033,6 +7636,7 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) __HAL_I2C_ENABLE_IT(hi2c, tmpisr); } + /** * @brief Manage the disabling of Interrupts. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_i2c.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_i2c.h index 8b816c6ef9b..40ab8526c5d 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_i2c.h @@ -47,29 +47,30 @@ extern "C" { typedef struct { uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. - This parameter calculated by referring to I2C initialization - section in Reference manual */ + This parameter calculated by referring to I2C initialization section + in Reference manual */ uint32_t OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ + This parameter can be a 7-bit or 10-bit address. */ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. - This parameter can be a value of @ref I2C_ADDRESSING_MODE */ + This parameter can be a value of @ref I2C_ADDRESSING_MODE */ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ + This parameter can be a 7-bit address. */ - uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected - This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing + mode is selected. + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ + This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ + This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ } I2C_InitTypeDef; @@ -199,12 +200,16 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t PreviousState; /*!< I2C communication Previous state */ - HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); + /*!< I2C transfer IRQ handler function pointer */ +#if defined(HAL_DMA_MODULE_ENABLED) DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ +#endif /*HAL_DMA_MODULE_ENABLED*/ + HAL_LockTypeDef Lock; /*!< I2C locking object */ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ @@ -215,21 +220,37 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */ - void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */ - void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */ - void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */ - void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */ - void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */ - void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */ - void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */ - void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */ + __IO uint32_t Devaddress; /*!< I2C Target device address */ - void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */ + __IO uint32_t Memaddress; /*!< I2C Target memory address */ - void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */ - void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Abort callback */ + + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< I2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp DeInit callback */ #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } I2C_HandleTypeDef; @@ -258,8 +279,11 @@ typedef enum /** * @brief HAL I2C Callback pointer definition */ -typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */ -typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); +/*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an I2C Address Match callback function */ #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ /** @@ -441,10 +465,10 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * @retval None */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) -#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) @@ -551,19 +575,19 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * @param __HANDLE__ specifies the I2C Handle. * @retval None */ -#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) +#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Disable the specified I2C peripheral. * @param __HANDLE__ specifies the I2C Handle. * @retval None */ -#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) +#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. * @param __HANDLE__ specifies the I2C Handle. * @retval None */ -#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) +#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) /** * @} */ @@ -603,12 +627,14 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); */ /* IO operation functions ****************************************************/ /******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, @@ -640,6 +666,7 @@ HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); +#if defined(HAL_DMA_MODULE_ENABLED) /******* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); @@ -660,6 +687,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ uint32_t XferOptions); HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +#endif /*HAL_DMA_MODULE_ENABLED*/ /** * @} */ @@ -688,9 +716,9 @@ void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); * @{ */ /* Peripheral State, Mode and Error functions *********************************/ -HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); +HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c); /** * @} @@ -765,8 +793,10 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ I2C_CR2_RD_WRN))) -#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)) -#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)) +#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \ + >> 16U)) +#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \ + >> 16U)) #define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) #define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) #define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_i2c_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_i2c_ex.c index bb18de8125c..ef1b495c353 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_i2c_ex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_i2c_ex.c @@ -5,10 +5,10 @@ * @brief I2C Extended HAL module driver. * This file provides firmware functions to manage the following * functionalities of I2C Extended peripheral: - * + I2C Extended Filter Mode Functions - * + I2C Extended WakeUp Mode Functions - * + I2C I2C Extended FastModePlus Functions - * + I2C I2C Extended Autonomous Mode Functions + * + Filter Mode Functions + * + WakeUp Mode Functions + * + FastModePlus Functions + * + Autonomous Mode Functions * ****************************************************************************** * @attention @@ -33,6 +33,7 @@ (+) Use of a configured Digital Noise Filter (+) Disable or enable wakeup from Stop mode(s) (+) Disable or enable Fast Mode Plus + (+) Configure Autonomous mode ##### How to use this driver ##### ============================================================================== @@ -76,12 +77,12 @@ * @{ */ -/** @defgroup I2CEx_Exported_Functions_Group1 I2C Extended Filter Mode Functions - * @brief I2C Extended Filter Mode Functions +/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @brief Filter Mode Functions * @verbatim =============================================================================== - ##### Extended Noise Filters functions ##### + ##### Filter Mode Functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure Noise Filters @@ -185,17 +186,16 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ return HAL_BUSY; } } - /** * @} */ -/** @addtogroup I2CEx_Exported_Functions_Group2 I2C Extended WakeUp Mode Functions - * @brief I2C Extended WakeUp Mode Functions +/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @brief WakeUp Mode Functions * @verbatim =============================================================================== - ##### Extended WakeUp Mode functions ##### + ##### WakeUp Mode Functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure Wake Up Feature @@ -281,17 +281,16 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) return HAL_BUSY; } } - /** * @} */ -/** @addtogroup I2CEx_Exported_Functions_Group3 I2C Extended FastModePlus Functions - * @brief I2C Extended FastModePlus Functions +/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions * @verbatim =============================================================================== - ##### Extended FastModePlus functions ##### + ##### Fast Mode Plus Functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure Fast Mode Plus @@ -353,12 +352,12 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t * @} */ -/** @addtogroup I2CEx_Exported_Functions_Group4 I2C Extended Autonomous Mode Functions - * @brief I2C Extended Autonomous Mode Functions +/** @defgroup I2CEx_Exported_Functions_Group4 Autonomous Mode Functions + * @brief Autonomous Mode Functions * @verbatim =============================================================================== - ##### Extended Autonomous Mode functions ##### + ##### Autonomous Mode functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure Autonomous Mode @@ -375,7 +374,8 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t * the configuration information of the autonomous mode for the specified I2Cx peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_I2CEx_SetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, I2C_AutonomousModeConfTypeDef *sConfig) +HAL_StatusTypeDef HAL_I2CEx_SetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, + const I2C_AutonomousModeConfTypeDef *sConfig) { if (hi2c->State == HAL_I2C_STATE_READY) { @@ -385,16 +385,18 @@ HAL_StatusTypeDef HAL_I2CEx_SetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, I2C hi2c->State = HAL_I2C_STATE_BUSY; /* Check the parameters */ + assert_param(IS_I2C_TRIG_INPUT_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_TRIG_SOURCE(hi2c->Instance, sConfig->TriggerSelection)); - assert_param(IS_I2C_AUTO_MODE_TRG_POL(sConfig->TriggerPolarity)); /* Disable the selected I2C peripheral to be able to configure AUTOCR */ __HAL_I2C_DISABLE(hi2c); /* I2Cx AUTOCR Configuration */ - WRITE_REG(hi2c->Instance->AUTOCR, (sConfig->TriggerState | ((sConfig->TriggerSelection) & I2C_AUTOCR_TRIGSEL_Msk) | - sConfig->TriggerPolarity)); + WRITE_REG(hi2c->Instance->AUTOCR, + (sConfig->TriggerState | \ + ((sConfig->TriggerSelection) & I2C_AUTOCR_TRIGSEL_Msk) | \ + sConfig->TriggerPolarity)); /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); @@ -420,10 +422,14 @@ HAL_StatusTypeDef HAL_I2CEx_SetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, I2C * the configuration information of the autonomous mode for the specified I2Cx peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_I2CEx_GetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, I2C_AutonomousModeConfTypeDef *sConfig) +HAL_StatusTypeDef HAL_I2CEx_GetConfigAutonomousMode(const I2C_HandleTypeDef *hi2c, + I2C_AutonomousModeConfTypeDef *sConfig) { uint32_t autocr_tmp; + /* Check the parameters */ + assert_param(IS_I2C_TRIG_INPUT_INSTANCE(hi2c->Instance)); + autocr_tmp = hi2c->Instance->AUTOCR; sConfig->TriggerState = (autocr_tmp & I2C_AUTOCR_TRIGEN); @@ -455,6 +461,9 @@ HAL_StatusTypeDef HAL_I2CEx_ClearConfigAutonomousMode(I2C_HandleTypeDef *hi2c) hi2c->State = HAL_I2C_STATE_BUSY; + /* Check the parameters */ + assert_param(IS_I2C_TRIG_INPUT_INSTANCE(hi2c->Instance)); + /* Disable the selected I2C peripheral to be able to clear AUTOCR */ __HAL_I2C_DISABLE(hi2c); @@ -475,11 +484,6 @@ HAL_StatusTypeDef HAL_I2CEx_ClearConfigAutonomousMode(I2C_HandleTypeDef *hi2c) return HAL_ERROR; } } - -/** - * @} - */ - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_i2c_ex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_i2c_ex.h index f32174dfd28..4bd1ab8d9bb 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_i2c_ex.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_i2c_ex.h @@ -40,8 +40,7 @@ extern "C" { * @{ */ -/** @defgroup I2C_Autonomous_Mode_Configuration_Structure_definition I2C Autonomous Mode Configuration Structure - definition +/** @defgroup I2C_Autonomous_Mode_Configuration_Structure_definition Autonomous Mode Configuration Structure definition * @brief I2C Autonomous Mode Configuration structure definition * @{ */ @@ -91,8 +90,8 @@ typedef struct /** @defgroup I2CEx_AutonomousMode_FunctionalState I2C Extended Autonomous Mode State * @{ */ -#define I2C_AUTO_MODE_DISABLE (0x00000000U) /* Autonomous mode disable */ -#define I2C_AUTO_MODE_ENABLE I2C_AUTOCR_TRIGEN /* Autonomous mode enable */ +#define I2C_AUTO_MODE_DISABLE (0x00000000U) /*!< Autonomous mode disable */ +#define I2C_AUTO_MODE_ENABLE I2C_AUTOCR_TRIGEN /*!< Autonomous mode enable */ /** * @} */ @@ -100,67 +99,67 @@ typedef struct /** @defgroup I2CEx_AutonomousMode_TriggerSelection I2C Extended Autonomous Mode Trigger Selection * @{ */ -#define I2C_TRIG_GRP1 (0x10000000U) /* Trigger Group for I2C1, I2C2 and I2C4 */ -#define I2C_TRIG_GRP2 (0x20000000U) /* Trigger Group for I2C3 */ +#define I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2, I2C4, I2C5, I2C6 (depends on Product) */ +#define I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ -/* HW Trigger signal is GPDMA_CH0_TRG */ #define I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x00000000U)) -/* HW Trigger signal is GPDMA_CH1_TRG */ +/*!< HW Trigger signal is GPDMA_CH0_TRG */ #define I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is GPDMA_CH2_TRG */ +/*!< HW Trigger signal is GPDMA_CH1_TRG */ #define I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is GPDMA_CH3_TRG */ +/*!< HW Trigger signal is GPDMA_CH2_TRG */ #define I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is EXTI5_TRG */ +/*!< HW Trigger signal is GPDMA_CH3_TRG */ #define I2C_GRP1_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is EXTI9_TRG */ +/*!< HW Trigger signal is EXTI5_TRG */ #define I2C_GRP1_EXTI9_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is LPTIM1_CH1_TRG */ +/*!< HW Trigger signal is EXTI9_TRG */ #define I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is LPTIM2_CH1_TRG */ +/*!< HW Trigger signal is LPTIM1_CH1_TRG */ #define I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is COMP1_TRG */ +/*!< HW Trigger signal is LPTIM2_CH1_TRG */ #define I2C_GRP1_COMP1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is COMP2_TRG */ +/*!< HW Trigger signal is COMP1_TRG */ #define I2C_GRP1_COMP2_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is RTC_ALRA_TRG */ +/*!< HW Trigger signal is COMP2_TRG */ #define I2C_GRP1_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is RTC_WUT_TRG */ +/*!< HW Trigger signal is RTC_ALRA_TRG */ #define I2C_GRP1_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_WUT_TRG */ -/* HW Trigger signal is LPDMA_CH0_TRG */ #define I2C_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x00000000U)) -/* HW Trigger signal is LPDMA_CH1_TRG */ +/*!< HW Trigger signal is LPDMA_CH0_TRG */ #define I2C_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is LPDMA_CH2_TRG */ +/*!< HW Trigger signal is LPDMA_CH1_TRG */ #define I2C_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is LPDMA_CH3_TRG */ +/*!< HW Trigger signal is LPDMA_CH2_TRG */ #define I2C_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is EXTI5_TRG */ +/*!< HW Trigger signal is LPDMA_CH3_TRG */ #define I2C_GRP2_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is EXTI8_TRG */ +/*!< HW Trigger signal is EXTI5_TRG */ #define I2C_GRP2_EXTI8_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is LPTIM1_CH1_TRG */ +/*!< HW Trigger signal is EXTI8_TRG */ #define I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is LPTIM3_CH1_TRG */ +/*!< HW Trigger signal is LPTIM1_CH1_TRG */ #define I2C_GRP2_LPTIM3_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is COMP1_TRG */ +/*!< HW Trigger signal is LPTIM3_CH1_TRG */ #define I2C_GRP2_COMP1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is COMP2_TRG */ +/*!< HW Trigger signal is COMP1_TRG */ #define I2C_GRP2_COMP2_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is RTC_ALRA_TRG */ +/*!< HW Trigger signal is COMP2_TRG */ #define I2C_GRP2_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is RTC_WUT_TRG */ +/*!< HW Trigger signal is RTC_ALRA_TRG */ #define I2C_GRP2_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_WUT_TRG */ /** * @} */ -/** @defgroup I2CEx_AutonomousMode_TriggerPolarity I2C Extended Autonomous Mode Trigger Polarity +/** @defgroup I2CEx_AutonomousMode_TriggerPolarity Extended Autonomous Mode Trigger Polarity * @{ */ -#define I2C_TRIG_POLARITY_RISING (0x00000000U) /* I2C HW Trigger signal on rising edge */ -#define I2C_TRIG_POLARITY_FALLING I2C_AUTOCR_TRIGPOL /* I2C HW Trigger signal on falling edge */ +#define I2C_TRIG_POLARITY_RISING (0x00000000U) /*!< I2C HW Trigger signal on rising edge */ +#define I2C_TRIG_POLARITY_FALLING I2C_AUTOCR_TRIGPOL /*!< I2C HW Trigger signal on falling edge */ /** * @} */ @@ -183,7 +182,7 @@ typedef struct * @{ */ -/** @addtogroup I2CEx_Exported_Functions_Group1 I2C Extended Filter Mode Functions +/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions * @{ */ /* Peripheral Control functions ************************************************/ @@ -193,7 +192,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ * @} */ -/** @addtogroup I2CEx_Exported_Functions_Group2 I2C Extended WakeUp Mode Functions +/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions * @{ */ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); @@ -202,7 +201,7 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); * @} */ -/** @addtogroup I2CEx_Exported_Functions_Group3 I2C Extended FastModePlus Functions +/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions * @{ */ HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t FastModePlus); @@ -210,11 +209,13 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t * @} */ -/** @addtogroup I2CEx_Exported_Functions_Group4 I2C Extended Autonomous Mode Functions +/** @addtogroup I2CEx_Exported_Functions_Group4 Autonomous Mode Functions * @{ */ -HAL_StatusTypeDef HAL_I2CEx_SetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, I2C_AutonomousModeConfTypeDef *sConfig); -HAL_StatusTypeDef HAL_I2CEx_GetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, I2C_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_I2CEx_SetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, + const I2C_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_I2CEx_GetConfigAutonomousMode(const I2C_HandleTypeDef *hi2c, + I2C_AutonomousModeConfTypeDef *sConfig); HAL_StatusTypeDef HAL_I2CEx_ClearConfigAutonomousMode(I2C_HandleTypeDef *hi2c); /** * @} @@ -278,6 +279,9 @@ HAL_StatusTypeDef HAL_I2CEx_ClearConfigAutonomousMode(I2C_HandleTypeDef *hi2c); ((__SOURCE__) == I2C_GRP2_RTC_ALRA_TRG ) || \ ((__SOURCE__) == I2C_GRP2_RTC_WUT_TRG )) +#define IS_I2C_TRIG_INPUT_INSTANCE(__INSTANCE__) (IS_I2C_GRP1_INSTANCE(__INSTANCE__) || \ + IS_I2C_GRP2_INSTANCE(__INSTANCE__)) + #define IS_I2C_AUTO_MODE_TRG_POL(__POLARITY__) (((__POLARITY__) == I2C_TRIG_POLARITY_RISING) || \ ((__POLARITY__) == I2C_TRIG_POLARITY_FALLING)) /** diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_icache.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_icache.c index ce41ead3fe3..4b423e08c52 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_icache.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_icache.c @@ -34,7 +34,7 @@ cache invalidate maintenance operation, error management and TrustZone security support. - (+) The ICACHE provides additionnaly the possibility to remap input address + (+) The ICACHE provides additionally the possibility to remap input address falling into up to four memory regions (used to remap aliased code in external memories to the internal Code region, for execution) @@ -44,10 +44,13 @@ [..] The ICACHE HAL driver can be used as follows: - (#) Enable and disable the Instruction Cache with respectively - @ref HAL_ICACHE_Enable() and @ref HAL_ICACHE_Disable() + (#) Optionally configure the Instruction Cache mode with + @ref HAL_ICACHE_ConfigAssociativityMode() if the default configuration + does not suit the application requirements. - (#) Configure the Instruction Cache mode with @ref HAL_ICACHE_ConfigAssociativityMode() + (#) Enable and disable the Instruction Cache with respectively + @ref HAL_ICACHE_Enable() and @ref HAL_ICACHE_Disable(). + Use @ref HAL_ICACHE_IsEnabled() to get the Instruction Cache status. (#) Initiate the cache maintenance invalidation procedure with either @ref HAL_ICACHE_Invalidate() (blocking mode) or @ref HAL_ICACHE_Invalidate_IT() @@ -233,9 +236,9 @@ HAL_StatusTypeDef HAL_ICACHE_Disable(void) HAL_StatusTypeDef status = HAL_OK; uint32_t tickstart; - /* Reset BSYENDF before to disable the instruction cache */ - /* that starts a cache invalidation procedure */ - CLEAR_BIT(ICACHE->FCR, ICACHE_FCR_CBSYENDF); + /* Make sure BSYENDF is reset before to disable the instruction cache */ + /* as it automatically starts a cache invalidation procedure */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); @@ -259,6 +262,15 @@ HAL_StatusTypeDef HAL_ICACHE_Disable(void) return status; } +/** + * @brief Check whether the Instruction Cache is enabled or not. + * @retval Status (0: disabled, 1: enabled) + */ +uint32_t HAL_ICACHE_IsEnabled(void) +{ + return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) ? 1UL : 0UL); +} + /** * @brief Invalidate the Instruction Cache. * @note This function waits for the end of cache invalidation procedure @@ -277,7 +289,7 @@ HAL_StatusTypeDef HAL_ICACHE_Invalidate(void) else { /* Make sure BSYENDF is reset before to start cache invalidation */ - CLEAR_BIT(ICACHE->FCR, ICACHE_FCR_CBSYENDF); + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); /* Launch cache invalidation */ SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); @@ -307,7 +319,7 @@ HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void) } else { - /* Make sure BSYENDF is reset */ + /* Make sure BSYENDF is reset before to start cache invalidation */ WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); /* Enable end of cache invalidation interrupt */ @@ -475,7 +487,7 @@ void HAL_ICACHE_IRQHandler(void) /* Disable error interrupt */ CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE); - /* Clear ICACHE error pending flag */ + /* Clear ERR pending flag */ WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF); /* Instruction cache error interrupt user callback */ @@ -488,7 +500,7 @@ void HAL_ICACHE_IRQHandler(void) /* Disable end of cache invalidation interrupt */ CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); - /* Clear ICACHE busyend pending flag */ + /* Clear BSYENDF pending flag */ WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); /* Instruction cache busyend interrupt user callback */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_icache.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_icache.h index fa066e322f4..53d0d08033b 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_icache.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_icache.h @@ -226,6 +226,7 @@ typedef struct /* Peripheral Control functions **********************************************/ HAL_StatusTypeDef HAL_ICACHE_Enable(void); HAL_StatusTypeDef HAL_ICACHE_Disable(void); +uint32_t HAL_ICACHE_IsEnabled(void); HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode); HAL_StatusTypeDef HAL_ICACHE_DeInit(void); diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_irda.c index 4acfd023ee1..87cb645c81d 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_irda.c @@ -125,8 +125,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback. - Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks: + Use Function HAL_IRDA_RegisterCallback() to register a user callback. + Function HAL_IRDA_RegisterCallback() allows to register following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. (+) TxCpltCallback : Tx Complete Callback. (+) RxHalfCpltCallback : Rx Half Complete Callback. @@ -141,9 +141,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default + Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. @@ -158,13 +158,13 @@ (+) MspDeInitCallback : IRDA MspDeInit. [..] - By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET + By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback(). + examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init() - and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init() + and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -173,8 +173,8 @@ in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit() - or @ref HAL_IRDA_Init() function. + using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit() + or HAL_IRDA_Init() function. [..] When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or @@ -182,6 +182,7 @@ and weak (surcharged) callbacks are used. @endverbatim + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -243,8 +244,11 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +#if defined(HAL_DMA_MODULE_ENABLED) static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda); +#endif /* HAL_DMA_MODULE_ENABLED */ static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda); +#if defined(HAL_DMA_MODULE_ENABLED) static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma); static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma); @@ -255,6 +259,7 @@ static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma); static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma); static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +#endif /* HAL_DMA_MODULE_ENABLED */ static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda); static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda); static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); @@ -462,6 +467,8 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) /** * @brief Register a User IRDA Callback * To be used instead of the weak predefined callback + * @note The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET + * to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID * @param hirda irda handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -490,8 +497,6 @@ HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_ return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hirda); if (hirda->gState == HAL_IRDA_STATE_READY) { @@ -576,15 +581,14 @@ HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hirda); - return status; } /** * @brief Unregister an IRDA callback * IRDA callback is redirected to the weak predefined callback + * @note The HAL_IRDA_UnRegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET + * to un-register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID * @param hirda irda handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -604,9 +608,6 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hirda); - if (HAL_IRDA_STATE_READY == hirda->gState) { switch (CallbackID) @@ -692,9 +693,6 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hirda); - return status; } #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ @@ -800,10 +798,10 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD * @param Timeout Specify timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint8_t *pdata8bits; - uint16_t *pdata16bits; + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; uint32_t tickstart; /* Check that a Tx process is not already ongoing */ @@ -830,7 +828,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) { pdata8bits = NULL; - pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */ + pdata16bits = (const uint16_t *) pData; /* Derogation R.11.3 */ } else { @@ -979,7 +977,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if (hirda->gState == HAL_IRDA_STATE_READY) @@ -1051,8 +1049,16 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, /* Process Unlocked */ __HAL_UNLOCK(hirda); - /* Enable the IRDA Parity Error and Data Register not empty Interrupts */ - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + if (hirda->Init.Parity != IRDA_PARITY_NONE) + { + /* Enable the IRDA Parity Error and Data Register not empty Interrupts */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + /* Enable the IRDA Data Register not empty Interrupts */ + SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); @@ -1065,6 +1071,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, } } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Send an amount of data in DMA mode. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), @@ -1076,7 +1083,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef status; uint16_t nbByte = Size; @@ -1272,8 +1279,11 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData /* Process Unlocked */ __HAL_UNLOCK(hirda); - /* Enable the UART Parity Error Interrupt */ - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + if (hirda->Init.Parity != IRDA_PARITY_NONE) + { + /* Enable the UART Parity Error Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); @@ -1365,7 +1375,10 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) __HAL_IRDA_CLEAR_OREFLAG(hirda); /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + if (hirda->Init.Parity != IRDA_PARITY_NONE) + { + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + } SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* Enable the IRDA DMA Rx request */ @@ -1447,6 +1460,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) return HAL_OK; } +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Abort ongoing transfers (blocking mode). @@ -1468,6 +1482,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); +#if defined(HAL_DMA_MODULE_ENABLED) /* Disable the IRDA DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) { @@ -1517,6 +1532,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) } } } +#endif /* HAL_DMA_MODULE_ENABLED */ /* Reset Tx and Rx transfer counters */ hirda->TxXferCount = 0U; @@ -1553,6 +1569,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) /* Disable TXEIE and TCIE interrupts */ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#if defined(HAL_DMA_MODULE_ENABLED) /* Disable the IRDA DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) { @@ -1577,6 +1594,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) } } } +#endif /* HAL_DMA_MODULE_ENABLED */ /* Reset Tx transfer counter */ hirda->TxXferCount = 0U; @@ -1606,6 +1624,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); +#if defined(HAL_DMA_MODULE_ENABLED) /* Disable the IRDA DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) { @@ -1630,6 +1649,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) } } } +#endif /* HAL_DMA_MODULE_ENABLED */ /* Reset Rx transfer counter */ hirda->RxXferCount = 0U; @@ -1667,6 +1687,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); +#if defined(HAL_DMA_MODULE_ENABLED) /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ /* DMA Tx Handle is valid */ @@ -1745,6 +1766,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) } } } +#endif /* HAL_DMA_MODULE_ENABLED */ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ if (abortcplt == 1U) @@ -1796,6 +1818,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) /* Disable TXEIE and TCIE interrupts */ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#if defined(HAL_DMA_MODULE_ENABLED) /* Disable the IRDA DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) { @@ -1834,6 +1857,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) } } else +#endif /* HAL_DMA_MODULE_ENABLED */ { /* Reset Tx transfer counter */ hirda->TxXferCount = 0U; @@ -1875,6 +1899,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); +#if defined(HAL_DMA_MODULE_ENABLED) /* Disable the IRDA DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) { @@ -1916,6 +1941,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) } } else +#endif /* HAL_DMA_MODULE_ENABLED */ { /* Reset Rx transfer counter */ hirda->RxXferCount = 0U; @@ -2024,6 +2050,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ IRDA_EndRxTransfer(hirda); +#if defined(HAL_DMA_MODULE_ENABLED) /* Disable the IRDA DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) { @@ -2055,6 +2082,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) } } else +#endif /* HAL_DMA_MODULE_ENABLED */ { #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) /* Call registered user error callback */ @@ -2256,7 +2284,7 @@ __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA module. * @retval HAL state */ -HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) +HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda) { /* Return IRDA handle state */ uint32_t temp1; @@ -2273,7 +2301,7 @@ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA module. * @retval IRDA Error Code */ -uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) +uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda) { return hirda->ErrorCode; } @@ -2361,21 +2389,21 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) { case IRDA_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_HSI: - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_LSE: - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; default: ret = HAL_ERROR; @@ -2385,7 +2413,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) /* USARTDIV must be greater than or equal to 0d16 */ if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX)) { - hirda->Instance->BRR = tmpreg; + hirda->Instance->BRR = (uint16_t)tmpreg; } else { @@ -2443,11 +2471,12 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) } /** - * @brief Handle IRDA Communication Timeout. + * @brief Handle IRDA Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @param Flag Specifies the IRDA flag to check. - * @param Status Flag status (SET or RESET) + * @param Status The actual Flag status (SET or RESET) * @param Tickstart Tick start value * @param Timeout Timeout duration * @retval HAL status @@ -2481,6 +2510,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion). * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains @@ -2495,7 +2525,7 @@ static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda) /* At end of Tx process, restore hirda->gState to Ready */ hirda->gState = HAL_IRDA_STATE_READY; } - +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). @@ -2514,6 +2544,7 @@ static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda) } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief DMA IRDA transmit process complete callback. * @param hdma Pointer to a DMA_HandleTypeDef structure that contains @@ -2837,6 +2868,7 @@ static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) HAL_IRDA_AbortReceiveCpltCallback(hirda); #endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Send an amount of data in interrupt mode. @@ -2848,7 +2880,7 @@ static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) */ static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) { - uint16_t *tmp; + const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) @@ -2865,7 +2897,7 @@ static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) { if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) { - tmp = (uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */ + tmp = (const uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */ hirda->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); hirda->pTxBuffPtr += 2U; } @@ -2973,3 +3005,4 @@ static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) * @} */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_irda.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_irda.h index fb6a20e8a6a..bf306a08f54 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_irda.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_irda.h @@ -143,7 +143,7 @@ typedef struct IRDA_InitTypeDef Init; /*!< IRDA communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */ uint16_t TxXferSize; /*!< IRDA Tx Transfer size */ @@ -157,10 +157,12 @@ typedef struct uint16_t Mask; /*!< USART RX RDR register mask */ +#if defined(HAL_DMA_MODULE_ENABLED) DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */ DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */ +#endif /* HAL_DMA_MODULE_ENABLED */ HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management @@ -266,7 +268,9 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer #define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */ #define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */ #define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#if defined(HAL_DMA_MODULE_ENABLED) #define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#endif /* HAL_DMA_MODULE_ENABLED */ #define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */ #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) #define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ @@ -827,15 +831,17 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda); HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda); HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda); +#endif /* HAL_DMA_MODULE_ENABLED */ /* Transfer Abort functions */ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda); HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda); @@ -865,8 +871,8 @@ void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda); */ /* Peripheral State and Error functions ***************************************/ -HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda); -uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); +HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda); +uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda); /** * @} @@ -889,3 +895,4 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); #endif #endif /* STM32U5xx_HAL_IRDA_H */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_irda_ex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_irda_ex.h index 759eddcff5b..b8d6352d0d0 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_irda_ex.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_irda_ex.h @@ -203,7 +203,7 @@ extern "C" { (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) -#else +#elif defined(USART2) #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ @@ -316,6 +316,98 @@ extern "C" { (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) +#else +#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + switch(__HAL_RCC_GET_UART4_SOURCE()) \ + { \ + case RCC_UART4CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART4CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART4CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_UART4CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == UART5) \ + { \ + switch(__HAL_RCC_GET_UART5_SOURCE()) \ + { \ + case RCC_UART5CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART5CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART5CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_UART5CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) #endif /* USART6 */ /** @brief Compute the mask to apply to retrieve the received data @@ -390,3 +482,4 @@ extern "C" { #endif #endif /* STM32U5xx_HAL_IRDA_EX_H */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_iwdg.c index 25ec1e126bd..4dbf8f7b40c 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_iwdg.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_iwdg.c @@ -128,14 +128,16 @@ /** @defgroup IWDG_Private_Defines IWDG Private Defines * @{ */ -/* Status register needs up to 5 LSI clock periods divided by the clock - prescaler to be updated. The number of LSI clock periods is upper-rounded to - 6 for the timeout value calculation. - The timeout value is also calculated using the highest prescaler (256) and +/* Status register needs up to 5 LSI clock periods to be updated. However a + synchronisation is added on prescaled LSI clock rising edge, so we only + consider a highest prescaler cycle. + The timeout value is calculated using the highest prescaler (1024) and the LSI_VALUE constant. The value of this constant can be changed by the user to take into account possible LSI clock period variations. - The timeout value is multiplied by 1000 to be converted in milliseconds. */ -#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE) + The timeout value is multiplied by 1000 to be converted in milliseconds. + LSI startup time is also considered here by adding LSI_STARTUP_TIME + converted in milliseconds. */ +#define HAL_IWDG_DEFAULT_TIMEOUT (((1UL * 1024UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) #define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_EWU | IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU) /** * @} @@ -224,20 +226,16 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) if (hiwdg->Init.EWI == IWDG_EWI_DISABLE) { - /* EWI comparator value different from 0, - * Disable the early wakeup interrupt + /* EWI comparator value equal 0, disable the early wakeup interrupt * acknowledge the early wakeup interrupt in any cases. it clears the EWIF flag in SR register - * Set Watchdog Early Wakeup Comparator to 0x00 - */ + * Set Watchdog Early Wakeup Comparator to 0x00 */ hiwdg->Instance->EWCR = IWDG_EWCR_EWIC; } else { - /* EWI comparator value different from 0, - * Enable the early wakeup interrupt + /* EWI comparator value different from 0, enable the early wakeup interrupt, * acknowledge the early wakeup interrupt in any cases. it clears the EWIF flag in SR register - * Set Watchdog Early Wakeup Comparator value - */ + * Set Watchdog Early Wakeup Comparator value */ hiwdg->Instance->EWCR = IWDG_EWCR_EWIE | IWDG_EWCR_EWIC | hiwdg->Init.EWI; } diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_iwdg.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_iwdg.h index 90f3f7eab15..2f67918fa5a 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_iwdg.h @@ -66,7 +66,7 @@ typedef struct typedef struct __IWDG_HandleTypeDef #else typedef struct -#endif /* (USE_HAL_IWDG_REGISTER_CALLBACKS) */ +#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */ { IWDG_TypeDef *Instance; /*!< Register base address */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_lptim.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_lptim.c index 749d5d264a1..184b4d0fca6 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_lptim.c @@ -107,13 +107,13 @@ The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback. - @ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle, + Use Function HAL_LPTIM_RegisterCallback() to register a callback. + HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the + Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. [..] These functions allow to register/unregister following callbacks: @@ -133,7 +133,7 @@ [..] By default, after the Init and when the state is HAL_LPTIM_STATE_RESET all interrupt callbacks are set to the corresponding weak functions: - examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback(). + examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback(). [..] Exception done for MspInit and MspDeInit functions that are reset to the legacy weak @@ -147,7 +147,7 @@ in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function. + using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function. [..] When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or @@ -187,14 +187,14 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_OC_ConfigTypeDef *sConfig); -static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_OC_ConfigTypeDef *sConfig); -static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_IC_ConfigTypeDef *sConfig); -static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_IC_ConfigTypeDef *sConfig); +static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig); +static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig); +static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig); +static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig); #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim); #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ -static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag); +static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag); void LPTIM_DMAError(DMA_HandleTypeDef *hdma); void LPTIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); void LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); @@ -422,8 +422,7 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim) hlptim->State = HAL_LPTIM_STATE_BUSY; __HAL_LPTIM_ENABLE(hlptim); - - if (hlptim->Instance != LPTIM4) + if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance)) { hlptim->Instance->CCMR1 = 0; } @@ -438,7 +437,7 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - if (hlptim->Instance != LPTIM4) + if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance)) { /* Clear flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK); @@ -568,26 +567,17 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Chan /* Check the parameters */ assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); - if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance)) + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) { - if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - /* Set the LPTIM channel state */ - LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + return HAL_ERROR; } - else - { - /* Check the LPTIM state */ - if (hlptim->State != HAL_LPTIM_STATE_READY) - { - return HAL_ERROR; - } - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - } + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); /* Reset WAVE bit to set PWM mode */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; @@ -601,7 +591,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Chan /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -622,7 +612,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Chann /* Check the parameters */ assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); - /* Set the LPTIM state */ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable LPTIM signal from the corresponding output pin */ @@ -631,16 +621,11 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Chann /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance)) - { - /* Set the LPTIM channel state */ - LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); - } - else - { - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - } + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; @@ -660,26 +645,17 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t C /* Check the parameters */ assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); - if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance)) + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) { - if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - /* Set the LPTIM channel state */ - LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + return HAL_ERROR; } - else - { - /* Check the LPTIM state */ - if (hlptim->State != HAL_LPTIM_STATE_READY) - { - return HAL_ERROR; - } - /* Set the TIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - } + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); /* Reset WAVE bit to set PWM mode */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; @@ -732,7 +708,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t C /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -753,7 +729,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Ch /* Check the parameters */ assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); - /* Set the LPTIM state */ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable LPTIM signal from the corresponding output pin */ @@ -809,16 +785,11 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Ch /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance)) - { - /* Set the LPTIM channel state */ - LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); - } - else - { - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - } + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; @@ -835,35 +806,32 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Ch * @param Length The length of data to be transferred from LPTIM peripheral to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, uint32_t *pData, +HAL_StatusTypeDef HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, const uint32_t *pData, uint32_t Length) { DMA_HandleTypeDef *hdma; /* Check the parameters */ + assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); - if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance)) + if ((pData == NULL) || (Length == 0U)) { - if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - /* Set the LPTIM channel state */ - LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + return HAL_ERROR; } - else - { - /* Check the LPTIM state */ - if (hlptim->State != HAL_LPTIM_STATE_READY) - { - return HAL_ERROR; - } - /* Set the TIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; } + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + /* Reset WAVE bit to set PWM mode */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; @@ -923,7 +891,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -942,9 +910,10 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) { /* Check the parameters */ + assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); - /* Set the LPTIM state */ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable update event DMA request */ @@ -970,16 +939,11 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t C /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance)) - { - /* Set the LPTIM channel state */ - LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); - } - else - { - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - } + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; @@ -999,26 +963,17 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Check the parameters */ assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); - if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance)) + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) { - if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - /* Set the LPTIM channel state */ - LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + return HAL_ERROR; } - else - { - /* Check the LPTIM state */ - if (hlptim->State != HAL_LPTIM_STATE_READY) - { - return HAL_ERROR; - } - /* Set the TIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - } + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); /* Reset WAVE bit to set one pulse mode */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; @@ -1032,7 +987,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1062,16 +1017,11 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance)) - { - /* Set the LPTIM channel state */ - LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); - } - else - { - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - } + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; @@ -1091,26 +1041,17 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3 /* Check the parameters */ assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); - if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance)) + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) { - if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - /* Set the LPTIM channel state */ - LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + return HAL_ERROR; } - else - { - /* Check the LPTIM state */ - if (hlptim->State != HAL_LPTIM_STATE_READY) - { - return HAL_ERROR; - } - /* Set the TIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - } + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); /* Reset WAVE bit to set one pulse mode */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; @@ -1163,7 +1104,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3 /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1239,16 +1180,11 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance)) - { - /* Set the LPTIM channel state */ - LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); - } - else - { - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - } + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; @@ -1268,26 +1204,17 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Check the parameters */ assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); - if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance)) + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) { - if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - /* Set the LPTIM channel state */ - LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + return HAL_ERROR; } - else - { - /* Check the LPTIM state */ - if (hlptim->State != HAL_LPTIM_STATE_READY) - { - return HAL_ERROR; - } - /* Set the TIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - } + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); /* Set WAVE bit to enable the set once mode */ hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; @@ -1301,7 +1228,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1331,16 +1258,11 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t C /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance)) - { - /* Set the LPTIM channel state */ - LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); - } - else - { - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - } + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; @@ -1360,26 +1282,17 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Check the parameters */ assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); - if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance)) + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) { - if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - /* Set the LPTIM channel state */ - LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + return HAL_ERROR; } - else - { - /* Check the LPTIM state */ - if (hlptim->State != HAL_LPTIM_STATE_READY) - { - return HAL_ERROR; - } - /* Set the TIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - } + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); /* Set WAVE bit to enable the set once mode */ hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; @@ -1430,7 +1343,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1504,16 +1417,11 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_ /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance)) - { - /* Set the LPTIM channel state */ - LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); - } - else - { - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - } + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; @@ -1558,7 +1466,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim) /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1584,7 +1492,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) /* Reset ENC bit to disable the encoder interface */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1644,7 +1552,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim) /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1687,7 +1595,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1733,7 +1641,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1759,7 +1667,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) /* Reset TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1817,7 +1725,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1861,7 +1769,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1897,7 +1805,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim) /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1920,7 +1828,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1968,7 +1876,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim) /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -2010,7 +1918,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -2028,29 +1936,21 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) */ HAL_StatusTypeDef HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) { + /* Check the parameters */ assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_CHANNELS(hlptim->Instance, Channel)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); - if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance)) + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) { - if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - /* Set the LPTIM channel state */ - LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + return HAL_ERROR; } - else - { - /* Check the LPTIM state */ - if (hlptim->State != HAL_LPTIM_STATE_READY) - { - return HAL_ERROR; - } - /* Set the TIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - } + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); @@ -2061,6 +1961,9 @@ HAL_StatusTypeDef HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Chann /* Enable capture */ __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel); + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } @@ -2076,8 +1979,12 @@ HAL_StatusTypeDef HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Chann */ HAL_StatusTypeDef HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) { + /* Check the parameters */ assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_CHANNELS(hlptim->Instance, Channel)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable capture */ __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel); @@ -2088,6 +1995,9 @@ HAL_StatusTypeDef HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channe /* Set the LPTIM channel state */ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } @@ -2103,29 +2013,21 @@ HAL_StatusTypeDef HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channe */ HAL_StatusTypeDef HAL_LPTIM_IC_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) { + /* Check the parameters */ assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_CHANNELS(hlptim->Instance, Channel)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); - if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance)) + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) { - if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - /* Set the LPTIM channel state */ - LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + return HAL_ERROR; } - else - { - /* Check the LPTIM state */ - if (hlptim->State != HAL_LPTIM_STATE_READY) - { - return HAL_ERROR; - } - /* Set the TIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - } + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); @@ -2156,6 +2058,9 @@ HAL_StatusTypeDef HAL_LPTIM_IC_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Ch /* Enable capture */ __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel); + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } @@ -2171,8 +2076,12 @@ HAL_StatusTypeDef HAL_LPTIM_IC_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Ch */ HAL_StatusTypeDef HAL_LPTIM_IC_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) { + /* Check the parameters */ assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_CHANNELS(hlptim->Instance, Channel)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; switch (Channel) { @@ -2197,6 +2106,9 @@ HAL_StatusTypeDef HAL_LPTIM_IC_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Cha /* Set the LPTIM channel state */ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } @@ -2217,30 +2129,27 @@ HAL_StatusTypeDef HAL_LPTIM_IC_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t C { DMA_HandleTypeDef *hdma; + /* Check the parameters */ assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_CHANNELS(hlptim->Instance, Channel)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); - if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance)) + if ((pData == NULL) || (Length == 0U)) { - if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - /* Set the LPTIM channel state */ - LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + return HAL_ERROR; } - else - { - /* Check the LPTIM state */ - if (hlptim->State != HAL_LPTIM_STATE_READY) - { - return HAL_ERROR; - } - /* Set the TIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; } + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); @@ -2302,6 +2211,9 @@ HAL_StatusTypeDef HAL_LPTIM_IC_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t C /* Enable capture */ __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel); + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } @@ -2317,8 +2229,12 @@ HAL_StatusTypeDef HAL_LPTIM_IC_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t C */ HAL_StatusTypeDef HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) { + /* Check the parameters */ assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_CHANNELS(hlptim->Instance, Channel)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; switch (Channel) { @@ -2347,6 +2263,9 @@ HAL_StatusTypeDef HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Ch /* Set the LPTIM channel state */ LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } @@ -2374,7 +2293,7 @@ HAL_StatusTypeDef HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Ch * @param hlptim LPTIM handle * @retval Counter value. */ -uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim) +uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -2387,7 +2306,7 @@ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim) * @param hlptim LPTIM handle * @retval Autoreload value. */ -uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim) +uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -2404,7 +2323,7 @@ uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim) * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected * @retval Compare value. */ -uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +uint32_t HAL_LPTIM_ReadCapturedValue(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel) { uint32_t tmpccr; @@ -2426,6 +2345,41 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) return tmpccr; } +/** + * @brief LPTimer Input Capture Get Offset(in counter step unit) + * @note The real capture value corresponding to the input capture trigger can be calculated using + * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset + * The Offset value is depending on the glitch filter value for the channel + * and the value of the prescaler for the kernel clock. + * Please check Errata Sheet V1_8 for more details under "variable latency + * on input capture channel" section. + * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @param Channel This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval The offset value + */ +uint8_t HAL_LPTIM_IC_GetOffset(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + + uint8_t offset ; + uint32_t prescaler; + uint32_t filter ; + + /* Get prescaler value */ + prescaler = LL_LPTIM_GetPrescaler(hlptim->Instance); + + /* Get filter value */ + filter = LL_LPTIM_IC_GetFilter(hlptim->Instance, Channel); + + /* Get offset value */ + offset = LL_LPTIM_IC_GET_OFFSET(prescaler, filter); + + /* return offset value */ + return offset; +} + /** * @} */ @@ -2450,14 +2404,19 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) * This parameter can be one of the following values: * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @note Successive calls to HAL_LPTIM_OC_ConfigChannel can only be performed + * after a delay that must be greater or equal than the value of + * (PRESC x 3) kernel clock cycles, PRESC[2:0] being the clock decimal + * division factor (1, 2, 4, ..., 128). Any successive call violating + * this delay, leads to unpredictable results. * @retval HAL status */ -HAL_StatusTypeDef HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, LPTIM_OC_ConfigTypeDef *sConfig, +HAL_StatusTypeDef HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status; /* Check the parameters */ - assert_param(IS_LPTIM_CHANNELS(hlptim->Instance, Channel)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); assert_param(IS_LPTIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_LPTIM_PULSE(sConfig->Pulse)); @@ -2495,7 +2454,7 @@ HAL_StatusTypeDef HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, LPTIM_ break; } - /* Change the LPTIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -2510,13 +2469,18 @@ HAL_StatusTypeDef HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, LPTIM_ * This parameter can be one of the following values: * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @note Successive calls to HAL_LPTIM_IC_ConfigChannel can only be performed + * after a delay that must be greater or equal than the value of + * (PRESC x 3) kernel clock cycles, PRESC[2:0] being the clock decimal + * division factor (1, 2, 4, ..., 128). Any successive call violating + * this delay, leads to unpredictable results. * @retval HAL status */ -HAL_StatusTypeDef HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, LPTIM_IC_ConfigTypeDef *sConfig, +HAL_StatusTypeDef HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_LPTIM_CHANNELS(hlptim->Instance, Channel)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); assert_param(IS_LPTIM_IC_PRESCALER(sConfig->ICPrescaler)); assert_param(IS_LPTIM_IC_POLARITY(sConfig->ICPolarity)); assert_param(IS_LPTIM_IC_FILTER(sConfig->ICFilter)); @@ -2549,7 +2513,7 @@ HAL_StatusTypeDef HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, LPTIM_ break; } - /* Change the LPTIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; @@ -3067,10 +3031,10 @@ __weak void HAL_LPTIM_ErrorCallback(LPTIM_HandleTypeDef *hlptim) * @arg @ref HAL_LPTIM_UPDATE_EVENT_CB_ID Update event detection Callback ID * @arg @ref HAL_LPTIM_REP_COUNTER_WRITE_CB_ID Repetition counter register write complete Callback ID * @arg @ref HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID Update event Half detection Callback ID + * @arg @ref HAL_LPTIM_ERROR_CB_ID Error Callback ID * @arg @ref HAL_LPTIM_IC_CAPTURE_CB_ID Input Capture Callback ID * @arg @ref HAL_LPTIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID * @arg @ref HAL_LPTIM_OVER_CAPTURE_CB_ID Over Capture Callback ID - * @arg @ref HAL_LPTIM_ERROR_CB_ID Error Callback ID * @param pCallback pointer to the callback function * @retval status */ @@ -3085,9 +3049,6 @@ HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hlptim); - if (hlptim->State == HAL_LPTIM_STATE_READY) { switch (CallbackID) @@ -3140,6 +3101,10 @@ HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, hlptim->UpdateEventHalfCpltCallback = pCallback; break; + case HAL_LPTIM_ERROR_CB_ID : + hlptim->ErrorCallback = pCallback; + break; + case HAL_LPTIM_IC_CAPTURE_CB_ID : hlptim->IC_CaptureCallback = pCallback; break; @@ -3152,10 +3117,6 @@ HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, hlptim->IC_OverCaptureCallback = pCallback; break; - case HAL_LPTIM_ERROR_CB_ID : - hlptim->ErrorCallback = pCallback; - break; - default : /* Return error status */ status = HAL_ERROR; @@ -3186,9 +3147,6 @@ HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hlptim); - return status; } @@ -3209,6 +3167,11 @@ HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID * @arg @ref HAL_LPTIM_UPDATE_EVENT_CB_ID Update event detection Callback ID * @arg @ref HAL_LPTIM_REP_COUNTER_WRITE_CB_ID Repetition counter register write complete Callback ID + * @arg @ref HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID Update event Half detection Callback ID + * @arg @ref HAL_LPTIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_LPTIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_LPTIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_LPTIM_OVER_CAPTURE_CB_ID Over Capture Callback ID * @retval status */ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, @@ -3216,9 +3179,6 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hlptim); - if (hlptim->State == HAL_LPTIM_STATE_READY) { switch (CallbackID) @@ -3283,6 +3243,11 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti hlptim->UpdateEventHalfCpltCallback = HAL_LPTIM_UpdateEventHalfCpltCallback; break; + case HAL_LPTIM_ERROR_CB_ID : + /* Legacy weak error Callback */ + hlptim->ErrorCallback = HAL_LPTIM_ErrorCallback; + break; + case HAL_LPTIM_IC_CAPTURE_CB_ID : /* Legacy weak IC Capture Callback */ hlptim->IC_CaptureCallback = HAL_LPTIM_IC_CaptureCallback; @@ -3330,9 +3295,6 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hlptim); - return status; } #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ @@ -3360,7 +3322,7 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti * @param hlptim LPTIM handle * @retval HAL state */ -HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim) +HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim) { /* Return LPTIM handle state */ return hlptim->State; @@ -3414,7 +3376,7 @@ static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim) * @param flag The lptim flag * @retval HAL status */ -static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag) +static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag) { HAL_StatusTypeDef result = HAL_OK; uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL); @@ -3586,7 +3548,7 @@ void LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef *hdma) * @param sConfig The output configuration structure * @retval None */ -static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_OC_ConfigTypeDef *sConfig) +static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig) { uint32_t tmpccmr1; uint32_t tmpcfgr; @@ -3639,7 +3601,7 @@ static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_ * @param sConfig The output configuration structure * @retval None */ -static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_OC_ConfigTypeDef *sConfig) +static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig) { uint32_t tmpccmr1; @@ -3678,7 +3640,7 @@ static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_ * @param sConfig The input configuration structure * @retval None */ -static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_IC_ConfigTypeDef *sConfig) +static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig) { uint32_t tmpccmr1; uint32_t tmpcfgr2; @@ -3708,7 +3670,7 @@ static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_IC_ConfigType * @param sConfig The input configuration structure * @retval None */ -static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_IC_ConfigTypeDef *sConfig) +static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig) { uint32_t tmpccmr1; uint32_t tmpcfgr2; diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_lptim.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_lptim.h index e5326e29401..d663aa9420b 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_lptim.h @@ -27,6 +27,9 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32u5xx_hal_def.h" +/* Include low level driver */ +#include "stm32u5xx_ll_lptim.h" + /** @addtogroup STM32U5xx_HAL_Driver * @{ */ @@ -104,7 +107,7 @@ typedef struct uint32_t Period; /*!< Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter can be a number between - Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + Min_Data = 0x0001 and Max_Data = 0xFFFF. */ uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare values is done immediately or after the end of current period. @@ -230,10 +233,10 @@ typedef struct void (* UpdateEventCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Update event detection Callback */ void (* RepCounterWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Repetition counter register write complete Callback */ void (* UpdateEventHalfCpltCallback)(struct __LPTIM_HandleTypeDef *hlptim);/*!< Update event half complete detection Callback */ + void (* ErrorCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Error Callback */ void (* IC_CaptureCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Input capture Callback */ void (* IC_CaptureHalfCpltCallback)(struct __LPTIM_HandleTypeDef *htim); /*!< Input Capture half complete Callback */ void (* IC_OverCaptureCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Over capture Callback */ - void (* ErrorCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Error Callback */ #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } LPTIM_HandleTypeDef; @@ -255,10 +258,10 @@ typedef enum HAL_LPTIM_UPDATE_EVENT_CB_ID = 0x09U, /*!< Update event detection Callback ID */ HAL_LPTIM_REP_COUNTER_WRITE_CB_ID = 0x0AU, /*!< Repetition counter register write complete Callback ID */ HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID = 0x0BU, /*!< Update event half complete detection Callback ID */ - HAL_LPTIM_IC_CAPTURE_CB_ID = 0x0CU, /*!< Input capture Callback ID */ - HAL_LPTIM_IC_CAPTURE_HALF_CB_ID = 0x0DU, /*!< Input capture half complete Callback ID */ - HAL_LPTIM_OVER_CAPTURE_CB_ID = 0x0EU, /*!< Over capture Callback ID */ - HAL_LPTIM_ERROR_CB_ID = 0x0FU, /*!< LPTIM Error Callback ID */ + HAL_LPTIM_ERROR_CB_ID = 0x0CU, /*!< LPTIM Error Callback ID */ + HAL_LPTIM_IC_CAPTURE_CB_ID = 0x0DU, /*!< Input capture Callback ID */ + HAL_LPTIM_IC_CAPTURE_HALF_CB_ID = 0x0EU, /*!< Input capture half complete Callback ID */ + HAL_LPTIM_OVER_CAPTURE_CB_ID = 0x0FU, /*!< Over capture Callback ID */ } HAL_LPTIM_CallbackIDTypeDef; /** @@ -464,9 +467,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin /** @defgroup LPTIM_Channel LPTIM Channel * @{ */ -#define LPTIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ -#define LPTIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ -#define LPTIM_CHANNEL_ALL 0x00000013U /*!< Global Capture/compare channel identifier */ +#define LPTIM_CHANNEL_1 LL_LPTIM_CHANNEL_CH1 /*!< Capture/compare channel 1 identifier */ +#define LPTIM_CHANNEL_2 LL_LPTIM_CHANNEL_CH2 /*!< Capture/compare channel 2 identifier */ /** * @} */ @@ -703,10 +705,15 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag. - * @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag. + * @arg LPTIM_FLAG_CMP1OK : Compare register 1 update OK Flag. + * @arg LPTIM_FLAG_CMP2OK : Compare register 2 update OK Flag. * @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag. * @arg LPTIM_FLAG_ARRM : Autoreload match Flag. - * @arg LPTIM_FLAG_CMPM : Compare match Flag. + * @arg LPTIM_FLAG_CC1 : Capture/Compare 1 interrupt flag. + * @arg LPTIM_FLAG_CC2 : Capture/Compare 2 interrupt flag. + * @arg LPTIM_FLAG_CC1O : Capture/Compare 1 over-capture flag. + * @arg LPTIM_FLAG_CC2O : Capture/Compare 2 over-capture flag. + * @arg LPTIM_FLAG_DIEROK : DMA & interrupt enable update OK flag. * @retval The state of the specified flag (SET or RESET). */ #define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__)) @@ -721,10 +728,15 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag. - * @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag. + * @arg LPTIM_FLAG_CMP1OK : Compare register 1 update OK Flag. + * @arg LPTIM_FLAG_CMP2OK : Compare register 2 update OK Flag. * @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag. * @arg LPTIM_FLAG_ARRM : Autoreload match Flag. - * @arg LPTIM_FLAG_CMPM : Compare match Flag. + * @arg LPTIM_FLAG_CC1 : Capture/Compare 1 interrupt flag. + * @arg LPTIM_FLAG_CC2 : Capture/Compare 2 interrupt flag. + * @arg LPTIM_FLAG_CC1O : Capture/Compare 1 over-capture flag. + * @arg LPTIM_FLAG_CC2O : Capture/Compare 2 over-capture flag. + * @arg LPTIM_FLAG_DIEROK : DMA & interrupt enable update OK flag. * @retval None. */ #define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) @@ -739,10 +751,14 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt. - * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt. + * @arg LPTIM_IT_CMP1OK : Compare register 1 update OK Interrupt. + * @arg LPTIM_IT_CMP2OK : Compare register 2 update OK Interrupt. * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt. * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. - * @arg LPTIM_IT_CMPM : Compare match Interrupt. + * @arg LPTIM_IT_CC1 : Capture/Compare 1 interrupt Interrupt. + * @arg LPTIM_IT_CC2 : Capture/Compare 2 interrupt Interrupt. + * @arg LPTIM_IT_CC1O : Capture/Compare 1 over-capture Interrupt. + * @arg LPTIM_IT_CC2O : Capture/Compare 2 over-capture Interrupt. * @retval None. * @note The LPTIM interrupts can only be enabled when the LPTIM instance is enabled. */ @@ -758,10 +774,14 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt. - * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt. + * @arg LPTIM_IT_CMP1OK : Compare register 1 update OK Interrupt. + * @arg LPTIM_IT_CMP2OK : Compare register 2 update OK Interrupt. * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt. * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. - * @arg LPTIM_IT_CMPM : Compare match Interrupt. + * @arg LPTIM_IT_CC1 : Capture/Compare 1 interrupt Interrupt. + * @arg LPTIM_IT_CC2 : Capture/Compare 2 interrupt Interrupt. + * @arg LPTIM_IT_CC1O : Capture/Compare 1 over-capture Interrupt. + * @arg LPTIM_IT_CC2O : Capture/Compare 2 over-capture Interrupt. * @retval None. * @note The LPTIM interrupts can only be disabled when the LPTIM instance is enabled. */ @@ -799,10 +819,14 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt. - * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt. + * @arg LPTIM_IT_CMP1OK : Compare register 1 update OK Interrupt. + * @arg LPTIM_IT_CMP2OK : Compare register 2 update OK Interrupt. * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt. * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. - * @arg LPTIM_IT_CMPM : Compare match Interrupt. + * @arg LPTIM_IT_CC1 : Capture/Compare 1 interrupt Interrupt. + * @arg LPTIM_IT_CC2 : Capture/Compare 2 interrupt Interrupt. + * @arg LPTIM_IT_CC1O : Capture/Compare 1 over-capture Interrupt. + * @arg LPTIM_IT_CC2O : Capture/Compare 2 over-capture Interrupt. * @retval Interrupt status. */ @@ -838,7 +862,7 @@ void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim); * @{ */ /* Config functions **********************************************************/ -HAL_StatusTypeDef HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, LPTIM_OC_ConfigTypeDef *sConfig, +HAL_StatusTypeDef HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig, uint32_t Channel); /* Start/Stop operation functions *********************************************/ @@ -849,7 +873,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Chann /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); -HAL_StatusTypeDef HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, uint32_t *pData, +HAL_StatusTypeDef HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, const uint32_t *pData, uint32_t Length); HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); @@ -895,7 +919,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim); /* ############################## Input Capture Mode ###############################*/ /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, LPTIM_IC_ConfigTypeDef *sConfig, +HAL_StatusTypeDef HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); HAL_StatusTypeDef HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); @@ -914,9 +938,10 @@ HAL_StatusTypeDef HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Ch * @{ */ /* Reading operation functions ************************************************/ -uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim); -uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim); -uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadCapturedValue(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +uint8_t HAL_LPTIM_IC_GetOffset(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel); /** * @} */ @@ -959,7 +984,7 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_ * @{ */ /* Peripheral State functions ************************************************/ -HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); +HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); /** * @} */ @@ -1048,17 +1073,16 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) -#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL) +#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) &&\ + ((__AUTORELOAD__) <= 0x0000FFFFUL)) #define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL) -#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL) +#define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\ + ((__PERIOD__) <= 0x0000FFFFUL)) #define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL) -#define IS_LPTIM_CHANNELS(__INSTANCE__, __CHANNEL__) (((__CHANNEL__) == LPTIM_CHANNEL_1) || \ - ((__CHANNEL__) == LPTIM_CHANNEL_2)) - #define IS_LPTIM_OC_POLARITY(__OCPOLARITY__) (((__OCPOLARITY__) == LPTIM_OCPOLARITY_LOW) || \ ((__OCPOLARITY__) == LPTIM_OCPOLARITY_HIGH)) #define IS_LPTIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_ICPSC_DIV1) ||\ @@ -1132,18 +1156,15 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); #define IS_LPTIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \ (((((__INSTANCE__) == LPTIM1_NS) || ((__INSTANCE__) == LPTIM1_S)) && \ (((__CHANNEL__) == LPTIM_CHANNEL_1) || \ - ((__CHANNEL__) == LPTIM_CHANNEL_2) || \ - ((__CHANNEL__) == LPTIM_CHANNEL_ALL))) \ + ((__CHANNEL__) == LPTIM_CHANNEL_2))) \ || \ ((((__INSTANCE__) == LPTIM2_NS) || ((__INSTANCE__) == LPTIM2_S)) && \ (((__CHANNEL__) == LPTIM_CHANNEL_1) || \ - ((__CHANNEL__) == LPTIM_CHANNEL_2) || \ - ((__CHANNEL__) == LPTIM_CHANNEL_ALL))) \ + ((__CHANNEL__) == LPTIM_CHANNEL_2))) \ || \ ((((__INSTANCE__) == LPTIM3_NS) || ((__INSTANCE__) == LPTIM3_S)) && \ (((__CHANNEL__) == LPTIM_CHANNEL_1) || \ - ((__CHANNEL__) == LPTIM_CHANNEL_2) || \ - ((__CHANNEL__) == LPTIM_CHANNEL_ALL))) \ + ((__CHANNEL__) == LPTIM_CHANNEL_2))) \ || \ ((((__INSTANCE__) == LPTIM4_NS) || ((__INSTANCE__) == LPTIM4_S)) && \ ((__CHANNEL__) == LPTIM_CHANNEL_1))) diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc.c new file mode 100644 index 00000000000..6e63a65f408 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc.c @@ -0,0 +1,2215 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_ltdc.c + * @author MCD Application Team + * @brief LTDC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the LTDC peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LTDC HAL driver can be used as follows: + + (#) Declare a LTDC_HandleTypeDef handle structure, for example: LTDC_HandleTypeDef hltdc; + + (#) Initialize the LTDC low level resources by implementing the HAL_LTDC_MspInit() API: + (##) Enable the LTDC interface clock + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the LTDC interrupt priority + (+++) Enable the NVIC LTDC IRQ Channel + + (#) Initialize the required configuration through the following parameters: + the LTDC timing, the horizontal and vertical polarity, the pixel clock polarity, + Data Enable polarity and the LTDC background color value using HAL_LTDC_Init() function + + *** Configuration *** + ========================= + [..] + (#) Program the required configuration through the following parameters: + the pixel format, the blending factors, input alpha value, the window size + and the image size using HAL_LTDC_ConfigLayer() function for foreground + or/and background layer. + + (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and + HAL_LTDC_EnableCLUT functions. + + (#) Optionally, enable the Dither using HAL_LTDC_EnableDither(). + + (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying() + and HAL_LTDC_EnableColorKeying functions. + + (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent() + function + + (#) If needed, reconfigure and change the pixel format value, the alpha value + value, the window size, the window position and the layer start address + for foreground or/and background layer using respectively the following + functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(), + HAL_LTDC_SetWindowPosition() and HAL_LTDC_SetAddress(). + + (#) Variant functions with _NoReload suffix allows to set the LTDC configuration/settings without immediate reload. + This is useful in case when the program requires to modify serval LTDC settings (on one or both layers) + then applying(reload) these settings in one shot by calling the function HAL_LTDC_Reload(). + + After calling the _NoReload functions to set different color/format/layer settings, + the program shall call the function HAL_LTDC_Reload() to apply(reload) these settings. + Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_IMMEDIATE if + an immediate reload is required. + Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_VERTICAL_BLANKING if + the reload should be done in the next vertical blanking period, + this option allows to avoid display flicker by applying the new settings during the vertical blanking period. + + + (#) To control LTDC state you can use the following function: HAL_LTDC_GetState() + + *** LTDC HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in LTDC HAL driver. + + (+) __HAL_LTDC_ENABLE: Enable the LTDC. + (+) __HAL_LTDC_DISABLE: Disable the LTDC. + (+) __HAL_LTDC_LAYER_ENABLE: Enable an LTDC Layer. + (+) __HAL_LTDC_LAYER_DISABLE: Disable an LTDC Layer. + (+) __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG: Reload Layer Configuration. + (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags. + (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags. + (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts. + (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts. + (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not. + + [..] + (@) You can refer to the LTDC HAL driver header file for more useful macros + + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_LTDC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use function HAL_LTDC_RegisterCallback() to register a callback. + + [..] + Function HAL_LTDC_RegisterCallback() allows to register following callbacks: + (+) LineEventCallback : LTDC Line Event Callback. + (+) ReloadEventCallback : LTDC Reload Event Callback. + (+) ErrorCallback : LTDC Error Callback + (+) MspInitCallback : LTDC MspInit. + (+) MspDeInitCallback : LTDC MspDeInit. + [..] + This function takes as parameters the HAL peripheral handle, the callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_LTDC_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_LTDC_UnRegisterCallback() takes as parameters the HAL peripheral handle + and the callback ID. + [..] + This function allows to reset following callbacks: + (+) LineEventCallback : LTDC Line Event Callback + (+) ReloadEventCallback : LTDC Reload Event Callback + (+) ErrorCallback : LTDC Error Callback + (+) MspInitCallback : LTDC MspInit + (+) MspDeInitCallback : LTDC MspDeInit. + + [..] + By default, after the HAL_LTDC_Init and when the state is HAL_LTDC_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_LTDC_LineEventCallback(), HAL_LTDC_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak (surcharged) functions in the HAL_LTDC_Init() and HAL_LTDC_DeInit() + only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_LTDC_Init() and HAL_LTDC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_LTDC_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_LTDC_STATE_READY or HAL_LTDC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_LTDC_RegisterCallback() before calling HAL_LTDC_DeInit() + or HAL_LTDC_Init() function. + + [..] + When the compilation define USE_HAL_LTDC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +#ifdef HAL_LTDC_MODULE_ENABLED + +#if defined (LTDC) + +/** @defgroup LTDC LTDC + * @brief LTDC HAL module driver + * @{ + */ + + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define LTDC_TIMEOUT_VALUE ((uint32_t)100U) /* 100ms */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup LTDC_Exported_Functions LTDC Exported Functions + * @{ + */ + +/** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the LTDC + (+) De-initialize the LTDC + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) +{ + uint32_t tmp; + uint32_t tmp1; + + /* Check the LTDC peripheral state */ + if (hltdc == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance)); + assert_param(IS_LTDC_HSYNC(hltdc->Init.HorizontalSync)); + assert_param(IS_LTDC_VSYNC(hltdc->Init.VerticalSync)); + assert_param(IS_LTDC_AHBP(hltdc->Init.AccumulatedHBP)); + assert_param(IS_LTDC_AVBP(hltdc->Init.AccumulatedVBP)); + assert_param(IS_LTDC_AAH(hltdc->Init.AccumulatedActiveH)); + assert_param(IS_LTDC_AAW(hltdc->Init.AccumulatedActiveW)); + assert_param(IS_LTDC_TOTALH(hltdc->Init.TotalHeigh)); + assert_param(IS_LTDC_TOTALW(hltdc->Init.TotalWidth)); + assert_param(IS_LTDC_HSPOL(hltdc->Init.HSPolarity)); + assert_param(IS_LTDC_VSPOL(hltdc->Init.VSPolarity)); + assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity)); + assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity)); + +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + if (hltdc->State == HAL_LTDC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hltdc->Lock = HAL_UNLOCKED; + + /* Reset the LTDC callback to the legacy weak callbacks */ + hltdc->LineEventCallback = HAL_LTDC_LineEventCallback; /* Legacy weak LineEventCallback */ + hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback; /* Legacy weak ReloadEventCallback */ + hltdc->ErrorCallback = HAL_LTDC_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hltdc->MspInitCallback == NULL) + { + hltdc->MspInitCallback = HAL_LTDC_MspInit; + } + /* Init the low level hardware */ + hltdc->MspInitCallback(hltdc); + } +#else + if (hltdc->State == HAL_LTDC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hltdc->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ + HAL_LTDC_MspInit(hltdc); + } +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Configure the HS, VS, DE and PC polarity */ + hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL); + hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \ + hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); + + /* Set Synchronization size */ + hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW); + tmp = (hltdc->Init.HorizontalSync << 16U); + hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync); + + /* Set Accumulated Back porch */ + hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP); + tmp = (hltdc->Init.AccumulatedHBP << 16U); + hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP); + + /* Set Accumulated Active Width */ + hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW); + tmp = (hltdc->Init.AccumulatedActiveW << 16U); + hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH); + + /* Set Total Width */ + hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW); + tmp = (hltdc->Init.TotalWidth << 16U); + hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh); + + /* Set the background color value */ + tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U); + tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U); + hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED); + hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue); + + /* Enable the Transfer Error and FIFO underrun interrupts */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU); + + /* Enable LTDC by setting LTDCEN bit */ + __HAL_LTDC_ENABLE(hltdc); + + /* Initialize the error code */ + hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-initialize the LTDC peripheral. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ + +HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc) +{ + uint32_t tickstart; + + /* Check the LTDC peripheral state */ + if (hltdc == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance)); + + /* Disable LTDC Layer 1 */ + __HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_1); + +#if defined(LTDC_Layer2_BASE) + /* Disable LTDC Layer 2 */ + __HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_2); +#endif /* LTDC_Layer2_BASE */ + + /* Reload during vertical blanking period */ + __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(hltdc); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for VSYNC Interrupt */ + while (READ_BIT(hltdc->Instance->CDSR, LTDC_CDSR_VSYNCS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > LTDC_TIMEOUT_VALUE) + { + break; + } + } + + /* Disable LTDC */ + __HAL_LTDC_DISABLE(hltdc); + +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + if (hltdc->MspDeInitCallback == NULL) + { + hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; + } + /* DeInit the low level hardware */ + hltdc->MspDeInitCallback(hltdc); +#else + /* DeInit the low level hardware */ + HAL_LTDC_MspDeInit(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + + /* Initialize the error code */ + hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Initialize the LTDC MSP. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-initialize the LTDC MSP. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User LTDC Callback + * To be used instead of the weak predefined callback + * @param hltdc ltdc handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID + * @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID + * @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, + pLTDC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hltdc); + + if (hltdc->State == HAL_LTDC_STATE_READY) + { + switch (CallbackID) + { + case HAL_LTDC_LINE_EVENT_CB_ID : + hltdc->LineEventCallback = pCallback; + break; + + case HAL_LTDC_RELOAD_EVENT_CB_ID : + hltdc->ReloadEventCallback = pCallback; + break; + + case HAL_LTDC_ERROR_CB_ID : + hltdc->ErrorCallback = pCallback; + break; + + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = pCallback; + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hltdc->State == HAL_LTDC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = pCallback; + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hltdc); + + return status; +} + +/** + * @brief Unregister an LTDC Callback + * LTDC callback is redirected to the weak predefined callback + * @param hltdc ltdc handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID + * @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID + * @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hltdc); + + if (hltdc->State == HAL_LTDC_STATE_READY) + { + switch (CallbackID) + { + case HAL_LTDC_LINE_EVENT_CB_ID : + hltdc->LineEventCallback = HAL_LTDC_LineEventCallback; /* Legacy weak LineEventCallback */ + break; + + case HAL_LTDC_RELOAD_EVENT_CB_ID : + hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback; /* Legacy weak ReloadEventCallback */ + break; + + case HAL_LTDC_ERROR_CB_ID : + hltdc->ErrorCallback = HAL_LTDC_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */ + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; /* Legcay weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hltdc->State == HAL_LTDC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */ + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; /* Legcay weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hltdc); + + return status; +} +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides function allowing to: + (+) Handle LTDC interrupt request + +@endverbatim + * @{ + */ +/** + * @brief Handle LTDC interrupt request. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ +void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc) +{ + uint32_t isrflags = READ_REG(hltdc->Instance->ISR); + uint32_t itsources = READ_REG(hltdc->Instance->IER); + + /* Transfer Error Interrupt management ***************************************/ + if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U)) + { + /* Disable the transfer Error interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE); + + /* Clear the transfer error flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE); + + /* Update error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_TE; + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Transfer error Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + hltdc->ErrorCallback(hltdc); +#else + /* Call legacy error callback*/ + HAL_LTDC_ErrorCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + } + + /* FIFO underrun Interrupt management ***************************************/ + if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U)) + { + /* Disable the FIFO underrun interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU); + + /* Clear the FIFO underrun flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU); + + /* Update error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_FU; + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Transfer error Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + hltdc->ErrorCallback(hltdc); +#else + /* Call legacy error callback*/ + HAL_LTDC_ErrorCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + } + + /* Line Interrupt management ************************************************/ + if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U)) + { + /* Disable the Line interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI); + + /* Clear the Line interrupt flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI); + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Line interrupt Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered Line Event callback */ + hltdc->LineEventCallback(hltdc); +#else + /*Call Legacy Line Event callback */ + HAL_LTDC_LineEventCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + } + + /* Register reload Interrupt management ***************************************/ + if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U)) + { + /* Disable the register reload interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR); + + /* Clear the register reload flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR); + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Reload interrupt Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered reload Event callback */ + hltdc->ReloadEventCallback(hltdc); +#else + /*Call Legacy Reload Event callback */ + HAL_LTDC_ReloadEventCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Error LTDC callback. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Line Event callback. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_LineEventCallback could be implemented in the user file + */ +} + +/** + * @brief Reload Event callback. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_ReloadEvenCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the LTDC foreground or/and background parameters. + (+) Set the active layer. + (+) Configure the color keying. + (+) Configure the C-LUT. + (+) Enable / Disable the color keying. + (+) Enable / Disable the C-LUT. + (+) Update the layer position. + (+) Update the layer size. + (+) Update pixel format on the fly. + (+) Update transparency on the fly. + (+) Update address on the fly. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the LTDC Layer according to the specified + * parameters in the LTDC_InitTypeDef and create the associated handle. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains + * the configuration information for the Layer. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); + assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); + assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); + assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); + assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0)); + assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1)); + assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); + assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); + assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Copy new layer configuration into handle structure */ + hltdc->LayerCfg[LayerIdx] = *pLayerCfg; + + /* Configure the LTDC Layer */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Configure the color keying. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param RGBValue the color key value + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Configure the default color values */ + LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); + LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Load the color lookup table. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pCLUT pointer to the color lookup table address. + * @param CLUTSize the color lookup table size. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx) +{ + uint32_t tmp; + uint32_t counter; + uint32_t *pcolorlut = pCLUT; + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + for (counter = 0U; (counter < CLUTSize); counter++) + { + if (hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44) + { + tmp = (((counter + (16U * counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \ + ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); + } + else + { + tmp = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \ + ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); + } + + pcolorlut++; + + /* Specifies the C-LUT address and RGB value */ + LTDC_LAYER(hltdc, LayerIdx)->CLUTWR = tmp; + } + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color keying. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color keying. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color lookup table. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color lookup table. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable Dither. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc) +{ + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable Dither by setting DTEN bit */ + LTDC->GCR |= (uint32_t)LTDC_GCR_DEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable Dither. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc) +{ + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable Dither by setting DTEN bit */ + LTDC->GCR &= ~(uint32_t)LTDC_GCR_DEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window size. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param XSize LTDC Pixel per line + * @param YSize LTDC Line number + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters (Layers parameters)*/ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(XSize)); + assert_param(IS_LTDC_CFBLNBR(YSize)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal stop */ + pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0; + + /* update vertical stop */ + pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0; + + /* Reconfigures the color frame buffer pitch in byte */ + pLayerCfg->ImageWidth = XSize; + + /* Reconfigures the frame buffer line number */ + pLayerCfg->ImageHeight = YSize; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window position. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param X0 LTDC window X offset + * @param Y0 LTDC window Y offset + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(X0)); + assert_param(IS_LTDC_CFBLNBR(Y0)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal start/stop */ + pLayerCfg->WindowX0 = X0; + pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth; + + /* update vertical start/stop */ + pLayerCfg->WindowY0 = Y0; + pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the pixel format. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Pixelformat new pixel format value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the pixel format */ + pLayerCfg->PixelFormat = Pixelformat; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the layer alpha value. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Alpha new alpha value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_ALPHA(Alpha)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Alpha value */ + pLayerCfg->Alpha = Alpha; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} +/** + * @brief Reconfigure the frame buffer Address. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Address new address value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Address */ + pLayerCfg->FBStartAdress = Address; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width + * that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to + * layer for which we want to read and display on screen only a portion 320x240 taken in the center + * of the buffer. + * The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by previous + * call to HAL_LTDC_ConfigLayer(). + * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default + * pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'. + * @param LayerIdx LTDC layer index concerned by the modification of line pitch. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) +{ + uint32_t tmp; + uint32_t pitchUpdate; + uint32_t pixelFormat; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* get LayerIdx used pixel format */ + pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; + + if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4U; + } + else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3U; + } + else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2U; + } + else + { + tmp = 1U; + } + + pitchUpdate = ((LinePitchInPixels * tmp) << 16U); + + /* Clear previously set standard pitch */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; + + /* Set the Reload type as immediate update of LTDC pitch configured above */ + LTDC->SRCR |= LTDC_SRCR_IMR; + + /* Set new line pitch value */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; + + /* Set the Reload type as immediate update of LTDC pitch configured above */ + LTDC->SRCR |= LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Define the position of the line interrupt. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Line Line Interrupt Position. + * @note User application may resort to HAL_LTDC_LineEventCallback() at line interrupt generation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LIPOS(Line)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable the Line interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI); + + /* Set the Line Interrupt position */ + LTDC->LIPCR = (uint32_t)Line; + + /* Enable the Line interrupt */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reload LTDC Layers configuration. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param ReloadType This parameter can be one of the following values : + * LTDC_RELOAD_IMMEDIATE : Immediate Reload + * LTDC_RELOAD_VERTICAL_BLANKING : Reload in the next Vertical Blanking + * @note User application may resort to HAL_LTDC_ReloadEventCallback() at reload interrupt generation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType) +{ + /* Check the parameters */ + assert_param(IS_LTDC_RELOAD(ReloadType)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable the Reload interrupt */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR); + + /* Apply Reload type */ + hltdc->Instance->SRCR = ReloadType; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Configure the LTDC Layer according to the specified without reloading + * parameters in the LTDC_InitTypeDef and create the associated handle. + * Variant of the function HAL_LTDC_ConfigLayer without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains + * the configuration information for the Layer. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, + uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); + assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); + assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); + assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); + assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0)); + assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1)); + assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); + assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); + assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Copy new layer configuration into handle structure */ + hltdc->LayerCfg[LayerIdx] = *pLayerCfg; + + /* Configure the LTDC Layer */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window size without reloading. + * Variant of the function HAL_LTDC_SetWindowSize without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param XSize LTDC Pixel per line + * @param YSize LTDC Line number + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, + uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters (Layers parameters)*/ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(XSize)); + assert_param(IS_LTDC_CFBLNBR(YSize)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal stop */ + pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0; + + /* update vertical stop */ + pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0; + + /* Reconfigures the color frame buffer pitch in byte */ + pLayerCfg->ImageWidth = XSize; + + /* Reconfigures the frame buffer line number */ + pLayerCfg->ImageHeight = YSize; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window position without reloading. + * Variant of the function HAL_LTDC_SetWindowPosition without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param X0 LTDC window X offset + * @param Y0 LTDC window Y offset + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, + uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(X0)); + assert_param(IS_LTDC_CFBLNBR(Y0)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal start/stop */ + pLayerCfg->WindowX0 = X0; + pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth; + + /* update vertical start/stop */ + pLayerCfg->WindowY0 = Y0; + pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the pixel format without reloading. + * Variant of the function HAL_LTDC_SetPixelFormat without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDfef structure that contains + * the configuration information for the LTDC. + * @param Pixelformat new pixel format value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the pixel format */ + pLayerCfg->PixelFormat = Pixelformat; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the layer alpha value without reloading. + * Variant of the function HAL_LTDC_SetAlpha without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Alpha new alpha value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_ALPHA(Alpha)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Alpha value */ + pLayerCfg->Alpha = Alpha; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the frame buffer Address without reloading. + * Variant of the function HAL_LTDC_SetAddress without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Address new address value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Address */ + pLayerCfg->FBStartAdress = Address; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width + * that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to + * layer for which we want to read and display on screen only a portion 320x240 taken in the center + * of the buffer. + * The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by + * previous call to HAL_LTDC_ConfigLayer(). + * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default + * pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). + * Variant of the function HAL_LTDC_SetPitch without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'. + * @param LayerIdx LTDC layer index concerned by the modification of line pitch. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) +{ + uint32_t tmp; + uint32_t pitchUpdate; + uint32_t pixelFormat; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* get LayerIdx used pixel format */ + pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; + + if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4U; + } + else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3U; + } + else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2U; + } + else + { + tmp = 1U; + } + + pitchUpdate = ((LinePitchInPixels * tmp) << 16U); + + /* Clear previously set standard pitch */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; + + /* Set new line pitch value */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + + +/** + * @brief Configure the color keying without reloading. + * Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param RGBValue the color key value + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Configure the default color values */ + LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); + LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color keying without reloading. + * Variant of the function HAL_LTDC_EnableColorKeying without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color keying without reloading. + * Variant of the function HAL_LTDC_DisableColorKeying without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color lookup table without reloading. + * Variant of the function HAL_LTDC_EnableCLUT without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color lookup table without reloading. + * Variant of the function HAL_LTDC_DisableCLUT without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the LTDC handle state. + (+) Get the LTDC handle error code. + +@endverbatim + * @{ + */ + +/** + * @brief Return the LTDC handle state. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL state + */ +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc) +{ + return hltdc->State; +} + +/** + * @brief Return the LTDC handle error code. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval LTDC Error Code + */ +uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc) +{ + return hltdc->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup LTDC_Private_Functions LTDC Private Functions + * @{ + */ + +/** + * @brief Configure the LTDC peripheral + * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pLayerCfg Pointer LTDC Layer Configuration structure + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval None + */ +static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +{ + uint32_t tmp; + uint32_t tmp1; + uint32_t tmp2; + + /* Configure the horizontal start and stop position */ + tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U); + LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); + LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \ + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); + + /* Configure the vertical start and stop position */ + tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U); + LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); + LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp); + + /* Specifies the pixel format */ + LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF); + LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat); + + /* Configure the default color values */ + tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U); + tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U); + tmp2 = (pLayerCfg->Alpha0 << 24U); + LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | + LTDC_LxDCCR_DCALPHA); + LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); + + /* Specifies the constant alpha value */ + LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA); + LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha); + + /* Specifies the blending factors */ + LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1); + LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2); + + /* Configure the color frame buffer start address */ + LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD); + LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress); + + if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4U; + } + else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3U; + } + else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2U; + } + else + { + tmp = 1U; + } + + /* Configure the color frame buffer pitch in byte */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP); + LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | \ + (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U)); + /* Configure the frame buffer line number */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR); + LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight); + + /* Enable LTDC_Layer by setting LEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN; +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* LTDC */ + +#endif /* HAL_LTDC_MODULE_ENABLED */ + +/** + * @} + */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc.h new file mode 100644 index 00000000000..da9ac7ad2a2 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc.h @@ -0,0 +1,719 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_ltdc.h + * @author MCD Application Team + * @brief Header file of LTDC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_LTDC_H +#define STM32U5xx_HAL_LTDC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +#if defined (LTDC) + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup LTDC LTDC + * @brief LTDC HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup LTDC_Exported_Types LTDC Exported Types + * @{ + */ +#define MAX_LAYER 2U + +/** + * @brief LTDC color structure definition + */ +typedef struct +{ + uint8_t Blue; /*!< Configures the blue value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint8_t Green; /*!< Configures the green value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint8_t Red; /*!< Configures the red value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint8_t Reserved; /*!< Reserved 0xFF */ +} LTDC_ColorTypeDef; + +/** + * @brief LTDC Init structure definition + */ +typedef struct +{ + uint32_t HSPolarity; /*!< configures the horizontal synchronization polarity. + This parameter can be one value of @ref LTDC_HS_POLARITY */ + + uint32_t VSPolarity; /*!< configures the vertical synchronization polarity. + This parameter can be one value of @ref LTDC_VS_POLARITY */ + + uint32_t DEPolarity; /*!< configures the data enable polarity. + This parameter can be one of value of @ref LTDC_DE_POLARITY */ + + uint32_t PCPolarity; /*!< configures the pixel clock polarity. + This parameter can be one of value of @ref LTDC_PC_POLARITY */ + + uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width. + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0xFFF. */ + + uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height. + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0x7FF. */ + + uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width. + This parameter must be a number between + Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */ + + uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height. + This parameter must be a number between + Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */ + + uint32_t AccumulatedActiveW; /*!< configures the accumulated active width. + This parameter must be a number between + Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */ + + uint32_t AccumulatedActiveH; /*!< configures the accumulated active height. + This parameter must be a number between + Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */ + + uint32_t TotalWidth; /*!< configures the total width. + This parameter must be a number between + Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */ + + uint32_t TotalHeigh; /*!< configures the total height. + This parameter must be a number between + Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */ + + LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */ +} LTDC_InitTypeDef; + +/** + * @brief LTDC Layer structure definition + */ +typedef struct +{ + uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position. + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0xFFF. */ + + uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position. + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0xFFF. */ + + uint32_t WindowY0; /*!< Configures the Window vertical Start Position. + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0x7FF. */ + + uint32_t WindowY1; /*!< Configures the Window vertical Stop Position. + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0x7FF. */ + + uint32_t PixelFormat; /*!< Specifies the pixel format. + This parameter can be one of value of @ref LTDC_Pixelformat */ + + uint32_t Alpha; /*!< Specifies the constant alpha used for blending. + This parameter must be a number between + Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint32_t Alpha0; /*!< Configures the default alpha value. + This parameter must be a number between + Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint32_t BlendingFactor1; /*!< Select the blending factor 1. + This parameter can be one of value of @ref LTDC_BlendingFactor1 */ + + uint32_t BlendingFactor2; /*!< Select the blending factor 2. + This parameter can be one of value of @ref LTDC_BlendingFactor2 */ + + uint32_t FBStartAdress; /*!< Configures the color frame buffer address */ + + uint32_t ImageWidth; /*!< Configures the color frame buffer line length. + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0x1FFF. */ + + uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer. + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0x7FF. */ + + LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */ +} LTDC_LayerCfgTypeDef; + +/** + * @brief HAL LTDC State structures definition + */ +typedef enum +{ + HAL_LTDC_STATE_RESET = 0x00U, /*!< LTDC not yet initialized or disabled */ + HAL_LTDC_STATE_READY = 0x01U, /*!< LTDC initialized and ready for use */ + HAL_LTDC_STATE_BUSY = 0x02U, /*!< LTDC internal process is ongoing */ + HAL_LTDC_STATE_TIMEOUT = 0x03U, /*!< LTDC Timeout state */ + HAL_LTDC_STATE_ERROR = 0x04U /*!< LTDC state error */ +} HAL_LTDC_StateTypeDef; + +/** + * @brief LTDC handle Structure definition + */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +typedef struct __LTDC_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ +{ + LTDC_TypeDef *Instance; /*!< LTDC Register base address */ + + LTDC_InitTypeDef Init; /*!< LTDC parameters */ + + LTDC_LayerCfgTypeDef LayerCfg[MAX_LAYER]; /*!< LTDC Layers parameters */ + + HAL_LockTypeDef Lock; /*!< LTDC Lock */ + + __IO HAL_LTDC_StateTypeDef State; /*!< LTDC state */ + + __IO uint32_t ErrorCode; /*!< LTDC Error code */ + +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + void (* LineEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Line Event Callback */ + void (* ReloadEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Reload Event Callback */ + void (* ErrorCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Error Callback */ + + void (* MspInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp Init callback */ + void (* MspDeInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp DeInit callback */ + +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + + +} LTDC_HandleTypeDef; + +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL LTDC Callback ID enumeration definition + */ +typedef enum +{ + HAL_LTDC_MSPINIT_CB_ID = 0x00U, /*!< LTDC MspInit callback ID */ + HAL_LTDC_MSPDEINIT_CB_ID = 0x01U, /*!< LTDC MspDeInit callback ID */ + + HAL_LTDC_LINE_EVENT_CB_ID = 0x02U, /*!< LTDC Line Event Callback ID */ + HAL_LTDC_RELOAD_EVENT_CB_ID = 0x03U, /*!< LTDC Reload Callback ID */ + HAL_LTDC_ERROR_CB_ID = 0x04U /*!< LTDC Error Callback ID */ + +} HAL_LTDC_CallbackIDTypeDef; + +/** + * @brief HAL LTDC Callback pointer definition + */ +typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer to an LTDC callback function */ + +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LTDC_Exported_Constants LTDC Exported Constants + * @{ + */ + +/** @defgroup LTDC_Error_Code LTDC Error Code + * @{ + */ +#define HAL_LTDC_ERROR_NONE 0x00000000U /*!< LTDC No error */ +#define HAL_LTDC_ERROR_TE 0x00000001U /*!< LTDC Transfer error */ +#define HAL_LTDC_ERROR_FU 0x00000002U /*!< LTDC FIFO Underrun */ +#define HAL_LTDC_ERROR_TIMEOUT 0x00000020U /*!< LTDC Timeout error */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +#define HAL_LTDC_ERROR_INVALID_CALLBACK 0x00000040U /*!< LTDC Invalid Callback error */ +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup LTDC_Layer LTDC Layer + * @{ + */ +#define LTDC_LAYER_1 0x00000000U /*!< LTDC Layer 1 */ +#define LTDC_LAYER_2 0x00000001U /*!< LTDC Layer 2 */ +/** + * @} + */ + +/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY + * @{ + */ +#define LTDC_HSPOLARITY_AL 0x00000000U /*!< Horizontal Synchronization is active low. */ +#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */ +/** + * @} + */ + +/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY + * @{ + */ +#define LTDC_VSPOLARITY_AL 0x00000000U /*!< Vertical Synchronization is active low. */ +#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */ +/** + * @} + */ + +/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY + * @{ + */ +#define LTDC_DEPOLARITY_AL 0x00000000U /*!< Data Enable, is active low. */ +#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */ +/** + * @} + */ + +/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY + * @{ + */ +#define LTDC_PCPOLARITY_IPC 0x00000000U /*!< input pixel clock. */ +#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */ +/** + * @} + */ + +/** @defgroup LTDC_SYNC LTDC SYNC + * @{ + */ +#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16U) /*!< Horizontal synchronization width. */ +#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization height. */ +/** + * @} + */ + +/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR + * @{ + */ +#define LTDC_COLOR 0x000000FFU /*!< Color mask */ +/** + * @} + */ + +/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1 + * @{ + */ +#define LTDC_BLENDING_FACTOR1_CA 0x00000400U /*!< Blending factor : Cte Alpha */ +#define LTDC_BLENDING_FACTOR1_PAxCA 0x00000600U /*!< Blending factor : Cte Alpha x Pixel Alpha*/ +/** + * @} + */ + +/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2 + * @{ + */ +#define LTDC_BLENDING_FACTOR2_CA 0x00000005U /*!< Blending factor : Cte Alpha */ +#define LTDC_BLENDING_FACTOR2_PAxCA 0x00000007U /*!< Blending factor : Cte Alpha x Pixel Alpha*/ +/** + * @} + */ + +/** @defgroup LTDC_Pixelformat LTDC Pixel format + * @{ + */ +#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */ +/** + * @} + */ + +/** @defgroup LTDC_Alpha LTDC Alpha + * @{ + */ +#define LTDC_ALPHA LTDC_LxCACR_CONSTA /*!< LTDC Constant Alpha mask */ +/** + * @} + */ + +/** @defgroup LTDC_LAYER_Config LTDC LAYER Config + * @{ + */ +#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16U) /*!< LTDC Layer stop position */ +#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */ + +#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */ +#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */ +/** + * @} + */ + +/** @defgroup LTDC_Interrupts LTDC Interrupts + * @{ + */ +#define LTDC_IT_LI LTDC_IER_LIE /*!< LTDC Line Interrupt */ +#define LTDC_IT_FU LTDC_IER_FUIE /*!< LTDC FIFO Underrun Interrupt */ +#define LTDC_IT_TE LTDC_IER_TERRIE /*!< LTDC Transfer Error Interrupt */ +#define LTDC_IT_RR LTDC_IER_RRIE /*!< LTDC Register Reload Interrupt */ +/** + * @} + */ + +/** @defgroup LTDC_Flags LTDC Flags + * @{ + */ +#define LTDC_FLAG_LI LTDC_ISR_LIF /*!< LTDC Line Interrupt Flag */ +#define LTDC_FLAG_FU LTDC_ISR_FUIF /*!< LTDC FIFO Underrun interrupt Flag */ +#define LTDC_FLAG_TE LTDC_ISR_TERRIF /*!< LTDC Transfer Error interrupt Flag */ +#define LTDC_FLAG_RR LTDC_ISR_RRIF /*!< LTDC Register Reload interrupt Flag */ +/** + * @} + */ + +/** @defgroup LTDC_Reload_Type LTDC Reload Type + * @{ + */ +#define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR /*!< Immediate Reload */ +#define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR /*!< Vertical Blanking Reload */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup LTDC_Exported_Macros LTDC Exported Macros + * @{ + */ + +/** @brief Reset LTDC handle state. + * @param __HANDLE__ LTDC handle + * @retval None + */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_LTDC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET) +#endif /*USE_HAL_LTDC_REGISTER_CALLBACKS */ + +/** + * @brief Enable the LTDC. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN) + +/** + * @brief Disable the LTDC. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN)) + +/** + * @brief Enable the LTDC Layer. + * @param __HANDLE__ LTDC handle + * @param __LAYER__ Specify the layer to be enabled. + * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval None. + */ +#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\ + |= (uint32_t)LTDC_LxCR_LEN) + +/** + * @brief Disable the LTDC Layer. + * @param __HANDLE__ LTDC handle + * @param __LAYER__ Specify the layer to be disabled. + * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval None. + */ +#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\ + &= ~(uint32_t)LTDC_LxCR_LEN) + +/** + * @brief Reload immediately all LTDC Layers. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR) + +/** + * @brief Reload during vertical blanking period all LTDC Layers. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR) + +/* Interrupt & Flag management */ +/** + * @brief Get the LTDC pending flags. + * @param __HANDLE__ LTDC handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg LTDC_FLAG_LI: Line Interrupt flag + * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag + * @arg LTDC_FLAG_TE: Transfer Error interrupt flag + * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) + +/** + * @brief Clears the LTDC pending flags. + * @param __HANDLE__ LTDC handle + * @param __FLAG__ Specify the flag to clear. + * This parameter can be any combination of the following values: + * @arg LTDC_FLAG_LI: Line Interrupt flag + * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag + * @arg LTDC_FLAG_TE: Transfer Error interrupt flag + * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag + * @retval None + */ +#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** + * @brief Enables the specified LTDC interrupts. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ Specify the LTDC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag + * @arg LTDC_IT_TE: Transfer Error interrupt flag + * @arg LTDC_IT_RR: Register Reload Interrupt Flag + * @retval None + */ +#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified LTDC interrupts. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ Specify the LTDC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag + * @arg LTDC_IT_TE: Transfer Error interrupt flag + * @arg LTDC_IT_RR: Register Reload Interrupt Flag + * @retval None + */ +#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified LTDC interrupt has occurred or not. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ Specify the LTDC interrupt source to check. + * This parameter can be one of the following values: + * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag + * @arg LTDC_IT_TE: Transfer Error interrupt flag + * @arg LTDC_IT_RR: Register Reload Interrupt Flag + * @retval The state of INTERRUPT (SET or RESET). + */ +#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) +/** + * @} + */ + +/* Include LTDC HAL Extension module */ +#include "stm32u5xx_hal_ltdc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LTDC_Exported_Functions + * @{ + */ +/** @addtogroup LTDC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc); +HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, + pLTDC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup LTDC_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc); +/** + * @} + */ + +/** @addtogroup LTDC_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line); +HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc); +HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc); +HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType); +HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, + uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, + uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, + uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); + +/** + * @} + */ + +/** @addtogroup LTDC_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State functions *************************************************/ +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc); +uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup LTDC_Private_Macros LTDC Private Macros + * @{ + */ +#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(\ + ((uint32_t)((__HANDLE__)->Instance))\ + + 0x84U + (0x80U*(__LAYER__))))) +#define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER) +#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL)\ + || ((__HSPOL__) == LTDC_HSPOLARITY_AH)) +#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL)\ + || ((__VSPOL__) == LTDC_VSPOLARITY_AH)) +#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL)\ + || ((__DEPOL__) == LTDC_DEPOLARITY_AH)) +#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC)\ + || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC)) +#define IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_AVBP(__AVBP__) ((__AVBP__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_AAW(__AAW__) ((__AAW__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_AAH(__AAH__) ((__AAH__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_TOTALW(__TOTALW__) ((__TOTALW__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_TOTALH(__TOTALH__) ((__TOTALH__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_BLUEVALUE(__BBLUE__) ((__BBLUE__) <= LTDC_COLOR) +#define IS_LTDC_GREENVALUE(__BGREEN__) ((__BGREEN__) <= LTDC_COLOR) +#define IS_LTDC_REDVALUE(__BRED__) ((__BRED__) <= LTDC_COLOR) +#define IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \ + ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA)) +#define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \ + ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA)) +#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88)) +#define IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA) +#define IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION) +#define IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION) +#define IS_LTDC_VCONFIGST(__VCONFIGST__) ((__VCONFIGST__) <= LTDC_STARTPOSITION) +#define IS_LTDC_VCONFIGSP(__VCONFIGSP__) ((__VCONFIGSP__) <= LTDC_STOPPOSITION) +#define IS_LTDC_CFBP(__CFBP__) ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER) +#define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER) +#define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER) +#define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU) +#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || \ + ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup LTDC_Private_Functions LTDC Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LTDC */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_LTDC_H */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc_ex.c new file mode 100644 index 00000000000..ab24d63bc26 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc_ex.c @@ -0,0 +1,151 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_ltdc_ex.c + * @author MCD Application Team + * @brief LTDC Extension HAL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +#if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED) + +#if defined (LTDC) && defined (DSI) + +/** @defgroup LTDCEx LTDCEx + * @brief LTDC HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions + * @{ + */ + +/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the LTDC + +@endverbatim + * @{ + */ + +/** + * @brief Retrieve common parameters from DSI Video mode configuration structure + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains + * the DSI video mode configuration parameters + * @note The implementation of this function is taking into account the LTDC + * polarities inversion as described in the current LTDC specification + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg) +{ + /* Retrieve signal polarities from DSI */ + + /* The following polarity is inverted: + LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */ + + /* Note 1 : Code in line w/ Current LTDC specification */ + hltdc->Init.DEPolarity = (VidCfg->DEPolarity == \ + DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; + hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL; + hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL; + + /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ + /* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29; + hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29; + hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */ + + /* Retrieve vertical timing parameters from DSI */ + hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1U; + hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U; + hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \ + VidCfg->VerticalActive - 1U; + hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \ + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U; + + return HAL_OK; +} + +/** + * @brief Retrieve common parameters from DSI Adapted command mode configuration structure + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains + * the DSI command mode configuration parameters + * @note The implementation of this function is taking into account the LTDC + * polarities inversion as described in the current LTDC specification + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg) +{ + /* Retrieve signal polarities from DSI */ + + /* The following polarities are inverted: + LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH + LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH + LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ + + /* Note 1 : Code in line w/ Current LTDC specification */ + hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == \ + DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; + hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; + hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; + + /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ + /* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29; + hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29; + hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */ + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LTDC && DSI */ + +#endif /* HAL_LTCD_MODULE_ENABLED && HAL_DSI_MODULE_ENABLED */ + +/** + * @} + */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc_ex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc_ex.h new file mode 100644 index 00000000000..811a030744f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ltdc_ex.h @@ -0,0 +1,83 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_ltdc_ex.h + * @author MCD Application Team + * @brief Header file of LTDC HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_LTDC_EX_H +#define STM32U5xx_HAL_LTDC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" + +#if defined (LTDC) && defined (DSI) + +#include "stm32u5xx_hal_dsi.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup LTDCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LTDCEx_Exported_Functions + * @{ + */ + +/** @addtogroup LTDCEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg); +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LTDC && DSI */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_LTDC_EX_H */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mdf.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mdf.c index e1a085e9a00..cca779f42d8 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mdf.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mdf.c @@ -237,7 +237,11 @@ /** @defgroup MDF_Private_Constants MDF Private Constants * @{ */ +#if defined(STM32U535xx) || defined(STM32U545xx) +#define MDF_INSTANCE_NUMBER 3U /* 2 instances for MDF1 and 1 instance for ADF1 */ +#else /* defined(STM32U535xx) || defined(STM32U545xx) */ #define MDF_INSTANCE_NUMBER 7U /* 6 instances for MDF1 and 1 instance for ADF1 */ +#endif /* defined(STM32U535xx) || defined(STM32U545xx) */ /** * @} */ @@ -913,7 +917,7 @@ HAL_StatusTypeDef HAL_MDF_UnRegisterSndLvlCallback(MDF_HandleTypeDef *hmdf) * @param pFilterConfig Filter configuration parameters. * @retval HAL status. */ -HAL_StatusTypeDef HAL_MDF_AcqStart(MDF_HandleTypeDef *hmdf, MDF_FilterConfigTypeDef *pFilterConfig) +HAL_StatusTypeDef HAL_MDF_AcqStart(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig) { HAL_StatusTypeDef status = HAL_OK; @@ -1135,7 +1139,7 @@ HAL_StatusTypeDef HAL_MDF_PollForSnapshotAcq(MDF_HandleTypeDef *hmdf, uint32_t T * @param pValue Acquisition value on 24 MSB. * @retval HAL status. */ -HAL_StatusTypeDef HAL_MDF_GetAcqValue(MDF_HandleTypeDef *hmdf, int32_t *pValue) +HAL_StatusTypeDef HAL_MDF_GetAcqValue(const MDF_HandleTypeDef *hmdf, int32_t *pValue) { HAL_StatusTypeDef status = HAL_OK; @@ -1290,7 +1294,7 @@ HAL_StatusTypeDef HAL_MDF_AcqStop(MDF_HandleTypeDef *hmdf) * @param pFilterConfig Filter configuration parameters. * @retval HAL status. */ -HAL_StatusTypeDef HAL_MDF_AcqStart_IT(MDF_HandleTypeDef *hmdf, MDF_FilterConfigTypeDef *pFilterConfig) +HAL_StatusTypeDef HAL_MDF_AcqStart_IT(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig) { HAL_StatusTypeDef status = HAL_OK; @@ -1470,8 +1474,8 @@ HAL_StatusTypeDef HAL_MDF_AcqStop_IT(MDF_HandleTypeDef *hmdf) * @param pDmaConfig DMA configuration parameters. * @retval HAL status. */ -HAL_StatusTypeDef HAL_MDF_AcqStart_DMA(MDF_HandleTypeDef *hmdf, MDF_FilterConfigTypeDef *pFilterConfig, - MDF_DmaConfigTypeDef *pDmaConfig) +HAL_StatusTypeDef HAL_MDF_AcqStart_DMA(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig, + const MDF_DmaConfigTypeDef *pDmaConfig) { HAL_StatusTypeDef status = HAL_OK; @@ -1686,7 +1690,7 @@ HAL_StatusTypeDef HAL_MDF_AcqStop_DMA(MDF_HandleTypeDef *hmdf) * @param hmdf MDF handle. * @retval HAL status. */ -HAL_StatusTypeDef HAL_MDF_GenerateTrgo(MDF_HandleTypeDef *hmdf) +HAL_StatusTypeDef HAL_MDF_GenerateTrgo(const MDF_HandleTypeDef *hmdf) { HAL_StatusTypeDef status = HAL_OK; @@ -1766,7 +1770,7 @@ HAL_StatusTypeDef HAL_MDF_SetDelay(MDF_HandleTypeDef *hmdf, uint32_t Delay) * This value is between Min_Data = 0 and Max_Data = 127. * @retval HAL status. */ -HAL_StatusTypeDef HAL_MDF_GetDelay(MDF_HandleTypeDef *hmdf, uint32_t *pDelay) +HAL_StatusTypeDef HAL_MDF_GetDelay(const MDF_HandleTypeDef *hmdf, uint32_t *pDelay) { HAL_StatusTypeDef status = HAL_OK; @@ -1843,7 +1847,7 @@ HAL_StatusTypeDef HAL_MDF_SetGain(MDF_HandleTypeDef *hmdf, int32_t Gain) * This parameter is between Min_Data = -16 and Max_Data = 24. * @retval HAL status. */ -HAL_StatusTypeDef HAL_MDF_GetGain(MDF_HandleTypeDef *hmdf, int32_t *pGain) +HAL_StatusTypeDef HAL_MDF_GetGain(const MDF_HandleTypeDef *hmdf, int32_t *pGain) { HAL_StatusTypeDef status = HAL_OK; @@ -1919,7 +1923,7 @@ HAL_StatusTypeDef HAL_MDF_SetOffset(MDF_HandleTypeDef *hmdf, int32_t Offset) * @retval HAL status. * @note This function must not be used with ADF instance. */ -HAL_StatusTypeDef HAL_MDF_GetOffset(MDF_HandleTypeDef *hmdf, int32_t *pOffset) +HAL_StatusTypeDef HAL_MDF_GetOffset(const MDF_HandleTypeDef *hmdf, int32_t *pOffset) { HAL_StatusTypeDef status = HAL_OK; @@ -2346,7 +2350,7 @@ HAL_StatusTypeDef HAL_MDF_CkabStop_IT(MDF_HandleTypeDef *hmdf) * @retval HAL status. * @note This function must not be used with ADF instance. */ -HAL_StatusTypeDef HAL_MDF_ScdStart(MDF_HandleTypeDef *hmdf, MDF_ScdConfigTypeDef *pScdConfig) +HAL_StatusTypeDef HAL_MDF_ScdStart(MDF_HandleTypeDef *hmdf, const MDF_ScdConfigTypeDef *pScdConfig) { HAL_StatusTypeDef status = HAL_OK; @@ -2502,7 +2506,7 @@ HAL_StatusTypeDef HAL_MDF_ScdStop(MDF_HandleTypeDef *hmdf) * @retval HAL status. * @note This function must not be used with ADF instance. */ -HAL_StatusTypeDef HAL_MDF_ScdStart_IT(MDF_HandleTypeDef *hmdf, MDF_ScdConfigTypeDef *pScdConfig) +HAL_StatusTypeDef HAL_MDF_ScdStart_IT(MDF_HandleTypeDef *hmdf, const MDF_ScdConfigTypeDef *pScdConfig) { HAL_StatusTypeDef status = HAL_OK; @@ -2624,7 +2628,7 @@ HAL_StatusTypeDef HAL_MDF_ScdStop_IT(MDF_HandleTypeDef *hmdf) * @retval HAL status. * @note This function must not be used with ADF instance. */ -HAL_StatusTypeDef HAL_MDF_OldStart(MDF_HandleTypeDef *hmdf, MDF_OldConfigTypeDef *pOldConfig) +HAL_StatusTypeDef HAL_MDF_OldStart(MDF_HandleTypeDef *hmdf, const MDF_OldConfigTypeDef *pOldConfig) { HAL_StatusTypeDef status = HAL_OK; @@ -2835,7 +2839,7 @@ HAL_StatusTypeDef HAL_MDF_OldStop(MDF_HandleTypeDef *hmdf) * @retval HAL status. * @note This function must not be used with ADF instance. */ -HAL_StatusTypeDef HAL_MDF_OldStart_IT(MDF_HandleTypeDef *hmdf, MDF_OldConfigTypeDef *pOldConfig) +HAL_StatusTypeDef HAL_MDF_OldStart_IT(MDF_HandleTypeDef *hmdf, const MDF_OldConfigTypeDef *pOldConfig) { HAL_StatusTypeDef status = HAL_OK; @@ -3233,7 +3237,7 @@ __weak void HAL_MDF_ErrorCallback(MDF_HandleTypeDef *hmdf) * @param hmdf MDF handle. * @retval MDF state. */ -HAL_MDF_StateTypeDef HAL_MDF_GetState(MDF_HandleTypeDef *hmdf) +HAL_MDF_StateTypeDef HAL_MDF_GetState(const MDF_HandleTypeDef *hmdf) { /* Return MDF state */ return hmdf->State; @@ -3244,7 +3248,7 @@ HAL_MDF_StateTypeDef HAL_MDF_GetState(MDF_HandleTypeDef *hmdf) * @param hmdf MDF handle. * @retval MDF error code. */ -uint32_t HAL_MDF_GetError(MDF_HandleTypeDef *hmdf) +uint32_t HAL_MDF_GetError(const MDF_HandleTypeDef *hmdf) { /* Return MDF error code */ return hmdf->ErrorCode; @@ -3281,6 +3285,7 @@ static uint32_t MDF_GetHandleNumberFromInstance(const MDF_Filter_TypeDef *const { handle_number = 1U; } +#if !defined(STM32U535xx) && !defined(STM32U545xx) else if (pInstance == MDF1_Filter2) { handle_number = 2U; @@ -3301,6 +3306,12 @@ static uint32_t MDF_GetHandleNumberFromInstance(const MDF_Filter_TypeDef *const { handle_number = 6U; } +#else /* !defined(STM32U535xx) && !defined(STM32U545xx) */ + else /* ADF1_Filter0 */ + { + handle_number = 2U; + } +#endif /* !defined(STM32U535xx) && !defined(STM32U545xx) */ return handle_number; } diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mdf.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mdf.h index 5ab4ebadcc5..6ee766a5287 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mdf.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mdf.h @@ -83,7 +83,9 @@ typedef struct { uint32_t InterleavedFilters; /*!< Number of filters in interleaved mode with filter 0. This parameter must be a number between Min_Data = 0 - and Max_Data = 5. + and Max_Data = 1 for STM32U535xx/STM32U545xx devices. + This parameter must be a number between Min_Data = 0 + and Max_Data = 5 for other devices. @note This parameter is not used for ADF instance */ uint32_t ProcClockDivider; /*!< Processing clock divider. This parameter must be a number between Min_Data = 1 @@ -467,6 +469,7 @@ typedef struct #define MDF_BITSTREAM1_RISING MDF_BSMXCR_BSSEL_1 /*!< @note Not available for ADF instance */ #define MDF_BITSTREAM1_FALLING (MDF_BSMXCR_BSSEL_0 | \ MDF_BSMXCR_BSSEL_1) /*!< @note Not available for ADF instance */ +#if !defined(STM32U535xx) && !defined(STM32U545xx) #define MDF_BITSTREAM2_RISING MDF_BSMXCR_BSSEL_2 /*!< @note Not available for ADF instance */ #define MDF_BITSTREAM2_FALLING (MDF_BSMXCR_BSSEL_0 | \ MDF_BSMXCR_BSSEL_2) /*!< @note Not available for ADF instance */ @@ -483,6 +486,7 @@ typedef struct #define MDF_BITSTREAM5_FALLING (MDF_BSMXCR_BSSEL_0 | \ MDF_BSMXCR_BSSEL_1 | \ MDF_BSMXCR_BSSEL_3) /*!< @note Not available for ADF instance */ +#endif /* !defined(STM32U535xx) && !defined(STM32U545xx) */ /** * @} */ @@ -668,8 +672,10 @@ typedef struct #define MDF_DATA_SOURCE_BSMX 0x00000000U /*!< Data from bitstream matrix */ #define MDF_DATA_SOURCE_ADCITF1 MDF_DFLTCICR_DATSRC_1 /*!< Data from ADC interface 1. @note Not available for ADF instance */ +#if defined(ADC2) #define MDF_DATA_SOURCE_ADCITF2 MDF_DFLTCICR_DATSRC /*!< Data from ADC interface 2. @note Not available for ADF instance */ +#endif /* ADC2 */ /** * @} */ @@ -837,24 +843,24 @@ HAL_StatusTypeDef HAL_MDF_UnRegisterSndLvlCallback(MDF_HandleTypeDef *hmdf); /** @addtogroup MDF_Exported_Functions_Group2 * @{ */ -HAL_StatusTypeDef HAL_MDF_AcqStart(MDF_HandleTypeDef *hmdf, MDF_FilterConfigTypeDef *pFilterConfig); +HAL_StatusTypeDef HAL_MDF_AcqStart(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig); HAL_StatusTypeDef HAL_MDF_PollForAcq(MDF_HandleTypeDef *hmdf, uint32_t Timeout); HAL_StatusTypeDef HAL_MDF_PollForSnapshotAcq(MDF_HandleTypeDef *hmdf, uint32_t Timeout); -HAL_StatusTypeDef HAL_MDF_GetAcqValue(MDF_HandleTypeDef *hmdf, int32_t *pValue); +HAL_StatusTypeDef HAL_MDF_GetAcqValue(const MDF_HandleTypeDef *hmdf, int32_t *pValue); HAL_StatusTypeDef HAL_MDF_GetSnapshotAcqValue(MDF_HandleTypeDef *hmdf, MDF_SnapshotParamTypeDef *pSnapshotParam); HAL_StatusTypeDef HAL_MDF_AcqStop(MDF_HandleTypeDef *hmdf); -HAL_StatusTypeDef HAL_MDF_AcqStart_IT(MDF_HandleTypeDef *hmdf, MDF_FilterConfigTypeDef *pFilterConfig); +HAL_StatusTypeDef HAL_MDF_AcqStart_IT(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig); HAL_StatusTypeDef HAL_MDF_AcqStop_IT(MDF_HandleTypeDef *hmdf); -HAL_StatusTypeDef HAL_MDF_AcqStart_DMA(MDF_HandleTypeDef *hmdf, MDF_FilterConfigTypeDef *pFilterConfig, - MDF_DmaConfigTypeDef *pDmaConfig); +HAL_StatusTypeDef HAL_MDF_AcqStart_DMA(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig, + const MDF_DmaConfigTypeDef *pDmaConfig); HAL_StatusTypeDef HAL_MDF_AcqStop_DMA(MDF_HandleTypeDef *hmdf); -HAL_StatusTypeDef HAL_MDF_GenerateTrgo(MDF_HandleTypeDef *hmdf); +HAL_StatusTypeDef HAL_MDF_GenerateTrgo(const MDF_HandleTypeDef *hmdf); HAL_StatusTypeDef HAL_MDF_SetDelay(MDF_HandleTypeDef *hmdf, uint32_t Delay); -HAL_StatusTypeDef HAL_MDF_GetDelay(MDF_HandleTypeDef *hmdf, uint32_t *pDelay); +HAL_StatusTypeDef HAL_MDF_GetDelay(const MDF_HandleTypeDef *hmdf, uint32_t *pDelay); HAL_StatusTypeDef HAL_MDF_SetGain(MDF_HandleTypeDef *hmdf, int32_t Gain); -HAL_StatusTypeDef HAL_MDF_GetGain(MDF_HandleTypeDef *hmdf, int32_t *pGain); +HAL_StatusTypeDef HAL_MDF_GetGain(const MDF_HandleTypeDef *hmdf, int32_t *pGain); HAL_StatusTypeDef HAL_MDF_SetOffset(MDF_HandleTypeDef *hmdf, int32_t Offset); -HAL_StatusTypeDef HAL_MDF_GetOffset(MDF_HandleTypeDef *hmdf, int32_t *pOffset); +HAL_StatusTypeDef HAL_MDF_GetOffset(const MDF_HandleTypeDef *hmdf, int32_t *pOffset); HAL_StatusTypeDef HAL_MDF_PollForSndLvl(MDF_HandleTypeDef *hmdf, uint32_t Timeout, uint32_t *pSoundLevel, uint32_t *pAmbientNoise); HAL_StatusTypeDef HAL_MDF_PollForSad(MDF_HandleTypeDef *hmdf, uint32_t Timeout); @@ -881,10 +887,10 @@ HAL_StatusTypeDef HAL_MDF_CkabStop_IT(MDF_HandleTypeDef *hmdf); /** @addtogroup MDF_Exported_Functions_Group4 * @{ */ -HAL_StatusTypeDef HAL_MDF_ScdStart(MDF_HandleTypeDef *hmdf, MDF_ScdConfigTypeDef *pScdConfig); +HAL_StatusTypeDef HAL_MDF_ScdStart(MDF_HandleTypeDef *hmdf, const MDF_ScdConfigTypeDef *pScdConfig); HAL_StatusTypeDef HAL_MDF_PollForScd(MDF_HandleTypeDef *hmdf, uint32_t Timeout); HAL_StatusTypeDef HAL_MDF_ScdStop(MDF_HandleTypeDef *hmdf); -HAL_StatusTypeDef HAL_MDF_ScdStart_IT(MDF_HandleTypeDef *hmdf, MDF_ScdConfigTypeDef *pScdConfig); +HAL_StatusTypeDef HAL_MDF_ScdStart_IT(MDF_HandleTypeDef *hmdf, const MDF_ScdConfigTypeDef *pScdConfig); HAL_StatusTypeDef HAL_MDF_ScdStop_IT(MDF_HandleTypeDef *hmdf); /** * @} @@ -894,10 +900,10 @@ HAL_StatusTypeDef HAL_MDF_ScdStop_IT(MDF_HandleTypeDef *hmdf); /** @addtogroup MDF_Exported_Functions_Group5 * @{ */ -HAL_StatusTypeDef HAL_MDF_OldStart(MDF_HandleTypeDef *hmdf, MDF_OldConfigTypeDef *pOldConfig); +HAL_StatusTypeDef HAL_MDF_OldStart(MDF_HandleTypeDef *hmdf, const MDF_OldConfigTypeDef *pOldConfig); HAL_StatusTypeDef HAL_MDF_PollForOld(MDF_HandleTypeDef *hmdf, uint32_t Timeout, uint32_t *pThresholdInfo); HAL_StatusTypeDef HAL_MDF_OldStop(MDF_HandleTypeDef *hmdf); -HAL_StatusTypeDef HAL_MDF_OldStart_IT(MDF_HandleTypeDef *hmdf, MDF_OldConfigTypeDef *pOldConfig); +HAL_StatusTypeDef HAL_MDF_OldStart_IT(MDF_HandleTypeDef *hmdf, const MDF_OldConfigTypeDef *pOldConfig); HAL_StatusTypeDef HAL_MDF_OldStop_IT(MDF_HandleTypeDef *hmdf); void HAL_MDF_OldCallback(MDF_HandleTypeDef *hmdf, uint32_t ThresholdInfo); /** @@ -910,8 +916,8 @@ void HAL_MDF_OldCallback(MDF_HandleTypeDef *hmdf, uint32_t Threshol */ void HAL_MDF_IRQHandler(MDF_HandleTypeDef *hmdf); void HAL_MDF_ErrorCallback(MDF_HandleTypeDef *hmdf); -HAL_MDF_StateTypeDef HAL_MDF_GetState(MDF_HandleTypeDef *hmdf); -uint32_t HAL_MDF_GetError(MDF_HandleTypeDef *hmdf); +HAL_MDF_StateTypeDef HAL_MDF_GetState(const MDF_HandleTypeDef *hmdf); +uint32_t HAL_MDF_GetError(const MDF_HandleTypeDef *hmdf); /** * @} */ @@ -924,15 +930,26 @@ uint32_t HAL_MDF_GetError(MDF_HandleTypeDef *hmdf); /** @defgroup MDF_Private_Macros MDF Private Macros * @{ */ +#if defined(STM32U535xx) || defined(STM32U545xx) +#define IS_MDF_INSTANCE(PARAM) (((PARAM) == MDF1_Filter0) || \ + ((PARAM) == MDF1_Filter1)) +#else /* defined(STM32U535xx) || defined(STM32U545xx) */ #define IS_MDF_INSTANCE(PARAM) (((PARAM) == MDF1_Filter0) || \ ((PARAM) == MDF1_Filter1) || \ ((PARAM) == MDF1_Filter2) || \ ((PARAM) == MDF1_Filter3) || \ ((PARAM) == MDF1_Filter4) || \ ((PARAM) == MDF1_Filter5)) +#endif /* defined(STM32U535xx) || defined(STM32U545xx) */ #define IS_ADF_INSTANCE(PARAM) ((PARAM) == ADF1_Filter0) +#if defined(STM32U535xx) || defined(STM32U545xx) +#define IS_MDF_FILTER_BITSTREAM(PARAM) (((PARAM) == MDF_BITSTREAM0_RISING) || \ + ((PARAM) == MDF_BITSTREAM0_FALLING) || \ + ((PARAM) == MDF_BITSTREAM1_RISING) || \ + ((PARAM) == MDF_BITSTREAM1_FALLING)) +#else /* defined(STM32U535xx) || defined(STM32U545xx) */ #define IS_MDF_FILTER_BITSTREAM(PARAM) (((PARAM) == MDF_BITSTREAM0_RISING) || \ ((PARAM) == MDF_BITSTREAM0_FALLING) || \ ((PARAM) == MDF_BITSTREAM1_RISING) || \ @@ -945,8 +962,13 @@ uint32_t HAL_MDF_GetError(MDF_HandleTypeDef *hmdf); ((PARAM) == MDF_BITSTREAM4_FALLING) || \ ((PARAM) == MDF_BITSTREAM5_RISING) || \ ((PARAM) == MDF_BITSTREAM5_FALLING)) +#endif /* defined(STM32U535xx) || defined(STM32U545xx) */ +#if defined(STM32U535xx) || defined(STM32U545xx) +#define IS_MDF_INTERLEAVED_FILTERS(PARAM) ((PARAM) <= 1U) +#else /* defined(STM32U535xx) || defined(STM32U545xx) */ #define IS_MDF_INTERLEAVED_FILTERS(PARAM) ((PARAM) <= 5U) +#endif /* defined(STM32U535xx) || defined(STM32U545xx) */ #define IS_MDF_PROC_CLOCK_DIVIDER(PARAM) ((1U <= (PARAM)) && ((PARAM) <= 128U)) @@ -1043,9 +1065,14 @@ uint32_t HAL_MDF_GetError(MDF_HandleTypeDef *hmdf); #define IS_MDF_SNAPSHOT_FORMAT(PARAM) (((PARAM) == MDF_SNAPSHOT_23BITS) || \ ((PARAM) == MDF_SNAPSHOT_16BITS)) +#if defined(ADC2) #define IS_MDF_DATA_SOURCE(PARAM) (((PARAM) == MDF_DATA_SOURCE_BSMX) || \ ((PARAM) == MDF_DATA_SOURCE_ADCITF1) || \ ((PARAM) == MDF_DATA_SOURCE_ADCITF2)) +#else /* ADC2 */ +#define IS_MDF_DATA_SOURCE(PARAM) (((PARAM) == MDF_DATA_SOURCE_BSMX) || \ + ((PARAM) == MDF_DATA_SOURCE_ADCITF1)) +#endif /* ADC2 */ #define IS_ADF_DATA_SOURCE(PARAM) ((PARAM) == MDF_DATA_SOURCE_BSMX) diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mmc.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mmc.c index faa2b70910f..d49d9fea1d3 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mmc.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mmc.c @@ -64,7 +64,7 @@ SDMMC Peripheral (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer). This function provide the following operations: - (#) Initialize the SDMMC peripheral interface with defaullt configuration. + (#) Initialize the SDMMC peripheral interface with default configuration. The initialization process is done at 400KHz. You can change or adapt this frequency by adjusting the "ClockDiv" field. The MMC Card frequency (SDMMC_CK) is computed as follows: @@ -188,7 +188,7 @@ The compilation define USE_HAL_MMC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_MMC_RegisterCallback() to register a user callback, + Use Functions HAL_MMC_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) TxCpltCallback : callback when a transmission transfer is completed. (+) RxCpltCallback : callback when a reception transfer is completed. @@ -201,7 +201,7 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_MMC_UnRegisterCallback() to reset a callback to the default + Use function HAL_MMC_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) TxCpltCallback : callback when a transmission transfer is completed. (+) RxCpltCallback : callback when a reception transfer is completed. @@ -215,12 +215,12 @@ (+) MspDeInitCallback : MMC MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET + By default, after the HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_MMC_Init - and @ref HAL_MMC_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_MMC_Init and @ref HAL_MMC_DeInit + reset to the legacy weak (surcharged) functions in the HAL_MMC_Init + and HAL_MMC_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_MMC_Init and HAL_MMC_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -228,14 +228,15 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_MMC_RegisterCallback before calling @ref HAL_MMC_DeInit - or @ref HAL_MMC_Init function. + using HAL_MMC_RegisterCallback before calling HAL_MMC_DeInit + or HAL_MMC_Init function. When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available and weak (surcharged) callbacks are used. @endverbatim + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -258,7 +259,7 @@ * @{ */ #if defined (VDD_VALUE) && (VDD_VALUE <= 1950U) -#define MMC_VOLTAGE_RANGE MMC_LOW_VOLTAGE_RANGE +#define MMC_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE #define MMC_EXT_CSD_PWR_CL_26_INDEX 201 #define MMC_EXT_CSD_PWR_CL_52_INDEX 200 @@ -268,7 +269,7 @@ #define MMC_EXT_CSD_PWR_CL_52_POS 0 #define MMC_EXT_CSD_PWR_CL_DDR_52_POS 16 #else -#define MMC_VOLTAGE_RANGE MMC_HIGH_VOLTAGE_RANGE +#define MMC_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE #define MMC_EXT_CSD_PWR_CL_26_INDEX 203 #define MMC_EXT_CSD_PWR_CL_52_INDEX 202 @@ -279,6 +280,11 @@ #define MMC_EXT_CSD_PWR_CL_DDR_52_POS 24 #endif /* (VDD_VALUE) && (VDD_VALUE <= 1950U)*/ +#define MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_INDEX 216 +#define MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_POS 0 +#define MMC_EXT_CSD_S_A_TIMEOUT_INDEX 217 +#define MMC_EXT_CSD_S_A_TIMEOUT_POS 8 + /* Frequencies used in the driver for clock divider calculation */ #define MMC_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */ #define MMC_HIGH_SPEED_FREQ 52000000U /* High speed phase : 52 MHz max */ @@ -446,8 +452,15 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) /* wait 74 Cycles: required power up waiting time before starting the MMC initialization sequence */ - sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); - HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); + if (Init.ClockDiv != 0U) + { + sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); + } + + if (sdmmc_clk != 0U) + { + HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); + } /* Identify card operating voltage */ errorstate = MMC_PowerON(hmmc); @@ -584,7 +597,8 @@ __weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc) * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, - uint32_t NumberOfBlocks, uint32_t Timeout) + uint32_t NumberOfBlocks, + uint32_t Timeout) { SDMMC_DataInitTypeDef config; uint32_t errorstate; @@ -612,7 +626,8 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui } /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ - if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) + & 0x000000FFU) != 0x0U) { if ((NumberOfBlocks % 8U) != 0U) { @@ -778,7 +793,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui * @param Timeout: Specify timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, +HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) { SDMMC_DataInitTypeDef config; @@ -788,7 +803,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u uint32_t data; uint32_t dataremaining; uint32_t add = BlockAdd; - uint8_t *tempbuff = pData; + const uint8_t *tempbuff = pData; if (NULL == pData) { @@ -974,8 +989,8 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u * @param NumberOfBlocks: Number of blocks to read. * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, - uint32_t BlockAdd, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; @@ -1087,7 +1102,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, * @param NumberOfBlocks: Number of blocks to write * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, +HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; @@ -1201,8 +1216,8 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData * @param NumberOfBlocks: Number of blocks to read. * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, - uint32_t BlockAdd, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; @@ -1316,7 +1331,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData * @param NumberOfBlocks: Number of blocks to write * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, +HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; @@ -1451,7 +1466,8 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, } /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ - if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) + & 0x000000FFU) != 0x0U) { if (((start_add % 8U) != 0U) || ((end_add % 8U) != 0U)) { @@ -1830,6 +1846,9 @@ __weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc) /** * @brief Register a User MMC Callback * To be used instead of the weak (surcharged) predefined callback + * @note The HAL_MMC_RegisterCallback() may be called before HAL_MMC_Init() in + * HAL_MMC_STATE_RESET to register callbacks for HAL_MMC_MSP_INIT_CB_ID + * and HAL_MMC_MSP_DEINIT_CB_ID. * @param hmmc : MMC handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: @@ -1856,9 +1875,6 @@ HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Call return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hmmc); - if (hmmc->State == HAL_MMC_STATE_READY) { switch (CallbackId) @@ -1921,14 +1937,15 @@ HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hmmc); return status; } /** * @brief Unregister a User MMC Callback * MMC Callback is redirected to the weak (surcharged) predefined callback + * @note The HAL_MMC_UnRegisterCallback() may be called before HAL_MMC_Init() in + * HAL_MMC_STATE_RESET to register callbacks for HAL_MMC_MSP_INIT_CB_ID + * and HAL_MMC_MSP_DEINIT_CB_ID. * @param hmmc : MMC handle * @param CallbackId : ID of the callback to be unregistered * This parameter can be one of the following values: @@ -1946,9 +1963,6 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hmmc); - if (hmmc->State == HAL_MMC_STATE_READY) { switch (CallbackId) @@ -2011,8 +2025,6 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hmmc); return status; } #endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ @@ -2641,35 +2653,90 @@ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc) */ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) { - HAL_MMC_CardStateTypeDef CardState; + uint32_t error_code; + uint32_t tickstart; - /* DIsable All interrupts */ - __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ - SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); + if (hmmc->State == HAL_MMC_STATE_BUSY) + { + /* DIsable All interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); - /* Clear All flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /*we will send the CMD12 in all cases in order to stop the data transfers*/ + /*In case the data transfer just finished , the external memory will not respond and will return HAL_MMC_ERROR_CMD_RSP_TIMEOUT*/ + /*In case the data transfer aborted , the external memory will respond and will return HAL_MMC_ERROR_NONE*/ + /*Other scenario will return HAL_ERROR*/ - /* If IDMA Context, disable Internal DMA */ - hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance); + error_code = hmmc->ErrorCode; + if ((error_code != HAL_MMC_ERROR_NONE) && (error_code != HAL_MMC_ERROR_CMD_RSP_TIMEOUT)) + { + return HAL_ERROR; + } - hmmc->State = HAL_MMC_STATE_READY; + tickstart = HAL_GetTick(); + if ((hmmc->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_CARD) + { + if (hmmc->ErrorCode == HAL_MMC_ERROR_NONE) + { + while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + } - /* Initialize the MMC operation */ - hmmc->Context = MMC_CONTEXT_NONE; + if (hmmc->ErrorCode == HAL_MMC_ERROR_CMD_RSP_TIMEOUT) + { + while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + } + } + else if ((hmmc->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_SDMMC) + { + while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + } + else + { + /* Nothing to do*/ + } - CardState = HAL_MMC_GetCardState(hmmc); - if ((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) - { - hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance); - } - if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE) - { - return HAL_ERROR; + /*The reason of all these while conditions previously is that we need to wait the SDMMC and clear the appropriate flags that will be set depending of the abort/non abort of the memory */ + /*Not waiting the SDMMC flags will cause the next SDMMC_DISABLE_IDMA to not get cleared and will result in next SDMMC read/write operation to fail */ + + /*SDMMC ready for clear data flags*/ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* If IDMA Context, disable Internal DMA */ + hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + + hmmc->State = HAL_MMC_STATE_READY; + + /* Initialize the MMC operation */ + hmmc->Context = MMC_CONTEXT_NONE; } return HAL_OK; } - /** * @brief Abort the current transfer and disable the MMC (IT mode). * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains @@ -3102,6 +3169,343 @@ HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, ui } } +/** + * @brief Switch the device from Standby State to Sleep State. + * @param hmmc pointer to MMC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc) +{ + uint32_t errorstate, + sleep_timeout, + timeout, + count, + response = 0U ; + uint32_t tickstart = HAL_GetTick(); + + /* Check the state of the driver */ + if (hmmc->State == HAL_MMC_STATE_READY) + { + /* Change State */ + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Set the power-off notification to powered-on : Ext_CSD[34] = 1 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220100U)); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + } while (((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + else + { + /* Set the power-off notification to sleep notification : Ext_CSD[34] = 4 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220400U)); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Field SLEEP_NOTIFICATION_TIME [216] */ + sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_INDEX / 4)] >> + MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_POS) & 0x000000FFU); + + /* Sleep/Awake Timeout = 10us * 2^SLEEP_NOTIFICATION_TIME */ + /* In HAL, the tick interrupt occurs each ms */ + if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U)) + { + sleep_timeout = 0x17U; /* Max register value defined is 0x17 */ + } + timeout = (((1UL << sleep_timeout) / 100U) + 1U); + + /* Wait that the device is ready by checking the D0 line */ + while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) + { + if ((HAL_GetTick() - tickstart) >= timeout) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + } + + /* Clear the flag corresponding to end D0 bus line */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); + + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, + (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + } while (((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + else + { + /* Switch the device in stand-by mode */ + (void)SDMMC_CmdSelDesel(hmmc->Instance, 0U); + + /* Field S_A_TIEMOUT [217] */ + sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_S_A_TIMEOUT_INDEX / 4)] >> + MMC_EXT_CSD_S_A_TIMEOUT_POS) & 0x000000FFU); + + /* Sleep/Awake Timeout = 100ns * 2^S_A_TIMEOUT */ + /* In HAL, the tick interrupt occurs each ms */ + if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U)) + { + sleep_timeout = 0x17U; /* Max register value defined is 0x17 */ + } + timeout = (((1UL << sleep_timeout) / 10000U) + 1U); + + if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_STANDBY) + { + /* Send CMD5 CMD_MMC_SLEEP_AWAKE with RCA and SLEEP as argument */ + errorstate = SDMMC_CmdSleepMmc(hmmc->Instance, + ((hmmc->MmcCard.RelCardAdd << 16U) | (0x1U << 15U))); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Wait that the device is ready by checking the D0 line */ + while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) + { + if ((HAL_GetTick() - tickstart) >= timeout) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + } + + /* Clear the flag corresponding to end D0 bus line */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); + } + } + else + { + errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE; + } + } + } + else + { + /* Nothing to do */ + } + } + } + } + } + else + { + /* Nothing to do */ + } + } + + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + + /* Manage errors */ + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + + if (errorstate != HAL_MMC_ERROR_TIMEOUT) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + else + { + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Switch the device from Sleep State to Standby State. + * @param hmmc pointer to MMC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc) +{ + uint32_t errorstate; + uint32_t sleep_timeout; + uint32_t timeout; + uint32_t count; + uint32_t response = 0U; + uint32_t tickstart = HAL_GetTick(); + + /* Check the state of the driver */ + if (hmmc->State == HAL_MMC_STATE_READY) + { + /* Change State */ + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Field S_A_TIEMOUT [217] */ + sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_S_A_TIMEOUT_INDEX / 4)] >> MMC_EXT_CSD_S_A_TIMEOUT_POS) & + 0x000000FFU); + + /* Sleep/Awake Timeout = 100ns * 2^S_A_TIMEOUT */ + /* In HAL, the tick interrupt occurs each ms */ + if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U)) + { + sleep_timeout = 0x17U; /* Max register value defined is 0x17 */ + } + timeout = (((1UL << sleep_timeout) / 10000U) + 1U); + + /* Send CMD5 CMD_MMC_SLEEP_AWAKE with RCA and AWAKE as argument */ + errorstate = SDMMC_CmdSleepMmc(hmmc->Instance, (hmmc->MmcCard.RelCardAdd << 16U)); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Wait that the device is ready by checking the D0 line */ + while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) + { + if ((HAL_GetTick() - tickstart) >= timeout) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + } + + /* Clear the flag corresponding to end D0 bus line */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); + + if (errorstate == HAL_MMC_ERROR_NONE) + { + if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_STANDBY) + { + /* Switch the device in transfer mode */ + errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (hmmc->MmcCard.RelCardAdd << 16U)); + if (errorstate == HAL_MMC_ERROR_NONE) + { + if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_TRANSFER) + { + /* Set the power-off notification to powered-on : Ext_CSD[34] = 1 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220100U)); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, + (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + } while (((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + } + else + { + /* NOthing to do */ + } + } + } + else + { + errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE; + } + } + } + else + { + errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE; + } + } + } + + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + + /* Manage errors */ + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + + if (errorstate != HAL_MMC_ERROR_TIMEOUT) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + else + { + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} /** * @} */ @@ -3361,7 +3765,8 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel } /* Poll on SDMMC flags */ - while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | + SDMMC_FLAG_DATAEND)) { if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) { @@ -3479,7 +3884,7 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) { uint32_t count; uint32_t data; - uint8_t *tmp; + const uint8_t *tmp; tmp = hmmc->pTxBuffPtr; @@ -3582,13 +3987,21 @@ static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state) { /* High Speed Clock should be less or equal to 52MHz*/ sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC); + if (sdmmc_clk == 0U) { errorstate = SDMMC_ERROR_INVALID_PARAMETER; } else { - Init.ClockDiv = sdmmc_clk / (2U * MMC_HIGH_SPEED_FREQ); + if (sdmmc_clk <= MMC_HIGH_SPEED_FREQ) + { + Init.ClockDiv = 0; + } + else + { + Init.ClockDiv = (sdmmc_clk / (2U * MMC_HIGH_SPEED_FREQ)) + 1U; + } (void)SDMMC_Init(hmmc->Instance, Init); SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED); diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mmc.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mmc.h index 9f63d6d567c..283746df8de 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mmc.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mmc.h @@ -63,15 +63,18 @@ typedef enum */ typedef uint32_t HAL_MMC_CardStateTypeDef; -#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready */ -#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */ -#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */ -#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */ -#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */ -#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */ -#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */ -#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */ -#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error */ +#define HAL_MMC_CARD_IDLE 0x00000000U /*!< Card is in idle state (can't be checked by CMD13) */ +#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready (can't be checked by CMD13) */ +#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state (can't be checked by CMD13) */ +#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */ +#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */ +#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */ +#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */ +#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */ +#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */ +#define HAL_MMC_CARD_BUSTEST 0x00000009U /*!< Card is in bus test state */ +#define HAL_MMC_CARD_SLEEP 0x0000000AU /*!< Card is in sleep state (can't be checked by CMD13) */ +#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error (can't be checked by CMD13) */ /** * @} */ @@ -118,7 +121,7 @@ typedef struct HAL_LockTypeDef Lock; /*!< MMC locking object */ - uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ uint32_t TxXferSize; /*!< MMC Tx Transfer size */ @@ -640,19 +643,20 @@ void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc); */ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, - uint32_t NumberOfBlocks, uint32_t Timeout); -HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks, + uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd); /* Non-Blocking mode: IT */ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, +HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, +HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc); @@ -724,6 +728,14 @@ HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, ui * @} */ +/** @defgroup MMC_Exported_Functions_Group8 Peripheral Sleep management + * @{ + */ +HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc); +/** + * @} + */ /* Private types -------------------------------------------------------------*/ /** @defgroup MMC_Private_Types MMC Private Types * @{ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mmc_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mmc_ex.c index 13a4338cc0c..8762b3c8ef1 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mmc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_mmc_ex.c @@ -30,6 +30,7 @@ HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions. @endverbatim + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_nand.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_nand.c index ccbad52fbae..182e0061edb 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_nand.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_nand.c @@ -69,25 +69,25 @@ The compilation define USE_HAL_NAND_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_NAND_RegisterCallback() to register a user callback, + Use Functions HAL_NAND_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) MspInitCallback : NAND MspInit. (+) MspDeInitCallback : NAND MspDeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_NAND_UnRegisterCallback() to reset a callback to the default + Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) MspInitCallback : NAND MspInit. (+) MspDeInitCallback : NAND MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET + By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_NAND_Init - and @ref HAL_NAND_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_NAND_Init and @ref HAL_NAND_DeInit + reset to the legacy weak (surcharged) functions in the HAL_NAND_Init + and HAL_NAND_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -95,8 +95,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_NAND_RegisterCallback before calling @ref HAL_NAND_DeInit - or @ref HAL_NAND_Init function. + using HAL_NAND_RegisterCallback before calling HAL_NAND_DeInit + or HAL_NAND_Init function. When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -516,8 +516,8 @@ HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceC * @param NumPageToRead number of pages to read from block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, - uint32_t NumPageToRead) +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumPageToRead) { uint32_t index; uint32_t tickstart; @@ -674,8 +674,8 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT * @param NumPageToRead number of pages to read from block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, - uint32_t NumPageToRead) +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumPageToRead) { uint32_t index; uint32_t tickstart; @@ -842,8 +842,8 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address * @param NumPageToWrite number of pages to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, - uint32_t NumPageToWrite) +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint8_t *pBuffer, uint32_t NumPageToWrite) { uint32_t index; uint32_t tickstart; @@ -851,7 +851,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address uint32_t numpageswritten = 0U; uint32_t nandaddress; uint32_t nbpages = NumPageToWrite; - uint8_t *buff = pBuffer; + const uint8_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -995,8 +995,8 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address * @param NumPageToWrite number of pages to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, - uint32_t NumPageToWrite) +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint16_t *pBuffer, uint32_t NumPageToWrite) { uint32_t index; uint32_t tickstart; @@ -1004,7 +1004,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres uint32_t numpageswritten = 0U; uint32_t nandaddress; uint32_t nbpages = NumPageToWrite; - uint16_t *buff = pBuffer; + const uint16_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1159,8 +1159,8 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres * @param NumSpareAreaToRead Number of spare area to read * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, - uint32_t NumSpareAreaToRead) +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumSpareAreaToRead) { uint32_t index; uint32_t tickstart; @@ -1324,7 +1324,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add * @param NumSpareAreaToRead Number of spare area to read * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead) { uint32_t index; @@ -1489,8 +1489,8 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad * @param NumSpareAreaTowrite number of spare areas to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, - uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) { uint32_t index; uint32_t tickstart; @@ -1499,7 +1499,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaTowrite; - uint8_t *buff = pBuffer; + const uint8_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1652,8 +1652,8 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad * @param NumSpareAreaTowrite number of spare areas to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, - uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) { uint32_t index; uint32_t tickstart; @@ -1662,7 +1662,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaTowrite; - uint16_t *buff = pBuffer; + const uint16_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1813,7 +1813,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A * @param pAddress pointer to NAND address structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) +HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress) { uint32_t deviceaddress; @@ -1869,7 +1869,7 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy * - NAND_VALID_ADDRESS: When the new address is valid address * - NAND_INVALID_ADDRESS: When the new address is invalid address */ -uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) +uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) { uint32_t status = NAND_VALID_ADDRESS; @@ -2180,7 +2180,7 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, * the configuration information for NAND module. * @retval HAL state */ -HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) +HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand) { return hnand->State; } @@ -2191,7 +2191,7 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) * the configuration information for NAND module. * @retval NAND status */ -uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) +uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand) { uint32_t data; uint32_t deviceaddress; @@ -2239,4 +2239,3 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) * @} */ - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_nand.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_nand.h index a36c6dd0612..8e9b57fb71c 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_nand.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_nand.h @@ -106,7 +106,7 @@ typedef struct command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. Example: Toshiba THTH58BYG3S0HBAI6. This parameter could be ENABLE or DISABLE - Please check the Read Mode sequnece in the NAND device datasheet */ + Please check the Read Mode sequence in the NAND device datasheet */ } NAND_DeviceConfigTypeDef; /** @@ -126,7 +126,7 @@ typedef struct __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ - NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ + NAND_DeviceConfigTypeDef Config; /*!< NAND physical characteristic information structure */ #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */ @@ -214,27 +214,27 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); /* IO operation functions ****************************************************/ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, - uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, - uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint8_t *pBuffer, uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, - uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); - -HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, - uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, - uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); + +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint16_t *pBuffer, uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, - uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); -HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); +HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress); -uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); +uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) /* NAND callback registering/unregistering */ @@ -264,8 +264,8 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, * @{ */ /* NAND State functions *******************************************************/ -HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); -uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); +HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand); +uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand); /** * @} */ @@ -375,4 +375,3 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); #endif #endif /* STM32U5xx_HAL_NAND_H */ - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_nor.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_nor.c index 8486db0d627..e55cadf075c 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_nor.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_nor.c @@ -66,25 +66,25 @@ The compilation define USE_HAL_NOR_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_NOR_RegisterCallback() to register a user callback, + Use Functions HAL_NOR_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) MspInitCallback : NOR MspInit. (+) MspDeInitCallback : NOR MspDeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_NOR_UnRegisterCallback() to reset a callback to the default + Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) MspInitCallback : NOR MspInit. (+) MspDeInitCallback : NOR MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET + By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_NOR_Init - and @ref HAL_NOR_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_NOR_Init and @ref HAL_NOR_DeInit + reset to the legacy weak (surcharged) functions in the HAL_NOR_Init + and HAL_NOR_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -92,8 +92,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_NOR_RegisterCallback before calling @ref HAL_NOR_DeInit - or @ref HAL_NOR_Init function. + using HAL_NOR_RegisterCallback before calling HAL_NOR_DeInit + or HAL_NOR_Init function. When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -126,6 +126,11 @@ */ /* Constants to define address to set to write a command */ +#define NOR_CMD_ADDRESS_FIRST_BYTE (uint16_t)0x0AAA +#define NOR_CMD_ADDRESS_FIRST_CFI_BYTE (uint16_t)0x00AA +#define NOR_CMD_ADDRESS_SECOND_BYTE (uint16_t)0x0555 +#define NOR_CMD_ADDRESS_THIRD_BYTE (uint16_t)0x0AAA + #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA @@ -229,6 +234,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe FMC_NORSRAM_TimingTypeDef *ExtTiming) { uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR handle parameter */ if (hnor == NULL) @@ -262,7 +268,8 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); /* Initialize NOR extended mode timing Interface */ - (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode); + (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, + hnor->Init.NSBank, hnor->Init.ExtendedMode); /* Enable the NORSRAM device */ __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); @@ -301,11 +308,32 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe deviceaddress = NOR_MEMORY_ADRESS4; } - /* Get the value of the command set */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); - hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET); + if (hnor->Init.WriteOperation == FMC_WRITE_OPERATION_DISABLE) + { + (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_PROTECTED; + } + else + { + /* Get the value of the command set */ + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE), + NOR_CMD_DATA_CFI); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + } + + hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET); + + status = HAL_NOR_ReturnToReadMode(hnor); + } - return HAL_NOR_ReturnToReadMode(hnor); + return status; } /** @@ -380,7 +408,7 @@ __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor) * @param Timeout Maximum timeout value * @retval None */ -__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) +__weak void HAL_NOR_MspWait(const NOR_HandleTypeDef *hnor, uint32_t Timeout) { /* Prevent unused argument(s) compilation warning */ UNUSED(hnor); @@ -428,7 +456,11 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I { return HAL_BUSY; } - else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED)) + else if (state == HAL_NOR_STATE_PROTECTED) + { + return HAL_ERROR; + } + else if (state == HAL_NOR_STATE_READY) { /* Process Locked */ __HAL_LOCK(hnor); @@ -457,9 +489,22 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I /* Send read ID command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_AUTO_SELECT); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_AUTO_SELECT); + } } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -515,7 +560,11 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) { return HAL_BUSY; } - else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED)) + else if (state == HAL_NOR_STATE_PROTECTED) + { + return HAL_ERROR; + } + else if (state == HAL_NOR_STATE_READY) { /* Process Locked */ __HAL_LOCK(hnor); @@ -589,7 +638,11 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint { return HAL_BUSY; } - else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED)) + else if (state == HAL_NOR_STATE_PROTECTED) + { + return HAL_ERROR; + } + else if (state == HAL_NOR_STATE_READY) { /* Process Locked */ __HAL_LOCK(hnor); @@ -618,9 +671,22 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint /* Send read data command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_READ_RESET); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_READ_RESET); + } } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -699,9 +765,21 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u /* Send program data command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_PROGRAM); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); + } } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -758,7 +836,11 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress { return HAL_BUSY; } - else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED)) + else if (state == HAL_NOR_STATE_PROTECTED) + { + return HAL_ERROR; + } + else if (state == HAL_NOR_STATE_READY) { /* Process Locked */ __HAL_LOCK(hnor); @@ -787,9 +869,22 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress /* Send read data command */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_READ_RESET); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_READ_RESET); + } } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) { @@ -882,10 +977,20 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - /* Issue unlock command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + /* Issue unlock command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + } + else + { + /* Issue unlock command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + } /* Write Buffer Load Command */ NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U)); @@ -985,14 +1090,26 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd /* Send block erase command sequence */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + } NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); } else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) @@ -1070,15 +1187,28 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) /* Send NOR chip erase command sequence */ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), + NOR_CMD_DATA_CHIP_ERASE); + } } else { @@ -1118,7 +1248,11 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR { return HAL_BUSY; } - else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED)) + else if (state == HAL_NOR_STATE_PROTECTED) + { + return HAL_ERROR; + } + else if (state == HAL_NOR_STATE_READY) { /* Process Locked */ __HAL_LOCK(hnor); @@ -1145,8 +1279,15 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR } /* Send read CFI query command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); - + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE), + NOR_CMD_DATA_CFI); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + } /* read the NOR CFI information */ pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS); pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS); @@ -1380,7 +1521,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) * the configuration information for NOR module. * @retval NOR controller state */ -HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) +HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor) { return hnor->State; } @@ -1394,7 +1535,7 @@ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) * @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR * or HAL_NOR_STATUS_TIMEOUT */ -HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) +HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(const NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) { HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING; uint16_t tmpsr1; @@ -1509,4 +1650,3 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres * @} */ - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_nor.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_nor.h index ee1e563f016..dac7063de76 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_nor.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_nor.h @@ -183,7 +183,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); -void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout); +void HAL_NOR_MspWait(const NOR_HandleTypeDef *hnor, uint32_t Timeout); /** * @} */ @@ -233,8 +233,8 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); */ /* NOR State functions ********************************************************/ -HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor); -HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); +HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor); +HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(const NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); /** * @} */ @@ -322,4 +322,3 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres #endif #endif /* STM32U5xx_HAL_NOR_H */ - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_opamp.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_opamp.c index fb76097924a..cbca4bd18e2 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_opamp.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_opamp.c @@ -118,7 +118,7 @@ and a pointer to the user callback function. (++) Use function @ref HAL_OPAMP_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+++) MspInitCallback : OPAMP MspInit. (+++) MspDeInitCallback : OPAMP MspdeInit. (+++) All Callbacks @@ -904,10 +904,11 @@ HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp) * */ -HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset) +HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(const OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset) { HAL_OPAMP_TrimmingValueTypeDef trimmingvalue; - __IO uint32_t *tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */ + __IO const uint32_t *tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or + LPOTR */ /* Check the OPAMP handle allocation */ /* Value can be retrieved in HAL_OPAMP_STATE_READY state */ @@ -941,11 +942,11 @@ HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(OPAMP_HandleTypeDef *hopa if ((hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED) || \ (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED)) { - tmp_opamp_reg_trimming = &OPAMP->OTR; + tmp_opamp_reg_trimming = &(hopamp->Instance->OTR); } else { - tmp_opamp_reg_trimming = &OPAMP->LPOTR; + tmp_opamp_reg_trimming = &(hopamp->Instance->LPOTR); } /* Get factory trimming */ @@ -992,7 +993,7 @@ HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(OPAMP_HandleTypeDef *hopa * @param hopamp : OPAMP handle * @retval HAL state */ -HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp) +HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(const OPAMP_HandleTypeDef *hopamp) { /* Check the OPAMP handle allocation */ if (hopamp == NULL) @@ -1028,7 +1029,7 @@ HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp) #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) /** * @brief Register a User OPAMP Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (overridden) predefined callback * @param hopamp : OPAMP handle * @param CallbackID : ID of the callback to be registered * This parameter can be one of the following values: @@ -1095,7 +1096,7 @@ HAL_StatusTypeDef HAL_OPAMP_RegisterCallback(OPAMP_HandleTypeDef *hopamp, HAL_OP /** * @brief Unregister a User OPAMP Callback - * OPAMP Callback is redirected to the weak (surcharged) predefined callback + * OPAMP Callback is redirected to the weak (overridden) predefined callback * @param hopamp : OPAMP handle * @param CallbackID : ID of the callback to be unregistered * This parameter can be one of the following values: diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_opamp.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_opamp.h index abca37a1f5f..294e240928e 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_opamp.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_opamp.h @@ -182,7 +182,6 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); #define OPAMP_NONINVERTINGINPUT_IO0 0x00000000U /*!< OPAMP non-inverting input connected to dedicated IO pin */ #define OPAMP_NONINVERTINGINPUT_DAC_CH OPAMP_CSR_VP_SEL /*!< OPAMP non-inverting input connected internally to DAC channel */ - /** * @} */ @@ -190,11 +189,9 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); /** @defgroup OPAMP_InvertingInput OPAMP Inverting Input * @{ */ - #define OPAMP_INVERTINGINPUT_IO0 0x00000000U /*!< OPAMP inverting input connected to dedicated IO pin low-leakage */ #define OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VM_SEL_0 /*!< OPAMP inverting input connected to alternative IO pin available on some device packages */ #define OPAMP_INVERTINGINPUT_CONNECT_NO OPAMP_CSR_VM_SEL_1 /*!< OPAMP inverting input not connected externally (PGA mode only) */ - /** * @} */ @@ -386,7 +383,7 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp); /* Peripheral Control functions ************************************************/ HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp); -HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset); +HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(const OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset); /** * @} @@ -397,7 +394,7 @@ HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(OPAMP_HandleTypeDef *hopa */ /* Peripheral State functions **************************************************/ -HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp); +HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(const OPAMP_HandleTypeDef *hopamp); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_opamp_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_opamp_ex.c index 6e34af0315f..f20407dca6f 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_opamp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_opamp_ex.c @@ -47,6 +47,7 @@ * @{ */ +#if defined(OPAMP2) /** @addtogroup OPAMPEx_Exported_Functions_Group1 * @brief Extended operation functions * @@ -366,7 +367,7 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /** * @} */ - +#endif /* OPAMP2 */ /** @defgroup OPAMPEx_Exported_Functions_Group2 Peripheral Control functions * @brief Peripheral Control functions diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_opamp_ex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_opamp_ex.h index 99947b3c8bf..6b40eb95c3a 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_opamp_ex.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_opamp_ex.h @@ -42,6 +42,7 @@ extern "C" { * @{ */ +#if defined(OPAMP2) /* I/O operation functions *****************************************************/ /** @addtogroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions * @{ @@ -51,6 +52,7 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /** * @} */ +#endif /* OPAMP2 */ /* Peripheral Control functions ************************************************/ /** @addtogroup OPAMPEx_Exported_Functions_Group2 diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ospi.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ospi.c index dc14ab5fea3..9ba57cf6cc6 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ospi.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ospi.c @@ -51,7 +51,7 @@ and the CS boundary using the HAL_OSPI_Init() function. [..] When using Hyperbus, configure the RW recovery time, the access time, - the write latency and the latency mode unsing the HAL_OSPI_HyperbusCfg() + the write latency and the latency mode using the HAL_OSPI_HyperbusCfg() function. *** Indirect functional mode *** @@ -282,7 +282,9 @@ static void OSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout); static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); +#if defined (OCTOSPIM) static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg); +#endif /** @endcond */ @@ -410,7 +412,7 @@ HAL_StatusTypeDef HAL_OSPI_Init(OSPI_HandleTypeDef *hospi) ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos)); /* Configure Dual Quad mode */ - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad); + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DMM, hospi->Init.DualQuad); /* Configure sample shifting and delay hold quarter cycle */ MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC), @@ -2581,6 +2583,7 @@ uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi) * @} */ +#if defined (OCTOSPIM) /** @defgroup OSPI_Exported_Functions_Group4 IO Manager configuration function * @brief OSPI IO Manager configuration function * @@ -2622,7 +2625,7 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * assert_param(IS_OSPIM_IO_PORT(cfg->IOLowPort)); assert_param(IS_OSPIM_IO_PORT(cfg->IOHighPort)); - if (hospi->Instance == OCTOSPI1) + if (hospi->Instance == (OCTOSPI_TypeDef *)OCTOSPI1) { instance = 0U; other_instance = 1U; @@ -2854,6 +2857,7 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * /** * @} */ +#endif /** @cond 0 @@ -3045,7 +3049,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC /* Configure the flash ID */ if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE) { - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FSEL, cmd->FlashId); + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_MSEL, cmd->FlashId); } if (cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG) @@ -3206,6 +3210,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC return status; } +#if defined (OCTOSPIM) /** * @brief Get the current IOM configuration for an OctoSPI instance. * @param instance_nb : number of the instance @@ -3320,6 +3325,7 @@ static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef * /* Return function status */ return status; } +#endif /** @defgroup OSPI_Exported_Functions_Group5 Delay Block function @@ -3346,11 +3352,13 @@ static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef * HAL_StatusTypeDef HAL_OSPI_DLYB_SetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg) { HAL_StatusTypeDef status = HAL_ERROR; - uint32_t tickstart; /* Enable OCTOSPI Free Running Clock (mandatory) */ SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK); + /* Update OCTOSPI state */ + hospi->State = HAL_OSPI_STATE_BUSY_CMD; + if (hospi->Instance == OCTOSPI1) { /* Enable the DelayBlock */ @@ -3361,6 +3369,7 @@ HAL_StatusTypeDef HAL_OSPI_DLYB_SetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DL status = HAL_OK; } +#if defined (OCTOSPI2) else if (hospi->Instance == OCTOSPI2) { /* Enable the DelayBlock */ @@ -3370,33 +3379,19 @@ HAL_StatusTypeDef HAL_OSPI_DLYB_SetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DL LL_DLYB_SetDelay(DLYB_OCTOSPI2, pdlyb_cfg); status = HAL_OK; } +#endif else { /* Nothing to do */ } - /* Disable OCTOSPI */ - __HAL_OSPI_DISABLE(hospi); - - /* Wait till OSPI Disabled or if Time out is reached, exit */ - tickstart = HAL_GetTick(); - while (READ_BIT(hospi->Instance->CR, OCTOSPI_CR_EN) == (uint32_t)SET) - { - if ((HAL_GetTick() - tickstart) > hospi->Timeout) - { - hospi->State = HAL_OSPI_STATE_ERROR; - hospi->ErrorCode |= HAL_OSPI_ERROR_TIMEOUT; - return HAL_TIMEOUT; - } - } + /* Abort the current OCTOSPI operation if exist */ + (void)HAL_OSPI_Abort(hospi); /* Disable Free Running Clock */ CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK); - /* Re-Enable OCTOSPI */ - __HAL_OSPI_ENABLE(hospi); - /* Return function status */ return status; } @@ -3416,11 +3411,13 @@ HAL_StatusTypeDef HAL_OSPI_DLYB_GetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DL LL_DLYB_GetDelay(DLYB_OCTOSPI1, pdlyb_cfg); status = HAL_OK; } +#if defined (OCTOSPI2) else if (hospi->Instance == OCTOSPI2) { LL_DLYB_GetDelay(DLYB_OCTOSPI2, pdlyb_cfg); status = HAL_OK; } +#endif else { @@ -3439,11 +3436,13 @@ HAL_StatusTypeDef HAL_OSPI_DLYB_GetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DL HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg) { HAL_StatusTypeDef status = HAL_ERROR; - uint32_t tickstart; /* Enable OCTOSPI Free Running Clock (mandatory) */ SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK); + /* Update OCTOSPI state */ + hospi->State = HAL_OSPI_STATE_BUSY_CMD; + if (hospi->Instance == OCTOSPI1) { /* Enable the DelayBlock */ @@ -3456,9 +3455,10 @@ HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, HAL_OS } /* Disable the DelayBlock */ - LL_DLYB_Enable(DLYB_OCTOSPI1); + LL_DLYB_Disable(DLYB_OCTOSPI1); } +#if defined (OCTOSPI2) else if (hospi->Instance == OCTOSPI2) { /* Enable the DelayBlock */ @@ -3471,35 +3471,21 @@ HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, HAL_OS } /* Disable the DelayBlock */ - LL_DLYB_Enable(DLYB_OCTOSPI2); + LL_DLYB_Disable(DLYB_OCTOSPI2); } +#endif else { /* Nothing to do */ } - /* Disable OCTOSPI */ - __HAL_OSPI_DISABLE(hospi); - - /* Wait till OSPI Disabled or if Time out is reached, exit */ - tickstart = HAL_GetTick(); - while (READ_BIT(hospi->Instance->CR, OCTOSPI_CR_EN) == (uint32_t)SET) - { - if ((HAL_GetTick() - tickstart) > hospi->Timeout) - { - hospi->State = HAL_OSPI_STATE_ERROR; - hospi->ErrorCode |= HAL_OSPI_ERROR_TIMEOUT; - return HAL_TIMEOUT; - } - } + /* Abort the current OctoSPI operation if exist */ + (void)HAL_OSPI_Abort(hospi); /* Disable Free Running Clock */ CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK); - /* Re-Enable OCTOSPI */ - __HAL_OSPI_ENABLE(hospi); - /* Return function status */ return status; } diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ospi.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ospi.h index 027c7cf9048..28a4f0aa6d8 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ospi.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ospi.h @@ -242,6 +242,7 @@ typedef struct This parameter can be any value between 0 and 0xFFFF */ } OSPI_MemoryMappedTypeDef; +#if defined (OCTOSPIM) /** * @brief HAL OSPI IO Manager Configuration structure definition */ @@ -261,6 +262,7 @@ typedef struct if some signals are multiplexed in the OSPI IO Manager with the other OSPI. This parameter can be a value between 1 and 256 */ } OSPIM_CfgTypeDef; +#endif #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) /** @@ -337,7 +339,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); * @{ */ #define HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */ -#define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DQM) /*!< Dual-Quad mode enabled */ +#define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DMM) /*!< Dual-Quad mode enabled */ /** * @} */ @@ -426,7 +428,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); * @{ */ #define HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U) /*!< FLASH 1 selected */ -#define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_FSEL) /*!< FLASH 2 selected */ +#define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_MSEL) /*!< FLASH 2 selected */ /** * @} */ @@ -653,6 +655,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); * @} */ +#if defined (OCTOSPIM) /** @defgroup OSPIM_IOPort OSPI IO Manager IO Port * @{ */ @@ -676,6 +679,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); /** * @} */ +#endif /** * @} */ @@ -873,6 +877,7 @@ uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi); * @} */ +#if defined (OCTOSPIM) /* OSPI IO Manager configuration function ************************************/ /** @addtogroup OSPI_Exported_Functions_Group4 * @{ @@ -883,6 +888,7 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeD * @} */ +#endif /* OSPI Delay Block function ************************************/ /** @addtogroup OSPI_Exported_Functions_Group5 Delay Block function @@ -1047,6 +1053,7 @@ HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, H ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED)) #define IS_OSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U) +#if defined (OCTOSPIM) #define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) @@ -1073,6 +1080,7 @@ HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, H #if defined (OCTOSPIM_CR_MUXEN) #define IS_OSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U)) #endif /*(OCTOSPIM_CR_MUXEN)*/ +#endif /** @endcond */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_otfdec.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_otfdec.c index 56a27a61ef6..02447f6ea99 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_otfdec.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_otfdec.c @@ -693,7 +693,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32 * @retval HAL state */ HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, - OTFDEC_RegionConfigTypeDef *Config, uint32_t lock) + const OTFDEC_RegionConfigTypeDef *Config, uint32_t lock) { OTFDEC_Region_TypeDef *region; uint32_t address; @@ -879,17 +879,20 @@ HAL_StatusTypeDef HAL_OTFDEC_DisableEnciphering(OTFDEC_HandleTypeDef *hotfdec) * @retval HAL state */ HAL_StatusTypeDef HAL_OTFDEC_Cipher(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, - uint32_t *input, uint32_t *output, uint32_t size, uint32_t start_address) + const uint32_t *input, uint32_t *output, uint32_t size, uint32_t start_address) { uint32_t j; __IO uint32_t *extMem_ptr = (uint32_t *)start_address; - uint32_t *in_ptr = input; + const uint32_t *in_ptr = input; uint32_t *out_ptr = output; /* Check the parameters */ assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance)); assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex)); + /* Prevent unused argument(s) compilation warning */ + UNUSED(RegionIndex); + if ((input == NULL) || (output == NULL) || (size == 0U)) { return HAL_ERROR; diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_otfdec.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_otfdec.h index 495005cb578..bfe659f16ac 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_otfdec.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_otfdec.h @@ -349,14 +349,14 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32 HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *pKey); HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode); HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, - OTFDEC_RegionConfigTypeDef *Config, uint32_t lock); + const OTFDEC_RegionConfigTypeDef *Config, uint32_t lock); uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey); HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); HAL_StatusTypeDef HAL_OTFDEC_ConfigAttributes(OTFDEC_HandleTypeDef *hotfdec, uint32_t Attributes); HAL_StatusTypeDef HAL_OTFDEC_EnableEnciphering(OTFDEC_HandleTypeDef *hotfdec); HAL_StatusTypeDef HAL_OTFDEC_DisableEnciphering(OTFDEC_HandleTypeDef *hotfdec); -HAL_StatusTypeDef HAL_OTFDEC_Cipher(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *input, +HAL_StatusTypeDef HAL_OTFDEC_Cipher(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, const uint32_t *input, uint32_t *output, uint32_t size, uint32_t start_address); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pcd.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pcd.c index 0c24acce11a..490c1236e7d 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pcd.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pcd.c @@ -37,6 +37,7 @@ (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: (##) Enable the PCD/USB Low Level interface clock using + (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device FS peripheral (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) @@ -68,7 +69,7 @@ #ifdef HAL_PCD_MODULE_ENABLED -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -92,6 +93,14 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#if defined (USB_DRD_FS) +static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); +#if (USE_USB_DOUBLE_BUFFER == 1U) +static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal); +static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal); +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -174,13 +183,15 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) } hpcd->State = HAL_PCD_STATE_BUSY; + #if defined (STM32U575xx) || defined (STM32U585xx) /* Disable DMA mode for FS instance */ - if ((USBx->CID & (0x1U << 8)) == 0U) + if ((USBx->CID & (0x1U << 14)) == 0U) { hpcd->Init.dma_enable = 0U; } #endif /* defined (STM32U575xx) || defined (STM32U585xx) */ + /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); @@ -200,7 +211,9 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /* Init ep structure */ hpcd->IN_ep[i].is_in = 1U; hpcd->IN_ep[i].num = i; +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) hpcd->IN_ep[i].tx_fifo_num = i; +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /* Control until ep is activated */ hpcd->IN_ep[i].type = EP_TYPE_CTRL; hpcd->IN_ep[i].maxpacket = 0U; @@ -322,7 +335,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID - * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID * @param pCallback pointer to the Callback function @@ -426,7 +439,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, /** * @brief Unregister an USB PCD Callback - * USB PCD callabck is redirected to the weak predefined callback + * USB PCD callback is redirected to the weak predefined callback * @param hpcd USB PCD handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -436,7 +449,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID - * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status @@ -1038,7 +1051,10 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) __HAL_PCD_DISABLE(hpcd); (void)USB_DevDisconnect(hpcd->Instance); + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #if defined (STM32U575xx) || defined (STM32U585xx) if (hpcd->Init.battery_charging_enable == 1U) @@ -1069,7 +1085,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) uint32_t epint; uint32_t epnum; uint32_t fifoemptymsk; - uint32_t temp; + uint32_t RegVal; /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) @@ -1080,6 +1096,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) return; } + /* store current frame number */ + hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos; + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) { /* incorrect mode, acknowledge the interrupt */ @@ -1091,30 +1110,31 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); - temp = USBx->GRXSTSP; + RegVal = USBx->GRXSTSP; - ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; + ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM]; - if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) + if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) { - if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U) + if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U) { (void)USB_ReadPacket(USBx, ep->xfer_buff, - (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4)); + (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4)); - ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; } } - else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) + else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) { (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; } else { /* ... */ } + USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); } @@ -1149,6 +1169,30 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); } + /* Clear OUT Endpoint disable interrupt */ + if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD) + { + if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; + } + + ep = &hpcd->OUT_ep[epnum]; + + if (ep->is_iso_incomplete == 1U) + { + ep->is_iso_incomplete = 0U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD); + } + /* Clear Status Phase Received interrupt */ if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) { @@ -1218,6 +1262,21 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) { + (void)USB_FlushTxFifo(USBx, epnum); + + ep = &hpcd->IN_ep[epnum]; + + if (ep->is_iso_incomplete == 1U) + { + ep->is_iso_incomplete = 0U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); } if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) @@ -1308,7 +1367,6 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { USBx_INEP(i)->DIEPINT = 0xFB7FU; USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; USBx_OUTEP(i)->DOEPINT = 0xFB7FU; USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; @@ -1380,18 +1438,37 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); } + /* Handle Global OUT NAK effective Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF)) + { + USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; + + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) + { + /* Abort current transaction and disable the EP */ + (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); + } + } + } + /* Handle Incomplete ISO IN Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) { - /* Keep application checking the corresponding Iso IN endpoint - causing the incomplete Interrupt */ - epnum = 0U; + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + RegVal = USBx_INEP(epnum)->DIEPCTL; -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && + ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)) + { + hpcd->IN_ep[epnum].is_iso_incomplete = 1U; + + /* Abort current transaction and disable the EP */ + (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U)); + } + } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); } @@ -1399,15 +1476,25 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Handle Incomplete ISO OUT Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) { - /* Keep application checking the corresponding Iso OUT endpoint - causing the incomplete Interrupt */ - epnum = 0U; + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + RegVal = USBx_OUTEP(epnum)->DOEPCTL; -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && + ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && + ((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U))) + { + hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; + + USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM; + + if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; + break; + } + } + } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); } @@ -1427,9 +1514,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Handle Disconnection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) { - temp = hpcd->Instance->GOTGINT; + RegVal = hpcd->Instance->GOTGINT; - if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) + if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DisconnectCallback(hpcd); @@ -1437,12 +1524,157 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) HAL_PCD_DisconnectCallback(hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - hpcd->Instance->GOTGINT |= temp; + hpcd->Instance->GOTGINT |= RegVal; } } } #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) +/** + * @brief This function handles PCD interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) +{ + uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance); + + if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR) + { + /* servicing of the endpoint correct transfer interrupt */ + /* clear of the CTR flag into the sub */ + (void)PCD_EP_ISR_Handler(hpcd); + + return; + } + + if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResetCallback(hpcd); +#else + HAL_PCD_ResetCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + (void)HAL_PCD_SetAddress(hpcd, 0U); + + return; + } + + if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); + + return; + } + + if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); + + return; + } + + if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP) + { + hpcd->Instance->CNTR &= ~(USB_CNTR_SUSPRDY); + hpcd->Instance->CNTR &= ~(USB_CNTR_SUSPEN); + + if (hpcd->LPM_State == LPM_L1) + { + hpcd->LPM_State = LPM_L0; +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); +#else + HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResumeCallback(hpcd); +#else + HAL_PCD_ResumeCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); + + return; + } + + if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP) + { + /* Force low-power mode in the macrocell */ + hpcd->Instance->CNTR |= USB_CNTR_SUSPEN; + + /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); + + hpcd->Instance->CNTR |= USB_CNTR_SUSPRDY; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else + HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + return; + } + + /* Handle LPM Interrupt */ + if ((wIstr & USB_ISTR_L1REQ) == USB_ISTR_L1REQ) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ); + if (hpcd->LPM_State == LPM_L0) + { + /* Force suspend and low-power mode before going to L1 state*/ + hpcd->Instance->CNTR |= USB_CNTR_SUSPRDY; + hpcd->Instance->CNTR |= USB_CNTR_SUSPEN; + + hpcd->LPM_State = LPM_L1; + hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2; +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); +#else + HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else + HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + return; + } + + if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SOFCallback(hpcd); +#else + HAL_PCD_SOFCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + return; + } + + if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF) + { + /* clear ESOF flag in ISTR */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); + + return; + } +} +#endif /* defined (USB_DRD_FS) */ /** * @brief Data OUT stage callback. @@ -1733,11 +1965,14 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, ep->maxpacket = ep_mps; ep->type = ep_type; +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) if (ep->is_in != 0U) { /* Assign a Tx FIFO */ ep->tx_fifo_num = ep->num; } +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) { @@ -1771,7 +2006,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; ep->is_in = 0U; } - ep->num = ep_addr & EP_ADDR_MSK; + ep->num = ep_addr & EP_ADDR_MSK; __HAL_LOCK(hpcd); (void)USB_DeactivateEndpoint(hpcd->Instance, ep); @@ -1801,19 +2036,16 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u ep->is_in = 0U; ep->num = ep_addr & EP_ADDR_MSK; +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) if (hpcd->Init.dma_enable == 1U) { ep->dma_addr = (uint32_t)pBuf; } - if ((ep_addr & EP_ADDR_MSK) == 0U) - { - (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); - } - else - { - (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); - } + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); +#else + (void)USB_EPStartXfer(hpcd->Instance, ep); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ return HAL_OK; } @@ -1845,23 +2077,24 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, /*setup and start the Xfer */ ep->xfer_buff = pBuf; ep->xfer_len = len; +#if defined (USB_DRD_FS) + ep->xfer_fill_db = 1U; + ep->xfer_len_db = len; +#endif /* defined (USB_DRD_FS) */ ep->xfer_count = 0U; ep->is_in = 1U; ep->num = ep_addr & EP_ADDR_MSK; +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) if (hpcd->Init.dma_enable == 1U) { ep->dma_addr = (uint32_t)pBuf; } - if ((ep_addr & EP_ADDR_MSK) == 0U) - { - (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); - } - else - { - (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); - } + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); +#else + (void)USB_EPStartXfer(hpcd->Instance, ep); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ return HAL_OK; } @@ -1899,10 +2132,12 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) (void)USB_EPSetStall(hpcd->Instance, ep); +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) if ((ep_addr & EP_ADDR_MSK) == 0U) { (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); } +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ __HAL_UNLOCK(hpcd); @@ -1945,6 +2180,32 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) return HAL_OK; } +/** + * @brief Abort an USB EP transaction. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + HAL_StatusTypeDef ret; + PCD_EPTypeDef *ep; + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + } + + /* Stop Xfer */ + ret = USB_EPStopXfer(hpcd->Instance, ep); + + return ret; +} + /** * @brief Flush an endpoint * @param hpcd PCD handle @@ -1953,6 +2214,7 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) */ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) __HAL_LOCK(hpcd); if ((ep_addr & 0x80U) == 0x80U) @@ -1965,6 +2227,11 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) } __HAL_UNLOCK(hpcd); +#else + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(ep_addr); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ return HAL_OK; } @@ -2018,6 +2285,35 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) return hpcd->State; } +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Set the USB Device high speed test mode. + * @param hpcd PCD handle + * @param testmode USB Device high speed test mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + + switch (testmode) + { + case TEST_J: + case TEST_K: + case TEST_SE0_NAK: + case TEST_PACKET: + case TEST_FORCE_EN: + USBx_DEVICE->DCTL |= (uint32_t)testmode << 4; + break; + + default: + break; + } + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /** * @} */ @@ -2099,6 +2395,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t */ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { + USB_OTG_EPTypeDef *ep; USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); @@ -2129,18 +2426,24 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint } else { - /* out data packet received over EP0 */ - hpcd->OUT_ep[epnum].xfer_count = - hpcd->OUT_ep[epnum].maxpacket - - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); + ep = &hpcd->OUT_ep[epnum]; - hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket; + /* out data packet received over EP */ + ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); - if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) + if (epnum == 0U) { - /* this is ZLP, so prepare EP0 for next setup */ - (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + if (ep->xfer_len == 0U) + { + /* this is ZLP, so prepare EP0 for next setup */ + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + } + else + { + ep->xfer_buff += ep->xfer_count; + } } + #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else @@ -2231,11 +2534,539 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint } #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) +/** + * @brief This function handles PCD Endpoint interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) +{ + PCD_EPTypeDef *ep; + uint16_t count; + uint16_t wIstr; + uint16_t wEPVal; + uint16_t TxPctSize; + uint8_t epindex; + +#if (USE_USB_DOUBLE_BUFFER != 1U) + count = 0U; +#endif /* USE_USB_DOUBLE_BUFFER */ + + /* stay in loop while pending interrupts */ + while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) + { + wIstr = (uint16_t)hpcd->Instance->ISTR; + + /* extract highest priority endpoint number */ + epindex = (uint8_t)(wIstr & USB_ISTR_IDN); + + if (epindex == 0U) + { + /* Decode and service control endpoint interrupt */ + + /* DIR bit = origin of the interrupt */ + if ((wIstr & USB_ISTR_DIR) == 0U) + { + /* DIR = 0 */ + + /* DIR = 0 => IN int */ + /* DIR = 0 implies that (EP_CTR_TX = 1) always */ + PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); + ep = &hpcd->IN_ep[0]; + + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + ep->xfer_buff += ep->xfer_count; + + /* TX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, 0U); +#else + HAL_PCD_DataInStageCallback(hpcd, 0U); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U)) + { + hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF); + hpcd->USB_Address = 0U; + } + } + else + { + /* DIR = 1 */ + + /* DIR = 1 & CTR_RX => SETUP or OUT int */ + /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ + ep = &hpcd->OUT_ep[0]; + wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); + + if ((wEPVal & USB_EP_SETUP) != 0U) + { + /* Get SETUP Packet */ + ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + + USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, + ep->pmaadress, (uint16_t)ep->xfer_count); + + /* SETUP bit kept frozen while CTR_RX = 1 */ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + + /* Process SETUP Packet*/ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SetupStageCallback(hpcd); +#else + HAL_PCD_SetupStageCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else if ((wEPVal & USB_EP_VTRX) != 0U) + { + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + + /* Get Control Data OUT Packet */ + ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + + if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U)) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, + ep->pmaadress, (uint16_t)ep->xfer_count); + + ep->xfer_buff += ep->xfer_count; + + /* Process Control Data OUT Packet */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, 0U); +#else + HAL_PCD_DataOutStageCallback(hpcd, 0U); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); + + if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) + { + PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } + } + } + } + else + { + /* Decode and service non control endpoints interrupt */ + /* process related endpoint register */ + wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, epindex); + + if ((wEPVal & USB_EP_VTRX) != 0U) + { + /* clear int flag */ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex); + ep = &hpcd->OUT_ep[epindex]; + + /* OUT Single Buffering */ + if (ep->doublebuffer == 0U) + { + count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + + if (count != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); + } + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + else + { + /* manage double buffer bulk out */ + if (ep->type == EP_TYPE_BULK) + { + count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal); + } + else /* manage double buffer iso out */ + { + /* free EP OUT Buffer */ + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); + + if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U) + { + /* read from endpoint BUF0Addr buffer */ + count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + + if (count != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); + } + } + else + { + /* read from endpoint BUF1Addr buffer */ + count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + + if (count != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); + } + } + } + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + /* multi-packet on the NON control OUT endpoint */ + ep->xfer_count += count; + ep->xfer_buff += count; + + if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) + { + /* RX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, ep->num); +#else + HAL_PCD_DataOutStageCallback(hpcd, ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + (void)USB_EPStartXfer(hpcd->Instance, ep); + } + } + + if ((wEPVal & USB_EP_VTTX) != 0U) + { + ep = &hpcd->IN_ep[epindex]; + + /* clear int flag */ + PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); + + if (ep->type == EP_TYPE_ISOC) + { + ep->xfer_len = 0U; + +#if (USE_USB_DOUBLE_BUFFER == 1U) + if (ep->doublebuffer != 0U) + { + if ((wEPVal & USB_EP_DTOG_TX) != 0U) + { + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + } + else + { + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + } + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + /* TX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, ep->num); +#else + HAL_PCD_DataInStageCallback(hpcd, ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + /* Manage Single Buffer Transaction */ + if ((wEPVal & USB_EP_KIND) == 0U) + { + /* multi-packet on the NON control IN endpoint */ + TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_len > TxPctSize) + { + ep->xfer_len -= TxPctSize; + } + else + { + ep->xfer_len = 0U; + } + + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + { + /* TX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, ep->num); +#else + HAL_PCD_DataInStageCallback(hpcd, ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + /* Transfer is not yet Done */ + ep->xfer_buff += TxPctSize; + ep->xfer_count += TxPctSize; + (void)USB_EPStartXfer(hpcd->Instance, ep); + } + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + /* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */ + else + { + (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal); + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + } + } + } + } + + return HAL_OK; +} + + +#if (USE_USB_DOUBLE_BUFFER == 1U) +/** + * @brief Manage double buffer bulk out transaction from ISR + * @param hpcd PCD handle + * @param ep current endpoint handle + * @param wEPVal Last snapshot of EPRx register value taken in ISR + * @retval HAL status + */ +static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, + PCD_EPTypeDef *ep, uint16_t wEPVal) +{ + uint16_t count; + + /* Manage Buffer0 OUT */ + if ((wEPVal & USB_EP_DTOG_RX) != 0U) + { + /* Get count of received Data on buffer0 */ + count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_len >= count) + { + ep->xfer_len -= count; + } + else + { + ep->xfer_len = 0U; + } + + if (ep->xfer_len == 0U) + { + /* set NAK to OUT endpoint since double buffer is enabled */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); + } + + /* Check if Buffer1 is in blocked state which requires to toggle */ + if ((wEPVal & USB_EP_DTOG_TX) != 0U) + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); + } + + if (count != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); + } + } + /* Manage Buffer 1 DTOG_RX=0 */ + else + { + /* Get count of received data */ + count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_len >= count) + { + ep->xfer_len -= count; + } + else + { + ep->xfer_len = 0U; + } + + if (ep->xfer_len == 0U) + { + /* set NAK on the current endpoint */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); + } + + /*Need to FreeUser Buffer*/ + if ((wEPVal & USB_EP_DTOG_TX) == 0U) + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); + } + + if (count != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); + } + } + + return count; +} + + +/** + * @brief Manage double buffer bulk IN transaction from ISR + * @param hpcd PCD handle + * @param ep current endpoint handle + * @param wEPVal Last snapshot of EPRx register value taken in ISR + * @retval HAL status + */ +static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, + PCD_EPTypeDef *ep, uint16_t wEPVal) +{ + uint32_t len; + uint16_t TxPctSize; + + /* Data Buffer0 ACK received */ + if ((wEPVal & USB_EP_DTOG_TX) != 0U) + { + /* multi-packet on the NON control IN endpoint */ + TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_len > TxPctSize) + { + ep->xfer_len -= TxPctSize; + } + else + { + ep->xfer_len = 0U; + } + + /* Transfer is completed */ + if (ep->xfer_len == 0U) + { + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + + /* TX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, ep->num); +#else + HAL_PCD_DataInStageCallback(hpcd, ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + if ((wEPVal & USB_EP_DTOG_RX) != 0U) + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); + } + } + else /* Transfer is not yet Done */ + { + /* need to Free USB Buff */ + if ((wEPVal & USB_EP_DTOG_RX) != 0U) + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); + } + + /* Still there is data to Fill in the next Buffer */ + if (ep->xfer_fill_db == 1U) + { + ep->xfer_buff += TxPctSize; + ep->xfer_count += TxPctSize; + + /* Calculate the len of the new buffer to fill */ + if (ep->xfer_len_db >= ep->maxpacket) + { + len = ep->maxpacket; + ep->xfer_len_db -= len; + } + else if (ep->xfer_len_db == 0U) + { + len = TxPctSize; + ep->xfer_fill_db = 0U; + } + else + { + ep->xfer_fill_db = 0U; + len = ep->xfer_len_db; + ep->xfer_len_db = 0U; + } + + /* Write remaining Data to Buffer */ + /* Set the Double buffer counter for pma buffer1 */ + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); + + /* Copy user buffer to USB PMA */ + USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, (uint16_t)len); + } + } + } + else /* Data Buffer1 ACK received */ + { + /* multi-packet on the NON control IN endpoint */ + TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_len >= TxPctSize) + { + ep->xfer_len -= TxPctSize; + } + else + { + ep->xfer_len = 0U; + } + + /* Transfer is completed */ + if (ep->xfer_len == 0U) + { + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + + /* TX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, ep->num); +#else + HAL_PCD_DataInStageCallback(hpcd, ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + /* need to Free USB Buff */ + if ((wEPVal & USB_EP_DTOG_RX) == 0U) + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); + } + } + else /* Transfer is not yet Done */ + { + /* need to Free USB Buff */ + if ((wEPVal & USB_EP_DTOG_RX) == 0U) + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); + } + + /* Still there is data to Fill in the next Buffer */ + if (ep->xfer_fill_db == 1U) + { + ep->xfer_buff += TxPctSize; + ep->xfer_count += TxPctSize; + + /* Calculate the len of the new buffer to fill */ + if (ep->xfer_len_db >= ep->maxpacket) + { + len = ep->maxpacket; + ep->xfer_len_db -= len; + } + else if (ep->xfer_len_db == 0U) + { + len = TxPctSize; + ep->xfer_fill_db = 0U; + } + else + { + len = ep->xfer_len_db; + ep->xfer_len_db = 0U; + ep->xfer_fill_db = 0; + } + + /* Set the Double buffer counter for pmabuffer1 */ + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); + + /* Copy the user buffer to USB PMA */ + USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, (uint16_t)len); + } + } + } + + /*enable endpoint IN*/ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); + + return HAL_OK; +} +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + +#endif /* defined (USB_DRD_FS) */ /** * @} */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #endif /* HAL_PCD_MODULE_ENABLED */ /** diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pcd.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pcd.h index 9ff6bb81f4c..f1b9fadb988 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pcd.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pcd.h @@ -27,7 +27,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32u5xx_ll_usb.h" -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) /** @addtogroup STM32U5xx_HAL_Driver * @{ @@ -85,6 +85,11 @@ typedef USB_OTG_GlobalTypeDef PCD_TypeDef; typedef USB_OTG_CfgTypeDef PCD_InitTypeDef; typedef USB_OTG_EPTypeDef PCD_EPTypeDef; #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) +typedef USB_DRD_TypeDef PCD_TypeDef; +typedef USB_DRD_CfgTypeDef PCD_InitTypeDef; +typedef USB_DRD_EPTypeDef PCD_EPTypeDef; +#endif /* defined (USB_DRD_FS) */ /** * @brief PCD Handle Structure definition @@ -98,14 +103,21 @@ typedef struct PCD_TypeDef *Instance; /*!< Register base address */ PCD_InitTypeDef Init; /*!< PCD required parameters */ __IO uint8_t USB_Address; /*!< USB Address */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) + PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ +#endif /* defined (USB_DRD_FS) */ HAL_LockTypeDef Lock; /*!< PCD peripheral status */ __IO PCD_StateTypeDef State; /*!< PCD communication state */ __IO uint32_t ErrorCode; /*!< PCD Error code */ uint32_t Setup[12]; /*!< Setup packet buffer */ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ uint32_t BESL; + uint32_t FrameNumber; /*!< Store Current Frame number */ uint32_t lpm_active; /*!< Enable or disable the Link Power Management . @@ -189,14 +201,14 @@ typedef struct * @brief macros to handle interrupts and specific clock configurations * @{ */ -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) #define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \ ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \ @@ -209,6 +221,10 @@ typedef struct ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\ + &= (uint16_t)(~(__INTERRUPT__))) +#endif /* defined (USB_DRD_FS) */ /** * @} @@ -268,12 +284,10 @@ typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgType * @} */ -HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, - HAL_PCD_CallbackIDTypeDef CallbackID, +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, - HAL_PCD_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback); @@ -295,14 +309,10 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, - pPCD_BcdCallbackTypeDef pCallback); - +HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, - pPCD_LpmCallbackTypeDef pCallback); - +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ /** @@ -341,22 +351,19 @@ void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, - uint16_t ep_mps, uint8_t ep_type); - +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, - uint8_t *pBuf, uint32_t len); - -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, - uint8_t *pBuf, uint32_t len); - - +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); /** @@ -380,6 +387,42 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** @defgroup PCD_Private_Constants PCD Private Constants * @{ */ +#if defined (USB_DRD_FS) +/** @defgroup PCD_EP0_MPS PCD EP0 MPS + * @{ + */ +#define PCD_EP0MPS_64 EP_MPS_64 +#define PCD_EP0MPS_32 EP_MPS_32 +#define PCD_EP0MPS_16 EP_MPS_16 +#define PCD_EP0MPS_08 EP_MPS_8 +/** + * @} + */ + +/** @defgroup PCD_ENDP PCD ENDP + * @{ + */ +#define PCD_ENDP0 0U +#define PCD_ENDP1 1U +#define PCD_ENDP2 2U +#define PCD_ENDP3 3U +#define PCD_ENDP4 4U +#define PCD_ENDP5 5U +#define PCD_ENDP6 6U +#define PCD_ENDP7 7U +/** + * @} + */ + +/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind + * @{ + */ +#define PCD_SNG_BUF 0U +#define PCD_DBL_BUF 1U +/** + * @} + */ +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -414,6 +457,203 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** @defgroup PCD_Private_Macros PCD Private Macros * @{ */ +#if defined (USB_DRD_FS) +/* PMA RX counter */ +#ifndef PCD_RX_PMA_CNT +#define PCD_RX_PMA_CNT 10U +#endif /* PCD_RX_PMA_CNT */ + +/* SetENDPOINT */ +#define PCD_SET_ENDPOINT USB_DRD_SET_CHEP + +/* GetENDPOINT Register value*/ +#define PCD_GET_ENDPOINT USB_DRD_GET_CHEP + + +/** + * @brief free buffer used from the application realizing it to the line + * toggles bit SW_BUF in the double buffered endpoint register + * @param USBx USB device. + * @param bEpNum, bDir + * @retval None + */ +#define PCD_FREE_USER_BUFFER USB_DRD_FREE_USER_BUFFER + +/** + * @brief sets the status for tx transfer (bits STAT_TX[1:0]). + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define PCD_SET_EP_TX_STATUS USB_DRD_SET_CHEP_TX_STATUS + +/** + * @brief sets the status for rx transfer (bits STAT_TX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define PCD_SET_EP_RX_STATUS USB_DRD_SET_CHEP_RX_STATUS + +/** + * @brief Sets/clears directly EP_KIND bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_KIND USB_DRD_SET_CHEP_KIND +#define PCD_CLEAR_EP_KIND USB_DRD_CLEAR_CHEP_KIND +#define PCD_SET_BULK_EP_DBUF PCD_SET_EP_KIND +#define PCD_CLEAR_BULK_EP_DBUF PCD_CLEAR_EP_KIND + + +/** + * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_CLEAR_RX_EP_CTR USB_DRD_CLEAR_RX_CHEP_CTR +#define PCD_CLEAR_TX_EP_CTR USB_DRD_CLEAR_TX_CHEP_CTR +/** + * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_RX_DTOG USB_DRD_RX_DTOG +#define PCD_TX_DTOG USB_DRD_TX_DTOG +/** + * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_CLEAR_RX_DTOG USB_DRD_CLEAR_RX_DTOG +#define PCD_CLEAR_TX_DTOG USB_DRD_CLEAR_TX_DTOG + +/** + * @brief Sets address in an endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bAddr Address. + * @retval None + */ +#define PCD_SET_EP_ADDRESS USB_DRD_SET_CHEP_ADDRESS + +/** + * @brief sets address of the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wAddr address to be set (must be word aligned). + * @retval None + */ +#define PCD_SET_EP_TX_ADDRESS USB_DRD_SET_CHEP_TX_ADDRESS +#define PCD_SET_EP_RX_ADDRESS USB_DRD_SET_CHEP_RX_ADDRESS + +/** + * @brief sets counter for the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wCount Counter value. + * @retval None + */ +#define PCD_SET_EP_TX_CNT USB_DRD_SET_CHEP_TX_CNT +#define PCD_SET_EP_RX_CNT USB_DRD_SET_CHEP_RX_CNT + +/** + * @brief gets counter of the tx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval Counter value + */ +#define PCD_GET_EP_TX_CNT USB_DRD_GET_CHEP_TX_CNT + +/** + * @brief gets counter of the rx buffer. + * @param Instance USB peripheral instance register address. + * @param bEpNum channel Number. + * @retval Counter value + */ +__STATIC_INLINE uint16_t PCD_GET_EP_RX_CNT(const PCD_TypeDef *Instance, uint16_t bEpNum) +{ + UNUSED(Instance); + __IO uint32_t count = PCD_RX_PMA_CNT; + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_RX_CNT((Instance), (bEpNum)); +} + +/** + * @brief Sets addresses in a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wBuf0Addr: buffer 0 address. + * @param wBuf1Addr = buffer 1 address. + * @retval None + */ +#define PCD_SET_EP_DBUF_ADDR USB_DRD_SET_CHEP_DBUF_ADDR + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bDir endpoint dir EP_DBUF_OUT = OUT + * EP_DBUF_IN = IN + * @param wCount: Counter value + * @retval None + */ +#define PCD_SET_EP_DBUF0_CNT USB_DRD_SET_CHEP_DBUF0_CNT +#define PCD_SET_EP_DBUF1_CNT USB_DRD_SET_CHEP_DBUF1_CNT +#define PCD_SET_EP_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT + +/** + * @brief gets counter of the rx buffer0. + * @param Instance USB peripheral instance register address. + * @param bEpNum channel Number. + * @retval Counter value + */ +__STATIC_INLINE uint16_t PCD_GET_EP_DBUF0_CNT(const PCD_TypeDef *Instance, uint16_t bEpNum) +{ + UNUSED(Instance); + __IO uint32_t count = PCD_RX_PMA_CNT; + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_DBUF0_CNT((Instance), (bEpNum)); +} + +/** + * @brief gets counter of the rx buffer1. + * @param Instance USB peripheral instance register address. + * @param bEpNum channel Number. + * @retval Counter value + */ +__STATIC_INLINE uint16_t PCD_GET_EP_DBUF1_CNT(const PCD_TypeDef *Instance, uint16_t bEpNum) +{ + UNUSED(Instance); + __IO uint32_t count = PCD_RX_PMA_CNT; + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bEpNum)); +} +#endif /* defined (USB_DRD_FS) */ /** * @} @@ -426,7 +666,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @} */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pcd_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pcd_ex.c index 445074d277f..aabc78133df 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pcd_ex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pcd_ex.c @@ -34,7 +34,7 @@ #ifdef HAL_PCD_MODULE_ENABLED -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ @@ -149,7 +149,7 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) return HAL_OK; } -#if defined (STM32U575xx) || defined (STM32U585xx) || defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) + /** * @brief Handle BatteryCharging Process. * @param hpcd PCD handle @@ -158,36 +158,16 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) { USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; -#if defined (STM32U575xx) || defined (STM32U585xx) uint32_t tickstart = HAL_GetTick(); -#endif /* defined (STM32U575xx) || defined (STM32U585xx) */ /* Enable DCD : Data Contact Detect */ USBx->GCCFG |= USB_OTG_GCCFG_DCDEN; -#if defined (STM32U575xx) || defined (STM32U585xx) - /* Wait Detect flag or a timeout is happen*/ - while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > 1000U) - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); -#else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - return; - } - } -#endif /* defined (STM32U575xx) || defined (STM32U585xx) */ - - /* Right response got */ - HAL_Delay(200U); + /* Wait for Min DCD Timeout */ + HAL_Delay(300U); #if defined (STM32U575xx) || defined (STM32U585xx) - /* Check Detect flag*/ + /* Check Detect flag */ if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET) { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) @@ -198,11 +178,11 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) } #endif /* defined (STM32U575xx) || defined (STM32U585xx) */ - /*Primary detection: checks if connected to Standard Downstream Port + /* Primary detection: checks if connected to Standard Downstream Port (without charging capability) */ USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN; HAL_Delay(50U); - USBx->GCCFG |= USB_OTG_GCCFG_PDEN; + USBx->GCCFG |= USB_OTG_GCCFG_PDEN; HAL_Delay(50U); #if defined (STM32U575xx) || defined (STM32U585xx) @@ -222,9 +202,9 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) { /* start secondary detection to check connection to Charging Downstream Port or Dedicated Charging Port */ - USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN; + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); HAL_Delay(50U); - USBx->GCCFG |= USB_OTG_GCCFG_SDEN; + USBx->GCCFG |= USB_OTG_GCCFG_SDEN; HAL_Delay(50U); #if defined (STM32U575xx) || defined (STM32U585xx) @@ -242,7 +222,7 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) } else { - /* case Charging Downstream Port */ + /* case Charging Downstream Port */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); #else @@ -254,11 +234,23 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) /* Battery Charging capability discovery finished */ (void)HAL_PCDEx_DeActivateBCD(hpcd); + /* Check for the Timeout, else start USB Device */ + if ((HAL_GetTick() - tickstart) > 1000U) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); + hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); #else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } } /** @@ -307,8 +299,228 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) return HAL_OK; } -#endif /* defined (STM32U575xx) || defined (STM32U585xx) || defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) */ + #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) +/** + * @brief Configure PMA for EP + * @param hpcd Device instance + * @param ep_addr endpoint address + * @param ep_kind endpoint Kind + * USB_SNG_BUF: Single Buffer used + * USB_DBL_BUF: Double Buffer used + * @param pmaadress: EP address in The PMA: In case of single buffer endpoint + * this parameter is 16-bit value providing the address + * in PMA allocated to endpoint. + * In case of double buffer endpoint this parameter + * is a 32-bit value providing the endpoint buffer 0 address + * in the LSB part of 32-bit value and endpoint buffer 1 address + * in the MSB part of 32-bit value. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, + uint16_t ep_kind, uint32_t pmaadress) +{ + PCD_EPTypeDef *ep; + + /* initialize ep structure*/ + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + } + + /* Here we check if the endpoint is single or double Buffer*/ + if (ep_kind == PCD_SNG_BUF) + { + /* Single Buffer */ + ep->doublebuffer = 0U; + /* Configure the PMA */ + ep->pmaadress = (uint16_t)pmaadress; + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + else /* USB_DBL_BUF */ + { + /* Double Buffer Endpoint */ + ep->doublebuffer = 1U; + /* Configure the PMA */ + ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU); + ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16); + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + return HAL_OK; +} + +/** + * @brief Activate BatteryCharging feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) +{ + USB_DRD_TypeDef *USBx = hpcd->Instance; + hpcd->battery_charging_active = 1U; + + /* Enable BCD feature */ + USBx->BCDR |= USB_BCDR_BCDEN; + + /* Enable DCD : Data Contact Detect */ + USBx->BCDR &= ~(USB_BCDR_PDEN); + USBx->BCDR &= ~(USB_BCDR_SDEN); + USBx->BCDR |= USB_BCDR_DCDEN; + + return HAL_OK; +} + +/** + * @brief Deactivate BatteryCharging feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) +{ + USB_DRD_TypeDef *USBx = hpcd->Instance; + hpcd->battery_charging_active = 0U; + + /* Disable BCD feature */ + USBx->BCDR &= ~(USB_BCDR_BCDEN); + + return HAL_OK; +} + +/** + * @brief Handle BatteryCharging Process. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) +{ + USB_DRD_TypeDef *USBx = hpcd->Instance; + uint32_t tickstart = HAL_GetTick(); + + /* Wait for Min DCD Timeout */ + HAL_Delay(300U); + + /* Data Pin Contact ? Check Detect flag */ + if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + /* Primary detection: checks if connected to Standard Downstream Port + (without charging capability) */ + USBx->BCDR &= ~(USB_BCDR_DCDEN); + HAL_Delay(50U); + USBx->BCDR |= (USB_BCDR_PDEN); + HAL_Delay(50U); + + /* If Charger detect ? */ + if ((USBx->BCDR & USB_BCDR_PDET) == USB_BCDR_PDET) + { + /* Start secondary detection to check connection to Charging Downstream + Port or Dedicated Charging Port */ + USBx->BCDR &= ~(USB_BCDR_PDEN); + HAL_Delay(50U); + USBx->BCDR |= (USB_BCDR_SDEN); + HAL_Delay(50U); + + /* If CDP ? */ + if ((USBx->BCDR & USB_BCDR_SDET) == USB_BCDR_SDET) + { + /* Dedicated Downstream Port DCP */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + /* Charging Downstream Port CDP */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + else /* NO */ + { + /* Standard Downstream Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + /* Battery Charging capability discovery finished Start Enumeration */ + (void)HAL_PCDEx_DeActivateBCD(hpcd); + + /* Check for the Timeout, else start USB Device */ + if ((HAL_GetTick() - tickstart) > 1000U) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } +} + + +/** + * @brief Activate LPM feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) +{ + + USB_DRD_TypeDef *USBx = hpcd->Instance; + hpcd->lpm_active = 1U; + hpcd->LPM_State = LPM_L0; + + USBx->LPMCSR |= USB_LPMCSR_LMPEN; + USBx->LPMCSR |= USB_LPMCSR_LPMACK; + + return HAL_OK; +} + +/** + * @brief Deactivate LPM feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) +{ + USB_DRD_TypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 0U; + + USBx->LPMCSR &= ~(USB_LPMCSR_LMPEN); + USBx->LPMCSR &= ~(USB_LPMCSR_LPMACK); + + return HAL_OK; +} + +#endif /* defined (USB_DRD_FS) */ /** * @brief Send LPM message to user layer callback. @@ -351,7 +563,7 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m /** * @} */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #endif /* HAL_PCD_MODULE_ENABLED */ /** diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pcd_ex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pcd_ex.h index d47dfaad3e8..ab2bb878e09 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pcd_ex.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pcd_ex.h @@ -22,12 +22,12 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /* __cplusplus */ /* Includes ------------------------------------------------------------------*/ #include "stm32u5xx_hal_def.h" -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) /** @addtogroup STM32U5xx_HAL_Driver * @{ */ @@ -51,15 +51,19 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, + uint16_t ep_kind, uint32_t pmaadress); +#endif /* defined (USB_DRD_FS) */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd); -#if defined (STM32U575xx) || defined (STM32U585xx) || defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) + HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd); void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd); -#endif /* defined (STM32U575xx) || defined (STM32U585xx) || defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) */ + void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); @@ -78,11 +82,11 @@ void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /** * @} */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #ifdef __cplusplus } -#endif +#endif /* __cplusplus */ #endif /* STM32U5xx_HAL_PCD_EX_H */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pka.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pka.c index 48bdaf6a1d4..019fd160779 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pka.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pka.c @@ -199,11 +199,11 @@ The compilation flag USE_HAL_PKA_REGISTER_CALLBACKS, when set to 1, allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_PKA_RegisterCallback() + Use Functions HAL_PKA_RegisterCallback() to register an interrupt callback. [..] - Function @ref HAL_PKA_RegisterCallback() allows to register following callbacks: + Function HAL_PKA_RegisterCallback() allows to register following callbacks: (+) OperationCpltCallback : callback for End of operation. (+) ErrorCallback : callback for error detection. (+) MspInitCallback : callback for Msp Init. @@ -212,11 +212,11 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_PKA_UnRegisterCallback to reset a callback to the default + Use function HAL_PKA_UnRegisterCallback to reset a callback to the default weak function. [..] - @ref HAL_PKA_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_PKA_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) OperationCpltCallback : callback for End of operation. @@ -225,27 +225,27 @@ (+) MspDeInitCallback : callback for Msp DeInit. [..] - By default, after the @ref HAL_PKA_Init() and when the state is @ref HAL_PKA_STATE_RESET + By default, after the HAL_PKA_Init() and when the state is HAL_PKA_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_PKA_OperationCpltCallback(), @ref HAL_PKA_ErrorCallback(). + examples HAL_PKA_OperationCpltCallback(), HAL_PKA_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_PKA_Init()/ @ref HAL_PKA_DeInit() only when + reset to the legacy weak functions in the HAL_PKA_Init()/ HAL_PKA_DeInit() only when these callbacks are null (not registered beforehand). [..] - If MspInit or MspDeInit are not null, the @ref HAL_PKA_Init()/ @ref HAL_PKA_DeInit() + If MspInit or MspDeInit are not null, the HAL_PKA_Init()/ HAL_PKA_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_PKA_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_PKA_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_PKA_STATE_READY or @ref HAL_PKA_STATE_RESET state, + in HAL_PKA_STATE_READY or HAL_PKA_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. [..] Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_PKA_RegisterCallback() before calling @ref HAL_PKA_DeInit() - or @ref HAL_PKA_Init() function. + using HAL_PKA_RegisterCallback() before calling HAL_PKA_DeInit() + or HAL_PKA_Init() function. [..] When the compilation flag USE_HAL_PKA_REGISTER_CALLBACKS is set to 0 or @@ -287,13 +287,16 @@ */ /* Private variables ---------------------------------------------------------*/ +static uint32_t primeordersize; +static uint32_t opsize; +static uint32_t modulussize; /* Private function prototypes -----------------------------------------------*/ /** @defgroup PKA_Private_Functions PKA Private Functions * @{ */ -uint32_t PKA_GetMode(PKA_HandleTypeDef *hpka); -HAL_StatusTypeDef PKA_PollEndOfOperation(PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart); -uint32_t PKA_CheckError(PKA_HandleTypeDef *hpka, uint32_t mode); +uint32_t PKA_GetMode(const PKA_HandleTypeDef *hpka); +HAL_StatusTypeDef PKA_PollEndOfOperation(const PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart); +uint32_t PKA_CheckError(const PKA_HandleTypeDef *hpka, uint32_t mode); uint32_t PKA_GetBitSize_u8(uint32_t byteNumber); uint32_t PKA_GetOptBitSize_u8(uint32_t byteNumber, uint8_t msb); uint32_t PKA_GetBitSize_u32(uint32_t wordNumber); @@ -321,7 +324,7 @@ void PKA_ECCProjective2Affine_Set(PKA_HandleTypeDef *hpka, PKA_ECCProjective2Aff void PKA_ECCCompleteAddition_Set(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in); HAL_StatusTypeDef PKA_WaitOnFlagUntilTimeout(PKA_HandleTypeDef *hpka, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); -uint32_t PKA_Result_GetSize(PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32_t Maxsize); +uint32_t PKA_Result_GetSize(const PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32_t Maxsize); /** * @} */ @@ -806,6 +809,8 @@ HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *i /* Set input parameter in PKA RAM */ PKA_ModExp_Set(hpka, in); + opsize = in->OpSize; + /* Start the operation */ return PKA_Process(hpka, PKA_MODE_MODULAR_EXP, Timeout); } @@ -821,6 +826,8 @@ HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef /* Set input parameter in PKA RAM */ PKA_ModExp_Set(hpka, in); + opsize = in->OpSize; + /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP); } @@ -837,6 +844,8 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFast /* Set input parameter in PKA RAM */ PKA_ModExpFastMode_Set(hpka, in); + opsize = in->OpSize; + /* Start the operation */ return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE, Timeout); } @@ -852,6 +861,8 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpF /* Set input parameter in PKA RAM */ PKA_ModExpFastMode_Set(hpka, in); + opsize = in->OpSize; + /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE); } @@ -870,6 +881,8 @@ HAL_StatusTypeDef HAL_PKA_ModExpProtectMode(PKA_HandleTypeDef *hpka, PKA_ModExpP /* Set input parameter in PKA RAM */ PKA_ModExpProtectMode_Set(hpka, in); + opsize = in->OpSize; + return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_PROTECT, Timeout); } @@ -885,6 +898,8 @@ HAL_StatusTypeDef HAL_PKA_ModExpProtectMode_IT(PKA_HandleTypeDef *hpka, PKA_ModE /* Set input parameter in PKA RAM */ PKA_ModExpProtectMode_Set(hpka, in); + opsize = in->OpSize; + return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_PROTECT); } @@ -899,7 +914,7 @@ void HAL_PKA_ModExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes) uint32_t size; /* Get output result size */ - size = PKA_Result_GetSize(hpka, PKA_MODULAR_EXP_OUT_RESULT, 130UL); + size = opsize; /* Move the result to appropriate location (indicated in out parameter) */ PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_RESULT], size); @@ -917,6 +932,8 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInType /* Set input parameter in PKA RAM */ PKA_ECDSASign_Set(hpka, in); + primeordersize = in->primeOrderSize; + /* Start the operation */ return PKA_Process(hpka, PKA_MODE_ECDSA_SIGNATURE, Timeout); } @@ -932,6 +949,8 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInT /* Set input parameter in PKA RAM */ PKA_ECDSASign_Set(hpka, in); + primeordersize = in->primeOrderSize; + /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_ECDSA_SIGNATURE); } @@ -948,7 +967,8 @@ void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDe uint32_t size; /* Get output result size */ - size = PKA_Result_GetSize(hpka, PKA_ECDSA_SIGN_OUT_SIGNATURE_R, 20UL); + size = primeordersize; + if (out != NULL) { @@ -1109,6 +1129,8 @@ HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *i /* Set input parameter in PKA RAM */ PKA_ECCMul_Set(hpka, in); + modulussize = in->modulusSize; + /* Start the operation */ return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout); } @@ -1124,6 +1146,8 @@ HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef /* Set input parameter in PKA RAM */ PKA_ECCMul_Set(hpka, in); + modulussize = in->modulusSize; + /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL); } @@ -1138,7 +1162,7 @@ void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out uint32_t size; /* Get output result size */ - size = PKA_Result_GetSize(hpka, PKA_ECC_SCALAR_MUL_OUT_RESULT_X, 20UL); + size = modulussize; /* If a destination buffer is provided */ if (out != NULL) @@ -1837,7 +1861,7 @@ __weak void HAL_PKA_ErrorCallback(PKA_HandleTypeDef *hpka) * @param hpka PKA handle * @retval HAL status */ -HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka) +HAL_PKA_StateTypeDef HAL_PKA_GetState(const PKA_HandleTypeDef *hpka) { /* Return PKA handle state */ return hpka->State; @@ -1848,7 +1872,7 @@ HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka) * @param hpka PKA handle * @retval PKA error code */ -uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka) +uint32_t HAL_PKA_GetError(const PKA_HandleTypeDef *hpka) { /* Return PKA handle error code */ return hpka->ErrorCode; @@ -1871,7 +1895,7 @@ uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka) * @param hpka PKA handle * @retval Return the current mode */ -uint32_t PKA_GetMode(PKA_HandleTypeDef *hpka) +uint32_t PKA_GetMode(const PKA_HandleTypeDef *hpka) { /* return the shifted PKA_CR_MODE value */ return (uint32_t)(READ_BIT(hpka->Instance->CR, PKA_CR_MODE) >> PKA_CR_MODE_Pos); @@ -1884,7 +1908,7 @@ uint32_t PKA_GetMode(PKA_HandleTypeDef *hpka) * @param Tickstart Tick start value * @retval HAL status */ -HAL_StatusTypeDef PKA_PollEndOfOperation(PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart) +HAL_StatusTypeDef PKA_PollEndOfOperation(const PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart) { /* Wait for the end of operation or timeout */ while ((hpka->Instance->SR & PKA_SR_PROCENDF) == 0UL) @@ -1907,7 +1931,7 @@ HAL_StatusTypeDef PKA_PollEndOfOperation(PKA_HandleTypeDef *hpka, uint32_t Timeo * @param mode PKA operating mode * @retval error code */ -uint32_t PKA_CheckError(PKA_HandleTypeDef *hpka, uint32_t mode) +uint32_t PKA_CheckError(const PKA_HandleTypeDef *hpka, uint32_t mode) { uint32_t err = HAL_PKA_ERROR_NONE; @@ -2263,15 +2287,15 @@ void PKA_ModExp_Set(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in) /* Move the input parameters pOp1 to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE], in->pOp1, in->OpSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + (in->OpSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + ((in->OpSize + 3UL) / 4UL)); /* Move the exponent to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT], in->pExp, in->expSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + (in->expSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + ((in->expSize + 3UL) / 4UL)); /* Move the modulus to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS], in->pMod, in->OpSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + (in->OpSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + ((in->OpSize + 3UL) / 4UL)); } /** @@ -2339,6 +2363,8 @@ void PKA_ModExpProtectMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInT * @brief Set input parameters. * @param hpka PKA handle * @param in Input information + * @note If the modulus size is bigger than the hash size (with a curve SECP521R1 when using a SHA256 hash + * for example)the hash value should be written at the end of the buffer with zeros padding at beginning. */ void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in) { @@ -2543,7 +2569,7 @@ void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in) /* Move the input parameters coefficient b to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_B_COEFF], in->coefB, in->modulusSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_B_COEFF + (in->modulusSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL)); /* Move the input parameters modulus value p to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], in->modulus, in->modulusSize); @@ -2563,7 +2589,7 @@ void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in) /* Move the input parameters curve prime order N to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], in->primeOrder, in->modulusSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + (in->modulusSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + ((in->modulusSize + 3UL) / 4UL)); } @@ -2605,7 +2631,7 @@ void PKA_ModRed_Set(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in) /* Move the input parameters modulus value n to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_MODULUS], in->pMod, in->modSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_MODULUS + (in->modSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_MODULUS + ((in->modSize + 3UL) / 4UL)); } /** @@ -2906,7 +2932,7 @@ HAL_StatusTypeDef PKA_WaitOnFlagUntilTimeout(PKA_HandleTypeDef *hpka, uint32_t F * @param Maxsize Specifies the possible max size of the result in words * @retval size */ -uint32_t PKA_Result_GetSize(PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32_t Maxsize) +uint32_t PKA_Result_GetSize(const PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32_t Maxsize) { uint32_t size; uint32_t current_index = Maxsize - 1UL; @@ -2935,4 +2961,3 @@ uint32_t PKA_Result_GetSize(PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32 /** * @} */ - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pka.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pka.h index eb7af5a48f7..5a043062b7c 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pka.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pka.h @@ -626,8 +626,8 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka); * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka); -uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka); +HAL_PKA_StateTypeDef HAL_PKA_GetState(const PKA_HandleTypeDef *hpka); +uint32_t HAL_PKA_GetError(const PKA_HandleTypeDef *hpka); /** * @} */ @@ -651,4 +651,3 @@ uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka); #endif #endif /* STM32U5xx_HAL_PKA_H */ - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pssi.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pssi.c index 45282b8dfcf..d8cf07b84cf 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pssi.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pssi.c @@ -12,7 +12,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -179,11 +179,12 @@ * @{ */ /* Private functions to handle DMA transfer */ +#if defined(HAL_DMA_MODULE_ENABLED) void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma); void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); void PSSI_DMAError(DMA_HandleTypeDef *hdma); void PSSI_DMAAbort(DMA_HandleTypeDef *hdma); - +#endif /*HAL_DMA_MODULE_ENABLED*/ /* Private functions to handle IT transfer */ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode); @@ -264,6 +265,7 @@ HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi) /* Allocate lock resource and initialize it */ hpssi->Lock = HAL_UNLOCKED; +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) /* Init the PSSI Callback settings */ hpssi->TxCpltCallback = HAL_PSSI_TxCpltCallback; /* Legacy weak TxCpltCallback */ hpssi->RxCpltCallback = HAL_PSSI_RxCpltCallback; /* Legacy weak RxCpltCallback */ @@ -277,7 +279,10 @@ HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi) /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ hpssi->MspInitCallback(hpssi); - +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_PSSI_MspInit(hpssi); +#endif /*USE_HAL_PSSI_REGISTER_CALLBACKS*/ } hpssi->State = HAL_PSSI_STATE_BUSY; @@ -320,6 +325,7 @@ HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi) /* Disable the PSSI Peripheral Clock */ HAL_PSSI_DISABLE(hpssi); +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) if (hpssi->MspDeInitCallback == NULL) { hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit */ @@ -327,6 +333,10 @@ HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi) /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ hpssi->MspDeInitCallback(hpssi); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_PSSI_MspDeInit(hpssi); +#endif /*USE_HAL_PSSI_REGISTER_CALLBACKS*/ hpssi->ErrorCode = HAL_PSSI_ERROR_NONE; hpssi->State = HAL_PSSI_STATE_RESET; @@ -354,7 +364,7 @@ __weak void HAL_PSSI_MspInit(PSSI_HandleTypeDef *hpssi) } /** - * @brief DeInitialize the PSSI MSP. + * @brief De-Initialize the PSSI MSP. * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains * the configuration information for the specified PSSI. * @retval None @@ -364,14 +374,18 @@ __weak void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi) /* Prevent unused argument(s) compilation warning */ UNUSED(hpssi); - /* NOTE : This function should not be modified, when the callback is needed, + /* NOTE : This function should not be modified; when the callback is needed, the HAL_PSSI_MspDeInit can be implemented in the user file */ } +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) /** * @brief Register a User PSSI Callback * To be used instead of the weak predefined callback + * @note The HAL_PSSI_RegisterCallback() may be called before HAL_PSSI_Init() in + * HAL_PSSI_STATE_RESET to register callbacks for HAL_PSSI_MSPINIT_CB_ID + * and HAL_PSSI_MSPDEINIT_CB_ID. * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains * the configuration information for the specified PSSI. * @param CallbackID ID of the callback to be registered @@ -397,8 +411,6 @@ HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_ return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpssi); if (HAL_PSSI_STATE_READY == hpssi->State) { @@ -467,14 +479,15 @@ HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpssi); return status; } /** * @brief Unregister an PSSI Callback * PSSI callback is redirected to the weak predefined callback + * @note The HAL_PSSI_UnRegisterCallback() may be called before HAL_PSSI_Init() in + * HAL_PSSI_STATE_RESET to un-register callbacks for HAL_PSSI_MSPINIT_CB_ID + * and HAL_PSSI_MSPDEINIT_CB_ID. * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains * the configuration information for the specified PSSI. * @param CallbackID ID of the callback to be unregistered @@ -491,35 +504,32 @@ HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSS { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpssi); - if (HAL_PSSI_STATE_READY == hpssi->State) { switch (CallbackID) { case HAL_PSSI_TX_COMPLETE_CB_ID : - hpssi->TxCpltCallback = HAL_PSSI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hpssi->TxCpltCallback = HAL_PSSI_TxCpltCallback; /* Legacy weak TxCpltCallback */ break; case HAL_PSSI_RX_COMPLETE_CB_ID : - hpssi->RxCpltCallback = HAL_PSSI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hpssi->RxCpltCallback = HAL_PSSI_RxCpltCallback; /* Legacy weak RxCpltCallback */ break; case HAL_PSSI_ERROR_CB_ID : - hpssi->ErrorCallback = HAL_PSSI_ErrorCallback; /* Legacy weak ErrorCallback */ + hpssi->ErrorCallback = HAL_PSSI_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_PSSI_ABORT_CB_ID : - hpssi->AbortCpltCallback = HAL_PSSI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hpssi->AbortCpltCallback = HAL_PSSI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; case HAL_PSSI_MSPINIT_CB_ID : - hpssi->MspInitCallback = HAL_PSSI_MspInit; /* Legacy weak MspInit */ + hpssi->MspInitCallback = HAL_PSSI_MspInit; /* Legacy weak MspInit */ break; case HAL_PSSI_MSPDEINIT_CB_ID : - hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit */ + hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit */ break; default : @@ -536,11 +546,11 @@ HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSS switch (CallbackID) { case HAL_PSSI_MSPINIT_CB_ID : - hpssi->MspInitCallback = HAL_PSSI_MspInit; /* Legacy weak MspInit */ + hpssi->MspInitCallback = HAL_PSSI_MspInit; /* Legacy weak MspInit */ break; case HAL_PSSI_MSPDEINIT_CB_ID : - hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit */ + hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit */ break; default : @@ -561,11 +571,10 @@ HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSS status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpssi); return status; } +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ /** * @} @@ -644,8 +653,11 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u /* Configure transfer parameters */ hpssi->Instance->CR |= PSSI_CR_OUTEN_OUTPUT | ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL); + +#if defined(HAL_DMA_MODULE_ENABLED) /* DMA Disable */ hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE; +#endif /*HAL_DMA_MODULE_ENABLED*/ /* Enable the selected PSSI peripheral */ HAL_PSSI_ENABLE(hpssi); @@ -699,7 +711,6 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u /* Increment Buffer pointer */ pbuffer++; transfer_size -= 2U; - } } else if (hpssi->Init.DataWidth == HAL_PSSI_32BITS) @@ -725,7 +736,6 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u pbuffer++; transfer_size -= 4U; } - } else { @@ -761,7 +771,6 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u } } - /** * @brief Receives an amount of data in blocking mode. * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains @@ -798,8 +807,10 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui hpssi->Instance->CR |= PSSI_CR_OUTEN_INPUT | ((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE) ? 0U : PSSI_CR_CKPOL); +#if defined(HAL_DMA_MODULE_ENABLED) /* DMA Disable */ hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE; +#endif /*HAL_DMA_MODULE_ENABLED*/ /* Enable the selected PSSI peripheral */ HAL_PSSI_ENABLE(hpssi); @@ -849,7 +860,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui *pbuffer = *dr; pbuffer++; transfer_size -= 2U; - } } else if (hpssi->Init.DataWidth == HAL_PSSI_32BITS) @@ -874,7 +884,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui *pbuffer = *(__IO uint32_t *)(&hpssi->Instance->DR); pbuffer++; transfer_size -= 4U; - } } else @@ -895,7 +904,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui return HAL_ERROR; } - hpssi->State = HAL_PSSI_STATE_READY; /* Process Unlocked */ @@ -909,6 +917,7 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui } } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Transmit an amount of data in non-blocking mode with DMA * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains @@ -1019,8 +1028,6 @@ HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDa if (dmaxferstatus == HAL_OK) { - - /* Update XferCount value */ hpssi->XferCount -= hpssi->XferSize; @@ -1065,7 +1072,6 @@ HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDa HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS); } - return HAL_OK; } else @@ -1115,7 +1121,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDat { if (hpssi->hdmarx != NULL) { - /* Configure BusWidth */ if (hpssi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE) { @@ -1216,7 +1221,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDat } else { - /* Process Unlocked */ __HAL_UNLOCK(hpssi); @@ -1232,8 +1236,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDat } } - - /** * @brief Abort a DMA process communication with Interrupt. * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains @@ -1242,7 +1244,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDat */ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi) { - /* Process Locked */ __HAL_LOCK(hpssi); @@ -1257,7 +1258,6 @@ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi) { if (hpssi->State == HAL_PSSI_STATE_BUSY_TX) { - hpssi->Instance->CR &= ~PSSI_CR_DMAEN; if (hpssi->hdmatx != NULL) @@ -1273,12 +1273,10 @@ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi) hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx); } } - } /* Abort DMA RX transfer if any */ else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX) { - hpssi->Instance->CR &= ~PSSI_CR_DMAEN; if (hpssi->hdmarx != NULL) @@ -1297,12 +1295,16 @@ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi) } else { + /* Call the error callback */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) hpssi->ErrorCallback(hpssi); +#else + HAL_PSSI_ErrorCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ } } - /* Process Unlocked */ __HAL_UNLOCK(hpssi); @@ -1312,14 +1314,14 @@ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi) HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS); return HAL_OK; - } +#endif /*HAL_DMA_MODULE_ENABLED*/ /** * @} */ -/** @defgroup PSSI_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks +/** @addtogroup PSSI_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks * @{ */ @@ -1335,13 +1337,12 @@ void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi) if (HAL_PSSI_GET_FLAG(hpssi, PSSI_FLAG_OVR_MIS) != 0U) { /* Reset handle parameters */ - hpssi->XferCount = 0U; /* Disable all interrupts */ HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS); - +#if defined(HAL_DMA_MODULE_ENABLED) /* Abort DMA TX transfer if any */ if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN) { @@ -1368,7 +1369,6 @@ void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi) hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx); } } - } /* Abort DMA RX transfer if any */ else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX) @@ -1397,10 +1397,15 @@ void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi) } else { +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) /* Call the corresponding callback to inform upper layer of the error */ hpssi->ErrorCallback(hpssi); +#else + HAL_PSSI_ErrorCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ } } +#endif /*HAL_DMA_MODULE_ENABLED*/ /* If state is an abort treatment on going, don't change state */ if (hpssi->State == HAL_PSSI_STATE_ABORT) @@ -1410,9 +1415,12 @@ void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi) /* Process Unlocked */ __HAL_UNLOCK(hpssi); +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) /* Call the corresponding callback to inform upper layer of End of Transfer */ hpssi->AbortCpltCallback(hpssi); - +#else + HAL_PSSI_AbortCpltCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ } else { @@ -1421,15 +1429,16 @@ void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi) /* Process Unlocked */ __HAL_UNLOCK(hpssi); +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) /* Call the corresponding callback to inform upper layer of End of Transfer */ hpssi->ErrorCallback(hpssi); - +#else + HAL_PSSI_ErrorCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ } - } } - /** * @brief Tx Transfer complete callback. * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains @@ -1462,7 +1471,6 @@ __weak void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi) */ } - /** * @brief PSSI error callback. * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains @@ -1520,20 +1528,19 @@ __weak void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi) * the configuration information for the specified PSSI. * @retval HAL state */ -HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi) +HAL_PSSI_StateTypeDef HAL_PSSI_GetState(const PSSI_HandleTypeDef *hpssi) { /* Return PSSI handle state */ return hpssi->State; } - /** * @brief Return the PSSI error code. * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains * the configuration information for the specified PSSI. * @retval PSSI Error Code */ -uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi) +uint32_t HAL_PSSI_GetError(const PSSI_HandleTypeDef *hpssi) { return hpssi->ErrorCode; } @@ -1558,9 +1565,7 @@ uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi) */ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode) { - /* Reset handle parameters */ - hpssi->XferCount = 0U; /* Set new error code */ @@ -1569,7 +1574,7 @@ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode) /* Disable all interrupts */ HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS); - +#if defined(HAL_DMA_MODULE_ENABLED) /* Abort DMA TX transfer if any */ if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN) { @@ -1593,7 +1598,6 @@ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode) hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx); } } - } /* Abort DMA RX transfer if any */ else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX) @@ -1622,6 +1626,7 @@ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode) /*Nothing to do*/ } } +#endif /*HAL_DMA_MODULE_ENABLED*/ /* If state is an abort treatment on going, don't change state */ if (hpssi->State == HAL_PSSI_STATE_ABORT) @@ -1632,9 +1637,11 @@ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode) __HAL_UNLOCK(hpssi); /* Call the corresponding callback to inform upper layer of End of Transfer */ - +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) hpssi->AbortCpltCallback(hpssi); - +#else + HAL_PSSI_AbortCpltCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ } else { @@ -1645,11 +1652,15 @@ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode) __HAL_UNLOCK(hpssi); /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) hpssi->ErrorCallback(hpssi); - +#else + HAL_PSSI_ErrorCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ } } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief DMA PSSI slave transmit process complete callback. * @param hdma DMA handle @@ -1662,7 +1673,6 @@ void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma) uint32_t tmperror; - /* Disable Interrupts */ HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS); @@ -1684,12 +1694,12 @@ void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma) __HAL_UNLOCK(hpssi); /* Call the corresponding callback to inform upper layer of End of Transfer */ - +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) hpssi->TxCpltCallback(hpssi); - +#else + HAL_PSSI_TxCpltCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ } - - } /** @@ -1704,7 +1714,6 @@ void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) uint32_t tmperror; - /* Disable Interrupts */ HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS); @@ -1726,11 +1735,12 @@ void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) __HAL_UNLOCK(hpssi); /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) hpssi->RxCpltCallback(hpssi); - +#else + HAL_PSSI_RxCpltCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ } - - } /** @@ -1754,16 +1764,23 @@ void PSSI_DMAAbort(DMA_HandleTypeDef *hdma) hpssi->State = HAL_PSSI_STATE_READY; /* Call the corresponding callback to inform upper layer of End of Transfer */ - +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) hpssi->AbortCpltCallback(hpssi); - +#else + HAL_PSSI_AbortCpltCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ } else { /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) hpssi->ErrorCallback(hpssi); +#else + HAL_PSSI_ErrorCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ } } +#endif /*HAL_DMA_MODULE_ENABLED*/ /** * @brief This function handles PSSI Communication Timeout. @@ -1797,6 +1814,8 @@ static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi } return HAL_OK; } + +#if defined(HAL_DMA_MODULE_ENABLED) void PSSI_DMAError(DMA_HandleTypeDef *hdma) { /* Derogation MISRAC2012-Rule-11.5 */ @@ -1804,7 +1823,6 @@ void PSSI_DMAError(DMA_HandleTypeDef *hdma) uint32_t tmperror; - /* Disable the selected PSSI peripheral */ HAL_PSSI_DISABLE(hpssi); @@ -1828,12 +1846,14 @@ void PSSI_DMAError(DMA_HandleTypeDef *hdma) __HAL_UNLOCK(hpssi); /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) hpssi->ErrorCallback(hpssi); - +#else + HAL_PSSI_ErrorCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ } - } - +#endif /*HAL_DMA_MODULE_ENABLED*/ /** diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pssi.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pssi.h index 6790e5170a3..09611952da3 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pssi.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pssi.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -31,6 +31,12 @@ extern "C" { * @{ */ #if defined(PSSI) + +#ifndef USE_HAL_PSSI_REGISTER_CALLBACKS +/* For backward compatibility, if USE_HAL_PSSI_REGISTER_CALLBACKS not defined, define it to 1*/ +#define USE_HAL_PSSI_REGISTER_CALLBACKS 0U +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ + /** @addtogroup PSSI PSSI * @brief PSSI HAL module driver * @{ @@ -76,16 +82,23 @@ typedef enum /** * @brief PSSI handle Structure definition */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) typedef struct __PSSI_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ { PSSI_TypeDef *Instance; /*!< PSSI register base address. */ PSSI_InitTypeDef Init; /*!< PSSI Initialization Structure. */ uint32_t *pBuffPtr; /*!< PSSI Data buffer. */ uint32_t XferCount; /*!< PSSI transfer count */ uint32_t XferSize; /*!< PSSI transfer size */ +#if defined(HAL_DMA_MODULE_ENABLED) DMA_HandleTypeDef *hdmatx; /*!< PSSI Tx DMA Handle parameters */ DMA_HandleTypeDef *hdmarx; /*!< PSSI Rx DMA Handle parameters */ +#endif /*HAL_DMA_MODULE_ENABLED*/ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) void (* TxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback. */ void (* RxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback. */ void (* ErrorCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback. */ @@ -93,6 +106,7 @@ typedef struct __PSSI_HandleTypeDef void (* MspInitCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI Msp Init callback. */ void (* MspDeInitCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI Msp DeInit callback. */ +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ HAL_LockTypeDef Lock; /*!< PSSI lock. */ __IO HAL_PSSI_StateTypeDef State; /*!< PSSI transfer state. */ @@ -100,7 +114,7 @@ typedef struct __PSSI_HandleTypeDef } PSSI_HandleTypeDef; - +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) /** * @brief HAL PSSI Callback pointer definition */ @@ -120,7 +134,7 @@ typedef enum HAL_PSSI_MSPDEINIT_CB_ID = 0x06U /*!< PSSI Msp DeInit callback ID */ } HAL_PSSI_CallbackIDTypeDef; - +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ /** * @} @@ -140,8 +154,9 @@ typedef enum #define HAL_PSSI_ERROR_OVER_RUN 0x00000004U /*!< FIFO Over-run error */ #define HAL_PSSI_ERROR_DMA 0x00000008U /*!< Dma error */ #define HAL_PSSI_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) #define HAL_PSSI_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid callback error */ - +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ /** * @} @@ -238,7 +253,7 @@ typedef enum #define PSSI_CR_16BITS PSSI_CR_EDM /*!< 16 Lines Mode */ #define PSSI_CR_8BITS (~PSSI_CR_EDM) /*!< 8 Lines Mode */ -#define PSSI_FLAG_RTT1B PSSI_SR_RTT1B /*!< 1 Byte Fifo Flag*/ +#define PSSI_FLAG_RTT1B PSSI_SR_RTT1B /*!< 1 Byte Fifo Flag */ #define PSSI_FLAG_RTT4B PSSI_SR_RTT4B /*!< 4 Bytes Fifo Flag*/ @@ -272,12 +287,15 @@ typedef enum * @param __HANDLE__ specifies the PSSI handle. * @retval None */ - +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) #define HAL_PSSI_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->State = HAL_PSSI_STATE_RESET;\ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ }while(0) +#else +#define HAL_PSSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PSSI_STATE_RESET) +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ /** @@ -387,6 +405,7 @@ typedef enum ((__BUSWIDTH__) == HAL_PSSI_16LINES )) /** + * @brief Check whether the PSSI Clock Polarity is valid. * @param __CLOCKPOL__ PSSI Clock Polarity * @retval Valid or not. @@ -433,11 +452,11 @@ HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi); void HAL_PSSI_MspInit(PSSI_HandleTypeDef *hpssi); void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi); /* Callbacks Register/UnRegister functions ***********************************/ - +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID, pPSSI_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID); - +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ /** * @} @@ -451,9 +470,11 @@ HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSS /* IO operation functions *******************************************************/ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout); +#if defined(HAL_DMA_MODULE_ENABLED) HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size); HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size); HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi); +#endif /*HAL_DMA_MODULE_ENABLED*/ /** * @} @@ -464,8 +485,8 @@ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi); */ /* Peripheral State functions ***************************************************/ -HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi); -uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi); +HAL_PSSI_StateTypeDef HAL_PSSI_GetState(const PSSI_HandleTypeDef *hpssi); +uint32_t HAL_PSSI_GetError(const PSSI_HandleTypeDef *hpssi); /** * @} @@ -481,7 +502,6 @@ void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi); void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi); void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi); - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pwr.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pwr.c index 86129f2ea10..9e4fb38286f 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pwr.c @@ -869,6 +869,9 @@ void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes) } } #else + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); + /* NSecure item management (TZEN = 0) */ if ((Attributes & PWR_ITEM_ATTR_NSEC_PRIV_MASK) == PWR_ITEM_ATTR_NSEC_PRIV_MASK) { diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pwr.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pwr.h index ac4a1efc0b2..672cfc2335f 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pwr.h @@ -137,6 +137,9 @@ typedef struct #define PWR_FLAG_TEMPH (0x0CU) /*!< Temperature level flag (versus high threshold) */ #define PWR_FLAG_TEMPL (0x0DU) /*!< Temperature level flag (versus low threshold) */ #define PWR_FLAG_VBATH (0x0EU) /*!< Backup domain voltage level flag (versus high threshold) */ +#if defined (PWR_VOSR_USBBOOSTRDY) +#define PWR_FLAG_USBBOOSTRDY (0x0FU) /*!< USB EPOD booster ready flag */ +#endif /* defined (PWR_VOSR_USBBOOSTRDY) */ /** * @} */ @@ -306,6 +309,11 @@ typedef struct * @arg @ref PWR_FLAG_BOOSTRDY : EPOD booster ready flag. * Indicates that EPOD booster ready, * frequency could be higher than 50 MHz. + * @arg @ref PWR_FLAG_USBBOOSTRDY : USB EPOD booster ready flag. + * Indicates that USB EPOD booster ready, + * frequency could be higher than 50 MHz. + * This flag is available only for STM32U59xxx and STM32U5Axxx + * devices. * @arg @ref PWR_FLAG_STOPF : Stop flag. * Indicates that the device was resumed from Stop mode. * @arg @ref PWR_FLAG_SBF : Standby flag. @@ -355,8 +363,35 @@ typedef struct * Indicates that a wakeup event was received from the WKUP line 8. * @retval The state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_PWR_GET_FLAG(__FLAG__) \ - ( \ +#if defined (PWR_FLAG_USBBOOSTRDY) +#define __HAL_PWR_GET_FLAG(__FLAG__) \ + ( \ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == PWR_VOSR_VOSRDY) : \ + ((__FLAG__) == PWR_FLAG_BOOSTRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == PWR_VOSR_BOOSTRDY) : \ + ((__FLAG__) == PWR_FLAG_USBBOOSTRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTRDY) == PWR_VOSR_USBBOOSTRDY) : \ + ((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->SR, PWR_SR_STOPF) == PWR_SR_STOPF) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->SR, PWR_SR_SBF) == PWR_SR_SBF) : \ + ((__FLAG__) == PWR_FLAG_VDDA2RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA2RDY) == PWR_SVMSR_VDDA2RDY) : \ + ((__FLAG__) == PWR_FLAG_VDDA1RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA1RDY) == PWR_SVMSR_VDDA1RDY) : \ + ((__FLAG__) == PWR_FLAG_VDDIO2RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDIO2RDY) == PWR_SVMSR_VDDIO2RDY) : \ + ((__FLAG__) == PWR_FLAG_VDDUSBRDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDUSBRDY) == PWR_SVMSR_VDDUSBRDY) : \ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY) == PWR_SVMSR_ACTVOSRDY) : \ + ((__FLAG__) == PWR_FLAG_PVDO) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO) == PWR_SVMSR_PVDO) : \ + ((__FLAG__) == PWR_FLAG_REGS) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_REGS) == PWR_SVMSR_REGS) : \ + ((__FLAG__) == PWR_FLAG_TEMPH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == PWR_BDSR_TEMPH) : \ + ((__FLAG__) == PWR_FLAG_TEMPL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == PWR_BDSR_TEMPL) : \ + ((__FLAG__) == PWR_FLAG_VBATH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == PWR_BDSR_VBATH) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == PWR_WUSR_WUF1) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == PWR_WUSR_WUF2) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == PWR_WUSR_WUF3) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == PWR_WUSR_WUF4) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG5) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == PWR_WUSR_WUF5) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == PWR_WUSR_WUF6) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == PWR_WUSR_WUF7) : \ + (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8)) +#else +#define __HAL_PWR_GET_FLAG(__FLAG__) \ + ( \ ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == PWR_VOSR_VOSRDY) : \ ((__FLAG__) == PWR_FLAG_BOOSTRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == PWR_VOSR_BOOSTRDY) : \ ((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->SR, PWR_SR_STOPF) == PWR_SR_STOPF) : \ @@ -379,6 +414,7 @@ typedef struct ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == PWR_WUSR_WUF6) : \ ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == PWR_WUSR_WUF7) : \ (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8)) +#endif /* defined (PWR_FLAG_USBBOOSTRDY) */ /** @brief Clear PWR flags. * @param __FLAG__ : Specifies the flag to clear. diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pwr_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pwr_ex.c index 20e7ac791c5..ff1861742ad 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pwr_ex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pwr_ex.c @@ -83,7 +83,7 @@ (#) Call HAL_PWREx_EnableVddUSB(), HAL_PWREx_EnableVddIO2() and HAL_PWREx_EnableVddA() to enable respectively VDDUSB, VDDIO2 and VDDA electrical and logical isolation. - It is recommanded to disable VDDUSB, VDDIO2 and VDDA electrical and + It is recommended to disable VDDUSB, VDDIO2 and VDDA electrical and logical isolation through HAL_PWREx_DisableVddUSB(), HAL_PWREx_DisableVddIO2() and HAL_PWREx_DisableVddA(). @@ -100,6 +100,23 @@ (++) VDDA versus 1V6 (++) VDDA versus 1V8 + (#) Call HAL_PWREx_EnableUSBHSTranceiverSupply() and + HAL_PWREx_DisableUSBHSTranceiverSupply() to enable / disable the internal + USB HS transceiver supply. + (+) This feature is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + and STM32U5Gxxx devices + + (#) Call HAL_PWREx_EnableOTGHSPHYLowPowerRetention() and + HAL_PWREx_DisableOTGHSPHYLowPowerRetention() to enable / disable OTG_HS PHY power during + low power modes (Stop2, Stop3 and Standby). + (+) This feature is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + and STM32U5Gxxx devices + + (#) Call HAL_PWREx_EnableVDD11USB() and + HAL_PWREx_DisableVDD11USB() to enable/ disable the VDD11USB. + (+) This feature is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + and STM32U5Gxxx devices + (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring() to enable / disable the VBAT and temperature monitoring. @@ -125,15 +142,29 @@ (+) Retained RAM can be one of the following RAMs : (++) SRAM1 (++) SRAM2 - (++) SRAM3 + (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx, + STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) (++) SRAM4 + (++) SRAM5 (available only for STM32U59xxx, STM32U5Axxx, + STM32U5Fxxx and STM32U5Gxxx devices) + (++) SRAM6 (available only for STM32U5Fxxx and STM32U5Gxxx devices) (++) ICACHE - (++) DMA2DRAM + (++) DMA2DRAM (available only for STM32U575xx, STM32U585xx, STM32U59xxx, + STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) (++) PKA32RAM (++) DCACHE1 (++) FMAC (++) FDCAN (++) USB + (++) DCACHE2 (available only for STM32U59xxx, STM32U5Axxx, + STM32U5Fxxx and STM32U5Gxxx devices) + (++) LTDC (available only for STM32U59xxx, STM32U5Axxx, + STM32U5Fxxx and STM32U5Gxxx devices) + (++) GFXMMU (available only for STM32U59xxx, STM32U5Axxx, + STM32U5Fxxx and STM32U5Gxxx devices) + (++) DSI (available only for STM32U59xxx, STM32U5Axxx, + STM32U5Fxxx and STM32U5Gxxx devices) + (++) JPEG (available only for STM32U5Fxxx and STM32U5Gxxx devices) (#) Call HAL_PWREx_EnableRAMsContentRunRetention() and HAL_PWREx_DisableRAMsContentRunRetention() to @@ -141,8 +172,12 @@ (+) Retained RAM can be one of the following RAMs : (++) SRAM1 (++) SRAM2 - (++) SRAM3 + (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx, + STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) (++) SRAM4 + (++) SRAM5 (available only for STM32U59xxx, STM32U5Axxx, + STM32U5Fxxx and STM32U5Gxxx devices) + (++) SRAM6 (available only for STM32U5Fxxx and STM32U5Gxxx devices) (#) Call HAL_PWREx_EnableFlashFastWakeUp() and HAL_PWREx_DisableFlashFastWakeUp() to enable / disable the flash memory @@ -161,9 +196,9 @@ and pull-down configuration. (#) Call HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() to - apply repectively pull-up and pull-down to selected I/O. + apply respectively pull-up and pull-down to selected I/O. Call HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() to - disable applied repectively pull-up and pull-down to selected I/O. + disable applied respectively pull-up and pull-down to selected I/O. @endverbatim ****************************************************************************** @@ -189,9 +224,17 @@ /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines * @{ */ -/*!< PORTI pins mask */ -#define PWR_PORTI_AVAILABLE_PINS (0xFFU) -/*!< Time out value of flags setting */ +#if defined (PWR_PUCRJ_PU0) +/* PORTI pins mask */ +#define PWR_PORTI_AVAILABLE_PINS (0xFFFFU) +/* PORTJ pins mask */ +#define PWR_PORTJ_AVAILABLE_PINS (0x0FFFU) +#else +/* PORTI pins mask */ +#define PWR_PORTI_AVAILABLE_PINS (0x00FFU) +#endif /* defined (PWR_PUCRJ_PU0) */ + +/* Time out value of flags setting */ #define PWR_FLAG_SETTING_DELAY (0x32U) /** @defgroup PWR_PVM_Mode_Mask PWR PVM Mode Mask @@ -308,6 +351,13 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) /* No change, nothing to do */ if (vos_old == VoltageScaling) { + /* Enable USB BOOST after wake up from Stop mode */ + if (VoltageScaling > PWR_REGULATOR_VOLTAGE_SCALE3) + { + /* Enable USB BOOST */ + SET_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN); + } + return HAL_OK; } @@ -325,7 +375,7 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) MODIFY_REG(PWR->VOSR, (PWR_VOSR_VOS | PWR_VOSR_BOOSTEN), VoltageScaling); } - /* Wait until VOSRDY is rised */ + /* Wait until VOSRDY is raised */ timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U; while (HAL_IS_BIT_CLR(PWR->VOSR, PWR_VOSR_VOSRDY) && (timeout != 0U)) { @@ -335,7 +385,7 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) /* Check time out */ if (timeout != 0U) { - /* Wait until ACTVOSRDY is rised */ + /* Wait until ACTVOSRDY is raised */ timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U; while ((HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY)) && (timeout != 0U)) { @@ -1004,7 +1054,7 @@ __weak void HAL_PWREx_S3WUCallback(uint32_t WakeUpPin) The switch to the VBAT supply is controlled by the power down reset embedded in the Reset block. - (+) After exiting reset, the USB Type-C "dead battery" behavior is enabled, + (+) After exiting reset, the USB Type-C (dead battery) behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to handover control to the UCPD (the UCPD must be initialized @@ -1330,6 +1380,86 @@ void HAL_PWREx_DisableMonitoring(void) CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); } +#if defined (PWR_VOSR_USBPWREN) +/** + * @brief Enable the internal USB HS transceiver supply. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_EnableUSBHSTranceiverSupply(void) +{ + uint32_t vos; + + /* Get the system applied voltage scaling range */ + vos = HAL_PWREx_GetVoltageRange(); + + /* Check the system applied voltage scaling range */ + if ((vos == PWR_REGULATOR_VOLTAGE_SCALE1) || (vos == PWR_REGULATOR_VOLTAGE_SCALE2)) + { + SET_BIT(PWR->VOSR, (PWR_VOSR_USBPWREN | PWR_VOSR_USBBOOSTEN)); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disable the internal USB HS transceiver supply. + * @retval HAL status. + */ +void HAL_PWREx_DisableUSBHSTranceiverSupply(void) +{ + CLEAR_BIT(PWR->VOSR, (PWR_VOSR_USBPWREN | PWR_VOSR_USBBOOSTEN)); +} +#endif /* defined (PWR_VOSR_USBPWREN) */ + +#if defined (PWR_CR1_FORCE_USBPWR) +/** + * @brief Enable OTG_HS PHY power during low power modes (Stop2, Stop3 and Standby). + * @retval None. + */ +void HAL_PWREx_EnableOTGHSPHYLowPowerRetention(void) +{ + /* Set FORCE_USBPWR bit */ + SET_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR); +} + +/** + * @brief Disable OTG_HS PHY power during low power modes (Stop2, Stop3 and Standby). + * @retval None. + */ +void HAL_PWREx_DisableOTGHSPHYLowPowerRetention(void) +{ + /* Clear FORCE_USBPWR bit */ + CLEAR_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR); +} +#endif /* defined (PWR_CR1_FORCE_USBPWR) */ + +#if defined (PWR_VOSR_VDD11USBDIS) +/** + * @brief Enable the VDD11USB. + * @retval None. + */ +void HAL_PWREx_EnableVDD11USB(void) +{ + /* Clear VDD11USBDIS bit */ + CLEAR_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS); +} + +/** + * @brief Disable the VDD11USB. + * @retval None. + */ +void HAL_PWREx_DisableVDD11USB(void) +{ + /* Set VDD11USBDIS bit */ + SET_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS); +} +#endif /* defined (PWR_VOSR_VDD11USBDIS) */ + +#ifdef UCPD1 /** * @brief Enable UCPD configuration memorization in Standby mode. * @retval None. @@ -1352,7 +1482,7 @@ void HAL_PWREx_DisableUCPDStandbyMode(void) /** * @brief Enable dead battery behavior. - * @note After exiting reset, the USB Type-C "dead battery" behavior is + * @note After exiting reset, the USB Type-C (dead battery) behavior is * enabled, which may have a pull-down effect on CC1 and CC2 pins. * It is recommended to disable it in all cases, either to stop this * pull-down or to handover control to the UCPD (the UCPD must be @@ -1366,7 +1496,7 @@ void HAL_PWREx_EnableUCPDDeadBattery(void) /** * @brief Disable dead battery behavior. - * @note After exiting reset, the USB Type-C "dead battery" behavior is + * @note After exiting reset, the USB Type-C (dead battery) behavior is * enabled, which may have a pull-down effect on CC1 and CC2 pins. * It is recommended to disable it in all cases, either to stop this * pull-down or to handover control to the UCPD (the UCPD must be @@ -1377,6 +1507,7 @@ void HAL_PWREx_DisableUCPDDeadBattery(void) { SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); } +#endif /* UCPD1 */ /** * @brief Enable the Battery charging. @@ -1539,10 +1670,12 @@ __weak void HAL_PWREx_AVM2Callback(void) (+) Retained content RAMs in Stop modes are : (++) SRAM1 (++) SRAM2 - (++) SRAM3 + (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx, + STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) (++) SRAM4 (++) ICACHE - (++) DMA2DRAM + (++) DMA2DRAM (available only for STM32U575xx, STM32U585xx, STM32U59xxx, + STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) (++) PKA32RAM (++) DCACHE (++) FMAC @@ -1555,7 +1688,8 @@ __weak void HAL_PWREx_AVM2Callback(void) (+) Retained content RAMs in Run modes are : (++) SRAM1 (++) SRAM2 - (++) SRAM3 + (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx, + STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) (++) SRAM4 [..] @@ -1576,9 +1710,9 @@ __weak void HAL_PWREx_AVM2Callback(void) * Stop 3 and Standby mode and its content is kept. * @param SRAM2Pages : Specifies the SRAM2 pages. * This parameter can be one of the following values : - * @arg PWR_SRAM2_PAGE1_STANDBY_RETENTION : SRAM2 page 1 retention. - * @arg PWR_SRAM2_PAGE2_STANDBY_RETENTION : SRAM2 page 2 retention. - * @arg PWR_SRAM2_FULL_STANDBY_RETENTION : SRAM2 page 1 and page 2 retention. + * @arg PWR_SRAM2_PAGE1_STANDBY : SRAM2 page 1 retention. + * @arg PWR_SRAM2_PAGE2_STANDBY : SRAM2 page 2 retention. + * @arg PWR_SRAM2_FULL_STANDBY : SRAM2 page 1 and page 2 retention. * @retval None. */ void HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages) @@ -1596,9 +1730,9 @@ void HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages) * mode and its content is lost. * @param SRAM2Pages : Specifies the SRAM2 pages. * This parameter can be one of the following values : - * @arg PWR_SRAM2_PAGE1_STANDBY_RETENTION : SRAM2 page 1 retention. - * @arg PWR_SRAM2_PAGE2_STANDBY_RETENTION : SRAM2 page 2 retention. - * @arg PWR_SRAM2_FULL_STANDBY_RETENTION : SRAM2 page 1 and page 2 retention. + * @arg PWR_SRAM2_PAGE1_STANDBY : SRAM2 page 1 retention. + * @arg PWR_SRAM2_PAGE2_STANDBY : SRAM2 page 2 retention. + * @arg PWR_SRAM2_FULL_STANDBY : SRAM2 page 1 and page 2 retention. * @retval None. */ void HAL_PWREx_DisableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages) @@ -1636,6 +1770,12 @@ void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID); CLEAR_BIT(PWR->CR2, dummy); +#if defined (PWR_CR4_SRAM1PDS4) + /* Calculate pages mask */ + dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID)) >> 0x03U; + CLEAR_BIT(PWR->CR4, dummy); +#endif /* defined (PWR_CR4_SRAM1PDS4) */ + break; } @@ -1646,12 +1786,13 @@ void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_SRAM2_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_SRAM2_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_SRAM2_FULL_STOP) & ~SRAM_ID_MASK; CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM2PDS1_Pos)); break; } +#if defined (PWR_CR2_SRAM3PDS1) /* SRAM 3 Stop retention */ case SRAM3_ID: { @@ -1663,8 +1804,16 @@ void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID); CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM3PDS1_Pos)); +#if defined (PWR_CR4_SRAM3PDS9) + /* Calculate pages mask */ + dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID | + PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID)) >> 0x08U; + CLEAR_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM3PDS9_Pos)); +#endif /* defined (PWR_CR4_SRAM3PDS9) */ + break; } +#endif /* PWR_CR2_SRAM3PDS1 */ /* SRAM 4 Stop retention */ case SRAM4_ID: @@ -1673,7 +1822,7 @@ void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_SRAM4_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_SRAM4_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_SRAM4_FULL_STOP) & ~SRAM_ID_MASK; CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM4PDS_Pos)); break; @@ -1686,7 +1835,7 @@ void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_ICACHE_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_ICACHE_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_ICACHE_FULL_STOP) & ~SRAM_ID_MASK; CLEAR_BIT(PWR->CR2, dummy << PWR_CR2_ICRAMPDS_Pos); break; @@ -1699,12 +1848,13 @@ void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_DCACHE1_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP) & ~SRAM_ID_MASK; CLEAR_BIT(PWR->CR2, dummy << PWR_CR2_DC1RAMPDS_Pos); break; } +#if defined (PWR_CR2_DMA2DRAMPDS) /* DMA2D RAM Stop retention */ case DMA2DRAM_ID: { @@ -1712,11 +1862,12 @@ void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_DMA2DRAM_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP) & ~SRAM_ID_MASK; CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_DMA2DRAMPDS_Pos)); break; } +#endif /* PWR_CR2_DMA2DRAMPDS */ /* FMAC, FDCAN and USB RAM Stop retention */ case PERIPHRAM_ID: @@ -1725,7 +1876,7 @@ void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_PERIPHRAM_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP) & ~SRAM_ID_MASK; CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_PRAMPDS_Pos)); break; @@ -1738,12 +1889,102 @@ void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_PKA32RAM_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP) & ~SRAM_ID_MASK; CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_PKARAMPDS_Pos)); break; } +#if defined (PWR_CR2_DC2RAMPDS) + /* DCACHE2 RAM Stop retention */ + case DCACHE2RAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_DCACHE2_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_DCACHE2_FULL_STOP) & ~SRAM_ID_MASK; + CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_DC2RAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_DC2RAMPDS) */ + +#if defined (PWR_CR2_GPRAMPDS) + /* LTDC and GFXMMU RAM Stop retention */ + case GRAPHIPRAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_GRAPHICPRAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_GRAPHICPRAM_FULL_STOP) & ~SRAM_ID_MASK; + CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_GPRAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_GPRAMPDS) */ + +#if defined (PWR_CR2_DSIRAMPDS) + /* DSI RAM Stop retention */ + case DSIRAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_DSIRAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_DSIRAM_FULL_STOP) & ~SRAM_ID_MASK; + CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_DSIRAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_DSIRAMPDS) */ + +#if defined (PWR_CR2_JPEGRAMPDS) + /* JPEG RAM Stop retention */ + case JPEGRAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_JPEGRAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_JPEGRAM_FULL_STOP) & ~SRAM_ID_MASK; + CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_JPEGRAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_JPEGRAMPDS) */ + +#if defined (PWR_CR4_SRAM5PDS1) + /* SRAM 5 Stop retention */ + case SRAM5_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_SRAM5_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = ((RAMSelection & PWR_SRAM5_FULL_STOP) & ~SRAM_ID_MASK); + CLEAR_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM5PDS1_Pos)); + + break; + } +#endif /* defined (PWR_CR4_SRAM5PDS1) */ + +#if defined (PWR_CR5_SRAM6PDS1) + /* SRAM 6 Stop retention */ + case SRAM6_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_SRAM6_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = ((RAMSelection & PWR_SRAM6_FULL_STOP) & ~SRAM_ID_MASK); + CLEAR_BIT(PWR->CR5, (dummy << PWR_CR5_SRAM6PDS1_Pos)); + + break; + } +#endif /* defined (PWR_CR5_SRAM6PDS1) */ + default: { return; @@ -1777,6 +2018,11 @@ void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) /* Calculate pages mask */ dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID); SET_BIT(PWR->CR2, dummy); +#if defined (PWR_CR4_SRAM1PDS4) + /* Calculate pages mask */ + dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID)) >> 0x03U; + SET_BIT(PWR->CR4, dummy); +#endif /* defined (PWR_CR4_SRAM1PDS4) */ break; } @@ -1788,12 +2034,13 @@ void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_SRAM2_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_SRAM2_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_SRAM2_FULL_STOP) & ~SRAM_ID_MASK; SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM2PDS1_Pos)); break; } +#if defined (PWR_CR2_SRAM3PDS1) /* SRAM 3 Stop retention */ case SRAM3_ID: { @@ -1805,8 +2052,16 @@ void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID); SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM3PDS1_Pos)); +#if defined (PWR_CR4_SRAM3PDS9) + /* Calculate pages mask */ + dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID | + PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID)) >> 0x08U; + SET_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM3PDS9_Pos)); +#endif /* defined (PWR_CR4_SRAM3PDS9) */ + break; } +#endif /* PWR_CR2_SRAM3PDS1 */ /* SRAM 4 Stop retention */ case SRAM4_ID: @@ -1815,7 +2070,7 @@ void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_SRAM4_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_SRAM4_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_SRAM4_FULL_STOP) & ~SRAM_ID_MASK; SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM4PDS_Pos)); break; @@ -1828,7 +2083,7 @@ void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_ICACHE_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_ICACHE_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_ICACHE_FULL_STOP) & ~SRAM_ID_MASK; SET_BIT(PWR->CR2, (dummy << PWR_CR2_ICRAMPDS_Pos)); break; @@ -1841,12 +2096,13 @@ void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_DCACHE1_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP) & ~SRAM_ID_MASK; SET_BIT(PWR->CR2, (dummy << PWR_CR2_DC1RAMPDS_Pos)); break; } +#if defined (PWR_CR2_DMA2DRAMPDS) /* DMA2D RAM Stop retention */ case DMA2DRAM_ID: { @@ -1854,11 +2110,12 @@ void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_DMA2DRAM_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP) & ~SRAM_ID_MASK; SET_BIT(PWR->CR2, (dummy << PWR_CR2_DMA2DRAMPDS_Pos)); break; } +#endif /* PWR_CR2_DMA2DRAMPDS */ /* FMAC, FDCAN and USB RAM Stop retention */ case PERIPHRAM_ID: @@ -1867,7 +2124,7 @@ void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_PERIPHRAM_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP) & ~SRAM_ID_MASK; SET_BIT(PWR->CR2, (dummy << PWR_CR2_PRAMPDS_Pos)); break; @@ -1880,12 +2137,102 @@ void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) assert_param(IS_PWR_PKA32RAM_STOP_RETENTION(RAMSelection)); /* Calculate pages mask */ - dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK; + dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP) & ~SRAM_ID_MASK; SET_BIT(PWR->CR2, (dummy << PWR_CR2_PKARAMPDS_Pos)); break; } +#if defined (PWR_CR2_DC2RAMPDS) + /* DCACHE2 RAM Stop retention */ + case DCACHE2RAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_DCACHE2_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_DCACHE2_FULL_STOP) & ~SRAM_ID_MASK; + SET_BIT(PWR->CR2, (dummy << PWR_CR2_DC2RAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_DC2RAMPDS) */ + +#if defined (PWR_CR2_GPRAMPDS) + /* LTDC and GFXMMU RAM Stop retention */ + case GRAPHIPRAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_GRAPHICPRAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_GRAPHICPRAM_FULL_STOP) & ~SRAM_ID_MASK; + SET_BIT(PWR->CR2, (dummy << PWR_CR2_GPRAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_GPRAMPDS) */ + +#if defined (PWR_CR2_DSIRAMPDS) + /* DSI RAM Stop retention */ + case DSIRAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_DSIRAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_DSIRAM_FULL_STOP) & ~SRAM_ID_MASK; + SET_BIT(PWR->CR2, (dummy << PWR_CR2_DSIRAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_DSIRAMPDS) */ + +#if defined (PWR_CR2_JPEGRAMPDS) + /* JPEG RAM Stop retention */ + case JPEGRAM_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_JPEGRAM_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = (RAMSelection & PWR_JPEGRAM_FULL_STOP) & ~SRAM_ID_MASK; + SET_BIT(PWR->CR2, (dummy << PWR_CR2_JPEGRAMPDS_Pos)); + + break; + } +#endif /* defined (PWR_CR2_JPEGRAMPDS) */ + +#if defined (PWR_CR4_SRAM5PDS1) + /* SRAM 5 Stop retention */ + case SRAM5_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_SRAM5_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = ((RAMSelection & PWR_SRAM5_FULL_STOP) & ~SRAM_ID_MASK); + SET_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM5PDS1_Pos)); + + break; + } +#endif /* defined (PWR_CR4_SRAM5PDS1) */ + +#if defined (PWR_CR5_SRAM6PDS1) + /* SRAM 6 Stop retention */ + case SRAM6_ID: + { + /* Check the parameters */ + assert_param(IS_PWR_SRAM6_STOP_RETENTION(RAMSelection)); + + /* Calculate pages mask */ + dummy = ((RAMSelection & PWR_SRAM6_FULL_STOP) & ~SRAM_ID_MASK); + SET_BIT(PWR->CR5, (dummy << PWR_CR5_SRAM6PDS1_Pos)); + + break; + } +#endif /* defined (PWR_CR5_SRAM6PDS1) */ + default: { return; @@ -1898,10 +2245,17 @@ void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) * @brief Enable RAMs full content retention in Run mode. * @param RAMSelection : Specifies the SRAM content to be retained in Run mode. * This parameter can be one or a combination of the following values : - * @arg PWR_SRAM1_FULL_RUN_RETENTION : SRAM1 full content retention. - * @arg PWR_SRAM2_FULL_RUN_RETENTION : SRAM2 full content retention. - * @arg PWR_SRAM3_FULL_RUN_RETENTION : SRAM3 full content retention. - * @arg PWR_SRAM4_FULL_RUN_RETENTION : SRAM4 full content retention. + * @arg PWR_SRAM1_FULL_RUN : SRAM1 full content retention. + * @arg PWR_SRAM2_FULL_RUN : SRAM2 full content retention. + * @arg PWR_SRAM3_FULL_RUN : SRAM3 full content retention (available only for STM32U575xx, + * STM32U585xx STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + and STM32U5Gxxx devices). + * @arg PWR_SRAM4_FULL_RUN : SRAM4 full content retention. + * @arg PWR_SRAM5_FULL_RUN : SRAM5 full content retention (available only for + * STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + * and STM32U5Gxxx devices). + * @arg PWR_SRAM6_FULL_RUN : SRAM6 full content retention (available only for + * STM32U5Fxxx and STM32U5Gxxx devices). * @retval None. */ void HAL_PWREx_EnableRAMsContentRunRetention(uint32_t RAMSelection) @@ -1917,10 +2271,17 @@ void HAL_PWREx_EnableRAMsContentRunRetention(uint32_t RAMSelection) * @brief Disable RAMs full content retention in Run mode. * @param RAMSelection : Specifies the SRAM content to be lost in Run mode. * This parameter can be one or a combination of the following values : - * @arg PWR_SRAM1_FULL_RUN_RETENTION : SRAM1 full content lost. - * @arg PWR_SRAM2_FULL_RUN_RETENTION : SRAM2 full content lost. - * @arg PWR_SRAM3_FULL_RUN_RETENTION : SRAM3 full content lost. - * @arg PWR_SRAM4_FULL_RUN_RETENTION : SRAM4 full content lost. + * @arg PWR_SRAM1_FULL_RUN : SRAM1 full content lost. + * @arg PWR_SRAM2_FULL_RUN : SRAM2 full content lost. + * @arg PWR_SRAM3_FULL_RUN : SRAM3 full content lost (available only for STM32U575xx, + * STM32U585xx STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + and STM32U5Gxxx devices). + * @arg PWR_SRAM4_FULL_RUN : SRAM4 full content lost. + * @arg PWR_SRAM5_FULL_RUN : SRAM5 full content retention (available only for + * STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + * and STM32U5Gxxx devices). + * @arg PWR_SRAM6_FULL_RUN : SRAM6 full content retention (available only for + * STM32U5Fxxx and STM32U5Gxxx devices). * @retval None. */ void HAL_PWREx_DisableRAMsContentRunRetention(uint32_t RAMSelection) @@ -2034,15 +2395,17 @@ void HAL_PWREx_DisableSRAM4FastWakeUp(void) * @verbatim =============================================================================== - ##### Voltage monitoring Functions ##### + ##### I/O Pull-Up Pull-Down Configuration Functions ##### =============================================================================== [..] In Standby and Shutdown mode, pull up and pull down can be configured to maintain an I/O in the selected state. If the APC bit in the PWR_APCR register is set, the I/Os can be configured either with a pull-up through - PWR_PUCRx registers (x=A,B,C,D,E,F,G,H,I), or with a pull-down through - PWR_PDCRx registers (x=A,B,C,D,E,F,G,H,I)), or can be kept in analog state + PWR_PUCRx registers (x=A,B,C,D,E,F,G,H,I,J), or with a pull-down through + PWR_PDCRx registers (x=A,B,C,D,E,F,G,H,I,J)), or can be kept in analog state if none of the PWR_PUCRx or PWR_PDCRx register is set. + (+) Port J is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx + and STM32U5Gxxx devices. [..] The pull-down configuration has highest priority over pull-up @@ -2139,10 +2502,12 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_P CLEAR_BIT(PWR->PDCRE, GPIO_Pin); break; +#ifdef PWR_PUCRF_PU0 case PWR_GPIO_F: /* Apply Pull Up to GPIO port F */ SET_BIT(PWR->PUCRF, GPIO_Pin); CLEAR_BIT(PWR->PDCRF, GPIO_Pin); break; +#endif /* PWR_PUCRF_PU0 */ case PWR_GPIO_G: /* Apply Pull Up to GPIO port G */ SET_BIT(PWR->PUCRG, GPIO_Pin); @@ -2154,10 +2519,19 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_P CLEAR_BIT(PWR->PDCRH, GPIO_Pin); break; +#ifdef PWR_PUCRI_PU0 case PWR_GPIO_I: /* Apply Pull Up to GPIO port I */ SET_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); CLEAR_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); break; +#endif /* PWR_PUCRI_PU0 */ + +#if defined (PWR_PUCRJ_PU0) + case PWR_GPIO_J: /* Apply Pull Up to GPIO port J */ + SET_BIT(PWR->PUCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); + CLEAR_BIT(PWR->PDCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); + break; +#endif /* defined (PWR_PUCRJ_PU0) */ default: return HAL_ERROR; @@ -2210,9 +2584,11 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_ CLEAR_BIT(PWR->PUCRE, GPIO_Pin); break; +#ifdef PWR_PUCRF_PU0 case PWR_GPIO_F: /* Disable Pull Up for GPIO port F */ CLEAR_BIT(PWR->PUCRF, GPIO_Pin); break; +#endif /* PWR_PUCRF_PU0 */ case PWR_GPIO_G: /* Disable Pull Up for GPIO port G */ CLEAR_BIT(PWR->PUCRG, GPIO_Pin); @@ -2222,9 +2598,17 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_ CLEAR_BIT(PWR->PUCRH, GPIO_Pin); break; +#ifdef PWR_PUCRI_PU0 case PWR_GPIO_I: /* Disable Pull Up for GPIO port I */ CLEAR_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); break; +#endif /* PWR_PUCRI_PU0 */ + +#if defined (PWR_PUCRJ_PU0) + case PWR_GPIO_J: /* Disable Pull Up for GPIO port J */ + CLEAR_BIT(PWR->PUCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); + break; +#endif /* defined (PWR_PUCRJ_PU0) */ default: return HAL_ERROR; @@ -2289,10 +2673,12 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO CLEAR_BIT(PWR->PUCRE, GPIO_Pin); break; +#ifdef PWR_PUCRF_PU0 case PWR_GPIO_F: /* Apply Pull Down to GPIO port F */ SET_BIT(PWR->PDCRF, GPIO_Pin); CLEAR_BIT(PWR->PUCRF, GPIO_Pin); break; +#endif /* PWR_PUCRF_PU0 */ case PWR_GPIO_G: /* Apply Pull Down to GPIO port G */ SET_BIT(PWR->PDCRG, GPIO_Pin); @@ -2304,10 +2690,19 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO CLEAR_BIT(PWR->PUCRH, GPIO_Pin); break; +#ifdef PWR_PUCRI_PU0 case PWR_GPIO_I: /* Apply Pull Down to GPIO port I */ SET_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); CLEAR_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); break; +#endif /* PWR_PUCRI_PU0 */ + +#if defined (PWR_PUCRJ_PU0) + case PWR_GPIO_J: /* Apply Pull Down to GPIO port J */ + SET_BIT(PWR->PDCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); + CLEAR_BIT(PWR->PUCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); + break; +#endif /* defined (PWR_PUCRJ_PU0) */ default: return HAL_ERROR; @@ -2360,9 +2755,11 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPI CLEAR_BIT(PWR->PDCRE, GPIO_Pin); break; +#ifdef PWR_PUCRF_PU0 case PWR_GPIO_F: /* Disable Pull Down for GPIO port F */ CLEAR_BIT(PWR->PDCRF, GPIO_Pin); break; +#endif /* PWR_PUCRF_PU0 */ case PWR_GPIO_G: /* Disable Pull Down for GPIO port G */ CLEAR_BIT(PWR->PDCRG, GPIO_Pin); @@ -2372,9 +2769,17 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPI CLEAR_BIT(PWR->PDCRH, GPIO_Pin); break; +#ifdef PWR_PUCRI_PU0 case PWR_GPIO_I: /* Disable Pull Down for GPIO port I */ CLEAR_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); break; +#endif /* PWR_PUCRI_PU0 */ + +#if defined (PWR_PUCRJ_PU0) + case PWR_GPIO_J: /* Disable Pull Down for GPIO port J */ + CLEAR_BIT(PWR->PDCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); + break; +#endif /* defined (PWR_PUCRJ_PU0) */ default: return HAL_ERROR; diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pwr_ex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pwr_ex.h index 88c5d5fede6..8086e6a027d 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pwr_ex.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_pwr_ex.h @@ -102,42 +102,117 @@ typedef struct * @{ */ /* SRAM1 pages retention defines */ -#define PWR_SRAM1_PAGE1_STOP_RETENTION (SRAM1_ID | PAGE01_ID) /*!< SRAM1 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM1_PAGE2_STOP_RETENTION (SRAM1_ID | PAGE02_ID) /*!< SRAM1 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM1_PAGE3_STOP_RETENTION (SRAM1_ID | PAGE03_ID) /*!< SRAM1 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM1_FULL_STOP_RETENTION (SRAM1_ID | 0x07U) /*!< SRAM1 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE1_STOP (SRAM1_ID | PAGE01_ID) /*!< SRAM1 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE2_STOP (SRAM1_ID | PAGE02_ID) /*!< SRAM1 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE3_STOP (SRAM1_ID | PAGE03_ID) /*!< SRAM1 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#if defined (PWR_CR4_SRAM1PDS4) +#define PWR_SRAM1_PAGE4_STOP (SRAM1_ID | PAGE04_ID) /*!< SRAM1 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE5_STOP (SRAM1_ID | PAGE05_ID) /*!< SRAM1 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE6_STOP (SRAM1_ID | PAGE06_ID) /*!< SRAM1 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE7_STOP (SRAM1_ID | PAGE07_ID) /*!< SRAM1 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE8_STOP (SRAM1_ID | PAGE08_ID) /*!< SRAM1 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE9_STOP (SRAM1_ID | PAGE09_ID) /*!< SRAM1 page 9 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE10_STOP (SRAM1_ID | PAGE10_ID) /*!< SRAM1 page 10 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE11_STOP (SRAM1_ID | PAGE11_ID) /*!< SRAM1 page 11 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_PAGE12_STOP (SRAM1_ID | PAGE12_ID) /*!< SRAM1 page 12 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM1_FULL_STOP (SRAM1_ID | 0x0FFFU) /*!< SRAM1 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ +#else +#define PWR_SRAM1_FULL_STOP (SRAM1_ID | 0x07U) /*!< SRAM1 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR4_SRAM1PDS4) */ /* SRAM2 pages retention defines */ -#define PWR_SRAM2_PAGE1_STOP_RETENTION (SRAM2_ID | PAGE01_ID) /*!< SRAM2 page 1 (8 KB) retention in Stop modes (Stop 0, 1, 2) */ -#define PWR_SRAM2_PAGE2_STOP_RETENTION (SRAM2_ID | PAGE02_ID) /*!< SRAM2 page 2 (54 KB) retention in Stop modes (Stop 0, 1, 2) */ -#define PWR_SRAM2_FULL_STOP_RETENTION (SRAM2_ID | 0x03U) /*!< SRAM2 all pages retention in Stop modes (Stop 0, 1, 2) */ +#define PWR_SRAM2_PAGE1_STOP (SRAM2_ID | PAGE01_ID) /*!< SRAM2 page 1 (8 KB) retention in Stop modes (Stop 0, 1, 2) */ +#define PWR_SRAM2_PAGE2_STOP (SRAM2_ID | PAGE02_ID) /*!< SRAM2 page 2 (54 KB) retention in Stop modes (Stop 0, 1, 2) */ +#define PWR_SRAM2_FULL_STOP (SRAM2_ID | 0x03U) /*!< SRAM2 all pages retention in Stop modes (Stop 0, 1, 2) */ +#if defined (PWR_CR2_SRAM3PDS1) /* SRAM3 pages retention defines */ -#define PWR_SRAM3_PAGE1_STOP_RETENTION (SRAM3_ID | PAGE01_ID) /*!< SRAM3 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE2_STOP_RETENTION (SRAM3_ID | PAGE02_ID) /*!< SRAM3 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE3_STOP_RETENTION (SRAM3_ID | PAGE03_ID) /*!< SRAM3 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE4_STOP_RETENTION (SRAM3_ID | PAGE04_ID) /*!< SRAM3 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE5_STOP_RETENTION (SRAM3_ID | PAGE05_ID) /*!< SRAM3 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE6_STOP_RETENTION (SRAM3_ID | PAGE06_ID) /*!< SRAM3 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE7_STOP_RETENTION (SRAM3_ID | PAGE07_ID) /*!< SRAM3 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE8_STOP_RETENTION (SRAM3_ID | PAGE08_ID) /*!< SRAM3 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_FULL_STOP_RETENTION (SRAM3_ID | 0xFFU) /*!< SRAM3 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE1_STOP (SRAM3_ID | PAGE01_ID) /*!< SRAM3 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE2_STOP (SRAM3_ID | PAGE02_ID) /*!< SRAM3 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE3_STOP (SRAM3_ID | PAGE03_ID) /*!< SRAM3 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE4_STOP (SRAM3_ID | PAGE04_ID) /*!< SRAM3 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE5_STOP (SRAM3_ID | PAGE05_ID) /*!< SRAM3 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE6_STOP (SRAM3_ID | PAGE06_ID) /*!< SRAM3 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE7_STOP (SRAM3_ID | PAGE07_ID) /*!< SRAM3 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE8_STOP (SRAM3_ID | PAGE08_ID) /*!< SRAM3 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#if defined (PWR_CR4_SRAM3PDS9) +#define PWR_SRAM3_PAGE9_STOP (SRAM3_ID | PAGE09_ID) /*!< SRAM3 page 9 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE10_STOP (SRAM3_ID | PAGE10_ID) /*!< SRAM3 page 10 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE11_STOP (SRAM3_ID | PAGE11_ID) /*!< SRAM3 page 11 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE12_STOP (SRAM3_ID | PAGE12_ID) /*!< SRAM3 page 12 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_PAGE13_STOP (SRAM3_ID | PAGE13_ID) /*!< SRAM3 page 13 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM3_FULL_STOP (SRAM3_ID | 0x1FFFU) /*!< SRAM3 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ +#else +#define PWR_SRAM3_FULL_STOP (SRAM3_ID | 0xFFU) /*!< SRAM3 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR4_SRAM3PDS9) */ +#endif /* PWR_CR2_SRAM3PDS1 */ /* SRAM4 page retention defines */ -#define PWR_SRAM4_FULL_STOP_RETENTION (SRAM4_ID | PAGE01_ID) /*!< SRAM4 retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM4_FULL_STOP (SRAM4_ID | PAGE01_ID) /*!< SRAM4 retention in Stop modes (Stop 0, 1, 2, 3) */ + +#if defined (PWR_CR4_SRAM5PDS1) +/* SRAM5 pages retention defines */ +#define PWR_SRAM5_PAGE1_STOP (SRAM5_ID | PAGE01_ID) /*!< SRAM5 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE2_STOP (SRAM5_ID | PAGE02_ID) /*!< SRAM5 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE3_STOP (SRAM5_ID | PAGE03_ID) /*!< SRAM5 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE4_STOP (SRAM5_ID | PAGE04_ID) /*!< SRAM5 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE5_STOP (SRAM5_ID | PAGE05_ID) /*!< SRAM5 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE6_STOP (SRAM5_ID | PAGE06_ID) /*!< SRAM5 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE7_STOP (SRAM5_ID | PAGE07_ID) /*!< SRAM5 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE8_STOP (SRAM5_ID | PAGE08_ID) /*!< SRAM5 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE9_STOP (SRAM5_ID | PAGE09_ID) /*!< SRAM5 page 9 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE10_STOP (SRAM5_ID | PAGE10_ID) /*!< SRAM5 page 10 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE11_STOP (SRAM5_ID | PAGE11_ID) /*!< SRAM5 page 11 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE12_STOP (SRAM5_ID | PAGE12_ID) /*!< SRAM5 page 12 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_PAGE13_STOP (SRAM5_ID | PAGE13_ID) /*!< SRAM5 page 13 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM5_FULL_STOP (SRAM5_ID | 0x1FFFU) /*!< SRAM5 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR4_SRAM5PDS1) */ + +#if defined (PWR_CR5_SRAM6PDS1) +/* SRAM5 pages retention defines */ +#define PWR_SRAM6_PAGE1_STOP (SRAM6_ID | PAGE01_ID) /*!< SRAM6 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_PAGE2_STOP (SRAM6_ID | PAGE02_ID) /*!< SRAM6 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_PAGE3_STOP (SRAM6_ID | PAGE03_ID) /*!< SRAM6 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_PAGE4_STOP (SRAM6_ID | PAGE04_ID) /*!< SRAM6 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_PAGE5_STOP (SRAM6_ID | PAGE05_ID) /*!< SRAM6 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_PAGE6_STOP (SRAM6_ID | PAGE06_ID) /*!< SRAM6 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_PAGE7_STOP (SRAM6_ID | PAGE07_ID) /*!< SRAM6 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_PAGE8_STOP (SRAM6_ID | PAGE08_ID) /*!< SRAM6 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_SRAM6_FULL_STOP (SRAM6_ID | 0xFFU) /*!< SRAM6 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR5_SRAM6PDS1) */ /* Cache RAMs retention defines */ -#define PWR_ICACHE_FULL_STOP_RETENTION (ICACHERAM_ID | PAGE01_ID) /*!< ICACHE page retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_DCACHE1_FULL_STOP_RETENTION (DCACHE1RAM_ID | PAGE01_ID) /*!< DCACHE1 page retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_ICACHE_FULL_STOP (ICACHERAM_ID | PAGE01_ID) /*!< ICACHE page retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_DCACHE1_FULL_STOP (DCACHE1RAM_ID | PAGE01_ID) /*!< DCACHE1 page retention in Stop modes (Stop 0, 1, 2, 3) */ +#if defined (PWR_CR2_DC2RAMPDS) +#define PWR_DCACHE2_FULL_STOP (DCACHE2RAM_ID | PAGE01_ID) /*!< DCACHE2 page retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR2_DC2RAMPDS) */ +#if defined (PWR_CR2_DMA2DRAMPDS) /* DMA2D RAM retention defines */ -#define PWR_DMA2DRAM_FULL_STOP_RETENTION (DMA2DRAM_ID | PAGE01_ID) /*!< DMA2D RAM retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_DMA2DRAM_FULL_STOP (DMA2DRAM_ID | PAGE01_ID) /*!< DMA2D RAM retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* PWR_CR2_DMA2DRAMPDS */ /* FMAC, FDCAN and USB RAMs retention defines */ -#define PWR_PERIPHRAM_FULL_STOP_RETENTION (PERIPHRAM_ID | PAGE01_ID) /*!< FMAC, FDCAN and USB RAM retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_PERIPHRAM_FULL_STOP (PERIPHRAM_ID | PAGE01_ID) /*!< FMAC, FDCAN and USB RAM retention in Stop modes (Stop 0, 1, 2, 3) */ /* PKA32 RAM retention defines */ -#define PWR_PKA32RAM_FULL_STOP_RETENTION (PKARAM_ID | PAGE01_ID) /*!< PKA32 RAM retention in Stop modes (Stop 0, 1, 2, 3) */ +#define PWR_PKA32RAM_FULL_STOP (PKARAM_ID | PAGE01_ID) /*!< PKA32 RAM retention in Stop modes (Stop 0, 1, 2, 3) */ + +#if defined (PWR_CR2_GPRAMPDS) +/* Graphic peripherals RAM retention defines */ +#define PWR_GRAPHICPRAM_FULL_STOP (GRAPHIPRAM_ID | PAGE01_ID) /*!< LTDC, GFXMMU retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR2_GPRAMPDS) */ + +#if defined (PWR_CR2_DSIRAMPDS) +/* DSI RAM retention defines */ +#define PWR_DSIRAM_FULL_STOP (DSIRAM_ID | PAGE01_ID) /*!< DSI RAM retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR2_DSIRAMPDS) */ + +#if defined (PWR_CR2_JPEGRAMPDS) +/* JPEG RAM retention defines */ +#define PWR_JPEGRAM_FULL_STOP (JPEGRAM_ID | PAGE01_ID) /*!< JPEG RAM retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR2_JPEGRAMPDS) */ /** * @} */ @@ -147,9 +222,9 @@ typedef struct * the SRAM2 content is preserved based on the same defines in Stop 3 mode. * @{ */ -#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_CR1_RRSB1 /*!< SRAM2 page 1 (8 KB) retention in Stop 3 and Standby modes */ -#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_CR1_RRSB2 /*!< SRAM2 page 2 (54 KB) retention in Stop 3 and Standby modes */ -#define PWR_SRAM2_FULL_STANDBY_RETENTION (PWR_CR1_RRSB1 | PWR_CR1_RRSB2) /*!< SRAM2 all pages retention in Stop 3 and Standby modes */ +#define PWR_SRAM2_PAGE1_STANDBY PWR_CR1_RRSB1 /*!< SRAM2 page 1 (8 KB) retention in Stop 3 and Standby modes */ +#define PWR_SRAM2_PAGE2_STANDBY PWR_CR1_RRSB2 /*!< SRAM2 page 2 (54 KB) retention in Stop 3 and Standby modes */ +#define PWR_SRAM2_FULL_STANDBY (PWR_CR1_RRSB1 | PWR_CR1_RRSB2) /*!< SRAM2 all pages retention in Stop 3 and Standby modes */ /** * @} */ @@ -157,10 +232,18 @@ typedef struct /** @defgroup PWREx_SRAMx_Contents_Run_Retention PWR Extended SRAM Contents Run Retention * @{ */ -#define PWR_SRAM1_FULL_RUN_RETENTION PWR_CR1_SRAM1PD /*!< SRAM1 full retention in Run mode */ -#define PWR_SRAM2_FULL_RUN_RETENTION PWR_CR1_SRAM2PD /*!< SRAM2 full retention in Run mode */ -#define PWR_SRAM3_FULL_RUN_RETENTION PWR_CR1_SRAM3PD /*!< SRAM3 full retention in Run mode */ -#define PWR_SRAM4_FULL_RUN_RETENTION PWR_CR1_SRAM4PD /*!< SRAM4 full retention in Run mode */ +#define PWR_SRAM1_FULL_RUN PWR_CR1_SRAM1PD /*!< SRAM1 full retention in Run mode */ +#define PWR_SRAM2_FULL_RUN PWR_CR1_SRAM2PD /*!< SRAM2 full retention in Run mode */ +#if defined (PWR_CR1_SRAM3PD) +#define PWR_SRAM3_FULL_RUN PWR_CR1_SRAM3PD /*!< SRAM3 full retention in Run mode */ +#endif /* PWR_CR1_SRAM3PD */ +#define PWR_SRAM4_FULL_RUN PWR_CR1_SRAM4PD /*!< SRAM4 full retention in Run mode */ +#if defined (PWR_CR1_SRAM5PD) +#define PWR_SRAM5_FULL_RUN PWR_CR1_SRAM5PD /*!< SRAM5 full retention in Run mode */ +#endif /* defined (PWR_CR1_SRAM5PD) */ +#if defined (PWR_CR1_SRAM6PD) +#define PWR_SRAM6_FULL_RUN PWR_CR1_SRAM6PD /*!< SRAM6 full retention in Run mode */ +#endif /* defined (PWR_CR1_SRAM6PD) */ /** * @} */ @@ -194,15 +277,6 @@ typedef struct * @} */ -/** @defgroup PWREx_VBAT_Battery_Charging_State PWR Extended Battery Charging State - * @{ - */ -#define PWR_BATTERY_CHARGING_DISABLE (0U) /*!< Disable battery charging */ -#define PWR_BATTERY_CHARGING_ENABLE PWR_BDCR2_VBE /*!< Enable battery charging */ -/** - * @} - */ - /** @defgroup PWREx_GPIO_Port PWR Extended GPIO Port * @{ */ @@ -211,10 +285,17 @@ typedef struct #define PWR_GPIO_C (0x02U) /*!< GPIO port C */ #define PWR_GPIO_D (0x03U) /*!< GPIO port D */ #define PWR_GPIO_E (0x04U) /*!< GPIO port E */ +#if defined (PWR_PUCRF_PU0) #define PWR_GPIO_F (0x05U) /*!< GPIO port F */ +#endif /* PWR_PUCRF_PU0 */ #define PWR_GPIO_G (0x06U) /*!< GPIO port G */ #define PWR_GPIO_H (0x07U) /*!< GPIO port H */ +#if defined (PWR_PUCRI_PU0) #define PWR_GPIO_I (0x08U) /*!< GPIO port I */ +#endif /* PWR_PUCRI_PU0 */ +#if defined (PWR_PUCRJ_PU0) +#define PWR_GPIO_J (0x09U) /*!< GPIO port J */ +#endif /* defined (PWR_PUCRJ_PU0) */ /** * @} */ @@ -673,13 +754,35 @@ typedef struct #define SRAM_ID_MASK (0xFFFFUL << 16U) #define SRAM1_ID (0x01UL << 16U) #define SRAM2_ID (0x01UL << 17U) +#if defined (PWR_CR2_SRAM3PDS1) #define SRAM3_ID (0x01UL << 18U) +#endif /* PWR_CR2_SRAM3PDS1 */ #define SRAM4_ID (0x01UL << 19U) #define ICACHERAM_ID (0x01UL << 20U) #define DCACHE1RAM_ID (0x01UL << 21U) +#if defined (PWR_CR2_DMA2DRAMPDS) #define DMA2DRAM_ID (0x01UL << 22U) +#endif /* PWR_CR2_DMA2DRAMPDS */ #define PERIPHRAM_ID (0x01UL << 23U) #define PKARAM_ID (0x01UL << 24U) +#if defined (PWR_CR2_DC2RAMPDS) +#define DCACHE2RAM_ID (0x01UL << 25U) +#endif /* defined (PWR_CR2_DC2RAMPDS) */ +#if defined (PWR_CR2_GPRAMPDS) +#define GRAPHIPRAM_ID (0x01UL << 26U) +#endif /* defined (PWR_CR2_GPRAMPDS) */ +#if defined (PWR_CR2_DSIRAMPDS) +#define DSIRAM_ID (0x01UL << 27U) +#endif /* defined (PWR_CR2_DSIRAMPDS) */ +#if defined (PWR_CR4_SRAM5PDS1) +#define SRAM5_ID (0x01UL << 28U) +#endif /* defined (PWR_CR4_SRAM5PDS1) */ +#if defined (PWR_CR5_SRAM6PDS1) +#define SRAM6_ID (0x01UL << 29U) +#endif /* defined (PWR_CR5_SRAM6PDS1) */ +#if defined (PWR_CR2_JPEGRAMPDS) +#define JPEGRAM_ID (0x01UL << 30U) +#endif /* defined (PWR_CR2_JPEGRAMPDS)*/ /* SRAM page retention IDs */ #define PAGE01_ID (0x01UL << 0U) @@ -697,8 +800,21 @@ typedef struct #define PAGE13_ID (0x01UL << 12U) /* All available RAM retention in Run mode define */ -#define PWR_ALL_RAM_RUN_RETENTION_MASK (PWR_SRAM1_FULL_RUN_RETENTION | PWR_SRAM2_FULL_RUN_RETENTION | \ - PWR_SRAM3_FULL_RUN_RETENTION | PWR_SRAM4_FULL_RUN_RETENTION) +#if defined (PWR_CR1_SRAM6PD) +#define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \ + PWR_SRAM3_FULL_RUN | PWR_SRAM4_FULL_RUN | \ + PWR_SRAM5_FULL_RUN | PWR_SRAM6_FULL_RUN) +#elif defined (PWR_CR1_SRAM5PD) +#define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \ + PWR_SRAM3_FULL_RUN | PWR_SRAM4_FULL_RUN | \ + PWR_SRAM5_FULL_RUN) +#elif defined (PWR_CR2_SRAM3PDS1) +#define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \ + PWR_SRAM3_FULL_RUN | PWR_SRAM4_FULL_RUN) +#else +#define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \ + PWR_SRAM4_FULL_RUN) +#endif /* defined (PWR_CR1_SRAM5PD) */ /** * @} */ @@ -747,13 +863,21 @@ typedef struct (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) -/* Battery charging activation check macro */ -#define IS_PWR_BATTERY_CHARGING(CHARGING) \ - (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\ - ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) - /* GPIO port check macro */ -#define IS_PWR_GPIO_PORT(GPIO_PORT) \ +#if defined (PWR_PUCRJ_PU0) +#define IS_PWR_GPIO_PORT(GPIO_PORT) \ + (((GPIO_PORT) == PWR_GPIO_A) ||\ + ((GPIO_PORT) == PWR_GPIO_B) ||\ + ((GPIO_PORT) == PWR_GPIO_C) ||\ + ((GPIO_PORT) == PWR_GPIO_D) ||\ + ((GPIO_PORT) == PWR_GPIO_E) ||\ + ((GPIO_PORT) == PWR_GPIO_F) ||\ + ((GPIO_PORT) == PWR_GPIO_G) ||\ + ((GPIO_PORT) == PWR_GPIO_H) ||\ + ((GPIO_PORT) == PWR_GPIO_I) ||\ + ((GPIO_PORT) == PWR_GPIO_J)) +#elif defined (PWR_PUCRF_PU0) && defined (PWR_PUCRI_PU0) +#define IS_PWR_GPIO_PORT(GPIO_PORT) \ (((GPIO_PORT) == PWR_GPIO_A) ||\ ((GPIO_PORT) == PWR_GPIO_B) ||\ ((GPIO_PORT) == PWR_GPIO_C) ||\ @@ -763,6 +887,16 @@ typedef struct ((GPIO_PORT) == PWR_GPIO_G) ||\ ((GPIO_PORT) == PWR_GPIO_H) ||\ ((GPIO_PORT) == PWR_GPIO_I)) +#else +#define IS_PWR_GPIO_PORT(GPIO_PORT) \ + (((GPIO_PORT) == PWR_GPIO_A) ||\ + ((GPIO_PORT) == PWR_GPIO_B) ||\ + ((GPIO_PORT) == PWR_GPIO_C) ||\ + ((GPIO_PORT) == PWR_GPIO_D) ||\ + ((GPIO_PORT) == PWR_GPIO_E) ||\ + ((GPIO_PORT) == PWR_GPIO_G) ||\ + ((GPIO_PORT) == PWR_GPIO_H)) +#endif /* defined (PWR_PUCRJ_PU0) */ /* GPIO pin mask check macro */ #define IS_PWR_GPIO_PIN_MASK(BIT_MASK) \ @@ -770,41 +904,75 @@ typedef struct /* SRAM2 retention in Standby mode check macro */ #define IS_PWR_SRAM2_STANDBY_RETENTION(CONTENT) \ - (((CONTENT) == PWR_SRAM2_PAGE1_STANDBY_RETENTION) ||\ - ((CONTENT) == PWR_SRAM2_PAGE2_STANDBY_RETENTION) ||\ - ((CONTENT) == PWR_SRAM2_FULL_STANDBY_RETENTION)) + (((CONTENT) == PWR_SRAM2_PAGE1_STANDBY) ||\ + ((CONTENT) == PWR_SRAM2_PAGE2_STANDBY) ||\ + ((CONTENT) == PWR_SRAM2_FULL_STANDBY)) /* RAMs retention in Stop mode check macros */ #define IS_PWR_SRAM1_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_SRAM1_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) + ((((RAMCONTENT) & (~PWR_SRAM1_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) #define IS_PWR_SRAM2_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_SRAM2_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) + ((((RAMCONTENT) & (~PWR_SRAM2_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#if defined (PWR_CR2_SRAM3PDS1) #define IS_PWR_SRAM3_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_SRAM3_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) + ((((RAMCONTENT) & (~PWR_SRAM3_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* PWR_CR2_SRAM3PDS1 */ #define IS_PWR_SRAM4_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_SRAM4_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) + ((((RAMCONTENT) & (~PWR_SRAM4_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) + +#if defined (PWR_CR4_SRAM5PDS1) +#define IS_PWR_SRAM5_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_SRAM5_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* defined (PWR_CR4_SRAM5PDS1) */ + +#if defined (PWR_CR5_SRAM6PDS1) +#define IS_PWR_SRAM6_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_SRAM6_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* defined (PWR_CR5_SRAM6PDS1) */ #define IS_PWR_ICACHE_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_ICACHE_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) + ((((RAMCONTENT) & (~PWR_ICACHE_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) #define IS_PWR_DCACHE1_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_DCACHE1_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) + ((((RAMCONTENT) & (~PWR_DCACHE1_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) + +#if defined (PWR_CR2_DC2RAMPDS) +#define IS_PWR_DCACHE2_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_DCACHE2_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* defined (PWR_CR2_DC2RAMPDS) */ +#if defined (PWR_CR2_DMA2DRAMPDS) #define IS_PWR_DMA2DRAM_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_DMA2DRAM_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) + ((((RAMCONTENT) & (~PWR_DMA2DRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* PWR_CR2_DMA2DRAMPDS */ #define IS_PWR_PERIPHRAM_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_PERIPHRAM_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) + ((((RAMCONTENT) & (~PWR_PERIPHRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) #define IS_PWR_PKA32RAM_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_PKA32RAM_FULL_STOP_RETENTION)) == 0U) && ((RAMCONTENT) != 0U)) + ((((RAMCONTENT) & (~PWR_PKA32RAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) + +#if defined (PWR_CR2_GPRAMPDS) +#define IS_PWR_GRAPHICPRAM_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_GRAPHICPRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* defined (PWR_CR2_GPRAMPDS) */ + +#if defined (PWR_CR2_DSIRAMPDS) +#define IS_PWR_DSIRAM_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_DSIRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* defined (PWR_CR2_DSIRAMPDS) */ + +#if defined (PWR_CR2_JPEGRAMPDS) +#define IS_PWR_JPEGRAM_STOP_RETENTION(RAMCONTENT) \ + ((((RAMCONTENT) & (~PWR_JPEGRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) +#endif /* defined (PWR_CR2_DSIRAMPDS) */ /* RAMs retention in Run mode check macro */ #define IS_PWR_RAM_RUN_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_ALL_RAM_RUN_RETENTION_MASK)) == 0U) && ((RAMCONTENT) != 0U)) + ((((RAMCONTENT) & (~PWR_ALL_RAM_RUN_MASK)) == 0U) && ((RAMCONTENT) != 0U)) /** * @} */ @@ -861,6 +1029,18 @@ void HAL_PWREx_EnableAVM1(void); void HAL_PWREx_DisableAVM1(void); void HAL_PWREx_EnableAVM2(void); void HAL_PWREx_DisableAVM2(void); +#if defined (PWR_VOSR_USBPWREN) +HAL_StatusTypeDef HAL_PWREx_EnableUSBHSTranceiverSupply(void); +void HAL_PWREx_DisableUSBHSTranceiverSupply(void); +#endif /* defined (PWR_VOSR_USBPWREN) */ +#if defined (PWR_CR1_FORCE_USBPWR) +void HAL_PWREx_EnableOTGHSPHYLowPowerRetention(void); +void HAL_PWREx_DisableOTGHSPHYLowPowerRetention(void); +#endif /* defined (PWR_CR1_FORCE_USBPWR) */ +#if defined (PWR_VOSR_VDD11USBDIS) +void HAL_PWREx_EnableVDD11USB(void); +void HAL_PWREx_DisableVDD11USB(void); +#endif /* defined (PWR_VOSR_VDD11USBDIS) */ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *pConfigPVM); void HAL_PWREx_EnableMonitoring(void); void HAL_PWREx_DisableMonitoring(void); diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ramcfg.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ramcfg.c index fdd5f5476fc..ad1e50afa25 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ramcfg.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ramcfg.c @@ -47,25 +47,32 @@ ##### How to use this driver ##### ============================================================================== [..] - (#) Call HAL_RAMCFG_Init() to initialize the RAMCFG peripheral before using + (#) Call HAL_RAMCFG_Init() to initialize the RAMCFG peripheral before using any feature. Call HAL_RAMCFG_DeInit() to de-initialize the RAMCFG when using this peripheral is no more needed or a hardware issue has occurred. + (+) HAL_RAMCFG_Init() and HAL_RAMCFG_DeInit() APIs do not change the + activation status of ECC feature. It is managed by + HAL_RAMCFG_StartECC(), HAL_RAMCFG_StopECC() or option bytes (When + available on the device). *** ECC feature *** =================== [..] (+) Call HAL_RAMCFG_StartECC() and HAL_RAMCFG_StopECC() to enable and - disable ECC hardware process. + disable ECC hardware mechanism. + (++) When ECC feature is previously enabled (case of option + byte activation), calling HAL_RAMCFG_StartECC() is + recommended to enable the ECC address latching feature. (+) Call HAL_RAMCFG_EnableNotification() and HAL_RAMCFG_DisableNotification() - to enable and disable ECC interrupts. Interrupts can be : + to enable and disable ECC interrupts. Interrupts can be: (++) Single error interrupt. (++) Double error interrupt. - (++) Double error interrupt redirected to Non masKable + (++) Double error interrupt redirected to Non maskable interrupt (NMI). (+) Call HAL_RAMCFG_GetSingleErrorAddress() to get the address of the - last fail RAM word detected (only for single error) and + last fail RAM word detected (only for single error) and call HAL_RAMCFG_GetDoubleErrorAddress() to get the address of the last fail RAM word detected (only for double error). @@ -162,12 +169,15 @@ ##### Initialization and de-initialization Functions ##### =============================================================================== [..] - This section provides functions allowing to initialize and de-initialize the - RAMCFG instance. + This section provides functions allowing to initialize and de-initialize the + RAMCFG instance. [..] - The HAL_RAMCFG_Init() function follows the RAMCFG instance configuration - procedures as described in the reference manual. - The HAL_RAMCFG_DeInit() function allows to deinitialize the RAMCFG instance. + The HAL_RAMCFG_Init() function follows the RAMCFG instance configuration + procedures as described in the reference manual. + The HAL_RAMCFG_DeInit() function allows to deinitialize the RAMCFG instance. + HAL_RAMCFG_Init() and HAL_RAMCFG_DeInit() APIs do not change the activation + status of ECC feature. It is managed by HAL_RAMCFG_StartECC(), + HAL_RAMCFG_StopECC() or option bytes (When available on the device). @endverbatim * @{ @@ -208,10 +218,8 @@ HAL_StatusTypeDef HAL_RAMCFG_Init(RAMCFG_HandleTypeDef *hramcfg) HAL_RAMCFG_MspInit(hramcfg); #endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */ - /* Unlock the SRAM ECC enable bit and disable the ECC feature */ - WRITE_REG(hramcfg->Instance->ECCKEY, RAMCFG_ECC_KEY1); - WRITE_REG(hramcfg->Instance->ECCKEY, RAMCFG_ECC_KEY2); - hramcfg->Instance->CR &= ~(RAMCFG_CR_ECCE | RAMCFG_CR_ALE); + /* Disable the ECC Address latch */ + hramcfg->Instance->CR &= ~(RAMCFG_CR_ALE); /* Disable all RAMCFG interrupts */ __HAL_RAMCFG_DISABLE_IT(hramcfg, RAMCFG_IT_ALL); @@ -246,10 +254,8 @@ HAL_StatusTypeDef HAL_RAMCFG_DeInit(RAMCFG_HandleTypeDef *hramcfg) /* Check the parameters */ assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance)); - /* Unlock the SRAM ECC enable bit and disable the ECC feature */ - WRITE_REG(hramcfg->Instance->ECCKEY, RAMCFG_ECC_KEY1); - WRITE_REG(hramcfg->Instance->ECCKEY, RAMCFG_ECC_KEY2); - hramcfg->Instance->CR &= ~(RAMCFG_CR_ECCE | RAMCFG_CR_ALE); + /* Disable the ECC Address latch */ + hramcfg->Instance->CR &= ~(RAMCFG_CR_ALE); /* Disable all RAMCFG interrupts */ __HAL_RAMCFG_DISABLE_IT(hramcfg, RAMCFG_IT_ALL); @@ -321,24 +327,24 @@ __weak void HAL_RAMCFG_MspDeInit(RAMCFG_HandleTypeDef *hramcfg) ##### ECC Operations Functions ##### =============================================================================== [..] - This section provides functions allowing to manage ECC feature provided by - the RAMCFG peripheral. + This section provides functions allowing to manage ECC feature provided by + the RAMCFG peripheral. [..] - The HAL_RAMCFG_StartECC() function allows enabling and starting the ECC - mechanism for the selected RAMCFG instance. - The HAL_RAMCFG_StopECC() function allows disabling and stopping the ECC - mechanism for the selected RAMCFG instance. - The HAL_RAMCFG_EnableNotification() function allows enabling interrupts - for single ECC error, double ECC error and NMI error. - The HAL_RAMCFG_DisableNotification() function allows disabling interrupts - for single ECC error, double ECC error. When NMI interrupt is enabled it - can only be disabled by a global peripheral reset or by a system reset. - The HAL_RAMCFG_IsECCErrorDetected() function allows to check if an ECC error - has occurred. - The HAL_RAMCFG_GetSingleErrorAddress() function allows to get the address of - the last single ECC error detected. - The HAL_RAMCFG_GetDoubleErrorAddress() function allows to get the address of - the last double ECC error detected. + The HAL_RAMCFG_StartECC() function allows starting the ECC mechanism and + enabling ECC address latching for the selected RAMCFG instance. + The HAL_RAMCFG_StopECC() function allows stopping the ECC mechanism and + disabling ECC address latching for the selected RAMCFG instance. + The HAL_RAMCFG_EnableNotification() function allows enabling interrupts + for single ECC error, double ECC error and NMI error. + The HAL_RAMCFG_DisableNotification() function allows disabling interrupts + for single ECC error, double ECC error. When NMI interrupt is enabled it + can only be disabled by a global peripheral reset or by a system reset. + The HAL_RAMCFG_IsECCErrorDetected() function allows to check if an ECC error + has occurred. + The HAL_RAMCFG_GetSingleErrorAddress() function allows to get the address of + the last single ECC error detected. + The HAL_RAMCFG_GetDoubleErrorAddress() function allows to get the address of + the last double ECC error detected. @endverbatim * @{ @@ -353,7 +359,6 @@ __weak void HAL_RAMCFG_MspDeInit(RAMCFG_HandleTypeDef *hramcfg) */ HAL_StatusTypeDef HAL_RAMCFG_StartECC(RAMCFG_HandleTypeDef *hramcfg) { - HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance)); @@ -364,7 +369,7 @@ HAL_StatusTypeDef HAL_RAMCFG_StartECC(RAMCFG_HandleTypeDef *hramcfg) /* Update RAMCFG peripheral state */ hramcfg->State = HAL_RAMCFG_STATE_BUSY; - /* Check if ECC mechanism is active */ + /* Check if ECC mechanism is non active */ if ((hramcfg->Instance->CR & RAMCFG_CR_ECCE) != RAMCFG_CR_ECCE) { /* Start the SRAM ECC mechanism and latching the error address */ @@ -379,7 +384,6 @@ HAL_StatusTypeDef HAL_RAMCFG_StartECC(RAMCFG_HandleTypeDef *hramcfg) /* Update the RAMCFG error code and return error */ hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY; status = HAL_ERROR; - } return status; @@ -411,7 +415,7 @@ HAL_StatusTypeDef HAL_RAMCFG_StopECC(RAMCFG_HandleTypeDef *hramcfg) WRITE_REG(hramcfg->Instance->ECCKEY, RAMCFG_ECC_KEY1); WRITE_REG(hramcfg->Instance->ECCKEY, RAMCFG_ECC_KEY2); - /* Start the SRAM ECC mechanism and latching the error address */ + /* Stop the SRAM ECC mechanism and latching the error address */ hramcfg->Instance->CR &= ~(RAMCFG_CR_ECCE | RAMCFG_CR_ALE); /* Update the RAMCFG state */ @@ -536,7 +540,7 @@ uint32_t HAL_RAMCFG_IsECCDoubleErrorDetected(RAMCFG_HandleTypeDef *hramcfg) /* Check the parameters */ assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance)); - /* Return the state of SEDC flag */ + /* Return the state of DEDC flag */ return ((READ_BIT(hramcfg->Instance->ISR, RAMCFG_FLAG_DOUBLEERR) == (RAMCFG_FLAG_DOUBLEERR)) ? 1UL : 0UL); } @@ -580,13 +584,13 @@ uint32_t HAL_RAMCFG_GetDoubleErrorAddress(RAMCFG_HandleTypeDef *hramcfg) ##### Wait State Functions ##### =============================================================================== [..] - This section provides functions allowing to get and configure the wait state - value . + This section provides functions allowing to get and configure the wait state + value. [..] - The HAL_RAMCFG_ConfigWaitState() function allows configuring the wait state - value. - The HAL_RAMCFG_GetWaitState() function allows getting the current wait state - value. + The HAL_RAMCFG_ConfigWaitState() function allows configuring the wait state + value. + The HAL_RAMCFG_GetWaitState() function allows getting the current wait state + value. @endverbatim * @{ @@ -655,14 +659,13 @@ uint32_t HAL_RAMCFG_GetWaitState(RAMCFG_HandleTypeDef *hramcfg) ##### Write Protection Functions ##### =============================================================================== [..] - This section provides functions to enable write protection feature for - the page(s) of SRAM2. + This section provides functions to enable write protection feature for + the page(s) of SRAM2. [..] - The HAL_RAMCFG_EnableWriteProtection() function allows the user to enable the write - protection for the page(s) of SRAM2. - The HAL_RAMCFG_GetWaitState() function allows get the current wait state - value. Disabling SRAM2 page(s) protection is performed only by a glabal - peripheral reset or a by a system reset. + The HAL_RAMCFG_EnableWriteProtection() function allows the user to enable the write + protection for the page(s) of SRAM2. + Disabling SRAM2 page(s) protection is performed only by a global + peripheral reset or a by a system reset. @endverbatim * @{ @@ -734,10 +737,10 @@ HAL_StatusTypeDef HAL_RAMCFG_EnableWriteProtection(RAMCFG_HandleTypeDef *hramcfg ##### Erase Operation Functions ##### =============================================================================== [..] - This section provides functions allowing a hardware erase for the given SRAM. + This section provides functions allowing a hardware erase for the given SRAM. [..] - The HAL_RAMCFG_Erase() function allows a hardware mass erase for the given - SRAM. The erase value for all SRAMs is 0. + The HAL_RAMCFG_Erase() function allows a hardware mass erase for the given + SRAM. The erase value for all SRAMs is 0. @endverbatim * @{ @@ -753,7 +756,6 @@ HAL_StatusTypeDef HAL_RAMCFG_EnableWriteProtection(RAMCFG_HandleTypeDef *hramcfg */ HAL_StatusTypeDef HAL_RAMCFG_Erase(RAMCFG_HandleTypeDef *hramcfg) { - uint32_t timeout = RAMCFG_TIMEOUT_VALUE; uint32_t tickstart = HAL_GetTick(); /* Check the parameters */ @@ -778,17 +780,14 @@ HAL_StatusTypeDef HAL_RAMCFG_Erase(RAMCFG_HandleTypeDef *hramcfg) */ while (__HAL_RAMCFG_GET_FLAG(hramcfg, RAMCFG_FLAG_SRAMBUSY) != 0U) { - if (timeout != HAL_MAX_DELAY) + if ((HAL_GetTick() - tickstart) > RAMCFG_TIMEOUT_VALUE) { - if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U)) - { - /* Update the RAMCFG error code */ - hramcfg->ErrorCode = HAL_RAMCFG_ERROR_TIMEOUT; - - /* Update the RAMCFG state and return error status */ - hramcfg->State = HAL_RAMCFG_STATE_ERROR; - return HAL_ERROR; - } + /* Update the RAMCFG error code */ + hramcfg->ErrorCode = HAL_RAMCFG_ERROR_TIMEOUT; + + /* Update the RAMCFG state and return error status */ + hramcfg->State = HAL_RAMCFG_STATE_ERROR; + return HAL_ERROR; } } } @@ -815,15 +814,15 @@ HAL_StatusTypeDef HAL_RAMCFG_Erase(RAMCFG_HandleTypeDef *hramcfg) ##### Handle Interrupt and Callbacks Functions ##### =============================================================================== [..] - This section provides functions to handle RAMCFG interrupts and - Register / UnRegister the different callbacks. + This section provides functions to handle RAMCFG interrupts and + Register / UnRegister the different callbacks. [..] - The HAL_RAMCFG_IRQHandler() function allows the user to handle the active RAMCFG - interrupt request. - The HAL_RAMCFG_RegisterCallback() function allows the user to register the selected - RAMCFG callbacks. - The HAL_RAMCFG_UnRegisterCallback() function allows the user to unregister the - selected RAMCFG callbacks. + The HAL_RAMCFG_IRQHandler() function allows the user to handle the active RAMCFG + interrupt request. + The HAL_RAMCFG_RegisterCallback() function allows the user to register the selected + RAMCFG callbacks. + The HAL_RAMCFG_UnRegisterCallback() function allows the user to unregister the + selected RAMCFG callbacks. @endverbatim * @{ */ @@ -918,7 +917,7 @@ __weak void HAL_RAMCFG_DetectDoubleErrorCallback(RAMCFG_HandleTypeDef *hramcfg) * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that * contains the configuration information for the * specified RAMCFG instance. - * @param CallbackID : User Callback identifier a HAL_MDMA_CallbackIDTypeDef + * @param CallbackID : User Callback identifier a HAL_RAMCFG_CallbackIDTypeDef * ENUM as parameter. * @param pCallback : Pointer to private callback function. * @retval HAL status. @@ -929,6 +928,9 @@ HAL_StatusTypeDef HAL_RAMCFG_RegisterCallback(RAMCFG_HandleTypeDef *hramcfg, { HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ + assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance)); + if (pCallback == NULL) { /* Update the error code and return error */ @@ -936,9 +938,6 @@ HAL_StatusTypeDef HAL_RAMCFG_RegisterCallback(RAMCFG_HandleTypeDef *hramcfg, return HAL_ERROR; } - /* Check the parameters */ - assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance)); - /* Check RAMCFG state */ if (hramcfg->State == HAL_RAMCFG_STATE_READY) { @@ -950,7 +949,7 @@ HAL_StatusTypeDef HAL_RAMCFG_RegisterCallback(RAMCFG_HandleTypeDef *hramcfg, break; case HAL_RAMCFG_DE_DETECT_CB_ID: - /* Register single error callback */ + /* Register double error callback */ hramcfg->DetectDoubleErrorCallback = pCallback; break; @@ -1007,7 +1006,7 @@ HAL_StatusTypeDef HAL_RAMCFG_RegisterCallback(RAMCFG_HandleTypeDef *hramcfg, * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that * contains the configuration information for the * specified RAMCFG instance. - * @param CallbackID : User Callback identifier a HAL_MDMA_CallbackIDTypeDef + * @param CallbackID : User Callback identifier a HAL_RAMCFG_CallbackIDTypeDef * ENUM as parameter. * @retval HAL status. */ @@ -1107,13 +1106,13 @@ HAL_StatusTypeDef HAL_RAMCFG_UnRegisterCallback(RAMCFG_HandleTypeDef *hramcfg, H ##### State and Error Functions ##### =============================================================================== [..] - This section provides functions to check and get the RAMCFG state - and the error code . + This section provides functions to check and get the RAMCFG state + and the error code. [..] - The HAL_RAMCFG_GetState() function allows the user to get the RAMCFG peripheral - state. - The HAL_RAMCFG_GetError() function allows the user to get the RAMCFG peripheral error - code. + The HAL_RAMCFG_GetState() function allows the user to get the RAMCFG peripheral + state. + The HAL_RAMCFG_GetError() function allows the user to get the RAMCFG peripheral error + code. @endverbatim * @{ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ramcfg.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ramcfg.h index e297977038e..6b40b4dc876 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ramcfg.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_ramcfg.h @@ -35,6 +35,7 @@ extern "C" { * @{ */ + /* Exported types ------------------------------------------------------------*/ /** @defgroup RAMCFG_Exported_Types RAMCFG Exported Types @@ -91,6 +92,7 @@ typedef struct * @} */ + /* Exported constants --------------------------------------------------------*/ /** @defgroup RAMCFG_Exported_Constants RAMCFG Exported Constants @@ -116,12 +118,11 @@ typedef struct * @brief RAMCFG Interrupts * @{ */ -#define RAMCFG_IT_SINGLEERR RAMCFG_IER_SEIE /* RAMCFG Single Error Interrupt */ -#define RAMCFG_IT_DOUBLEERR RAMCFG_IER_DEIE /* RAMCFG Double Error Interrupt */ -#define RAMCFG_IT_NMIERR RAMCFG_IER_ECCNMI /* RAMCFG Double Error redirected to NMI Interrupt */ -#define RAMCFG_IT_ALL (RAMCFG_IER_SEIE | \ - RAMCFG_IER_DEIE | \ - RAMCFG_IER_ECCNMI) /* RAMCFG All RAMCFG interrupt */ +#define RAMCFG_IT_SINGLEERR RAMCFG_IER_SEIE /*!< RAMCFG Single Error Interrupt */ +#define RAMCFG_IT_DOUBLEERR RAMCFG_IER_DEIE /*!< RAMCFG Double Error Interrupt */ +#define RAMCFG_IT_NMIERR RAMCFG_IER_ECCNMI /*!< RAMCFG Double Error redirected to NMI Interrupt */ +#define RAMCFG_IT_ALL \ + (RAMCFG_IER_SEIE | RAMCFG_IER_DEIE |RAMCFG_IER_ECCNMI) /*!< RAMCFG All RAMCFG interrupt */ /** * @} */ @@ -130,12 +131,11 @@ typedef struct * @brief RAMCFG Monitor Flags * @{ */ -#define RAMCFG_FLAG_SINGLEERR RAMCFG_ISR_SEDC /* RAMCFG Single Error Detected and Corrected Flag */ -#define RAMCFG_FLAG_DOUBLEERR RAMCFG_ISR_DED /* RAMCFG Double Error Detected Flag */ -#define RAMCFG_FLAG_SRAMBUSY RAMCFG_ISR_SRAMBUSY /* RAMCFG SRAM busy Flag */ -#define RAMCFG_FLAGS_ALL (RAMCFG_ISR_SEDC | \ - RAMCFG_ISR_DED | \ - RAMCFG_ISR_SRAMBUSY) /* RAMCFG All Flags */ +#define RAMCFG_FLAG_SINGLEERR RAMCFG_ISR_SEDC /*!< RAMCFG Single Error Detected and Corrected Flag */ +#define RAMCFG_FLAG_DOUBLEERR RAMCFG_ISR_DED /*!< RAMCFG Double Error Detected Flag */ +#define RAMCFG_FLAG_SRAMBUSY RAMCFG_ISR_SRAMBUSY /*!< RAMCFG SRAM busy Flag */ +#define RAMCFG_FLAGS_ALL \ + (RAMCFG_ISR_SEDC | RAMCFG_ISR_DED | RAMCFG_ISR_SRAMBUSY) /*!< RAMCFG All Flags */ /** * @} */ @@ -144,14 +144,14 @@ typedef struct * @brief RAMCFG Wait State * @{ */ -#define RAMCFG_WAITSTATE_0 (0U) /* RAMCFG 0 Wait State */ -#define RAMCFG_WAITSTATE_1 (RAMCFG_CR_WSC_0) /* RAMCFG 1 Wait State */ -#define RAMCFG_WAITSTATE_2 (RAMCFG_CR_WSC_1) /* RAMCFG 2 Wait State */ -#define RAMCFG_WAITSTATE_3 (RAMCFG_CR_WSC_0 | RAMCFG_CR_WSC_1) /* RAMCFG 3 Wait State */ -#define RAMCFG_WAITSTATE_4 (RAMCFG_CR_WSC_2) /* RAMCFG 4 Wait State */ -#define RAMCFG_WAITSTATE_5 (RAMCFG_CR_WSC_0 | RAMCFG_CR_WSC_2) /* RAMCFG 5 Wait State */ -#define RAMCFG_WAITSTATE_6 (RAMCFG_CR_WSC_1 | RAMCFG_CR_WSC_2) /* RAMCFG 6 Wait State */ -#define RAMCFG_WAITSTATE_7 (RAMCFG_CR_WSC_0 | RAMCFG_CR_WSC_1 | RAMCFG_CR_WSC_2) /* RAMCFG 7 Wait State */ +#define RAMCFG_WAITSTATE_0 (0U) /*!< RAMCFG 0 Wait State */ +#define RAMCFG_WAITSTATE_1 (RAMCFG_CR_WSC_0) /*!< RAMCFG 1 Wait State */ +#define RAMCFG_WAITSTATE_2 (RAMCFG_CR_WSC_1) /*!< RAMCFG 2 Wait State */ +#define RAMCFG_WAITSTATE_3 (RAMCFG_CR_WSC_0 | RAMCFG_CR_WSC_1) /*!< RAMCFG 3 Wait State */ +#define RAMCFG_WAITSTATE_4 (RAMCFG_CR_WSC_2) /*!< RAMCFG 4 Wait State */ +#define RAMCFG_WAITSTATE_5 (RAMCFG_CR_WSC_0 | RAMCFG_CR_WSC_2) /*!< RAMCFG 5 Wait State */ +#define RAMCFG_WAITSTATE_6 (RAMCFG_CR_WSC_1 | RAMCFG_CR_WSC_2) /*!< RAMCFG 6 Wait State */ +#define RAMCFG_WAITSTATE_7 (RAMCFG_CR_WSC_0 | RAMCFG_CR_WSC_1 | RAMCFG_CR_WSC_2) /*!< RAMCFG 7 Wait State */ /** * @} */ @@ -160,11 +160,11 @@ typedef struct * @brief RAMCFG Keys * @{ */ -#define RAMCFG_ERASE_KEY1 (0xCAU) /* RAMCFG launch Erase Key 1 */ -#define RAMCFG_ERASE_KEY2 (0x53U) /* RAMCFG launch Erase Key 2 */ +#define RAMCFG_ERASE_KEY1 (0xCAU) /*!< RAMCFG launch Erase Key 1 */ +#define RAMCFG_ERASE_KEY2 (0x53U) /*!< RAMCFG launch Erase Key 2 */ -#define RAMCFG_ECC_KEY1 (0xAEU) /* RAMCFG launch ECC Key 1 */ -#define RAMCFG_ECC_KEY2 (0x75U) /* RAMCFG launch ECC Key 2 */ +#define RAMCFG_ECC_KEY1 (0xAEU) /*!< RAMCFG launch ECC Key 1 */ +#define RAMCFG_ECC_KEY2 (0x75U) /*!< RAMCFG launch ECC Key 2 */ /** * @} */ @@ -175,9 +175,6 @@ typedef struct */ - - - /* Exported macro ------------------------------------------------------------*/ /** @defgroup RAMCFG_Exported_Macros RAMCFG Exported Macros @@ -367,6 +364,7 @@ HAL_RAMCFG_StateTypeDef HAL_RAMCFG_GetState(RAMCFG_HandleTypeDef *hramcfg); * @} */ + /* Private Constants ---------------------------------------------------------*/ /** @defgroup RAMCFG_Private_Constants RAMCFG Private Defines and Constants @@ -377,6 +375,7 @@ HAL_RAMCFG_StateTypeDef HAL_RAMCFG_GetState(RAMCFG_HandleTypeDef *hramcfg); * @} */ + /* Private macros ------------------------------------------------------------*/ /** @defgroup RAMCFG_Private_Macros RAMCFG Private Macros @@ -396,15 +395,11 @@ HAL_RAMCFG_StateTypeDef HAL_RAMCFG_GetState(RAMCFG_HandleTypeDef *hramcfg); #define IS_RAMCFG_WRITEPROTECTION_PAGE(PAGE) ((PAGE) <= 64U) - /** * @} */ - - - /* Private functions ---------------------------------------------------------*/ /** @defgroup RAMCFG_Private_Functions RAMCFG Private Functions @@ -427,5 +422,4 @@ HAL_RAMCFG_StateTypeDef HAL_RAMCFG_GetState(RAMCFG_HandleTypeDef *hramcfg); } #endif - #endif /* STM32U5xx_HAL_RAMCFG_H */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rcc.c index d6775b260fb..70d421125d0 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rcc.c @@ -43,7 +43,7 @@ (+) Configure the AHB and APB busses prescalers (+) Enable the clock for the peripheral(s) to be used (+) Configure the clock source(s) for peripherals which clocks are not - derived from the System clock (SAIx, SYSTICK, RTC, ADC, USB OTG FS/SDMMC1/RNG) + derived from the System clock (SAIx, SYSTICK, RTC, ADC, USB OTG FS/USB FS/SDMMC1/RNG) @endverbatim ****************************************************************************** @@ -69,6 +69,7 @@ * @{ */ #define PLLDIVR_RESET_VALUE (0x01010280U) +#define PLL_FRAC_WAIT_VALUE 1U /* PLL Fractional part waiting time before new latch enable : 1 ms */ /** * @} */ @@ -83,6 +84,7 @@ ((__HSE__) == RCC_HSE_BYPASS) || ((__HSE__) == RCC_HSE_BYPASS_DIGITAL)) #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ + ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY) || \ ((__LSE__) == RCC_LSE_BYPASS)) #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) @@ -124,7 +126,7 @@ #define IS_RCC_PLLRGE_VALUE(VALUE) (((VALUE) == RCC_PLLVCIRANGE_0) || \ ((VALUE) == RCC_PLLVCIRANGE_1)) -#define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <= 8191U) +#define IS_RCC_PLL_FRACN_VALUE(VALUE) ((VALUE) <= 8191U) #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x1FU)) @@ -183,7 +185,8 @@ /** @defgroup RCC_Private_Constants RCC Private Constants * @{ */ -#define LSI_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ +#define LSI_TIMEOUT_VALUE 5UL /* 5 ms (LSI maximum timeout is LSI startup time + LSI_VALUE/128 when + LSI prediv is used) */ #define HSI48_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ #define SHSI_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ #define MSIK_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ @@ -245,7 +248,7 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange); the PLL as System clock source. (+) MSI (Multiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ. - It can be used to generate the clock for the USB OTG FS (48 MHz). + It can be used to generate the clock for the USB FS or USB OTG FS (48 MHz). The number of flash wait states is automatically adjusted when MSI range is updated with HAL_RCC_OscConfig() and the MSI is used as System clock source. @@ -259,14 +262,14 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange); (+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks: (++) The first output is used to generate the high speed system clock (up to 80MHz). - (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), + (++) The second output is used to generate the clock for the USB FS or USB OTG FS (48 MHz), the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). (++) The third output is used to generate an accurate clock to achieve high-quality audio performance on SAI interface. (+) PLL2 (clocked by HSI, HSE or MSI) providing up to three independent output clocks: (++) The first output is used to generate SAR ADC1 clock. - (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), + (++) The second output is used to generate the clock for the USB Fs or USB OTG FS (48 MHz), the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). (++) The Third output is used to generate an accurate clock to achieve high-quality audio performance on SAI interface. @@ -304,7 +307,7 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange); divided by 2 to 31. You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function to configure this clock. - (+@) USB OTG FS, SDMMC1 and RNG: USB OTG FS requires a frequency equal to 48 MHz + (+@) USB FS, USB OTG FS, SDMMC1 and RNG: USB OTG FS or USB FS requires a frequency equal to 48 MHz to work correctly, while the SDMMC1 and RNG peripherals require a frequency equal or lower than to 48 MHz. This clock is derived of the main PLL or PLL2 through PLLQ divider. You have to enable the peripheral clock and use @@ -353,6 +356,7 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange); * - LSI, LSE and RTC clocks * @retval HAL status */ + HAL_StatusTypeDef HAL_RCC_DeInit(void) { uint32_t tickstart; @@ -369,6 +373,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) { return HAL_ERROR; } + } tickstart = HAL_GetTick(); @@ -534,13 +539,15 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) * first and then HSE On or HSE Bypass. * @retval HAL status */ -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pRCC_OscInitStruct) { uint32_t tickstart; HAL_StatusTypeDef status; uint32_t sysclk_source; uint32_t pll_config; FlagStatus pwrboosten = RESET; + uint32_t temp1_pllckcfg; + uint32_t temp2_pllckcfg; /* Check Null pointer */ if (pRCC_OscInitStruct == NULL) @@ -567,7 +574,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_MSI))) { - if ((READ_BIT(RCC->CR, RCC_CR_MSISRDY) != 0U) && (pRCC_OscInitStruct->MSIState == RCC_MSI_OFF)) + if (pRCC_OscInitStruct->MSIState == RCC_MSI_OFF) { return HAL_ERROR; } @@ -580,10 +587,14 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) (HCLK) and the supply voltage of the device */ if (pRCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) { - /* First increase number of wait states update if necessary */ - if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK) + /* Decrease number of wait states update if necessary */ + /* Only possible when MSI is the System clock source */ + if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) { - return HAL_ERROR; + if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK) + { + return HAL_ERROR; + } } /* Selects the Multiple Speed oscillator (MSI) clock range */ @@ -601,10 +612,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \ (pRCC_OscInitStruct->MSIClockRange)); - /* Decrease number of wait states update if necessary */ - if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK) + if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) { - return HAL_ERROR; + if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK) + { + return HAL_ERROR; + } } } @@ -671,7 +684,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) { - if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (pRCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + if (pRCC_OscInitStruct->HSEState == RCC_HSE_OFF) { return HAL_ERROR; } @@ -722,7 +735,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) { /* When HSI is used as system clock it will not be disabled */ - if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (pRCC_OscInitStruct->HSIState == RCC_HSI_OFF)) + if (pRCC_OscInitStruct->HSIState == RCC_HSI_OFF) { return HAL_ERROR; } @@ -1148,6 +1161,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) if ((pRCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) { + FlagStatus pwrclkchanged = RESET; + /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) { @@ -1167,7 +1182,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) tickstart = HAL_GetTick(); - /* Wait till PLL is ready */ + /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) @@ -1176,8 +1191,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) } } - /* Enable PWR CLK */ - __HAL_RCC_PWR_CLK_ENABLE(); + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } /*Disable EPOD to configure PLL1MBOOST*/ if (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) == PWR_VOSR_BOOSTEN) @@ -1195,16 +1214,16 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) pRCC_OscInitStruct->PLL.PLLQ, pRCC_OscInitStruct->PLL.PLLR); - assert_param(IS_RCC_PLLFRACN_VALUE(pRCC_OscInitStruct->PLL.PLLFRACN)); + assert_param(IS_RCC_PLL_FRACN_VALUE(pRCC_OscInitStruct->PLL.PLLFRACN)); /* Disable PLL1FRACN */ - __HAL_RCC_PLLFRACN_DISABLE(); + __HAL_RCC_PLL_FRACN_DISABLE(); /* Configure PLL PLL1FRACN */ - __HAL_RCC_PLLFRACN_CONFIG(pRCC_OscInitStruct->PLL.PLLFRACN); + __HAL_RCC_PLL_FRACN_CONFIG(pRCC_OscInitStruct->PLL.PLLFRACN); /* Enable PLL1FRACN */ - __HAL_RCC_PLLFRACN_ENABLE(); + __HAL_RCC_PLL_FRACN_ENABLE(); assert_param(IS_RCC_PLLRGE_VALUE(pRCC_OscInitStruct->PLL.PLLRGE)); @@ -1217,8 +1236,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) SET_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN); } - /*Disable PWR clk */ - __HAL_RCC_PWR_CLK_DISABLE(); + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } /* Enable PLL System Clock output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); @@ -1242,9 +1264,6 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) /* Disable the main PLL */ __HAL_RCC_PLL_DISABLE(); - /* Disable main PLL outputs to save power if no PLLs on */ - __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL1_DIVP | RCC_PLL1_DIVQ | RCC_PLL1_DIVR); - tickstart = HAL_GetTick(); /* Wait till PLL is disabled */ @@ -1255,11 +1274,57 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) return HAL_TIMEOUT; } } + + /* Unselect main PLL clock source and disable main PLL outputs to save power */ + RCC->PLL1CFGR &= ~(RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1PEN | RCC_PLL1CFGR_PLL1QEN | RCC_PLL1CFGR_PLL1REN); + } } else { - return HAL_ERROR; + /* Do not return HAL_ERROR if request repeats the current configuration */ + temp1_pllckcfg = RCC->PLL1CFGR; + temp2_pllckcfg = RCC->PLL1DIVR; + if (((pRCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(temp1_pllckcfg, RCC_PLL1CFGR_PLL1SRC) != pRCC_OscInitStruct->PLL.PLLSource) || + ((READ_BIT(temp1_pllckcfg, RCC_PLL1CFGR_PLL1M) >> \ + RCC_PLL1CFGR_PLL1M_Pos) != (pRCC_OscInitStruct->PLL.PLLM - 1U)) || + (READ_BIT(temp1_pllckcfg, RCC_PLL1CFGR_PLL1MBOOST) != pRCC_OscInitStruct->PLL.PLLMBOOST) || + (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1N) != (pRCC_OscInitStruct->PLL.PLLN - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1P) >> \ + RCC_PLL1DIVR_PLL1P_Pos) != (pRCC_OscInitStruct->PLL.PLLP - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1Q) >> \ + RCC_PLL1DIVR_PLL1Q_Pos) != (pRCC_OscInitStruct->PLL.PLLQ - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1R) >> \ + RCC_PLL1DIVR_PLL1R_Pos) != (pRCC_OscInitStruct->PLL.PLLR - 1U))) + { + return HAL_ERROR; + } + + /* FRACN1 on-the-fly value update */ + if ((READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN) >> \ + RCC_PLL1FRACR_PLL1FRACN_Pos) != (pRCC_OscInitStruct->PLL.PLLFRACN)) + { + assert_param(IS_RCC_PLL_FRACN_VALUE(pRCC_OscInitStruct->PLL.PLLFRACN)); + + /* Disable PLL1FRACN. */ + __HAL_RCC_PLL_FRACN_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait at least 2 CK_REF (PLL1 input source divided by M) period to make sure next latched value + will be taken into account. */ + while ((HAL_GetTick() - tickstart) < PLL_FRAC_WAIT_VALUE) + { + } + + /* Configure PLL PLL1FRACN */ + __HAL_RCC_PLL_FRACN_CONFIG(pRCC_OscInitStruct->PLL.PLLFRACN); + + /* Enable PLL1FRACN to latch the new value. */ + __HAL_RCC_PLL_FRACN_ENABLE(); + } } } return HAL_OK; @@ -1333,15 +1398,60 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_Clk } } + /* Increasing the BUS frequency divider */ + /*-------------------------- PCLK3 Configuration ---------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK3) == RCC_CLOCKTYPE_PCLK3) + { + if ((pRCC_ClkInitStruct->APB3CLKDivider) > (RCC->CFGR3 & RCC_CFGR3_PPRE3)) + { + assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, pRCC_ClkInitStruct->APB3CLKDivider); + } + } + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + if ((pRCC_ClkInitStruct->APB2CLKDivider) > ((RCC->CFGR2 & RCC_CFGR2_PPRE2) >> 4)) + { + assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, ((pRCC_ClkInitStruct->APB2CLKDivider) << 4)); + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + if ((pRCC_ClkInitStruct->APB1CLKDivider) > (RCC->CFGR2 & RCC_CFGR2_PPRE1)) + { + assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, pRCC_ClkInitStruct->APB1CLKDivider); + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + if ((pRCC_ClkInitStruct->AHBCLKDivider) > (RCC->CFGR2 & RCC_CFGR2_HPRE)) + { + assert_param(IS_RCC_HCLK(pRCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider); + } + } + /*------------------------- SYSCLK Configuration ---------------------------*/ if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) { assert_param(IS_RCC_SYSCLKSOURCE(pRCC_ClkInitStruct->SYSCLKSource)); + FlagStatus pwrclkchanged = RESET; /* PLL is selected as System Clock Source */ if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) { - __HAL_RCC_PWR_CLK_ENABLE(); + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } tickstart = HAL_GetTick(); /* Check if EPOD is enabled */ if (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) != 0U) @@ -1356,7 +1466,11 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_Clk } } - __HAL_RCC_PWR_CLK_DISABLE(); + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } /* Check the PLL ready flag */ if (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == 0U) @@ -1444,45 +1558,58 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_Clk } } + /* Decreasing the BUS frequency divider */ /*-------------------------- HCLK Configuration --------------------------*/ if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) { - assert_param(IS_RCC_HCLK(pRCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider); + if ((pRCC_ClkInitStruct->AHBCLKDivider) < (RCC->CFGR2 & RCC_CFGR2_HPRE)) + { + assert_param(IS_RCC_HCLK(pRCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider); + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { - assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB1CLKDivider)); - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, pRCC_ClkInitStruct->APB1CLKDivider); + if ((pRCC_ClkInitStruct->APB1CLKDivider) < (RCC->CFGR2 & RCC_CFGR2_PPRE1)) + { + assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, pRCC_ClkInitStruct->APB1CLKDivider); + } } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) { - assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB2CLKDivider)); - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, ((pRCC_ClkInitStruct->APB2CLKDivider) << 4)); + if ((pRCC_ClkInitStruct->APB2CLKDivider) < ((RCC->CFGR2 & RCC_CFGR2_PPRE2) >> 4)) + { + assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, ((pRCC_ClkInitStruct->APB2CLKDivider) << 4)); + } } /*-------------------------- PCLK3 Configuration ---------------------------*/ if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK3) == RCC_CLOCKTYPE_PCLK3) { - assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB3CLKDivider)); - MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, pRCC_ClkInitStruct->APB3CLKDivider); - } - - /* Decreasing the number of wait states because of lower CPU frequency */ - if (FLatency < __HAL_FLASH_GET_LATENCY()) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if (__HAL_FLASH_GET_LATENCY() != FLatency) + if ((pRCC_ClkInitStruct->APB3CLKDivider) < (RCC->CFGR3 & RCC_CFGR3_PPRE3)) { - return HAL_ERROR; + assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, (pRCC_ClkInitStruct->APB3CLKDivider)); } } @@ -1529,7 +1656,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_Clk * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLL1CLK main PLL clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source @@ -1751,6 +1878,10 @@ uint32_t HAL_RCC_GetPCLK3Freq(void) */ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) { + uint32_t regval; + uint32_t reg1val; + uint32_t reg2val; + /* Check the parameters */ assert_param(pRCC_OscInitStruct != (void *)NULL); @@ -1758,104 +1889,62 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) pRCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \ RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48; + /* Get Control register */ + regval = RCC->CR; + /* Get the HSE configuration -----------------------------------------------*/ - if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == RCC_CR_HSEBYP) - { - pRCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; - } - else if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) - { - pRCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_DIGITAL; - } - else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) - { - pRCC_OscInitStruct->HSEState = RCC_HSE_ON; - } - else - { - pRCC_OscInitStruct->HSEState = RCC_HSE_OFF; - } + pRCC_OscInitStruct->HSEState = (regval & (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_HSEEXT)); /* Get the MSI configuration -----------------------------------------------*/ - if ((RCC->CR & RCC_CR_MSISON) == RCC_CR_MSISON) - { - pRCC_OscInitStruct->MSIState = RCC_MSI_ON; - } - else - { - pRCC_OscInitStruct->MSIState = RCC_MSI_OFF; - } + pRCC_OscInitStruct->MSIState = regval & RCC_CR_MSISON; + + reg1val = RCC->ICSCR1; + reg2val = RCC->ICSCR2; - pRCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->CR & RCC_ICSCR1_MSISRANGE)); + pRCC_OscInitStruct->MSIClockRange = (uint32_t)((reg1val & RCC_ICSCR1_MSISRANGE)); if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_12) { - pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR2 & RCC_ICSCR2_MSITRIM3) >> \ + pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM3) >> \ RCC_ICSCR2_MSITRIM3_Pos); } else if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_8) { - pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR2 & RCC_ICSCR2_MSITRIM2) >> \ + pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM2) >> \ RCC_ICSCR2_MSITRIM2_Pos); } else if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_4) { - pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR2 & RCC_ICSCR2_MSITRIM1) >> \ + pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM1) >> \ RCC_ICSCR2_MSITRIM1_Pos); } else /*if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_0)*/ { - pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR2 & RCC_ICSCR2_MSITRIM0) >> \ + pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM0) >> \ RCC_ICSCR2_MSITRIM0_Pos); } - /* Get the HSI configuration -----------------------------------------------*/ - if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) - { - pRCC_OscInitStruct->HSIState = RCC_HSI_ON; - } - else - { - pRCC_OscInitStruct->HSIState = RCC_HSI_OFF; - } + /* Get the HSI configuration -----------------------------------------------*/ + pRCC_OscInitStruct->HSIState = regval & RCC_CR_HSION; pRCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR3 & RCC_ICSCR3_HSITRIM) >> RCC_ICSCR3_HSITRIM_Pos); + /* Get BDCR register */ + regval = RCC->BDCR; + /* Get the LSE configuration -----------------------------------------------*/ - if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) - { - pRCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; - } - else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) - { - pRCC_OscInitStruct->LSEState = RCC_LSE_ON; - } - else - { - pRCC_OscInitStruct->LSEState = RCC_LSE_OFF; - } + pRCC_OscInitStruct->LSEState = (regval & (RCC_BDCR_LSEON | RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSEN)); /* Get the LSI configuration -----------------------------------------------*/ - if ((RCC->BDCR & RCC_BDCR_LSION) == RCC_BDCR_LSION) - { - pRCC_OscInitStruct->LSIState = RCC_LSI_ON; - } - else - { - pRCC_OscInitStruct->LSIState = RCC_LSI_OFF; - } + pRCC_OscInitStruct->LSIState = regval & RCC_BDCR_LSION; + + /* Get Control register */ + regval = RCC->CR; /* Get the HSI48 configuration ---------------------------------------------*/ - if ((RCC->CR & RCC_CR_HSI48ON) == RCC_CR_HSI48ON) - { - pRCC_OscInitStruct->HSI48State = RCC_HSI48_ON; - } - else - { - pRCC_OscInitStruct->HSI48State = RCC_HSI48_OFF; - } + pRCC_OscInitStruct->HSI48State = regval & RCC_CR_HSI48ON; /* Get the PLL configuration -----------------------------------------------*/ - if ((RCC->CR & RCC_CR_PLL1ON) == RCC_CR_PLL1ON) + if ((regval & RCC_CR_PLL1ON) == RCC_CR_PLL1ON) { pRCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; } @@ -1863,17 +1952,21 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) { pRCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; } - pRCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); - pRCC_OscInitStruct->PLL.PLLM = (uint32_t)(((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U); - pRCC_OscInitStruct->PLL.PLLN = (uint32_t)(((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1U); - pRCC_OscInitStruct->PLL.PLLQ = (uint32_t)(((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1U); - pRCC_OscInitStruct->PLL.PLLR = (uint32_t)(((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U); - pRCC_OscInitStruct->PLL.PLLP = (uint32_t)(((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1U); - pRCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1RGE)); + + reg1val = RCC->PLL1CFGR; + reg2val = RCC->PLL1DIVR; + + pRCC_OscInitStruct->PLL.PLLSource = (uint32_t)(reg1val & RCC_PLL1CFGR_PLL1SRC); + pRCC_OscInitStruct->PLL.PLLM = (uint32_t)(((reg1val & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U); + pRCC_OscInitStruct->PLL.PLLN = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1U); + pRCC_OscInitStruct->PLL.PLLQ = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1U); + pRCC_OscInitStruct->PLL.PLLR = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U); + pRCC_OscInitStruct->PLL.PLLP = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1U); + pRCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((reg1val & RCC_PLL1CFGR_PLL1RGE)); pRCC_OscInitStruct->PLL.PLLFRACN = (uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \ RCC_PLL1FRACR_PLL1FRACN_Pos)); - pRCC_OscInitStruct->PLL.PLLMBOOST = (uint32_t)(((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1MBOOST) >> \ - RCC_PLL1CFGR_PLL1MBOOST_Pos) + 1U); + pRCC_OscInitStruct->PLL.PLLMBOOST = (uint32_t)(((reg1val & RCC_PLL1CFGR_PLL1MBOOST) >> \ + RCC_PLL1CFGR_PLL1MBOOST_Pos)); } /** @@ -2152,7 +2245,6 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) else { if (msirange > RCC_MSIRANGE_2) - { if (vos == PWR_REGULATOR_VOLTAGE_SCALE4) { @@ -2173,7 +2265,6 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) else { if (msirange == RCC_MSIRANGE_1) - { if (vos == PWR_REGULATOR_VOLTAGE_SCALE3) { diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rcc.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rcc.h index b1e1636a5e9..7d47c617cdf 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rcc.h @@ -60,21 +60,21 @@ typedef struct uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ - uint32_t PLLP; /*!< PLLP: Division factor for system clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 128 - odd division factors are not allowed */ + uint32_t PLLP; /*!< PLLP: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks. This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ - uint32_t PLLR; /*!< PLLR: Division factor for peripheral clocks. - This parameter must be a number between Min_Data = 2 and Max_Data = 128 */ + uint32_t PLLR; /*!< PLLR: Division factor for system clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 128 + Only division by 1 and even division factors are allowed */ uint32_t PLLRGE; /*!< PLLRGE: PLL1 clock Input range - This parameter must be a value of @ref RCC_PLL_VCI_Range */ + This parameter must be a value of @ref RCC_PLL_VCI_Range */ uint32_t PLLFRACN; /*!< PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for - PLL1 VCO It should be a value between 0 and 32767 */ + PLL1 VCO It should be a value between 0 and 8191 */ } RCC_PLLInitTypeDef; @@ -115,7 +115,7 @@ typedef struct This parameter can be a value of @ref RCC_MSI_Clock_Range */ uint32_t MSIKClockRange; /*!< The MSIK frequency range. - This parameter can be a value of @ref RCC_MSIk_Clock_Range */ + This parameter can be a value of @ref RCC_MSIK_Clock_Range */ uint32_t HSI48State; /*!< The new state of the HSI48. This parameter can be a value of @ref RCC_HSI48_Config */ @@ -323,12 +323,16 @@ typedef struct * @} */ + + + /** @defgroup RCC_PLL_Clock_Output RCC PLL Clock Output * @{ */ #define RCC_PLL1_DIVP RCC_PLL1CFGR_PLL1PEN #define RCC_PLL1_DIVQ RCC_PLL1CFGR_PLL1QEN #define RCC_PLL1_DIVR RCC_PLL1CFGR_PLL1REN + /** * @} */ @@ -365,6 +369,7 @@ typedef struct #define RCC_PLLSOURCE_MSI RCC_PLL1CFGR_PLL1SRC_0 #define RCC_PLLSOURCE_HSI RCC_PLL1CFGR_PLL1SRC_1 #define RCC_PLLSOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) + /** * @} */ @@ -394,26 +399,26 @@ typedef struct * @} */ -/** @defgroup RCC_MSIk_Clock_Range MSIK Clock Range +/** @defgroup RCC_MSIK_Clock_Range MSIK Clock Range * @{ */ -#define RCC_MSIKRANGE_0 0x00000000U /*!< MSIk = 48 MHz */ -#define RCC_MSIKRANGE_1 RCC_ICSCR1_MSIKRANGE_0 /*!< MSIk = 24 MHz */ -#define RCC_MSIKRANGE_2 RCC_ICSCR1_MSIKRANGE_1 /*!< MSIk = 16 MHz */ -#define RCC_MSIKRANGE_3 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1) /*!< MSIk = 12 MHz */ -#define RCC_MSIKRANGE_4 RCC_ICSCR1_MSIKRANGE_2 /*!< MSIk = 4 MHz */ -#define RCC_MSIKRANGE_5 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIk = 2 MHz */ -#define RCC_MSIKRANGE_6 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIk = 1.33 MHz */ -#define RCC_MSIKRANGE_7 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIk = 1 MHz */ -#define RCC_MSIKRANGE_8 RCC_ICSCR1_MSIKRANGE_3 /*!< MSIk = 3.072 MHz */ -#define RCC_MSIKRANGE_9 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 1.536 MHz */ -#define RCC_MSIKRANGE_10 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 1.024 MHz */ -#define RCC_MSIKRANGE_11 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 768 KHz */ -#define RCC_MSIKRANGE_12 (RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 400 KHz */ -#define RCC_MSIKRANGE_13 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 200 KHz */ -#define RCC_MSIKRANGE_14 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 133 KHz */ +#define RCC_MSIKRANGE_0 0x00000000U /*!< MSIK = 48 MHz */ +#define RCC_MSIKRANGE_1 RCC_ICSCR1_MSIKRANGE_0 /*!< MSIK = 24 MHz */ +#define RCC_MSIKRANGE_2 RCC_ICSCR1_MSIKRANGE_1 /*!< MSIK = 16 MHz */ +#define RCC_MSIKRANGE_3 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1) /*!< MSIK = 12 MHz */ +#define RCC_MSIKRANGE_4 RCC_ICSCR1_MSIKRANGE_2 /*!< MSIK = 4 MHz */ +#define RCC_MSIKRANGE_5 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 2 MHz */ +#define RCC_MSIKRANGE_6 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1.33 MHz */ +#define RCC_MSIKRANGE_7 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1 MHz */ +#define RCC_MSIKRANGE_8 RCC_ICSCR1_MSIKRANGE_3 /*!< MSIK = 3.072 MHz */ +#define RCC_MSIKRANGE_9 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.536 MHz */ +#define RCC_MSIKRANGE_10 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.024 MHz */ +#define RCC_MSIKRANGE_11 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 768 KHz */ +#define RCC_MSIKRANGE_12 (RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 400 KHz */ +#define RCC_MSIKRANGE_13 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 200 KHz */ +#define RCC_MSIKRANGE_14 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 133 KHz */ #define RCC_MSIKRANGE_15 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 |\ - RCC_ICSCR1_MSIKRANGE_3) /*!< MSIk = 100 KHz */ + RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 100 KHz */ /** * @} */ @@ -574,7 +579,6 @@ typedef struct #define RCC_FLAG_LSESYSRDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSESYSRDY_Pos)) /*!< LSESYS Ready flag */ #define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)) /*!< LSE Clock Security System Interrupt flag */ #define RCC_FLAG_LSIRDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSIRDY_Pos)) /*!< LSI Ready flag */ - /* Flags in the CSR register */ #define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_RMVF_Pos)) /*!< Remove reset flag */ #define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)) /*!< Option Byte Loader reset flag */ @@ -633,12 +637,12 @@ typedef struct #define RCC_PLL1 RCC_SECCFGR_PLL1SEC #define RCC_PLL2 RCC_SECCFGR_PLL2SEC #define RCC_PLL3 RCC_SECCFGR_PLL3SEC -#define RCC_CLK48M RCC_SECCFGR_CLK48MSEC +#define RCC_ICLK RCC_SECCFGR_ICLKSEC #define RCC_HSI48 RCC_SECCFGR_HSI48SEC #define RCC_RMVF RCC_SECCFGR_RMVFSEC #define RCC_ALL (RCC_HSI|RCC_HSE|RCC_MSI|RCC_LSI|RCC_LSE|RCC_HSI48| \ RCC_SYSCLK|RCC_PRESC|RCC_PLL1|RCC_PLL2| \ - RCC_PLL3|RCC_CLK48M|RCC_RMVF) + RCC_PLL3|RCC_ICLK|RCC_RMVF) /** * @} */ @@ -673,49 +677,60 @@ typedef struct #define __HAL_RCC_GPDMA1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_FMAC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_TSC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_CRC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ UNUSED(tmpreg); \ } while(0) + +#if defined(JPEG) +#define __HAL_RCC_JPEG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* JPEG */ + #define __HAL_RCC_RAMCFG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ UNUSED(tmpreg); \ } while(0) @@ -723,23 +738,55 @@ typedef struct #define __HAL_RCC_MDF1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \ UNUSED(tmpreg); \ } while(0) +#if defined(DMA2D) #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ UNUSED(tmpreg); \ } while(0) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GPU2D */ + +#if defined(DCACHE2) +#define __HAL_RCC_DCACHE2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* DCACHE2 */ #define __HAL_RCC_GTZC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \ UNUSED(tmpreg); \ } while(0) @@ -747,7 +794,7 @@ typedef struct #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); \ UNUSED(tmpreg); \ } while(0) @@ -755,7 +802,7 @@ typedef struct #define __HAL_RCC_DCACHE1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ UNUSED(tmpreg); \ } while(0) @@ -763,12 +810,12 @@ typedef struct #define __HAL_RCC_SRAM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) +#define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) #define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) @@ -780,11 +827,29 @@ typedef struct #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) +#if defined(JPEG) +#define __HAL_RCC_JPEG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN) +#endif /* JPEG */ + #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) #define __HAL_RCC_RAMCFG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) +#if defined(DMA2D) #define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN) +#endif /* GPU2D */ + +#if defined(DCACHE2) +#define __HAL_RCC_DCACHE2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN) +#endif /* DCACHE2 */ #define __HAL_RCC_GTZC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) @@ -807,7 +872,7 @@ typedef struct #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN); \ UNUSED(tmpreg); \ } while(0) @@ -815,7 +880,7 @@ typedef struct #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN); \ UNUSED(tmpreg); \ } while(0) @@ -823,7 +888,7 @@ typedef struct #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN); \ UNUSED(tmpreg); \ } while(0) @@ -831,7 +896,7 @@ typedef struct #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN); \ UNUSED(tmpreg); \ } while(0) @@ -839,23 +904,25 @@ typedef struct #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN); \ UNUSED(tmpreg); \ } while(0) +#if defined(GPIOF) #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN); \ UNUSED(tmpreg); \ } while(0) +#endif /* GPIOF */ #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN); \ UNUSED(tmpreg); \ } while(0) @@ -863,48 +930,84 @@ typedef struct #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN); \ UNUSED(tmpreg); \ } while(0) +#if defined (GPIOI) #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN); \ UNUSED(tmpreg); \ } while(0) +#endif /* GPIOI */ -#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN); \ - UNUSED(tmpreg); \ - } while(0) +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN); \ + UNUSED(tmpreg); \ + } while(0) + +#endif /* GPIOJ */ + +#define __HAL_RCC_ADC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN); \ + UNUSED(tmpreg); \ + } while(0) -#define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \ +#define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN); \ UNUSED(tmpreg); \ } while(0) +#if defined (USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* USB_OTG_HS */ +#if defined(USB_OTG_FS) #define __HAL_RCC_USB_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ UNUSED(tmpreg); \ } while(0) +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE /*!< alias define for compatibility with legacy code */ +#endif /* defined (USB_OTG_FS) */ + +#if defined(RCC_AHB2ENR1_USBPHYCEN) +#define __HAL_RCC_USBPHYC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_USBPHYCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_USBPHYCEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* defined (RCC_AHB2ENR1_USBPHYCEN) */ + #if defined(AES) #define __HAL_RCC_AES_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN); \ UNUSED(tmpreg); \ } while(0) @@ -914,7 +1017,7 @@ typedef struct #define __HAL_RCC_HASH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN); \ UNUSED(tmpreg); \ } while(0) @@ -923,7 +1026,7 @@ typedef struct #define __HAL_RCC_RNG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN); \ UNUSED(tmpreg); \ } while(0) @@ -931,98 +1034,111 @@ typedef struct #define __HAL_RCC_PKA_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN); \ UNUSED(tmpreg); \ } while(0) +#if defined(SAES) #define __HAL_RCC_SAES_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN); \ UNUSED(tmpreg); \ } while(0) +#endif /* SAES */ +#if defined(OCTOSPIM) #define __HAL_RCC_OSPIM_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN); \ UNUSED(tmpreg); \ } while(0) +#endif /* OCTOSPIM */ #define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN); \ UNUSED(tmpreg); \ } while(0) +#if defined(OTFDEC2) #define __HAL_RCC_OTFDEC2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* OTFDEC2 */ #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN); \ UNUSED(tmpreg); \ } while(0) +#if defined(SDMMC2) #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* SDMMC2 */ #define __HAL_RCC_SRAM2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN); \ UNUSED(tmpreg); \ } while(0) - +#if defined(SRAM3_BASE) #define __HAL_RCC_SRAM3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* SRAM3_BASE */ +#if defined(FMC_BASE) #define __HAL_RCC_FMC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN); \ UNUSED(tmpreg); \ } while(0) +#endif /* FMC_BASE */ #define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN); \ UNUSED(tmpreg); \ } while(0) +#if defined(OCTOSPI2) #define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* OCTOSPI2 */ #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) @@ -1034,19 +1150,38 @@ typedef struct #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) +#if defined(GPIOF) #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) +#endif /* GPIOF */ #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) +#if defined(GPIOI) #define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) +#endif /* GPIOI */ + +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN) +#endif /* GPIOJ */ -#define __HAL_RCC_ADC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN) +#define __HAL_RCC_ADC12_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN) #define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE /*!< alias define for compatibility with legacy code */ +#endif /* USB_OTG_FS */ + +#if defined(RCC_AHB2ENR1_USBPHYCEN) +#define __HAL_RCC_USBPHYC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_USBPHYCEN) +#endif /* defined (RCC_AHB2ENR1_USBPHYCEN) */ #if defined(AES) #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) @@ -1060,27 +1195,83 @@ typedef struct #define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) +#if defined(SAES) #define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) +#endif /* SAES */ +#if defined(OCTOSPIM) #define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) +#endif /* OCTOSPIM */ #define __HAL_RCC_OTFDEC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) +#if defined(OTFDEC2) #define __HAL_RCC_OTFDEC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) +#endif /* OTFDEC2 */ #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) +#if defined(SDMMC2) #define __HAL_RCC_SDMMC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) +#endif /* SDMMC2 */ #define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) +#if defined(SRAM3_BASE) #define __HAL_RCC_SRAM3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) +#endif /* SRAM3_BASE */ + +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* HSPI1 */ + +#if defined (SRAM6_BASE) +#define __HAL_RCC_SRAM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SRAM6_BASE */ + +#if defined (SRAM5_BASE) +#define __HAL_RCC_SRAM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SRAM5_BASE */ +#if defined(FMC_BASE) #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) +#endif /* FMC_BASE */ #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) +#if defined(OCTOSPI2) #define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) +#endif /* OCTOSPI2 */ + +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN) +#endif /* HSPI1 */ + +#if defined (SRAM6_BASE) +#define __HAL_RCC_SRAM6_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN) +#endif /* SRAM6_BASE */ + +#if defined (SRAM5_BASE) +#define __HAL_RCC_SRAM5_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN) +#endif /* SRAM5_BASE */ /** * @} */ @@ -1102,55 +1293,55 @@ typedef struct #define __HAL_RCC_APB3_CLK_DISABLE() SET_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); -#define __HAL_RCC_AHB1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ - tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_AHB2_1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \ - tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_AHB2_2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \ - tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \ - UNUSED(tmpreg); \ - } while(0) - - -#define __HAL_RCC_AHB3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \ - tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_APB1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ - tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_APB2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ - tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_APB3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \ - tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_AHB1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_AHB2_1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \ + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_AHB2_2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \ + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_AHB3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \ + tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_APB1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_APB2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_APB3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \ + tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \ + UNUSED(tmpreg); \ + } while(0) /** * @} @@ -1163,10 +1354,11 @@ typedef struct * using it. * @{ */ + #define __HAL_RCC_LPGPIO1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \ UNUSED(tmpreg); \ } while(0) @@ -1174,7 +1366,7 @@ typedef struct #define __HAL_RCC_PWR_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \ UNUSED(tmpreg); \ } while(0) @@ -1182,7 +1374,7 @@ typedef struct #define __HAL_RCC_ADC4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \ UNUSED(tmpreg); \ } while(0) @@ -1190,7 +1382,7 @@ typedef struct #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \ UNUSED(tmpreg); \ } while(0) @@ -1198,7 +1390,7 @@ typedef struct #define __HAL_RCC_LPDMA1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \ UNUSED(tmpreg); \ } while(0) @@ -1206,7 +1398,7 @@ typedef struct #define __HAL_RCC_ADF1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN); \ UNUSED(tmpreg); \ } while(0) @@ -1214,7 +1406,7 @@ typedef struct #define __HAL_RCC_GTZC2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN); \ UNUSED(tmpreg); \ } while(0) @@ -1222,7 +1414,7 @@ typedef struct #define __HAL_RCC_SRAM4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN); \ UNUSED(tmpreg); \ } while(0) @@ -1242,6 +1434,7 @@ typedef struct #define __HAL_RCC_GTZC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) #define __HAL_RCC_SRAM4_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) + /** * @} */ @@ -1253,10 +1446,11 @@ typedef struct * using it. * @{ */ + #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ UNUSED(tmpreg); \ } while(0) @@ -1264,7 +1458,7 @@ typedef struct #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ UNUSED(tmpreg); \ } while(0) @@ -1272,7 +1466,7 @@ typedef struct #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ UNUSED(tmpreg); \ } while(0) @@ -1280,7 +1474,7 @@ typedef struct #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ UNUSED(tmpreg); \ } while(0) @@ -1288,7 +1482,7 @@ typedef struct #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ UNUSED(tmpreg); \ } while(0) @@ -1296,7 +1490,7 @@ typedef struct #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ UNUSED(tmpreg); \ } while(0) @@ -1304,7 +1498,7 @@ typedef struct #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ UNUSED(tmpreg); \ } while(0) @@ -1312,23 +1506,25 @@ typedef struct #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ UNUSED(tmpreg); \ } while(0) +#if defined(USART2) #define __HAL_RCC_USART2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* USART2 */ #define __HAL_RCC_USART3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ UNUSED(tmpreg); \ } while(0) @@ -1336,7 +1532,7 @@ typedef struct #define __HAL_RCC_UART4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ UNUSED(tmpreg); \ } while(0) @@ -1344,7 +1540,7 @@ typedef struct #define __HAL_RCC_UART5_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ UNUSED(tmpreg); \ } while(0) @@ -1352,7 +1548,7 @@ typedef struct #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ UNUSED(tmpreg); \ } while(0) @@ -1360,7 +1556,7 @@ typedef struct #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ UNUSED(tmpreg); \ } while(0) @@ -1368,52 +1564,77 @@ typedef struct #define __HAL_RCC_CRS_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_I2C4_CLK_ENABLE() do { \ + +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* USART6 */ -#define __HAL_RCC_DTS_CLK_ENABLE() do { \ +#define __HAL_RCC_I2C4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN); \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ UNUSED(tmpreg); \ } while(0) +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* I2C6 */ + #define __HAL_RCC_FDCAN1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ UNUSED(tmpreg); \ } while(0) +#if defined(UCPD1) #define __HAL_RCC_UCPD_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* UCPD1 */ -#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) +#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) @@ -1425,11 +1646,11 @@ typedef struct #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) -#define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) - #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) +#if defined(USART2) #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) +#endif /* USART2 */ #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) @@ -1443,15 +1664,28 @@ typedef struct #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) -#define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN) +#endif /* USART6 */ -#define __HAL_RCC_DTS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2 , RCC_APB1ENR2_DTSEN) +#define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN) +#endif /* I2C6 */ + #define __HAL_RCC_FDCAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) +#if defined(UCPD1) #define __HAL_RCC_UCPD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) +#endif /* UCPD1 */ + /** * @} */ @@ -1463,78 +1697,120 @@ typedef struct * using it. * @{ */ -#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ + UNUSED(tmpreg); \ + } while(0) -#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ + UNUSED(tmpreg); \ + } while(0) -#define __HAL_RCC_USART1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ - UNUSED(tmpreg); \ - } while(0) -#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ + UNUSED(tmpreg); \ + } while(0) -#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ + UNUSED(tmpreg); \ + } while(0) -#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ + UNUSED(tmpreg); \ + } while(0) -#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ +#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_SAI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined (SAI2) +#define __HAL_RCC_SAI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SAI2 */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_FS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* DSI */ #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) @@ -1552,7 +1828,26 @@ typedef struct #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) +#if defined (SAI2) #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) +#endif /* SAI2 */ + +#if defined (USB_DRD_FS) +#define __HAL_RCC_USB_FS_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN) +#endif /* DSI */ + /** * @} */ @@ -1567,7 +1862,7 @@ typedef struct #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN); \ UNUSED(tmpreg); \ } while(0) @@ -1575,7 +1870,7 @@ typedef struct #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN); \ UNUSED(tmpreg); \ } while(0) @@ -1583,7 +1878,7 @@ typedef struct #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ UNUSED(tmpreg); \ } while(0) @@ -1591,7 +1886,7 @@ typedef struct #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ UNUSED(tmpreg); \ } while(0) @@ -1599,7 +1894,7 @@ typedef struct #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ UNUSED(tmpreg); \ } while(0) @@ -1607,7 +1902,7 @@ typedef struct #define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ UNUSED(tmpreg); \ } while(0) @@ -1615,7 +1910,7 @@ typedef struct #define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ UNUSED(tmpreg); \ } while(0) @@ -1623,7 +1918,7 @@ typedef struct #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN); \ UNUSED(tmpreg); \ } while(0) @@ -1631,7 +1926,7 @@ typedef struct #define __HAL_RCC_COMP_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN); \ UNUSED(tmpreg); \ } while(0) @@ -1639,7 +1934,7 @@ typedef struct #define __HAL_RCC_VREF_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ UNUSED(tmpreg); \ } while(0) @@ -1647,7 +1942,7 @@ typedef struct #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ - /* Delay after an RCC peripheral clock enabling */ \ + /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ UNUSED(tmpreg); \ } while(0) @@ -1696,11 +1991,29 @@ typedef struct #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) +#if defined(JPEG) +#define __HAL_RCC_JPEG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN) != 0U) +#endif /* JPEG */ + #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U) #define __HAL_RCC_RAMCFG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) != 0U) +#if defined(DMA2D) #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != 0U) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != 0U) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN) != 0U) +#endif /* GPU2D */ + +#if defined(DCACHE2) +#define __HAL_RCC_DCACHE2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN) != 0U) +#endif /* DCACHE2 */ #define __HAL_RCC_GTZC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) != 0U) @@ -1710,7 +2023,7 @@ typedef struct #define __HAL_RCC_SRAM1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) != 0U) -#define __HAL_RCC_GPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) == 0U) +#define __HAL_RCC_GPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) == 0U) #define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U) @@ -1722,11 +2035,29 @@ typedef struct #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) +#if defined(JPEG) +#define __HAL_RCC_JPEG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN) == 0U) +#endif /* JPEG */ + #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U) #define __HAL_RCC_RAMCFG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) == 0U) +#if defined (DMA2D) #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == 0U) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == 0U) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN) == 0U) +#endif /* GPU2D */ + +#if defined(DCACHE2) +#define __HAL_RCC_DCACHE2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN) == 0U) +#endif /* DCACHE2 */ #define __HAL_RCC_GTZC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) == 0U) @@ -1756,19 +2087,34 @@ typedef struct #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) != 0U) +#if defined(GPIOF) #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) != 0U) +#endif /* GPIOF */ #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) != 0U) #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) != 0U) +#if defined(GPIOI) #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) != 0U) +#endif /* GPIOI */ + +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN) != 0U) +#endif /* GPIOJ */ -#define __HAL_RCC_ADC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN) != 0U) +#define __HAL_RCC_ADC12_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN) != 0U) #define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) != 0U) +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) != 0U) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) != 0U) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED /*!< alias define for compatibility with legacy code */ +#endif /* USB_OTG_FS */ #if defined(AES) #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) != 0U) @@ -1782,27 +2128,53 @@ typedef struct #define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) != 0U) -#define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) != 0U) +#if defined(SAES) +#define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) != 0U) +#endif /* SAES */ +#if defined(OCTOSPIM) #define __HAL_RCC_OSPIM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) != 0U) +#endif /* OCTOSPIM */ #define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) != 0U) +#if defined(OTFDEC2) #define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) != 0U) +#endif /* OTFDEC2 */ #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) != 0U) +#if defined(SDMMC2) #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) != 0U) +#endif /* SDMMC2 */ -#define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) != 0U) +#define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) != 0U) -#define __HAL_RCC_SRAM3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) != 0U) +#if defined (SRAM3_BASE) +#define __HAL_RCC_SRAM3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) != 0U) +#endif /* SRAM3_BASE */ +#if defined(FMC_BASE) #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) != 0U) +#endif /* FMC_BASE */ + +#define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) != 0U) + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) != 0U) +#endif /* OCTOSPI2 */ -#define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) != 0U) +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2,RCC_AHB2ENR2_HSPI1EN) != 0U) +#endif /* HSPI1 */ -#define __HAL_RCC_OSPI2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) != 0U) +#if defined (SRAM6_BASE) +#define __HAL_RCC_SRAM6_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN) != 0U) +#endif /* SRAM6_BASE */ + +#if defined (SRAM5_BASE) +#define __HAL_RCC_SRAM5_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN) != 0U) +#endif /* SRAM5_BASE */ #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) == 0U) @@ -1814,19 +2186,34 @@ typedef struct #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) == 0U) +#if defined(GPIOF) #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) == 0U) +#endif /* GPIOF */ #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) == 0U) #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) == 0U) +#if defined(GPIOI) #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) == 0U) +#endif /* GPIOI */ + +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN) == 0U) +#endif /* GPIOJ */ -#define __HAL_RCC_ADC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC1EN) == 0U) +#define __HAL_RCC_ADC12_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN) == 0U) #define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) == 0U) +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) == 0U) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) == 0U) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED /*!< alias define for compatibility with legacy code */ +#endif /* USB_OTG_FS */ #if defined(AES) #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) == 0U) @@ -1840,27 +2227,53 @@ typedef struct #define __HAL_RCC_PKA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) == 0U) +#if defined(SAES) #define __HAL_RCC_SAES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) == 0U) +#endif /* SAES */ +#if defined(OCTOSPIM) #define __HAL_RCC_OSPIM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) == 0U) +#endif /* OCTOSPIM */ #define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) == 0U) +#if defined (OTFDEC2) #define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) == 0U) +#endif /* OTFDEC2 */ #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) == 0U) +#if defined (SDMMC2) #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) == 0U) +#endif /* SDMMC2 */ #define __HAL_RCC_SRAM2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) == 0U) +#if defined (SRAM3_BASE) #define __HAL_RCC_SRAM3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) == 0U) +#endif /* SRAM3_BASE */ + +#if defined(FMC_BASE) +#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) == 0U) +#endif /* FMC_BASE */ + +#define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) == 0U) -#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) == 0U) +#if defined (OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) == 0U) +#endif /* OCTOSPI2 */ -#define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) == 0U) +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN) == 0U) +#endif /* HSPI1 */ -#define __HAL_RCC_OSPI2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) == 0U) +#if defined (SRAM6_BASE) +#define __HAL_RCC_SRAM6_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN) == 0U) +#endif /* SRAM6_BASE */ + +#if defined (SRAM5_BASE) +#define __HAL_RCC_SRAM5_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN) == 0U) +#endif /* SRAM5_BASE */ /** * @} */ @@ -1903,6 +2316,7 @@ typedef struct #define __HAL_RCC_GTZC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) == 0U) #define __HAL_RCC_SRAM4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) == 0U) + /** * @} */ @@ -1930,7 +2344,9 @@ typedef struct #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U) +#if defined(USART2) #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) +#endif /* USART2 */ #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U) @@ -1944,15 +2360,27 @@ typedef struct #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U) -#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U) +#if defined(USART6) +#define __HAL_RCC_USART6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN) != 0U) +#endif /* USART6 */ -#define __HAL_RCC_DTS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN) != 0U) +#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U) #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U) +#if defined(I2C5) +#define __HAL_RCC_I2C5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN) != 0U) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN) != 0U) +#endif /* I2C6 */ + #define __HAL_RCC_FDCAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) != 0U) +#if defined (UCPD1) #define __HAL_RCC_UCPD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U) +#endif /* UCPD1 */ #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U) @@ -1968,7 +2396,9 @@ typedef struct #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U) +#if defined(USART2) #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U) +#endif /* USART2 */ #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U) @@ -1982,15 +2412,28 @@ typedef struct #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U) -#define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U) +#if defined(USART6) +#define __HAL_RCC_USART6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN) == 0U) +#endif /* USART6 */ -#define __HAL_RCC_DTS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_DTSEN) == 0U) +#define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U) #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U) +#if defined(I2C5) +#define __HAL_RCC_I2C5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN) == 0U) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN) == 0U) +#endif /* I2C6 */ + #define __HAL_RCC_FDCAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) == 0U) +#if defined(UCPD1) #define __HAL_RCC_UCPD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U) +#endif /* UCPD1 */ + /** * @} */ @@ -2002,6 +2445,7 @@ typedef struct * using it. * @{ */ + #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) @@ -2018,7 +2462,25 @@ typedef struct #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) +#if defined (SAI2) #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U) +#endif /* SAI2 */ + +#if defined (USB_DRD_FS) +#define __HAL_RCC_USB_FS_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) != 0U) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) != 0U) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != 0U) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN) != 0U) +#endif /* DSI */ #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) @@ -2036,7 +2498,26 @@ typedef struct #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) +#if defined (SAI2) #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U) +#endif /* SAI2 */ + +#if defined (USB_DRD_FS) +#define __HAL_RCC_USB_FS_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) == 0U) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) == 0U) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == 0U) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN) == 0U) +#endif /* DSI */ + /** * @} */ @@ -2101,7 +2582,7 @@ typedef struct */ #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x0007100FU) -#define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) +#define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) #define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) @@ -2111,15 +2592,29 @@ typedef struct #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) +#if defined(JPEG) +#define __HAL_RCC_JPEG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_JPEGRST) +#endif /* JPEG */ + #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) #define __HAL_RCC_RAMCFG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) +#if defined(DMA2D) #define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPU2DRST) +#endif /* GPU2D */ #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) -#define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) +#define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) #define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) @@ -2129,11 +2624,26 @@ typedef struct #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) +#if defined(JPEG) +#define __HAL_RCC_JPEG_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_JPEGRST) +#endif /* JPEG */ + #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) #define __HAL_RCC_RAMCFG_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) +#if defined(DMA2D) #define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPU2DRST) +#endif /* GPU2D */ + /** * @} */ @@ -2142,115 +2652,182 @@ typedef struct * @brief Force or release AHB2 peripheral reset. * @{ */ -#define __HAL_RCC_AHB2_FORCE_RESET() do{\ - WRITE_REG(RCC->AHB2RSTR1, 0x19BF55FFU);\ - WRITE_REG(RCC->AHB2RSTR2, 0x00000111U);\ - }while(0) +#define __HAL_RCC_AHB2_FORCE_RESET() do{\ + WRITE_REG(RCC->AHB2RSTR1, 0x19BF55FFU);\ + WRITE_REG(RCC->AHB2RSTR2, 0x00000111U);\ + }while(0) + +#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST) + +#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST) + +#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST) + +#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST) -#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST) +#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST) -#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST) +#if defined(GPIOF) +#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST) +#endif /* GPIOF */ -#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST) +#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST) -#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST) +#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST) -#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST) +#endif /* GPIOI */ -#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST) +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOJRST) +#endif /* GPIOJ */ -#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST) +#define __HAL_RCC_ADC12_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC12RST) -#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST) +#define __HAL_RCC_DCMI_PSSI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST) -#define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST) +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) +#endif /* USB_OTG_HS */ -#define __HAL_RCC_ADC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC1RST) +#if defined(USB_OTG_FS) +#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_FORCE_RESET /*!< alias define for compatibility with legacy code */ +#endif /* USB_OTG_FS */ -#define __HAL_RCC_DCMI_PSSI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST) +#if defined(AES) +#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST) +#endif /* AES */ + +#define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST) + +#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST) -#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) +#define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST) -#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST) +#if defined(SAES) +#define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST) +#endif /* SAES */ -#define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST) +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST) +#endif /* OCTOSPIM */ -#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST) +#define __HAL_RCC_OTFDEC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST) -#define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST) +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST) +#endif /* OTFDEC2 */ -#define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST) +#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST) -#define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST) +#if defined(SDMMC2) +#define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST) +#endif /* SDMMC2 */ -#define __HAL_RCC_OTFDEC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST) +#if defined(FMC_BASE) +#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST) +#endif /* FMC_BASE */ -#define __HAL_RCC_OTFDEC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST) +#define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST) -#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST) +#if defined (OCTOSPI2) +#define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST) +#endif /* OCTOSPI2 */ -#define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST) +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_HSPI1RST) +#endif /* HSPI1 */ -#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST) +#define __HAL_RCC_AHB2_RELEASE_RESET() do{\ + WRITE_REG(RCC->AHB2RSTR1, 0x00000000U);\ + WRITE_REG(RCC->AHB2RSTR2, 0x00000000U);\ + }while(0) -#define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST) +#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST) -#define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST) +#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST) -#define __HAL_RCC_AHB2_RELEASE_RESET() do{\ - WRITE_REG(RCC->AHB2RSTR1, 0x00000000U);\ - WRITE_REG(RCC->AHB2RSTR2, 0x00000000U);\ - }while(0) +#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST) -#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST) +#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST) -#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST) +#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST) -#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST) +#if defined(GPIOF) +#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST) +#endif /* GPIOF */ -#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST) +#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST) -#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST) +#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST) -#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST) +#endif /* GPIOI */ -#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST) +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOJRST) +#endif /* GPIOJ */ -#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST) +#define __HAL_RCC_ADC12_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC12RST) -#define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST) +#define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST) -#define __HAL_RCC_ADC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC1RST) +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) +#endif /* USB_OTG_HS */ -#define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST) +#if defined(USB_OTG_FS) +#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET /*!< alias define for compatibility with legacy code */ +#endif /* USB_OTG_FS */ + +#if defined(AES) +#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST) +#endif /* AES */ -#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) +#define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST) -#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST) +#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST) -#define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST) +#define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST) -#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST) +#if defined(SAES) +#define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST) +#endif /* SAES */ -#define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST) +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST) +#endif /* OCTOSPIM */ -#define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST) +#define __HAL_RCC_OTFDEC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST) -#define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST) +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST) +#endif /* OTFDEC2 */ -#define __HAL_RCC_OTFDEC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST) +#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST) -#define __HAL_RCC_OTFDEC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST) +#if defined(SDMMC2) +#define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST) +#endif /* SDMMC2 */ -#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST) +#if defined(FMC_BASE) +#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST) +#endif /* FMC_BASE */ -#define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST) +#define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST) -#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST) +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST) +#endif /* OCTOSPI2 */ -#define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST) +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_HSPI1RST) +#endif /* HSPI1 */ -#define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST) /** * @} */ @@ -2282,13 +2859,16 @@ typedef struct #define __HAL_RCC_LPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPDMA1RST) #define __HAL_RCC_ADF1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADF1RST) + /** * @} */ + /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset * @brief Force or release APB1 peripheral reset. * @{ */ + #define __HAL_RCC_APB1_FORCE_RESET() do { \ WRITE_REG(RCC->APB1RSTR1, 0x027E403FU); \ WRITE_REG(RCC->APB1RSTR2, 0x00800222U); \ @@ -2308,7 +2888,9 @@ typedef struct #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) +#if defined (USART2) #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) +#endif /* USART2 */ #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) @@ -2322,13 +2904,27 @@ typedef struct #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) +#if defined(USART6) +#define __HAL_RCC_USART6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART6RST) +#endif /* USART6 */ + #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) +#if defined(I2C5) +#define __HAL_RCC_I2C5_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C5RST) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C6RST) +#endif /* I2C6 */ + #define __HAL_RCC_FDCAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST) +#if defined(UCPD1) #define __HAL_RCC_UCPD_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) +#endif /* UCPD1 */ #define __HAL_RCC_APB1_RELEASE_RESET() do { \ WRITE_REG(RCC->APB1RSTR1, 0x00000000U); \ @@ -2349,7 +2945,9 @@ typedef struct #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) +#if defined(USART2) #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) +#endif /* USART2 */ #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) @@ -2363,13 +2961,28 @@ typedef struct #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) +#if defined(USART6) +#define __HAL_RCC_USART6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART6RST) +#endif /* USART6 */ + #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) +#if defined(I2C5) +#define __HAL_RCC_I2C5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C5RST) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C6RST) +#endif /* I2C6 */ + #define __HAL_RCC_FDCAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST) +#if defined(UCPD1) #define __HAL_RCC_UCPD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) +#endif /* UCPD1 */ + /** * @} */ @@ -2396,7 +3009,25 @@ typedef struct #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) +#if defined(SAI2) #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) +#endif /* SAI2 */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_FS_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_GFXTIMRST) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIHOSTRST) +#endif /* DSI */ #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) @@ -2416,7 +3047,26 @@ typedef struct #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) +#if defined(SAI2) #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) +#endif /* SAI2 */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_FS_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_GFXTIMRST) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIHOSTRST) +#endif /* DSI */ + /** * @} */ @@ -2468,6 +3118,7 @@ typedef struct #define __HAL_RCC_COMP_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_COMPRST) #define __HAL_RCC_VREF_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) + /** * @} */ @@ -2493,11 +3144,29 @@ typedef struct #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) +#if defined(JPEG) +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_JPEGSMEN) +#endif /* JPEG */ + #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) #define __HAL_RCC_RAMCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) +#if defined(DMA2D) #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPU2DSMEN) +#endif /* GPU2D */ + +#if defined(DCACHE2) +#define __HAL_RCC_DCACHE2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE2SMEN) +#endif /* DCACHE2 */ #define __HAL_RCC_GTZC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) @@ -2521,11 +3190,29 @@ typedef struct #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) +#if defined(JPEG) +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_JPEGSMEN) +#endif /* JPEG */ + #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) #define __HAL_RCC_RAMCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) +#if defined(DMA2D) #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPU2DSMEN) +#endif /* GPU2D */ + +#if defined(DCACHE2) +#define __HAL_RCC_DCACHE2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE2SMEN) +#endif /* DCACHE2 */ #define __HAL_RCC_GTZC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) @@ -2533,9 +3220,10 @@ typedef struct #define __HAL_RCC_ICACHE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) -#define __HAL_RCC_DCACHE1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE1SMEN) +#define __HAL_RCC_DCACHE1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE1SMEN) #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) + /** * @} */ @@ -2559,22 +3247,41 @@ typedef struct #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOESMEN) +#if defined(GPIOF) #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOFSMEN) +#endif /* GPIOF */ #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOGSMEN) #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOHSMEN) +#if defined(GPIOI) #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOISMEN) +#endif /* GPIOI */ -#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC1SMEN) +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOJSMEN) +#endif /* GPIOJ */ + +#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC12SMEN) #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_DCMI_PSSISMEN) +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE /*!< alias define for compatibility with legacy code */ +#endif /* USB_OTG_FS */ + +#if defined(RCC_AHB2SMENR1_USBPHYCSMEN) +#define __HAL_RCC_USBPHYCCLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_USBPHYCSMEN) +#endif /* RCC_AHB2SMENR1_USBPHYCSMEN */ #if defined(AES) -#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN); +#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN) #endif /* AES */ #if defined(HASH) @@ -2585,27 +3292,53 @@ typedef struct #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_PKASMEN) +#if defined(SAES) #define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SAESSMEN) +#endif /* SAES */ +#if defined(OCTOSPIM) #define __HAL_RCC_OCTOSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OCTOSPIMSMEN) +#endif /* OCTOSPIM */ #define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC1SMEN) +#if defined(OTFDEC2) #define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC2SMEN) +#endif /* OTFDEC2 */ #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC1SMEN) +#if defined(SDMMC2) #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC2SMEN) +#endif /* SDMMC2 */ #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM2SMEN) +#if defined(SRAM3_BASE) #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM3SMEN) +#endif /* SRAM3_BASE */ +#if defined(FMC_BASE) #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_FSMCSMEN) +#endif /* FMC_BASE */ #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI1SMEN) +#if defined(OCTOSPI2) #define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI2SMEN) +#endif /* OCTOSPI2 */ + +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_HSPI1SMEN) +#endif /* HSPI1 */ + +#if defined(SRAM6_BASE) +#define __HAL_RCC_SRAM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM6SMEN) +#endif /* SRAM6_BASE */ + +#if defined(SRAM5_BASE) +#define __HAL_RCC_SRAM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM5SMEN) +#endif /* SRAM5_BASE */ #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOASMEN) @@ -2617,22 +3350,41 @@ typedef struct #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOESMEN) +#if defined(GPIOF) #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOFSMEN) +#endif /* GPIOF */ #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOGSMEN) #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOHSMEN) +#if defined(GPIOI) #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOISMEN) +#endif /* GPIOI */ + +#if defined(GPIOJ) +#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOJSMEN) +#endif /* GPIOJ */ -#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC1SMEN) +#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC12SMEN) #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_DCMI_PSSISMEN) +#if defined(USB_OTG_HS) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) +#endif /* USB_OTG_HS */ + +#if defined(USB_OTG_FS) #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE /*!< alias define for compatibility with legacy code */ +#endif /* USB_OTG_FS */ + +#if defined(RCC_AHB2SMENR1_USBPHYCSMEN) +#define __HAL_RCC_USBPHYCCLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_USBPHYCSMEN) +#endif /* RCC_AHB2SMENR1_USBPHYCSMEN */ #if defined(AES) -#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN); +#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN) #endif /* AES */ #if defined(HASH) @@ -2643,27 +3395,54 @@ typedef struct #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_PKASMEN) +#if defined(SAES) #define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SAESSMEN) +#endif /* SAES */ +#if defined(OCTOSPIM) #define __HAL_RCC_OCTOSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OCTOSPIMSMEN) +#endif /* OCTOSPIM */ #define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC1SMEN) +#if defined(OTFDEC2) #define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC2SMEN) +#endif /* OTFDEC2 */ #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC1SMEN) +#if defined(SDMMC2) #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC2SMEN) +#endif /* SDMMC2 */ #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM2SMEN) +#if defined(SRAM3_BASE) #define __HAL_RCC_SRAM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM3SMEN) +#endif /* SRAM3_BASE */ +#if defined(FMC_BASE) #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_FSMCSMEN) +#endif /* FMC_BASE */ #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI1SMEN) +#if defined(OCTOSPI2) #define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI2SMEN) +#endif /* OCTOSPI2 */ + +#if defined(HSPI1) +#define __HAL_RCC_HSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_HSPI1SMEN) +#endif /* HSPI1 */ + +#if defined(SRAM6_BASE) +#define __HAL_RCC_SRAM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM6SMEN) +#endif /* SRAM6_BASE */ + +#if defined(SRAM5_BASE) +#define __HAL_RCC_SRAM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM5SMEN) +#endif /* SRAM5_BASE */ + /** * @} */ @@ -2677,7 +3456,7 @@ typedef struct * is enabled only when a peripheral requests AHB clock. * @{ */ -#define __HAL_RCC_LPGPIO1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN) +#define __HAL_RCC_LPGPIO1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN) #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PWRSMEN) @@ -2685,7 +3464,7 @@ typedef struct #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_DAC1SMEN) -#define __HAL_RCC_LPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN) +#define __HAL_RCC_LPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN) #define __HAL_RCC_ADF1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADF1SMEN) @@ -2693,7 +3472,7 @@ typedef struct #define __HAL_RCC_SRAM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM4SMEN) -#define __HAL_RCC_LPGPIO1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN) +#define __HAL_RCC_LPGPIO1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN) #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PWRSMEN) @@ -2701,13 +3480,14 @@ typedef struct #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_DAC1SMEN) -#define __HAL_RCC_LPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN) +#define __HAL_RCC_LPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN) #define __HAL_RCC_ADF1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADF1SMEN) #define __HAL_RCC_GTZC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_GTZC2SMEN) #define __HAL_RCC_SRAM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM4SMEN) + /** * @} */ @@ -2737,7 +3517,9 @@ typedef struct #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) +#if defined(USART2) #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) +#endif /* USART2 */ #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) @@ -2751,13 +3533,27 @@ typedef struct #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART6SMEN) +#endif /* USART6 */ + #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C5SMEN) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C6SMEN) +#endif /* I2C6 */ + #define __HAL_RCC_FDCAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN) +#if defined(UCPD1) #define __HAL_RCC_UCPD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) +#endif /* UCPD1 */ #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) @@ -2775,7 +3571,9 @@ typedef struct #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) +#if defined(USART2) #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) +#endif /* USART2 */ #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) @@ -2789,13 +3587,28 @@ typedef struct #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART6SMEN) +#endif /* USART6 */ + #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C5SMEN) +#endif /* I2C5 */ + +#if defined(I2C6) +#define __HAL_RCC_I2C6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C6SMEN) +#endif /* I2C6 */ + #define __HAL_RCC_FDCAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN) +#if defined(UCPD1) #define __HAL_RCC_UCPD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) +#endif /* UCPD1 */ + /** * @} */ @@ -2825,7 +3638,25 @@ typedef struct #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) +#if defined(SAI2) #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) +#endif /* SAI2 */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USBSMEN) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_GFXTIMSMEN) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSIHOSTSMEN) +#endif /* DSI */ #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) @@ -2843,7 +3674,25 @@ typedef struct #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) +#if defined(SAI2) #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) +#endif /* SAI2 */ + +#if defined(USB_DRD_FS) +#define __HAL_RCC_USB_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USBSMEN) +#endif /* USB_DRD_FS */ + +#if defined(GFXTIM) +#define __HAL_RCC_GFXTIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_GFXTIMSMEN) +#endif /* GFXTIM */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSIHOSTSMEN) +#endif /* DSI */ /** * @} @@ -2901,6 +3750,7 @@ typedef struct #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_VREFSMEN) #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_RTCAPBSMEN) + /** * @} */ @@ -2941,7 +3791,6 @@ typedef struct #define __HAL_RCC_SRAM4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_SRAM4AMEN) - #define __HAL_RCC_SPI3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_SPI3AMEN) #define __HAL_RCC_LPUART1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPUART1AMEN) @@ -2973,10 +3822,12 @@ typedef struct #define __HAL_RCC_ADF1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_ADF1AMEN) #define __HAL_RCC_SRAM4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_SRAM4AMEN) + /** * @} */ + /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset * @{ */ @@ -3046,7 +3897,6 @@ typedef struct #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ MODIFY_REG(RCC->ICSCR3, RCC_ICSCR3_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR3_HSITRIM_Pos) - /** * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) * in STOP mode to be quickly available as kernel clock for USARTs, LPUART and I2Cs. @@ -3130,6 +3980,7 @@ typedef struct SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE, (__MSIRANGEVALUE__)); \ } while(0) + /** * @brief Macro configures the Internal Multi Speed kernel oscillator (MSIK) clock range in run mode * @note After restart from Reset , the MSIK clock is around 4 MHz. @@ -3184,14 +4035,15 @@ typedef struct #define __HAL_RCC_LSE_GLITCHFILTER_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_LSEGFON ) #define __HAL_RCC_LSE_GLITCHFILTER_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEGFON ) + /** * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode - * After Standby its frequency can be selected between 5 possible values (4, 2, 1.5, 1, or 3.072 MHz). + * After Standby its frequency can be selected between 5 possible values (4, 2, 1.33, 1, or 3.072 MHz). * @param __MSIRANGEVALUE__: specifies the MSI clock range. * This parameter must be one of the following values: * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset) * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz - * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.5 MHz + * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz * @retval None @@ -3203,20 +4055,20 @@ typedef struct } while(0) /** * @brief Macro configures the Internal Multi Speed oscillator (MSIK) clock range after Standby mode - * After Standby its frequency can be selected between 5 possible values (4, 2, 1.5, 1, or 3.072 MHz). - * @param __MSIRANGEVALUE__: specifies the MSI clock range. + * After Standby its frequency can be selected between 5 possible values (4, 2, 1.33, 1, or 3.072 MHz). + * @param __MSIKRANGEVALUE__: specifies the MSIK clock range. * This parameter must be one of the following values: - * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset) - * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz - * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.5 MHz - * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz - * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz + * @arg @ref RCC_MSIKRANGE_4 MSIK clock is around 4 MHz (default after Reset) + * @arg @ref RCC_MSIKRANGE_5 MSIK clock is around 2 MHz + * @arg @ref RCC_MSIKRANGE_6 MSIK clock is around 1.33 MHz + * @arg @ref RCC_MSIKRANGE_7 MSIK clock is around 1 MHz + * @arg @ref RCC_MSIKRANGE_8 MSIK clock is around 3.072 MHz * @retval None */ -#define __HAL_RCC_MSIK_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) do {SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ - MODIFY_REG(RCC->CSR, RCC_CSR_MSISSRANGE,\ - (__MSIRANGEVALUE__) >> (RCC_ICSCR1_MSISRANGE_Pos -\ - RCC_CSR_MSISSRANGE_Pos));\ +#define __HAL_RCC_MSIK_STANDBY_RANGE_CONFIG(__MSIKRANGEVALUE__) do {SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ + MODIFY_REG(RCC->CSR, RCC_CSR_MSIKSRANGE,\ + (__MSIKRANGEVALUE__) >> (RCC_ICSCR1_MSIKRANGE_Pos -\ + RCC_CSR_MSIKSRANGE_Pos));\ } while(0) /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode @@ -3325,6 +4177,7 @@ typedef struct { \ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ } \ } while(0) @@ -3339,7 +4192,6 @@ typedef struct #define __HAL_RCC_LSESYS_DISABLE() CLEAR_BIT(RCC->BDCR,RCC_BDCR_LSESYSEN) - /** @brief Macro to set Low-speed clock (LSI) divider. * @note This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). * The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC. @@ -3376,26 +4228,37 @@ typedef struct * is stable and can be used to clock the RTC. * @param __STATE__: specifies the new state of the LSE. * This parameter can be one of the following values: - * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after + * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after * 6 LSE oscillator clock cycles. - * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. - * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. + * @arg @ref RCC_LSE_ON_RTC_ONLY Turn ON the LSE oscillator to be used only for RTC. + * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator to be used by any peripheral. + * @arg @ref RCC_LSE_BYPASS_RTC_ONLY LSE oscillator bypassed with external clock to be used only for RTC. + * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock to be used by any peripheral * @retval None */ #define __HAL_RCC_LSE_CONFIG(__STATE__) \ do { \ - if((__STATE__) == RCC_LSE_ON) \ + if((__STATE__) == RCC_LSE_ON_RTC_ONLY) \ { \ SET_BIT(RCC->BDCR,RCC_BDCR_LSEON); \ } \ - else if((__STATE__) == RCC_LSE_BYPASS) \ + else if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS_RTC_ONLY) \ { \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ + } \ else \ { \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ } \ } while(0) @@ -3515,9 +4378,9 @@ typedef struct * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1 * @retval None */ -#define __HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) +#define __HAL_RCC_PLL_FRACN_ENABLE() SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) -#define __HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) +#define __HAL_RCC_PLL_FRACN_DISABLE() CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) /** * @brief Macro to configure the main PLL clock source, multiplication and division factors. @@ -3544,15 +4407,15 @@ typedef struct * output frequency is between 128 and 544 MHz(Voltage range 1 or 2) * between 128 and 330 MHZ (Voltage range 3) and not allowed for Voltage range 4. * - * @param __PLL1P__: specifies the division factor for system clock. - * This parameter must be a number between 2 and 128 (where odd numbers not allowed) - * - * @param __PLL1Q__: specifies the division factor for peripheral kernel clocks + * @param __PLL1P__: specifies the division factor for peripheral kernel clocks. * This parameter must be a number between 1 and 128 * - * @param __PLL1R__: specifies the division factor for peripheral kernel clocks + * @param __PLL1Q__: specifies the division factor for peripheral kernel clocks. * This parameter must be a number between 1 and 128 * + * @param __PLL1R__: specifies the division factor for system clock. + * This parameter must be a number between 1 and 128 (Only division by 1 and even division are allowed) + * * @retval None */ #define __HAL_RCC_PLL_CONFIG(__PLL1SOURCE__, __PLL1MBOOST__,__PLL1M__, __PLL1N__, __PLL1P__, __PLL1Q__, __PLL1R__) \ @@ -3590,7 +4453,7 @@ typedef struct * 150 to 420 MHz if PLL1VCOSEL = 1. * @retval None */ -#define __HAL_RCC_PLLFRACN_CONFIG(__PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN,\ +#define __HAL_RCC_PLL_FRACN_CONFIG(__PLL1FRACN__) WRITE_REG(RCC->PLL1FRACR, \ (uint32_t)(__PLL1FRACN__) << \ RCC_PLL1FRACR_PLL1FRACN_Pos) @@ -3687,7 +4550,7 @@ typedef struct * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLL1CLK Main PLL clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source @@ -3820,7 +4683,6 @@ typedef struct */ #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_MSI) || \ ((SOURCE) == RCC_PLLSOURCE_HSI) || \ - ((SOURCE) == RCC_PLLSOURCE_NONE) || \ ((SOURCE) == RCC_PLLSOURCE_HSE)) #define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 16U)) @@ -3872,6 +4734,13 @@ typedef struct ((__RANGE__) == RCC_MSIKRANGE_13) || \ ((__RANGE__) == RCC_MSIKRANGE_14) || \ ((__RANGE__) == RCC_MSIKRANGE_15)) + +#define IS_RCC_MSIK_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIKRANGE_4) || \ + ((__RANGE__) == RCC_MSIKRANGE_5) || \ + ((__RANGE__) == RCC_MSIKRANGE_6) || \ + ((__RANGE__) == RCC_MSIKRANGE_7) || \ + ((__RANGE__) == RCC_MSIKRANGE_8)) + /** * @} */ @@ -3890,7 +4759,7 @@ typedef struct /* Initialization and de-initialization functions ******************************/ HAL_StatusTypeDef HAL_RCC_DeInit(void); -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pRCC_OscInitStruct); HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_ClkInitStruct, uint32_t FLatency); /** diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rcc_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rcc_ex.c index 2b9be9d9910..39736af31cf 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rcc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rcc_ex.c @@ -45,11 +45,15 @@ #define PLL2_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ #define PLL3_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ -#define LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +/* Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. */ +#if defined (STM32U585xx) || defined (STM32U575xx) +#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM23 /*!< External interrupt line 23 connected to the LSE CSS interrupt Line */ +#else +#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM24 /*!< External interrupt line 24 connected to the LSE CSS interrupt Line */ +#endif /* STM32U585xx || STM32U575xx */ -#define LSCO_GPIO_PORT GPIOA - -#define LSCO_PIN GPIO_PIN_2 +/* Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. */ +#define RCC_EXTI_LINE_MSIPLLUNLCK EXTI_IMR1_IM23 /*!< External interrupt line 23 connected to the MSI PLL UNLOCK interrupt Line */ /** * @} @@ -79,11 +83,13 @@ ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)) +#if defined(USART2) #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)) +#endif /* USART2 */ #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ @@ -103,6 +109,14 @@ ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE)) +#if defined(USART6) +#define IS_RCC_USART6CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART6CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_USART6CLKSOURCE_LSE)) +#endif /* USART6 */ + #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK3) || \ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ @@ -134,6 +148,22 @@ ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)|| \ ((__SOURCE__) == RCC_I2C4CLKSOURCE_MSIK)) +#if defined(I2C5) +#define IS_RCC_I2C5CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C5CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C5CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2C5CLKSOURCE_HSI)|| \ + ((__SOURCE__) == RCC_I2C5CLKSOURCE_MSIK)) +#endif /* I2C5 */ + +#if defined(I2C6) +#define IS_RCC_I2C6CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C6CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C6CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2C6CLKSOURCE_HSI)|| \ + ((__SOURCE__) == RCC_I2C6CLKSOURCE_MSIK)) +#endif /* I2C6 */ + #define IS_RCC_SAI1CLK(__SOURCE__) \ (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \ @@ -141,12 +171,14 @@ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) +#if defined(SAI2) #define IS_RCC_SAI2CLK(__SOURCE__) \ (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL1) || \ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI)) +#endif /* SAI2 */ #define IS_RCC_LPTIM1CLK(__SOURCE__) \ (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_MSIK) || \ @@ -212,11 +244,19 @@ ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL1) ||\ ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2)) -#define IS_RCC_CLK48CLKSOURCE(__SOURCE__)\ - (((__SOURCE__) == RCC_CLK48CLKSOURCE_HSI48)|| \ - ((__SOURCE__) == RCC_CLK48CLKSOURCE_PLL2) || \ - ((__SOURCE__) == RCC_CLK48CLKSOURCE_PLL1) || \ - ((__SOURCE__) == RCC_CLK48CLKSOURCE_MSIK)) +#if defined(HSPI1) +#define IS_RCC_HSPICLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_HSPICLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_HSPICLKSOURCE_PLL1) || \ + ((__SOURCE__) == RCC_HSPICLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_HSPICLKSOURCE_PLL3)) +#endif /* HSPI1 */ + +#define IS_RCC_ICLKCLKSOURCE(__SOURCE__)\ + (((__SOURCE__) == RCC_ICLK_CLKSOURCE_HSI48)|| \ + ((__SOURCE__) == RCC_ICLK_CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_ICLK_CLKSOURCE_PLL1) || \ + ((__SOURCE__) == RCC_ICLK_CLKSOURCE_MSIK)) #define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_SPI1CLKSOURCE_PCLK2) || \ @@ -244,6 +284,33 @@ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) + +#if defined(LTDC) + +#define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LTDCCLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLL2)) + +#endif /* LTDC */ + +#if defined(DSI) + +#define IS_RCC_DSICLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_DSICLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_DSICLKSOURCE_DSIPHY)) + +#endif /* DSI */ + +#if defined(USB_OTG_HS) + +#define IS_RCC_USBPHYCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USBPHYCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_USBPHYCLKSOURCE_HSE_DIV2) || \ + ((__SOURCE__) == RCC_USBPHYCLKSOURCE_PLL1) || \ + ((__SOURCE__) == RCC_USBPHYCLKSOURCE_PLL1_DIV2)) + +#endif /* USB_OTG_HS */ + #if defined(CRS) #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ @@ -269,14 +336,18 @@ #endif /* CRS */ +/** + * @} + */ + /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup RCCEx_Private_Functions RCCEx Private Functions * @{ */ static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource); -static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *Pll2); -static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *Pll3); +static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *Pll2); +static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *Pll3); /** * @} */ @@ -316,36 +387,43 @@ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *Pll3); * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C5 I2C5 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C6 I2C6 peripheral clock * @arg @ref RCC_PERIPHCLK_LPTIM34 LPTIM34 peripheral clock * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock - * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1,ADC4,DAC peripheral clock + * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1 ADC2 ADC4 DAC1 peripheral clock * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock * @arg @ref RCC_PERIPHCLK_ADF1 ADF1 peripheral clock * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock - * @arg @ref RCC_PERIPHCLK_CLK48 CLK48 peripheral clock - * @arg @ref RCC_PERIPHCLK_SDMMC SDMMC peripheral clock + * @arg @ref RCC_PERIPHCLK_ICLK ICLK peripheral clock + * @arg @ref RCC_PERIPHCLK_SDMMC SDMMC1 peripheral clock * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock * @arg @ref RCC_PERIPHCLK_OSPI OSPI peripheral clock * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock * @arg @ref RCC_PERIPHCLK_DAC1 DAC1 peripheral clock + * @arg @ref RCC_PERIPHCLK_HSPI HSPI peripheral clock + * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock + * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock + * @arg @ref RCC_PERIPHCLK_USBPHY USBPHY peripheral clock * * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select * the RTC clock source: in this case the access to Backup domain is enabled. * * @retval HAL status */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPeriphClkInit) { uint32_t tmpregister; uint32_t tickstart; @@ -365,6 +443,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl __HAL_RCC_USART1_CONFIG(pPeriphClkInit->Usart1ClockSelection); } +#if defined(USART2) /*-------------------------- USART2 clock source configuration -------------------*/ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) { @@ -374,6 +453,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(pPeriphClkInit->Usart2ClockSelection); } +#endif /* USART2 */ /*-------------------------- USART3 clock source configuration -------------------*/ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) @@ -404,6 +484,17 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl /* Configure the UART5 clock source */ __HAL_RCC_UART5_CONFIG(pPeriphClkInit->Uart5ClockSelection); } +#if defined(USART6) + /*-------------------------- USART6 clock source configuration -------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) + { + /* Check the parameters */ + assert_param(IS_RCC_USART6CLKSOURCE(pPeriphClkInit->Usart6ClockSelection)); + + /* Configure the USART6 clock source */ + __HAL_RCC_USART6_CONFIG(pPeriphClkInit->Usart6ClockSelection); + } +#endif /* USART6 */ /*-------------------------- LPUART1 clock source configuration ------------------*/ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) @@ -455,6 +546,30 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl __HAL_RCC_I2C4_CONFIG(pPeriphClkInit->I2c4ClockSelection); } +#if defined(I2C5) + /*-------------------------- I2C5 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C5) == RCC_PERIPHCLK_I2C5) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C5CLKSOURCE(pPeriphClkInit->I2c5ClockSelection)); + + /* Configure the I2C5 clock source */ + __HAL_RCC_I2C5_CONFIG(pPeriphClkInit->I2c5ClockSelection); + } +#endif /* I2C5 */ + +#if defined(I2C6) + /*-------------------------- I2C6 clock source configuration ---------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C6) == RCC_PERIPHCLK_I2C6) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C6CLKSOURCE(pPeriphClkInit->I2c6ClockSelection)); + + /* Configure the I2C6 clock source */ + __HAL_RCC_I2C6_CONFIG(pPeriphClkInit->I2c6ClockSelection); + } +#endif /* I2C6 */ + /*-------------------------- LPTIM1 clock source configuration -------------------*/ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) { @@ -527,6 +642,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl } } +#if defined(SAI2) /*-------------------------- SAI2 clock source configuration ---------------------*/ if ((((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2)) { @@ -576,6 +692,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl status = ret; } } +#endif /* SAI2 */ /*-------------------------- ADCDAC clock source configuration ----------------------*/ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADCDAC) == RCC_PERIPHCLK_ADCDAC) @@ -639,7 +756,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl ret = HAL_ERROR; break; } - if (ret == HAL_OK) { /* Configure the MDF1 interface clock source */ @@ -657,7 +773,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl { /* Check the parameters */ assert_param(IS_RCC_ADF1CLKSOURCE(pPeriphClkInit->Adf1ClockSelection)); - switch (pPeriphClkInit->Adf1ClockSelection) { case RCC_ADF1CLKSOURCE_PLL1: @@ -678,7 +793,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl ret = HAL_ERROR; break; } - if (ret == HAL_OK) { /* Configure the ADF1 interface clock source */ @@ -697,7 +811,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl FlagStatus pwrclkchanged = RESET; /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(pPeriphClkInit->RTCClockSelection)); - /* Enable Power Clock */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) { @@ -776,25 +889,25 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl } } - /*-------------------------------------- CK48 Configuration -----------------------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + /*-------------------------------------- ICLK Configuration -----------------------------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ICLK) == RCC_PERIPHCLK_ICLK) { /* Check the parameters */ - assert_param(IS_RCC_CLK48CLKSOURCE(pPeriphClkInit->Clk48ClockSelection)); + assert_param(IS_RCC_ICLKCLKSOURCE(pPeriphClkInit->IclkClockSelection)); - switch (pPeriphClkInit->Clk48ClockSelection) + switch (pPeriphClkInit->IclkClockSelection) { - case RCC_CLK48CLKSOURCE_PLL2: + case RCC_ICLK_CLKSOURCE_PLL2: /* PLL2 input clock, parameters M, N,P,Q & R configuration and clock output (PLL2ClockOut) */ ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); break; - case RCC_CLK48CLKSOURCE_PLL1: - /* Enable CLK48 Clock output generated from System PLL */ + case RCC_ICLK_CLKSOURCE_PLL1: + /* Enable ICLK Clock output generated from System PLL */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); break; - case RCC_CLK48CLKSOURCE_HSI48: + case RCC_ICLK_CLKSOURCE_HSI48: break; - case RCC_CLK48CLKSOURCE_MSIK: + case RCC_ICLK_CLKSOURCE_MSIK: break; default: ret = HAL_ERROR; @@ -803,7 +916,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl if (ret == HAL_OK) { /* Configure the CLK48 source */ - __HAL_RCC_CLK48_CONFIG(pPeriphClkInit->Clk48ClockSelection); + __HAL_RCC_CLK48_CONFIG(pPeriphClkInit->IclkClockSelection); } else { @@ -835,7 +948,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl ret = HAL_ERROR; break; } - if (ret == HAL_OK) { /* Set the source of RNG clock*/ @@ -847,7 +959,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl status = ret; } } - /*-------------------------- SAES clock source configuration ----------------*/ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAES) == RCC_PERIPHCLK_SAES) { @@ -857,7 +968,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl /* Configure the SAES clock source */ __HAL_RCC_SAES_CONFIG(pPeriphClkInit->SaesClockSelection); } - /*-------------------------- SDMMC1/2 clock source configuration -------------------*/ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == (RCC_PERIPHCLK_SDMMC)) { @@ -917,12 +1027,70 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl } if (pPeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL2) { - /* Enable PLL2 Q CLK output */ - __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); + /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + } + if (ret == HAL_OK) + { + /* Configure the OctoSPI clock source */ + __HAL_RCC_OSPI_CONFIG(pPeriphClkInit->OspiClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#if defined(HSPI1) + /*-------------------------- HSPIx kernel clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HSPI) == RCC_PERIPHCLK_HSPI) + { + + /* Check the parameters */ + assert_param(IS_RCC_HSPICLKSOURCE(pPeriphClkInit->HspiClockSelection)); + + switch (pPeriphClkInit->HspiClockSelection) + { + case RCC_HSPICLKSOURCE_SYSCLK: /* SYSCLK is used as clock source for HSPI kernel clock*/ + /* HSPI kernel clock source config set later after clock selection check */ + break; + + case RCC_HSPICLKSOURCE_PLL1: /* PLL1 is used as clock source for HSPI kernel clock*/ + /* Enable 48M2 Clock output generated from System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + /* HSPI kernel clock source config set later after clock selection check */ + break; + + case RCC_HSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for HSPI kernel clock*/ + /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* HSPI kernel clock source config set later after clock selection check */ + break; + + case RCC_HSPICLKSOURCE_PLL3: /* PLL3 is used as clock source for HSPI kernel clock*/ + /* PLL3 input clock, parameters M, N & R configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* HSPI kernel clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of HSPI kernel clock*/ + __HAL_RCC_HSPI_CONFIG(pPeriphClkInit->HspiClockSelection); + } + else + { + /* set overall return value */ + status = ret; } - /* Configure the OctoSPI clock source */ - __HAL_RCC_OSPI_CONFIG(pPeriphClkInit->OspiClockSelection); } +#endif /* defined(HSPI1) */ /*-------------------------- FDCAN1 kernel clock source configuration -------------*/ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN1) == (RCC_PERIPHCLK_FDCAN1)) @@ -963,6 +1131,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl /*-------------------------- DAC1 clock source configuration ----------------*/ if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DAC1) == RCC_PERIPHCLK_DAC1) { + /* Check the parameters */ assert_param(IS_RCC_DAC1CLKSOURCE(pPeriphClkInit->Dac1ClockSelection)); @@ -970,30 +1139,183 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphCl __HAL_RCC_DAC1_CONFIG(pPeriphClkInit->Dac1ClockSelection); } +#if defined(LTDC) + + /*-------------------------- LTDC clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) + { + + /* Check the parameters */ + assert_param(IS_RCC_LTDCCLKSOURCE(pPeriphClkInit->LtdcClockSelection)); + + switch (pPeriphClkInit->LtdcClockSelection) + { + case RCC_LTDCCLKSOURCE_PLL2: /* PLL2 is used as clock source for LTDC clock*/ + /* PLL2 input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ + ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); + /* LTDC clock source config set later after clock selection check */ + break; + + case RCC_LTDCCLKSOURCE_PLL3: /* PLL3 is used as clock source for LTDC clock*/ + /* PLL3 input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + /* LTDC clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LTDC clock*/ + __HAL_RCC_LTDC_CONFIG(pPeriphClkInit->LtdcClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#endif /* defined(LTDC) */ + +#if defined(DSI) + + /*-------------------------- DSI clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI) + { + + /* Check the parameters */ + assert_param(IS_RCC_DSICLKSOURCE(pPeriphClkInit->DsiClockSelection)); + + if (pPeriphClkInit->DsiClockSelection == RCC_DSICLKSOURCE_PLL3) + { + /* PLL3 is used as clock source for DSI clock*/ + /* PLL3 input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */ + ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); + } + + if (ret == HAL_OK) + { + /* Set the source of DSI clock*/ + __HAL_RCC_DSI_CONFIG(pPeriphClkInit->DsiClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#endif /* defined(DSI) */ + +#if defined(USB_OTG_HS) + + /*-------------------------- USB PHY clock source configuration ----------------*/ + if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USBPHY) == RCC_PERIPHCLK_USBPHY) + { + + /* Check the parameters */ + assert_param(IS_RCC_USBPHYCLKSOURCE(pPeriphClkInit->UsbPhyClockSelection)); + + switch (pPeriphClkInit->UsbPhyClockSelection) + { + case RCC_USBPHYCLKSOURCE_HSE: /* HSE is used as clock source for USB PHY clock*/ + case RCC_USBPHYCLKSOURCE_HSE_DIV2: /* HSE div 2 is used as clock source for USB PHY clock*/ + /* USB-PHY clock source config set later after clock selection check */ + break; + + case RCC_USBPHYCLKSOURCE_PLL1: /* PLL1 P divider clock selected as USB PHY clock */ + case RCC_USBPHYCLKSOURCE_PLL1_DIV2: /* PLL1 P divider clock div 2 selected as USB PHY clock */ + /* Enable P Clock output generated from System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); + /* USB-PHY clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USBPHY clock*/ + __HAL_RCC_USBPHY_CONFIG(pPeriphClkInit->UsbPhyClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#endif /* defined(USB_OTG_HS) */ + return status; } + + /** * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * returns the configuration information for the Extended Peripherals * clocks(USART1, USART2, USART3, UART4, UART5, LPUART, I2C1, I2C2, I2C3, LPTIM1, LPTIM2, SAI1, SAI2, - * SAES, ADC1, ADC4, MDF1, MDF2, RTC, CLK48, SDMMC1, I2C4, SPI12, SPI3, OSPI, FDCAN1, DAC1). + * ADC1, ADC2, MDF1, MDF2, RTC, CLK48, SDMMC1, I2C4, SPI12, SPI3, OSPI, FDCAN1, DAC1). * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) { /* Set all possible values for the extended clock type parameter------------*/ +#if (defined(STM32U599xx) || defined(STM32U5A9xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx)) + pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \ + RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ + RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \ + RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_LTDC | \ + RCC_PERIPHCLK_DSI | RCC_PERIPHCLK_USBPHY; +#elif (defined(STM32U595xx) || defined(STM32U5A5xx)) + pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \ + RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ + RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \ + RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_USBPHY; +#elif (defined(STM32U585xx) || defined(STM32U575xx)) pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | \ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ RCC_PERIPHCLK_SAES | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | \ - RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | \ RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | \ RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | \ RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1; +#else + pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ + RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 | \ + RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAES | \ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | \ + RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_ICLK | \ + RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_I2C4 | \ + RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \ + RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1; +#endif /* (defined(STM32U599xx) || defined(STM32U5A9xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx)) */ /* Get the PLL2 Clock configuration -----------------------------------------------*/ pPeriphClkInit->PLL2.PLL2Source = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC) >> RCC_PLL2CFGR_PLL2SRC_Pos); @@ -1020,8 +1342,10 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) /* Get the USART1 clock source ---------------------------------------------*/ pPeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); +#if defined(USART2) /* Get the USART2 clock source ---------------------------------------------*/ pPeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); +#endif /* USART2 */ /* Get the USART3 clock source ---------------------------------------------*/ pPeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); @@ -1035,6 +1359,11 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) /* Get the LPUART1 clock source --------------------------------------------*/ pPeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); +#if defined(USART6) + /* Get the UART6 clock source ---------------------------------------------*/ + pPeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); +#endif /* defined(USART6) */ + /* Get the I2C1 clock source -----------------------------------------------*/ pPeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); @@ -1047,6 +1376,16 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) /* Get the I2C4 clock source -----------------------------------------------*/ pPeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE(); +#if defined(I2C5) + /* Get the clock source ---------------------------------------------*/ + pPeriphClkInit->I2c5ClockSelection = __HAL_RCC_GET_I2C5_SOURCE(); +#endif /* defined(I2C5) */ + +#if defined(I2C6) + /* Get the clock source ---------------------------------------------*/ + pPeriphClkInit->I2c6ClockSelection = __HAL_RCC_GET_I2C6_SOURCE(); +#endif /* defined(I2C6) */ + /* Get the LPTIM1 clock source ---------------------------------------------*/ pPeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); @@ -1071,11 +1410,13 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) /* Get the SAI1 clock source -----------------------------------------------*/ pPeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); +#if defined(SAI2) /* Get the SAI2 clock source -----------------------------------------------*/ pPeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); +#endif /* SAI2 */ /* Get the CLK48 clock source ----------------------------------------------*/ - pPeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); + pPeriphClkInit->IclkClockSelection = __HAL_RCC_GET_ICLK_SOURCE(); /* Get the SDMMC clock source ----------------------------------------------*/ pPeriphClkInit->SdmmcClockSelection = __HAL_RCC_GET_SDMMC_SOURCE(); @@ -1103,6 +1444,26 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) /* Get the RNG clock source ------------------------------------------------*/ pPeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); + +#if defined(HSPI1) + /* Get the HSPI kernel clock source ------------------------------------------------*/ + pPeriphClkInit->HspiClockSelection = __HAL_RCC_GET_HSPI_SOURCE(); +#endif /* defined(HSPI1) */ + +#if defined(LTDC) + /* Get the LTDC clock source ------------------------------------------------*/ + pPeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE(); +#endif /* defined(LTDC) */ + +#if defined(DSI) + /* Get the DSI clock source ------------------------------------------------*/ + pPeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE(); +#endif /* defined(DSI) */ + +#if defined(USB_OTG_HS) + /* Get the USB PHY clock source ------------------------------------------------*/ + pPeriphClkInit->UsbPhyClockSelection = __HAL_RCC_GET_USBPHY_SOURCE(); +#endif /* defined(USB_OTG_HS) */ } /** @@ -1132,7 +1493,7 @@ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks) pll1n = (RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N); pll1source = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); pll1m = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U; - pll1fracen = RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN; + pll1fracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN) >> RCC_PLL1CFGR_PLL1FRACEN_Pos); fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \ RCC_PLL1FRACR_PLL1FRACN_Pos)); @@ -1199,6 +1560,7 @@ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks) PLL1_Clocks->PLL1_Q_Frequency = 0U; PLL1_Clocks->PLL1_R_Frequency = 0U; } + } /** @@ -1230,7 +1592,7 @@ void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks) pll2n = (RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N); pll2source = (RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC); pll2m = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1U; - pll2fracen = RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN; + pll2fracen = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN) >> RCC_PLL2CFGR_PLL2FRACEN_Pos); fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \ RCC_PLL2FRACR_PLL2FRACN_Pos)); @@ -1328,7 +1690,7 @@ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) pll3n = (RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N); pll3source = (RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC); pll3m = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos) + 1U; - pll3fracen = RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3FRACEN; + pll3fracen = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3FRACEN) >> RCC_PLL3CFGR_PLL3FRACEN_Pos); fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \ RCC_PLL3FRACR_PLL3FRACN_Pos)); @@ -1409,31 +1771,41 @@ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock - * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock - * @arg @ref RCC_PERIPHCLK_LPTIM34 LPTIM34 peripheral clock + * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock - * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock + * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock + * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock + * @arg @ref RCC_PERIPHCLK_ICLK ICLK peripheral clock + * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock - * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1,ADC4, DAC1 peripheral clock - * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock - * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock - * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock - * @arg @ref RCC_PERIPHCLK_CLK48 CLK48 peripheral clock + * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock + * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock * @arg @ref RCC_PERIPHCLK_SDMMC SDMMC peripheral clock - * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock - * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock - * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock (*) * @arg @ref RCC_PERIPHCLK_OSPI OSPI peripheral clock - * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock + * @arg @ref RCC_PERIPHCLK_HSPI1 HSPI1 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_I2C5 I2C5 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_I2C6 I2C6 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_USBPHY USB_OTG_HS peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + * @arg @ref RCC_PERIPHCLK_LPTIM34 LPTIM34 peripheral clock + * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock + * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1 ADC2 ADC4 DAC1 peripheral clock * @arg @ref RCC_PERIPHCLK_DAC1 DAC1 peripheral clock + * @arg @ref RCC_PERIPHCLK_ADF1 ADF1 peripheral clock + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock * @retval Frequency in Hz + * + * (*) value not defined in all devices. */ -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) { PLL1_ClocksTypeDef pll1_clocks; PLL2_ClocksTypeDef pll2_clocks; @@ -1478,219 +1850,145 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) frequency = 0U; } } - else + else if (PeriphClk == RCC_PERIPHCLK_SAI1) { - /* Other external peripheral clock source than RTC */ - switch (PeriphClk) - { - case RCC_PERIPHCLK_SAI1: + srcclk = __HAL_RCC_GET_SAI1_SOURCE(); - srcclk = __HAL_RCC_GET_SAI1_SOURCE(); - - switch (srcclk) - { - case RCC_SAI1CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */ - - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_P_Frequency; - break; - - case RCC_SAI1CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */ - - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_P_Frequency; - break; + switch (srcclk) + { + case RCC_SAI1CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */ - case RCC_SAI1CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */ + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_P_Frequency; + break; - HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - frequency = pll3_clocks.PLL3_P_Frequency; - break; + case RCC_SAI1CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */ - case RCC_SAI1CLKSOURCE_PIN: + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + break; - frequency = EXTERNAL_SAI1_CLOCK_VALUE; - break; + case RCC_SAI1CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */ - case RCC_SAI1CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */ + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + break; - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; + case RCC_SAI1CLKSOURCE_PIN: - default : - { - frequency = 0U; - break; - } - } + frequency = EXTERNAL_SAI1_CLOCK_VALUE; break; - case RCC_PERIPHCLK_SAI2: - - srcclk = __HAL_RCC_GET_SAI2_SOURCE(); + case RCC_SAI1CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */ - switch (srcclk) + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) { - case RCC_SAI2CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */ - - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_P_Frequency; - break; - - case RCC_SAI2CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */ - - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_P_Frequency; - break; + frequency = HSI_VALUE; + } + else + { + frequency = 0U; + } + break; - case RCC_SAI2CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */ + default : + { + frequency = 0U; + break; + } + } + } +#if defined(SAI2) + else if (PeriphClk == RCC_PERIPHCLK_SAI2) + { + srcclk = __HAL_RCC_GET_SAI2_SOURCE(); - HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - frequency = pll3_clocks.PLL3_P_Frequency; - break; + switch (srcclk) + { + case RCC_SAI2CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */ - case RCC_SAI2CLKSOURCE_PIN: + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_P_Frequency; + break; - frequency = EXTERNAL_SAI1_CLOCK_VALUE; - break; + case RCC_SAI2CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */ - case RCC_SAI2CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */ + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + break; - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; + case RCC_SAI2CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */ - default : + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + break; - frequency = 0U; - break; + case RCC_SAI2CLKSOURCE_PIN: - } + frequency = EXTERNAL_SAI1_CLOCK_VALUE; break; - case RCC_PERIPHCLK_SAES: - /* Get the current SAES source */ - srcclk = __HAL_RCC_GET_SAES_SOURCE(); - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI)) + case RCC_SAI2CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */ + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) { frequency = HSI_VALUE; } - else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI_DIV2)) - { - frequency = HSI_VALUE >> 1U; - } - /* Clock not enabled for SAES */ else { frequency = 0U; } break; - case RCC_PERIPHCLK_CLK48: - - srcclk = __HAL_RCC_GET_CLK48_SOURCE(); - - switch (srcclk) - { - case RCC_CLK48CLKSOURCE_PLL1: /* PLL1Q */ - - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_Q_Frequency; - break; - - case RCC_CLK48CLKSOURCE_PLL2: /* PLL2Q */ - - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_Q_Frequency; - break; + default : - case RCC_CLK48CLKSOURCE_HSI48: /* HSI48 */ + frequency = 0U; + break; + } + } +#endif /* SAI2 */ + else if (PeriphClk == RCC_PERIPHCLK_SAES) + { + /* Get the current SAES source */ + srcclk = __HAL_RCC_GET_SAES_SOURCE(); - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) - { - frequency = HSI48_VALUE; - } - else - { - frequency = 0U; - } - break; - - case RCC_CLK48CLKSOURCE_MSIK: /* MSIK frequency range in HZ */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI)) + { + frequency = HSI_VALUE; + } + else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI_DIV2)) + { + frequency = HSI_VALUE >> 1U; + } + /* Clock not enabled for SAES */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_ICLK) + { + srcclk = __HAL_RCC_GET_ICLK_SOURCE(); - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - break; + switch (srcclk) + { + case RCC_ICLK_CLKSOURCE_PLL1: /* PLL1Q */ - default : + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; - frequency = 0U; - break; + case RCC_ICLK_CLKSOURCE_PLL2: /* PLL2Q */ - } + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; break; - case RCC_PERIPHCLK_SDMMC: - srcclk = __HAL_RCC_GET_SDMMC_SOURCE(); - if (srcclk == RCC_SDMMCCLKSOURCE_CLK48) - { - srcclk = __HAL_RCC_GET_CLK48_SOURCE(); + case RCC_ICLK_CLKSOURCE_HSI48: /* HSI48 */ - switch (srcclk) - { - case RCC_CLK48CLKSOURCE_PLL1: /* PLL1Q */ - { - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_Q_Frequency; - break; - } - case RCC_CLK48CLKSOURCE_PLL2: /* PLL2Q */ - { - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_Q_Frequency; - break; - } - case RCC_CLK48CLKSOURCE_HSI48: /* HSI48 */ - { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) - { - frequency = HSI48_VALUE; - } - else - { - frequency = 0U; - } - break; - } - case RCC_CLK48CLKSOURCE_MSIK: /* MSIK frequency range in HZ */ - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - break; - } - default : - { - frequency = 0U; - break; - } - } - break; - } - else if (srcclk == RCC_SDMMCCLKSOURCE_PLL1) + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) { - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_P_Frequency; + frequency = HSI48_VALUE; } else { @@ -1698,692 +1996,1090 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } break; - case RCC_PERIPHCLK_USART1: - /* Get the current USART1 source */ - srcclk = __HAL_RCC_GET_USART1_SOURCE(); + case RCC_ICLK_CLKSOURCE_MSIK: /* MSIK frequency range in HZ */ - if (srcclk == RCC_USART1CLKSOURCE_PCLK2) + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) { - frequency = HAL_RCC_GetPCLK2Freq(); - } - else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; } - /* Clock not enabled for USART1 */ else { frequency = 0U; } break; - case RCC_PERIPHCLK_USART2: - /* Get the current USART2 source */ - srcclk = __HAL_RCC_GET_USART2_SOURCE(); + default : - if (srcclk == RCC_USART2CLKSOURCE_PCLK1) + frequency = 0U; + break; + } + } + else if (PeriphClk == RCC_PERIPHCLK_SDMMC) + { + srcclk = __HAL_RCC_GET_SDMMC_SOURCE(); + if (srcclk == RCC_SDMMCCLKSOURCE_CLK48) + { + srcclk = __HAL_RCC_GET_ICLK_SOURCE(); + + switch (srcclk) + { + case RCC_ICLK_CLKSOURCE_PLL1: /* PLL1Q */ { - frequency = HAL_RCC_GetPCLK1Freq(); + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; } - else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) + case RCC_ICLK_CLKSOURCE_PLL2: /* PLL2Q */ { - frequency = HAL_RCC_GetSysClockFreq(); + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + break; } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI)) + case RCC_ICLK_CLKSOURCE_HSI48: /* HSI48 */ { - frequency = HSI_VALUE; + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) + { + frequency = HSI48_VALUE; + } + else + { + frequency = 0U; + } + break; } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE)) + case RCC_ICLK_CLKSOURCE_MSIK: /* MSIK frequency range in HZ */ { - frequency = LSE_VALUE; + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + else + { + frequency = 0U; + } + break; } - /* Clock not enabled for USART2 */ - else + default : { frequency = 0U; + break; } + } + } + else if (srcclk == RCC_SDMMCCLKSOURCE_PLL1) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_P_Frequency; + } + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_USART1) + { + /* Get the current USART1 source */ + srcclk = __HAL_RCC_GET_USART1_SOURCE(); + + if (srcclk == RCC_USART1CLKSOURCE_PCLK2) + { + frequency = HAL_RCC_GetPCLK2Freq(); + } + else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART1 */ + else + { + frequency = 0U; + } + } +#if defined(USART2) + else if (PeriphClk == RCC_PERIPHCLK_USART2) + { + /* Get the current USART2 source */ + srcclk = __HAL_RCC_GET_USART2_SOURCE(); + + if (srcclk == RCC_USART2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART2 */ + else + { + frequency = 0U; + } + } +#endif /* USART2 */ + else if (PeriphClk == RCC_PERIPHCLK_USART3) + { + /* Get the current USART3 source */ + srcclk = __HAL_RCC_GET_USART3_SOURCE(); + + if (srcclk == RCC_USART3CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART3 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_UART4) + { + /* Get the current UART4 source */ + srcclk = __HAL_RCC_GET_UART4_SOURCE(); + + if (srcclk == RCC_UART4CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART4CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for UART4 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_UART5) + { + /* Get the current UART5 source */ + srcclk = __HAL_RCC_GET_UART5_SOURCE(); + + if (srcclk == RCC_UART5CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART5CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for UART5 */ + else + { + frequency = 0U; + } + } +#if defined(USART6) + else if (PeriphClk == RCC_PERIPHCLK_USART6) + { + /* Get the current USART6 source */ + srcclk = __HAL_RCC_GET_USART6_SOURCE(); + + if (srcclk == RCC_USART6CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_USART6CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART6CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART6CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for UART5 */ + else + { + frequency = 0U; + } + } +#endif /* USART6 */ + else if (PeriphClk == RCC_PERIPHCLK_LPUART1) + { + /* Get the current LPUART1 source */ + srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); + + if (srcclk == RCC_LPUART1CLKSOURCE_PCLK3) + { + frequency = HAL_RCC_GetPCLK3Freq(); + } + else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_MSIK)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + /* Clock not enabled for LPUART1 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_ADCDAC) + { + srcclk = __HAL_RCC_GET_ADCDAC_SOURCE(); + + if (srcclk == RCC_ADCDACCLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if (srcclk == RCC_ADCDACCLKSOURCE_PLL2) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_R_Frequency; + } + else if (srcclk == RCC_ADCDACCLKSOURCE_HCLK) + { + frequency = HAL_RCC_GetHCLKFreq(); + } + else if (srcclk == RCC_ADCDACCLKSOURCE_MSIK) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + else + { + frequency = 0U; + } + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSE)) + { + frequency = HSE_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + /* Clock not enabled for ADC */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_MDF1) + { + /* Get the current MDF1 source */ + srcclk = __HAL_RCC_GET_MDF1_SOURCE(); + + switch (srcclk) + { + case RCC_MDF1CLKSOURCE_PLL1: + + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_P_Frequency; break; - case RCC_PERIPHCLK_USART3: - /* Get the current USART3 source */ - srcclk = __HAL_RCC_GET_USART3_SOURCE(); + case RCC_MDF1CLKSOURCE_PLL3: - if (srcclk == RCC_USART3CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for USART3 */ - else - { - frequency = 0U; - } + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; break; - case RCC_PERIPHCLK_UART4: - /* Get the current UART4 source */ - srcclk = __HAL_RCC_GET_UART4_SOURCE(); + case RCC_MDF1CLKSOURCE_HCLK: - if (srcclk == RCC_UART4CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART4CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for UART4 */ - else - { - frequency = 0U; - } + frequency = HAL_RCC_GetHCLKFreq(); break; - case RCC_PERIPHCLK_UART5: - /* Get the current UART5 source */ - srcclk = __HAL_RCC_GET_UART5_SOURCE(); + case RCC_MDF1CLKSOURCE_PIN: - if (srcclk == RCC_UART5CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART5CLKSOURCE_LSE)) + frequency = EXTERNAL_SAI1_CLOCK_VALUE; + break; + + case RCC_MDF1CLKSOURCE_MSIK: + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) { - frequency = LSE_VALUE; + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; } - /* Clock not enabled for UART5 */ else { frequency = 0U; } break; - case RCC_PERIPHCLK_LPUART1: - /* Get the current LPUART1 source */ - srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); + default: - if (srcclk == RCC_LPUART1CLKSOURCE_PCLK3) - { - frequency = HAL_RCC_GetPCLK3Freq(); - } - else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_MSIK)) - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - } - /* Clock not enabled for LPUART1 */ - else - { - frequency = 0U; - } + frequency = 0U; break; + } + } + else if (PeriphClk == RCC_PERIPHCLK_ADF1) + { + /* Get the current ADF1 source */ + srcclk = __HAL_RCC_GET_ADF1_SOURCE(); - case RCC_PERIPHCLK_ADCDAC: - - srcclk = __HAL_RCC_GET_ADCDAC_SOURCE(); + switch (srcclk) + { + case RCC_ADF1CLKSOURCE_PLL1: - if (srcclk == RCC_ADCDACCLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if (srcclk == RCC_ADCDACCLKSOURCE_PLL2) - { - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_R_Frequency; - } - else if (srcclk == RCC_ADCDACCLKSOURCE_HCLK) - { - frequency = HAL_RCC_GetHCLKFreq(); - break; - } - else if (srcclk == RCC_ADCDACCLKSOURCE_MSIK) - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)]; - break; - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSE)) - { - frequency = HSE_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for ADC */ - else - { - frequency = 0U; - } + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_P_Frequency; break; - case RCC_PERIPHCLK_MDF1: - /* Get the current MDF1 source */ - srcclk = __HAL_RCC_GET_MDF1_SOURCE(); - - switch (srcclk) - { - case RCC_MDF1CLKSOURCE_PLL1: - - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_P_Frequency; - break; - - case RCC_MDF1CLKSOURCE_PLL3: - - HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - frequency = pll3_clocks.PLL3_Q_Frequency; - break; - - case RCC_MDF1CLKSOURCE_HCLK: - - frequency = HAL_RCC_GetHCLKFreq(); - break; - - case RCC_MDF1CLKSOURCE_PIN: - - frequency = EXTERNAL_SAI1_CLOCK_VALUE; - break; + case RCC_ADF1CLKSOURCE_PLL3: - case RCC_MDF1CLKSOURCE_MSIK: + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + break; - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - break; + case RCC_ADF1CLKSOURCE_HCLK: - default: + frequency = HAL_RCC_GetHCLKFreq(); + break; - frequency = 0U; - break; + case RCC_ADF1CLKSOURCE_PIN: - } + frequency = EXTERNAL_SAI1_CLOCK_VALUE; break; - case RCC_PERIPHCLK_ADF1: - /* Get the current ADF1 source */ - srcclk = __HAL_RCC_GET_ADF1_SOURCE(); + case RCC_ADF1CLKSOURCE_MSIK: - switch (srcclk) + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) { - case RCC_ADF1CLKSOURCE_PLL1: - - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_P_Frequency; - break; - - case RCC_ADF1CLKSOURCE_PLL3: - - HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - frequency = pll3_clocks.PLL3_Q_Frequency; - break; - - case RCC_ADF1CLKSOURCE_HCLK: - - frequency = HAL_RCC_GetHCLKFreq(); - break; - - case RCC_ADF1CLKSOURCE_PIN: + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + else + { + frequency = 0U; + } + break; - frequency = EXTERNAL_SAI1_CLOCK_VALUE; - break; + default: - case RCC_ADF1CLKSOURCE_MSIK: + frequency = 0U; + break; + } + } + else if (PeriphClk == RCC_PERIPHCLK_I2C1) + { + /* Get the current I2C1 source */ + srcclk = __HAL_RCC_GET_I2C1_SOURCE(); - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - break; + if (srcclk == RCC_I2C1CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C1CLKSOURCE_MSIK)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + /* Clock not enabled for I2C1 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_I2C2) + { + /* Get the current I2C2 source */ + srcclk = __HAL_RCC_GET_I2C2_SOURCE(); - default: + if (srcclk == RCC_I2C2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C2CLKSOURCE_MSIK)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + /* Clock not enabled for I2C2 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_I2C3) + { + /* Get the current I2C3 source */ + srcclk = __HAL_RCC_GET_I2C3_SOURCE(); - frequency = 0U; - break; - } + switch (srcclk) + { + case RCC_I2C3CLKSOURCE_PCLK3: + { + frequency = HAL_RCC_GetPCLK3Freq(); break; - - case RCC_PERIPHCLK_I2C1: - /* Get the current I2C1 source */ - srcclk = __HAL_RCC_GET_I2C1_SOURCE(); - - if (srcclk == RCC_I2C1CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI)) + } + case RCC_I2C3CLKSOURCE_HSI: + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) { frequency = HSI_VALUE; } - /* Clock not enabled for I2C1 */ else { frequency = 0U; } break; - - case RCC_PERIPHCLK_I2C2: - /* Get the current I2C2 source */ - srcclk = __HAL_RCC_GET_I2C2_SOURCE(); - - if (srcclk == RCC_I2C2CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI)) + } + case RCC_I2C3CLKSOURCE_SYSCLK: + { + frequency = HAL_RCC_GetSysClockFreq(); + break; + } + case RCC_I2C3CLKSOURCE_MSIK: + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) { - frequency = HSI_VALUE; + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; } - /* Clock not enabled for I2C2 */ else { frequency = 0U; } break; + } + default: + { + frequency = 0U; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_I2C4) + { + /* Get the current I2C4 source */ + srcclk = __HAL_RCC_GET_I2C4_SOURCE(); - case RCC_PERIPHCLK_I2C3: - /* Get the current I2C3 source */ - srcclk = __HAL_RCC_GET_I2C3_SOURCE(); + if (srcclk == RCC_I2C4CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_I2C4CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C4CLKSOURCE_MSIK)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + /* Clock not enabled for I2C4 */ + else + { + frequency = 0U; + } + } +#if defined (I2C5) + else if (PeriphClk == RCC_PERIPHCLK_I2C5) + { + /* Get the current I2C5 source */ + srcclk = __HAL_RCC_GET_I2C5_SOURCE(); - switch (srcclk) - { - case RCC_I2C3CLKSOURCE_PCLK3: - { - frequency = HAL_RCC_GetPCLK3Freq(); - break; - } - case RCC_I2C3CLKSOURCE_HSI: - { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; - } - case RCC_I2C3CLKSOURCE_SYSCLK: - { - frequency = HAL_RCC_GetSysClockFreq(); - break; - } - case RCC_I2C3CLKSOURCE_MSIK: - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)]; - break; - } - default: - { - frequency = 0U; - break; - } - } + if (srcclk == RCC_I2C5CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_I2C5CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C5CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C5CLKSOURCE_MSIK)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + /* Clock not enabled for I2C5 */ + else + { + frequency = 0U; + } + } +#endif /* I2C5 */ +#if defined (I2C6) + else if (PeriphClk == RCC_PERIPHCLK_I2C6) + { + /* Get the current I2C6 source */ + srcclk = __HAL_RCC_GET_I2C6_SOURCE(); + + if (srcclk == RCC_I2C6CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_I2C6CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C6CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C6CLKSOURCE_MSIK)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + /* Clock not enabled for I2C6 */ + else + { + frequency = 0U; + } + } +#endif /* I2C6 */ + else if (PeriphClk == RCC_PERIPHCLK_LPTIM34) + { + /* Get the current LPTIM34 source */ + srcclk = __HAL_RCC_GET_LPTIM34_SOURCE(); + + if (srcclk == RCC_LPTIM34CLKSOURCE_MSIK) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + else + { + frequency = 0U; + } + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSI)) + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV)) + { + frequency = LSI_VALUE / 128U; + } + else + { + frequency = LSI_VALUE; + } + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for LPTIM34 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_LPTIM1) + { + /* Get the current LPTIM1 source */ + srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); + + if (srcclk == RCC_LPTIM1CLKSOURCE_MSIK) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; + } + else + { + frequency = 0U; + } + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSI)) + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV)) + { + frequency = LSI_VALUE / 128U; + } + else + { + frequency = LSI_VALUE; + } + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for LPTIM1 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_LPTIM2) + { + /* Get the current LPTIM2 source */ + srcclk = __HAL_RCC_GET_LPTIM2_SOURCE(); + + if (srcclk == RCC_LPTIM2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSI)) + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV)) + { + frequency = LSI_VALUE / 128U; + } + else + { + frequency = LSI_VALUE; + } + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for LPTIM2 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_FDCAN1) + { + /* Get the current FDCAN1 kernel source */ + srcclk = __HAL_RCC_GET_FDCAN1_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_FDCAN1CLKSOURCE_HSE)) + { + frequency = HSE_VALUE; + } + else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL1) /* PLL1 ? */ + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL2) /* PLL2 ? */ + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + /* Clock not enabled for FDCAN1 */ + else + { + frequency = 0U; + } + } + else if (PeriphClk == RCC_PERIPHCLK_SPI1) + { + /* Get the current SPI1 kernel source */ + srcclk = __HAL_RCC_GET_SPI1_SOURCE(); + switch (srcclk) + { + case RCC_SPI1CLKSOURCE_PCLK2: + + frequency = HAL_RCC_GetPCLK2Freq(); + break; + + case RCC_SPI1CLKSOURCE_SYSCLK: + + frequency = HAL_RCC_GetSysClockFreq(); break; - case RCC_PERIPHCLK_I2C4: - /* Get the current I2C4 source */ - srcclk = __HAL_RCC_GET_I2C4_SOURCE(); + case RCC_SPI1CLKSOURCE_HSI: - if (srcclk == RCC_I2C4CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if (srcclk == RCC_I2C4CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_HSI)) + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) { frequency = HSI_VALUE; } - /* Clock not enabled for I2C4 */ else { frequency = 0U; } break; - case RCC_PERIPHCLK_LPTIM34: - /* Get the current LPTIM34 source */ - srcclk = __HAL_RCC_GET_LPTIM34_SOURCE(); + case RCC_SPI1CLKSOURCE_MSIK: - if (srcclk == RCC_LPTIM34CLKSOURCE_MSIK) + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) { frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSI)) + else { - frequency = LSI_VALUE; + frequency = 0U; } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_HSI)) + break; + + default: + + frequency = 0U; + break; + } + } + else if (PeriphClk == RCC_PERIPHCLK_SPI2) + { + /* Get the current SPI2 kernel source */ + srcclk = __HAL_RCC_GET_SPI2_SOURCE(); + switch (srcclk) + { + case RCC_SPI2CLKSOURCE_PCLK1: + + frequency = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_SPI2CLKSOURCE_SYSCLK: + + frequency = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_SPI2CLKSOURCE_HSI: + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) { frequency = HSI_VALUE; } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for LPTIM34 */ else { frequency = 0U; } break; - case RCC_PERIPHCLK_LPTIM1: - /* Get the current LPTIM1 source */ - srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); + case RCC_SPI2CLKSOURCE_MSIK: - if (srcclk == RCC_LPTIM1CLKSOURCE_MSIK) + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) { frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSI)) - { - frequency = LSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for LPTIM1 */ else { frequency = 0U; } break; - case RCC_PERIPHCLK_LPTIM2: - /* Get the current LPTIM2 source */ - srcclk = __HAL_RCC_GET_LPTIM2_SOURCE(); + default: + + frequency = 0U; + break; + } + } + else if (PeriphClk == RCC_PERIPHCLK_SPI3) + { + /* Get the current SPI3 kernel source */ + srcclk = __HAL_RCC_GET_SPI3_SOURCE(); + switch (srcclk) + { + case RCC_SPI3CLKSOURCE_PCLK3: + + frequency = HAL_RCC_GetPCLK3Freq(); + break; + + case RCC_SPI3CLKSOURCE_SYSCLK: - if (srcclk == RCC_LPTIM2CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSI)) - { - frequency = LSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_HSI)) + frequency = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_SPI3CLKSOURCE_HSI: + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) { frequency = HSI_VALUE; } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for LPTIM2 */ else { frequency = 0U; } break; - case RCC_PERIPHCLK_FDCAN1: - /* Get the current FDCAN1 kernel source */ - srcclk = __HAL_RCC_GET_FDCAN1_SOURCE(); + case RCC_SPI3CLKSOURCE_MSIK: - if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_FDCAN1CLKSOURCE_HSE)) - { - frequency = HSE_VALUE; - } - else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL1) /* PLL1 ? */ - { - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_Q_Frequency; - } - else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL2) /* PLL2 ? */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) { - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_P_Frequency; + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; } - /* Clock not enabled for FDCAN1 */ else { frequency = 0U; } break; - case RCC_PERIPHCLK_SPI1: - /* Get the current SPI1 kernel source */ - srcclk = __HAL_RCC_GET_SPI1_SOURCE(); - switch (srcclk) - { - case RCC_SPI1CLKSOURCE_PCLK2: - - frequency = HAL_RCC_GetPCLK2Freq(); - break; + default: - case RCC_SPI1CLKSOURCE_SYSCLK: + frequency = 0U; + break; + } + } + else if (PeriphClk == RCC_PERIPHCLK_OSPI) + { + /* Get the current OSPI kernel source */ + srcclk = __HAL_RCC_GET_OSPI_SOURCE(); - frequency = HAL_RCC_GetSysClockFreq(); - break; + switch (srcclk) + { + case RCC_OSPICLKSOURCE_PLL2: - case RCC_SPI1CLKSOURCE_HSI: + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + break; - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; + case RCC_OSPICLKSOURCE_PLL1: - case RCC_SPI1CLKSOURCE_MSIK: + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - break; + case RCC_OSPICLKSOURCE_SYSCLK: - default: + frequency = HAL_RCC_GetSysClockFreq(); + break; - frequency = 0U; - break; + case RCC_OSPICLKSOURCE_MSIK: + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) + { + frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; } - break; - - case RCC_PERIPHCLK_SPI2: - /* Get the current SPI2 kernel source */ - srcclk = __HAL_RCC_GET_SPI2_SOURCE(); - switch (srcclk) + else { - case RCC_SPI2CLKSOURCE_PCLK1: - - frequency = HAL_RCC_GetPCLK1Freq(); - break; - - case RCC_SPI2CLKSOURCE_SYSCLK: - - frequency = HAL_RCC_GetSysClockFreq(); - break; - - case RCC_SPI2CLKSOURCE_HSI: - - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; - - case RCC_SPI2CLKSOURCE_MSIK: - - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - break; - - default: - - frequency = 0U; - break; - + frequency = 0U; } break; - case RCC_PERIPHCLK_SPI3: - /* Get the current SPI3 kernel source */ - srcclk = __HAL_RCC_GET_SPI3_SOURCE(); - switch (srcclk) - { - case RCC_SPI3CLKSOURCE_PCLK3: - - frequency = HAL_RCC_GetPCLK3Freq(); - break; + default: - case RCC_SPI3CLKSOURCE_SYSCLK: + frequency = 0U; + break; + } + } +#if defined(HSPI1) - frequency = HAL_RCC_GetSysClockFreq(); - break; + else if (PeriphClk == RCC_PERIPHCLK_HSPI) + { + /* Get the current HSPI kernel source */ + srcclk = __HAL_RCC_GET_HSPI_SOURCE(); - case RCC_SPI3CLKSOURCE_HSI: + switch (srcclk) + { + case RCC_HSPICLKSOURCE_SYSCLK: - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; + frequency = HAL_RCC_GetSysClockFreq(); + break; - case RCC_SPI3CLKSOURCE_MSIK: + case RCC_HSPICLKSOURCE_PLL1: - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - break; + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; - default: + case RCC_HSPICLKSOURCE_PLL2: - frequency = 0U; - break; - } + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; break; + case RCC_HSPICLKSOURCE_PLL3: - case RCC_PERIPHCLK_OSPI: - /* Get the current OSPI kernel source */ - srcclk = __HAL_RCC_GET_OSPI_SOURCE(); - - switch (srcclk) - { - case RCC_OSPICLKSOURCE_PLL2: + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; + break; - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_Q_Frequency; - break; + default: - case RCC_OSPICLKSOURCE_PLL1: + frequency = 0U; + break; + } + } +#endif /* defined(HSPI1) */ + else if (PeriphClk == RCC_PERIPHCLK_DAC1) + { + /* Get the current DAC1 kernel source */ + srcclk = __HAL_RCC_GET_DAC1_SOURCE(); - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_Q_Frequency; - break; + /* Check if LSE is ready and if DAC1 clock selection is LSE */ + if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Check if LSI is ready and if DAC1 clock selection is LSI */ + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSI)) + { + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV)) + { + frequency = LSI_VALUE / 128U; + } + else + { + frequency = LSI_VALUE; + } + } + /* Clock not enabled for DAC1*/ + else + { + frequency = 0U; + } - case RCC_OSPICLKSOURCE_SYSCLK: + } + else if (PeriphClk == RCC_PERIPHCLK_RNG) + { + /* Get the current RNG kernel source */ + srcclk = __HAL_RCC_GET_RNG_SOURCE(); - frequency = HAL_RCC_GetSysClockFreq(); - break; + /* Check if HSI48 is ready and if RNG clock selection is HSI48 */ + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI48)) + { + frequency = HSI48_VALUE; + } - case RCC_OSPICLKSOURCE_MSIK: + /* Check if HSI48 is ready and if RNG clock selection is HSI48_DIV2 */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI48_DIV2)) + { + frequency = HSI48_VALUE >> 1U ; + } - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - break; + /* Check if HSI is ready and if RNG clock selection is HSI */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + /* Clock not enabled for RNG */ + else + { + frequency = 0U; + } + } +#if defined(LTDC) + else if (PeriphClk == RCC_PERIPHCLK_LTDC) + { + /* Get the current LTDC kernel source */ + srcclk = __HAL_RCC_GET_LTDC_SOURCE(); - default: + switch (srcclk) + { + case RCC_LTDCCLKSOURCE_PLL3: /* PLL3R is the clock source for LTDC */ - frequency = 0U; - break; - } + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; break; - case RCC_PERIPHCLK_DAC1: - /* Get the current DAC1 kernel source */ - srcclk = __HAL_RCC_GET_DAC1_SOURCE(); - /* Check if LSE is ready and if DAC1 clock selection is LSE */ - if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Check if LSI is ready and if DAC1 clock selection is LSI */ - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSI)) - { - frequency = LSI_VALUE; - } - /* Clock not enabled for DAC1*/ - else - { - frequency = 0U; - } + case RCC_LTDCCLKSOURCE_PLL2: /* PLL2R is the clock source for LTDC */ + + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_R_Frequency; break; default: - frequency = 0U; + + frequency = 0U; break; } } +#endif /* defined(LTDC) */ + +#if defined(USB_OTG_HS) + + else if (PeriphClk == RCC_PERIPHCLK_USBPHY) + { + /* Get the current USB_OTG_HS kernel source */ + srcclk = __HAL_RCC_GET_USBPHY_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_USBPHYCLKSOURCE_HSE)) + { + frequency = HSE_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_USBPHYCLKSOURCE_HSE_DIV2)) + { + frequency = HSE_VALUE >> 1U ; + } + else if (srcclk == RCC_USBPHYCLKSOURCE_PLL1) /* PLL1P */ + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_P_Frequency; + } + else if (srcclk == RCC_USBPHYCLKSOURCE_PLL1_DIV2) /* PLL1P_DIV2 */ + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = (pll1_clocks.PLL1_P_Frequency) / 2U; + } + /* Clock not enabled for USB_OTG_HS */ + else + { + frequency = 0U; + } + } +#endif /* defined(USB_OTG_HS) */ + + else + { + frequency = 0; + } return (frequency); } -/** - * @} - */ /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions * @brief Extended Clock management functions @@ -2406,7 +3102,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) * contains the configuration information for the PLL2 * @retval HAL status */ -HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) +HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(const RCC_PLL2InitTypeDef *PLL2Init) { uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; @@ -2480,6 +3176,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) } } } + return status; } @@ -2521,7 +3218,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void) * contains the configuration information for the PLL3 * @retval HAL status */ -HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef *PLL3Init) +HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(const RCC_PLL3InitTypeDef *PLL3Init) { uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; @@ -2593,6 +3290,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef *PLL3Init) } } } + return status; } @@ -2739,7 +3437,7 @@ void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk) * This parameter can be one of the following values: * @arg @ref RCC_MSIRANGE_4 Range 4 around 4 MHz (reset value) * @arg @ref RCC_MSIRANGE_5 Range 5 around 2 MHz - * @arg @ref RCC_MSIRANGE_6 Range 6 around 1.5 MHz + * @arg @ref RCC_MSIRANGE_6 Range 6 around 1.33 MHz * @arg @ref RCC_MSIRANGE_7 Range 7 around 1 MHz * @arg @ref RCC_MSIRANGE_8 Range 8 around 3.072 MHz * @retval None @@ -2751,6 +3449,25 @@ void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange) __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange); } +/** + * @brief Configure the MSIK range after standby mode. + * @note After Standby its frequency can be selected between 5 possible values (1, 1.33, 2, 3.072 or 4 MHz). + * @param MSIKRange MSIK range + * This parameter can be one of the following values: + * @arg @ref RCC_MSIKRANGE_4 Range 4 around 4 MHz (reset value) + * @arg @ref RCC_MSIKRANGE_5 Range 5 around 2 MHz + * @arg @ref RCC_MSIKRANGE_6 Range 6 around 1.33 MHz + * @arg @ref RCC_MSIKRANGE_7 Range 7 around 1 MHz + * @arg @ref RCC_MSIKRANGE_8 Range 8 around 3.072 MHz + * @retval None + */ +void HAL_RCCEx_StandbyMSIKRangeConfig(uint32_t MSIKRange) +{ + assert_param(IS_RCC_MSIK_STANDBY_CLOCK_RANGE(MSIKRange)); + + __HAL_RCC_MSIK_STANDBY_RANGE_CONFIG(MSIKRange); +} + /** * @brief Enable the LSE Clock Security System. * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled @@ -2773,15 +3490,57 @@ void HAL_RCCEx_DisableLSECSS(void) CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); } +/** + * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line. + * @note LSE Clock Security System Interrupt is mapped on EXTI line + * Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. + * @retval None + */ +void HAL_RCCEx_EnableLSECSS_IT(void) +{ + /* Enable LSE CSS */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; + + /* Enable IT on LSECSS EXTI Line */ + SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS); + /* Enable the RCC LSECSS EXTI Interrupt Rising Edge */ + SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS); +} + /** * @brief Handle the RCC LSE Clock Security System interrupt request. + * @note LSECSS EXTI is not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. * @retval None */ void HAL_RCCEx_LSECSS_IRQHandler(void) { + uint32_t falling_edge_flag; + uint32_t rising_edge_flag; + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) != 0U) { - /* RCC LSE Clock Security System interrupt user callback */ + /* Read Falling Edge flag on LSECSS EXTI interrupt */ + falling_edge_flag = READ_BIT(EXTI->FPR1, RCC_EXTI_LINE_LSECSS); + + /* Read Rising Edge flag on LSECSS EXTI interrupt */ + rising_edge_flag = READ_BIT(EXTI->RPR1, RCC_EXTI_LINE_LSECSS); + + /* Check Rising/falling Edge flag on LSECSS EXTI interrupt */ + if ((falling_edge_flag == RCC_EXTI_LINE_LSECSS) || \ + (rising_edge_flag == RCC_EXTI_LINE_LSECSS)) + { + if (rising_edge_flag == RCC_EXTI_LINE_LSECSS) + { + /* Clear the RCC LSECSS EXTI Rising Edge flag */ + WRITE_REG(EXTI->RPR1, RCC_EXTI_LINE_LSECSS); + } + if (falling_edge_flag == RCC_EXTI_LINE_LSECSS) + { + /* Clear the RCC LSECSS EXTI Falling Edge flag */ + WRITE_REG(EXTI->FPR1, RCC_EXTI_LINE_LSECSS); + } + } + /* RCC LSECSS interrupt user callback */ HAL_RCCEx_LSECSS_Callback(); } } @@ -2797,6 +3556,61 @@ __weak void HAL_RCCEx_LSECSS_Callback(void) */ } +/** + * @brief Enable the MSI PLL Unlock Interrupt & corresponding EXTI line. + * @note MSI PLL Unlock Interrupt is mapped on EXTI line + * Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. + * @retval None + */ +void HAL_RCCEx_EnableMSIPLLUNLCK_IT(void) +{ + /* Enable IT on MSI PLL Unlock EXTI Line */ + SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_MSIPLLUNLCK); + /* Enable the RCC MSI PLL UNLOCK EXTI Interrupt Rising Edge */ + SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_MSIPLLUNLCK); +} + +/** + * @brief Handle the RCC MSI PLL Unlock interrupt request. + * @note Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. + * @retval None + */ +void HAL_RCCEx_MSIPLLUNLCK_IRQHandler(void) +{ + uint32_t rising_edge_flag = READ_BIT(EXTI->RPR1, RCC_EXTI_LINE_MSIPLLUNLCK); + uint32_t falling_edge_flag = READ_BIT(EXTI->FPR1, RCC_EXTI_LINE_MSIPLLUNLCK); + + /* Check Rising/falling Edge flag on MSI PLL UNLOCK EXTI interrupt */ + if ((rising_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK) || \ + (falling_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK)) + { + if (rising_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK) + { + /* Clear the RCC MSI PLL UNLOCK EXTI Rising Edge flag */ + WRITE_REG(EXTI->RPR1, RCC_EXTI_LINE_MSIPLLUNLCK); + } + if (falling_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK) + { + /* Clear the RCC MSI PLL UNLOCK EXTI Falling Edge flag */ + WRITE_REG(EXTI->FPR1, RCC_EXTI_LINE_MSIPLLUNLCK); + } + /* RCC MSI PLL Unlock interrupt user callback */ + HAL_RCCEx_MSIPLLUNLCK_Callback(); + } +} + +/** + * @brief RCCEx RCC MSI PLL Unlock interrupt callback. + * @note Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. + * @retval none + */ +__weak void HAL_RCCEx_MSIPLLUNLCK_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_MSIPLLUNLCK_Callback should be implemented in the user file + */ +} + /** * @brief Select the Low Speed clock source to output on LSCO pin (PA2). * @param LSCOSource specifies the Low Speed clock source to output. @@ -2807,23 +3621,12 @@ __weak void HAL_RCCEx_LSECSS_Callback(void) */ void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) { - GPIO_InitTypeDef gpio_initstruct; FlagStatus pwrclkchanged = RESET; FlagStatus backupchanged = RESET; /* Check the parameters */ assert_param(IS_RCC_LSCOSOURCE(LSCOSource)); - /* LSCO Pin Clock Enable */ - LSCO_CLK_ENABLE(); - - /* Configure the LSCO pin in analog mode */ - gpio_initstruct.Pin = LSCO_PIN; - gpio_initstruct.Mode = GPIO_MODE_ANALOG; - gpio_initstruct.Speed = GPIO_SPEED_FREQ_HIGH; - gpio_initstruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(LSCO_GPIO_PORT, &gpio_initstruct); - /* Update LSCOSEL clock source in Backup Domain control register */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) { @@ -2904,7 +3707,6 @@ void HAL_RCCEx_DisableMSIPLLMode(void) { CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN); } - /** * @} */ @@ -2930,7 +3732,7 @@ void HAL_RCCEx_DisableMSIPLLMode(void) (+++) Default values can be set for frequency Error Measurement (reload and error limit) and also HSI48 oscillator smooth trimming. (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate - directly reload value with target and sychronization frequencies values + directly reload value with target and synchronization frequencies values (##) Call function HAL_RCCEx_CRSConfig which (+++) Resets CRS registers to their default values. (+++) Configures CRS registers with synchronization configuration @@ -3369,11 +4171,11 @@ static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource) * @brief Configure the PLL2 VCI ranges, multiplication and division factors and enable it * @param pll2: Pointer to an RCC_PLL2InitTypeDef structure that * contains the configuration parameters as well as VCI clock ranges. - * @note PLL2 is temporary disable to apply new parameters + * @note PLL2 is temporary disabled to apply new parameters * * @retval HAL status */ -static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2) +static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2) { uint32_t tickstart; @@ -3441,13 +4243,13 @@ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2) } /** - * @brief Configure the parameters N & P & optionally M of PLL3 and enable PLL3 output clock(s). - * @param pll3 pointer to an RCC_PLL3InitTypeDef structure that - * contains the configuration parameters N & P & optionally M as well as PLL3 output clock(s) - * @note PLL3 is temporary disable to apply new parameters + * @brief Configure the PLL3 VCI ranges, multiplication and division factors and enable it + * @param pll3: Pointer to an RCC_PLL3InitTypeDef structure that + * contains the configuration parameters as well as VCI clock ranges. + * @note PLL3 is temporary disabled to apply new parameters * @retval HAL status */ -static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3) +static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3) { uint32_t tickstart; assert_param(IS_RCC_PLLSOURCE(pll3->PLL3Source)); diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rcc_ex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rcc_ex.h index e32ee69fa84..c516bff14fb 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rcc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rcc_ex.h @@ -46,7 +46,7 @@ extern "C" { typedef struct { uint32_t PLL2Source; /*!< RCC_PLL2Source: PLL2 entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ + This parameter must be a value of @ref RCC_PLL_Clock_Source */ uint32_t PLL2M; /*!< PLL2M: Division factor for PLL2 VCO input clock. This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ @@ -55,23 +55,22 @@ typedef struct This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ uint32_t PLL2P; /*!< PLL2P: Division factor for system clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 128 */ + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ uint32_t PLL2Q; /*!< PLL2Q: Division factor for peripheral clocks. This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ uint32_t PLL2R; /*!< PLL2R: Division factor for peripheral clocks. - This parameter must be a number between Min_Data = 1 and Max_Data = 128 - odd division factors are not allowed */ + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ - uint32_t PLL2RGE; /*!PLL3CFGR, (__PLL3_CLOCKOUT__)) -/** @brief Macro to configure the ADC1, ADC4 and DAC interface clock. +/** @brief Macro to configure the ADC1, ADC2, ADC4 and DAC interface clock. * @param __ADCDAC_CLKSOURCE__ specifies the ADC1, ADC4 and DAC digital interface clock source. * This parameter can be one of the following values: - * @arg @ref RCC_ADCDACCLKSOURCE_HCLK clock selected as ADC1, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK clock selected as ADC1, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_PLL2 clock selected as ADC1, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_HSE clock selected as ADC1, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_HSI clock selected as ADC1, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_MSIK clock selected as ADC1, ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_HCLK clock selected as ADC1, ADC2, ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK clock selected as ADC1, ADC2 ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_PLL2 clock selected as ADC1, ADC2 ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_HSE clock selected as ADC1, ADC2 ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_HSI clock selected as ADC1, ADC2 ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_MSIK clock selected as ADC1, ADC2 ADC4 and DAC clock * @retval None */ #define __HAL_RCC_ADCDAC_CONFIG(__ADCDAC_CLKSOURCE__) \ @@ -1186,12 +1377,12 @@ typedef struct /** @brief Macro to get the ADCDAC clock source. * @retval The clock source can be one of the following values: - * @arg @ref RCC_ADCDACCLKSOURCE_HCLK clock used as ADC1, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK clock used as ADC1, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_PLL2 clock used as ADC1, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_HSE clock used as ADC1, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_HSI clock used as ADC1, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_MSIK clock used as ADC1, ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_HCLK clock used as ADC1, ADC2, ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK clock used as ADC1, ADC2, ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_PLL2 clock used as ADC1, ADC2, ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_HSE clock used as ADC1, ADC2, ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_HSI clock used as ADC1, ADC2, ADC4 and DAC clock + * @arg @ref RCC_ADCDACCLKSOURCE_MSIK clock used as ADC1, ADC2, ADC4 and DAC clock */ #define __HAL_RCC_GET_ADCDAC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_ADCDACSEL))) @@ -1204,7 +1395,7 @@ typedef struct * @arg RCC_CLK48CLKSOURCE_MSIK : MSIK selected as CLK48 source */ #define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, (uint32_t)(__CLK48_SOURCE__)) + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ICLKSEL, (uint32_t)(__CLK48_SOURCE__)) /** @brief macro to get the CLK48 source. * @retval The clock source can be one of the following values: @@ -1213,7 +1404,7 @@ typedef struct * @arg RCC_CLK48CLKSOURCE_PLL1 : PLL1 used as CLK48 source * @arg RCC_CLK48CLKSOURCE_MSIK : MSIK used as CLK48 source */ -#define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL))) +#define __HAL_RCC_GET_ICLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ICLKSEL))) /** @brief Macro to configure the FDCAN1 kernel clock (FDCAN1CLK). * @param __FDCAN1_CLKSOURCE__ specifies the FDCAN1 kernel clock source. @@ -1441,6 +1632,54 @@ typedef struct */ #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C4SEL))) +#if defined(I2C5) +/** @brief Macro to configure the I2C5 clock (I2C5CLK). + * + * @param __I2C5_CLKSOURCE__ specifies the I2C5 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C5CLKSOURCE_PCLK1 PCLK1 selected as I2C5 clock + * @arg @ref RCC_I2C5CLKSOURCE_SYSCLK System Clock selected as I2C5 clock + * @arg @ref RCC_I2C5CLKSOURCE_HSI HSI selected as I2C5 clock + * @arg @ref RCC_I2C5CLKSOURCE_MSIK MSIK selected as I2C5 clock + * @retval None + */ +#define __HAL_RCC_I2C5_CONFIG(__I2C5_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C5SEL, (uint32_t)(__I2C5_CLKSOURCE__)) + +/** @brief Macro to get the I2C5 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C5CLKSOURCE_PCLK1 PCLK1 selected as I2C5 clock + * @arg @ref RCC_I2C5CLKSOURCE_SYSCLK System Clock selected as I2C5 clock + * @arg @ref RCC_I2C5CLKSOURCE_HSI HSI selected as I2C5 clock + * @arg @ref RCC_I2C5CLKSOURCE_MSIK MSIK selected as I2C5 clock + */ +#define __HAL_RCC_GET_I2C5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C5SEL))) +#endif /* I2C5 */ + +#if defined(I2C6) +/** @brief Macro to configure the I2C6 clock (I2C6CLK). + * + * @param __I2C6_CLKSOURCE__ specifies the I2C6 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C6CLKSOURCE_PCLK1 PCLK1 selected as I2C6 clock + * @arg @ref RCC_I2C6CLKSOURCE_SYSCLK System Clock selected as I2C6 clock + * @arg @ref RCC_I2C6CLKSOURCE_HSI HSI selected as I2C6 clock + * @arg @ref RCC_I2C6CLKSOURCE_MSIK MSIK selected as I2C6 clock + * @retval None + */ +#define __HAL_RCC_I2C6_CONFIG(__I2C6_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C6SEL, (uint32_t)(__I2C6_CLKSOURCE__)) + +/** @brief Macro to get the I2C6 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C6CLKSOURCE_PCLK1 PCLK1 selected as I2C6 clock + * @arg @ref RCC_I2C6CLKSOURCE_SYSCLK System Clock selected as I2C6 clock + * @arg @ref RCC_I2C6CLKSOURCE_HSI HSI selected as I2C6 clock + * @arg @ref RCC_I2C6CLKSOURCE_MSIK MSIK selected as I2C6 clock + */ +#define __HAL_RCC_GET_I2C6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C6SEL))) +#endif /* I2C6 */ + /** @brief Macro to configure the USART1 clock (USART1CLK). * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. * This parameter can be one of the following values: @@ -1462,6 +1701,7 @@ typedef struct */ #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART1SEL))) +#if defined(USART2) /** @brief Macro to configure the USART2 clock (USART2CLK). * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. * This parameter can be one of the following values: @@ -1482,6 +1722,7 @@ typedef struct * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock */ #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART2SEL))) +#endif /* USART2 */ /** @brief Macro to configure the USART3 clock (USART3CLK). * @@ -1548,6 +1789,30 @@ typedef struct */ #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART5SEL))) +#if defined(USART6) +/** @brief Macro to configure the USART6 clock (USART6CLK). + * + * @param __USART6_CLKSOURCE__ specifies the USART6 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART6CLKSOURCE_PCLK1 PCLK1 selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_SYSCLK System Clock selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock + * @retval None + */ +#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__)) + +/** @brief Macro to get the USART6 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART6CLKSOURCE_PCLK1 PCLK1 selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_SYSCLK System Clock selected as USART6 clock + * @arg @ref RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock + */ +#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USART6SEL))) +#endif /* USART6 */ + /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). * * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. @@ -1572,7 +1837,6 @@ typedef struct */ #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL))) - /** @brief Macro to configure the OctoSPI clock. * @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source. * This parameter can be one of the following values: @@ -1594,6 +1858,29 @@ typedef struct */ #define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OCTOSPISEL))) +#if defined(HSPI1) +/** @brief Macro to configure the HexaSPI clock. + * @param __HSPI_CLKSOURCE__ specifies the HexaSPI clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_HSPICLKSOURCE_SYSCLK System Clock selected as HexaSPI clock + * @arg @ref RCC_HSPICLKSOURCE_PLL1 PLL1 Q divider clock selected as HexaSPI clock + * @arg @ref RCC_HSPICLKSOURCE_PLL2 PLL2 Q divider clock selected as HexaSPI clock + * @arg @ref RCC_HSPICLKSOURCE_PLL3 PLL3 R divider clock selected as HexaSPI clock + * @retval None + */ +#define __HAL_RCC_HSPI_CONFIG(__HSPI_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_HSPISEL, (uint32_t)(__HSPI_CLKSOURCE__)) + +/** @brief Macro to get the HexaSPI clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_HSPICLKSOURCE_SYSCLK System Clock selected as HexaSPI clock + * @arg @ref RCC_HSPICLKSOURCE_PLL1 PLL1 Q divider clock selected as HexaSPI clock + * @arg @ref RCC_HSPICLKSOURCE_PLL2 PLL2 Q divider clock selected as HexaSPI clock + * @arg @ref RCC_HSPICLKSOURCE_PLL3 PLL3 R divider clock selected as HexaSPI clock + */ +#define __HAL_RCC_GET_HSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_HSPISEL))) +#endif /* HSPI1 */ + /** @brief Macro to configure the SDMMC1/2 clock (SDMMCCLK). * @param __SDMMC_CLKSOURCE__: specifies the SDMMC1/2 clock source. * This parameter can be one of the following values: @@ -1673,6 +1960,7 @@ typedef struct */ #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL))) +#if defined(SAI2) /** * @brief Macro to configure the SAI2 clock source. * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived @@ -1697,6 +1985,7 @@ typedef struct * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16 */ #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL))) +#endif /* SAI2 */ /** @brief Macro to configure the MDF1 clock. * @param __MDF1_CLKSOURCE__ specifies the MDF1 clock source. @@ -1761,6 +2050,101 @@ typedef struct */ #define __HAL_RCC_GET_DAC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_DAC1SEL))) +#if defined(LTDC) + +/** @brief Macro to configure the LTDC clock. + * @param __LTDC_CLKSOURCE__ specifies the LTDC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LTDCCLKSOURCE_PLL3 PLL3 divider R clock selected as LTDC kernel clock + * @arg @ref RCC_LTDCCLKSOURCE_PLL2 PLL2 divider R clock selected as LTDC kernel clock + * @retval None + */ +#define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LTDCSEL, (__LTDC_CLKSOURCE__)) + +/** @brief Macro to get the LTDC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LTDCCLKSOURCE_PLL3 PLL3 divider R clock selected as LTDC kernel clock + * @arg @ref RCC_LTDCCLKSOURCE_PLL2 PLL2 divider R clock selected as LTDC kernel clock + */ +#define __HAL_RCC_GET_LTDC_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LTDCSEL)) + +#endif /* LTDC */ + +#if defined(DSI) + +/** @brief Macro to configure the DSI clock. + * @param __DSI_CLKSOURCE__ specifies the DSI clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock + * @arg @ref RCC_DSICLKSOURCE_PLL3 PLL3 divider P clock selected as DSI clock (low power case) + * @retval None + */ +#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSIHOSTSEL, (__DSI_CLKSOURCE__)) + +/** @brief Macro to get the DSI clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock + * @arg @ref RCC_DSICLKSOURCE_PLL3 PLL3 divider P clock selected as DSI clock (low power case) + */ +#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSIHOSTSEL)) + +#endif /* DSI */ + +#if defined(USB_OTG_HS) + +/** @brief Macro to configure the USB PHY clock. + * @param __USBPHY_CLKSOURCE__ specifies the USB PHY clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USBPHYCLKSOURCE_HSE HSE clock selected as USB PHY clock + * @arg @ref RCC_USBPHYCLKSOURCE_HSE_DIV2 HSE clock div by 2 selected as USB PHY clock + * @arg @ref RCC_USBPHYCLKSOURCE_PLL1 PLL1 P divider clock selected as USB PHY clock + * @arg @ref RCC_USBPHYCLKSOURCE_PLL1_DIV2 PLL1 P divider clock div by 2 selected as USB PHY clock + * @retval None + */ +#define __HAL_RCC_USBPHY_CONFIG(__USBPHY_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBPHYCSEL, (__USBPHY_CLKSOURCE__)) + +/** @brief Macro to get the USB PHY clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USBPHYCLKSOURCE_HSE HSE clock selected as USB PHY clock + * @arg @ref RCC_USBPHYCLKSOURCE_HSE_DIV2 HSE clock div by 2 selected as USB PHY clock + * @arg @ref RCC_USBPHYCLKSOURCE_PLL1 PLL1 P divider clock selected as USB PHY clock + * @arg @ref RCC_USBPHYCLKSOURCE_PLL1_DIV2 PLL1 P divider clock div by 2 selected as USB PHY clock + */ +#define __HAL_RCC_GET_USBPHY_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USBPHYCSEL)) + +#endif /* USB_OTG_HS */ + +#if defined(RCC_CFGR2_PPRE_DPHY) + +/** @brief Macro to configure the DPHY clock. + * @param __PRESCALER__ specifies the DPHY clock source prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_HCLK_DIV1 HCLK divided by 1 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV2 HCLK divided by 2 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV4 HCLK divided by 4 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV8 HCLK divided by 8 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV16 HCLK divided by 16 selected as DPHY clock + * @retval None + */ +#define __HAL_RCC_DPHY_CONFIG(__PRESCALER__) \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE_DPHY, (__PRESCALER__) << 8UL) + +/** @brief Macro to get the DPHY clock prescaler configuration. + * @retval The clock source prescaler can be one of the following values: + * @arg @ref RCC_HCLK_DIV1 HCLK divided by 1 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV2 HCLK divided by 2 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV4 HCLK divided by 4 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV8 HCLK divided by 8 selected as DPHY clock + * @arg @ref RCC_HCLK_DIV16 HCLK divided by 16 selected as DPHY clock + * @retval None + */ +#define __HAL_RCC_GET_DPHY_CONFIG() (READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE_DPHY) >> 8UL) + +#endif /* defined(RCC_CFGR2_PPRE_DPHY) */ + #if defined(CRS) /** @@ -1929,12 +2313,12 @@ typedef struct * @{ */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit); +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPeriphClkInit); void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit); -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); -void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks); -void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks); -void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk); +void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks); +void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks); +void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks); /** * @} */ @@ -1943,9 +2327,9 @@ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks); * @{ */ -HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init); +HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(const RCC_PLL2InitTypeDef *PLL2Init); HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); -HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef *PLL3Init); +HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(const RCC_PLL3InitTypeDef *PLL3Init); HAL_StatusTypeDef HAL_RCCEx_DisablePLL3(void); HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLFastStartup(void); HAL_StatusTypeDef HAL_RCCEx_DisableMSIPLLFastStartup(void); @@ -1953,15 +2337,19 @@ HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLModeSelection(uint32_t MSIPLLModeSelecti void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk); void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange); +void HAL_RCCEx_StandbyMSIKRangeConfig(uint32_t MSIKRange); void HAL_RCCEx_EnableLSECSS(void); void HAL_RCCEx_DisableLSECSS(void); +void HAL_RCCEx_EnableLSECSS_IT(void); +void HAL_RCCEx_EnableMSIPLLUNLCK_IT(void); void HAL_RCCEx_LSECSS_IRQHandler(void); void HAL_RCCEx_LSECSS_Callback(void); +void HAL_RCCEx_MSIPLLUNLCK_IRQHandler(void); +void HAL_RCCEx_MSIPLLUNLCK_Callback(void); void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); void HAL_RCCEx_DisableLSCO(void); void HAL_RCCEx_EnableMSIPLLMode(void); void HAL_RCCEx_DisableMSIPLLMode(void); - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rng.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rng.c index fb402fdb7da..02131b687f6 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rng.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rng.c @@ -42,8 +42,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_RNG_RegisterCallback() to register a user callback. - Function @ref HAL_RNG_RegisterCallback() allows to register following callbacks: + Use Function HAL_RNG_RegisterCallback() to register a user callback. + Function HAL_RNG_RegisterCallback() allows to register following callbacks: (+) ErrorCallback : RNG Error Callback. (+) MspInitCallback : RNG MspInit. (+) MspDeInitCallback : RNG MspDeInit. @@ -51,9 +51,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_RNG_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. - @ref HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, + Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default + weak (overridden) function. + HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) ErrorCallback : RNG Error Callback. @@ -62,16 +62,16 @@ [..] For specific callback ReadyDataCallback, use dedicated register callbacks: - respectively @ref HAL_RNG_RegisterReadyDataCallback() , @ref HAL_RNG_UnRegisterReadyDataCallback(). + respectively HAL_RNG_RegisterReadyDataCallback() , HAL_RNG_UnRegisterReadyDataCallback(). [..] - By default, after the @ref HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: - example @ref HAL_RNG_ErrorCallback(). + By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET + all callbacks are set to the corresponding weak (overridden) functions: + example HAL_RNG_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_RNG_Init() - and @ref HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_RNG_Init() and @ref HAL_RNG_DeInit() + reset to the legacy weak (overridden) functions in the HAL_RNG_Init() + and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -80,13 +80,13 @@ in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_RNG_RegisterCallback() before calling @ref HAL_RNG_DeInit() - or @ref HAL_RNG_Init() function. + using HAL_RNG_RegisterCallback() before calling HAL_RNG_DeInit() + or HAL_RNG_Init() function. [..] When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -200,7 +200,6 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Clock Error Detection Configuration when CONDRT bit is set to 1 */ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST); - /* Writing bit CONDRST=0 */ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); @@ -386,8 +385,6 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hrng); if (HAL_RNG_STATE_READY == hrng->State) { @@ -441,14 +438,12 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hrng); return status; } /** * @brief Unregister an RNG Callback - * RNG callabck is redirected to the weak predefined callback + * RNG callback is redirected to the weak predefined callback * @param hrng RNG handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -461,8 +456,6 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hrng); if (HAL_RNG_STATE_READY == hrng->State) { @@ -516,8 +509,6 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hrng); return status; } @@ -680,8 +671,9 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t be used as it may not have enough entropy */ if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) { - /* Update the error code */ + /* Update the error code and status */ hrng->ErrorCode = HAL_RNG_ERROR_SEED; + status = HAL_ERROR; /* Clear bit DRDY */ CLEAR_BIT(hrng->Instance->SR, RNG_FLAG_DRDY); } @@ -844,7 +836,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) * the configuration information for RNG. * @retval random value */ -uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng) +uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng) { return (hrng->RandomNumber); } @@ -911,7 +903,7 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) * the configuration information for RNG. * @retval HAL state */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) +HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng) { return hrng->State; } @@ -921,7 +913,7 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) * @param hrng: pointer to a RNG_HandleTypeDef structure. * @retval RNG Error Code */ -uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng) +uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng) { /* Return RNG Error Code */ return hrng->ErrorCode; @@ -1031,3 +1023,4 @@ HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng) /** * @} */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rng.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rng.h index 1a07a943d8c..aa1a5bb43a2 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rng.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rng.h @@ -317,7 +317,7 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng); */ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit); HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng); -uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng); void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng); void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng); @@ -330,8 +330,8 @@ void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit); /** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions * @{ */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng); -uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng); +HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng); /** * @} */ @@ -386,3 +386,4 @@ HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng); #endif /* STM32U5xx_HAL_RNG_H */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rng_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rng_ex.c index c2f225b700c..ece25420aa9 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rng_ex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rng_ex.c @@ -30,7 +30,7 @@ #if defined(RNG) -/** @addtogroup RNGEx +/** @addtogroup RNG_Ex * @brief RNG Extended HAL module driver. * @{ */ @@ -41,7 +41,7 @@ /* Private defines -----------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Constants RNGEx Private Constants +/** @addtogroup RNG_Ex_Private_Constants * @{ */ #define RNG_TIMEOUT_VALUE 2U @@ -53,11 +53,11 @@ /* Private functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RNGEx_Exported_Functions +/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions * @{ */ -/** @addtogroup RNGEx_Exported_Functions_Group1 +/** @defgroup RNG_Ex_Exported_Functions_Group1 Configuration and lock functions * @brief Configuration functions * @verbatim @@ -82,7 +82,7 @@ * @retval HAL status */ -HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf) +HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf) { uint32_t tickstart; uint32_t cr_value; @@ -123,7 +123,7 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef | (pConf->Config3 << RNG_CR_RNG_CONFIG3_Pos)); MODIFY_REG(hrng->Instance->CR, RNG_CR_NISTC | RNG_CR_CLKDIV | RNG_CR_RNG_CONFIG1 - | RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3, + | RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3 | RNG_CR_ARDIS, (uint32_t)(RNG_CR_CONDRST | cr_value)); /* RNG health test control in accordance with NIST */ @@ -269,12 +269,12 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) * @} */ -/** @addtogroup RNGEx_Exported_Functions_Group2 +/** @defgroup RNG_Ex_Exported_Functions_Group2 Recover from seed error function * @brief Recover from seed error function * @verbatim =============================================================================== - ##### Configuration and lock functions ##### + ##### Recover from seed error function ##### =============================================================================== [..] This section provide function allowing to: (+) Recover from a seed error @@ -336,3 +336,4 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) /** * @} */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rng_ex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rng_ex.h index cf62366f6f1..878598859ff 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rng_ex.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rng_ex.h @@ -34,19 +34,19 @@ extern "C" { #if defined(RNG) #if defined(RNG_CR_CONDRST) -/** @defgroup RNGEx RNGEx +/** @defgroup RNG_Ex RNG_Ex * @brief RNG Extension HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ -/** @defgroup RNGEx_Exported_Types RNGEx Exported Types - * @brief RNGEx Exported types +/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types + * @brief RNG_Ex Exported types * @{ */ /** - * @brief RNGEX Configuration Structure definition + * @brief RNG_Ex Configuration Structure definition */ typedef struct @@ -55,11 +55,11 @@ typedef struct uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */ uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can - be a value of @ref RNGEX_Clock_Divider_Factor */ + be a value of @ref RNG_Ex_Clock_Divider_Factor */ uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a - value of @ref RNGEX_NIST_Compliance */ + value of @ref RNG_Ex_NIST_Compliance */ uint32_t AutoReset; /*!< automatic reset When a noise source error occurs - value of @ref RNGEX_Auto_Reset */ + value of @ref RNG_Ex_Auto_Reset */ uint32_t HealthTest; /*!< RNG health test control must be a value between 0x0FFCABFF and 0x00005200 */ } RNG_ConfigTypeDef; @@ -69,11 +69,11 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup RNGEX_Exported_Constants RNGEX Exported Constants +/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants * @{ */ -/** @defgroup RNGEX_Clock_Divider_Factor Value used to configure an internal +/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal * programmable divider acting on the incoming RNG clock * @{ */ @@ -112,7 +112,7 @@ typedef struct * @} */ -/** @defgroup RNGEX_NIST_Compliance NIST Compliance configuration +/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration * @{ */ #define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ @@ -121,7 +121,7 @@ typedef struct /** * @} */ -/** @defgroup RNGEX_Auto_Reset Auto Reset configuration +/** @defgroup RNG_Ex_Auto_Reset Auto Reset configuration * @{ */ #define RNG_ARDIS_ENABLE (0x00000000UL) /*!< automatic reset after seed error*/ @@ -136,7 +136,7 @@ typedef struct */ /* Private types -------------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Types RNGEx Private Types +/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types * @{ */ @@ -145,7 +145,7 @@ typedef struct */ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Variables RNGEx Private Variables +/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables * @{ */ @@ -154,7 +154,7 @@ typedef struct */ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Constants RNGEx Private Constants +/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants * @{ */ @@ -163,7 +163,7 @@ typedef struct */ /* Private macros ------------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Macros RNGEx Private Macros +/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros * @{ */ @@ -202,7 +202,7 @@ typedef struct */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Functions RNGEx Private Functions +/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions * @{ */ @@ -211,14 +211,14 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ -/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions +/** @addtogroup RNG_Ex_Exported_Functions * @{ */ -/** @addtogroup RNGEx_Exported_Functions_Group1 +/** @addtogroup RNG_Ex_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf); +HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf); HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf); HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); @@ -226,7 +226,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); * @} */ -/** @addtogroup RNGEx_Exported_Functions_Group2 +/** @addtogroup RNG_Ex_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); @@ -259,4 +259,5 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); #endif -#endif /* STM32U5xx_HAL_RNGEX_H */ +#endif /* STM32U5xx_HAL_RNG_EX_H */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rtc.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rtc.c index 208ee460a27..71f7bb0bc91 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rtc.c @@ -362,39 +362,50 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Enter Initialization mode */ - status = RTC_EnterInitMode(hrtc); - if (status == HAL_OK) + /* Check if the calendar has been not initialized */ + if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) { - /* Clear RTC_CR FMT, OSEL and POL Bits */ - CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); - /* Set RTC_CR register */ - SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); - - /* Configure the RTC PRER */ - WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Configure the Binary mode */ - MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU); - - /* Exit Initialization mode */ - status = RTC_ExitInitMode(hrtc); + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); if (status == HAL_OK) { - MODIFY_REG(RTC->CR, \ - RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \ - hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); + /* Clear RTC_CR FMT, OSEL and POL Bits */ + CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); + /* Set RTC_CR register */ + SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); + + /* Configure the RTC PRER */ + WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); + + /* Configure the Binary mode */ + MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + if (status == HAL_OK) + { + MODIFY_REG(RTC->CR, \ + RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \ + hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); + } } - } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + else + { + /* Calendar is already initialized */ + /* Set flag to OK */ + status = HAL_OK; + } if (status == HAL_OK) { + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; } } @@ -1056,7 +1067,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim * @param hrtc RTC handle * @retval None */ -void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc) +void HAL_RTC_DST_Add1Hour(const RTC_HandleTypeDef *hrtc) { UNUSED(hrtc); __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); @@ -1070,7 +1081,7 @@ void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval None */ -void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc) +void HAL_RTC_DST_Sub1Hour(const RTC_HandleTypeDef *hrtc) { UNUSED(hrtc); __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); @@ -1084,7 +1095,7 @@ void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval None */ -void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc) +void HAL_RTC_DST_SetStoreOperation(const RTC_HandleTypeDef *hrtc) { UNUSED(hrtc); __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); @@ -1097,7 +1108,7 @@ void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval None */ -void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc) +void HAL_RTC_DST_ClearStoreOperation(const RTC_HandleTypeDef *hrtc) { UNUSED(hrtc); __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); @@ -1110,7 +1121,7 @@ void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval operation see RTC_StoreOperation_Definitions */ -uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc) +uint32_t HAL_RTC_DST_ReadStoreOperation(const RTC_HandleTypeDef *hrtc) { UNUSED(hrtc); return READ_BIT(RTC->CR, RTC_CR_BKP); @@ -1141,20 +1152,21 @@ uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc) * @arg RTC_FORMAT_BCD: BCD format * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +HAL_StatusTypeDef HAL_RTC_GetTime(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { uint32_t tmpreg; UNUSED(hrtc); - /* Get subseconds structure field from the corresponding register*/ + /* Get subseconds structure field from the corresponding register */ sTime->SubSeconds = READ_REG(RTC->SSR); + if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) != RTC_BINARY_ONLY) { /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); - /* Get SecondFraction structure field from the corresponding register field*/ + /* Get SecondFraction structure field from the corresponding register field */ sTime->SecondFraction = (uint32_t)(READ_REG(RTC->PRER) & RTC_PRER_PREDIV_S); /* Get the TR register */ @@ -1175,6 +1187,15 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds); } } + else + { + /* Initialize structure fields */ + sTime->Hours = 0U; + sTime->Minutes = 0U; + sTime->Seconds = 0U; + sTime->TimeFormat = 0U; + sTime->SecondFraction = 0U; + } return HAL_OK; } @@ -1273,7 +1294,7 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat * @arg RTC_FORMAT_BCD: BCD format * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +HAL_StatusTypeDef HAL_RTC_GetDate(const RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { uint32_t datetmpreg; @@ -1799,7 +1820,8 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar * @arg RTC_FORMAT_BCD: BCD format * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) +HAL_StatusTypeDef HAL_RTC_GetAlarm(const RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, + uint32_t Format) { uint32_t tmpreg; uint32_t subsecondtmpreg; @@ -1867,7 +1889,7 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) /* Get interrupt status */ uint32_t tmp = READ_REG(RTC->SMISR); - if ((tmp & RTC_SMISR_ALRAMF) != 0u) + if ((tmp & RTC_SMISR_ALRAMF) != 0U) { /* Clear the AlarmA interrupt pending bit */ WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); @@ -1879,7 +1901,7 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } - if ((tmp & RTC_SMISR_ALRBMF) != 0u) + if ((tmp & RTC_SMISR_ALRBMF) != 0U) { /* Clear the AlarmB interrupt pending bit */ WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); @@ -1960,8 +1982,11 @@ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + uint32_t tickstart = HAL_GetTick(); while (READ_BIT(RTC->SR, RTC_SR_ALRAF) == 0U) @@ -1970,8 +1995,15 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->SR, RTC_SR_ALRAF) == 0U) + { + return HAL_TIMEOUT; + } + else + { + break; + } } } } @@ -1979,9 +2011,6 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T /* Clear the Alarm interrupt pending bit */ WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - return HAL_OK; } @@ -2022,7 +2051,6 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { uint32_t tickstart; - UNUSED(hrtc); /* Clear RSF flag */ CLEAR_BIT(RTC->ICSR, RTC_ICSR_RSF); @@ -2033,7 +2061,17 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == 0U) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + else + { + break; + } } } @@ -2063,7 +2101,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval HAL state */ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc) +HAL_RTCStateTypeDef HAL_RTC_GetState(const RTC_HandleTypeDef *hrtc) { /* Return RTC handle state */ return hrtc->State; @@ -2091,7 +2129,6 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; - UNUSED(hrtc); /* Check if the Initialization mode is set */ if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) { @@ -2104,8 +2141,18 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - status = HAL_TIMEOUT; - hrtc->State = HAL_RTC_STATE_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) + { + status = HAL_TIMEOUT; + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + } + else + { + break; + } } } } diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rtc.h index 3aa5ee084a3..86d45b99982 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rtc.h @@ -288,7 +288,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_Hour_Formats RTC Hour Formats * @{ */ -#define RTC_HOURFORMAT_24 0x00000000u +#define RTC_HOURFORMAT_24 0U #define RTC_HOURFORMAT_12 RTC_CR_FMT /** * @} @@ -297,7 +297,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition * @{ */ -#define RTC_OUTPUT_DISABLE 0x00000000u +#define RTC_OUTPUT_DISABLE 0U #define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0 #define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1 #define RTC_OUTPUT_WAKEUP RTC_CR_OSEL @@ -309,7 +309,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions * @{ */ -#define RTC_OUTPUT_POLARITY_HIGH 0x00000000u +#define RTC_OUTPUT_POLARITY_HIGH 0U #define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL /** * @} @@ -318,7 +318,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT * @{ */ -#define RTC_OUTPUT_TYPE_PUSHPULL 0x00000000u +#define RTC_OUTPUT_TYPE_PUSHPULL 0U #define RTC_OUTPUT_TYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE /** * @} @@ -327,7 +327,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_Output_PullUp_ALARM_OUT RTC Output Pull-Up ALARM OUT * @{ */ -#define RTC_OUTPUT_PULLUP_NONE 0x00000000u +#define RTC_OUTPUT_PULLUP_NONE 0U #define RTC_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU /** * @} @@ -336,7 +336,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap * @{ */ -#define RTC_OUTPUT_REMAP_NONE 0x00000000u +#define RTC_OUTPUT_REMAP_NONE 0U #define RTC_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN /** * @} @@ -345,8 +345,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions * @{ */ -#define RTC_HOURFORMAT12_AM 0x0u -#define RTC_HOURFORMAT12_PM 0x1u +#define RTC_HOURFORMAT12_AM 0U +#define RTC_HOURFORMAT12_PM 1U /** * @} */ @@ -356,7 +356,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to */ #define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H #define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H -#define RTC_DAYLIGHTSAVING_NONE 0x00000000u +#define RTC_DAYLIGHTSAVING_NONE 0U /** * @} */ @@ -364,7 +364,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions * @{ */ -#define RTC_STOREOPERATION_RESET 0x00000000u +#define RTC_STOREOPERATION_RESET 0U #define RTC_STOREOPERATION_SET RTC_CR_BKP /** * @} @@ -373,8 +373,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions * @{ */ -#define RTC_FORMAT_BIN 0x00000000u -#define RTC_FORMAT_BCD 0x00000001u +#define RTC_FORMAT_BIN 0U +#define RTC_FORMAT_BCD 1U /** * @} */ @@ -419,7 +419,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions * @{ */ -#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000u +#define RTC_ALARMDATEWEEKDAYSEL_DATE 0U #define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /** @@ -429,7 +429,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions * @{ */ -#define RTC_ALARMMASK_NONE 0x00000000u +#define RTC_ALARMMASK_NONE 0U #define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 #define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 #define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 @@ -453,8 +453,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_ALARM_Flag_AutoClear_Definitions RTC Alarms Flag Auto Clear Definitions * @{ */ -#define ALARM_FLAG_AUTOCLR_ENABLE 0x00000001u -#define ALARM_FLAG_AUTOCLR_DISABLE 0x00000000u +#define ALARM_FLAG_AUTOCLR_ENABLE 1U +#define ALARM_FLAG_AUTOCLR_DISABLE 0U /** * @} */ @@ -462,7 +462,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions * @{ */ -#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000u /*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */ +#define RTC_ALARMSUBSECONDMASK_ALL 0U /*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */ #define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] not used in Alarmcomparison. Only SS[0] is compared. */ #define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 /*!< SS[14:2] not used in Alarm comparison. Only SS[1:0] are compared */ #define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1) /*!< SS[14:3] not used in Alarm comparison. Only SS[2:0] are compared */ @@ -497,7 +497,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_Interruption_Mask RTC Interruptions Flag Mask * @{ */ -#define RTC_FLAG_MASK 0x001Fu /*!< RTC flags mask */ +#define RTC_FLAG_MASK 0x001FU /*!< RTC flags mask */ /** * @} */ @@ -721,6 +721,13 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to ? ((RTC->SCR = (RTC_CLEAR_ALRAF))) :\ (RTC->SCR = (RTC_CLEAR_ALRBF))) +/** + * @brief Check whether if the RTC Calendar is initialized. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) ((((RTC->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS) ? 1U : 0U) + /** * @} */ @@ -759,14 +766,14 @@ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Ca */ /* RTC Time and Date functions ************************************************/ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetTime(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc); -void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc); -void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc); -void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc); -uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_GetDate(const RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +void HAL_RTC_DST_Add1Hour(const RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_Sub1Hour(const RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_SetStoreOperation(const RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_ClearStoreOperation(const RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTC_DST_ReadStoreOperation(const RTC_HandleTypeDef *hrtc); /** * @} */ @@ -778,10 +785,10 @@ uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, +HAL_StatusTypeDef HAL_RTC_GetAlarm(const RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout); void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); /** * @} @@ -800,7 +807,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc); * @{ */ /* Peripheral State functions *************************************************/ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); +HAL_RTCStateTypeDef HAL_RTC_GetState(const RTC_HandleTypeDef *hrtc); /** * @} */ @@ -822,10 +829,10 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define RTC_DR_RESERVED_MASK (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \ RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \ RTC_DR_DU) -#define RTC_INIT_MASK 0xFFFFFFFFu +#define RTC_INIT_MASK 0xFFFFFFFFU #define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF)) -#define RTC_TIMEOUT_VALUE 1000u +#define RTC_TIMEOUT_VALUE 1000U /** * @} @@ -873,11 +880,11 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || \ ((FORMAT) == RTC_FORMAT_BCD)) -#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99u) +#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U) -#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1u) && ((MONTH) <= 12u)) +#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U)) -#define IS_RTC_DATE(DATE) (((DATE) >= 1u) && ((DATE) <= 31u)) +#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U)) #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ @@ -887,7 +894,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >0u) && ((DATE) <= 31u)) +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U)) #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ @@ -915,13 +922,13 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos)) -#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0u) && ((HOUR) <= 12u)) +#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23u) +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59u) +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59u) +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rtc_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rtc_ex.c index fbaa5281edb..074991032f3 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rtc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rtc_ex.c @@ -326,6 +326,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc) /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; /* Disable the write protection for RTC registers */ @@ -360,8 +361,9 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe RTC_DateTypeDef *sTimeStampDate, uint32_t Format) { uint32_t tmptime; - uint32_t tmpdate; + uint32_t tmpdate; + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -403,41 +405,19 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe return HAL_OK; } -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** - * @brief Handle TimeStamp secure interrupt request. + * @brief Handle TimeStamp interrupt request. * @param hrtc RTC handle * @retval None */ void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc) { + /* Get the pending status of the TimeStamp Interrupt */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) if (READ_BIT(RTC->SMISR, RTC_SMISR_TSMF) != 0U) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call TimeStampEvent registered Callback */ - hrtc->TimeStampEventCallback(hrtc); #else - HAL_RTCEx_TimeStampEventCallback(hrtc); -#endif /*(USE_HAL_RTC_REGISTER_CALLBACKS == 1)*/ - /* Clearing flags after the Callback because the content of RTC_TSTR and RTC_TSDR are cleared when - TSF bit is reset.*/ - WRITE_REG(RTC->SCR, RTC_SCR_CITSF | RTC_SCR_CTSF); - } - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -#else /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/** - * @brief Handle TimeStamp non-secure interrupt request. - * @param hrtc RTC handle - * @retval None - */ -void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc) -{ if (READ_BIT(RTC->MISR, RTC_MISR_TSMF) != 0U) +#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ { #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) /* Call TimeStampEvent registered Callback */ @@ -446,14 +426,13 @@ void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc) HAL_RTCEx_TimeStampEventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ /* Clearing flags after the Callback because the content of RTC_TSTR and RTC_TSDR are cleared when - TSF bit is reset.*/ + TSF bit is reset.*/ WRITE_REG(RTC->SCR, RTC_SCR_CITSF | RTC_SCR_CTSF); } /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; } -#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @brief TimeStamp callback. @@ -478,6 +457,9 @@ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) */ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + uint32_t tickstart = HAL_GetTick(); while (READ_BIT(RTC->SR, RTC_SR_TSF) == 0U) @@ -487,9 +469,6 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 /* Clear the TIMESTAMP OverRun Flag */ WRITE_REG(RTC->SCR, RTC_SCR_CTSOVF); - /* Change TIMESTAMP state */ - hrtc->State = HAL_RTC_STATE_ERROR; - return HAL_ERROR; } @@ -497,15 +476,19 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->SR, RTC_SR_TSF) == 0U) + { + return HAL_TIMEOUT; + } + else + { + break; + } } } } - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - return HAL_OK; } @@ -545,6 +528,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; /* Disable the write protection for RTC registers */ @@ -559,19 +543,29 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) { tickstart = HAL_GetTick(); + while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + else + { + break; + } } } } @@ -588,6 +582,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -621,6 +616,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; /* Disable the write protection for RTC registers */ @@ -642,15 +638,24 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + else + { + break; + } } } } @@ -667,6 +672,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -687,6 +693,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; /* Disable the write protection for RTC registers */ @@ -697,26 +704,37 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) CLEAR_BIT(RTC->CR, (RTC_CR_WUTE | RTC_CR_WUTIE)); tickstart = HAL_GetTick(); + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - hrtc->State = HAL_RTC_STATE_TIMEOUT; + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } + else + { + break; + } } } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -732,46 +750,25 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) */ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) { + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); /* Get the counter value */ return (uint32_t)(READ_BIT(RTC->WUTR, RTC_WUTR_WUT)); } -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** - * @brief Handle Wake Up Timer secure interrupt request. + * @brief Handle Wake Up Timer interrupt request. * @param hrtc RTC handle * @retval None */ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) { - if ((RTC->SMISR & RTC_SMISR_WUTMF) != 0u) - { - /* Immediately clear flags */ - WRITE_REG(RTC->SCR, RTC_SCR_CWUTF); -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call wake up timer registered Callback */ - hrtc->WakeUpTimerEventCallback(hrtc); + /* Get the pending status of the Wake-Up Timer Interrupt */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (READ_BIT(RTC->SMISR, RTC_SMISR_WUTMF) != 0U) #else - HAL_RTCEx_WakeUpTimerEventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -#else /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/** - * @brief Handle Wake Up Timer non-secure interrupt request. - * @param hrtc RTC handle - * @retval None - */ -void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) -{ - /* Get the pending status of the WAKEUPTIMER Interrupt */ if (READ_BIT(RTC->MISR, RTC_MISR_WUTMF) != 0U) +#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ { /* Clear the WAKEUPTIMER interrupt pending bit */ WRITE_REG(RTC->SCR, RTC_SCR_CWUTF); @@ -788,7 +785,6 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; } -#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @brief Wake Up Timer callback. @@ -805,7 +801,6 @@ __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) */ } - /** * @brief Handle Wake Up Timer Polling. * @param hrtc RTC handle @@ -814,6 +809,9 @@ __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) */ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + uint32_t tickstart = HAL_GetTick(); while (READ_BIT(RTC->SR, RTC_SR_WUTF) == 0U) @@ -822,8 +820,15 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->SR, RTC_SR_WUTF) == 0U) + { + return HAL_TIMEOUT; + } + else + { + break; + } } } } @@ -869,8 +874,6 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin * @{ */ - - /** * @brief Set the Smooth calibration parameters. * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses @@ -878,7 +881,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin * SmoothCalibMinusPulsesValue must be equal to 0. * @param hrtc RTC handle * @param SmoothCalibPeriod Select the Smooth Calibration Period. - * This parameter can be can be one of the following values : + * This parameter can be one of the following values : * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s. * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s. * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s. @@ -903,20 +906,21 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t Smo /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* check if a calibration is pending*/ - if (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U) - { - tickstart = HAL_GetTick(); + tickstart = HAL_GetTick(); - /* check if a calibration is pending*/ - while (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U) + /* check if a calibration is pending */ + while (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -929,6 +933,10 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t Smo return HAL_TIMEOUT; } + else + { + break; + } } } @@ -965,6 +973,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetLowPowerCalib(RTC_HandleTypeDef *hrtc, uint32_t L /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; /* Disable the write protection for RTC registers */ @@ -1008,6 +1017,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t Sh /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; /* Disable the write protection for RTC registers */ @@ -1015,20 +1025,29 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t Sh tickstart = HAL_GetTick(); - /* Wait until the shift is completed*/ + /* Wait until the shift is completed */ while (READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) != 0U) { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) != 0U) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - hrtc->State = HAL_RTC_STATE_TIMEOUT; + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } + else + { + break; + } } } @@ -1046,6 +1065,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t Sh /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; /* Process Unlocked */ @@ -1098,6 +1118,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32 /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; /* Disable the write protection for RTC registers */ @@ -1131,6 +1152,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc) /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; /* Disable the write protection for RTC registers */ @@ -1163,6 +1185,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc) /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; /* Disable the write protection for RTC registers */ @@ -1184,6 +1207,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc) if (status == HAL_OK) { + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; } @@ -1205,6 +1229,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc) /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; /* Disable the write protection for RTC registers */ @@ -1226,6 +1251,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc) if (status == HAL_OK) { + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; } @@ -1247,6 +1273,7 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc) /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; /* Disable the write protection for RTC registers */ @@ -1279,6 +1306,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc) /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; /* Disable the write protection for RTC registers */ @@ -1309,6 +1337,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc) */ HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, uint32_t Instance) { + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); UNUSED(Instance); /* This register is read-only only and is incremented by one when a write access is done to this @@ -1329,6 +1358,7 @@ HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, u */ HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t Instance, uint32_t *Value) { + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); UNUSED(Instance); @@ -1349,6 +1379,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetSSRU_IT(RTC_HandleTypeDef *hrtc) /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; /* Disable the write protection for RTC registers */ @@ -1360,6 +1391,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetSSRU_IT(RTC_HandleTypeDef *hrtc) /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -1378,17 +1410,19 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateSSRU(RTC_HandleTypeDef *hrtc) /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_SSRU_DISABLE_IT(hrtc, RTC_IT_TS); + __HAL_RTC_SSRU_DISABLE_IT(hrtc, RTC_IT_SSRU); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -1397,7 +1431,6 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateSSRU(RTC_HandleTypeDef *hrtc) return HAL_OK; } -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** * @brief Handle SSR underflow interrupt request. * @param hrtc RTC handle @@ -1405,10 +1438,15 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateSSRU(RTC_HandleTypeDef *hrtc) */ void HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc) { - if ((RTC->SMISR & RTC_SMISR_SSRUMF) != 0u) + /* Get the pending status of the SSR Underflow Interrupt */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (READ_BIT(RTC->SMISR, RTC_SMISR_SSRUMF) != 0U) +#else + if (READ_BIT(RTC->MISR, RTC_MISR_SSRUMF) != 0U) +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ { - /* Immediately clear flags */ - RTC->SCR = RTC_SCR_CSSRUF; + /* Immediately clear SSR underflow flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CSSRUF); /* SSRU callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) @@ -1423,32 +1461,7 @@ void HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc) /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; } -#else -/** - * @brief Handle SSR underflow interrupt request. - * @param hrtc RTC handle - * @retval None - */ -void HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc) -{ - if ((RTC->MISR & RTC_MISR_SSRUMF) != 0u) - { - /* Immediately clear flags */ - RTC->SCR = RTC_SCR_CSSRUF; - /* SSRU callback */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call SSRUEvent registered Callback */ - hrtc->SSRUEventCallback(hrtc); -#else - HAL_RTCEx_SSRUEventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @brief SSR underflow callback. * @param hrtc RTC handle @@ -1506,6 +1519,9 @@ __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) */ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + uint32_t tickstart = HAL_GetTick(); while (READ_BIT(RTC->SR, RTC_SR_ALRBF) == 0U) @@ -1514,8 +1530,15 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->SR, RTC_SR_ALRBF) == 0U) + { + return HAL_TIMEOUT; + } + else + { + break; + } } } } @@ -1622,6 +1645,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef /* Timestamp on tamper */ if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sTamper->TimeStampOnTamperDetection) { + /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection); __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1694,6 +1718,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType /* Timestamp on tamper */ if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sTamper->TimeStampOnTamperDetection) { + /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection); __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1823,7 +1848,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_Active } /* Configure ATOSELx[] in case of output sharing */ - ATCR2 |= sAllTamper->TampInput[i].Output << ((3u * i) + TAMP_ATCR2_ATOSEL1_Pos); + ATCR2 |= sAllTamper->TampInput[i].Output << ((3U * i) + TAMP_ATCR2_ATOSEL1_Pos); if (i != sAllTamper->TampInput[i].Output) { @@ -1845,14 +1870,24 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_Active WRITE_REG(TAMP->ATSEEDR, sAllTamper->Seed[i]); } - /* Wait till RTC SEEDF flag is set and if Time out is reached exit */ + /* Wait till RTC SEEDF flag is cleared and if Time out is reached exit */ tickstart = HAL_GetTick(); - while (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0u) + while (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U) { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + else + { + break; + } } } @@ -1906,14 +1941,24 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSe WRITE_REG(TAMP->ATSEEDR, pSeed[i]); } - /* Wait till RTC SEEDF flag is set and if Time out is reached exit */ + /* Wait till RTC SEEDF flag is cleared and if Time out is reached exit */ tickstart = HAL_GetTick(); while (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U) { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + else + { + break; + } } } @@ -1929,6 +1974,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSe */ HAL_StatusTypeDef HAL_RTCEx_SetBoothardwareKey(RTC_HandleTypeDef *hrtc) { + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); WRITE_REG(TAMP->SECCFGR, TAMP_SECCFGR_BHKLOCK); @@ -1986,7 +2032,9 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc) */ HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout) { + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); + assert_param(IS_RTC_TAMPER(Tamper)); uint32_t tickstart = HAL_GetTick(); @@ -1998,7 +2046,15 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(TAMP->SR, Tamper) != Tamper) + { + return HAL_TIMEOUT; + } + else + { + break; + } } } } @@ -2029,11 +2085,15 @@ HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_Inter /* timestamp on internal tamper */ if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection) { + /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection); + + /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } + /* No Erase Backup register enable for Internal Tamper */ if (sIntTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) { /* Control register 3 */ @@ -2120,7 +2180,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_In */ HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper) { + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); + assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper)); /* Disable the selected Tamper pin */ @@ -2146,7 +2208,9 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, ui */ HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout) { + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); + assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper)); uint32_t tickstart = HAL_GetTick(); @@ -2158,7 +2222,15 @@ HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(TAMP->SR, IntTamper) != IntTamper) + { + return HAL_TIMEOUT; + } + else + { + break; + } } } } @@ -2169,22 +2241,19 @@ HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, return HAL_OK; } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** @brief Handle Tamper secure interrupt request. +/** + * @brief Handle Tamper interrupt request. * @param hrtc RTC handle * @retval None */ void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc) { - uint32_t tmp; - - /* Get secure interrupt status */ - tmp = READ_REG(TAMP->SMISR); - - /* Immediately clear flags */ - WRITE_REG(TAMP->SCR, tmp); + /* Get the pending status of the Tampers Interrupt */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t tmp = READ_REG(TAMP->SMISR); +#else + uint32_t tmp = READ_REG(TAMP->MISR); +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* Check Tamper1 status */ if ((tmp & RTC_TAMPER_1) == RTC_TAMPER_1) @@ -2412,247 +2481,10 @@ void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc) HAL_RTCEx_InternalTamper13EventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } -} - - -#else -/** - * @brief Handle Tamper non-secure interrupt request. - * @param hrtc RTC handle - * @retval None - */ -void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc) -{ - /* Get interrupt status */ - uint32_t tmp = READ_REG(TAMP->MISR); - /* Immediately clear flags */ + /* Clear flags after treatment to allow the potential tamper feature */ WRITE_REG(TAMP->SCR, tmp); - - /* Check Tamper1 status */ - if ((tmp & RTC_TAMPER_1) == RTC_TAMPER_1) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Tamper 1 Event registered Callback */ - hrtc->Tamper1EventCallback(hrtc); -#else - /* Tamper1 callback */ - HAL_RTCEx_Tamper1EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Tamper2 status */ - if ((tmp & RTC_TAMPER_2) == RTC_TAMPER_2) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Tamper 2 Event registered Callback */ - hrtc->Tamper2EventCallback(hrtc); -#else - /* Tamper2 callback */ - HAL_RTCEx_Tamper2EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Tamper3 status */ - if ((tmp & RTC_TAMPER_3) == RTC_TAMPER_3) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Tamper 3 Event registered Callback */ - hrtc->Tamper3EventCallback(hrtc); -#else - /* Tamper3 callback */ - HAL_RTCEx_Tamper3EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Tamper4 status */ - if ((tmp & RTC_TAMPER_4) == RTC_TAMPER_4) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Tamper 4 Event registered Callback */ - hrtc->Tamper4EventCallback(hrtc); -#else - /* Tamper4 callback */ - HAL_RTCEx_Tamper4EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Tamper5 status */ - if ((tmp & RTC_TAMPER_5) == RTC_TAMPER_5) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Tamper 5 Event registered Callback */ - hrtc->Tamper5EventCallback(hrtc); -#else - /* Tamper5 callback */ - HAL_RTCEx_Tamper5EventCallback(hrtc); -#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ - } - - /* Check Tamper6 status */ - if ((tmp & RTC_TAMPER_6) == RTC_TAMPER_6) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Tamper 6 Event registered Callback */ - hrtc->Tamper6EventCallback(hrtc); -#else - /* Tamper6 callback */ - HAL_RTCEx_Tamper6EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Tamper7 status */ - if ((tmp & RTC_TAMPER_7) == RTC_TAMPER_7) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Tamper 7 Event registered Callback */ - hrtc->Tamper7EventCallback(hrtc); -#else - /* Tamper7 callback */ - HAL_RTCEx_Tamper7EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Tamper8 status */ - if ((tmp & RTC_TAMPER_8) == RTC_TAMPER_8) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Tamper 8 Event registered Callback */ - hrtc->Tamper8EventCallback(hrtc); -#else - /* Tamper8 callback */ - HAL_RTCEx_Tamper8EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Internal Tamper1 status */ - if ((tmp & RTC_INT_TAMPER_1) == RTC_INT_TAMPER_1) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper 1 Event registered Callback */ - hrtc->InternalTamper1EventCallback(hrtc); -#else - /* Internal Tamper1 callback */ - HAL_RTCEx_InternalTamper1EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Internal Tamper2 status */ - if ((tmp & RTC_INT_TAMPER_2) == RTC_INT_TAMPER_2) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper 2 Event registered Callback */ - hrtc->InternalTamper2EventCallback(hrtc); -#else - /* Internal Tamper2 callback */ - HAL_RTCEx_InternalTamper2EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Internal Tamper3 status */ - if ((tmp & RTC_INT_TAMPER_3) == RTC_INT_TAMPER_3) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper 3 Event registered Callback */ - hrtc->InternalTamper3EventCallback(hrtc); -#else - /* Internal Tamper3 callback */ - HAL_RTCEx_InternalTamper3EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Internal Tamper5 status */ - if ((tmp & RTC_INT_TAMPER_5) == RTC_INT_TAMPER_5) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper 5 Event registered Callback */ - hrtc->InternalTamper5EventCallback(hrtc); -#else - /* Internal Tamper5 callback */ - HAL_RTCEx_InternalTamper5EventCallback(hrtc); -#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ - } - /* Check Internal Tamper6 status */ - if ((tmp & RTC_INT_TAMPER_6) == RTC_INT_TAMPER_6) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper 6 Event registered Callback */ - hrtc->InternalTamper6EventCallback(hrtc); -#else - /* Internal Tamper6 callback */ - HAL_RTCEx_InternalTamper6EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - /* Check Internal Tamper7 status */ - if ((tmp & RTC_INT_TAMPER_7) == RTC_INT_TAMPER_7) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper 7 Event registered Callback */ - hrtc->InternalTamper7EventCallback(hrtc); -#else - /* Internal Tamper7 callback */ - HAL_RTCEx_InternalTamper7EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - /* Check Internal Tamper8 status */ - if ((tmp & RTC_INT_TAMPER_8) == RTC_INT_TAMPER_8) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper 8 Event registered Callback */ - hrtc->InternalTamper8EventCallback(hrtc); -#else - /* Internal Tamper8 callback */ - HAL_RTCEx_InternalTamper8EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - /* Check Internal Tamper9 status */ - if ((tmp & RTC_INT_TAMPER_9) == RTC_INT_TAMPER_9) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper 9 Event registered Callback */ - hrtc->InternalTamper9EventCallback(hrtc); -#else - /* Internal Tamper9 callback */ - HAL_RTCEx_InternalTamper9EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - /* Check Internal Tamper11 status */ - if ((tmp & RTC_INT_TAMPER_11) == RTC_INT_TAMPER_11) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper 11 Event registered Callback */ - hrtc->InternalTamper11EventCallback(hrtc); -#else - /* Internal Tamper11 callback */ - HAL_RTCEx_InternalTamper11EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Internal Tamper12 status */ - if ((tmp & RTC_INT_TAMPER_12) == RTC_INT_TAMPER_12) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper 12 Event registered Callback */ - hrtc->InternalTamper12EventCallback(hrtc); -#else - /* Internal Tamper12 callback */ - HAL_RTCEx_InternalTamper12EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } - - /* Check Internal Tamper13 status */ - if ((tmp & RTC_INT_TAMPER_13) == RTC_INT_TAMPER_13) - { -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper 13 Event registered Callback */ - hrtc->InternalTamper13EventCallback(hrtc); -#else - /* Internal Tamper13 callback */ - HAL_RTCEx_InternalTamper13EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1 */ - } } -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** * @brief Tamper 1 callback. @@ -2669,7 +2501,6 @@ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) */ } - /** * @brief Tamper 2 callback. * @param hrtc RTC handle @@ -2955,7 +2786,7 @@ __weak void HAL_RTCEx_InternalTamper13EventCallback(RTC_HandleTypeDef *hrtc) [..] (+) Before calling any tamper or internal tamper function, you have to call first HAL_RTC_Init() function. - (+) In that ine you can select to output tamper event on RTC pin. + (+) In that one you can select to output tamper event on RTC pin. [..] This subsection provides functions allowing to (+) Write a data in a specified RTC Backup data register @@ -2977,7 +2808,9 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3 { uint32_t tmp; + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); + /* Check the parameters */ assert_param(IS_RTC_BKP(BackupRegister)); @@ -3000,6 +2833,7 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) { uint32_t tmp; + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); /* Check the parameters */ assert_param(IS_RTC_BKP(BackupRegister)); @@ -3113,6 +2947,7 @@ uint32_t HAL_RTCEx_Get_Erase_SecretDev_Conf(void) */ HAL_StatusTypeDef HAL_RTCEx_SecureModeGet(RTC_HandleTypeDef *hrtc, RTC_SecureStateTypeDef *secureState) { + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); /* Read registers */ uint32_t rtc_seccfgr = READ_REG(RTC->SECCFGR); @@ -3122,7 +2957,7 @@ HAL_StatusTypeDef HAL_RTCEx_SecureModeGet(RTC_HandleTypeDef *hrtc, RTC_SecureSta secureState->rtcSecureFull = READ_BIT(rtc_seccfgr, RTC_SECCFGR_SEC); /* Warning, rtcNonSecureFeatures is only relevant if secureState->rtcSecureFull == RTC_SECURE_FULL_NO */ - secureState->rtcNonSecureFeatures = READ_BIT(rtc_seccfgr, RTC_NONSECURE_FEATURE_ALL); + secureState->rtcNonSecureFeatures = READ_BIT(rtc_seccfgr, RTC_NONSECURE_FEATURE_NONE); /* TAMP */ secureState->tampSecureFull = READ_BIT(tamp_seccfgr, TAMP_SECCFGR_TAMPSEC); @@ -3149,6 +2984,7 @@ HAL_StatusTypeDef HAL_RTCEx_SecureModeGet(RTC_HandleTypeDef *hrtc, RTC_SecureSta */ HAL_StatusTypeDef HAL_RTCEx_SecureModeSet(RTC_HandleTypeDef *hrtc, RTC_SecureStateTypeDef *secureState) { + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); assert_param(IS_RTC_SECURE_FULL(secureState->rtcSecureFull)); assert_param(IS_RTC_NONSECURE_FEATURES(secureState->rtcNonSecureFeatures)); @@ -3201,6 +3037,7 @@ HAL_StatusTypeDef HAL_RTCEx_SecureModeSet(RTC_HandleTypeDef *hrtc, RTC_SecureSta */ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeSet(RTC_HandleTypeDef *hrtc, RTC_PrivilegeStateTypeDef *privilegeState) { + /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); assert_param(IS_RTC_PRIVILEGE_FULL(privilegeState->rtcPrivilegeFull)); assert_param(IS_RTC_PRIVILEGE_FEATURES(privilegeState->rtcPrivilegeFeatures)); @@ -3242,12 +3079,14 @@ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeSet(RTC_HandleTypeDef *hrtc, RTC_Privil */ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(RTC_HandleTypeDef *hrtc, RTC_PrivilegeStateTypeDef *privilegeState) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* Read registers */ uint32_t rtc_privcfgr = READ_REG(RTC->PRIVCFGR); uint32_t tamp_privcfgr = READ_REG(TAMP->PRIVCFGR); uint32_t tamp_seccfgr = READ_REG(TAMP->SECCFGR); - UNUSED(hrtc); /* RTC privilege configuration */ privilegeState->rtcPrivilegeFull = READ_BIT(rtc_privcfgr, RTC_PRIVCFGR_PRIV); diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rtc_ex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rtc_ex.h index c1837547dc8..fa81143a1e7 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rtc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_rtc_ex.h @@ -131,7 +131,7 @@ typedef struct uint32_t Seed[RTC_ATAMP_SEED_NB_UINT32]; /*!< Specifies the RNG Seed value. - This parameter is an array of value from 0 to 0xFFFFFFFF. */ + This parameter is an array of value from 0 to 0xFFFFFFFF */ RTC_ATampInputTypeDef TampInput[RTC_TAMP_NB]; /*!< Specifies configuration of all active tampers. @@ -171,12 +171,12 @@ typedef struct uint32_t rtcNonSecureFeatures; /*!< Specifies the non-secure features. This parameter is only relevant if RTC is not fully secure - (rtcSecureFull == RTC_SECURE_FULL_NO). + (rtcSecureFull == RTC_SECURE_FULL_NO). This parameter can be a combination of @ref RTCEx_RTC_NonSecure_Features. */ uint32_t tampSecureFull; /*!< Specifies If the TAMP is fully secure or not execpt monotonic counters - and BackUp registers. + and BackUp registers. This parameter can be a value of @ref RTCEx_TAMP_Secure_Full */ uint32_t backupRegisterStartZone2; /*!< Specifies the backup register start zone 2 @@ -194,7 +194,7 @@ typedef struct uint32_t MonotonicCounterSecure; /*!< Specifies If the monotonic counter is secure or not This parameter can be a value of - @ref RTCEx_TAMP_Monotonic_Counter_Secure */ + @ref RTCEx_TAMP_Monotonic_Counter_Secure */ } RTC_SecureStateTypeDef; /** * @} @@ -225,8 +225,8 @@ typedef struct disabled. */ uint32_t backupRegisterStartZone2; /*!< Specifies the backup register start zone 2. - Zone 1 : read secure write secure. - Zone 2 : read non-secure write secure. + Zone 1 granted accesses : read secure, write secure. + Zone 2 granted accesses : read non-secure, write secure. This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to specify the register . Warning : this parameter is writable in secure mode or if trustzone is @@ -234,7 +234,7 @@ typedef struct Warning : this parameter is shared with RTC_SecureStateTypeDef */ uint32_t backupRegisterStartZone3; /*!< Specifies the backup register start zone 3. - Zone 3 : read non-secure write non-secure. + Zone 3 granted accesses : read non-secure, write non-secure. This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to specify the register. Warning : this parameter is writable in secure mode or if trustzone is @@ -261,8 +261,8 @@ typedef struct /** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition * @{ */ -#define RTC_TIMESTAMPEDGE_RISING 0x00000000u -#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE +#define RTC_TIMESTAMPEDGE_RISING 0U +#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE /** * @} */ @@ -270,7 +270,7 @@ typedef struct /** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection * @{ */ -#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000u +#define RTC_TIMESTAMPPIN_DEFAULT 0U /** * @} */ @@ -278,12 +278,12 @@ typedef struct /** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions * @{ */ -#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000u -#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0 -#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1 -#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1) -#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2 -#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0U +#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0 +#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1 +#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1) +#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2 +#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2) /** * @} */ @@ -291,12 +291,12 @@ typedef struct /** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions * @{ */ -#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000u /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 32s, else 2exp20 RTCCLK pulses */ -#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 16s, else 2exp19 RTCCLK pulses */ -#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 8s, else 2exp18 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_32SEC 0U /*!< If RTCCLK = 32768 Hz, Smooth calibration period + is 32s, else 2exp20 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibration period + is 16s, else 2exp19 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, Smooth calibration period + is 8s, else 2exp18 RTCCLK pulses */ /** * @} */ @@ -304,11 +304,11 @@ typedef struct /** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions * @{ */ -#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added - during a X -second window = Y - CALM[8:0] - with Y = 512, 256, 128 when X = 32, 16, 8 */ -#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000u /*!< The number of RTCCLK pulses subbstited - during a 32-second window = CALM[8:0] */ +#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added + during a X -second window = Y - CALM[8:0] + with Y = 512, 256, 128 when X = 32, 16, 8 */ +#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0U /*!< The number of RTCCLK pulses subbstited + during a 32-second window = CALM[8:0] */ /** * @} */ @@ -316,13 +316,10 @@ typedef struct /** @defgroup RTCEx_Smooth_calib_low_power_Definitions RTCEx Smooth calib Low Power Definitions * @{ */ -#define RTC_LPCAL_SET RTC_CALR_LPCAL /*!< Calibration window is 220 ck_apre, - which is the required configuration for - ultra-low consumption mode. */ -#define RTC_LPCAL_RESET 0x00000000u /*!< Calibration window is 220 RTCCLK, - which is a high-consumption mode. - This mode should be set only when less - than 32s calibration window is required. */ +#define RTC_LPCAL_SET RTC_CALR_LPCAL /*!< Calibration window is 2exp20 ck_apre, which is the required configuration for ultra-low consumption mode. */ +#define RTC_LPCAL_RESET 0U /*!< Calibration window is 2exp20 RTCCLK, which is a high-consumption mode. + This mode should be set only when less + than 32s calibration window is required. */ /** * @} */ @@ -330,9 +327,8 @@ typedef struct /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions * @{ */ -#define RTC_CALIBOUTPUT_512HZ 0x00000000u -#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL - +#define RTC_CALIBOUTPUT_512HZ 0U +#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL /** * @} */ @@ -341,8 +337,8 @@ typedef struct /** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definitions * @{ */ -#define RTC_SHIFTADD1S_RESET 0x00000000u -#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S +#define RTC_SHIFTADD1S_RESET 0U +#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S /** * @} */ @@ -400,10 +396,10 @@ typedef struct /** @defgroup RTCEx_Tamper_Trigger RTCEx Tamper Trigger * @{ */ -#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00u /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ -#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x01u /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ -#define RTC_TAMPERTRIGGER_LOWLEVEL 0x02u /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */ -#define RTC_TAMPERTRIGGER_HIGHLEVEL 0x03u /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_RISINGEDGE 0U /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_FALLINGEDGE 1U /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_LOWLEVEL 2U /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_HIGHLEVEL 3U /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */ /** * @} */ @@ -420,8 +416,8 @@ typedef struct /** @defgroup RTCEx_Tamper_EraseBackUp RTCEx Tamper EraseBackUp * @{ */ -#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00u -#define RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01u +#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0U +#define RTC_TAMPER_ERASE_BACKUP_DISABLE 1U /** * @} */ @@ -429,7 +425,7 @@ typedef struct /** @defgroup RTCEx_Tamper_Filter RTCEx Tamper Filter * @{ */ -#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ +#define RTC_TAMPERFILTER_DISABLE 0U /*!< Tamper filter is disabled */ #define RTC_TAMPERFILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */ #define RTC_TAMPERFILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4 @@ -443,7 +439,7 @@ typedef struct /** @defgroup RTCEx_Tamper_Sampling_Frequencies RTCEx Tamper Sampling Frequencies * @{ */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ @@ -459,7 +455,7 @@ typedef struct /** @defgroup RTCEx_Tamper_Pin_Precharge_Duration RTCEx Tamper Pin Precharge Duration * @{ */ -#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ +#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ #define RTC_TAMPERPRECHARGEDURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ #define RTC_TAMPERPRECHARGEDURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ #define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (TAMP_FLTCR_TAMPPRCH_0 | TAMP_FLTCR_TAMPPRCH_1) /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ @@ -470,7 +466,7 @@ typedef struct /** @defgroup RTCEx_Tamper_Pull_UP RTCEx Tamper Pull UP * @{ */ -#define RTC_TAMPER_PULLUP_ENABLE 0x00000000u /*!< Tamper pins are pre-charged before sampling */ +#define RTC_TAMPER_PULLUP_ENABLE 0U /*!< Tamper pins are pre-charged before sampling */ #define RTC_TAMPER_PULLUP_DISABLE TAMP_FLTCR_TAMPPUDIS /*!< Tamper pins pre-charge is disabled */ /** * @} @@ -479,7 +475,7 @@ typedef struct /** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection RTCEx Tamper TimeStamp On Tamper Detection Definitions * @{ */ -#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000u /*!< TimeStamp on Tamper Detection event is not saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0U /*!< TimeStamp on Tamper Detection event is not saved */ #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_CR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */ /** * @} @@ -533,9 +529,9 @@ typedef struct #define RTC_FLAG_TAMP_6 TAMP_SR_TAMP6F #define RTC_FLAG_TAMP_7 TAMP_SR_TAMP7F #define RTC_FLAG_TAMP_8 TAMP_SR_TAMP8F -#define RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2 | RTC_FLAG_TAMP_3 |\ - RTC_FLAG_TAMP_4 | RTC_FLAG_TAMP_5 | RTC_FLAG_TAMP_6 |\ - RTC_FLAG_TAMP_7 | RTC_FLAG_TAMP_8) +#define RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2 | RTC_FLAG_TAMP_3 |\ + RTC_FLAG_TAMP_4 | RTC_FLAG_TAMP_5 | RTC_FLAG_TAMP_6 |\ + RTC_FLAG_TAMP_7 | RTC_FLAG_TAMP_8) #define RTC_FLAG_INT_TAMP_1 TAMP_SR_ITAMP1F @@ -563,8 +559,8 @@ typedef struct /** @defgroup RTCEx_ActiveTamper_Enable RTCEx_ActiveTamper_Enable Definitions * @{ */ -#define RTC_ATAMP_ENABLE 1u -#define RTC_ATAMP_DISABLE 0u +#define RTC_ATAMP_ENABLE 1U +#define RTC_ATAMP_DISABLE 0U /** * @} */ @@ -572,8 +568,8 @@ typedef struct /** @defgroup RTCEx_ActiveTamper_Interrupt RTCEx_ActiveTamper_Interrupt Definitions * @{ */ -#define RTC_ATAMP_INTERRUPT_ENABLE 1u -#define RTC_ATAMP_INTERRUPT_DISABLE 0u +#define RTC_ATAMP_INTERRUPT_ENABLE 1U +#define RTC_ATAMP_INTERRUPT_DISABLE 0U /** * @} */ @@ -582,7 +578,7 @@ typedef struct * @{ */ #define RTC_ATAMP_FILTER_ENABLE TAMP_ATCR1_FLTEN -#define RTC_ATAMP_FILTER_DISABLE 0u +#define RTC_ATAMP_FILTER_DISABLE 0U /** * @} */ @@ -590,14 +586,15 @@ typedef struct /** @defgroup RTCEx_ActiveTamper_Async_prescaler RTCEx Active_Tamper_Asynchronous_Prescaler clock Definitions * @{ */ -#define RTC_ATAMP_ASYNCPRES_RTCCLK 0u /*!< RTCCLK */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK 0U /*!< RTCCLK */ #define RTC_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0 /*!< RTCCLK/2 */ #define RTC_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1 /*!< RTCCLK/4 */ -#define RTC_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/8 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/8 */ #define RTC_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2 /*!< RTCCLK/16 */ #define RTC_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/32 */ #define RTC_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1) /*!< RTCCLK/64 */ #define RTC_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/128 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_2048 (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/2048 */ /** * @} */ @@ -605,14 +602,14 @@ typedef struct /** @defgroup RTCEx_ActiveTamper_Sel RTCEx Active Tamper selection Definition * @{ */ -#define RTC_ATAMP_1 0u /*!< Tamper 1 */ -#define RTC_ATAMP_2 1u /*!< Tamper 2 */ -#define RTC_ATAMP_3 2u /*!< Tamper 3 */ -#define RTC_ATAMP_4 3u /*!< Tamper 4 */ -#define RTC_ATAMP_5 4u /*!< Tamper 5 */ -#define RTC_ATAMP_6 5u /*!< Tamper 6 */ -#define RTC_ATAMP_7 6u /*!< Tamper 7 */ -#define RTC_ATAMP_8 7u /*!< Tamper 8 */ +#define RTC_ATAMP_1 0U /*!< Tamper 1 */ +#define RTC_ATAMP_2 1U /*!< Tamper 2 */ +#define RTC_ATAMP_3 2U /*!< Tamper 3 */ +#define RTC_ATAMP_4 3U /*!< Tamper 4 */ +#define RTC_ATAMP_5 4U /*!< Tamper 5 */ +#define RTC_ATAMP_6 5U /*!< Tamper 6 */ +#define RTC_ATAMP_7 6U /*!< Tamper 7 */ +#define RTC_ATAMP_8 7U /*!< Tamper 8 */ /** * @} */ @@ -620,7 +617,7 @@ typedef struct /** @defgroup RTCEx_MonotonicCounter_Instance RTCEx Monotonic Counter Instance Definition * @{ */ -#define RTC_MONOTONIC_COUNTER_1 0u /*!< Monotonic counter 1 */ +#define RTC_MONOTONIC_COUNTER_1 0U /*!< Monotonic counter 1 */ /** * @} */ @@ -628,39 +625,39 @@ typedef struct /** @defgroup RTCEx_Backup_Registers RTCEx Backup Registers Definition * @{ */ -#define RTC_BKP_NUMBER RTC_BKP_NB -#define RTC_BKP_DR0 0x00u -#define RTC_BKP_DR1 0x01u -#define RTC_BKP_DR2 0x02u -#define RTC_BKP_DR3 0x03u -#define RTC_BKP_DR4 0x04u -#define RTC_BKP_DR5 0x05u -#define RTC_BKP_DR6 0x06u -#define RTC_BKP_DR7 0x07u -#define RTC_BKP_DR8 0x08u -#define RTC_BKP_DR9 0x09u -#define RTC_BKP_DR10 0x0Au -#define RTC_BKP_DR11 0x0Bu -#define RTC_BKP_DR12 0x0Cu -#define RTC_BKP_DR13 0x0Du -#define RTC_BKP_DR14 0x0Eu -#define RTC_BKP_DR15 0x0Fu -#define RTC_BKP_DR16 0x10u -#define RTC_BKP_DR17 0x11u -#define RTC_BKP_DR18 0x12u -#define RTC_BKP_DR19 0x13u -#define RTC_BKP_DR20 0x14u -#define RTC_BKP_DR21 0x15u -#define RTC_BKP_DR22 0x16u -#define RTC_BKP_DR23 0x17u -#define RTC_BKP_DR24 0x18u -#define RTC_BKP_DR25 0x19u -#define RTC_BKP_DR26 0x1Au -#define RTC_BKP_DR27 0x1Bu -#define RTC_BKP_DR28 0x1Cu -#define RTC_BKP_DR29 0x1Du -#define RTC_BKP_DR30 0x1Eu -#define RTC_BKP_DR31 0x1Fu +#define RTC_BKP_NUMBER RTC_BKP_NB +#define RTC_BKP_DR0 0x00U +#define RTC_BKP_DR1 0x01U +#define RTC_BKP_DR2 0x02U +#define RTC_BKP_DR3 0x03U +#define RTC_BKP_DR4 0x04U +#define RTC_BKP_DR5 0x05U +#define RTC_BKP_DR6 0x06U +#define RTC_BKP_DR7 0x07U +#define RTC_BKP_DR8 0x08U +#define RTC_BKP_DR9 0x09U +#define RTC_BKP_DR10 0x0AU +#define RTC_BKP_DR11 0x0BU +#define RTC_BKP_DR12 0x0CU +#define RTC_BKP_DR13 0x0DU +#define RTC_BKP_DR14 0x0EU +#define RTC_BKP_DR15 0x0FU +#define RTC_BKP_DR16 0x10U +#define RTC_BKP_DR17 0x11U +#define RTC_BKP_DR18 0x12U +#define RTC_BKP_DR19 0x13U +#define RTC_BKP_DR20 0x14U +#define RTC_BKP_DR21 0x15U +#define RTC_BKP_DR22 0x16U +#define RTC_BKP_DR23 0x17U +#define RTC_BKP_DR24 0x18U +#define RTC_BKP_DR25 0x19U +#define RTC_BKP_DR26 0x1AU +#define RTC_BKP_DR27 0x1BU +#define RTC_BKP_DR28 0x1CU +#define RTC_BKP_DR29 0x1DU +#define RTC_BKP_DR30 0x1EU +#define RTC_BKP_DR31 0x1FU /** * @} */ @@ -668,25 +665,25 @@ typedef struct * Warning : It Should not be confused with the Binary format @ref RTC_Input_parameter_format_definitions. * @{ */ -#define RTC_BINARY_NONE 0x00000000u /*!< Free running BCD calendar mode (Binary mode disabled). */ -#define RTC_BINARY_ONLY RTC_ICSR_BIN_0 /*!< Free running Binary mode (BCD mode disabled) */ -#define RTC_BINARY_MIX RTC_ICSR_BIN_1 /*!< Free running BCD calendar and Binary modes */ +#define RTC_BINARY_NONE 0U /*!< Free running BCD calendar mode (Binary mode disabled) */ +#define RTC_BINARY_ONLY RTC_ICSR_BIN_0 /*!< Free running Binary mode (BCD mode disabled) */ +#define RTC_BINARY_MIX RTC_ICSR_BIN_1 /*!< Free running BCD calendar and Binary modes */ /** * @} */ /** @defgroup RTCEx_Binary_mix_BCDU If Binary mode is RTC_BINARY_MIX, the BCD calendar second is incremented - * using the SSR Least Significant Bits. + * using the SSR Least Significant Bits. * @{ */ -#define RTC_BINARY_MIX_BCDU_0 0x00000000u /*!< The 1s BCD calendar increment is generated each time SS[7:0] = 0 */ -#define RTC_BINARY_MIX_BCDU_1 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[8:0] = 0 */ -#define RTC_BINARY_MIX_BCDU_2 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[9:0] = 0 */ -#define RTC_BINARY_MIX_BCDU_3 (0x3UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[10:0] = 0 */ -#define RTC_BINARY_MIX_BCDU_4 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[11:0] = 0 */ -#define RTC_BINARY_MIX_BCDU_5 (0x5UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[12:0] = 0 */ -#define RTC_BINARY_MIX_BCDU_6 (0x6UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[13:0] = 0 */ -#define RTC_BINARY_MIX_BCDU_7 (0x7UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[14:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_0 0U /*!< The 1s BCD calendar increment is generated each time SS[7:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_1 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[8:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_2 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[9:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_3 (0x3UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[10:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_4 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[11:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_5 (0x5UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[12:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_6 (0x6UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[13:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_7 (0x7UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[14:0] = 0 */ /** * @} */ @@ -694,7 +691,7 @@ typedef struct /** @defgroup RTCEx_Alarm_Sub_Seconds_binary_Masks_Definitions RTC Alarm Sub Seconds with binary mode Masks Definitions * @{ */ -#define RTC_ALARMSUBSECONDBINMASK_ALL 0x00000000u /*!< All Alarm SS fields are masked.There is no comparison on sub seconds for Alarm */ +#define RTC_ALARMSUBSECONDBINMASK_ALL 0U /*!< All Alarm SS fields are masked.There is no comparison on sub seconds for Alarm */ #define RTC_ALARMSUBSECONDBINMASK_SS31_1 (1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:1] are don't care in Alarm comparison. Only SS[0] is compared. */ #define RTC_ALARMSUBSECONDBINMASK_SS31_2 (2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:2] are don't care in Alarm comparison. Only SS[1:0] are compared */ #define RTC_ALARMSUBSECONDBINMASK_SS31_3 (3UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:3] are don't care in Alarm comparison. Only SS[2:0] are compared */ @@ -745,7 +742,7 @@ typedef struct * @{ */ #define RTC_SECURE_FULL_YES RTC_SECCFGR_SEC /*!< RTC full secure */ -#define RTC_SECURE_FULL_NO 0u /*!< RTC is not full secure, features can be unsecure. See RTC_LL_EC_UNSECURE_RTC_FEATURE */ +#define RTC_SECURE_FULL_NO 0U /*!< RTC is not full secure, features can be unsecure. See RTC_LL_EC_UNSECURE_RTC_FEATURE */ /** * @} */ @@ -763,7 +760,7 @@ typedef struct #define RTC_NONSECURE_FEATURE_WUT ~RTC_SECCFGR_WUTSEC /*!< Wake up timer */ #define RTC_NONSECURE_FEATURE_ALRA ~RTC_SECCFGR_ALRASEC /*!< Alarm A */ #define RTC_NONSECURE_FEATURE_ALRB ~RTC_SECCFGR_ALRBSEC /*!< Alarm B */ -#define RTC_NONSECURE_FEATURE_ALL 0u +#define RTC_NONSECURE_FEATURE_ALL 0U /** * @} */ @@ -772,7 +769,7 @@ typedef struct * @{ */ #define TAMP_SECURE_FULL_YES TAMP_SECCFGR_TAMPSEC /*!< TAMPER full secure */ -#define TAMP_SECURE_FULL_NO 0u /*!< TAMPER is not secure */ +#define TAMP_SECURE_FULL_NO 0U /*!< TAMPER is not secure */ /** * @} */ @@ -781,7 +778,7 @@ typedef struct * @{ */ #define TAMP_MONOTONIC_CNT_SECURE_YES TAMP_SECCFGR_CNT1SEC /*!< TAMPER Monotonic Counter secure */ -#define TAMP_MONOTONIC_CNT_SECURE_NO 0u /*!< TAMPER Monotonic Counter is not secure */ +#define TAMP_MONOTONIC_CNT_SECURE_NO 0U /*!< TAMPER Monotonic Counter is not secure */ /** * @} */ @@ -789,7 +786,7 @@ typedef struct * @{ */ #define RTC_PRIVILEGE_FULL_YES RTC_PRIVCFGR_PRIV -#define RTC_PRIVILEGE_FULL_NO 0u +#define RTC_PRIVILEGE_FULL_NO 0U /** * @} */ @@ -797,7 +794,7 @@ typedef struct /** @defgroup RTCEx_RTC_Privilege_Features RTCEx Privilege Features Definition * @{ */ -#define RTC_PRIVILEGE_FEATURE_NONE 0u +#define RTC_PRIVILEGE_FEATURE_NONE 0U #define RTC_PRIVILEGE_FEATURE_INIT RTC_PRIVCFGR_INITPRIV /*!< Initialization */ #define RTC_PRIVILEGE_FEATURE_CAL RTC_PRIVCFGR_CALPRIV /*!< Calibration */ #define RTC_PRIVILEGE_FEATURE_TS RTC_PRIVCFGR_TSPRIV /*!< Time stamp */ @@ -815,7 +812,7 @@ typedef struct * @{ */ #define TAMP_PRIVILEGE_FULL_YES TAMP_PRIVCFGR_TAMPPRIV -#define TAMP_PRIVILEGE_FULL_NO 0u +#define TAMP_PRIVILEGE_FULL_NO 0U /** * @} */ @@ -824,7 +821,7 @@ typedef struct * @{ */ #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_ERCFGR0 -#define TAMP_SECRETDEVICE_ERASE_DISABLE 0u +#define TAMP_SECRETDEVICE_ERASE_DISABLE 0U /** * @} */ @@ -833,7 +830,7 @@ typedef struct * @{ */ #define TAMP_MONOTONIC_CNT_PRIVILEGE_YES TAMP_PRIVCFGR_CNT1PRIV -#define TAMP_MONOTONIC_CNT_PRIVILEGE_NO 0u +#define TAMP_MONOTONIC_CNT_PRIVILEGE_NO 0U /** * @} */ @@ -841,7 +838,7 @@ typedef struct /** @defgroup RTCEx_Backup_Reg_Privilege_zone RTCEx Privilege Backup register privilege zone Definition * @{ */ -#define RTC_PRIVILEGE_BKUP_ZONE_NONE 0u +#define RTC_PRIVILEGE_BKUP_ZONE_NONE 0U #define RTC_PRIVILEGE_BKUP_ZONE_1 TAMP_PRIVCFGR_BKPRWPRIV #define RTC_PRIVILEGE_BKUP_ZONE_2 TAMP_PRIVCFGR_BKPWPRIV #define RTC_PRIVILEGE_BKUP_ZONE_ALL (RTC_PRIVILEGE_BKUP_ZONE_1 | RTC_PRIVILEGE_BKUP_ZONE_2) @@ -1657,11 +1654,11 @@ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(RTC_HandleTypeDef *hrtc, RTC_Privil ((LPCAL) == RTC_LPCAL_RESET)) -#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & RTC_TAMPER_ALL) != 0x00U) && \ - (((__TAMPER__) & ~RTC_TAMPER_ALL) == 0x00U)) +#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & RTC_TAMPER_ALL) != 0U) && \ + (((__TAMPER__) & ~RTC_TAMPER_ALL) == 0U)) -#define IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__) ((((__INT_TAMPER__) & RTC_INT_TAMPER_ALL) != 0x00U) && \ - (((__INT_TAMPER__) & ~RTC_INT_TAMPER_ALL) == 0x00U)) +#define IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__) ((((__INT_TAMPER__) & RTC_INT_TAMPER_ALL) != 0U) && \ + (((__INT_TAMPER__) & ~RTC_INT_TAMPER_ALL) == 0U)) #define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ @@ -1712,7 +1709,7 @@ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(RTC_HandleTypeDef *hrtc, RTC_Privil #define IS_RTC_SECURE_FULL(__STATE__) (((__STATE__) == RTC_SECURE_FULL_YES) || \ ((__STATE__) == RTC_SECURE_FULL_NO)) -#define IS_RTC_NONSECURE_FEATURES(__FEATURES__) (((__FEATURES__) & ~RTC_NONSECURE_FEATURE_NONE) == 0u) +#define IS_RTC_NONSECURE_FEATURES(__FEATURES__) (((__FEATURES__) & ~RTC_NONSECURE_FEATURE_NONE) == 0U) #define IS_TAMP_SECURE_FULL(__STATE__) (((__STATE__) == TAMP_SECURE_FULL_YES) || \ ((__STATE__) == TAMP_SECURE_FULL_NO)) @@ -1723,7 +1720,7 @@ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(RTC_HandleTypeDef *hrtc, RTC_Privil #define IS_RTC_PRIVILEGE_FULL(__STATE__) (((__STATE__) == RTC_PRIVILEGE_FULL_YES) || \ ((__STATE__) == RTC_PRIVILEGE_FULL_NO)) -#define IS_RTC_PRIVILEGE_FEATURES(__FEATURES__) (((__FEATURES__) & ~RTC_PRIVILEGE_FEATURE_ALL) == 0u) +#define IS_RTC_PRIVILEGE_FEATURES(__FEATURES__) (((__FEATURES__) & ~RTC_PRIVILEGE_FEATURE_ALL) == 0U) #define IS_TAMP_PRIVILEGE_FULL(__STATE__) (((__STATE__) == TAMP_PRIVILEGE_FULL_YES) || \ ((__STATE__) == TAMP_PRIVILEGE_FULL_NO)) @@ -1731,7 +1728,7 @@ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(RTC_HandleTypeDef *hrtc, RTC_Privil #define IS_TAMP_MONOTONIC_CNT_PRIVILEGE(__STATE__) (((__STATE__) == TAMP_MONOTONIC_CNT_PRIVILEGE_YES) || \ ((__STATE__) == TAMP_MONOTONIC_CNT_PRIVILEGE_NO)) -#define IS_RTC_PRIVILEGE_BKUP_ZONE(__ZONES__) (((__ZONES__) & ~RTC_PRIVILEGE_BKUP_ZONE_ALL) == 0u) +#define IS_RTC_PRIVILEGE_BKUP_ZONE(__ZONES__) (((__ZONES__) & ~RTC_PRIVILEGE_BKUP_ZONE_ALL) == 0U) #define IS_RTC_BINARY_MODE(MODE) (((MODE) == RTC_BINARY_NONE) || \ ((MODE) == RTC_BINARY_ONLY) || \ @@ -1746,7 +1743,7 @@ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(RTC_HandleTypeDef *hrtc, RTC_Privil ((BDCU) == RTC_BINARY_MIX_BCDU_6) || \ ((BDCU) == RTC_BINARY_MIX_BCDU_7)) -#define IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(MASK) (((MASK) == 0u) || \ +#define IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(MASK) (((MASK) == 0U) || \ (((MASK) >= RTC_ALARMSUBSECONDBINMASK_SS31_1) &&\ ((MASK) <= RTC_ALARMSUBSECONDBINMASK_NONE))) diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sai.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sai.c index a3bff261001..88bc4ce85ad 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sai.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sai.c @@ -244,6 +244,8 @@ typedef enum */ #define SAI_DEFAULT_TIMEOUT 4U #define SAI_LONG_TIMEOUT 1000U +#define SAI_SPDIF_FRAME_LENGTH 64U +#define SAI_AC97_FRAME_LENGTH 256U /** * @} */ @@ -367,7 +369,9 @@ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protoco */ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) { +#if defined(SAI2) uint32_t tmpregisterGCR; +#endif /* SAI2 */ uint32_t ckstr_bits; uint32_t syncen_bits; @@ -459,6 +463,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) hsai->State = HAL_SAI_STATE_BUSY; +#if defined(SAI2) /* SAI Block Synchro Configuration -----------------------------------------*/ /* This setting must be done with both audio block (A & B) disabled */ switch (hsai->Init.SynchroExt) @@ -476,6 +481,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) tmpregisterGCR = 0; break; } +#endif /* SAI2 */ switch (hsai->Init.Synchro) { @@ -485,6 +491,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) case SAI_SYNCHRONOUS : syncen_bits = SAI_xCR1_SYNCEN_0; break; +#if defined(SAI2) case SAI_SYNCHRONOUS_EXT_SAI1 : syncen_bits = SAI_xCR1_SYNCEN_1; break; @@ -492,11 +499,13 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) syncen_bits = SAI_xCR1_SYNCEN_1; tmpregisterGCR |= SAI_GCR_SYNCIN_0; break; +#endif /* SAI2 */ default : syncen_bits = 0; break; } +#if defined(SAI2) if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B)) { SAI1->GCR = tmpregisterGCR; @@ -505,21 +514,28 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) { SAI2->GCR = tmpregisterGCR; } +#else /* SAI2 */ + SAI1->GCR = 0; +#endif /* SAI2 */ if (hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV) { - uint32_t freq = 0; + uint32_t freq; uint32_t tmpval; /* In this case, the MCKDIV value is calculated to get AudioFrequency */ +#if defined(SAI2) if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B)) { freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1); } - if ((hsai->Instance == SAI2_Block_A) || (hsai->Instance == SAI2_Block_B)) + else { freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2); } +#else /* SAI2 */ + freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1); +#endif /* SAI2 */ /* Configure Master Clock Divider using the following formula : - If NODIV = 1 : @@ -534,12 +550,12 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL) { /* For SPDIF protocol, frame length is set by hardware to 64 */ - tmpframelength = 64U; + tmpframelength = SAI_SPDIF_FRAME_LENGTH; } else if (hsai->Init.Protocol == SAI_AC97_PROTOCOL) { /* For AC97 protocol, frame length is set by hardware to 256 */ - tmpframelength = 256U; + tmpframelength = SAI_AC97_FRAME_LENGTH; } else { @@ -2202,7 +2218,7 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) * the configuration information for SAI module. * @retval HAL state */ -HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) +HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai) { return hsai->State; } @@ -2213,7 +2229,7 @@ HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) * the configuration information for the specified SAI Block. * @retval SAI Error Code */ -uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai) +uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai) { return hsai->ErrorCode; } diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sai.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sai.h index 69a799d791f..18a69353181 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sai.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sai.h @@ -808,8 +808,8 @@ void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai); * @{ */ /* Peripheral State functions ************************************************/ -HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai); -uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); +HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai); +uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai); /** * @} */ @@ -822,9 +822,13 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Private_Macros SAI Private Macros * @{ */ +#if defined(SAI2) #define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\ ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\ ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE)) +#else /* SAI2 */ +#define IS_SAI_BLOCK_SYNCEXT(STATE) ((STATE) == SAI_SYNCEXT_DISABLE) +#endif /* SAI2 */ #define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_I2S_STANDARD) ||\ ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\ @@ -878,10 +882,15 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); #define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \ ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE)) +#if defined(SAI2) #define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \ ((SYNCHRO) == SAI_SYNCHRONOUS) || \ ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \ ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2)) +#else /* SAI2 */ +#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \ + ((SYNCHRO) == SAI_SYNCHRONOUS)) +#endif /* SAI2 */ #define IS_SAI_BLOCK_MCK_OUTPUT(VALUE) (((VALUE) == SAI_MCK_OUTPUT_ENABLE) || \ ((VALUE) == SAI_MCK_OUTPUT_DISABLE)) diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sai_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sai_ex.c index 6104e09ec58..ff309d5e656 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sai_ex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sai_ex.c @@ -73,7 +73,8 @@ * @param pdmMicDelay Microphone delays configuration. * @retval HAL status */ -HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay) +HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(const SAI_HandleTypeDef *hsai, + const SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay) { HAL_StatusTypeDef status = HAL_OK; uint32_t offset; diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sai_ex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sai_ex.h index bb81be746d2..4a471e8135b 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sai_ex.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sai_ex.h @@ -69,7 +69,8 @@ typedef struct /** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions * @{ */ -HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay); +HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(const SAI_HandleTypeDef *hsai, + const SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sd.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sd.c index 9602c5543e2..82b1a91d9bc 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sd.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sd.c @@ -193,7 +193,7 @@ The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_SD_RegisterCallback() to register a user callback, + Use Functions HAL_SD_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) TxCpltCallback : callback when a transmission transfer is completed. (+) RxCpltCallback : callback when a reception transfer is completed. @@ -208,9 +208,9 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. For specific callbacks TransceiverCallback use dedicated register callbacks: - respectively @ref HAL_SD_RegisterTransceiverCallback(). + respectively HAL_SD_RegisterTransceiverCallback(). - Use function @ref HAL_SD_UnRegisterCallback() to reset a callback to the default + Use function HAL_SD_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) TxCpltCallback : callback when a transmission transfer is completed. (+) RxCpltCallback : callback when a reception transfer is completed. @@ -222,14 +222,14 @@ (+) MspDeInitCallback : SD MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. For specific callbacks TransceiverCallback use dedicated unregister callbacks: - respectively @ref HAL_SD_UnRegisterTransceiverCallback(). + respectively HAL_SD_UnRegisterTransceiverCallback(). - By default, after the @ref HAL_SD_Init and if the state is HAL_SD_STATE_RESET + By default, after the HAL_SD_Init and if the state is HAL_SD_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_SD_Init - and @ref HAL_SD_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_SD_Init and @ref HAL_SD_DeInit + reset to the legacy weak (surcharged) functions in the HAL_SD_Init + and HAL_SD_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SD_Init and HAL_SD_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -237,14 +237,15 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_SD_RegisterCallback before calling @ref HAL_SD_DeInit - or @ref HAL_SD_Init function. + using HAL_SD_RegisterCallback before calling HAL_SD_DeInit + or HAL_SD_Init function. When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available and weak (surcharged) callbacks are used. @endverbatim + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -297,9 +298,9 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR); static void SD_PowerOFF(SD_HandleTypeDef *hsd); static void SD_Write_IT(SD_HandleTypeDef *hsd); static void SD_Read_IT(SD_HandleTypeDef *hsd); -static uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd); +static uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode); #if (USE_SD_TRANSCEIVER != 0U) -static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd); +static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd, uint32_t UltraHighSpeedMode); static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd); #endif /* USE_SD_TRANSCEIVER */ /** @@ -393,7 +394,7 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } - hsd->State = HAL_SD_STATE_BUSY; + hsd->State = HAL_SD_STATE_PROGRAMMING; /* Initialize the Card parameters */ if (HAL_SD_InitCard(hsd) != HAL_OK) @@ -474,7 +475,7 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; /* Init Clock should be less or equal to 400Khz*/ - sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC); + sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC); if (sdmmc_clk == 0U) { hsd->State = HAL_SD_STATE_READY; @@ -504,8 +505,15 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) /* wait 74 Cycles: required power up waiting time before starting the SD initialization sequence */ - sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); - HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); + if (Init.ClockDiv != 0U) + { + sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); + } + + if (sdmmc_clk != 0U) + { + HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); + } /* Identify card operating voltage */ errorstate = SD_PowerON(hsd); @@ -842,8 +850,8 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 * @param Timeout: Specify timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, - uint32_t Timeout) +HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks, uint32_t Timeout) { SDMMC_DataInitTypeDef config; uint32_t errorstate; @@ -852,7 +860,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint uint32_t data; uint32_t dataremaining; uint32_t add = BlockAdd; - uint8_t *tempbuff = pData; + const uint8_t *tempbuff = pData; if (NULL == pData) { @@ -1124,7 +1132,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui * @param NumberOfBlocks: Number of blocks to write * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, +HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; @@ -1320,7 +1328,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u * @param NumberOfBlocks: Number of blocks to write * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; @@ -1826,6 +1834,9 @@ __weak void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status) /** * @brief Register a User SD Callback * To be used instead of the weak (surcharged) predefined callback + * @note The HAL_SD_RegisterCallback() may be called before HAL_SD_Init() in + * HAL_SD_STATE_RESET to register callbacks for HAL_SD_MSP_INIT_CB_ID + * and HAL_SD_MSP_DEINIT_CB_ID. * @param hsd : SD handle * @param CallbackID : ID of the callback to be registered * This parameter can be one of the following values: @@ -1852,9 +1863,6 @@ HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callback return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsd); - if (hsd->State == HAL_SD_STATE_READY) { switch (CallbackID) @@ -1917,14 +1925,15 @@ HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callback status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsd); return status; } /** * @brief Unregister a User SD Callback * SD Callback is redirected to the weak (surcharged) predefined callback + * @note The HAL_SD_UnRegisterCallback() may be called before HAL_SD_Init() in + * HAL_SD_STATE_RESET to register callbacks for HAL_SD_MSP_INIT_CB_ID + * and HAL_SD_MSP_DEINIT_CB_ID. * @param hsd : SD handle * @param CallbackID : ID of the callback to be unregistered * This parameter can be one of the following values: @@ -1942,9 +1951,6 @@ HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callba { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hsd); - if (hsd->State == HAL_SD_STATE_READY) { switch (CallbackID) @@ -2007,8 +2013,6 @@ HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callba status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsd); return status; } @@ -2251,7 +2255,7 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef } /** - * @brief Gets the SD status info. + * @brief Gets the SD status info.( shall be called if there is no SD transaction ongoing ) * @param hsd: Pointer to SD handle * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that * will contain the SD card status information @@ -2263,6 +2267,11 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT uint32_t errorstate; HAL_StatusTypeDef status = HAL_OK; + if (hsd->State == HAL_SD_STATE_BUSY) + { + return HAL_ERROR; + } + errorstate = SD_SendSDStatus(hsd, sd_status); if (errorstate != HAL_SD_ERROR_NONE) { @@ -2311,6 +2320,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT status = HAL_ERROR; } + return status; } @@ -2385,7 +2395,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t } else { - /* MMC Card does not support this feature */ + /* SD Card does not support this feature */ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; } @@ -2397,7 +2407,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t } else { - sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC); + sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC); if (sdmmc_clk != 0U) { /* Configure the SDMMC peripheral */ @@ -2533,9 +2543,9 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t { hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED; /* Enable Ultra High Speed */ - if (SD_UltraHighSpeed(hsd) != HAL_SD_ERROR_NONE) + if (SD_UltraHighSpeed(hsd, SDMMC_SDR104_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) { - if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; status = HAL_ERROR; @@ -2545,7 +2555,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) { /* Enable High Speed */ - if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; status = HAL_ERROR; @@ -2557,13 +2567,33 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t } break; } - case SDMMC_SPEED_MODE_ULTRA: + case SDMMC_SPEED_MODE_ULTRA_SDR104: + { + if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + /* Enable UltraHigh Speed */ + if (SD_UltraHighSpeed(hsd, SDMMC_SDR104_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED; + } + else + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; + } + case SDMMC_SPEED_MODE_ULTRA_SDR50: { if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { /* Enable UltraHigh Speed */ - if (SD_UltraHighSpeed(hsd) != HAL_SD_ERROR_NONE) + if (SD_UltraHighSpeed(hsd, SDMMC_SDR50_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; status = HAL_ERROR; @@ -2604,7 +2634,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { /* Enable High Speed */ - if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; status = HAL_ERROR; @@ -2618,7 +2648,16 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t break; } case SDMMC_SPEED_MODE_DEFAULT: + { + /* Switch to default Speed */ + if (SD_SwitchSpeed(hsd, SDMMC_SDR12_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; + } default: hsd->ErrorCode |= HAL_SD_ERROR_PARAM; status = HAL_ERROR; @@ -2636,7 +2675,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { /* Enable High Speed */ - if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; status = HAL_ERROR; @@ -2655,7 +2694,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { /* Enable High Speed */ - if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; status = HAL_ERROR; @@ -2669,7 +2708,16 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t break; } case SDMMC_SPEED_MODE_DEFAULT: + { + /* Switch to default Speed */ + if (SD_SwitchSpeed(hsd, SDMMC_SDR12_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; + } case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/ default: hsd->ErrorCode |= HAL_SD_ERROR_PARAM; @@ -2687,7 +2735,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { /* Enable High Speed */ - if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; status = HAL_ERROR; @@ -2706,7 +2754,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { /* Enable High Speed */ - if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; status = HAL_ERROR; @@ -2720,7 +2768,16 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t break; } case SDMMC_SPEED_MODE_DEFAULT: + { + /* Switch to default Speed */ + if (SD_SwitchSpeed(hsd, SDMMC_SDR12_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; + } case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/ default: hsd->ErrorCode |= HAL_SD_ERROR_PARAM; @@ -2786,35 +2843,94 @@ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) */ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) { - HAL_SD_CardStateTypeDef CardState; + uint32_t error_code; + uint32_t tickstart; - /* DIsable All interrupts */ - __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ - SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); + if (hsd->State == HAL_SD_STATE_BUSY) + { + /* DIsable All interrupts */ + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); + __SDMMC_CMDTRANS_DISABLE(hsd->Instance); - /* Clear All flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + /*we will send the CMD12 in all cases in order to stop the data transfers*/ + /*In case the data transfer just finished , the external memory will not respond and will return HAL_SD_ERROR_CMD_RSP_TIMEOUT*/ + /*In case the data transfer aborted , the external memory will respond and will return HAL_SD_ERROR_NONE*/ + /*Other scenario will return HAL_ERROR*/ - /* If IDMA Context, disable Internal DMA */ - hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); + error_code = hsd->ErrorCode; + if ((error_code != HAL_SD_ERROR_NONE) && (error_code != HAL_SD_ERROR_CMD_RSP_TIMEOUT)) + { + return HAL_ERROR; + } - hsd->State = HAL_SD_STATE_READY; + tickstart = HAL_GetTick(); + if ((hsd->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_CARD) + { + if (hsd->ErrorCode == HAL_SD_ERROR_NONE) + { + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } + } + } - /* Initialize the SD operation */ - hsd->Context = SD_CONTEXT_NONE; + if (hsd->ErrorCode == HAL_SD_ERROR_CMD_RSP_TIMEOUT) + { + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } + } + } + } + else if ((hsd->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_SDMMC) + { + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } + } + } + else + { + /* Nothing to do*/ + } - CardState = HAL_SD_GetCardState(hsd); - if ((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) - { - hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); - } - if (hsd->ErrorCode != HAL_SD_ERROR_NONE) - { - return HAL_ERROR; + /*The reason of all these while conditions previously is that we need to wait the SDMMC and clear + the appropriate flags that will be set depending of the abort/non abort of the memory */ + /*Not waiting the SDMMC flags will cause the next SDMMC_DISABLE_IDMA to not get cleared + and will result in next SDMMC read/write operation to fail */ + + /*SDMMC ready for clear data flags*/ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_BUSYD0END); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + /* If IDMA Context, disable Internal DMA */ + hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + + hsd->State = HAL_SD_STATE_READY; + + /* Initialize the SD operation */ + hsd->Context = SD_CONTEXT_NONE; } return HAL_OK; } + /** * @brief Abort the current transfer and disable the SD (IT mode). * @param hsd: pointer to a SD_HandleTypeDef structure that contains @@ -2882,7 +2998,8 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) { HAL_SD_CardCSDTypeDef CSD; uint32_t errorstate; - uint16_t sd_rca = 1U; + uint16_t sd_rca = 0U; + uint32_t tickstart = HAL_GetTick(); /* Check the power State */ if (SDMMC_GetPowerState(hsd->Instance) == 0U) @@ -2913,10 +3030,17 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) { /* Send CMD3 SET_REL_ADDR with argument 0 */ /* SD Card publishes its RCA. */ - errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca); - if (errorstate != HAL_SD_ERROR_NONE) + while (sd_rca == 0U) { - return errorstate; + errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca); + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + if ((HAL_GetTick() - tickstart) >= SDMMC_CMDTIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } } } if (hsd->SdCard.CardType != CARD_SECURED) @@ -2986,7 +3110,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */ errorstate = SDMMC_CmdOperCond(hsd->Instance); - if (errorstate != HAL_SD_ERROR_NONE) + if (errorstate == SDMMC_ERROR_TIMEOUT) /* No response to CMD8 */ { hsd->SdCard.CardVersion = CARD_V1_X; /* CMD0: GO_IDLE_STATE */ @@ -3044,7 +3168,10 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) return HAL_SD_ERROR_INVALID_VOLTRANGE; } - if ((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ + /* Set default card type */ + hsd->SdCard.CardType = CARD_SDSC; + + if ((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) { hsd->SdCard.CardType = CARD_SDHC_SDXC; #if (USE_SD_TRANSCEIVER != 0U) @@ -3510,7 +3637,7 @@ static void SD_Write_IT(SD_HandleTypeDef *hsd) { uint32_t count; uint32_t data; - uint8_t *tmp; + const uint8_t *tmp; tmp = hsd->pTxBuffPtr; @@ -3539,11 +3666,12 @@ static void SD_Write_IT(SD_HandleTypeDef *hsd) * @brief Switches the SD card to High Speed mode. * This API must be used after "Transfer State" * @note This operation should be followed by the configuration - * of PLL to have SDMMCCK clock between 50 and 120 MHz + * of PLL to have SDMMCCK clock between 25 and 50 MHz * @param hsd: SD handle + * @param SwitchSpeedMode: SD speed mode( SDMMC_SDR12_SWITCH_PATTERN, SDMMC_SDR25_SWITCH_PATTERN) * @retval SD Card error state */ -uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd) +uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode) { uint32_t errorstate = HAL_SD_ERROR_NONE; SDMMC_DataInitTypeDef sdmmc_datainitstructure; @@ -3558,7 +3686,7 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd) return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; } - if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) + if (hsd->SdCard.CardSpeed >= CARD_HIGH_SPEED) { /* Initialize the Data control register */ hsd->Instance->DCTRL = 0; @@ -3580,7 +3708,7 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd) (void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure); - errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR25_SWITCH_PATTERN); + errorstate = SDMMC_CmdSwitch(hsd->Instance, SwitchSpeedMode); if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; @@ -3654,9 +3782,10 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd) * @note This operation should be followed by the configuration * of PLL to have SDMMCCK clock between 50 and 120 MHz * @param hsd: SD handle + * @param UltraHighSpeedMode: SD speed mode( SDMMC_SDR50_SWITCH_PATTERN, SDMMC_SDR104_SWITCH_PATTERN) * @retval SD Card error state */ -static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd) +static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd, uint32_t UltraHighSpeedMode) { uint32_t errorstate = HAL_SD_ERROR_NONE; SDMMC_DataInitTypeDef sdmmc_datainitstructure; @@ -3695,7 +3824,7 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd) return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR); } - errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR104_SWITCH_PATTERN); + errorstate = SDMMC_CmdSwitch(hsd->Instance, UltraHighSpeedMode); if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sd.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sd.h index 94f68ab28c7..144819b2113 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sd.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sd.h @@ -126,7 +126,7 @@ typedef struct HAL_LockTypeDef Lock; /*!< SD locking object */ - uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */ uint32_t TxXferSize; /*!< SD Tx Transfer size */ @@ -293,7 +293,7 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup SD_Exported_Constants Exported Constants +/** @defgroup SD_Exported_Constants SD Exported Constants * @{ */ @@ -630,18 +630,18 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); -HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, - uint32_t Timeout); +HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks, uint32_t Timeout); HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd); /* Non-Blocking mode: IT */ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, +HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd); diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sd_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sd_ex.c index d017a7990a0..9df46db9e77 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sd_ex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sd_ex.c @@ -29,6 +29,7 @@ and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions. @endverbatim + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -388,7 +389,3 @@ HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd, SDMM /** * @} */ - -/** - * @} - */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smartcard.c index e4f045754b6..3ba04706a42 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smartcard.c @@ -177,6 +177,7 @@ @endverbatim + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -236,6 +237,7 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard); static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard); +#if defined(HAL_DMA_MODULE_ENABLED) static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma); @@ -244,6 +246,7 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma); static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma); static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +#endif /* HAL_DMA_MODULE_ENABLED */ static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard); static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard); static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); @@ -467,6 +470,9 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief Register a User SMARTCARD Callback * To be used instead of the weak predefined callback + * @note The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init() + * in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID + * and HAL_SMARTCARD_MSPDEINIT_CB_ID * @param hsmartcard smartcard handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -496,8 +502,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmart return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsmartcard); if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { @@ -583,15 +587,15 @@ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmart status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmartcard); - return status; } /** * @brief Unregister an SMARTCARD callback * SMARTCARD callback is redirected to the weak predefined callback + * @note The HAL_SMARTCARD_UnRegisterCallback() may be called before HAL_SMARTCARD_Init() + * in HAL_SMARTCARD_STATE_RESET to un-register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID + * and HAL_SMARTCARD_MSPDEINIT_CB_ID * @param hsmartcard smartcard handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -612,9 +616,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hsmartcard); - if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState) { switch (CallbackID) @@ -700,9 +701,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmartcard); - return status; } #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ @@ -808,11 +806,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; - uint8_t *ptmpdata = pData; + const uint8_t *ptmpdata = pData; /* Check that a Tx process is not already ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) @@ -982,7 +980,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin * @param Size amount of data to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) @@ -1132,6 +1130,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, } } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Send an amount of data in DMA mode. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains @@ -1140,7 +1139,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, * @param Size amount of data to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef status; @@ -1368,6 +1367,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, return HAL_BUSY; } } +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Abort ongoing transfers (blocking mode). @@ -1391,6 +1391,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); +#if defined(HAL_DMA_MODULE_ENABLED) /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { @@ -1440,6 +1441,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) } } } +#endif /* HAL_DMA_MODULE_ENABLED */ /* Reset Tx and Rx transfer counters */ hsmartcard->TxXferCount = 0U; @@ -1486,6 +1488,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); } +#if defined(HAL_DMA_MODULE_ENABLED) /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { @@ -1510,6 +1513,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar } } } +#endif /* HAL_DMA_MODULE_ENABLED */ /* Reset Tx transfer counter */ hsmartcard->TxXferCount = 0U; @@ -1550,6 +1554,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); } +#if defined(HAL_DMA_MODULE_ENABLED) /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { @@ -1574,6 +1579,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard } } } +#endif /* HAL_DMA_MODULE_ENABLED */ /* Reset Rx transfer counter */ hsmartcard->RxXferCount = 0U; @@ -1615,6 +1621,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); +#if defined(HAL_DMA_MODULE_ENABLED) /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ @@ -1694,6 +1701,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) } } } +#endif /* HAL_DMA_MODULE_ENABLED */ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ if (abortcplt == 1U) @@ -1759,6 +1767,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); } +#if defined(HAL_DMA_MODULE_ENABLED) /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { @@ -1800,6 +1809,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart } } else +#endif /* HAL_DMA_MODULE_ENABLED */ { /* Reset Tx transfer counter */ hsmartcard->TxXferCount = 0U; @@ -1855,6 +1865,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); } +#if defined(HAL_DMA_MODULE_ENABLED) /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { @@ -1901,6 +1912,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc } } else +#endif /* HAL_DMA_MODULE_ENABLED */ { /* Reset Rx transfer counter */ hsmartcard->RxXferCount = 0U; @@ -2036,6 +2048,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ SMARTCARD_EndRxTransfer(hsmartcard); +#if defined(HAL_DMA_MODULE_ENABLED) /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { @@ -2067,6 +2080,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) } } else +#endif /* HAL_DMA_MODULE_ENABLED */ { #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) /* Call registered user error callback */ @@ -2088,6 +2102,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) Disable Tx Interrupts, and disable Tx DMA request, if ongoing */ SMARTCARD_EndTxTransfer(hsmartcard); +#if defined(HAL_DMA_MODULE_ENABLED) /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { @@ -2119,6 +2134,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) } } else +#endif /* HAL_DMA_MODULE_ENABLED */ { #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) /* Call registered user error callback */ @@ -2339,7 +2355,7 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsma * the configuration information for the specified SMARTCARD module. * @retval SMARTCARD handle state */ -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard) +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard) { /* Return SMARTCARD handle state */ uint32_t temp1; @@ -2356,7 +2372,7 @@ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmar * the configuration information for the specified SMARTCARD module. * @retval SMARTCARD handle Error Code */ -uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) +uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard) { return hsmartcard->ErrorCode; } @@ -2483,25 +2499,25 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard { case SMARTCARD_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_HSI: - tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + tmpreg = (uint32_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_LSE: - tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + tmpreg = (uint32_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; default: @@ -2512,7 +2528,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard /* USARTDIV must be greater than or equal to 0d16 */ if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX)) { - hsmartcard->Instance->BRR = tmpreg; + hsmartcard->Instance->BRR = (uint16_t)tmpreg; } else { @@ -2643,11 +2659,12 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar } /** - * @brief Handle SMARTCARD Communication Timeout. + * @brief Handle SMARTCARD Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @param Flag Specifies the SMARTCARD flag to check. - * @param Status The new Flag status (SET or RESET). + * @param Status The actual Flag status (SET or RESET). * @param Tickstart Tick start value * @param Timeout Timeout duration. * @retval HAL status @@ -2715,6 +2732,7 @@ static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief DMA SMARTCARD transmit process complete callback. * @param hdma Pointer to a DMA_HandleTypeDef structure that contains @@ -2983,6 +3001,7 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard); #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Send an amount of data in non-blocking mode. diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smartcard.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smartcard.h index f18abfc3a0c..31e92e22b7d 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smartcard.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smartcard.h @@ -201,7 +201,7 @@ typedef struct __SMARTCARD_HandleTypeDef SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */ uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */ @@ -225,10 +225,12 @@ typedef struct __SMARTCARD_HandleTypeDef void (*TxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ +#if defined(HAL_DMA_MODULE_ENABLED) DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */ DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */ +#endif /* HAL_DMA_MODULE_ENABLED */ HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global @@ -350,7 +352,9 @@ typedef enum #define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */ #define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */ #define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#if defined(HAL_DMA_MODULE_ENABLED) #define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#endif /* HAL_DMA_MODULE_ENABLED */ #define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */ #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) #define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ @@ -951,7 +955,7 @@ typedef enum (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) -#else +#elif defined(USART2) #define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ @@ -1022,6 +1026,56 @@ typedef enum (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) +#else +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) #endif /* USART6 */ /** @brief Check the Baud rate range. @@ -1246,14 +1300,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma * @{ */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); +#endif /* HAL_DMA_MODULE_ENABLED */ /* Transfer Abort functions */ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard); HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard); @@ -1279,8 +1335,8 @@ void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) * @{ */ -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard); -uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard); +uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard); /** * @} @@ -1303,3 +1359,4 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmar #endif #endif /* STM32U5xx_HAL_SMARTCARD_H */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smartcard_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smartcard_ex.c index a9ad00d44c6..b662cf32bcd 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smartcard_ex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smartcard_ex.c @@ -37,6 +37,7 @@ configured prior starting RX/TX transfers. @endverbatim + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smartcard_ex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smartcard_ex.h index 4470cbd50ec..3f1d66114a8 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smartcard_ex.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smartcard_ex.h @@ -333,3 +333,4 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hs #endif #endif /* STM32U5xx_HAL_SMARTCARD_EX_H */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smbus.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smbus.c index 5f334d8fbe4..788393f115e 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smbus.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smbus.c @@ -31,7 +31,7 @@ (#) Declare a SMBUS_HandleTypeDef handle structure, for example: SMBUS_HandleTypeDef hsmbus; - (#)Initialize the SMBUS low level resources by implementing the @ref HAL_SMBUS_MspInit() API: + (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API: (##) Enable the SMBUSx interface clock (##) SMBUS pins configuration (+++) Enable the clock for the SMBUS GPIOs @@ -44,11 +44,11 @@ Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode, Peripheral mode and Packet Error Check mode in the hsmbus Init structure. - (#) Initialize the SMBUS registers by calling the @ref HAL_SMBUS_Init() API: + (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API: (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customized @ref HAL_SMBUS_MspInit(&hsmbus) API. + by calling the customized HAL_SMBUS_MspInit(&hsmbus) API. - (#) To check if target device is ready for communication, use the function @ref HAL_SMBUS_IsDeviceReady() + (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady() (#) For SMBUS IO operations, only one mode of operations is available within this driver @@ -56,62 +56,63 @@ =================================== [..] (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode - using @ref HAL_SMBUS_Master_Transmit_IT() - (++) At transmission end of transfer @ref HAL_SMBUS_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_MasterTxCpltCallback() + using HAL_SMBUS_Master_Transmit_IT() + (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback() (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode - using @ref HAL_SMBUS_Master_Receive_IT() - (++) At reception end of transfer @ref HAL_SMBUS_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_MasterRxCpltCallback() - (+) Abort a master/host SMBUS process communication with Interrupt using @ref HAL_SMBUS_Master_Abort_IT() + using HAL_SMBUS_Master_Receive_IT() + (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback() + (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT() (++) The associated previous transfer callback is called at the end of abort process - (++) mean @ref HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit - (++) mean @ref HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive + (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit + (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode - using @ref HAL_SMBUS_EnableListen_IT() @ref HAL_SMBUS_DisableListen_IT() - (++) When address slave/device SMBUS match, @ref HAL_SMBUS_AddrCallback() is executed and user can - add his own code to check the Address Match Code and the transmission direction + using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT() + (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction request by master/host (Write/Read). - (++) At Listen mode end @ref HAL_SMBUS_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_ListenCpltCallback() + (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_ListenCpltCallback() (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode - using @ref HAL_SMBUS_Slave_Transmit_IT() - (++) At transmission end of transfer @ref HAL_SMBUS_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_SlaveTxCpltCallback() + using HAL_SMBUS_Slave_Transmit_IT() + (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback() (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode - using @ref HAL_SMBUS_Slave_Receive_IT() - (++) At reception end of transfer @ref HAL_SMBUS_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_SlaveRxCpltCallback() - (+) Enable/Disable the SMBUS alert mode using @ref HAL_SMBUS_EnableAlert_IT() @ref HAL_SMBUS_DisableAlert_IT() - (++) When SMBUS Alert is generated @ref HAL_SMBUS_ErrorCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback() - to check the Alert Error Code using function @ref HAL_SMBUS_GetError() - (+) Get HAL state machine or error values using @ref HAL_SMBUS_GetState() or @ref HAL_SMBUS_GetError() - (+) In case of transfer Error, @ref HAL_SMBUS_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback() - to check the Error Code using function @ref HAL_SMBUS_GetError() + using HAL_SMBUS_Slave_Receive_IT() + (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback() + (+) Enable/Disable the SMBUS alert mode using + HAL_SMBUS_EnableAlert_IT() or HAL_SMBUS_DisableAlert_IT() + (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_ErrorCallback() + to check the Alert Error Code using function HAL_SMBUS_GetError() + (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError() + (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_SMBUS_ErrorCallback() + to check the Error Code using function HAL_SMBUS_GetError() *** SMBUS HAL driver macros list *** ================================== [..] Below the list of most used macros in SMBUS HAL driver. - (+) @ref __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral - (+) @ref __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral - (+) @ref __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not - (+) @ref __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag - (+) @ref __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt - (+) @ref __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt + (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral + (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral + (+) __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not + (+) __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag + (+) __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt + (+) __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt *** Callback registration *** ============================================= [..] The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback() + Use Functions HAL_SMBUS_RegisterCallback() or HAL_SMBUS_RegisterAddrCallback() to register an interrupt callback. [..] - Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks: + Function HAL_SMBUS_RegisterCallback() allows to register following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer. (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. @@ -123,11 +124,11 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback. + For specific callback AddrCallback use dedicated register callbacks : HAL_SMBUS_RegisterAddrCallback. [..] - Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default + Use function HAL_SMBUS_UnRegisterCallback to reset a callback to the default weak function. - @ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. @@ -139,24 +140,24 @@ (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. [..] - For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback. + For callback AddrCallback use dedicated register callbacks : HAL_SMBUS_UnRegisterAddrCallback. [..] - By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET + By default, after the HAL_SMBUS_Init() and when the state is HAL_I2C_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback(). + examples HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MasterRxCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() only when + reset to the legacy weak functions in the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() only when these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() + If MspInit or MspDeInit are not null, the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, + in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit() - or @ref HAL_SMBUS_Init() function. + using HAL_SMBUS_RegisterCallback() before calling HAL_SMBUS_DeInit() + or HAL_SMBUS_Init() function. [..] When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks @@ -207,20 +208,28 @@ /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions * @{ */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, - uint32_t Timeout); +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, + FlagStatus Status, uint32_t Timeout); -static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); -static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); +/* Private functions for SMBUS transfer IRQ handler */ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); -static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); +/* Private functions to centralize the enable/disable of Interrupts */ +static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); +static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); -static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); +/* Private function to flush TXDR register */ +static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus); + +/* Private function to handle start, restart or stop a transfer */ +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, + uint32_t Mode, uint32_t Request); -static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, - uint32_t Request); +/* Private function to Convert Specific options */ +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); /** * @} */ @@ -352,24 +361,26 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) } } + /*---------------------------- SMBUSx CR2 Configuration ------------------------*/ /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */ /* AUTOEND and NACK bit will be manage during Transfer process */ hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/ /* Configure SMBUSx: Dual mode and Own Address2 */ - hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | \ + hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | \ (hsmbus->Init.OwnAddress2Masks << 8U)); /*---------------------------- SMBUSx CR1 Configuration ------------------------*/ /* Configure SMBUSx: Generalcall and NoStretch mode */ - hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | \ - hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter); + hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | \ + hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | \ + hsmbus->Init.AnalogFilter); /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */ - if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) && \ - ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ + if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) && \ + ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))) { hsmbus->Instance->CR1 |= I2C_CR1_SBC; @@ -564,6 +575,9 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin /** * @brief Register a User SMBUS Callback * To be used instead of the weak predefined callback + * @note The HAL_SMBUS_RegisterCallback() may be called before HAL_SMBUS_Init() in + * HAL_SMBUS_STATE_RESET to register callbacks for HAL_SMBUS_MSPINIT_CB_ID and + * HAL_SMBUS_MSPDEINIT_CB_ID. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param CallbackID ID of the callback to be registered @@ -579,7 +593,8 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, +HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -592,9 +607,6 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SM return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsmbus); - if (HAL_SMBUS_STATE_READY == hsmbus->State) { switch (CallbackID) @@ -670,14 +682,15 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SM status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmbus); return status; } /** * @brief Unregister an SMBUS Callback * SMBUS callback is redirected to the weak predefined callback + * @note The HAL_SMBUS_UnRegisterCallback() may be called before HAL_SMBUS_Init() in + * HAL_SMBUS_STATE_RESET to un-register callbacks for HAL_SMBUS_MSPINIT_CB_ID and + * HAL_SMBUS_MSPDEINIT_CB_ID * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param CallbackID ID of the callback to be unregistered @@ -693,13 +706,11 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SM * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID) +HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hsmbus); - if (HAL_SMBUS_STATE_READY == hsmbus->State) { switch (CallbackID) @@ -775,8 +786,6 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmbus); return status; } @@ -788,7 +797,8 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_ * @param pCallback pointer to the Address Match Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, + pSMBUS_AddrCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -799,8 +809,6 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pS return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsmbus); if (HAL_SMBUS_STATE_READY == hsmbus->State) { @@ -815,8 +823,6 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pS status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmbus); return status; } @@ -831,9 +837,6 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hsmbus); - if (HAL_SMBUS_STATE_READY == hsmbus->State) { hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */ @@ -847,8 +850,6 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmbus); return status; } @@ -912,8 +913,8 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions) { uint32_t tmp; @@ -955,13 +956,15 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* Check if the Autonomous mode is enabled */ if ((hsmbus->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | \ - (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_NO_START_WRITE); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_GENERATE_NO_START_WRITE); } else { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | \ - (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_GENERATE_START_WRITE); } } else @@ -972,10 +975,11 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* Store current volatile XferOptions, misra rule */ tmp = hsmbus->XferOptions; - if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \ + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \ (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -987,12 +991,14 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* Check if the Autonomous mode is enabled */ if ((hsmbus->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + hsmbus->XferOptions, SMBUS_GENERATE_NO_START_WRITE); } else { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); } } @@ -1077,13 +1083,15 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 /* Check if the Autonomous mode is enabled */ if ((hsmbus->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | \ - (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_NO_START_READ); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_GENERATE_NO_START_READ); } else { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | \ - (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_GENERATE_START_READ); } } else @@ -1094,10 +1102,11 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 /* Store current volatile XferOptions, Misra rule */ tmp = hsmbus->XferOptions; - if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && \ + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && \ (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -1109,12 +1118,14 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 /* Check if the Autonomous mode is enabled */ if ((hsmbus->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + hsmbus->XferOptions, SMBUS_GENERATE_NO_START_READ); } else { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + hsmbus->XferOptions, SMBUS_GENERATE_START_READ); } } @@ -1260,12 +1271,14 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, - SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_NO_STARTSTOP); } else { /* Set NBYTE to transmit */ - SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ @@ -1351,7 +1364,8 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U)) { - SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); } else { @@ -1614,12 +1628,13 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1); /* SMBUS in mode Transmitter ---------------------------------------------------*/ - if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) \ - && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || \ - (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || \ - (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || \ - (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || \ - (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) + if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | + SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && + ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) @@ -1638,12 +1653,13 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS in mode Receiver ----------------------------------------------------*/ - if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) \ - && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || \ - (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || \ - (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || \ - (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || \ - (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) + if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | + SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && + ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) @@ -1662,11 +1678,11 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS in mode Listener Only --------------------------------------------------*/ - if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || \ - (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || \ - (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && \ - ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || \ - (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || \ + if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || + (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || + (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && + ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) { if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) @@ -1758,7 +1774,8 @@ __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) * @param AddrMatchCode Address Match Code * @retval None */ -__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode) +__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, + uint16_t AddrMatchCode) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmbus); @@ -1827,7 +1844,7 @@ __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval HAL state */ -uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus) +uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus) { /* Return SMBUS handle state */ return hsmbus->State; @@ -1839,7 +1856,7 @@ uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval SMBUS Error Code */ -uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) +uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus) { return hsmbus->ErrorCode; } @@ -1880,6 +1897,9 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t /* No need to generate STOP, it is automatically done */ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); @@ -2005,13 +2025,15 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t if (hsmbus->XferCount > MAX_NBYTE_SIZE) { SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, - (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); + (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), + SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } else { hsmbus->XferSize = hsmbus->XferCount; - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) @@ -2168,6 +2190,9 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S /* Clear NACK Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); } @@ -2189,6 +2214,9 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S /* Set ErrorCode corresponding to a Non-Acknowledge */ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); @@ -2219,7 +2247,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } - else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || \ + else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)) { if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) @@ -2263,7 +2291,8 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S else { /* Set Reload for next Bytes */ - SMBUS_TransferConfig(hsmbus, 0, 1, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_TransferConfig(hsmbus, 0, 1, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); /* Ack last Byte Read */ @@ -2277,13 +2306,15 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S if (hsmbus->XferCount > MAX_NBYTE_SIZE) { SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, - (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); + (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), + SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } else { hsmbus->XferSize = hsmbus->XferCount; - SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) @@ -2528,7 +2559,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) uint32_t tmperror; /* SMBUS Bus error interrupt occurred ------------------------------------*/ - if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR; @@ -2537,7 +2569,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR; @@ -2546,7 +2579,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ - if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO; @@ -2555,7 +2589,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ - if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT; @@ -2564,7 +2599,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ - if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT; @@ -2573,7 +2609,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ - if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; @@ -2581,7 +2618,10 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); } - /* Store current volatile hsmbus->State, misra rule */ + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + + /* Store current volatile hsmbus->ErrorCode, misra rule */ tmperror = hsmbus->ErrorCode; /* Call the Error Callback in case of Error detected */ @@ -2621,8 +2661,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, - uint32_t Timeout) +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, + FlagStatus Status, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); @@ -2651,6 +2691,27 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu return HAL_OK; } +/** + * @brief SMBUS Tx data register flush process. + * @param hsmbus SMBUS handle. + * @retval None + */ +static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + { + hsmbus->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXE) == RESET) + { + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TXE); + } +} + /** * @brief Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set). * @param hsmbus SMBUS handle. @@ -2671,8 +2732,8 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ -static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, - uint32_t Request) +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, + uint32_t Mode, uint32_t Request) { /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); @@ -2680,11 +2741,12 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre assert_param(IS_SMBUS_TRANSFER_REQUEST(Request)); /* update CR2 register */ - MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ - (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | \ - I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ - (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + MODIFY_REG(hsmbus->Instance->CR2, + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ (uint32_t)Mode | (uint32_t)Request)); } diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smbus.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smbus.h index e231b8f62ef..da6299fdeb3 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smbus.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smbus.h @@ -47,42 +47,43 @@ extern "C" { typedef struct { uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. - This parameter calculated by referring to SMBUS initialization - section in Reference manual */ + This parameter calculated by referring to SMBUS initialization section + in Reference manual */ uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. - This parameter can be a value of @ref SMBUS_Analog_Filter */ + This parameter can be a value of @ref SMBUS_Analog_Filter */ uint32_t OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit address. */ + This parameter can be a 7-bit address. */ uint32_t AddressingMode; /*!< Specifies addressing mode selected. - This parameter can be a value of @ref SMBUS_addressing_mode */ + This parameter can be a value of @ref SMBUS_addressing_mode */ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref SMBUS_dual_addressing_mode */ + This parameter can be a value of @ref SMBUS_dual_addressing_mode */ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ + This parameter can be a 7-bit address. */ - uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected - This parameter can be a value of @ref SMBUS_own_address2_masks. */ + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address + if dual addressing mode is selected + This parameter can be a value of @ref SMBUS_own_address2_masks. */ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ + This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref SMBUS_nostretch_mode */ + This parameter can be a value of @ref SMBUS_nostretch_mode */ uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. - This parameter can be a value of @ref SMBUS_packet_error_check_mode */ + This parameter can be a value of @ref SMBUS_packet_error_check_mode */ uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. - This parameter can be a value of @ref SMBUS_peripheral_mode */ + This parameter can be a value of @ref SMBUS_peripheral_mode */ uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. - (Enable bits and different timeout values) - This parameter calculated by referring to SMBUS initialization - section in Reference manual */ + (Enable bits and different timeout values) + This parameter calculated by referring to SMBUS initialization section + in Reference manual */ } SMBUS_InitTypeDef; /** * @} @@ -101,7 +102,7 @@ typedef struct #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ #define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ #define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ -#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ +#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ /** * @} */ @@ -120,7 +121,7 @@ typedef struct #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) -#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ #define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ /** @@ -158,17 +159,26 @@ typedef struct __IO uint32_t ErrorCode; /*!< SMBUS Error code */ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) - void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Tx Transfer completed callback */ - void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Rx Transfer completed callback */ - void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Tx Transfer completed callback */ - void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Rx Transfer completed callback */ - void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Listen Complete callback */ - void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Error callback */ - - void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< SMBUS Slave Address Match callback */ - - void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp Init callback */ - void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp DeInit callback */ + void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Listen Complete callback */ + void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Error callback */ + + void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< SMBUS Slave Address Match callback */ + + void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Msp Init callback */ + void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Msp DeInit callback */ #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } SMBUS_HandleTypeDef; @@ -194,8 +204,11 @@ typedef enum /** * @brief HAL SMBUS Callback pointer definition */ -typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an SMBUS callback function */ -typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an SMBUS Address Match callback function */ +typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); +/*!< pointer to an SMBUS callback function */ +typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an SMBUS Address Match callback function */ #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ /** @@ -351,17 +364,19 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * - XXXXXXXX : Interrupt control mask * @{ */ -#define SMBUS_IT_ERRI I2C_CR1_ERRIE -#define SMBUS_IT_TCI I2C_CR1_TCIE -#define SMBUS_IT_STOPI I2C_CR1_STOPIE -#define SMBUS_IT_NACKI I2C_CR1_NACKIE -#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE -#define SMBUS_IT_RXI I2C_CR1_RXIE -#define SMBUS_IT_TXI I2C_CR1_TXIE -#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI) -#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI) -#define SMBUS_IT_ALERT (SMBUS_IT_ERRI) -#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) +#define SMBUS_IT_ERRI I2C_CR1_ERRIE +#define SMBUS_IT_TCI I2C_CR1_TCIE +#define SMBUS_IT_STOPI I2C_CR1_STOPIE +#define SMBUS_IT_NACKI I2C_CR1_NACKIE +#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE +#define SMBUS_IT_RXI I2C_CR1_RXIE +#define SMBUS_IT_TXI I2C_CR1_TXIE +#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \ + SMBUS_IT_NACKI | SMBUS_IT_TXI) +#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \ + SMBUS_IT_RXI) +#define SMBUS_IT_ALERT (SMBUS_IT_ERRI) +#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) /** * @} */ @@ -407,14 +422,14 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * @retval None */ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) -#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ +#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) -#endif /*USE_HAL_SMBUS_REGISTER_CALLBACKS*/ +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ /** @brief Enable the specified SMBUS interrupts. * @param __HANDLE__ specifies the SMBUS Handle. @@ -462,8 +477,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \ - (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SMBUS flag is set or not. * @param __HANDLE__ specifies the SMBUS Handle. @@ -489,14 +504,15 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * @retval The new state of __FLAG__ (SET or RESET). */ #define SMBUS_FLAG_MASK (0x0001FFFFU) -#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \ - ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & \ - SMBUS_FLAG_MASK)) ? SET : RESET) +#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \ + (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ + ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the SMBUS Handle. * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: + * @arg @ref SMBUS_FLAG_TXE Transmit data register empty * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) * @arg @ref SMBUS_FLAG_AF NACK received flag * @arg @ref SMBUS_FLAG_STOPF STOP detection flag @@ -509,7 +525,9 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * * @retval None */ -#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) +#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == SMBUS_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) /** @brief Enable the specified SMBUS peripheral. * @param __HANDLE__ specifies the SMBUS Handle. @@ -541,52 +559,53 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * @{ */ -#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ - ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) +#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ + ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) -#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) +#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) -#define IS_SMBUS_ADDRESSING_MODE(MODE) ((MODE) == SMBUS_ADDRESSINGMODE_7BIT) +#define IS_SMBUS_ADDRESSING_MODE(MODE) ((MODE) == SMBUS_ADDRESSINGMODE_7BIT) -#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ - ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) +#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) -#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ - ((MASK) == SMBUS_OA2_MASK01) || \ - ((MASK) == SMBUS_OA2_MASK02) || \ - ((MASK) == SMBUS_OA2_MASK03) || \ - ((MASK) == SMBUS_OA2_MASK04) || \ - ((MASK) == SMBUS_OA2_MASK05) || \ - ((MASK) == SMBUS_OA2_MASK06) || \ - ((MASK) == SMBUS_OA2_MASK07)) +#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ + ((MASK) == SMBUS_OA2_MASK01) || \ + ((MASK) == SMBUS_OA2_MASK02) || \ + ((MASK) == SMBUS_OA2_MASK03) || \ + ((MASK) == SMBUS_OA2_MASK04) || \ + ((MASK) == SMBUS_OA2_MASK05) || \ + ((MASK) == SMBUS_OA2_MASK06) || \ + ((MASK) == SMBUS_OA2_MASK07)) -#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ - ((CALL) == SMBUS_GENERALCALL_ENABLE)) +#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ + ((CALL) == SMBUS_GENERALCALL_ENABLE)) -#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ - ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) +#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ + ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) -#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ - ((PEC) == SMBUS_PEC_ENABLE)) +#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ + ((PEC) == SMBUS_PEC_ENABLE)) -#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ - ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ - ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) +#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ + ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ + ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) -#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ - ((MODE) == SMBUS_AUTOEND_MODE) || \ - ((MODE) == SMBUS_SOFTEND_MODE) || \ - ((MODE) == SMBUS_SENDPEC_MODE) || \ - ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) +#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ + ((MODE) == SMBUS_AUTOEND_MODE) || \ + ((MODE) == SMBUS_SOFTEND_MODE) || \ + ((MODE) == SMBUS_SENDPEC_MODE) || \ + ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \ + SMBUS_RELOAD_MODE ))) -#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ - ((REQUEST) == SMBUS_GENERATE_START_READ) || \ - ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ - ((REQUEST) == SMBUS_NO_STARTSTOP)) +#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ + ((REQUEST) == SMBUS_GENERATE_START_READ) || \ + ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ + ((REQUEST) == SMBUS_NO_STARTSTOP)) #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ @@ -598,26 +617,25 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) -#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ - ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) - -#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | \ - I2C_CR1_SMBDEN | \ - I2C_CR1_PECEN))) -#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | \ - I2C_CR2_HEAD10R | \ - I2C_CR2_NBYTES | \ - I2C_CR2_RELOAD | \ - I2C_CR2_RD_WRN))) - -#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ - (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ - (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & \ - (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \ +#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) + +#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ + (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \ + I2C_CR1_PECEN))) +#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ + I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ + I2C_CR2_RD_WRN))) + +#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ + (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & \ + (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \ (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) @@ -626,7 +644,7 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) -#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ +#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) #define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) @@ -636,6 +654,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t /** * @} */ + +/* Include SMBUS HAL Extended module */ #include "stm32u5xx_hal_smbus_ex.h" /* Exported functions --------------------------------------------------------*/ @@ -657,11 +677,14 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, +HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID); -HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, + pSMBUS_AddrCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ /** @@ -673,15 +696,24 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); */ /* IO operation functions *****************************************************/ +/** @addtogroup Blocking_mode_Polling Blocking mode Polling + * @{ + */ /******* Blocking mode: Polling */ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); +/** + * @} + */ +/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt + * @{ + */ /******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); @@ -719,8 +751,12 @@ void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); */ /* Peripheral State and Errors functions **************************************************/ -uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); -uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); +uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus); +uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus); + +/** + * @} + */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smbus_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smbus_ex.c index e651a0bddcc..ce0724b63a2 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smbus_ex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smbus_ex.c @@ -27,7 +27,6 @@ devices contains the following additional features (+) Disable or enable wakeup from Stop mode(s) - (+) Disable or enable Fast Mode Plus ##### How to use this driver ##### ============================================================================== @@ -68,15 +67,15 @@ * @{ */ -/** @defgroup SMBUSEx_Exported_Functions_Group2 SMBUS Extended WakeUp Mode Functions - * @brief WakeUp configuration functions +/** @defgroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions + * @brief WakeUp Mode Functions * @verbatim =============================================================================== - ##### Extended WakeUp Mode Functions ##### + ##### WakeUp Mode Functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to enable and - disable WakeUp from Stop mode(s). + [..] This section provides functions allowing to: + (+) Configure Wake Up Feature @endverbatim * @{ @@ -159,20 +158,19 @@ HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus) return HAL_BUSY; } } - /** * @} */ -/** @defgroup SMBUSEx_Exported_Functions_Group3 SMBUS Extended FastModePlus Functions - * @brief FastModePlus Configuration functions +/** @defgroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions * @verbatim =============================================================================== - ##### Extended FastModePlus Function ##### + ##### Fast Mode Plus Functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to configure - Fast Mode Plus. + [..] This section provides functions allowing to: + (+) Configure Fast Mode Plus @endverbatim * @{ @@ -231,15 +229,19 @@ HAL_StatusTypeDef HAL_SMBUSEx_ConfigFastModePlus(SMBUS_HandleTypeDef *hsmbus, ui * @} */ -/** @addtogroup SMBUSEx_Exported_Functions_Group4 SMBUS Extended Autonomous Mode Functions - * @brief SMBUS Extended Autonomous Mode Functions +/** + * @} + */ + +/** @defgroup SMBUSEx_Exported_Functions_Group4 Autonomous Mode Functions + * @brief Autonomous Mode Functions * @verbatim =============================================================================== - ##### Extended Autonomous Mode functions ##### + ##### Autonomous Mode functions ##### =============================================================================== - [..] This section provides functions allowing Set,Get and clear - Autonomous Mode configuration. + [..] This section provides functions allowing to: + (+) Configure Autonomous Mode @endverbatim * @{ @@ -254,7 +256,7 @@ HAL_StatusTypeDef HAL_SMBUSEx_ConfigFastModePlus(SMBUS_HandleTypeDef *hsmbus, ui * @retval HAL status */ HAL_StatusTypeDef HAL_SMBUSEx_SetConfigAutonomousMode(SMBUS_HandleTypeDef *hsmbus, - SMBUS_AutonomousModeConfTypeDef *sConfig) + const SMBUS_AutonomousModeConfTypeDef *sConfig) { if (hsmbus->State == HAL_SMBUS_STATE_READY) { @@ -264,16 +266,18 @@ HAL_StatusTypeDef HAL_SMBUSEx_SetConfigAutonomousMode(SMBUS_HandleTypeDef *hsmbu hsmbus->State = HAL_SMBUS_STATE_BUSY; /* Check the parameters */ + assert_param(IS_SMBUS_TRIG_INPUT_INSTANCE(hsmbus->Instance)); assert_param(IS_SMBUS_TRIG_SOURCE(hsmbus->Instance, sConfig->TriggerSelection)); - assert_param(IS_SMBUS_AUTO_MODE_TRG_POL(sConfig->TriggerPolarity)); /* Disable the selected SMBUS peripheral to be able to configure AUTOCR */ __HAL_SMBUS_DISABLE(hsmbus); /* SMBUSx AUTOCR Configuration */ - WRITE_REG(hsmbus->Instance->AUTOCR, (sConfig->TriggerState | ((sConfig->TriggerSelection) & \ - I2C_AUTOCR_TRIGSEL_Msk) | sConfig->TriggerPolarity)); + WRITE_REG(hsmbus->Instance->AUTOCR, + (sConfig->TriggerState | \ + ((sConfig->TriggerSelection) & I2C_AUTOCR_TRIGSEL_Msk) | \ + sConfig->TriggerPolarity)); /* Enable the selected SMBUS peripheral */ __HAL_SMBUS_ENABLE(hsmbus); @@ -299,11 +303,14 @@ HAL_StatusTypeDef HAL_SMBUSEx_SetConfigAutonomousMode(SMBUS_HandleTypeDef *hsmbu * the configuration information of the autonomous mode for the specified SMBUSx peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUSEx_GetConfigAutonomousMode(SMBUS_HandleTypeDef *hsmbus, \ +HAL_StatusTypeDef HAL_SMBUSEx_GetConfigAutonomousMode(const SMBUS_HandleTypeDef *hsmbus, SMBUS_AutonomousModeConfTypeDef *sConfig) { uint32_t autocr_tmp; + /* Check the parameters */ + assert_param(IS_SMBUS_TRIG_INPUT_INSTANCE(hsmbus->Instance)); + autocr_tmp = hsmbus->Instance->AUTOCR; sConfig->TriggerState = (autocr_tmp & I2C_AUTOCR_TRIGEN); @@ -335,6 +342,9 @@ HAL_StatusTypeDef HAL_SMBUSEx_ClearConfigAutonomousMode(SMBUS_HandleTypeDef *hsm hsmbus->State = HAL_SMBUS_STATE_BUSY; + /* Check the parameters */ + assert_param(IS_SMBUS_TRIG_INPUT_INSTANCE(hsmbus->Instance)); + /* Disable the selected SMBUS peripheral to be able to clear AUTOCR */ __HAL_SMBUS_DISABLE(hsmbus); @@ -355,7 +365,6 @@ HAL_StatusTypeDef HAL_SMBUSEx_ClearConfigAutonomousMode(SMBUS_HandleTypeDef *hsm return HAL_ERROR; } } - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smbus_ex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smbus_ex.h index c8ff32aa999..d479fb2211e 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smbus_ex.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_smbus_ex.h @@ -40,7 +40,7 @@ extern "C" { * @{ */ -/** @defgroup SMBUS_Autonomous_Mode_Configuration_Structure_definition SMBUS Autonomous Mode Configuration +/** @defgroup SMBUS_Autonomous_Mode_Configuration_Structure_definition Autonomous Mode Configuration Structure definition. * @brief SMBUS Autonomous Mode Configuration structure definition * @{ @@ -91,63 +91,63 @@ typedef struct /** @defgroup SMBUSEx_AutonomousMode_TriggerSelection SMBUS Extended Autonomous Mode Trigger Selection * @{ */ -#define SMBUS_TRIG_GRP1 (0x10000000U) /* Trigger Group for I2C1, I2C2 and I2C4 */ -#define SMBUS_TRIG_GRP2 (0x20000000U) /* Trigger Group for I2C3 */ - -/* HW Trigger signal is GPDMA_CH0_TRG */ -#define SMBUS_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x00000000U)) -/* HW Trigger signal is GPDMA_CH1_TRG */ -#define SMBUS_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is GPDMA_CH2_TRG */ -#define SMBUS_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is GPDMA_CH3_TRG */ -#define SMBUS_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is EXTI5_TRG */ -#define SMBUS_GRP1_EXTI5_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is EXTI9_TRG */ -#define SMBUS_GRP1_EXTI9_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is LPTIM1_CH1_TRG */ -#define SMBUS_GRP1_LPTIM1_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is LPTIM2_CH1_TRG */ -#define SMBUS_GRP1_LPTIM2_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is COMP1_TRG */ -#define SMBUS_GRP1_COMP1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is COMP2_TRG */ -#define SMBUS_GRP1_COMP2_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is RTC_ALRA_TRG */ -#define SMBUS_GRP1_RTC_ALRA_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is RTC_WUT_TRG */ -#define SMBUS_GRP1_RTC_WUT_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) - -/* HW Trigger signal is LPDMA_CH0_TRG */ -#define SMBUS_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x00000000U)) -/* HW Trigger signal is LPDMA_CH1_TRG */ -#define SMBUS_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is LPDMA_CH2_TRG */ -#define SMBUS_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is LPDMA_CH3_TRG */ -#define SMBUS_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is EXTI5_TRG */ -#define SMBUS_GRP2_EXTI5_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is EXTI8_TRG */ -#define SMBUS_GRP2_EXTI8_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is LPTIM1_CH1_TRG */ -#define SMBUS_GRP2_LPTIM1_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is LPTIM3_CH1_TRG */ -#define SMBUS_GRP2_LPTIM3_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is COMP1_TRG */ -#define SMBUS_GRP2_COMP1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is COMP2_TRG */ -#define SMBUS_GRP2_COMP2_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is RTC_ALRA_TRG */ -#define SMBUS_GRP2_RTC_ALRA_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is RTC_WUT_TRG */ -#define SMBUS_GRP2_RTC_WUT_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2, I2C4, I2C5, I2C6 (depends on Product) */ +#define SMBUS_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ + +#define SMBUS_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x00000000U)) +/*!< HW Trigger signal is GPDMA_CH0_TRG */ +#define SMBUS_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH1_TRG */ +#define SMBUS_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH2_TRG */ +#define SMBUS_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH3_TRG */ +#define SMBUS_GRP1_EXTI5_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI5_TRG */ +#define SMBUS_GRP1_EXTI9_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI9_TRG */ +#define SMBUS_GRP1_LPTIM1_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPTIM1_CH1_TRG */ +#define SMBUS_GRP1_LPTIM2_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPTIM2_CH1_TRG */ +#define SMBUS_GRP1_COMP1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP1_TRG */ +#define SMBUS_GRP1_COMP2_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP2_TRG */ +#define SMBUS_GRP1_RTC_ALRA_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_ALRA_TRG */ +#define SMBUS_GRP1_RTC_WUT_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_WUT_TRG */ + +#define SMBUS_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x00000000U)) +/*!< HW Trigger signal is LPDMA_CH0_TRG */ +#define SMBUS_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPDMA_CH1_TRG */ +#define SMBUS_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPDMA_CH2_TRG */ +#define SMBUS_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPDMA_CH3_TRG */ +#define SMBUS_GRP2_EXTI5_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI5_TRG */ +#define SMBUS_GRP2_EXTI8_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI8_TRG */ +#define SMBUS_GRP2_LPTIM1_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPTIM1_CH1_TRG */ +#define SMBUS_GRP2_LPTIM3_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPTIM3_CH1_TRG */ +#define SMBUS_GRP2_COMP1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP1_TRG */ +#define SMBUS_GRP2_COMP2_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP2_TRG */ +#define SMBUS_GRP2_RTC_ALRA_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_ALRA_TRG */ +#define SMBUS_GRP2_RTC_WUT_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_WUT_TRG */ /** * @} */ -/** @defgroup SMBUSEx_AutonomousMode_TriggerPolarity SMBUS Extended Autonomous Mode Trigger Polarity +/** @defgroup SMBUSEx_AutonomousMode_TriggerPolarity Extended Autonomous Mode Trigger Polarity * @{ */ #define SMBUS_TRIG_POLARITY_RISING (0x00000000U) /* SMBUS HW Trigger signal on rising edge */ @@ -174,7 +174,7 @@ typedef struct * @{ */ -/** @addtogroup SMBUSEx_Exported_Functions_Group2 SMBUS Extended WakeUp Mode Functions +/** @addtogroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions * @{ */ /* Peripheral Control functions ************************************************/ @@ -184,7 +184,7 @@ HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus); * @} */ -/** @addtogroup SMBUSEx_Exported_Functions_Group3 SMBUS Extended FastModePlus Functions +/** @addtogroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions * @{ */ HAL_StatusTypeDef HAL_SMBUSEx_ConfigFastModePlus(SMBUS_HandleTypeDef *hsmbus, uint32_t FastModePlus); @@ -192,12 +192,12 @@ HAL_StatusTypeDef HAL_SMBUSEx_ConfigFastModePlus(SMBUS_HandleTypeDef *hsmbus, ui * @} */ -/** @addtogroup SMBUSEx_Exported_Functions_Group4 SMBUS Extended Autonomous Mode Functions +/** @addtogroup SMBUSEx_Exported_Functions_Group4 Autonomous Mode Functions * @{ */ HAL_StatusTypeDef HAL_SMBUSEx_SetConfigAutonomousMode(SMBUS_HandleTypeDef *hsmbus, - SMBUS_AutonomousModeConfTypeDef *sConfig); -HAL_StatusTypeDef HAL_SMBUSEx_GetConfigAutonomousMode(SMBUS_HandleTypeDef *hsmbus, + const SMBUS_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_SMBUSEx_GetConfigAutonomousMode(const SMBUS_HandleTypeDef *hsmbus, SMBUS_AutonomousModeConfTypeDef *sConfig); HAL_StatusTypeDef HAL_SMBUSEx_ClearConfigAutonomousMode(SMBUS_HandleTypeDef *hsmbus); /** @@ -227,36 +227,39 @@ HAL_StatusTypeDef HAL_SMBUSEx_ClearConfigAutonomousMode(SMBUS_HandleTypeDef *hsm #define IS_SMBUS_AUTO_MODE(__MODE__) (((__MODE__) == SMBUS_AUTO_MODE_DISABLE) || \ ((__MODE__) == SMBUS_AUTO_MODE_ENABLE)) -#define IS_SMBUS_TRIG_SOURCE(__INSTANCE__, __SOURCE__) (((__INSTANCE__) == I2C3) ? \ - IS_SMBUS_GRP2_TRIG_SOURCE(__SOURCE__) : \ - IS_SMBUS_GRP1_TRIG_SOURCE(__SOURCE__)) - -#define IS_SMBUS_GRP1_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SMBUS_GRP1_GPDMA_CH0_TCF_TRG ) || \ - ((__SOURCE__) == SMBUS_GRP1_GPDMA_CH1_TCF_TRG ) || \ - ((__SOURCE__) == SMBUS_GRP1_GPDMA_CH2_TCF_TRG ) || \ - ((__SOURCE__) == SMBUS_GRP1_GPDMA_CH3_TCF_TRG ) || \ - ((__SOURCE__) == SMBUS_GRP1_EXTI5_TRG ) || \ - ((__SOURCE__) == SMBUS_GRP1_EXTI9_TRG ) || \ - ((__SOURCE__) == SMBUS_GRP1_LPTIM1_CH1_TRG ) || \ - ((__SOURCE__) == SMBUS_GRP1_LPTIM2_CH1_TRG ) || \ - ((__SOURCE__) == SMBUS_GRP1_COMP1_TRG ) || \ - ((__SOURCE__) == SMBUS_GRP1_COMP2_TRG ) || \ - ((__SOURCE__) == SMBUS_GRP1_RTC_ALRA_TRG ) || \ +#define IS_SMBUS_TRIG_SOURCE(__INSTANCE__, __SOURCE__) (((__INSTANCE__) == I2C3) ? \ + IS_SMBUS_GRP2_TRIG_SOURCE(__SOURCE__) : \ + IS_SMBUS_GRP1_TRIG_SOURCE(__SOURCE__)) + +#define IS_SMBUS_GRP1_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SMBUS_GRP1_GPDMA_CH0_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_GPDMA_CH1_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_GPDMA_CH2_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_GPDMA_CH3_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_EXTI5_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_EXTI9_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_LPTIM1_CH1_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_LPTIM2_CH1_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_COMP1_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_COMP2_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_RTC_ALRA_TRG ) || \ ((__SOURCE__) == SMBUS_GRP1_RTC_WUT_TRG )) -#define IS_SMBUS_GRP2_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SMBUS_GRP2_LPDMA_CH0_TCF_TRG ) || \ - ((__SOURCE__) == SMBUS_GRP2_LPDMA_CH1_TCF_TRG ) || \ - ((__SOURCE__) == SMBUS_GRP2_LPDMA_CH2_TCF_TRG ) || \ - ((__SOURCE__) == SMBUS_GRP2_LPDMA_CH3_TCF_TRG ) || \ - ((__SOURCE__) == SMBUS_GRP2_EXTI5_TRG ) || \ - ((__SOURCE__) == SMBUS_GRP2_EXTI8_TRG ) || \ - ((__SOURCE__) == SMBUS_GRP2_LPTIM1_CH1_TRG ) || \ - ((__SOURCE__) == SMBUS_GRP2_LPTIM3_CH1_TRG ) || \ - ((__SOURCE__) == SMBUS_GRP2_COMP1_TRG ) || \ - ((__SOURCE__) == SMBUS_GRP2_COMP2_TRG ) || \ - ((__SOURCE__) == SMBUS_GRP2_RTC_ALRA_TRG ) || \ +#define IS_SMBUS_GRP2_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SMBUS_GRP2_LPDMA_CH0_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_LPDMA_CH1_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_LPDMA_CH2_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_LPDMA_CH3_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_EXTI5_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_EXTI8_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_LPTIM1_CH1_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_LPTIM3_CH1_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_COMP1_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_COMP2_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_RTC_ALRA_TRG ) || \ ((__SOURCE__) == SMBUS_GRP2_RTC_WUT_TRG )) +#define IS_SMBUS_TRIG_INPUT_INSTANCE(__INSTANCE__) (IS_SMBUS_GRP1_INSTANCE(__INSTANCE__) || \ + IS_SMBUS_GRP2_INSTANCE(__INSTANCE__)) + #define IS_SMBUS_AUTO_MODE_TRG_POL(__POLARITY__) (((__POLARITY__) == SMBUS_TRIG_POLARITY_RISING) || \ ((__POLARITY__) == SMBUS_TRIG_POLARITY_FALLING)) /** diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_spi.c index a84c36d929c..498141290db 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_spi.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_spi.c @@ -70,6 +70,7 @@ (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback (+) ErrorCallback : SPI Error callback (+) AbortCpltCallback : SPI Abort callback + (+) SuspendCallback : SPI Suspend callback (+) MspInitCallback : SPI Msp Init callback (+) MspDeInitCallback : SPI Msp DeInit callback This function takes as parameters the HAL peripheral handle, the Callback ID @@ -89,6 +90,7 @@ (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback (+) ErrorCallback : SPI Error callback (+) AbortCpltCallback : SPI Abort callback + (+) SuspendCallback : SPI Suspend callback (+) MspInitCallback : SPI Msp Init callback (+) MspDeInitCallback : SPI Msp DeInit callback @@ -113,6 +115,10 @@ not defined, the callback registering feature is not available and weak (surcharged) callbacks are used. + SuspendCallback restriction: + SuspendCallback is called only when MasterReceiverAutoSusp is enabled and + EOT interrupt is activated. SuspendCallback is used in relation with functions + HAL_SPI_Transmit_IT, HAL_SPI_Receive_IT and HAL_SPI_TransmitReceive_IT. [..] Circular mode restriction: @@ -167,8 +173,8 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma); static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus FlagStatus, - uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(const SPI_HandleTypeDef *hspi, uint32_t Flag, + FlagStatus FlagStatus, uint32_t Timeout, uint32_t Tickstart); static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi); static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi); static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi); @@ -177,7 +183,7 @@ static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi); static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi); static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi); static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi); -static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi); +static uint32_t SPI_GetPacketSize(const SPI_HandleTypeDef *hspi); /** @@ -289,6 +295,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) assert_param(IS_SPI_RDY_MASTER_MANAGEMENT(hspi->Init.ReadyMasterManagement)); assert_param(IS_SPI_RDY_POLARITY(hspi->Init.ReadyPolarity)); + assert_param(IS_SPI_MASTER_RX_AUTOSUSP(hspi->Init.MasterReceiverAutoSusp)); /* Verify that the SPI instance supports Data Size higher than 16bits */ if ((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (hspi->Init.DataSize > SPI_DATASIZE_16BIT)) @@ -349,6 +356,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hspi->SuspendCallback = HAL_SPI_SuspendCallback; /* Legacy weak SuspendCallback */ if (hspi->MspInitCallback == NULL) { @@ -386,6 +394,16 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) SET_BIT(hspi->Instance->CR1, SPI_CR1_SSI); } + /* SPIx Master Rx Auto Suspend Configuration */ + if (((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER) && (hspi->Init.DataSize >= SPI_DATASIZE_8BIT)) + { + MODIFY_REG(hspi->Instance->CR1, SPI_CR1_MASRX, hspi->Init.MasterReceiverAutoSusp); + } + else + { + CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_MASRX); + } + /* SPIx CFG1 Configuration */ WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_length | hspi->Init.FifoThreshold | hspi->Init.DataSize)); @@ -603,6 +621,10 @@ HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Call hspi->AbortCpltCallback = pCallback; break; + case HAL_SPI_SUSPEND_CB_ID : + hspi->SuspendCallback = pCallback; + break; + case HAL_SPI_MSPINIT_CB_ID : hspi->MspInitCallback = pCallback; break; @@ -706,6 +728,10 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; + case HAL_SPI_SUSPEND_CB_ID : + hspi->SuspendCallback = HAL_SPI_SuspendCallback; /* Legacy weak SuspendCallback */ + break; + case HAL_SPI_MSPINIT_CB_ID : hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ break; @@ -804,7 +830,7 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @param Timeout: Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { #if defined (__GNUC__) __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); @@ -839,7 +865,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -855,6 +881,10 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { SPI_1LINE_TX(hspi); } + else + { + SPI_2LINES_TX(hspi); + } /* Set the number of data at current transfer */ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); @@ -877,7 +907,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Wait until TXP flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint32_t); hspi->TxXferCount--; } @@ -910,16 +940,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint32_t); hspi->TxXferCount -= (uint16_t)2UL; } else { #if defined (__GNUC__) - *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); #else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); #endif /* __GNUC__ */ hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -953,23 +983,23 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA)) { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint32_t); hspi->TxXferCount -= (uint16_t)4UL; } else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) { #if defined (__GNUC__) - *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); #else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); #endif /* __GNUC__ */ hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= (uint16_t)2UL; } else { - *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); hspi->TxXferCount--; } @@ -994,7 +1024,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint } /* Wait for Tx (and CRC) data to be sent */ - if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK) + if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } @@ -1034,13 +1064,6 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) - { - hspi->State = HAL_SPI_STATE_BUSY_RX; - /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ - return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); - } - /* Lock the process */ __HAL_LOCK(hspi); @@ -1080,6 +1103,10 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 { SPI_1LINE_RX(hspi); } + else + { + SPI_2LINES_RX(hspi); + } /* Set the number of data at current transfer */ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); @@ -1130,25 +1157,16 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Transfer loop */ while (hspi->RxXferCount > 0UL) { - /* Check the RXWNE/FRLVL flag */ - if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) { - if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL) - { - *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - hspi->RxXferCount -= (uint16_t)2UL; - } - else - { #if defined (__GNUC__) - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; #else - *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); #endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - } + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; } else { @@ -1174,31 +1192,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Transfer loop */ while (hspi->RxXferCount > 0UL) { - /* Check the RXWNE/FRLVL flag */ - if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) { - if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL) - { - *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - hspi->RxXferCount -= (uint16_t)4UL; - } - else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_RX_FIFO_1PACKET) - { -#if defined (__GNUC__) - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; -#else - *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); -#endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount -= (uint16_t)2UL; - } - else - { - *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint8_t); - hspi->RxXferCount--; - } + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; } else { @@ -1219,11 +1218,16 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } } - /* Wait for Rx (and CRC) data to be received */ - if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK) +#if (USE_SPI_CRC != 0UL) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + /* Wait for crc data to be received */ + if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } } +#endif /* USE_SPI_CRC */ /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); @@ -1250,10 +1254,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 * @param Timeout: Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) { - HAL_SPI_StateTypeDef tmp_state; HAL_StatusTypeDef errorcode = HAL_OK; #if defined (__GNUC__) __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); @@ -1261,7 +1264,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD #endif /* __GNUC__ */ uint32_t tickstart; - uint32_t tmp_mode; uint16_t initial_TxXferCount; uint16_t initial_RxXferCount; @@ -1276,13 +1278,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD initial_TxXferCount = Size; initial_RxXferCount = Size; - tmp_state = hspi->State; - tmp_mode = hspi->Init.Mode; - if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && \ - (hspi->Init.Direction == SPI_DIRECTION_2LINES) && \ - (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + if (hspi->State != HAL_SPI_STATE_READY) { errorcode = HAL_BUSY; __HAL_UNLOCK(hspi); @@ -1296,18 +1293,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD return errorcode; } - /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ - if (hspi->State != HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } - /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->pRxBuffPtr = (uint8_t *)pRxData; hspi->RxXferCount = Size; hspi->RxXferSize = Size; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferCount = Size; hspi->TxXferSize = Size; @@ -1315,6 +1307,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->RxISR = NULL; hspi->TxISR = NULL; + /* Set Full-Duplex mode */ + SPI_2LINES(hspi); + /* Set the number of data at current transfer */ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); @@ -1334,7 +1329,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Check TXP flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL)) { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint32_t); hspi->TxXferCount --; initial_TxXferCount = hspi->TxXferCount; @@ -1369,50 +1364,30 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) { - /* Check TXP flag */ + /* Check the TXP flag */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP) && (initial_TxXferCount > 0UL)) { - if ((initial_TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) - { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint32_t); - hspi->TxXferCount -= (uint16_t)2UL; - initial_TxXferCount = hspi->TxXferCount; - } - else - { #if defined (__GNUC__) - *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); #else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); #endif /* __GNUC__ */ - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; - initial_TxXferCount = hspi->TxXferCount; - } + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + initial_TxXferCount = hspi->TxXferCount; } - /* Check RXWNE/FRLVL flag */ - if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) && (initial_RxXferCount > 0UL)) + /* Check the RXP flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL)) { - if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL) - { - *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - hspi->RxXferCount -= (uint16_t)2UL; - initial_RxXferCount = hspi->RxXferCount; - } - else - { #if defined (__GNUC__) - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; #else - *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); #endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - initial_RxXferCount = hspi->RxXferCount; - } + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; } /* Timeout management */ @@ -1435,64 +1410,22 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) { - /* check TXP flag */ + /* Check the TXP flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL)) { - if ((initial_TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA)) - { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint32_t); - hspi->TxXferCount -= (uint16_t)4UL; - initial_TxXferCount = hspi->TxXferCount; - } - else if ((initial_TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) - { -#if defined (__GNUC__) - *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); -#else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); -#endif /* __GNUC__ */ - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= (uint16_t)2UL; - initial_TxXferCount = hspi->TxXferCount; - } - else - { - *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint8_t); - hspi->TxXferCount--; - initial_TxXferCount = hspi->TxXferCount; - } + *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + initial_TxXferCount = hspi->TxXferCount; } - /* Wait until RXWNE/FRLVL flag is reset */ - if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) && (initial_RxXferCount > 0UL)) + /* Check the RXP flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL)) { - if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL) - { - *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - hspi->RxXferCount -= (uint16_t)4UL; - initial_RxXferCount = hspi->RxXferCount; - } - else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_RX_FIFO_1PACKET) - { -#if defined (__GNUC__) - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; -#else - *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); -#endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount -= (uint16_t)2UL; - initial_RxXferCount = hspi->RxXferCount; - } - else - { - *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint8_t); - hspi->RxXferCount--; - initial_RxXferCount = hspi->RxXferCount; - } + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; } /* Timeout management */ @@ -1512,7 +1445,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } /* Wait for Tx/Rx (and CRC) data to be sent/received */ - if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK) + if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } @@ -1540,7 +1473,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD * @param Size : amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; @@ -1567,7 +1500,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1596,6 +1529,10 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u { SPI_1LINE_TX(hspi); } + else + { + SPI_2LINES_TX(hspi); + } /* Set the number of data at current transfer */ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); @@ -1631,13 +1568,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) - { - hspi->State = HAL_SPI_STATE_BUSY_RX; - /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ - return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); - } - /* Lock the process */ __HAL_LOCK(hspi); @@ -1687,6 +1617,10 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui { SPI_1LINE_RX(hspi); } + else + { + SPI_2LINES_RX(hspi); + } /* Note : The SPI must be enabled after unlocking current process to avoid the risk of SPI interrupt handle execution before current @@ -1721,33 +1655,23 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui * @param Size : amount of data to be sent and received * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { - HAL_SPI_StateTypeDef tmp_state; HAL_StatusTypeDef errorcode = HAL_OK; - uint32_t max_fifo_length = 0UL; uint32_t tmp_TxXferCount; #if defined (__GNUC__) __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); #endif /* __GNUC__ */ - uint32_t tmp_mode; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); /* Lock the process */ __HAL_LOCK(hspi); - /* Init temporary variables */ - tmp_state = hspi->State; - tmp_mode = hspi->Init.Mode; - - if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && \ - (hspi->Init.Direction == SPI_DIRECTION_2LINES) && \ - (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + if (hspi->State != HAL_SPI_STATE_READY) { errorcode = HAL_BUSY; __HAL_UNLOCK(hspi); @@ -1761,15 +1685,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p return errorcode; } - /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ - if (hspi->State != HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } - /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -1794,6 +1713,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p hspi->TxISR = SPI_TxISR_8BIT; } + /* Set Full-Duplex mode */ + SPI_2LINES(hspi); + /* Set the number of data at current transfer */ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); @@ -1801,77 +1723,35 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p __HAL_SPI_ENABLE(hspi); /* Fill in the TxFIFO */ - while ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (tmp_TxXferCount != 0UL) && (max_fifo_length < MAX_FIFO_LENGTH)) + while ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (tmp_TxXferCount != 0UL)) { - if (max_fifo_length < MAX_FIFO_LENGTH) + /* Transmit data in 32 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; + } + /* Transmit data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* Transmit data in 32 Bit mode */ - if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) - { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint32_t); - hspi->TxXferCount--; - tmp_TxXferCount = hspi->TxXferCount; - } - /* Transmit data in 16 Bit mode */ - else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) - { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint32_t); - hspi->TxXferCount -= (uint16_t)2UL; - tmp_TxXferCount = hspi->TxXferCount; - } - else - { -#if defined (__GNUC__) - *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); -#else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); -#endif /* __GNUC__ */ - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; - tmp_TxXferCount = hspi->TxXferCount; - } - } - /* Transmit data in 8 Bit mode */ - else - { - if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA)) - { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint32_t); - hspi->TxXferCount -= (uint16_t)4UL; - tmp_TxXferCount = hspi->TxXferCount; - } - else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) - { #if defined (__GNUC__) - *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); #else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); #endif /* __GNUC__ */ - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= (uint16_t)2UL; - tmp_TxXferCount = hspi->TxXferCount; - } - else - { - *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint8_t); - hspi->TxXferCount--; - tmp_TxXferCount = hspi->TxXferCount; - } - } - - max_fifo_length++; + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; } + /* Transmit data in 8 Bit mode */ else { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; } } @@ -1900,7 +1780,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p * @param Size : amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode; @@ -1927,7 +1807,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1943,6 +1823,10 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, { SPI_1LINE_TX(hspi); } + else + { + SPI_2LINES_TX(hspi); + } /* Packing mode management is enabled by the DMA settings */ if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmatx->Init.SrcDataWidth != DMA_SRC_DATAWIDTH_WORD) && \ @@ -2102,13 +1986,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) - { - hspi->State = HAL_SPI_STATE_BUSY_RX; - /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ - return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); - } - /* Lock the process */ __HAL_LOCK(hspi); @@ -2144,6 +2021,10 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u { SPI_1LINE_RX(hspi); } + else + { + SPI_2LINES_RX(hspi); + } /* Packing mode management is enabled by the DMA settings */ if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) && \ @@ -2297,28 +2178,18 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u * @note When the CRC feature is enabled the pRxData Length must be Size + 1 * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { - HAL_SPI_StateTypeDef tmp_state; HAL_StatusTypeDef errorcode; - uint32_t tmp_mode; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); /* Lock the process */ __HAL_LOCK(hspi); - /* Init temporary variables */ - tmp_state = hspi->State; - tmp_mode = hspi->Init.Mode; - - if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && \ - (hspi->Init.Direction == SPI_DIRECTION_2LINES) && \ - (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + if (hspi->State != HAL_SPI_STATE_READY) { errorcode = HAL_BUSY; __HAL_UNLOCK(hspi); @@ -2332,15 +2203,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * return errorcode; } - /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ - if (hspi->State != HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } - /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -2351,6 +2217,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * hspi->RxISR = NULL; hspi->TxISR = NULL; + /* Set Full-Duplex mode */ + SPI_2LINES(hspi); + /* Reset the Tx/Rx DMA bits */ CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); @@ -2402,19 +2271,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Adjustment done */ } - /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ - if (hspi->State == HAL_SPI_STATE_BUSY_RX) - { - /* Set the SPI Rx DMA Half transfer complete callback */ - hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; - hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; - } - else - { - /* Set the SPI Tx/Rx DMA Half transfer complete callback */ - hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; - hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; - } + /* Set the SPI Tx/Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; /* Set the DMA error callback */ hspi->hdmarx->XferErrorCallback = SPI_DMAError; @@ -2490,9 +2349,11 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * is performed in DMA reception complete callback */ hspi->hdmatx->XferHalfCpltCallback = NULL; hspi->hdmatx->XferCpltCallback = NULL; - hspi->hdmatx->XferErrorCallback = NULL; hspi->hdmatx->XferAbortCallback = NULL; + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) { hspi->TxXferCount = Size; @@ -2616,6 +2477,20 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) /* If master communication on going, make sure current frame is done before closing the connection */ if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) { + /* Disable EOT interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); + + /* Request a Suspend transfer */ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP); do { @@ -2625,7 +2500,21 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } - } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); + } + while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); + + /* Clear SUSP flag */ + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); } /* Disable the SPI DMA Tx request if enabled */ @@ -2670,7 +2559,7 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) SPI_AbortTransfer(hspi); /* Check error during Abort procedure */ - if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) + if (HAL_IS_BIT_SET(hspi->ErrorCode, HAL_SPI_ERROR_ABORT)) { /* return HAL_Error in case of error during Abort procedure */ errorcode = HAL_ERROR; @@ -2722,6 +2611,20 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) /* If master communication on going, make sure current frame is done before closing the connection */ if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) { + /* Disable EOT interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); + + /* Request a Suspend transfer */ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP); do { @@ -2731,7 +2634,21 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } - } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); + } + while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); + + /* Clear SUSP flag */ + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); } /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized @@ -2794,7 +2711,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) SPI_AbortTransfer(hspi); /* Check error during Abort procedure */ - if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) + if (HAL_IS_BIT_SET(hspi->ErrorCode, HAL_SPI_ERROR_ABORT)) { /* return HAL_Error in case of error during Abort procedure */ errorcode = HAL_ERROR; @@ -2883,6 +2800,20 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); #endif /* __GNUC__ */ + /* SPI in SUSPEND mode ----------------------------------------------------*/ + if (HAL_IS_BIT_SET(itflag, SPI_FLAG_SUSP) && HAL_IS_BIT_SET(itsource, SPI_FLAG_EOT)) + { + /* Clear the Suspend flag */ + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + + /* Suspend on going, Call the Suspend callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->SuspendCallback(hspi); +#else + HAL_SPI_SuspendCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } /* SPI in mode Transmitter and Receiver ------------------------------------*/ if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && \ @@ -2926,57 +2857,51 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) /* Disable EOT interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); - /* DMA Normal Mode */ - if (HAL_IS_BIT_CLR(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN) || - ((State != HAL_SPI_STATE_BUSY_RX) && (hspi->hdmarx->Mode != DMA_LINKEDLIST_CIRCULAR)) || - ((State != HAL_SPI_STATE_BUSY_TX) && (hspi->hdmatx->Mode != DMA_LINKEDLIST_CIRCULAR))) + /* For the IT based receive extra polling maybe required for last packet */ + if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN)) { - /* For the IT based receive extra polling maybe required for last packet */ - if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN)) + /* Pooling remaining data */ + while (hspi->RxXferCount != 0UL) { - /* Pooling remaining data */ - while (hspi->RxXferCount != 0UL) + /* Receive data in 32 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + } + /* Receive data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* Receive data in 32 Bit mode */ - if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) - { - *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - } - /* Receive data in 16 Bit mode */ - else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { #if defined (__GNUC__) - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; #else - *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); #endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - } - /* Receive data in 8 Bit mode */ - else - { - *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint8_t); - } - - hspi->RxXferCount--; + hspi->pRxBuffPtr += sizeof(uint16_t); } + /* Receive data in 8 Bit mode */ + else + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + } + + hspi->RxXferCount--; } + } - /* Call SPI Standard close procedure */ - SPI_CloseTransfer(hspi); + /* Call SPI Standard close procedure */ + SPI_CloseTransfer(hspi); - hspi->State = HAL_SPI_STATE_READY; - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { + hspi->State = HAL_SPI_STATE_READY; + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) - hspi->ErrorCallback(hspi); + hspi->ErrorCallback(hspi); #else - HAL_SPI_ErrorCallback(hspi); + HAL_SPI_ErrorCallback(hspi); #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - return; - } + return; } #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) @@ -3016,14 +2941,6 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) return; } - if (HAL_IS_BIT_SET(itflag, SPI_FLAG_SUSP) && HAL_IS_BIT_SET(itsource, SPI_FLAG_EOT)) - { - /* Abort on going, clear SUSP flag to avoid infinite looping */ - __HAL_SPI_CLEAR_SUSPFLAG(hspi); - - return; - } - /* SPI in Error Treatment --------------------------------------------------*/ if ((trigger & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE | SPI_FLAG_UDR)) != 0UL) { @@ -3116,7 +3033,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval None */ -__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) +__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); @@ -3132,7 +3049,7 @@ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval None */ -__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) +__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); @@ -3148,7 +3065,7 @@ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval None */ -__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) +__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); @@ -3164,7 +3081,7 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval None */ -__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) +__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); @@ -3180,7 +3097,7 @@ __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval None */ -__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) +__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); @@ -3196,7 +3113,7 @@ __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval None */ -__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) +__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); @@ -3212,7 +3129,7 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval None */ -__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) +__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); @@ -3230,7 +3147,7 @@ __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) * @param hspi SPI handle. * @retval None */ -__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) +__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); @@ -3240,6 +3157,21 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) */ } +/** + * @brief SPI Suspend callback. + * @param hspi SPI handle. + * @retval None + */ +__weak void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_SuspendCallback can be implemented in the user file. + */ +} + /** * @} */ @@ -3265,7 +3197,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI state */ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi) { /* Return SPI handle state */ return hspi->State; @@ -3277,7 +3209,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI error code in bitmap format */ -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) { /* Return SPI ErrorCode */ return hspi->ErrorCode; @@ -3387,9 +3319,9 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) * the configuration information for the specified DMA module. * @retval None */ -static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) hspi->TxHalfCpltCallback(hspi); @@ -3404,9 +3336,9 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) * the configuration information for the specified DMA module. * @retval None */ -static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) hspi->RxHalfCpltCallback(hspi); @@ -3421,9 +3353,9 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) * the configuration information for the specified DMA module. * @retval None */ -static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) hspi->TxRxHalfCpltCallback(hspi); @@ -3635,7 +3567,7 @@ static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi) static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi) { /* Transmit data in 8 Bit mode */ - *(__IO uint8_t *)&hspi->Instance->TXDR = *((uint8_t *)hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->TXDR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); hspi->TxXferCount--; @@ -3659,9 +3591,9 @@ static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi) #if defined (__GNUC__) __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); - *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); #else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); #endif /* __GNUC__ */ hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -3683,7 +3615,7 @@ static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi) static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi) { /* Transmit data in 32 Bit mode */ - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint32_t); hspi->TxXferCount--; @@ -3817,8 +3749,8 @@ static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi) * @param Tickstart: Tick start value * @retval HAL status */ -static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, - uint32_t Tickstart, uint32_t Timeout) +static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(const SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) { /* Wait until flag is set */ while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) == Status) @@ -3838,7 +3770,7 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin * the configuration information for SPI module. * @retval Packet size occupied in the fifo */ -static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi) +static uint32_t SPI_GetPacketSize(const SPI_HandleTypeDef *hspi) { uint32_t fifo_threashold = (hspi->Init.FifoThreshold >> SPI_CFG1_FTHLV_Pos) + 1UL; uint32_t data_size = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) + 1UL; diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_spi.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_spi.h index 2217e55bb4c..bbc186528d2 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_spi.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_spi.h @@ -161,7 +161,7 @@ typedef struct __SPI_HandleTypeDef SPI_InitTypeDef Init; /*!< SPI communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ uint16_t TxXferSize; /*!< SPI Tx Transfer size */ @@ -199,6 +199,7 @@ typedef struct __SPI_HandleTypeDef void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ + void (* SuspendCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Suspend callback */ void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ @@ -219,8 +220,9 @@ typedef enum HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /*!< SPI TxRx Half Completed callback ID */ HAL_SPI_ERROR_CB_ID = 0x06UL, /*!< SPI Error callback ID */ HAL_SPI_ABORT_CB_ID = 0x07UL, /*!< SPI Abort callback ID */ - HAL_SPI_MSPINIT_CB_ID = 0x08UL, /*!< SPI Msp Init callback ID */ - HAL_SPI_MSPDEINIT_CB_ID = 0x09UL /*!< SPI Msp DeInit callback ID */ + HAL_SPI_SUSPEND_CB_ID = 0x08UL, /*!< SPI Suspend callback ID */ + HAL_SPI_MSPINIT_CB_ID = 0x09UL, /*!< SPI Msp Init callback ID */ + HAL_SPI_MSPDEINIT_CB_ID = 0x0AUL /*!< SPI Msp DeInit callback ID */ } HAL_SPI_CallbackIDTypeDef; @@ -839,18 +841,18 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @{ */ /* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); @@ -871,6 +873,7 @@ void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi); /** * @} */ @@ -880,8 +883,8 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); */ /* Peripheral State and Error functions ***************************************/ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); /** * @} */ @@ -895,19 +898,40 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); * @{ */ -/** @brief Set the SPI transmit-only mode. +/** @brief Set the SPI transmit-only mode in 1Line configuration. * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_HDDIR) +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) -/** @brief Set the SPI receive-only mode. +/** @brief Set the SPI receive-only mode in 1Line configuration. * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 ,SPI_CR1_HDDIR) +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) + +/** @brief Set the SPI transmit-only mode in 2Lines configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_2LINES_TX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_0) + +/** @brief Set the SPI receive-only mode in 2Lines configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_2LINES_RX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_1) + +/** @brief Set the SPI Transmit-Receive mode in 2Lines configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_2LINES(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, 0x00000000UL) #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ ((MODE) == SPI_MODE_MASTER)) @@ -1006,13 +1030,14 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \ ((NSSP) == SPI_NSS_PULSE_DISABLE)) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_BYPASS) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ @@ -1077,6 +1102,9 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); #define IS_SPI_RDY_POLARITY(POLARITY) (((POLARITY) == SPI_RDY_POLARITY_HIGH) || \ ((POLARITY) == SPI_RDY_POLARITY_LOW)) + +#define IS_SPI_MASTER_RX_AUTOSUSP(MODE) (((MODE) == SPI_MASTER_RX_AUTOSUSP_DISABLE) || \ + ((MODE) == SPI_MASTER_RX_AUTOSUSP_ENABLE)) /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_spi_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_spi_ex.c index 0c1ab23847b..e46eb950223 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_spi_ex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_spi_ex.c @@ -72,7 +72,7 @@ * the configuration information for the specified SPI module. * @retval HAL status */ -HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi) +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi) { uint8_t count = 0; uint32_t itflag = hspi->Instance->SR; @@ -217,7 +217,8 @@ HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t * the configuration information of the autonomous mode for the specified SPIx peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_SPIEx_SetConfigAutonomousMode(SPI_HandleTypeDef *hspi, SPI_AutonomousModeConfTypeDef *sConfig) +HAL_StatusTypeDef HAL_SPIEx_SetConfigAutonomousMode(SPI_HandleTypeDef *hspi, + const SPI_AutonomousModeConfTypeDef *sConfig) { if (hspi->State == HAL_SPI_STATE_READY) { @@ -227,8 +228,8 @@ HAL_StatusTypeDef HAL_SPIEx_SetConfigAutonomousMode(SPI_HandleTypeDef *hspi, SPI hspi->State = HAL_SPI_STATE_BUSY; /* Check the parameters */ + assert_param(IS_SPI_AUTONOMOUS_INSTANCE(hspi->Instance)); assert_param(IS_SPI_TRIG_SOURCE(hspi->Instance, sConfig->TriggerSelection)); - assert_param(IS_SPI_AUTO_MODE_TRG_POL(sConfig->TriggerPolarity)); /* Disable the selected SPI peripheral to be able to configure AUTOCR */ @@ -259,13 +260,18 @@ HAL_StatusTypeDef HAL_SPIEx_SetConfigAutonomousMode(SPI_HandleTypeDef *hspi, SPI * the configuration information of the autonomous mode for the specified SPIx peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_SPIEx_GetConfigAutonomousMode(SPI_HandleTypeDef *hspi, SPI_AutonomousModeConfTypeDef *sConfig) +HAL_StatusTypeDef HAL_SPIEx_GetConfigAutonomousMode(const SPI_HandleTypeDef *hspi, + SPI_AutonomousModeConfTypeDef *sConfig) { uint32_t autocr_tmp; + /* Check the parameters */ + assert_param(IS_SPI_AUTONOMOUS_INSTANCE(hspi->Instance)); + autocr_tmp = hspi->Instance->AUTOCR; sConfig->TriggerState = (autocr_tmp & SPI_AUTOCR_TRIGEN); +#if defined(SPI_TRIG_GRP2) if (IS_SPI_GRP2_INSTANCE(hspi->Instance)) { sConfig->TriggerSelection = ((autocr_tmp & SPI_AUTOCR_TRIGSEL) | SPI_TRIG_GRP2); @@ -274,6 +280,9 @@ HAL_StatusTypeDef HAL_SPIEx_GetConfigAutonomousMode(SPI_HandleTypeDef *hspi, SPI { sConfig->TriggerSelection = ((autocr_tmp & SPI_AUTOCR_TRIGSEL) | SPI_TRIG_GRP1); } +#else + sConfig->TriggerSelection = ((autocr_tmp & SPI_AUTOCR_TRIGSEL) | SPI_TRIG_GRP1); +#endif /* SPI_TRIG_GRP2 */ sConfig->TriggerPolarity = (autocr_tmp & SPI_AUTOCR_TRIGPOL); return HAL_OK; @@ -294,6 +303,9 @@ HAL_StatusTypeDef HAL_SPIEx_ClearConfigAutonomousMode(SPI_HandleTypeDef *hspi) hspi->State = HAL_SPI_STATE_BUSY; + /* Check the parameters */ + assert_param(IS_SPI_AUTONOMOUS_INSTANCE(hspi->Instance)); + /* Disable the selected SPI peripheral to be able to clear AUTOCR */ __HAL_SPI_DISABLE(hspi); diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_spi_ex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_spi_ex.h index c9830aa3a1e..b6fea7baf19 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_spi_ex.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_spi_ex.h @@ -79,7 +79,9 @@ typedef struct * @{ */ #define SPI_TRIG_GRP1 (0x10000000U) /* Trigger Group for SPI1 and SPI2 */ +#if defined(SPI3) #define SPI_TRIG_GRP2 (0x20000000U) /* Trigger Group for SPI3 */ +#endif /* GRP2_AVAILABILITY */ /* HW Trigger signal is GPDMA_CH0_TRG */ #define SPI_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x00000000U)) @@ -106,6 +108,7 @@ typedef struct /* HW Trigger signal is RTC_WUT_TRG */ #define SPI_GRP1_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP1 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos)) +#if defined(SPI3) /* HW Trigger signal is LPDMA_CH0_TRG */ #define SPI_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x00000000U)) /* HW Trigger signal is LPDMA_CH1_TRG */ @@ -130,6 +133,7 @@ typedef struct #define SPI_GRP2_RTC_ALRA_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is RTC_WUT_TRG */ #define SPI_GRP2_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos)) +#endif /* GRP2_AVAILABILITY */ /** * @} */ @@ -155,14 +159,18 @@ typedef struct #define IS_SPI_AUTO_MODE(__MODE__) (((__MODE__) == SPI_AUTO_MODE_DISABLE) || \ ((__MODE__) == SPI_AUTO_MODE_ENABLE)) -#define IS_SPI_TRIG_SOURCE(__INSTANCE__, __SOURCE__) (((__INSTANCE__) == SPI3) ? \ - IS_SPI_GRP2_TRIG_SOURCE(__SOURCE__) : \ - IS_SPI_GRP1_TRIG_SOURCE(__SOURCE__)) +#if defined(SPI_TRIG_GRP2) +#define IS_SPI_AUTONOMOUS_INSTANCE(__INSTANCE__) (IS_SPI_GRP1_INSTANCE(__INSTANCE__) || \ + IS_SPI_GRP2_INSTANCE(__INSTANCE__)) +#else +#define IS_SPI_AUTONOMOUS_INSTANCE(__INSTANCE__) IS_SPI_GRP1_INSTANCE(__INSTANCE__) +#endif /* SPI_TRIG_GRP2 */ -#define IS_SPI_GRP1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) ||\ - ((__INSTANCE__) == SPI2)) - -#define IS_SPI_GRP2_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPI3) +#if defined(SPI_TRIG_GRP2) +#define IS_SPI_TRIG_SOURCE(__INSTANCE__, __SOURCE__) ((IS_SPI_GRP2_INSTANCE(__INSTANCE__)) ? \ + IS_SPI_GRP2_TRIG_SOURCE(__SOURCE__) : \ + IS_SPI_GRP1_TRIG_SOURCE(__SOURCE__)) +#endif /* SPI_TRIG_GRP2 */ #define IS_SPI_GRP1_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SPI_GRP1_GPDMA_CH0_TCF_TRG ) || \ ((__SOURCE__) == SPI_GRP1_GPDMA_CH1_TCF_TRG ) || \ @@ -207,7 +215,7 @@ typedef struct /** @addtogroup SPIEx_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour); @@ -218,8 +226,10 @@ HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t /** @addtogroup SPI_Autonomous_Mode_Functions Autonomous Mode Functions * @{ */ -HAL_StatusTypeDef HAL_SPIEx_SetConfigAutonomousMode(SPI_HandleTypeDef *hspi, SPI_AutonomousModeConfTypeDef *sConfig); -HAL_StatusTypeDef HAL_SPIEx_GetConfigAutonomousMode(SPI_HandleTypeDef *hspi, SPI_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_SPIEx_SetConfigAutonomousMode(SPI_HandleTypeDef *hspi, + const SPI_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_SPIEx_GetConfigAutonomousMode(const SPI_HandleTypeDef *hspi, + SPI_AutonomousModeConfTypeDef *sConfig); HAL_StatusTypeDef HAL_SPIEx_ClearConfigAutonomousMode(SPI_HandleTypeDef *hspi); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sram.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sram.c index 1d340c94880..70302c004df 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sram.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sram.c @@ -75,25 +75,25 @@ The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_SRAM_RegisterCallback() to register a user callback, + Use Functions HAL_SRAM_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) MspInitCallback : SRAM MspInit. (+) MspDeInitCallback : SRAM MspDeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_SRAM_UnRegisterCallback() to reset a callback to the default + Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) MspInitCallback : SRAM MspInit. (+) MspDeInitCallback : SRAM MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET + By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_SRAM_Init - and @ref HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_SRAM_Init and @ref HAL_SRAM_DeInit + reset to the legacy weak (surcharged) functions in the HAL_SRAM_Init + and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -101,8 +101,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_SRAM_RegisterCallback before calling @ref HAL_SRAM_DeInit - or @ref HAL_SRAM_Init function. + using HAL_SRAM_RegisterCallback before calling HAL_SRAM_DeInit + or HAL_SRAM_Init function. When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -132,9 +132,15 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +/** @addtogroup SRAM_Private_Functions SRAM Private Functions + * @{ + */ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma); static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma); static void SRAM_DMAError(DMA_HandleTypeDef *hdma); +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ @@ -1141,7 +1147,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) * the configuration information for SRAM module. * @retval HAL state */ -HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) +HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram) { return hsram->State; } @@ -1154,6 +1160,10 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) * @} */ +/** @addtogroup SRAM_Private_Functions SRAM Private Functions + * @{ + */ + /** * @brief DMA SRAM process complete callback. * @param hdma : DMA handle @@ -1220,6 +1230,10 @@ static void SRAM_DMAError(DMA_HandleTypeDef *hdma) #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } +/** + * @} + */ + /** * @} */ @@ -1230,4 +1244,3 @@ static void SRAM_DMAError(DMA_HandleTypeDef *hdma) * @} */ - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sram.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sram.h index 9ffc6f09fb3..ac2f7fdb94e 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sram.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_sram.h @@ -204,7 +204,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); */ /* SRAM State functions ******************************************************/ -HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); +HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram); /** * @} @@ -228,4 +228,3 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); #endif #endif /* STM32U5xx_HAL_SRAM_H */ - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tim.c index d2b540a821a..7288f8cc140 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tim.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tim.c @@ -217,11 +217,11 @@ all interrupt callbacks are set to the corresponding weak functions: /** @addtogroup TIM_Private_Functions * @{ */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); @@ -237,7 +237,7 @@ static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig); + const TIM_SlaveConfigTypeDef *sSlaveConfig); /** * @} */ @@ -290,6 +290,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -537,7 +538,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) * @param Length The length of data to be transferred from memory to peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; @@ -551,7 +552,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat } else if (htim->State == HAL_TIM_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -673,6 +674,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -1062,7 +1064,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -1077,7 +1080,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -1340,6 +1343,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -1729,7 +1733,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -1744,7 +1749,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -2006,6 +2011,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -2399,7 +2405,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -2417,20 +2423,6 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - switch (Channel) { case TIM_CHANNEL_1: @@ -2522,6 +2514,20 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel break; } + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + /* Return function status */ return status; } @@ -2655,6 +2661,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -3032,7 +3039,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) { uint32_t tmpsmcr; uint32_t tmpccmr1; @@ -3058,6 +3065,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); if (htim->State == HAL_TIM_STATE_RESET) { @@ -3567,7 +3575,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData1 == NULL) && (Length > 0U)) + if ((pData1 == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -3592,7 +3600,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData2 == NULL) && (Length > 0U)) + if ((pData2 == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -3621,7 +3629,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U)) { return HAL_ERROR; } @@ -3660,11 +3668,12 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); break; } @@ -3686,11 +3695,12 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); break; } @@ -3725,17 +3735,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Return error status */ return HAL_ERROR; } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + break; } } @@ -4114,7 +4126,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef *sConfig, + const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; @@ -4212,7 +4224,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; @@ -4314,7 +4326,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef *sConfig, + const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; @@ -4619,12 +4631,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength) { HAL_StatusTypeDef status = HAL_OK; uint32_t BlockDataLength = 0; uint32_t data_width; - DMA_HandleTypeDef *hdma = NULL; + const DMA_HandleTypeDef *hdma = NULL; assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -4704,12 +4716,12 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t status = HAL_ERROR; break; } - } - if (status == HAL_OK) - { - status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - BlockDataLength); + if (status == HAL_OK) + { + status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + BlockDataLength); + } } @@ -4765,7 +4777,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; @@ -5079,7 +5091,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B HAL_StatusTypeDef status = HAL_OK; uint32_t BlockDataLength = 0; uint32_t data_width; - DMA_HandleTypeDef *hdma = NULL; + const DMA_HandleTypeDef *hdma = NULL; assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -5160,12 +5172,12 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B status = HAL_ERROR; break; } - } - if (status == HAL_OK) - { - status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - BlockDataLength); + if (status == HAL_OK) + { + status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + BlockDataLength); + } } return status; @@ -5542,7 +5554,7 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, - TIM_ClearInputConfigTypeDef *sClearInputConfig, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; @@ -5571,7 +5583,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, /* Clear the OCREF clear selection bit */ CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); - /* Clear TIM1_AF2_OCRSEL (reset value) */ + /* Clear TIMx_AF2_OCRSEL (reset value) */ MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL, sClearInputConfig->ClearInputSource); break; } @@ -5716,7 +5728,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, * contains the clock source information for the TIM peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -5908,7 +5920,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset). * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); @@ -5949,7 +5961,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig) + const TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); @@ -5991,7 +6003,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval Captured value */ -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpreg = 0U; @@ -6312,8 +6324,6 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call { return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(htim); if (htim->State == HAL_TIM_STATE_READY) { @@ -6525,9 +6535,6 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(htim); - return status; } @@ -6575,9 +6582,6 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(htim); - if (htim->State == HAL_TIM_STATE_READY) { switch (CallbackID) @@ -6834,9 +6838,6 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(htim); - return status; } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ @@ -6865,7 +6866,7 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca * @param htim TIM Base handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6875,7 +6876,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) * @param htim TIM Output Compare handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6885,7 +6886,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) * @param htim TIM handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6895,7 +6896,7 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) * @param htim TIM IC handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6905,7 +6906,7 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) * @param htim TIM OPM handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6915,7 +6916,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) * @param htim TIM Encoder Interface handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6925,7 +6926,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) * @param htim TIM handle * @retval Active channel */ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) { return htim->Channel; } @@ -6943,7 +6944,7 @@ HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_6: TIM Channel 6 * @retval TIM Channel state */ -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_TIM_ChannelStateTypeDef channel_state; @@ -6960,7 +6961,7 @@ HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, ui * @param htim TIM handle * @retval DMA burst state */ -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); @@ -7249,7 +7250,7 @@ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) * @param Structure TIM Base configuration structure * @retval None */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { uint32_t tmpcr1; tmpcr1 = TIMx->CR1; @@ -7297,17 +7298,18 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) * @param OC_Config The output configuration structure * @retval None */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7372,17 +7374,18 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @param OC_Config The output configuration structure * @retval None */ -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7448,17 +7451,18 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @param OC_Config The output configuration structure * @retval None */ -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7522,17 +7526,18 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @param OC_Config The output configuration structure * @retval None */ -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -7600,17 +7605,18 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, - TIM_OC_InitTypeDef *OC_Config) + const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ @@ -7653,17 +7659,18 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, - TIM_OC_InitTypeDef *OC_Config) + const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ @@ -7707,7 +7714,7 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, * @retval None */ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig) + const TIM_SlaveConfigTypeDef *sSlaveConfig) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -7854,9 +7861,9 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC1E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Select the Input */ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) @@ -7944,9 +7951,9 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; @@ -7983,9 +7990,9 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; @@ -8027,9 +8034,9 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccer; /* Disable the Channel 3: Reset the CC3E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC3E; tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC3S; @@ -8075,9 +8082,9 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccer; /* Disable the Channel 4: Reset the CC4E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC4E; tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S; @@ -8105,16 +8112,16 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @arg TIM_TS_ITR1: Internal Trigger 1 * @arg TIM_TS_ITR2: Internal Trigger 2 * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input * @arg TIM_TS_ITR4: Internal Trigger 4 * @arg TIM_TS_ITR5: Internal Trigger 5 * @arg TIM_TS_ITR6: Internal Trigger 6 * @arg TIM_TS_ITR7: Internal Trigger 7 * @arg TIM_TS_ITR8: Internal Trigger 8 * @arg TIM_TS_ITR11: Internal Trigger 11 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tim.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tim.h index 0c457b2b02a..f920a6cd40b 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tim.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tim.h @@ -770,6 +770,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +/** @defgroup TIM_CC_DMA_Request CCx DMA request selection + * @{ + */ +#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ +#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + /** @defgroup TIM_Flag_definition TIM Flag Definition * @{ */ @@ -814,16 +823,16 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_Clock_Source TIM Clock Source * @{ */ -#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ -#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ -#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ -#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ -#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ #define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */ #define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */ #define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */ @@ -1071,16 +1080,16 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ -#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ -#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ -#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ -#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ #define TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) */ #define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) */ #define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */ #define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */ #define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */ #define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ /** * @} @@ -1802,6 +1811,17 @@ mode. TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ }while(0) +/** @brief Select the Capture/compare DMA request source. + * @param __HANDLE__ specifies the TIM Handle. + * @param __CCDMA__ specifies Capture/compare DMA request source + * This parameter can be one of the following values: + * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event + * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event + * @retval None + */ +#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ + MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) + /** * @} */ @@ -1866,7 +1886,7 @@ mode. ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) #define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ - ((__MODE__) == TIM_UIFREMAP_ENALE)) + ((__MODE__) == TIM_UIFREMAP_ENABLE)) #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ @@ -1932,21 +1952,24 @@ mode. #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2)) +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \ + ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U)) + #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ ((__CHANNEL__) == TIM_CHANNEL_3) || \ ((__CHANNEL__) == TIM_CHANNEL_4)) #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ @@ -2072,18 +2095,6 @@ mode. ((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || \ ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) -#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_ITR4) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR11)|| \ - ((__SELECTION__) == TIM_TS_NONE)) - #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ @@ -2248,7 +2259,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); /** * @} @@ -2270,7 +2281,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -2292,7 +2304,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -2344,7 +2357,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @{ */ /* Timer Encoder functions ****************************************************/ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); @@ -2377,21 +2390,25 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); * @{ */ /* Control functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, + uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel); -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, @@ -2401,7 +2418,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ @@ -2438,17 +2455,17 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca * @{ */ /* Peripheral State functions ************************************************/ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); /* Peripheral Channel state functions ************************************************/ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); /** * @} */ @@ -2462,9 +2479,9 @@ HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); /** @defgroup TIM_Private_Functions TIM Private Functions * @{ */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tim_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tim_ex.c index 1ae8e14f0d5..a3604f3c196 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tim_ex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tim_ex.c @@ -154,7 +154,7 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig) { TIM_OC_InitTypeDef OC_Config; @@ -170,6 +170,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); @@ -520,7 +521,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -904,7 +905,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -919,7 +921,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -1434,7 +1436,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -1449,7 +1452,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -2108,7 +2111,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint3 * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef *sMasterConfig) + const TIM_MasterConfigTypeDef *sMasterConfig) { uint32_t tmpcr2; uint32_t tmpsmcr; @@ -2181,7 +2184,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; @@ -2264,7 +2267,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, - TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) + const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) { HAL_StatusTypeDef status = HAL_OK; @@ -2316,7 +2319,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, case TIM_BREAKINPUTSOURCE_MDF1: { bkin_enable_mask = TIM1_AF1_BKDF1BK0E; - bkin_enable_bitpos = 8U; + bkin_enable_bitpos = TIM1_AF1_BKDF1BK0E_Pos; + /* No polarity bit for MDF. Variable bkin_polarity_mask keeps its default value 0 */ bkin_polarity_mask = 0U; bkin_polarity_bitpos = 0U; break; @@ -2388,12 +2392,15 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @arg TIM_TIM1_ETR_COMP2 TIM1 ETR is connected to COMP2 output * @arg TIM_TIM1_ETR_HSI TIM1 ETR is connected to HSI * @arg TIM_TIM1_ETR_MSIS TIM1_ETR is connected to MSIS + * @arg TIM_TIM1_ETR_ADC2_AWD2 TIM1_ETR is connected to ADC2 AWD2 (*) + * @arg TIM_TIM1_ETR_ADC2_AWD3 TIM1_ETR is connected to ADC2 AWD3 (*) * @arg TIM_TIM1_ETR_ADC1_AWD1 TIM1 ETR is connected to ADC1 AWD1 * @arg TIM_TIM1_ETR_ADC1_AWD2 TIM1 ETR is connected to ADC1 AWD2 * @arg TIM_TIM1_ETR_ADC1_AWD3 TIM1 ETR is connected to ADC1 AWD3 * @arg TIM_TIM1_ETR_ADC4_AWD1 TIM1 ETR is connected to ADC4 AWD1 * @arg TIM_TIM1_ETR_ADC4_AWD2 TIM1 ETR is connected to ADC4 AWD2 * @arg TIM_TIM1_ETR_ADC4_AWD3 TIM1 ETR is connected to ADC4 AWD3 + * @arg TIM_TIM1_ETR_ADC2_AWD1 TIM1_ETR is connected to ADC2 AWD1 (*) * * For TIM2, the parameter can take one of the following values: * @arg TIM_TIM2_ETR_GPIO TIM2 ETR is connected to GPIO @@ -2402,10 +2409,15 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @arg TIM_TIM2_ETR_MSIK TIM2 ETR is connected to MSIK * @arg TIM_TIM2_ETR_HSI TIM2 ETR is connected to HSI * @arg TIM_TIM2_ETR_MSIS TIM2_ETR is connected to MSIS + * @arg TIM_TIM2_ETR_DCMI_VSYNC TIM2_ETR is connected to DCMI VSYNC (*) + * @arg TIM_TIM2_ETR_LTDC_VSYNC TIM2_ETR is connected to LTDC_VSYNC (*) * @arg TIM_TIM2_ETR_TIM3_ETR TIM2 ETR is connected to TIM3 ETR pin * @arg TIM_TIM2_ETR_TIM4_ETR TIM2 ETR is connected to TIM4 ETR pin * @arg TIM_TIM2_ETR_TIM5_ETR TIM2 ETR is connected to TIM5 ETR pin * @arg TIM_TIM2_ETR_LSE TIM2 ETR is connected to LSE + * @arg TIM_TIM2_ETR_DSI_TE TIM2_ETR is connected to DSI_TE (*) + * @arg TIM_TIM2_ETR_DCMI_HSYNC TIM2_ETR is connected to DCMI HSYNC (*) + * @arg TIM_TIM2_ETR_LTDC_HSYNC TIM2_ETR is connected to LTDC HSYNC (*) * * For TIM3, the parameter can take one of the following values: * @arg TIM_TIM3_ETR_GPIO TIM3 ETR is connected to GPIO @@ -2414,11 +2426,16 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @arg TIM_TIM3_ETR_MSIK TIM3 ETR is connected to MSIK * @arg TIM_TIM3_ETR_HSI TIM3 ETR is connected to HSI * @arg TIM_TIM3_ETR_MSIS TIM3_ETR is connected to MSIS + * @arg TIM_TIM3_ETR_DCMI_VSYNC TIM3_ETR is connected to DCMI VSYNC (*) + * @arg TIM_TIM3_ETR_LTDC_VSYNC TIM3_ETR is connected to LTDC_VSYNC (*) * @arg TIM_TIM3_ETR_TIM2_ETR TIM3 ETR is connected to TIM2 ETR pin * @arg TIM_TIM3_ETR_TIM4_ETR TIM3 ETR is connected to TIM4 ETR pin + * @arg TIM_TIM3_ETR_DSI_TE TIM2_ETR is connected to DSI_TE (*) * @arg TIM_TIM3_ETR_ADC1_AWD1 TIM3 ETR is connected to ADC1 AWD1 * @arg TIM_TIM3_ETR_ADC1_AWD2 TIM3 ETR is connected to ADC1 AWD2 * @arg TIM_TIM3_ETR_ADC1_AWD3 TIM3 ETR is connected to ADC1 AWD3 + * @arg TIM_TIM3_ETR_DCMI_HSYNC TIM3_ETR is connected to DCMI HSYNC (*) + * @arg TIM_TIM3_ETR_LTDC_HSYNC TIM3_ETR is connected to LTDC HSYNC (*) * * For TIM4, the parameter can take one of the following values: * @arg TIM_TIM4_ETR_GPIO TIM4 ETR is connected to GPIO @@ -2427,8 +2444,16 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @arg TIM_TIM4_ETR_MSIK TIM4 ETR is connected to MSIK * @arg TIM_TIM4_ETR_HSI TIM4 ETR is connected to HSI * @arg TIM_TIM4_ETR_MSIS TIM4_ETR is connected to MSIS + * @arg TIM_TIM4_ETR_DCMI_VSYNC TIM4_ETR is connected to DCMI VSYNC (*) + * @arg TIM_TIM4_ETR_LTDC_VSYNC TIM4_ETR is connected to LTDC_VSYNC (*) * @arg TIM_TIM4_ETR_TIM3_ETR TIM4 ETR is connected to TIM3 ETR pin * @arg TIM_TIM4_ETR_TIM5_ETR TIM4 ETR is connected to TIM5 ETR pin + * @arg TIM_TIM4_ETR_DSI_TE TIM2_ETR is connected to DSI_TE (*) + * @arg TIM_TIM4_ETR_ADC2_AWD1 TIM4_ETR is connected to ADC2 AWD1 (*) + * @arg TIM_TIM4_ETR_ADC2_AWD2 TIM4_ETR is connected to ADC2 AWD2 (*) + * @arg TIM_TIM4_ETR_ADC2_AWD3 TIM4_ETR is connected to ADC2 AWD3 (*) + * @arg TIM_TIM4_ETR_DCMI_HSYNC TIM4_ETR is connected to DCMI HSYNC (*) + * @arg TIM_TIM4_ETR_LTDC_HSYNC TIM4_ETR is connected to LTDC HSYNC (*) * * For TIM5, the parameter can take one of the following values: * @arg TIM_TIM5_ETR_GPIO TIM5 ETR is connected to GPIO @@ -2437,8 +2462,13 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @arg TIM_TIM5_ETR_MSIK TIM5 ETR is connected to MSIK * @arg TIM_TIM5_ETR_HSI TIM5 ETR is connected to HSI * @arg TIM_TIM5_ETR_MSIS TIM5_ETR is connected to MSIS + * @arg TIM_TIM5_ETR_DCMI_VSYNC TIM5_ETR is connected to DCMI VSYNC (*) + * @arg TIM_TIM5_ETR_LTDC_VSYNC TIM5_ETR is connected to LTDC_VSYNC (*) * @arg TIM_TIM5_ETR_TIM2_ETR TIM5 ETR is connected to TIM2 ETR pin * @arg TIM_TIM5_ETR_TIM3_ETR TIM5 ETR is connected to TIM3 ETR pin + * @arg TIM_TIM5_ETR_DSI_TE TIM5_ETR is connected to DSI_TE (*) + * @arg TIM_TIM5_ETR_DCMI_HSYNC TIM5_ETR is connected to DCMI HSYNC (*) + * @arg TIM_TIM5_ETR_LTDC_HSYNC TIM5_ETR is connected to LTDC HSYNC (*) * * For TIM8, the parameter can take one of the following values: * @arg TIM_TIM8_ETR_GPIO TIM8 ETR is connected to GPIO @@ -2447,12 +2477,17 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @arg TIM_TIM8_ETR_MSIK TIM8 ETR is connected to MSIK * @arg TIM_TIM8_ETR_HSI TIM8 ETR is connected to HSI * @arg TIM_TIM8_ETR_MSIS TIM8_ETR is connected to MSIS + * @arg TIM_TIM8_ETR_ADC2_AWD2 TIM8_ETR is connected to ADC2 AWD2 (*) + * @arg TIM_TIM8_ETR_ADC2_AWD3 TIM8_ETR is connected to ADC2 AWD3 (*) * @arg TIM_TIM8_ETR_ADC1_AWD1 TIM8 ETR is connected to ADC1 AWD1 * @arg TIM_TIM8_ETR_ADC1_AWD2 TIM8 ETR is connected to ADC1 AWD2 * @arg TIM_TIM8_ETR_ADC1_AWD3 TIM8 ETR is connected to ADC1 AWD3 * @arg TIM_TIM8_ETR_ADC4_AWD1 TIM8 ETR is connected to ADC4 AWD1 * @arg TIM_TIM8_ETR_ADC4_AWD2 TIM8 ETR is connected to ADC4 AWD2 * @arg TIM_TIM8_ETR_ADC4_AWD3 TIM8 ETR is connected to ADC4 AWD3 + * @arg TIM_TIM8_ETR_ADC2_AWD1 TIM8_ETR is connected to ADC2 AWD1 (*) + * + * (*) Value not defined in all devices. * * @retval HAL status */ @@ -2698,7 +2733,7 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B * @note Break input is automatically armed as soon as MOE bit is set. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput) { HAL_StatusTypeDef status = HAL_OK; uint32_t tickstart; @@ -3028,6 +3063,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim, sEncoderIndexConfig->Filter); /* Configures the encoder index */ +#if defined (STM32U575xx) || defined (STM32U585xx) if (HAL_GetREVID() >= REV_ID_B) /* supported in cut2 */ { MODIFY_REG(htim->Instance->ECR, @@ -3047,6 +3083,15 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim, sEncoderIndexConfig->Position | TIM_ECR_IE)); } +#else + MODIFY_REG(htim->Instance->ECR, + TIM_ECR_IDIR_Msk | TIM_ECR_IBLK_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk, + (sEncoderIndexConfig->Direction | + (sEncoderIndexConfig->Blanking) | + ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) | + sEncoderIndexConfig->Position | + TIM_ECR_IE)); +#endif /* STM32U575xx || STM32U585xx */ __HAL_UNLOCK(htim); @@ -3272,7 +3317,7 @@ __weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim) * @param htim TIM Hall Sensor handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -3288,7 +3333,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_4: TIM Channel 4 * @retval TIM Complementary channel state */ -HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) { HAL_TIM_ChannelStateTypeDef channel_state; @@ -3308,7 +3353,7 @@ HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Functions TIMEx Private Functions +/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions * @{ */ @@ -3466,6 +3511,7 @@ HAL_StatusTypeDef HAL_TIMEx_EnableHSE32(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_HSE32_INSTANCE(htim->Instance)); +#if defined (STM32U575xx) || defined (STM32U585xx) /* The Cut1.x contains a limitation when using HSE/32 as input capture for TIM16 Bug ID 56: On TIM16, the HSE/32 input capture requires the set of HSE32EN bit of TIM17 Option Register */ if (HAL_GetREVID() < REV_ID_B) /* Cut1.x */ @@ -3477,6 +3523,9 @@ HAL_StatusTypeDef HAL_TIMEx_EnableHSE32(TIM_HandleTypeDef *htim) { SET_BIT(htim->Instance->OR1, TIM_OR1_HSE32EN); } +#else + SET_BIT(htim->Instance->OR1, TIM_OR1_HSE32EN); +#endif /* STM32U575xx || STM32U585xx */ return HAL_OK; } @@ -3492,6 +3541,7 @@ HAL_StatusTypeDef HAL_TIMEx_DisableHSE32(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_HSE32_INSTANCE(htim->Instance)); +#if defined (STM32U575xx) || defined (STM32U585xx) if (HAL_GetREVID() < REV_ID_B) /* Cut1.x */ { __HAL_RCC_TIM17_CLK_ENABLE(); @@ -3501,6 +3551,9 @@ HAL_StatusTypeDef HAL_TIMEx_DisableHSE32(TIM_HandleTypeDef *htim) { CLEAR_BIT(htim->Instance->OR1, TIM_OR1_HSE32EN); } +#else + CLEAR_BIT(htim->Instance->OR1, TIM_OR1_HSE32EN); +#endif /* STM32U575xx || STM32U585xx */ return HAL_OK; } diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tim_ex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tim_ex.h index ef7cfd10f03..e45a20e25b3 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tim_ex.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tim_ex.h @@ -112,12 +112,19 @@ typedef struct #define TIM_TIM1_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to MSIK */ #define TIM_TIM1_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM1_ETR is connected to HSI */ #define TIM_TIM1_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to MSI */ +#if defined(ADC2) +#define TIM_TIM1_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM1_ETR is connected to ADC2 AWD2 */ +#define TIM_TIM1_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC2 AWD3 */ +#endif /* ADC2 */ #define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_3) /*!< TIM1_ETR is connected to ADC1 AWD1 */ #define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD2 */ #define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM1_ETR is connected to ADC1 AWD3 */ #define TIM_TIM1_ETR_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC4 AWD1 */ #define TIM_TIM1_ETR_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< TIM1_ETR is connected to ADC4 AWD2 */ #define TIM_TIM1_ETR_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC4 AWD3 */ +#if defined(ADC2) +#define TIM_TIM1_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM1_ETR is connected to ADC2 AWD1 */ +#endif /* ADC2 */ #define TIM_TIM2_ETR_GPIO 0x00000000UL /*!< TIM2_ETR is not connected to I/O */ #define TIM_TIM2_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM2_ETR is connected to COMP1 output */ @@ -125,22 +132,44 @@ typedef struct #define TIM_TIM2_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to MSIK */ #define TIM_TIM2_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to HSI */ #define TIM_TIM2_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to MSIS */ +#if defined(DCMI) && defined(LTDC) +#define TIM_TIM2_ETR_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to DCMI VSYNC */ +#define TIM_TIM2_ETR_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to LTDC_VSYNC */ +#endif /* DCMI && LTDC */ #define TIM_TIM2_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< TIM2_ETR is connected to TIM3 ETR */ #define TIM_TIM2_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to TIM4 ETR */ #define TIM_TIM2_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to TIM5 ETR */ #define TIM_TIM2_ETR_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to LSE */ +#if defined(DSI) +#define TIM_TIM2_ETR_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to DSI_TE */ +#endif /* DSI */ +#if defined(DCMI) && defined(LTDC) +#define TIM_TIM2_ETR_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to DCMI HSYNC */ +#define TIM_TIM2_ETR_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to LTDC HSYNC */ +#endif /* DCMI && LTDC */ #define TIM_TIM3_ETR_GPIO 0x00000000UL /*!< TIM3_ETR is not connected to I/O */ #define TIM_TIM3_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to COMP1 output */ #define TIM_TIM3_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM3_ETR is connected to COMP2 output */ #define TIM_TIM3_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to MSIK */ #define TIM_TIM3_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM3_ETR is connected to HSI */ -#define TIM_TIM3_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to MSIS */ +#define TIM_TIM3_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to MSIS */ +#if defined(DCMI) && defined(LTDC) +#define TIM_TIM3_ETR_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM3_ETR is connected to DCMI VSYNC */ +#define TIM_TIM3_ETR_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to LTDC_VSYNC */ +#endif /* DCMI && LTDC */ #define TIM_TIM3_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< TIM3_ETR is connected to TIM2 ETR */ #define TIM_TIM3_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to TIM4 ETR */ +#if defined(DSI) +#define TIM_TIM3_ETR_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM3_ETR is connected to DSI_TE */ +#endif /* DSI */ #define TIM_TIM3_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to ADC1 AWD1 */ #define TIM_TIM3_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< TIM3_ETR is connected to ADC1 AWD2 */ #define TIM_TIM3_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to ADC1 AWD3 */ +#if defined(DCMI) && defined(LTDC) +#define TIM_TIM3_ETR_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM3_ETR is connected to DCMI HSYNC */ +#define TIM_TIM3_ETR_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to LTDC HSYNC */ +#endif /* DCMI && LTDC */ #define TIM_TIM4_ETR_GPIO 0x00000000UL /*!< TIM4_ETR is not connected to I/O */ #define TIM_TIM4_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM4_ETR is connected to COMP1 output */ @@ -148,8 +177,24 @@ typedef struct #define TIM_TIM4_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to MSIK */ #define TIM_TIM4_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM4_ETR is connected to HSI */ #define TIM_TIM4_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to MSIS */ +#if defined(DCMI) && defined(LTDC) +#define TIM_TIM4_ETR_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM4_ETR is connected to DCMI VSYNC */ +#define TIM_TIM4_ETR_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to LTDC_VSYNC */ +#endif /* DCMI && LTDC */ #define TIM_TIM4_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< TIM4_ETR is connected to TIM3 ETR */ #define TIM_TIM4_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to TIM5 ETR */ +#if defined(DSI) +#define TIM_TIM4_ETR_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to DSI_TE */ +#endif /* DSI */ +#if defined(ADC2) +#define TIM_TIM4_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to ADC2 AWD1 */ +#define TIM_TIM4_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< TIM4_ETR is connected to ADC2 AWD2 */ +#define TIM_TIM4_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to ADC2 AWD3 */ +#endif /* ADC2 */ +#if defined(DCMI) && defined(LTDC) +#define TIM_TIM4_ETR_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM4_ETR is connected to DCMI HSYNC */ +#define TIM_TIM4_ETR_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to LTDC HSYNC */ +#endif /* DCMI && LTDC */ #define TIM_TIM5_ETR_GPIO 0x00000000UL /*!< TIM5_ETR is not connected to I/O */ #define TIM_TIM5_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to COMP1 output */ @@ -157,8 +202,19 @@ typedef struct #define TIM_TIM5_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to MSIK */ #define TIM_TIM5_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM5_ETR is connected to HSI */ #define TIM_TIM5_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to MSIS */ +#if defined(DCMI) && defined(LTDC) +#define TIM_TIM5_ETR_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM5_ETR is connected to DCMI VSYNC */ +#define TIM_TIM5_ETR_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to LTDC_VSYNC */ +#endif /* DCMI && LTDC */ #define TIM_TIM5_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< TIM5_ETR is connected to TIM2 ETR */ #define TIM_TIM5_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to TIM3 ETR */ +#if defined(DSI) +#define TIM_TIM5_ETR_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM5_ETR is connected to DSI_TE */ +#endif /* DSI */ +#if defined(DCMI) && defined(LTDC) +#define TIM_TIM5_ETR_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM5_ETR is connected to DCMI HSYNC */ +#define TIM_TIM5_ETR_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to LTDC HSYNC */ +#endif /* DCMI && LTDC */ #define TIM_TIM8_ETR_GPIO 0x00000000UL /*!< TIM8_ETR is not connected to I/O */ #define TIM_TIM8_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM8_ETR is connected to COMP1 output */ @@ -166,12 +222,19 @@ typedef struct #define TIM_TIM8_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to MSIK */ #define TIM_TIM8_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM8_ETR is connected to HSI */ #define TIM_TIM8_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to MSIS */ +#if defined(ADC2) +#define TIM_TIM8_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM8_ETR is connected to ADC2 AWD2 */ +#define TIM_TIM8_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD3 */ +#endif /* ADC2 */ #define TIM_TIM8_ETR_ADC1_AWD1 TIM1_AF1_ETRSEL_3 /*!< TIM8_ETR is connected to ADC1 AWD1 */ #define TIM_TIM8_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC1 AWD2 */ #define TIM_TIM8_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM8_ETR is connected to ADC1 AWD3 */ #define TIM_TIM8_ETR_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC4 AWD1 */ #define TIM_TIM8_ETR_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< TIM8_ETR is connected to ADC4 AWD2 */ #define TIM_TIM8_ETR_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC4 AWD3 */ +#if defined(ADC2) +#define TIM_TIM8_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM8_ETR is connected to ADC2 AWD1 */ +#endif /* ADC2 */ /** * @} */ @@ -486,14 +549,14 @@ typedef struct #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ ((((INSTANCE) == TIM1) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ @@ -502,14 +565,14 @@ typedef struct || \ (((INSTANCE) == TIM2) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ @@ -519,14 +582,14 @@ typedef struct || \ (((INSTANCE) == TIM3) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ @@ -535,15 +598,15 @@ typedef struct || \ (((INSTANCE) == TIM4) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ @@ -551,15 +614,15 @@ typedef struct || \ (((INSTANCE) == TIM5) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ @@ -567,15 +630,15 @@ typedef struct || \ (((INSTANCE) == TIM8) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ @@ -583,13 +646,13 @@ typedef struct || \ (((INSTANCE) == TIM15) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ @@ -597,12 +660,12 @@ typedef struct #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ - (((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ @@ -611,12 +674,12 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM2) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ @@ -625,12 +688,12 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM3) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ @@ -639,13 +702,13 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM4) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ @@ -653,13 +716,13 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM5) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ @@ -667,13 +730,13 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM8) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ @@ -681,13 +744,13 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM15) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ @@ -775,7 +838,7 @@ typedef struct #define IS_TIM_OC_CHANNEL_MODE(__MODE__, __CHANNEL__) \ (IS_TIM_OC_MODE(__MODE__) \ && ((((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) \ - ? (((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4)) : (1==1)) ) + ? (((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4)) : (1 == 1))) #define IS_TIM_PULSEONCOMPARE_CHANNEL(__CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_3) || \ @@ -830,7 +893,7 @@ typedef struct * @{ */ /* Timer Hall Sensor functions **********************************************/ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); @@ -863,7 +926,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -882,7 +946,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -916,11 +981,11 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef *sMasterConfig); + const TIM_MasterConfigTypeDef *sMasterConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, - TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); + const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel); @@ -928,7 +993,7 @@ HAL_StatusTypeDef HAL_TIMEx_EnableHSE32(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_DisableHSE32(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); -HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput); HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim, uint32_t PulseWidthPrescaler, @@ -974,8 +1039,8 @@ void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim); * @{ */ /* Extended Peripheral State functions ***************************************/ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN); /** * @} */ @@ -986,7 +1051,7 @@ HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, /* End of exported functions -------------------------------------------------*/ /* Private functions----------------------------------------------------------*/ -/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions +/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions * @{ */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tsc.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tsc.c index 5cbb12c858e..4e0f84425a7 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tsc.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tsc.c @@ -93,10 +93,10 @@ [..] The compilation flag USE_HAL_TSC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_TSC_RegisterCallback() to register an interrupt callback. + Use Functions HAL_TSC_RegisterCallback() to register an interrupt callback. [..] - Function @ref HAL_TSC_RegisterCallback() allows to register following callbacks: + Function HAL_TSC_RegisterCallback() allows to register following callbacks: (+) ConvCpltCallback : callback for conversion complete process. (+) ErrorCallback : callback for error detection. (+) MspInitCallback : callback for Msp Init. @@ -106,9 +106,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_TSC_UnRegisterCallback to reset a callback to the default + Use function HAL_TSC_UnRegisterCallback to reset a callback to the default weak function. - @ref HAL_TSC_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_TSC_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. [..] This function allows to reset following callbacks: @@ -118,23 +118,23 @@ (+) MspDeInitCallback : callback for Msp DeInit. [..] - By default, after the @ref HAL_TSC_Init() and when the state is @ref HAL_TSC_STATE_RESET + By default, after the HAL_TSC_Init() and when the state is HAL_TSC_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_TSC_ConvCpltCallback(), @ref HAL_TSC_ErrorCallback(). + examples HAL_TSC_ConvCpltCallback(), HAL_TSC_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_TSC_Init()/ @ref HAL_TSC_DeInit() only when + reset to the legacy weak functions in the HAL_TSC_Init()/ HAL_TSC_DeInit() only when these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the @ref HAL_TSC_Init()/ @ref HAL_TSC_DeInit() + If MspInit or MspDeInit are not null, the HAL_TSC_Init()/ HAL_TSC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_TSC_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_TSC_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_TSC_STATE_READY or @ref HAL_TSC_STATE_RESET state, + in HAL_TSC_STATE_READY or HAL_TSC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_TSC_RegisterCallback() before calling @ref HAL_TSC_DeInit() - or @ref HAL_TSC_Init() function. + using HAL_TSC_RegisterCallback() before calling HAL_TSC_DeInit() + or HAL_TSC_Init() function. [..] When the compilation flag USE_HAL_TSC_REGISTER_CALLBACKS is set to 0 or @@ -821,7 +821,7 @@ HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc) * @param gx_index Index of the group * @retval Group status */ -TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index) +TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(const TSC_HandleTypeDef *htsc, uint32_t gx_index) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); @@ -838,7 +838,7 @@ TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t * @param gx_index Index of the group * @retval Acquisition measure */ -uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index) +uint32_t HAL_TSC_GroupGetValue(const TSC_HandleTypeDef *htsc, uint32_t gx_index) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); @@ -873,7 +873,7 @@ uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index) * @param config Pointer to the configuration structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config) +HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, const TSC_IOConfigTypeDef *config) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tsc.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tsc.h index be6312315c7..24fff1c615a 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tsc.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_tsc.h @@ -137,7 +137,9 @@ enum TSC_GROUP5_IDX, TSC_GROUP6_IDX, TSC_GROUP7_IDX, +#if defined(TSC_IOCCR_G8_IO1) TSC_GROUP8_IDX, +#endif /* TSC_IOCCR_G8_IO1 */ TSC_NB_OF_GROUPS }; @@ -186,22 +188,38 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to /** @defgroup TSC_CTPulseHL_Config CTPulse High Length * @{ */ -#define TSC_CTPH_1CYCLE 0x00000000UL /*!< Charge transfer pulse high during 1 cycle (PGCLK) */ -#define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */ -#define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */ -#define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 4 cycles (PGCLK) */ -#define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 /*!< Charge transfer pulse high during 5 cycles (PGCLK) */ -#define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 6 cycles (PGCLK) */ -#define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 7 cycles (PGCLK) */ -#define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 8 cycles (PGCLK) */ -#define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 /*!< Charge transfer pulse high during 9 cycles (PGCLK) */ -#define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 10 cycles (PGCLK) */ -#define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 11 cycles (PGCLK) */ -#define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 12 cycles (PGCLK) */ -#define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) /*!< Charge transfer pulse high during 13 cycles (PGCLK) */ -#define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 14 cycles (PGCLK) */ -#define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 15 cycles (PGCLK) */ -#define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 16 cycles (PGCLK) */ +#define TSC_CTPH_1CYCLE 0x00000000UL +/*!< Charge transfer pulse high during 1 cycle (PGCLK) */ +#define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 +/*!< Charge transfer pulse high during 2 cycles (PGCLK) */ +#define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 +/*!< Charge transfer pulse high during 3 cycles (PGCLK) */ +#define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) +/*!< Charge transfer pulse high during 4 cycles (PGCLK) */ +#define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 +/*!< Charge transfer pulse high during 5 cycles (PGCLK) */ +#define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) +/*!< Charge transfer pulse high during 6 cycles (PGCLK) */ +#define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) +/*!< Charge transfer pulse high during 7 cycles (PGCLK) */ +#define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) +/*!< Charge transfer pulse high during 8 cycles (PGCLK) */ +#define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 +/*!< Charge transfer pulse high during 9 cycles (PGCLK) */ +#define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) +/*!< Charge transfer pulse high during 10 cycles (PGCLK) */ +#define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) +/*!< Charge transfer pulse high during 11 cycles (PGCLK) */ +#define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) +/*!< Charge transfer pulse high during 12 cycles (PGCLK) */ +#define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) +/*!< Charge transfer pulse high during 13 cycles (PGCLK) */ +#define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) +/*!< Charge transfer pulse high during 14 cycles (PGCLK) */ +#define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) +/*!< Charge transfer pulse high during 15 cycles (PGCLK) */ +#define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) +/*!< Charge transfer pulse high during 16 cycles (PGCLK) */ /** * @} */ @@ -209,22 +227,38 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to /** @defgroup TSC_CTPulseLL_Config CTPulse Low Length * @{ */ -#define TSC_CTPL_1CYCLE 0x00000000UL /*!< Charge transfer pulse low during 1 cycle (PGCLK) */ -#define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */ -#define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */ -#define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 4 cycles (PGCLK) */ -#define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 /*!< Charge transfer pulse low during 5 cycles (PGCLK) */ -#define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 6 cycles (PGCLK) */ -#define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 7 cycles (PGCLK) */ -#define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 8 cycles (PGCLK) */ -#define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 /*!< Charge transfer pulse low during 9 cycles (PGCLK) */ -#define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 10 cycles (PGCLK) */ -#define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 11 cycles (PGCLK) */ -#define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 12 cycles (PGCLK) */ -#define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) /*!< Charge transfer pulse low during 13 cycles (PGCLK) */ -#define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 14 cycles (PGCLK) */ -#define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 15 cycles (PGCLK) */ -#define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 16 cycles (PGCLK) */ +#define TSC_CTPL_1CYCLE 0x00000000UL +/*!< Charge transfer pulse low during 1 cycle (PGCLK) */ +#define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 +/*!< Charge transfer pulse low during 2 cycles (PGCLK) */ +#define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 +/*!< Charge transfer pulse low during 3 cycles (PGCLK) */ +#define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) +/*!< Charge transfer pulse low during 4 cycles (PGCLK) */ +#define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 +/*!< Charge transfer pulse low during 5 cycles (PGCLK) */ +#define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) +/*!< Charge transfer pulse low during 6 cycles (PGCLK) */ +#define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) +/*!< Charge transfer pulse low during 7 cycles (PGCLK) */ +#define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) +/*!< Charge transfer pulse low during 8 cycles (PGCLK) */ +#define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 +/*!< Charge transfer pulse low during 9 cycles (PGCLK) */ +#define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) +/*!< Charge transfer pulse low during 10 cycles (PGCLK) */ +#define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) +/*!< Charge transfer pulse low during 11 cycles (PGCLK) */ +#define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) +/*!< Charge transfer pulse low during 12 cycles (PGCLK) */ +#define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) +/*!< Charge transfer pulse low during 13 cycles (PGCLK) */ +#define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) +/*!< Charge transfer pulse low during 14 cycles (PGCLK) */ +#define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) +/*!< Charge transfer pulse low during 15 cycles (PGCLK) */ +#define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) +/*!< Charge transfer pulse low during 16 cycles (PGCLK) */ /** * @} */ @@ -288,8 +322,11 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to /** @defgroup TSC_Acquisition_Mode Acquisition Mode * @{ */ -#define TSC_ACQ_MODE_NORMAL 0x00000000UL /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */ -#define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM /*!< Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) */ +#define TSC_ACQ_MODE_NORMAL 0x00000000UL +/*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */ +#define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM +/*!< Synchronized acquisition mode (acquisition starts if START bit is set and +when the selected signal is detected on the SYNC input pin) */ /** * @} */ @@ -322,19 +359,31 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to #define TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX) #define TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX) #define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX) +#if defined(TSC_IOCCR_G8_IO1) #define TSC_GROUP8 (0x1UL << TSC_GROUP8_IDX) +#endif /* TSC_IOCCR_G8_IO1 */ + +#define TSC_GROUPX_NOT_SUPPORTED 0xFF000000UL /*!< TSC GroupX not supported */ #define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */ #define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */ #define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */ +#if defined(TSC_IOCCR_G1_IO4) #define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */ +#else +#define TSC_GROUP1_IO4 TSC_GROUPX_NOT_SUPPORTED /*!< TSC Group1 IO4 not supported */ +#endif /* TSC_IOCCR_G1_IO4 */ #define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */ #define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */ #define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */ #define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */ +#if defined(TSC_IOCCR_G3_IO1) #define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */ +#else +#define TSC_GROUP3_IO1 TSC_GROUPX_NOT_SUPPORTED /*!< TSC Group3 IO1 not supported */ +#endif /* TSC_IOCCR_G3_IO1 */ #define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */ #define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */ #define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */ @@ -358,11 +407,19 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to #define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */ #define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */ #define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */ +#if defined(TSC_IOCCR_G8_IO1) #define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1 /*!< TSC Group8 IO1 */ #define TSC_GROUP8_IO2 TSC_IOCCR_G8_IO2 /*!< TSC Group8 IO2 */ #define TSC_GROUP8_IO3 TSC_IOCCR_G8_IO3 /*!< TSC Group8 IO3 */ #define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4 /*!< TSC Group8 IO4 */ +#else + +#define TSC_GROUP8_IO1 (uint32_t)(0x00000080UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group8 IO1 not supported */ +#define TSC_GROUP8_IO2 TSC_GROUP8_IO1 /*!< TSC Group8 IO2 not supported */ +#define TSC_GROUP8_IO3 TSC_GROUP8_IO1 /*!< TSC Group8 IO3 not supported */ +#define TSC_GROUP8_IO4 TSC_GROUP8_IO1 /*!< TSC Group8 IO4 not supported */ +#endif /* TSC_IOCCR_G8_IO1 */ /** * @} */ @@ -382,10 +439,10 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to * @retval None */ #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) -#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_TSC_STATE_RESET;\ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ +#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_TSC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) @@ -670,7 +727,9 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to #define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL)\ || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS))) -#define IS_TSC_GROUP(__VALUE__) (((__VALUE__) == 0UL) ||\ + +#define IS_TSC_GROUP(__VALUE__) ((((__VALUE__) & TSC_GROUPX_NOT_SUPPORTED) != TSC_GROUPX_NOT_SUPPORTED) && \ + (((__VALUE__) == 0UL) ||\ (((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\ (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\ (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\ @@ -702,7 +761,8 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to (((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\ (((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\ (((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\ - (((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4)) + (((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4))) + /** * @} */ @@ -740,8 +800,8 @@ HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc); HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc); HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc); HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc); -TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index); -uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index); +TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(const TSC_HandleTypeDef *htsc, uint32_t gx_index); +uint32_t HAL_TSC_GroupGetValue(const TSC_HandleTypeDef *htsc, uint32_t gx_index); /** * @} */ @@ -750,7 +810,7 @@ uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index); * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config); +HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, const TSC_IOConfigTypeDef *config); HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_uart.c index 14998aaa388..0f28a6f5ef0 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_uart.c @@ -87,8 +87,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_UART_RegisterCallback() to register a user callback. - Function @ref HAL_UART_RegisterCallback() allows to register following callbacks: + Use Function HAL_UART_RegisterCallback() to register a user callback. + Function HAL_UART_RegisterCallback() allows to register following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. (+) TxCpltCallback : Tx Complete Callback. (+) RxHalfCpltCallback : Rx Half Complete Callback. @@ -106,9 +106,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default + Use function HAL_UART_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. @@ -127,16 +127,16 @@ [..] For specific callback RxEventCallback, use dedicated registration/reset functions: - respectively @ref HAL_UART_RegisterRxEventCallback() , @ref HAL_UART_UnRegisterRxEventCallback(). + respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback(). [..] - By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback(). + examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init() - and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_UART_Init() + and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -145,8 +145,8 @@ in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit() - or @ref HAL_UART_Init() function. + using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit() + or HAL_UART_Init() function. [..] When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or @@ -155,6 +155,7 @@ @endverbatim + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -196,8 +197,9 @@ /** @addtogroup UART_Private_Functions * @{ */ -static void UART_EndTxTransfer(UART_HandleTypeDef *huart); static void UART_EndRxTransfer(UART_HandleTypeDef *huart); +#if defined(HAL_DMA_MODULE_ENABLED) +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); @@ -208,6 +210,7 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +#endif /* HAL_DMA_MODULE_ENABLED */ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart); static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); @@ -655,6 +658,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_RESET; huart->RxState = HAL_UART_STATE_RESET; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; __HAL_UNLOCK(huart); @@ -695,6 +699,9 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) /** * @brief Register a User UART Callback * To be used instead of the weak predefined callback + * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID * @param huart uart handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -726,8 +733,6 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ return HAL_ERROR; } - __HAL_LOCK(huart); - if (huart->gState == HAL_UART_STATE_READY) { switch (CallbackID) @@ -813,14 +818,15 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ status = HAL_ERROR; } - __HAL_UNLOCK(huart); - return status; } /** * @brief Unregister an UART Callback * UART callaback is redirected to the weak predefined callback + * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID * @param huart uart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -843,8 +849,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR { HAL_StatusTypeDef status = HAL_OK; - __HAL_LOCK(huart); - if (HAL_UART_STATE_READY == huart->gState) { switch (CallbackID) @@ -932,8 +936,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR status = HAL_ERROR; } - __HAL_UNLOCK(huart); - return status; } @@ -1109,10 +1111,10 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint8_t *pdata8bits; - uint16_t *pdata16bits; + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; uint32_t tickstart; /* Check that a Tx process is not already ongoing */ @@ -1123,8 +1125,14 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u return HAL_ERROR; } - __HAL_LOCK(huart); +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } +#endif /* USART_DMAREQUESTS_SW_WA */ huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; @@ -1138,7 +1146,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { pdata8bits = NULL; - pdata16bits = (uint16_t *) pData; + pdata16bits = (const uint16_t *) pData; } else { @@ -1146,12 +1154,13 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u pdata16bits = NULL; } - __HAL_UNLOCK(huart); - while (huart->TxXferCount > 0U) { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { + + huart->gState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } if (pdata8bits == NULL) @@ -1169,6 +1178,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { + huart->gState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } @@ -1213,8 +1224,14 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui return HAL_ERROR; } - __HAL_LOCK(huart); +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } +#endif /* USART_DMAREQUESTS_SW_WA */ huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; @@ -1241,13 +1258,13 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui pdata16bits = NULL; } - __HAL_UNLOCK(huart); - /* as long as data have to be received */ while (huart->RxXferCount > 0U) { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { + huart->RxState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } if (pdata8bits == NULL) @@ -1284,7 +1301,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) @@ -1294,8 +1311,14 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData return HAL_ERROR; } - __HAL_LOCK(huart); +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } +#endif /* USART_DMAREQUESTS_SW_WA */ huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; @@ -1317,8 +1340,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData huart->TxISR = UART_TxISR_8BIT_FIFOEN; } - __HAL_UNLOCK(huart); - /* Enable the TX FIFO threshold interrupt */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); } @@ -1334,8 +1355,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData huart->TxISR = UART_TxISR_8BIT; } - __HAL_UNLOCK(huart); - /* Enable the Transmit Data Register Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); } @@ -1368,11 +1387,17 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, return HAL_ERROR; } - __HAL_LOCK(huart); - /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ if (!(IS_LPUART_INSTANCE(huart->Instance))) { /* Check that USART RTOEN bit is set */ @@ -1391,6 +1416,7 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, } } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Send an amount of data in DMA mode. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), @@ -1401,7 +1427,7 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef status; uint16_t nbByte = Size; @@ -1414,8 +1440,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat return HAL_ERROR; } - __HAL_LOCK(huart); - huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; @@ -1479,8 +1503,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; - __HAL_UNLOCK(huart); - /* Restore huart->gState to ready */ huart->gState = HAL_UART_STATE_READY; @@ -1490,8 +1512,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Clear the TC flag in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); - __HAL_UNLOCK(huart); - /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); @@ -1526,8 +1546,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData return HAL_ERROR; } - __HAL_LOCK(huart); - /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; @@ -1559,26 +1577,54 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) const HAL_UART_StateTypeDef gstate = huart->gState; const HAL_UART_StateTypeDef rxstate = huart->RxState; - __HAL_LOCK(huart); - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && (gstate == HAL_UART_STATE_BUSY_TX)) { - /* Disable the UART DMA Tx request */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + /* Suspend the UART DMA Tx channel : use blocking DMA Suspend API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + huart->hdmatx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } } if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && (rxstate == HAL_UART_STATE_BUSY_RX)) { - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + /* Suspend the UART DMA Rx channel : use blocking DMA Suspend API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - /* Disable the UART DMA Rx request */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - } + /* Set the UART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + huart->hdmarx->XferSuspendCallback = NULL; - __HAL_UNLOCK(huart); + if (HAL_DMAEx_Suspend(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } return HAL_OK; } @@ -1590,12 +1636,19 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { - __HAL_LOCK(huart); - if (huart->gState == HAL_UART_STATE_BUSY_TX) { - /* Enable the UART DMA Tx request */ - ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + /* Resume the UART DMA Tx channel */ + if (huart->hdmatx != NULL) + { + if (HAL_DMAEx_Resume(huart->hdmatx) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_ERROR; + } + } } if (huart->RxState == HAL_UART_STATE_BUSY_RX) { @@ -1603,14 +1656,24 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - /* Enable the UART DMA Rx request */ - ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - } + /* Resume the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + if (HAL_DMAEx_Resume(huart->hdmarx) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; - __HAL_UNLOCK(huart); + return HAL_ERROR; + } + } + } return HAL_OK; } @@ -1682,6 +1745,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) return HAL_OK; } +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Abort ongoing transfers (blocking mode). @@ -1708,11 +1772,15 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } - /* Disable the UART DMA Tx request if enabled */ +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) { @@ -1733,11 +1801,14 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) } } - /* Disable the UART DMA Rx request if enabled */ + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) { @@ -1757,6 +1828,7 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) } } } +#endif /* HAL_DMA_MODULE_ENABLED */ /* Reset Tx and Rx transfer counters */ huart->TxXferCount = 0U; @@ -1802,11 +1874,15 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - /* Disable the UART DMA Tx request if enabled */ +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) { @@ -1826,6 +1902,7 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) } } } +#endif /* HAL_DMA_MODULE_ENABLED */ /* Reset Tx transfer counter */ huart->TxXferCount = 0U; @@ -1866,11 +1943,15 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } - /* Disable the UART DMA Rx request if enabled */ +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) { @@ -1890,6 +1971,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) } } } +#endif /* HAL_DMA_MODULE_ENABLED */ /* Reset Rx transfer counter */ huart->RxXferCount = 0U; @@ -1936,6 +2018,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } +#if defined(HAL_DMA_MODULE_ENABLED) /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ /* DMA Tx Handle is valid */ @@ -1967,12 +2050,14 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) } } - /* Disable the UART DMA Tx request if enabled */ + /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable DMA Tx at UART level */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmatx != NULL) { @@ -1991,11 +2076,14 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) } } - /* Disable the UART DMA Rx request if enabled */ + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmarx != NULL) { @@ -2014,6 +2102,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) } } } +#endif /* HAL_DMA_MODULE_ENABLED */ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ if (abortcplt == 1U) @@ -2079,11 +2168,15 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - /* Disable the UART DMA Tx request if enabled */ +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmatx != NULL) { @@ -2120,6 +2213,7 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) } } else +#endif /* HAL_DMA_MODULE_ENABLED */ { /* Reset Tx transfer counter */ huart->TxXferCount = 0U; @@ -2175,11 +2269,15 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } - /* Disable the UART DMA Rx request if enabled */ +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmarx != NULL) { @@ -2223,6 +2321,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) } } else +#endif /* HAL_DMA_MODULE_ENABLED */ { /* Reset Rx transfer counter */ huart->RxXferCount = 0U; @@ -2356,11 +2455,15 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); - /* Disable the UART DMA Rx request if enabled */ +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) { @@ -2389,6 +2492,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } } else +#endif /* HAL_DMA_MODULE_ENABLED */ { /* Call user error callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -2426,6 +2530,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); +#if defined(HAL_DMA_MODULE_ENABLED) /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { @@ -2447,10 +2552,12 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; @@ -2460,6 +2567,11 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); @@ -2472,6 +2584,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } else { +#endif /* HAL_DMA_MODULE_ENABLED */ /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ @@ -2493,6 +2606,11 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) huart->RxISR = NULL; ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); @@ -2502,7 +2620,9 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; +#if defined(HAL_DMA_MODULE_ENABLED) } +#endif /* HAL_DMA_MODULE_ENABLED */ } /* UART in mode Transmitter ------------------------------------------------*/ @@ -2959,7 +3079,7 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) * the configuration information for the specified UART. * @retval HAL state */ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) { uint32_t temp1; uint32_t temp2; @@ -2975,7 +3095,7 @@ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) * the configuration information for the specified UART. * @retval UART Error Code */ -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) { return huart->ErrorCode; } @@ -3129,7 +3249,7 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) { - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); @@ -3149,10 +3269,10 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) if (pclk != 0U) { /* USARTDIV must be greater than or equal to 0d16 */ - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) { - huart->Instance->BRR = usartdiv; + huart->Instance->BRR = (uint16_t)usartdiv; } else { @@ -3217,12 +3337,14 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); } +#if defined(HAL_DMA_MODULE_ENABLED) /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); } +#endif /* HAL_DMA_MODULE_ENABLED */ /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) @@ -3267,6 +3389,13 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { + /* Disable TXE interrupt for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + /* Timeout occurred */ return HAL_TIMEOUT; } @@ -3278,6 +3407,15 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->RxState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + /* Timeout occurred */ return HAL_TIMEOUT; } @@ -3287,6 +3425,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; __HAL_UNLOCK(huart); @@ -3294,10 +3433,11 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) } /** - * @brief Handle UART Communication Timeout. + * @brief This function handles UART Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param huart UART handle. * @param Flag Specifies the UART flag to check - * @param Status Flag status (SET or RESET) + * @param Status The actual Flag status (SET or RESET) * @param Tickstart Tick start value * @param Timeout Timeout duration * @retval HAL status @@ -3313,35 +3453,39 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) - interrupts for the interrupt process */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | - USART_CR1_TXEIE_TXFNFIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - __HAL_UNLOCK(huart); return HAL_TIMEOUT; } if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) + { + /* Clear Overrun Error flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_ORE; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_ERROR; + } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) - interrupts for the interrupt process */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | - USART_CR1_TXEIE_TXFNFIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; huart->ErrorCode = HAL_UART_ERROR_RTO; /* Process Unlocked */ @@ -3395,10 +3539,11 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat huart->RxISR = UART_RxISR_8BIT_FIFOEN; } - __HAL_UNLOCK(huart); - /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); } else @@ -3413,14 +3558,20 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat huart->RxISR = UART_RxISR_8BIT; } - __HAL_UNLOCK(huart); - /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } } return HAL_OK; } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Start Receive operation in DMA mode. * @note This function could be called by all HAL UART API providing reception in DMA mode. @@ -3499,18 +3650,18 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; - __HAL_UNLOCK(huart); - /* Restore huart->RxState to ready */ huart->RxState = HAL_UART_STATE_READY; return HAL_ERROR; } } - __HAL_UNLOCK(huart); /* Enable the UART Parity Error Interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); @@ -3537,6 +3688,7 @@ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; } +#endif /* HAL_DMA_MODULE_ENABLED */ /** @@ -3565,6 +3717,7 @@ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief DMA UART transmit process complete callback. * @param hdma DMA handle. @@ -3579,10 +3732,12 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { huart->TxXferCount = 0U; +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } @@ -3635,10 +3790,12 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -3649,6 +3806,10 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) } } + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -3683,6 +3844,10 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Half Transfer */ + huart->RxEventType = HAL_UART_RXEVENT_HT; + /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -3941,6 +4106,7 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) HAL_UART_AbortReceiveCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief TX interrupt handler for 7 or 8 bits data word length . @@ -3980,7 +4146,7 @@ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) */ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) { - uint16_t *tmp; + const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) @@ -3995,7 +4161,7 @@ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) } else { - tmp = (uint16_t *) huart->pTxBuffPtr; + tmp = (const uint16_t *) huart->pTxBuffPtr; huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; @@ -4052,7 +4218,7 @@ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) */ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { - uint16_t *tmp; + const uint16_t *tmp; uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ @@ -4072,7 +4238,7 @@ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) { - tmp = (uint16_t *) huart->pTxBuffPtr; + tmp = (const uint16_t *) huart->pTxBuffPtr; huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; @@ -4143,6 +4309,19 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4158,6 +4337,7 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); @@ -4222,6 +4402,19 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4237,6 +4430,7 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); @@ -4352,6 +4546,19 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4367,6 +4574,7 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); @@ -4502,6 +4710,19 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4517,6 +4738,7 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); @@ -4575,3 +4797,4 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) /** * @} */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_uart.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_uart.h index 5340081a2af..988f5be2b1b 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_uart.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_uart.h @@ -122,9 +122,11 @@ typedef struct uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. This parameter can be a value of @ref UART_Overrun_Disable. */ +#if defined(HAL_DMA_MODULE_ENABLED) uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ +#endif /* HAL_DMA_MODULE_ENABLED */ uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. This parameter can be a value of @ref UART_AutoBaudRate_Enable. */ @@ -181,7 +183,7 @@ typedef uint32_t HAL_UART_StateTypeDef; /** * @brief HAL UART Reception type definition * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. - * It is expected to admit following values : + * This parameter can be a value of @ref UART_Reception_Type_Values : * HAL_UART_RECEPTION_STANDARD = 0x00U, * HAL_UART_RECEPTION_TOIDLE = 0x01U, * HAL_UART_RECEPTION_TORTO = 0x02U, @@ -189,6 +191,17 @@ typedef uint32_t HAL_UART_StateTypeDef; */ typedef uint32_t HAL_UART_RxTypeTypeDef; +/** + * @brief HAL UART Rx Event type definition + * @note HAL UART Rx Event type value aims to identify which type of Event has occurred + * leading to call of the RxEvent callback. + * This parameter can be a value of @ref UART_RxEvent_Type_Values : + * HAL_UART_RXEVENT_TC = 0x00U, + * HAL_UART_RXEVENT_HT = 0x01U, + * HAL_UART_RXEVENT_IDLE = 0x02U, + */ +typedef uint32_t HAL_UART_RxEventTypeTypeDef; + /** * @brief UART handle Structure definition */ @@ -200,7 +213,7 @@ typedef struct __UART_HandleTypeDef UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ uint16_t TxXferSize; /*!< UART Tx Transfer size */ @@ -223,14 +236,18 @@ typedef struct __UART_HandleTypeDef __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */ + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ +#if defined(HAL_DMA_MODULE_ENABLED) DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ +#endif /* HAL_DMA_MODULE_ENABLED */ HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management @@ -334,7 +351,9 @@ typedef void (*pUART_RxEventCallbackTypeDef) #define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ #define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */ #define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#if defined(HAL_DMA_MODULE_ENABLED) #define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#endif /* HAL_DMA_MODULE_ENABLED */ #define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -474,6 +493,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) * @} */ +#if defined(HAL_DMA_MODULE_ENABLED) /** @defgroup UART_DMA_Tx UART DMA Tx * @{ */ @@ -491,6 +511,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) /** * @} */ +#endif /* HAL_DMA_MODULE_ENABLED */ /** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection * @{ @@ -531,7 +552,9 @@ typedef void (*pUART_RxEventCallbackTypeDef) #define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ #define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ #define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ +#if defined(HAL_DMA_MODULE_ENABLED) #define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ +#endif /* HAL_DMA_MODULE_ENABLED */ #define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */ #define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ /** @@ -592,6 +615,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) * @} */ +#if defined(HAL_DMA_MODULE_ENABLED) /** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error * @{ */ @@ -600,6 +624,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) /** * @} */ +#endif /* HAL_DMA_MODULE_ENABLED */ /** @defgroup UART_MSB_First UART Advanced Feature MSB First * @{ @@ -787,7 +812,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) * @} */ -/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values +/** @defgroup UART_Reception_Type_Values UART Reception type values * @{ */ #define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ @@ -798,6 +823,16 @@ typedef void (*pUART_RxEventCallbackTypeDef) * @} */ +/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values + * @{ + */ +#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */ +#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */ +#define HAL_UART_RXEVENT_IDLE (0x00000002U) /*!< RxEvent linked to IDLE event */ +/** + * @} + */ + /** * @} */ @@ -1365,6 +1400,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) #define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Ensure that UART DMA TX state is valid. * @param __DMATX__ UART DMA TX state. @@ -1381,6 +1417,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) #define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ ((__DMARX__) == UART_DMA_RX_ENABLE)) +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Ensure that UART half-duplex state is valid. * @param __HDSEL__ UART half-duplex state. @@ -1413,6 +1450,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) * @param __INIT__ UART advanced features initialization. * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) */ +#if defined(HAL_DMA_MODULE_ENABLED) #define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ UART_ADVFEATURE_TXINVERT_INIT | \ UART_ADVFEATURE_RXINVERT_INIT | \ @@ -1422,6 +1460,16 @@ typedef void (*pUART_RxEventCallbackTypeDef) UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ UART_ADVFEATURE_MSBFIRST_INIT)) +#else +#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ + UART_ADVFEATURE_TXINVERT_INIT | \ + UART_ADVFEATURE_RXINVERT_INIT | \ + UART_ADVFEATURE_DATAINVERT_INIT | \ + UART_ADVFEATURE_SWAP_INIT | \ + UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ + UART_ADVFEATURE_MSBFIRST_INIT)) +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Ensure that UART frame TX inversion setting is valid. @@ -1472,6 +1520,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Ensure that UART DMA enabling or disabling on error setting is valid. * @param __DMA__ UART DMA enabling or disabling on error setting. @@ -1479,6 +1528,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) */ #define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Ensure that UART frame MSB first setting is valid. @@ -1582,15 +1632,17 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); +#endif /* HAL_DMA_MODULE_ENABLED */ /* Transfer Abort functions */ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); @@ -1640,8 +1692,8 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); */ /* Peripheral State and Errors functions **************************************************/ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart); /** * @} @@ -1664,7 +1716,9 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ uint32_t Tickstart, uint32_t Timeout); void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @} @@ -1694,3 +1748,4 @@ extern const uint16_t UARTPrescTable[12]; #endif #endif /* STM32U5xx_HAL_UART_H */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_uart_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_uart_ex.c index 984b0031fba..13d1ebca954 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_uart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_uart_ex.c @@ -37,6 +37,7 @@ configured prior starting RX/TX transfers. @endverbatim + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -702,11 +703,10 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p return HAL_ERROR; } - __HAL_LOCK(huart); - huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); @@ -730,8 +730,6 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p pdata16bits = NULL; } - __HAL_UNLOCK(huart); - /* Initialize output number of received elements */ *RxLen = 0U; @@ -748,6 +746,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p /* If Set, and data has already been received, this means Idle Event is valid : End reception */ if (*RxLen > 0U) { + huart->RxEventType = HAL_UART_RXEVENT_IDLE; huart->RxState = HAL_UART_STATE_READY; return HAL_OK; @@ -813,7 +812,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) @@ -823,29 +822,24 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t return HAL_ERROR; } - __HAL_LOCK(huart); - /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; - status = UART_Start_Receive_IT(huart, pData, Size); + (void)UART_Start_Receive_IT(huart, pData, Size); - /* Check Rx process has been successfully started */ - if (status == HAL_OK) + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - } - else - { - /* In case of errors already pending when reception is started, - Interrupts may have already been raised and lead to reception abortion. - (Overrun error for instance). - In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ - status = HAL_ERROR; - } + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; } return status; @@ -856,6 +850,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t } } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Receive an amount of data in DMA mode till either the expected number * of data is received or an IDLE event occurs. @@ -885,10 +880,9 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ return HAL_ERROR; } - __HAL_LOCK(huart); - /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; status = UART_Start_Receive_DMA(huart, pData, Size); @@ -917,6 +911,37 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ return HAL_BUSY; } } +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Provide Rx Event type that has lead to RxEvent callback execution. + * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress + * of reception process is provided to application through calls of Rx Event callback (either default one + * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, + * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead + * to Rx Event callback execution. + * @note This function is expected to be called within the user implementation of Rx Event Callback, + * in order to provide the accurate value : + * In Interrupt Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one) + * In DMA Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one). + * In DMA mode, RxEvent callback could be called several times; + * When DMA is configured in Normal Mode, HT event does not stop Reception process; + * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; + * @param huart UART handle. + * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values) + */ +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart) +{ + /* Return Rx Event type value, as stored in UART handle */ + return (huart->RxEventType); +} /** * @brief Set autonomous mode Configuration. @@ -924,7 +949,8 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ * @param sConfig Autonomous mode structure parameters. * @retval HAL status */ -HAL_StatusTypeDef HAL_UARTEx_SetConfigAutonomousMode(UART_HandleTypeDef *huart, UART_AutonomousModeConfTypeDef *sConfig) +HAL_StatusTypeDef HAL_UARTEx_SetConfigAutonomousMode(UART_HandleTypeDef *huart, + const UART_AutonomousModeConfTypeDef *sConfig) { uint32_t tmpreg; @@ -986,7 +1012,8 @@ HAL_StatusTypeDef HAL_UARTEx_SetConfigAutonomousMode(UART_HandleTypeDef *huart, * @param sConfig Autonomous mode structure parameters. * @retval HAL status */ -HAL_StatusTypeDef HAL_UARTEx_GetConfigAutonomousMode(UART_HandleTypeDef *huart, UART_AutonomousModeConfTypeDef *sConfig) +HAL_StatusTypeDef HAL_UARTEx_GetConfigAutonomousMode(const UART_HandleTypeDef *huart, + UART_AutonomousModeConfTypeDef *sConfig) { uint32_t tmpreg; @@ -1113,3 +1140,4 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) /** * @} */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_uart_ex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_uart_ex.h index e1c97ff94ec..f733981f18f 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_uart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_uart_ex.h @@ -267,12 +267,16 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout); HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#endif /* HAL_DMA_MODULE_ENABLED */ + +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart); /* Autonomous Mode Control functions **********************************************/ HAL_StatusTypeDef HAL_UARTEx_SetConfigAutonomousMode(UART_HandleTypeDef *huart, - UART_AutonomousModeConfTypeDef *sConfig); -HAL_StatusTypeDef HAL_UARTEx_GetConfigAutonomousMode(UART_HandleTypeDef *huart, + const UART_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_UARTEx_GetConfigAutonomousMode(const UART_HandleTypeDef *huart, UART_AutonomousModeConfTypeDef *sConfig); HAL_StatusTypeDef HAL_UARTEx_ClearConfigAutonomousMode(UART_HandleTypeDef *huart); @@ -296,72 +300,100 @@ HAL_StatusTypeDef HAL_UARTEx_ClearConfigAutonomousMode(UART_HandleTypeDef *huart * @retval UART clocking source, written in __CLOCKSOURCE__. */ #if defined(USART6) -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART1; \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART2; \ - } \ - else if((__HANDLE__)->Instance == USART3) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART3; \ - } \ - else if((__HANDLE__)->Instance == UART4) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_UART4; \ - } \ - else if((__HANDLE__)->Instance == UART5) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_UART5; \ - } \ - else if((__HANDLE__)->Instance == USART6) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART6; \ - } \ - else if((__HANDLE__)->Instance == LPUART1) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_LPUART1; \ - } \ - else \ - { \ - (__CLOCKSOURCE__) = 0U; \ - } \ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ + } \ + else if((__HANDLE__)->Instance == UART5) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART6; \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = 0U; \ + } \ + } while(0U) +#elif defined(USART2) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ + } \ + else if((__HANDLE__)->Instance == UART5) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = 0U; \ + } \ } while(0U) #else -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART1; \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART2; \ - } \ - else if((__HANDLE__)->Instance == USART3) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_USART3; \ - } \ - else if((__HANDLE__)->Instance == UART4) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_UART4; \ - } \ - else if((__HANDLE__)->Instance == UART5) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_UART5; \ - } \ - else if((__HANDLE__)->Instance == LPUART1) \ - { \ - (__CLOCKSOURCE__) = RCC_PERIPHCLK_LPUART1; \ - } \ - else \ - { \ - (__CLOCKSOURCE__) = 0U; \ - } \ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ + } \ + else if((__HANDLE__)->Instance == UART5) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = 0U; \ + } \ } while(0U) #endif /* USART6 */ @@ -512,3 +544,4 @@ HAL_StatusTypeDef HAL_UARTEx_ClearConfigAutonomousMode(UART_HandleTypeDef *huart #endif #endif /* STM32U5xx_HAL_UART_EX_H */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_usart.c index fcf2061e667..b263359d4c9 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_usart.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_usart.c @@ -73,8 +73,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_USART_RegisterCallback() to register a user callback. - Function @ref HAL_USART_RegisterCallback() allows to register following callbacks: + Use Function HAL_USART_RegisterCallback() to register a user callback. + Function HAL_USART_RegisterCallback() allows to register following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. (+) TxCpltCallback : Tx Complete Callback. (+) RxHalfCpltCallback : Rx Half Complete Callback. @@ -90,9 +90,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_USART_UnRegisterCallback() to reset a callback to the default + Use function HAL_USART_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. @@ -108,13 +108,13 @@ (+) MspDeInitCallback : USART MspDeInit. [..] - By default, after the @ref HAL_USART_Init() and when the state is HAL_USART_STATE_RESET + By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_USART_TxCpltCallback(), @ref HAL_USART_RxHalfCpltCallback(). + examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_USART_Init() - and @ref HAL_USART_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_USART_Init() and @ref HAL_USART_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_USART_Init() + and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -123,8 +123,8 @@ in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_USART_RegisterCallback() before calling @ref HAL_USART_DeInit() - or @ref HAL_USART_Init() function. + using HAL_USART_RegisterCallback() before calling HAL_USART_DeInit() + or HAL_USART_Init() function. [..] When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or @@ -133,6 +133,7 @@ @endverbatim + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -182,6 +183,7 @@ void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart); #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ static void USART_EndTransfer(USART_HandleTypeDef *husart); +#if defined(HAL_DMA_MODULE_ENABLED) static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); @@ -190,6 +192,7 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma); static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma); static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +#endif /* HAL_DMA_MODULE_ENABLED */ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart); @@ -406,6 +409,8 @@ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) /** * @brief Register a User USART Callback * To be used instead of the weak predefined callback + * @note The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET + * to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID * @param husart usart handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -435,8 +440,6 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(husart); if (husart->State == HAL_USART_STATE_READY) { @@ -525,15 +528,14 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(husart); - return status; } /** * @brief Unregister an USART Callback * USART callaback is redirected to the weak predefined callback + * @note The HAL_USART_UnRegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET + * to un-register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID * @param husart usart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -554,9 +556,6 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(husart); - if (HAL_USART_STATE_READY == husart->State) { switch (CallbackID) @@ -644,9 +643,6 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(husart); - return status; } #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ @@ -747,10 +743,11 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, + uint32_t Timeout) { - uint8_t *ptxdata8bits; - uint16_t *ptxdata16bits; + const uint8_t *ptxdata8bits; + const uint16_t *ptxdata16bits; uint32_t tickstart; if (husart->State == HAL_USART_STATE_READY) @@ -763,6 +760,14 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa /* Process Locked */ __HAL_LOCK(husart); +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX; @@ -776,7 +781,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { ptxdata8bits = NULL; - ptxdata16bits = (uint16_t *) pTxData; + ptxdata16bits = (const uint16_t *) pTxData; } else { @@ -861,6 +866,14 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat /* Process Locked */ __HAL_LOCK(husart); +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; @@ -956,13 +969,13 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { uint8_t *prxdata8bits; uint16_t *prxdata16bits; - uint8_t *ptxdata8bits; - uint16_t *ptxdata16bits; + const uint8_t *ptxdata8bits; + const uint16_t *ptxdata16bits; uint16_t uhMask; uint16_t rxdatacount; uint32_t tickstart; @@ -977,6 +990,20 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t /* Process Locked */ __HAL_LOCK(husart); +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + } + + /* Disable the USART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; @@ -997,7 +1024,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t { prxdata8bits = NULL; ptxdata8bits = NULL; - ptxdata16bits = (uint16_t *) pTxData; + ptxdata16bits = (const uint16_t *) pTxData; prxdata16bits = (uint16_t *) pRxData; } else @@ -1103,7 +1130,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t * @param Size amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) { if (husart->State == HAL_USART_STATE_READY) { @@ -1115,6 +1142,14 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT /* Process Locked */ __HAL_LOCK(husart); +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ husart->pTxBuffPtr = pTxData; husart->TxXferSize = Size; husart->TxXferCount = Size; @@ -1200,6 +1235,14 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx /* Process Locked */ __HAL_LOCK(husart); +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ husart->pRxBuffPtr = pRxData; husart->RxXferSize = Size; husart->RxXferCount = Size; @@ -1230,7 +1273,10 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx __HAL_UNLOCK(husart); /* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); } else @@ -1249,7 +1295,14 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx __HAL_UNLOCK(husart); /* Enable the USART Parity Error and Data Register not empty Interrupts */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } } if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) @@ -1290,7 +1343,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received). * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { @@ -1304,6 +1357,20 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint /* Process Locked */ __HAL_LOCK(husart); +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + } + + /* Disable the USART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ husart->pRxBuffPtr = pRxData; husart->RxXferSize = Size; husart->RxXferCount = Size; @@ -1338,8 +1405,11 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - /* Enable the USART Parity Error interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the TX and RX FIFO Threshold interrupts */ SET_BIT(husart->Instance->CR3, (USART_CR3_TXFTIE | USART_CR3_RXFTIE)); @@ -1364,7 +1434,14 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint SET_BIT(husart->Instance->CR3, USART_CR3_EIE); /* Enable the USART Parity Error and USART Data Register not empty Interrupts */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } /* Enable the USART Transmit Data Register Empty Interrupt */ SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); @@ -1378,6 +1455,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint } } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Send an amount of data in DMA mode. * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), @@ -1388,10 +1466,10 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint * @param Size amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) { HAL_StatusTypeDef status = HAL_OK; - uint32_t *tmp; + const uint32_t *tmp; uint16_t nbByte = Size; if (husart->State == HAL_USART_STATE_READY) @@ -1429,7 +1507,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p nbByte = Size * 2U; } - tmp = (uint32_t *)&pTxData; + tmp = (const uint32_t *)&pTxData; /* Check linked list mode */ if ((husart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) @@ -1440,7 +1518,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; /* Set DMA source address */ - husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = *(uint32_t *)tmp; + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = *(const uint32_t *)tmp; /* Set DMA destination address */ husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = @@ -1458,7 +1536,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p else { /* Enable the USART transmit DMA channel */ - status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, nbByte); + status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, nbByte); } } @@ -1633,8 +1711,11 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /* Process Unlocked */ __HAL_UNLOCK(husart); - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); @@ -1689,11 +1770,11 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR * @param Size amount of data elements (u8 or u16) to be received/sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { HAL_StatusTypeDef status; - uint32_t *tmp; + const uint32_t *tmp; uint16_t nbByte = Size; if (husart->State == HAL_USART_STATE_READY) @@ -1755,7 +1836,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin (uint32_t)&husart->Instance->RDR; /* Set DMA destination address */ - husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = *(uint32_t *)tmp; + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = *(const uint32_t *)tmp; /* Enable the USART receive DMA channel */ status = HAL_DMAEx_List_Start_IT(husart->hdmarx); @@ -1769,13 +1850,13 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin else { /* Enable the USART receive DMA channel */ - status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, nbByte); + status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(const uint32_t *)tmp, nbByte); } /* Enable the USART transmit DMA channel */ if (status == HAL_OK) { - tmp = (uint32_t *)&pTxData; + tmp = (const uint32_t *)&pTxData; /* Check linked list mode */ if ((husart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) @@ -1786,7 +1867,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; /* Set DMA source address */ - husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = *(uint32_t *)tmp; + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = *(const uint32_t *)tmp; /* Set DMA destination address */ husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = @@ -1803,7 +1884,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin } else { - status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, nbByte); + status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, nbByte); } } } @@ -1817,8 +1898,11 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin /* Process Unlocked */ __HAL_UNLOCK(husart); - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); @@ -1879,25 +1963,63 @@ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) && (state == HAL_USART_STATE_BUSY_TX)) { - /* Disable the USART DMA Tx request */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + /* Suspend the USART DMA Tx channel : use blocking DMA Suspend API (no callback) */ + if (husart->hdmatx != NULL) + { + /* Set the USART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + husart->hdmatx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } } else if ((state == HAL_USART_STATE_BUSY_RX) || (state == HAL_USART_STATE_BUSY_TX_RX)) { - if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Set the USART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + husart->hdmarx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(husart->hdmarx) != HAL_OK) { - /* Disable the USART DMA Tx request */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } } - if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + + if (state == HAL_USART_STATE_BUSY_TX_RX) { - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + /* Set the USART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + husart->hdmatx->XferSuspendCallback = NULL; - /* Disable the USART DMA Rx request */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + if (HAL_DMAEx_Suspend(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } } else @@ -1925,8 +2047,17 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) if (state == HAL_USART_STATE_BUSY_TX) { - /* Enable the USART DMA Tx request */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + /* Resume the USART DMA Tx channel */ + if (husart->hdmatx != NULL) + { + if (HAL_DMAEx_Resume(husart->hdmatx) != HAL_OK) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_ERROR; + } + } } else if ((state == HAL_USART_STATE_BUSY_RX) || (state == HAL_USART_STATE_BUSY_TX_RX)) @@ -1935,14 +2066,38 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - /* Enable the USART DMA Rx request before the DMA Tx request */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); + /* Resume the USART DMA Rx channel */ + if (husart->hdmarx != NULL) + { + if (HAL_DMAEx_Resume(husart->hdmarx) != HAL_OK) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_ERROR; + } + } + + if (state == HAL_USART_STATE_BUSY_TX_RX) + { + /* Resume the USART DMA Tx channel */ + if (husart->hdmatx != NULL) + { + if (HAL_DMAEx_Resume(husart->hdmatx) != HAL_OK) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; - /* Enable the USART DMA Tx request */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + return HAL_ERROR; + } + } + } } else { @@ -2007,6 +2162,7 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) return HAL_OK; } +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Abort ongoing transfers (blocking mode). @@ -2027,11 +2183,15 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) USART_CR1_TCIE)); CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); - /* Disable the USART DMA Tx request if enabled */ +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the USART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */ if (husart->hdmatx != NULL) { @@ -2052,11 +2212,14 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) } } - /* Disable the USART DMA Rx request if enabled */ + /* Abort the USART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Rx request if enabled */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */ if (husart->hdmarx != NULL) { @@ -2076,6 +2239,7 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) } } } +#endif /* HAL_DMA_MODULE_ENABLED */ /* Reset Tx and Rx transfer counters */ husart->TxXferCount = 0U; @@ -2125,6 +2289,7 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) USART_CR1_TCIE)); CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); +#if defined(HAL_DMA_MODULE_ENABLED) /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ /* DMA Tx Handle is valid */ @@ -2156,12 +2321,14 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) } } - /* Disable the USART DMA Tx request if enabled */ + /* Abort the USART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable DMA Tx at USART level */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */ if (husart->hdmatx != NULL) { @@ -2180,11 +2347,14 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) } } - /* Disable the USART DMA Rx request if enabled */ + /* Abort the USART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Rx request if enabled */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */ if (husart->hdmarx != NULL) { @@ -2203,6 +2373,7 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) } } } +#endif /* HAL_DMA_MODULE_ENABLED */ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ if (abortcplt == 1U) @@ -2362,11 +2533,15 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) Disable Interrupts, and disable DMA requests, if ongoing */ USART_EndTransfer(husart); - /* Disable the USART DMA Rx request if enabled */ +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the USART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Rx request if enabled */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Abort the USART DMA Tx channel */ if (husart->hdmatx != NULL) { @@ -2405,6 +2580,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) } } else +#endif /* HAL_DMA_MODULE_ENABLED */ { /* Call user error callback */ #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) @@ -2613,7 +2789,7 @@ __weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart) * the configuration information for the specified USART. * @retval USART handle state */ -HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart) { return husart->State; } @@ -2624,7 +2800,7 @@ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) * the configuration information for the specified USART. * @retval USART handle Error Code */ -uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart) { return husart->ErrorCode; } @@ -2678,6 +2854,7 @@ static void USART_EndTransfer(USART_HandleTypeDef *husart) husart->State = HAL_USART_STATE_READY; } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief DMA USART transmit process complete callback. * @param hdma DMA handle. @@ -2694,10 +2871,12 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) if (husart->State == HAL_USART_STATE_BUSY_TX) { +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the USART CR3 register */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); +#endif /* !USART_DMAREQUESTS_SW_WA */ /* Enable the USART Transmit Complete Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_TC); } @@ -2754,6 +2933,7 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit in USART CR3 register */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); @@ -2761,6 +2941,7 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) clock to the slave device */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); +#endif /* !USART_DMAREQUESTS_SW_WA */ if (husart->State == HAL_USART_STATE_BUSY_RX) { #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) @@ -2969,12 +3150,14 @@ static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } +#endif /* HAL_DMA_MODULE_ENABLED */ /** - * @brief Handle USART Communication Timeout. + * @brief Handle USART Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param husart USART handle. * @param Flag Specifies the USART flag to check. - * @param Status the Flag status (SET or RESET). + * @param Status the actual Flag status (SET or RESET). * @param Tickstart Tick start value * @param Timeout timeout duration. * @retval HAL status @@ -3199,7 +3382,7 @@ static void USART_TxISR_8BIT(USART_HandleTypeDef *husart) static void USART_TxISR_16BIT(USART_HandleTypeDef *husart) { const HAL_USART_StateTypeDef state = husart->State; - uint16_t *tmp; + const uint16_t *tmp; if ((state == HAL_USART_STATE_BUSY_TX) || (state == HAL_USART_STATE_BUSY_TX_RX)) @@ -3214,7 +3397,7 @@ static void USART_TxISR_16BIT(USART_HandleTypeDef *husart) } else { - tmp = (uint16_t *) husart->pTxBuffPtr; + tmp = (const uint16_t *) husart->pTxBuffPtr; husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); husart->pTxBuffPtr += 2U; husart->TxXferCount--; @@ -3280,7 +3463,7 @@ static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) { const HAL_USART_StateTypeDef state = husart->State; - uint16_t *tmp; + const uint16_t *tmp; uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ @@ -3301,7 +3484,7 @@ static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) } else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET) { - tmp = (uint16_t *) husart->pTxBuffPtr; + tmp = (const uint16_t *) husart->pTxBuffPtr; husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); husart->pTxBuffPtr += 2U; husart->TxXferCount--; @@ -3832,3 +4015,4 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) /** * @} */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_usart.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_usart.h index 51b241afced..3607e4f3df5 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_usart.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_usart.h @@ -124,7 +124,7 @@ typedef struct __USART_HandleTypeDef USART_InitTypeDef Init; /*!< USART communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */ uint16_t TxXferSize; /*!< USART Tx Transfer size */ @@ -152,10 +152,12 @@ typedef struct __USART_HandleTypeDef void (*TxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Tx IRQ handler */ +#if defined(HAL_DMA_MODULE_ENABLED) DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */ DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */ +#endif /* HAL_DMA_MODULE_ENABLED */ HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_USART_StateTypeDef State; /*!< USART communication state */ @@ -224,7 +226,9 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin #define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */ #define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */ #define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#if defined(HAL_DMA_MODULE_ENABLED) #define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#endif /* HAL_DMA_MODULE_ENABLED */ #define HAL_USART_ERROR_UDR (0x00000020U) /*!< SPI slave underrun error */ #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) #define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ @@ -814,7 +818,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) -#else +#elif defined(USART2) #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ @@ -885,6 +889,56 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) +#else +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) #endif /* USART6 */ /** @brief Check USART Baud rate. @@ -1014,21 +1068,24 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart); +#endif /* HAL_DMA_MODULE_ENABLED */ /* Transfer Abort functions */ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart); @@ -1051,8 +1108,8 @@ void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart); */ /* Peripheral State and Error functions ***************************************/ -HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart); -uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart); +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart); /** * @} @@ -1075,3 +1132,4 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); #endif #endif /* STM32U5xx_HAL_USART_H */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_usart_ex.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_usart_ex.c index f641ee9ac0b..2853a14e5a5 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_usart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_usart_ex.c @@ -36,6 +36,7 @@ starting RX/TX transfers. @endverbatim + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -483,7 +484,7 @@ HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, ui * @retval HAL status */ HAL_StatusTypeDef HAL_USARTEx_SetConfigAutonomousMode(USART_HandleTypeDef *husart, - USART_AutonomousModeConfTypeDef *sConfig) + const USART_AutonomousModeConfTypeDef *sConfig) { uint32_t tmpreg; @@ -538,7 +539,7 @@ HAL_StatusTypeDef HAL_USARTEx_SetConfigAutonomousMode(USART_HandleTypeDef *husar * @param sConfig Autonomous mode structure parameters. * @retval HAL status */ -HAL_StatusTypeDef HAL_USARTEx_GetConfigAutonomousMode(USART_HandleTypeDef *husart, +HAL_StatusTypeDef HAL_USARTEx_GetConfigAutonomousMode(const USART_HandleTypeDef *husart, USART_AutonomousModeConfTypeDef *sConfig) { uint32_t tmpreg; @@ -653,3 +654,4 @@ static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) /** * @} */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_usart_ex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_usart_ex.h index de0480fb4a7..de4cc6705fe 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_usart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_usart_ex.h @@ -365,8 +365,8 @@ HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold); HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold); HAL_StatusTypeDef HAL_USARTEx_SetConfigAutonomousMode(USART_HandleTypeDef *husart, - USART_AutonomousModeConfTypeDef *sConfig); -HAL_StatusTypeDef HAL_USARTEx_GetConfigAutonomousMode(USART_HandleTypeDef *husart, + const USART_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_USARTEx_GetConfigAutonomousMode(const USART_HandleTypeDef *husart, USART_AutonomousModeConfTypeDef *sConfig); HAL_StatusTypeDef HAL_USARTEx_ClearConfigAutonomousMode(USART_HandleTypeDef *husart); @@ -391,3 +391,4 @@ HAL_StatusTypeDef HAL_USARTEx_ClearConfigAutonomousMode(USART_HandleTypeDef *hus #endif #endif /* STM32U5xx_HAL_USART_EX_H */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_xspi.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_xspi.c new file mode 100644 index 00000000000..65e7f946cac --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_xspi.c @@ -0,0 +1,3911 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_xspi.c + * @author MCD Application Team + * @brief XSPI HAL module driver. + This file provides firmware functions to manage the following + functionalities of the OctoSPI/HSPI interface (XSPI). + + Initialization and de-initialization functions + + Hyperbus configuration + + Indirect functional mode management + + Memory-mapped functional mode management + + Auto-polling functional mode management + + Interrupts and flags management + + DMA channel configuration for indirect functional mode + + Errors management and abort functionality + + IO manager configuration (if available) + + Delay block configuration + + HIGH-SPEED INTERFACE configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + *** Initialization *** + ====================== + [..] + As prerequisite, fill in the HAL_XSPI_MspInit() : + (+) Enable OctoSPI/HSPI clocks interface with __HAL_RCC_XSPI_CLK_ENABLE(). + (+) Reset OctoSPI/HSPI Peripheral with __HAL_RCC_XSPI_FORCE_RESET() and __HAL_RCC_XSPI_RELEASE_RESET(). + (+) Enable the clocks for the OctoSPI/HSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). + (+) Configure these OctoSPI/HSPI pins in alternate mode using HAL_GPIO_Init(). + (+) If interrupt or DMA mode is used, enable and configure OctoSPI/HSPI global + interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + (+) If DMA mode is used, enable the clocks for the OctoSPI/HSPI DMA channel + with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), + link it with OctoSPI/HSPI handle using __HAL_LINKDMA(), enable and configure + DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + [..] + Configure the fifo threshold, the memory mode, the memory type, the + device size, the CS high time, the free running clock, the clock mode, + the wrap size, the clock prescaler, the sample shifting, the hold delay + and the CS boundary using the HAL_XSPI_Init() function. + [..] + When using Hyperbus, configure the RW recovery time, the access time, + the write latency and the latency mode using the HAL_XSPI_HyperbusCfg() + function. + + *** Indirect functional mode *** + ================================ + [..] + In regular mode, configure the command sequence using the HAL_XSPI_Command() + or HAL_XSPI_Command_IT() functions : + (+) Instruction phase : the mode used and if present the size, the instruction + opcode and the DTR mode. + (+) Address phase : the mode used and if present the size, the address + value and the DTR mode. + (+) Alternate-bytes phase : the mode used and if present the size, the + alternate bytes values and the DTR mode. + (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). + (+) Data phase : the mode used and if present the number of bytes and the DTR mode. + (+) Data strobe (DQS) mode : the activation (or not) of this mode + (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. + (+) IO selection : to access external memory. + (+) Operation type : always common configuration. + [..] + In Hyperbus mode, configure the command sequence using the HAL_XSPI_HyperbusCmd() + function : + (+) Address space : indicate if the access will be done in register or memory + (+) Address size + (+) Number of data + (+) Data strobe (DQS) mode : the activation (or not) of this mode + [..] + If no data is required for the command (only for regular mode, not for + Hyperbus mode), it is sent directly to the memory : + (+) In polling mode, the output of the function is done when the transfer is complete. + (+) In interrupt mode, HAL_XSPI_CmdCpltCallback() will be called when the transfer is complete. + [..] + For the indirect write mode, use HAL_XSPI_Transmit(), HAL_XSPI_Transmit_DMA() or + HAL_XSPI_Transmit_IT() after the command configuration : + (+) In polling mode, the output of the function is done when the transfer is complete. + (+) In interrupt mode, HAL_XSPI_FifoThresholdCallback() will be called when the fifo threshold + is reached and HAL_XSPI_TxCpltCallback() will be called when the transfer is complete. + (+) In DMA mode, HAL_XSPI_TxHalfCpltCallback() will be called at the half transfer and + HAL_XSPI_TxCpltCallback() will be called when the transfer is complete. + [..] + For the indirect read mode, use HAL_XSPI_Receive(), HAL_XSPI_Receive_DMA() or + HAL_XSPI_Receive_IT() after the command configuration : + (+) In polling mode, the output of the function is done when the transfer is complete. + (+) In interrupt mode, HAL_XSPI_FifoThresholdCallback() will be called when the fifo threshold + is reached and HAL_XSPI_RxCpltCallback() will be called when the transfer is complete. + (+) In DMA mode, HAL_XSPI_RxHalfCpltCallback() will be called at the half transfer and + HAL_XSPI_RxCpltCallback() will be called when the transfer is complete. + + *** Auto-polling functional mode *** + ==================================== + [..] + Configure the command sequence by the same way than the indirect mode + [..] + Configure the auto-polling functional mode using the HAL_XSPI_AutoPolling() + or HAL_XSPI_AutoPolling_IT() functions : + (+) The size of the status bytes, the match value, the mask used, the match mode (OR/AND), + the polling interval and the automatic stop activation. + [..] + After the configuration : + (+) In polling mode, the output of the function is done when the status match is reached. The + automatic stop is activated to avoid an infinite loop. + (+) In interrupt mode, HAL_XSPI_StatusMatchCallback() will be called each time the status match is reached. + + *** Memory-mapped functional mode *** + ===================================== + [..] + Configure the command sequence by the same way than the indirect mode except + for the operation type in regular mode : + (+) Operation type equals to read configuration : the command configuration + applies to read access in memory-mapped mode + (+) Operation type equals to write configuration : the command configuration + applies to write access in memory-mapped mode + (+) Both read and write configuration should be performed before activating + memory-mapped mode + [..] + Configure the memory-mapped functional mode using the HAL_XSPI_MemoryMapped() + functions : + (+) The timeout activation and the timeout period. + [..] + After the configuration, the OctoSPI/HSPI will be used as soon as an access on the AHB is done on + the address range. HAL_XSPI_TimeOutCallback() will be called when the timeout expires. + + *** Errors management and abort functionality *** + ================================================= + [..] + HAL_XSPI_GetError() function gives the error raised during the last operation. + [..] + HAL_XSPI_Abort() and HAL_XSPI_AbortIT() functions aborts any on-going operation and + flushes the fifo : + (+) In polling mode, the output of the function is done when the transfer + complete bit is set and the busy bit cleared. + (+) In interrupt mode, HAL_XSPI_AbortCpltCallback() will be called when + the transfer complete bit is set. + + *** Control functions *** + ========================= + [..] + HAL_XSPI_GetState() function gives the current state of the HAL XSPI driver. + [..] + HAL_XSPI_SetTimeout() function configures the timeout value used in the driver. + [..] + HAL_XSPI_SetFifoThreshold() function configures the threshold on the Fifo of the OctoSPI/HSPI Peripheral. + [..] + HAL_XSPI_SetMemoryType() function configures the type of the external memory. + [..] + HAL_XSPI_SetDeviceSize() function configures the size of the external memory. + [..] + HAL_XSPI_SetClockPrescaler() function configures the clock prescaler of the OctoSPI/HSPI Peripheral. + [..] + HAL_XSPI_GetFifoThreshold() function gives the current of the Fifo's threshold + + *** IO manager configuration functions (if available) *** + ========================================== + [..] + HAL_XSPIM_Config() function configures the IO manager (if available) for the XSPI instance. + + *** Delay Block functions *** + ========================================== + [..] + The delay block (DLYB) is used to generate an output clock that is dephased from the input clock. + (+) The delay line length can be Configure to one period of the Input clock with HAL_XSPI_DLYB_GetClockPeriod(). + (+) The phase of the output clock can be programmed directly with HAL_XSPI_DLYB_SetConfig(). + (+) The phase of the output clock can be got with HAL_XSPI_DLYB_GetConfig(). + [..] + + *** High-speed interface and calibration functions *** + ========================================== + [..] + The purpose of High-speed interface is primary to shift data or data strobe by one quarter of octal + bus clock period, with a correct timing accuracy. DLL must be calibrated versus this clock period. + The calibration process is automatically enabled when one of the three conditions below is met: + (+) The HSPI exits Reset state. + (+) The Prescaler is set. + (+) The configuration of communication is set. + [..] + HAL_XSPI_GetDelayValue() function Get the delay values of the high-speed interface DLLs.. + [..] + HAL_XSPI_SetDelayValue() function Set the delay values of the high-speed interface DLLs.. + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_XSPI_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use function HAL_XSPI_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) FifoThresholdCallback : callback when the fifo threshold is reached. + (+) CmdCpltCallback : callback when a command without data is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxHalfCpltCallback : callback when half of the reception transfer is completed. + (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed. + (+) StatusMatchCallback : callback when a status match occurs. + (+) TimeOutCallback : callback when the timeout perioed expires. + (+) MspInitCallback : XSPI MspInit. + (+) MspDeInitCallback : XSPI MspDeInit. + [..] + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_XSPI_UnRegisterCallback() to reset a callback to the default + weak (overridden) function. It allows to reset following callbacks: + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) FifoThresholdCallback : callback when the fifo threshold is reached. + (+) CmdCpltCallback : callback when a command without data is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxHalfCpltCallback : callback when half of the reception transfer is completed. + (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed. + (+) StatusMatchCallback : callback when a status match occurs. + (+) TimeOutCallback : callback when the timeout perioed expires. + (+) MspInitCallback : XSPI MspInit. + (+) MspDeInitCallback : XSPI MspDeInit. + [..] + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + [..] + By default, after the HAL_XSPI_Init() and if the state is HAL_XSPI_STATE_RESET + all callbacks are reset to the corresponding legacy weak (overridden) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (overridden) functions in the HAL_XSPI_Init() + and HAL_XSPI_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_XSPI_Init() and HAL_XSPI_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + [..] + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_XSPI_RegisterCallback() before calling HAL_XSPI_DeInit() + or HAL_XSPI_Init() function. + + [..] + When The compilation define USE_HAL_XSPI_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (overridden) callbacks are used. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal.h" + +#if defined(HSPI) || defined(HSPI1) || defined(HSPI2)|| defined(OCTOSPI) || defined(OCTOSPI1)|| defined(OCTOSPI2) + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @defgroup XSPI XSPI + * @brief XSPI HAL module driver + * @{ + */ + +#ifdef HAL_XSPI_MODULE_ENABLED + +/** + @cond 0 + */ +/* Private typedef -----------------------------------------------------------*/ + +/* Private define ------------------------------------------------------------*/ +#define XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!< Indirect write mode */ +#define XSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)XSPI_CR_FMODE_0) /*!< Indirect read mode */ +#define XSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)XSPI_CR_FMODE_1) /*!< Automatic polling mode */ +#define XSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)XSPI_CR_FMODE) /*!< Memory-mapped mode */ + +#define XSPI_CFG_STATE_MASK 0x00000004U +#define XSPI_BUSY_STATE_MASK 0x00000008U + +#if defined(OCTOSPIM) +#define OSPI_NB_INSTANCE 2U +#define OSPI_IOM_NB_PORTS 2U +#define OSPI_IOM_PORT_MASK 0x1U + +#endif /* OCTOSPIM */ +/* Private macro -------------------------------------------------------------*/ +#define IS_XSPI_FUNCTIONAL_MODE(MODE) (((MODE) == XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \ + ((MODE) == XSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \ + ((MODE) == XSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \ + ((MODE) == XSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)) + +/* Private variables ---------------------------------------------------------*/ + +/* Private function prototypes -----------------------------------------------*/ +static void XSPI_DMACplt(DMA_HandleTypeDef *hdma); +static void XSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma); +static void XSPI_DMAError(DMA_HandleTypeDef *hdma); +static void XSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef XSPI_WaitFlagStateUntilTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Flag, FlagStatus State, + uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd); +#if defined(OCTOSPIM) +static void XSPIM_GetConfig(uint8_t instance_nb, XSPIM_CfgTypeDef *const pCfg); +#endif /* OCTOSPIM */ +/** + @endcond + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup XSPI_Exported_Functions XSPI Exported Functions + * @{ + */ + +/** @defgroup XSPI_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Initialize the XSPI. + (+) De-initialize the XSPI. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the XSPI mode according to the specified parameters + * in the XSPI_InitTypeDef and initialize the associated handle. + * @param hxspi : XSPI handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Init(XSPI_HandleTypeDef *hxspi) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + + /* Check the XSPI handle allocation */ + if (hxspi == NULL) + { + status = HAL_ERROR; + /* No error code can be set set as the handler is null */ + } + else + { + /* Check the parameters of the initialization structure */ + assert_param(IS_XSPI_MEMORY_MODE(hxspi->Init.MemoryMode)); + assert_param(IS_XSPI_MEMORY_TYPE(hxspi->Init.MemoryType)); + assert_param(IS_XSPI_MEMORY_SIZE(hxspi->Init.MemorySize)); + assert_param(IS_XSPI_CS_HIGH_TIME_CYCLE(hxspi->Init.ChipSelectHighTimeCycle)); + assert_param(IS_XSPI_FREE_RUN_CLK(hxspi->Init.FreeRunningClock)); + assert_param(IS_XSPI_CLOCK_MODE(hxspi->Init.ClockMode)); + assert_param(IS_XSPI_WRAP_SIZE(hxspi->Init.WrapSize)); + assert_param(IS_XSPI_CLK_PRESCALER(hxspi->Init.ClockPrescaler)); + assert_param(IS_XSPI_SAMPLE_SHIFTING(hxspi->Init.SampleShifting)); + assert_param(IS_XSPI_DHQC(hxspi->Init.DelayHoldQuarterCycle)); + assert_param(IS_XSPI_CS_BOUND(hxspi->Init.ChipSelectBoundary)); + if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) + { + assert_param(IS_OCTOSPI_FIFO_THRESHOLD_BYTE(hxspi->Init.FifoThresholdByte)); + } +#if defined(HSPI1) + if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) + { + assert_param(IS_HSPI_FIFO_THRESHOLD_BYTE(hxspi->Init.FifoThresholdByte)); + } +#endif /* HSPI1 */ + if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) + { + assert_param(IS_XSPI_DLYB_BYPASS(hxspi->Init.DelayBlockBypass)); + } + if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) + { + assert_param(IS_XSPI_MAXTRAN(hxspi->Init.MaxTran)); + } + /* Initialize error code */ + hxspi->ErrorCode = HAL_XSPI_ERROR_NONE; + + /* Check if the state is the reset state */ + if (hxspi->State == HAL_XSPI_STATE_RESET) + { +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + /* Reset Callback pointers in HAL_XSPI_STATE_RESET only */ + hxspi->ErrorCallback = HAL_XSPI_ErrorCallback; + hxspi->AbortCpltCallback = HAL_XSPI_AbortCpltCallback; + hxspi->FifoThresholdCallback = HAL_XSPI_FifoThresholdCallback; + hxspi->CmdCpltCallback = HAL_XSPI_CmdCpltCallback; + hxspi->RxCpltCallback = HAL_XSPI_RxCpltCallback; + hxspi->TxCpltCallback = HAL_XSPI_TxCpltCallback; + hxspi->RxHalfCpltCallback = HAL_XSPI_RxHalfCpltCallback; + hxspi->TxHalfCpltCallback = HAL_XSPI_TxHalfCpltCallback; + hxspi->StatusMatchCallback = HAL_XSPI_StatusMatchCallback; + hxspi->TimeOutCallback = HAL_XSPI_TimeOutCallback; + + if (hxspi->MspInitCallback == NULL) + { + hxspi->MspInitCallback = HAL_XSPI_MspInit; + } + + /* Init the low level hardware */ + hxspi->MspInitCallback(hxspi); +#else + /* Initialization of the low level hardware */ + HAL_XSPI_MspInit(hxspi); +#endif /* defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + + /* Configure the default timeout for the XSPI memory access */ + (void)HAL_XSPI_SetTimeout(hxspi, HAL_XSPI_TIMEOUT_DEFAULT_VALUE); + + /* Configure memory type, device size, chip select high time, free running clock, clock mode */ + MODIFY_REG(hxspi->Instance->DCR1, + (XSPI_DCR1_MTYP | XSPI_DCR1_DEVSIZE | XSPI_DCR1_CSHT | XSPI_DCR1_FRCK | XSPI_DCR1_CKMODE), + (hxspi->Init.MemoryType | ((hxspi->Init.MemorySize) << XSPI_DCR1_DEVSIZE_Pos) | + ((hxspi->Init.ChipSelectHighTimeCycle - 1U) << XSPI_DCR1_CSHT_Pos) | hxspi->Init.ClockMode)); + + /* Configure delay block bypass */ + if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) + { + MODIFY_REG(hxspi->Instance->DCR1, OCTOSPI_DCR1_DLYBYP, hxspi->Init.DelayBlockBypass); + } + + /* Configure wrap size */ + MODIFY_REG(hxspi->Instance->DCR2, XSPI_DCR2_WRAPSIZE, hxspi->Init.WrapSize); + + /* Configure chip select boundary */ + MODIFY_REG(hxspi->Instance->DCR3, XSPI_DCR3_CSBOUND, (hxspi->Init.ChipSelectBoundary << XSPI_DCR3_CSBOUND_Pos)); + + /* Configure maximum transfer */ + if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) + { + MODIFY_REG(hxspi->Instance->DCR3, OCTOSPI_DCR3_MAXTRAN, (hxspi->Init.MaxTran << OCTOSPI_DCR3_MAXTRAN_Pos)); + } + + /* Configure refresh */ + hxspi->Instance->DCR4 = hxspi->Init.Refresh; + + /* Configure FIFO threshold */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FTHRES, ((hxspi->Init.FifoThresholdByte - 1U) << XSPI_CR_FTHRES_Pos)); + + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout); + + if (status == HAL_OK) + { + /* Configure clock prescaler */ + MODIFY_REG(hxspi->Instance->DCR2, XSPI_DCR2_PRESCALER, + ((hxspi->Init.ClockPrescaler) << XSPI_DCR2_PRESCALER_Pos)); + +#if defined(HSPI_CALFCR_FINE) + if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) + { + /* The configuration of clock prescaler trigger automatically a calibration process. + So it is necessary to wait the calibration is complete */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout); + if (status != HAL_OK) + { + return status; + } + } +#endif /* HSPI_CALFCR_FINE */ + /* Configure Dual Memory mode */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_DMM, hxspi->Init.MemoryMode); + + /* Configure sample shifting and delay hold quarter cycle */ + MODIFY_REG(hxspi->Instance->TCR, (XSPI_TCR_SSHIFT | XSPI_TCR_DHQC), + (hxspi->Init.SampleShifting | hxspi->Init.DelayHoldQuarterCycle)); + + /* Enable XSPI */ + HAL_XSPI_ENABLE(hxspi); + + /* Enable free running clock if needed : must be done after XSPI enable */ + if (hxspi->Init.FreeRunningClock == HAL_XSPI_FREERUNCLK_ENABLE) + { + SET_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); + } + + /* Initialize the XSPI state */ + if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) + { + hxspi->State = HAL_XSPI_STATE_HYPERBUS_INIT; + } + else + { + hxspi->State = HAL_XSPI_STATE_READY; + } + } + } + } + return status; +} + +/** + * @brief Initialize the XSPI MSP. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_MspInit(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_XSPI_MspInit can be implemented in the user file + */ +} + +/** + * @brief De-Initialize the XSPI peripheral. + * @param hxspi : XSPI handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_DeInit(XSPI_HandleTypeDef *hxspi) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the XSPI handle allocation */ + if (hxspi == NULL) + { + status = HAL_ERROR; + /* No error code can be set as the handler is null */ + } + else + { + /* Disable XSPI */ + HAL_XSPI_DISABLE(hxspi); + + /* Disable free running clock if needed : must be done after XSPI disable */ + CLEAR_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); + +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + if (hxspi->MspDeInitCallback == NULL) + { + hxspi->MspDeInitCallback = HAL_XSPI_MspDeInit; + } + + /* De-initialize the low level hardware */ + hxspi->MspDeInitCallback(hxspi); +#else + /* De-initialize the low-level hardware */ + HAL_XSPI_MspDeInit(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + + /* Reset the driver state */ + hxspi->State = HAL_XSPI_STATE_RESET; + } + + return status; +} + +/** + * @brief DeInitialize the XSPI MSP. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_MspDeInit(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_XSPI_MspDeInit can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup XSPI_Exported_Functions_Group2 Input and Output operation functions + * @brief XSPI Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Handle the interrupts. + (+) Handle the command sequence (regular and Hyperbus). + (+) Handle the Hyperbus configuration. + (+) Transmit data in blocking, interrupt or DMA mode. + (+) Receive data in blocking, interrupt or DMA mode. + (+) Manage the auto-polling functional mode. + (+) Manage the memory-mapped functional mode. + +@endverbatim + * @{ + */ + +/** + * @brief Handle XSPI interrupt request. + * @param hxspi : XSPI handle + * @retval None + */ +void HAL_XSPI_IRQHandler(XSPI_HandleTypeDef *hxspi) +{ + __IO uint32_t *data_reg = &hxspi->Instance->DR; + uint32_t flag = hxspi->Instance->SR; + uint32_t itsource = hxspi->Instance->CR; + uint32_t currentstate = hxspi->State; + + /* XSPI fifo threshold interrupt occurred -------------------------------*/ + if (((flag & HAL_XSPI_FLAG_FT) != 0U) && ((itsource & HAL_XSPI_IT_FT) != 0U)) + { + if (currentstate == HAL_XSPI_STATE_BUSY_TX) + { + /* Write a data in the fifo */ + *((__IO uint8_t *)data_reg) = *hxspi->pBuffPtr; + hxspi->pBuffPtr++; + hxspi->XferCount--; + } + else if (currentstate == HAL_XSPI_STATE_BUSY_RX) + { + /* Read a data from the fifo */ + *hxspi->pBuffPtr = *((__IO uint8_t *)data_reg); + hxspi->pBuffPtr++; + hxspi->XferCount--; + } + else + { + /* Nothing to do */ + } + + if (hxspi->XferCount == 0U) + { + /* All data have been received or transmitted for the transfer */ + /* Disable fifo threshold interrupt */ + HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_FT); + } + + /* Fifo threshold callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->FifoThresholdCallback(hxspi); +#else + HAL_XSPI_FifoThresholdCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + /* XSPI transfer complete interrupt occurred ----------------------------*/ + else if (((flag & HAL_XSPI_FLAG_TC) != 0U) && ((itsource & HAL_XSPI_IT_TC) != 0U)) + { + if (currentstate == HAL_XSPI_STATE_BUSY_RX) + { + if ((hxspi->XferCount > 0U) && ((flag & XSPI_SR_FLEVEL) != 0U)) + { + /* Read the last data received in the fifo */ + *hxspi->pBuffPtr = *((__IO uint8_t *)data_reg); + hxspi->pBuffPtr++; + hxspi->XferCount--; + } + else if (hxspi->XferCount == 0U) + { + /* Clear flag */ + hxspi->Instance->FCR = HAL_XSPI_FLAG_TC; + + /* Disable the interrupts */ + HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); + + hxspi->State = HAL_XSPI_STATE_READY; + + /* RX complete callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->RxCpltCallback(hxspi); +#else + HAL_XSPI_RxCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + else + { + /* Nothing to do */ + } + } + else + { + /* Clear flag */ + hxspi->Instance->FCR = HAL_XSPI_FLAG_TC; + + /* Disable the interrupts */ + HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); + + hxspi->State = HAL_XSPI_STATE_READY; + + if (currentstate == HAL_XSPI_STATE_BUSY_TX) + { + /* TX complete callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->TxCpltCallback(hxspi); +#else + HAL_XSPI_TxCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + else if (currentstate == HAL_XSPI_STATE_BUSY_CMD) + { + /* Command complete callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->CmdCpltCallback(hxspi); +#else + HAL_XSPI_CmdCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + else if (currentstate == HAL_XSPI_STATE_ABORT) + { + if (hxspi->ErrorCode == HAL_XSPI_ERROR_NONE) + { + /* Abort called by the user */ + /* Abort complete callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->AbortCpltCallback(hxspi); +#else + HAL_XSPI_AbortCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + else + { + /* Abort due to an error (eg : DMA error) */ + /* Error callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->ErrorCallback(hxspi); +#else + HAL_XSPI_ErrorCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + } + else + { + /* Nothing to do */ + } + } + } + /* XSPI status match interrupt occurred ---------------------------------*/ + else if (((flag & HAL_XSPI_FLAG_SM) != 0U) && ((itsource & HAL_XSPI_IT_SM) != 0U)) + { + /* Clear flag */ + hxspi->Instance->FCR = HAL_XSPI_FLAG_SM; + + /* Check if automatic poll mode stop is activated */ + if ((hxspi->Instance->CR & XSPI_CR_APMS) != 0U) + { + /* Disable the interrupts */ + HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_SM | HAL_XSPI_IT_TE); + + hxspi->State = HAL_XSPI_STATE_READY; + } + + /* Status match callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->StatusMatchCallback(hxspi); +#else + HAL_XSPI_StatusMatchCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + /* XSPI transfer error interrupt occurred -------------------------------*/ + else if (((flag & HAL_XSPI_FLAG_TE) != 0U) && ((itsource & HAL_XSPI_IT_TE) != 0U)) + { + /* Clear flag */ + hxspi->Instance->FCR = HAL_XSPI_FLAG_TE; + + /* Disable all interrupts */ + HAL_XSPI_DISABLE_IT(hxspi, (HAL_XSPI_IT_TO | HAL_XSPI_IT_SM | HAL_XSPI_IT_FT | HAL_XSPI_IT_TC | HAL_XSPI_IT_TE)); + + /* Set error code */ + hxspi->ErrorCode = HAL_XSPI_ERROR_TRANSFER; + + /* Check if the DMA is enabled */ + if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) + { + /* Disable the DMA transfer on the XSPI side */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); + + /* Disable the DMA transmit on the DMA side */ + hxspi->hdmatx->XferAbortCallback = XSPI_DMAAbortCplt; + if (HAL_DMA_Abort_IT(hxspi->hdmatx) != HAL_OK) + { + hxspi->State = HAL_XSPI_STATE_READY; + + /* Error callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->ErrorCallback(hxspi); +#else + HAL_XSPI_ErrorCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + + /* Disable the DMA receive on the DMA side */ + hxspi->hdmarx->XferAbortCallback = XSPI_DMAAbortCplt; + if (HAL_DMA_Abort_IT(hxspi->hdmarx) != HAL_OK) + { + hxspi->State = HAL_XSPI_STATE_READY; + + /* Error callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->ErrorCallback(hxspi); +#else + HAL_XSPI_ErrorCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + } + else + { + hxspi->State = HAL_XSPI_STATE_READY; + + /* Error callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->ErrorCallback(hxspi); +#else + HAL_XSPI_ErrorCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + } + /* XSPI timeout interrupt occurred --------------------------------------*/ + else if (((flag & HAL_XSPI_FLAG_TO) != 0U) && ((itsource & HAL_XSPI_IT_TO) != 0U)) + { + /* Clear flag */ + hxspi->Instance->FCR = HAL_XSPI_FLAG_TO; + + /* Timeout callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->TimeOutCallback(hxspi); +#else + HAL_XSPI_TimeOutCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief Set the command configuration. + * @param hxspi : XSPI handle + * @param pCmd : structure that contains the command configuration information + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd, uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t state; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the command structure */ + assert_param(IS_XSPI_OPERATION_TYPE(pCmd->OperationType)); + if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM) + { + if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) + { + assert_param(IS_OCTOSPI_IO_SELECT(pCmd->IOSelect)); + } +#if defined(HSPI1) + else if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) + { + assert_param(IS_HSPI_IO_SELECT(pCmd->IOSelect)); + } +#endif /* HSPI1 */ + else + { + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + } + + assert_param(IS_XSPI_INSTRUCTION_MODE(pCmd->InstructionMode)); + if (pCmd->InstructionMode != HAL_XSPI_INSTRUCTION_NONE) + { + assert_param(IS_XSPI_INSTRUCTION_WIDTH(pCmd->InstructionWidth)); + assert_param(IS_XSPI_INSTRUCTION_DTR_MODE(pCmd->InstructionDTRMode)); + } + + assert_param(IS_XSPI_ADDRESS_MODE(pCmd->AddressMode)); + if (pCmd->AddressMode != HAL_XSPI_ADDRESS_NONE) + { + assert_param(IS_XSPI_ADDRESS_WIDTH(pCmd->AddressWidth)); + assert_param(IS_XSPI_ADDRESS_DTR_MODE(pCmd->AddressDTRMode)); + } + + assert_param(IS_XSPI_ALT_BYTES_MODE(pCmd->AlternateBytesMode)); + if (pCmd->AlternateBytesMode != HAL_XSPI_ALT_BYTES_NONE) + { + assert_param(IS_XSPI_ALT_BYTES_WIDTH(pCmd->AlternateBytesWidth)); + assert_param(IS_XSPI_ALT_BYTES_DTR_MODE(pCmd->AlternateBytesDTRMode)); + } + + if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) + { + assert_param(IS_OCTOSPI_DATA_MODE(pCmd->DataMode)); + } +#if defined(HSPI1) + else if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) + { + assert_param(IS_HSPI_DATA_MODE(hxspi->Init.MemoryType, pCmd->DataMode)); + } +#endif /* HSPI1 */ + else + { + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) + { + assert_param(IS_XSPI_DATA_LENGTH(pCmd->DataLength)); + } + assert_param(IS_XSPI_DATA_DTR_MODE(pCmd->DataDTRMode)); + assert_param(IS_XSPI_DUMMY_CYCLES(pCmd->DummyCycles)); + } + + assert_param(IS_XSPI_DQS_MODE(pCmd->DQSMode)); + assert_param(IS_XSPI_SIOO_MODE(pCmd->SIOOMode)); + + /* Check the state of the driver */ + state = hxspi->State; + if (((state == HAL_XSPI_STATE_READY) && (hxspi->Init.MemoryType != HAL_XSPI_MEMTYPE_HYPERBUS)) || + ((state == HAL_XSPI_STATE_READ_CMD_CFG) && ((pCmd->OperationType == HAL_XSPI_OPTYPE_WRITE_CFG) || + (pCmd->OperationType == HAL_XSPI_OPTYPE_WRAP_CFG))) || + ((state == HAL_XSPI_STATE_WRITE_CMD_CFG) && + ((pCmd->OperationType == HAL_XSPI_OPTYPE_READ_CFG) || + (pCmd->OperationType == HAL_XSPI_OPTYPE_WRAP_CFG)))) + { + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Initialize error code */ + hxspi->ErrorCode = HAL_XSPI_ERROR_NONE; + + /* Configure the registers */ + status = XSPI_ConfigCmd(hxspi, pCmd); + + if (status == HAL_OK) + { + if (pCmd->DataMode == HAL_XSPI_DATA_NONE) + { + /* When there is no data phase, the transfer start as soon as the configuration is done + so wait until TC flag is set to go back in idle state */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout); + + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); + } + else + { + /* Update the state */ + if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) + { + hxspi->State = HAL_XSPI_STATE_CMD_CFG; + } + else if (pCmd->OperationType == HAL_XSPI_OPTYPE_READ_CFG) + { + if (hxspi->State == HAL_XSPI_STATE_WRITE_CMD_CFG) + { + hxspi->State = HAL_XSPI_STATE_CMD_CFG; + } + else + { + hxspi->State = HAL_XSPI_STATE_READ_CMD_CFG; + } + } + else if (pCmd->OperationType == HAL_XSPI_OPTYPE_WRITE_CFG) + { + if (hxspi->State == HAL_XSPI_STATE_READ_CMD_CFG) + { + hxspi->State = HAL_XSPI_STATE_CMD_CFG; + } + else + { + hxspi->State = HAL_XSPI_STATE_WRITE_CMD_CFG; + } + } + else + { + /* Wrap configuration, no state change */ + } + } + } + } + else + { + status = HAL_BUSY; + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Set the command configuration in interrupt mode. + * @param hxspi : XSPI handle + * @param pCmd : structure that contains the command configuration information + * @note This function is used only in Indirect Read or Write Modes + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the command structure */ + assert_param(IS_XSPI_OPERATION_TYPE(pCmd->OperationType)); + + if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) + { + if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM) + { + assert_param(IS_OCTOSPI_IO_SELECT(pCmd->IOSelect)); + } + } +#if defined(HSPI1) + else if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) + { + if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM) + { + assert_param(IS_HSPI_IO_SELECT(pCmd->IOSelect)); + } + } +#endif /* HSPI */ + else + { + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + assert_param(IS_XSPI_INSTRUCTION_MODE(pCmd->InstructionMode)); + if (pCmd->InstructionMode != HAL_XSPI_INSTRUCTION_NONE) + { + assert_param(IS_XSPI_INSTRUCTION_WIDTH(pCmd->InstructionWidth)); + assert_param(IS_XSPI_INSTRUCTION_DTR_MODE(pCmd->InstructionDTRMode)); + } + + assert_param(IS_XSPI_ADDRESS_MODE(pCmd->AddressMode)); + if (pCmd->AddressMode != HAL_XSPI_ADDRESS_NONE) + { + assert_param(IS_XSPI_ADDRESS_WIDTH(pCmd->AddressWidth)); + assert_param(IS_XSPI_ADDRESS_DTR_MODE(pCmd->AddressDTRMode)); + } + + assert_param(IS_XSPI_ALT_BYTES_MODE(pCmd->AlternateBytesMode)); + if (pCmd->AlternateBytesMode != HAL_XSPI_ALT_BYTES_NONE) + { + assert_param(IS_XSPI_ALT_BYTES_WIDTH(pCmd->AlternateBytesWidth)); + assert_param(IS_XSPI_ALT_BYTES_DTR_MODE(pCmd->AlternateBytesDTRMode)); + } + + if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) + { + assert_param(IS_OCTOSPI_DATA_MODE(pCmd->DataMode)); + } +#if defined(HSPI1) + else if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) + { + assert_param(IS_HSPI_DATA_MODE(hxspi->Init.MemoryType, pCmd->DataMode)); + } +#endif /* HSPI1 */ + else + { + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + assert_param(IS_XSPI_DATA_LENGTH(pCmd->DataLength)); + assert_param(IS_XSPI_DATA_DTR_MODE(pCmd->DataDTRMode)); + assert_param(IS_XSPI_DUMMY_CYCLES(pCmd->DummyCycles)); + } + + assert_param(IS_XSPI_DQS_MODE(pCmd->DQSMode)); + assert_param(IS_XSPI_SIOO_MODE(pCmd->SIOOMode)); + + /* Check the state of the driver */ + if ((hxspi->State == HAL_XSPI_STATE_READY) && (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) && + (pCmd->DataMode == HAL_XSPI_DATA_NONE) && (hxspi->Init.MemoryType != HAL_XSPI_MEMTYPE_HYPERBUS)) + { + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout); + + if (status == HAL_OK) + { + /* Initialize error code */ + hxspi->ErrorCode = HAL_XSPI_ERROR_NONE; + + /* Clear flags related to interrupt */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); + + /* Configure the registers */ + status = XSPI_ConfigCmd(hxspi, pCmd); + + if (status == HAL_OK) + { + /* Update the state */ + hxspi->State = HAL_XSPI_STATE_BUSY_CMD; + + /* Enable the transfer complete and transfer error interrupts */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_TE); + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Configure the Hyperbus parameters. + * @param hxspi : XSPI handle + * @param pCfg : Pointer to Structure containing the Hyperbus configuration + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCfgTypeDef *const pCfg, + uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t state; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the hyperbus configuration structure */ + assert_param(IS_XSPI_RW_RECOVERY_TIME_CYCLE(pCfg->RWRecoveryTimeCycle)); + assert_param(IS_XSPI_ACCESS_TIME_CYCLE(pCfg->AccessTimeCycle)); + assert_param(IS_XSPI_WRITE_ZERO_LATENCY(pCfg->WriteZeroLatency)); + assert_param(IS_XSPI_LATENCY_MODE(pCfg->LatencyMode)); + + /* Check the state of the driver */ + state = hxspi->State; + if ((state == HAL_XSPI_STATE_HYPERBUS_INIT) || (state == HAL_XSPI_STATE_READY)) + { + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Configure Hyperbus configuration Latency register */ + WRITE_REG(hxspi->Instance->HLCR, ((pCfg->RWRecoveryTimeCycle << XSPI_HLCR_TRWR_Pos) | + (pCfg->AccessTimeCycle << XSPI_HLCR_TACC_Pos) | + pCfg->WriteZeroLatency | pCfg->LatencyMode)); + + /* Update the state */ + hxspi->State = HAL_XSPI_STATE_READY; + } + else + { + status = HAL_BUSY; + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Set the Hyperbus command configuration. + * @param hxspi : XSPI handle + * @param pCmd : Structure containing the Hyperbus command + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCmdTypeDef *const pCmd, + uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the hyperbus command structure */ + assert_param(IS_XSPI_ADDRESS_SPACE(pCmd->AddressSpace)); + assert_param(IS_XSPI_ADDRESS_WIDTH(pCmd->AddressWidth)); + assert_param(IS_XSPI_DATA_LENGTH(pCmd->DataLength)); + assert_param(IS_XSPI_DQS_MODE(pCmd->DQSMode)); +#if defined(HSPI1) + if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) + { + assert_param(IS_HSPI_DATA_MODE(hxspi->Init.MemoryType, pCmd->DataMode)); + } + else + { + /* Nothing to do */ + } +#endif /* HSPI1 */ + + /* Check the state of the driver */ + if ((hxspi->State == HAL_XSPI_STATE_READY) && (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS)) + { + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Re-initialize the value of the functional mode */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, 0U); + + /* Configure the address space in the DCR1 register */ + MODIFY_REG(hxspi->Instance->DCR1, XSPI_DCR1_MTYP_0, pCmd->AddressSpace); + + /* Configure the CCR and WCCR registers with the address size and the following configuration : + - DQS signal enabled (used as RWDS) + - DTR mode enabled on address and data */ + if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) + { + /* - address and data on 8 lines */ + WRITE_REG(hxspi->Instance->CCR, (pCmd->DQSMode | XSPI_CCR_DDTR | XSPI_CCR_DMODE_2 | + pCmd->AddressWidth | XSPI_CCR_ADDTR | XSPI_CCR_ADMODE_2)); + WRITE_REG(hxspi->Instance->WCCR, (pCmd->DQSMode | XSPI_WCCR_DDTR | XSPI_WCCR_DMODE_2 | + pCmd->AddressWidth | XSPI_WCCR_ADDTR | XSPI_WCCR_ADMODE_2)); + } +#if defined(HSPI1) + else if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) + { + /* - address and data on 8 or 16 lines */ + WRITE_REG(hxspi->Instance->CCR, (pCmd->DQSMode | XSPI_CCR_DDTR | pCmd->DataMode | + pCmd->AddressWidth | XSPI_CCR_ADDTR | XSPI_CCR_ADMODE_2)); + WRITE_REG(hxspi->Instance->WCCR, (pCmd->DQSMode | XSPI_WCCR_DDTR | pCmd->DataMode | + pCmd->AddressWidth | XSPI_WCCR_ADDTR | XSPI_WCCR_ADMODE_2)); + } +#endif /* HSPI1 */ + else + { + /* Nothing to do */ + } + + /* Configure the DLR register with the number of data */ + WRITE_REG(hxspi->Instance->DLR, (pCmd->DataLength - 1U)); + + /* Configure the AR register with the address value */ + WRITE_REG(hxspi->Instance->AR, pCmd->Address); + + /* Update the state */ + hxspi->State = HAL_XSPI_STATE_CMD_CFG; + } + else + { + status = HAL_BUSY; + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Transmit an amount of data in blocking mode. + * @param hxspi : XSPI handle + * @param pData : pointer to data buffer + * @param Timeout : Timeout duration + * @note This function is used only in Indirect Write Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + __IO uint32_t *data_reg = &hxspi->Instance->DR; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; + hxspi->XferSize = hxspi->XferCount; + hxspi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect write */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + do + { + /* Wait till fifo threshold flag is set to send data */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_FT, SET, tickstart, Timeout); + + if (status != HAL_OK) + { + break; + } + + *((__IO uint8_t *)data_reg) = *hxspi->pBuffPtr; + hxspi->pBuffPtr++; + hxspi->XferCount--; + } while (hxspi->XferCount > 0U); + + if (status == HAL_OK) + { + /* Wait till transfer complete flag is set to go back in idle state */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Clear transfer complete flag */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); + + hxspi->State = HAL_XSPI_STATE_READY; + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + } + + return status; +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hxspi : XSPI handle + * @param pData : pointer to data buffer + * @param Timeout : Timeout duration + * @note This function is used only in Indirect Read Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + __IO uint32_t *data_reg = &hxspi->Instance->DR; + uint32_t addr_reg = hxspi->Instance->AR; + uint32_t ir_reg = hxspi->Instance->IR; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; + hxspi->XferSize = hxspi->XferCount; + hxspi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect read */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Trig the transfer by re-writing address or instruction register */ + if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hxspi->Instance->IR, ir_reg); + } + } + + do + { + /* Wait till fifo threshold or transfer complete flags are set to read received data */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, (HAL_XSPI_FLAG_FT | HAL_XSPI_FLAG_TC), SET, tickstart, Timeout); + + if (status != HAL_OK) + { + break; + } + + *hxspi->pBuffPtr = *((__IO uint8_t *)data_reg); + hxspi->pBuffPtr++; + hxspi->XferCount--; + } while (hxspi->XferCount > 0U); + + if (status == HAL_OK) + { + /* Wait till transfer complete flag is set to go back in idle state */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Clear transfer complete flag */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); + + hxspi->State = HAL_XSPI_STATE_READY; + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + } + + return status; +} + +/** + * @brief Send an amount of data in non-blocking mode with interrupt. + * @param hxspi : XSPI handle + * @param pData : pointer to data buffer + * @note This function is used only in Indirect Write Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; + hxspi->XferSize = hxspi->XferCount; + hxspi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect write */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + /* Clear flags related to interrupt */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); + + /* Update the state */ + hxspi->State = HAL_XSPI_STATE_BUSY_TX; + + /* Enable the transfer complete, fifo threshold and transfer error interrupts */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + } + + return status; +} + +/** + * @brief Receive an amount of data in non-blocking mode with interrupt. + * @param hxspi : XSPI handle + * @param pData : pointer to data buffer + * @note This function is used only in Indirect Read Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t addr_reg = hxspi->Instance->AR; + uint32_t ir_reg = hxspi->Instance->IR; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; + hxspi->XferSize = hxspi->XferCount; + hxspi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect read */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Clear flags related to interrupt */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); + + /* Update the state */ + hxspi->State = HAL_XSPI_STATE_BUSY_RX; + + /* Enable the transfer complete, fifo threshold and transfer error interrupts */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); + + /* Trig the transfer by re-writing address or instruction register */ + if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hxspi->Instance->IR, ir_reg); + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + } + + return status; +} + +/** + * @brief Send an amount of data in non-blocking mode with DMA. + * @param hxspi : XSPI handle + * @param pData : pointer to data buffer + * @note This function is used only in Indirect Write Mode + * @note If DMA peripheral access is configured as halfword, the number + * of data and the fifo threshold should be aligned on halfword + * @note If DMA peripheral access is configured as word, the number + * of data and the fifo threshold should be aligned on word + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t data_size = hxspi->Instance->DLR + 1U; + DMA_QListTypeDef *p_queue = {NULL}; + uint32_t data_width = DMA_DEST_DATAWIDTH_BYTE; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + if ((hxspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + p_queue = hxspi->hdmatx->LinkedListQueue; + if ((p_queue != NULL) && (p_queue->Head != NULL)) + { + data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; + } + else + { + /* Set Error Code function status */ + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + + /* Return function status */ + status = HAL_ERROR; + } + } + else + { + data_width = hxspi->hdmatx->Init.DestDataWidth; + } + /* Configure counters and size */ + if (data_width == DMA_DEST_DATAWIDTH_BYTE) + { + hxspi->XferCount = data_size; + } + else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD) + { + if (((data_size % 2U) != 0U) || ((hxspi->Init.FifoThresholdByte % 2U) != 0U)) + { + /* The number of data or the fifo threshold is not aligned on halfword + => no transfer possible with DMA peripheral access configured as halfword */ + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + hxspi->XferCount = data_size; + } + } + else if (data_width == DMA_DEST_DATAWIDTH_WORD) + { + if (((data_size % 4U) != 0U) || ((hxspi->Init.FifoThresholdByte % 4U) != 0U)) + { + /* The number of data or the fifo threshold is not aligned on word + => no transfer possible with DMA peripheral access configured as word */ + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + hxspi->XferCount = data_size; + } + } + else + { + /* Nothing to do */ + } + + if (status == HAL_OK) + { + hxspi->XferSize = hxspi->XferCount; + hxspi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect write */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + /* Clear flags related to interrupt */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); + + /* Update the state */ + hxspi->State = HAL_XSPI_STATE_BUSY_TX; + + /* Set the DMA transfer complete callback */ + hxspi->hdmatx->XferCpltCallback = XSPI_DMACplt; + + /* Set the DMA Half transfer complete callback */ + hxspi->hdmatx->XferHalfCpltCallback = XSPI_DMAHalfCplt; + + /* Set the DMA error callback */ + hxspi->hdmatx->XferErrorCallback = XSPI_DMAError; + + /* Clear the DMA abort callback */ + hxspi->hdmatx->XferAbortCallback = NULL; + + /* Enable the transmit DMA Channel */ + if ((hxspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hxspi->hdmatx->LinkedListQueue != NULL) + { + /* Enable the DMA channel */ + MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \ + (DMA_CTR1_SINC | DMA_CTR1_DINC), (DMA_SINC_INCREMENTED | DMA_DINC_FIXED)); + MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET], \ + DMA_CTR2_DREQ, DMA_MEMORY_TO_PERIPH); + /* Set DMA data size*/ + p_queue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hxspi->XferSize; + /* Set DMA source address */ + p_queue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; + /* Set DMA destination address */ + p_queue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hxspi->Instance->DR; + + status = HAL_DMAEx_List_Start_IT(hxspi->hdmatx); + } + else + { + /* Set Error Code */ + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + + hxspi->State = HAL_XSPI_STATE_READY; + + /* Return function status */ + status = HAL_ERROR; + } + } + else + { + if ((hxspi->hdmatx->Init.Direction == DMA_MEMORY_TO_PERIPH) && + (hxspi->hdmatx->Init.SrcInc == DMA_SINC_INCREMENTED) && (hxspi->hdmatx->Init.DestInc == DMA_DINC_FIXED)) + { + status = HAL_DMA_Start_IT(hxspi->hdmatx, (uint32_t)pData, (uint32_t)&hxspi->Instance->DR, hxspi->XferSize); + } + else + { + /* no transmit possible with DMA peripheral, invalid configuration */ + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + } + if (status == HAL_OK) + { + /* Enable the transfer error interrupt */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TE); + + /* Enable the DMA transfer by setting the DMAEN bit */ + SET_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + hxspi->State = HAL_XSPI_STATE_READY; + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + } + + return status; +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA. + * @param hxspi : XSPI handle + * @param pData : pointer to data buffer. + * @note This function is used only in Indirect Read Mode + * @note If DMA peripheral access is configured as halfword, the number + * of data and the fifo threshold should be aligned on halfword + * @note If DMA peripheral access is configured as word, the number + * of data and the fifo threshold should be aligned on word + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t data_size = hxspi->Instance->DLR + 1U; + uint32_t addr_reg = hxspi->Instance->AR; + uint32_t ir_reg = hxspi->Instance->IR; + DMA_QListTypeDef *p_queue = {NULL}; + uint32_t data_width = DMA_DEST_DATAWIDTH_BYTE; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + if ((hxspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + p_queue = hxspi->hdmarx->LinkedListQueue; + if ((p_queue != NULL) && (p_queue->Head != NULL)) + { + data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; + } + else + { + /* Set Error Code */ + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + + /* Return function status */ + status = HAL_ERROR; + } + } + else + { + data_width = hxspi->hdmarx->Init.DestDataWidth; + } + + /* Configure counters and size */ + if (data_width == DMA_DEST_DATAWIDTH_BYTE) + { + hxspi->XferCount = data_size; + } + else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD) + { + if (((data_size % 2U) != 0U) || ((hxspi->Init.FifoThresholdByte % 2U) != 0U)) + { + /* The number of data or the fifo threshold is not aligned on halfword + => no transfer possible with DMA peripheral access configured as halfword */ + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + hxspi->XferCount = data_size; + } + } + else if (data_width == DMA_DEST_DATAWIDTH_WORD) + { + if (((data_size % 4U) != 0U) || ((hxspi->Init.FifoThresholdByte % 4U) != 0U)) + { + /* The number of data or the fifo threshold is not aligned on word + => no transfer possible with DMA peripheral access configured as word */ + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + hxspi->XferCount = data_size; + } + } + else + { + /* Nothing to do */ + } + + if (status == HAL_OK) + { + hxspi->XferSize = hxspi->XferCount; + hxspi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect read */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Clear flags related to interrupt */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); + + /* Update the state */ + hxspi->State = HAL_XSPI_STATE_BUSY_RX; + + /* Set the DMA transfer complete callback */ + hxspi->hdmarx->XferCpltCallback = XSPI_DMACplt; + + /* Set the DMA Half transfer complete callback */ + hxspi->hdmarx->XferHalfCpltCallback = XSPI_DMAHalfCplt; + + /* Set the DMA error callback */ + hxspi->hdmarx->XferErrorCallback = XSPI_DMAError; + + /* Clear the DMA abort callback */ + hxspi->hdmarx->XferAbortCallback = NULL; + + /* Enable the receive DMA Channel */ + if ((hxspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hxspi->hdmarx->LinkedListQueue != NULL) + { + /* Enable the DMA channel */ + MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \ + (DMA_CTR1_SINC | DMA_CTR1_DINC), (DMA_SINC_FIXED | DMA_DINC_INCREMENTED)); + MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET], \ + DMA_CTR2_DREQ, DMA_PERIPH_TO_MEMORY); + /* Set DMA data size */ + p_queue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hxspi->XferSize; + /* Set DMA source address */ + p_queue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hxspi->Instance->DR; + /* Set DMA destination address */ + p_queue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + status = HAL_DMAEx_List_Start_IT(hxspi->hdmarx); + } + else + { + /* Set Error Code */ + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + + hxspi->State = HAL_XSPI_STATE_READY; + + /* Return function status */ + status = HAL_ERROR; + } + } + else + { + if ((hxspi->hdmarx->Init.Direction == DMA_PERIPH_TO_MEMORY) && (hxspi->hdmarx->Init.SrcInc == DMA_SINC_FIXED) + && (hxspi->hdmarx->Init.DestInc == DMA_DINC_INCREMENTED)) + { + status = HAL_DMA_Start_IT(hxspi->hdmarx, (uint32_t)&hxspi->Instance->DR, (uint32_t)pData, hxspi->XferSize); + } + else + { + /* no receive possible with DMA peripheral, invalid configuration */ + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + } + if (status == HAL_OK) + { + /* Enable the transfer error interrupt */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TE); + + /* Trig the transfer by re-writing address or instruction register */ + if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hxspi->Instance->IR, ir_reg); + } + } + + /* Enable the DMA transfer by setting the DMAEN bit */ + SET_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + hxspi->State = HAL_XSPI_STATE_READY; + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + } + + return status; +} + +/** + * @brief Configure the XSPI Automatic Polling Mode in blocking mode. + * @param hxspi : XSPI handle + * @param pCfg : Pointer to structure that contains the polling configuration information. + * @param Timeout : Timeout duration + * @note This function is used only in Automatic Polling Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg, + uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + uint32_t addr_reg = hxspi->Instance->AR; + uint32_t ir_reg = hxspi->Instance->IR; +#ifdef USE_FULL_ASSERT + uint32_t dlr_reg = hxspi->Instance->DLR; +#endif /* USE_FULL_ASSERT */ + + /* Check the parameters of the autopolling configuration structure */ + assert_param(IS_XSPI_MATCH_MODE(pCfg->MatchMode)); + assert_param(IS_XSPI_AUTOMATIC_STOP(pCfg->AutomaticStop)); + assert_param(IS_XSPI_INTERVAL(pCfg->IntervalTime)); + assert_param(IS_XSPI_STATUS_BYTES_SIZE(dlr_reg + 1U)); + + /* Check the state */ + if ((hxspi->State == HAL_XSPI_STATE_CMD_CFG) && (pCfg->AutomaticStop == HAL_XSPI_AUTOMATIC_STOP_ENABLE)) + { + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Configure registers */ + WRITE_REG(hxspi->Instance->PSMAR, pCfg->MatchValue); + WRITE_REG(hxspi->Instance->PSMKR, pCfg->MatchMask); + WRITE_REG(hxspi->Instance->PIR, pCfg->IntervalTime); + MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_PMM | XSPI_CR_APMS | XSPI_CR_FMODE), + (pCfg->MatchMode | pCfg->AutomaticStop | XSPI_FUNCTIONAL_MODE_AUTO_POLLING)); + + /* Trig the transfer by re-writing address or instruction register */ + if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hxspi->Instance->IR, ir_reg); + } + } + + /* Wait till status match flag is set to go back in idle state */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_SM, SET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Clear status match flag */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_SM); + + hxspi->State = HAL_XSPI_STATE_READY; + } + } + else + { + status = HAL_BUSY; + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Configure the XSPI Automatic Polling Mode in non-blocking mode. + * @param hxspi : XSPI handle + * @param pCfg : Pointer to structure that contains the polling configuration information. + * @note This function is used only in Automatic Polling Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + uint32_t addr_reg = hxspi->Instance->AR; + uint32_t ir_reg = hxspi->Instance->IR; +#ifdef USE_FULL_ASSERT + uint32_t dlr_reg = hxspi->Instance->DLR; +#endif /* USE_FULL_ASSERT */ + + /* Check the parameters of the autopolling configuration structure */ + assert_param(IS_XSPI_MATCH_MODE(pCfg->MatchMode)); + assert_param(IS_XSPI_AUTOMATIC_STOP(pCfg->AutomaticStop)); + assert_param(IS_XSPI_INTERVAL(pCfg->IntervalTime)); + assert_param(IS_XSPI_STATUS_BYTES_SIZE(dlr_reg + 1U)); + + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout); + + if (status == HAL_OK) + { + /* Configure registers */ + WRITE_REG(hxspi->Instance->PSMAR, pCfg->MatchValue); + WRITE_REG(hxspi->Instance->PSMKR, pCfg->MatchMask); + WRITE_REG(hxspi->Instance->PIR, pCfg->IntervalTime); + MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_PMM | XSPI_CR_APMS | XSPI_CR_FMODE), + (pCfg->MatchMode | pCfg->AutomaticStop | XSPI_FUNCTIONAL_MODE_AUTO_POLLING)); + + /* Clear flags related to interrupt */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_SM); + + hxspi->State = HAL_XSPI_STATE_BUSY_AUTO_POLLING; + + /* Enable the status match and transfer error interrupts */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_SM | HAL_XSPI_IT_TE); + + /* Trig the transfer by re-writing address or instruction register */ + if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hxspi->Instance->IR, ir_reg); + } + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Configure the Memory Mapped mode. + * @param hxspi : XSPI handle + * @param pCfg : Pointer to structure that contains the memory mapped configuration information. + * @note This function is used only in Memory mapped Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, XSPI_MemoryMappedTypeDef *const pCfg) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the memory-mapped configuration structure */ + assert_param(IS_XSPI_TIMEOUT_ACTIVATION(pCfg->TimeOutActivation)); + + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout); + + if (status == HAL_OK) + { + hxspi->State = HAL_XSPI_STATE_BUSY_MEM_MAPPED; + + if (pCfg->TimeOutActivation == HAL_XSPI_TIMEOUT_COUNTER_ENABLE) + { + assert_param(IS_XSPI_TIMEOUT_PERIOD(pCfg->TimeoutPeriodClock)); + + /* Configure register */ + WRITE_REG(hxspi->Instance->LPTR, pCfg->TimeoutPeriodClock); + + /* Clear flags related to interrupt */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TO); + + /* Enable the timeout interrupt */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TO); + } + + /* Configure CR register with functional mode as memory-mapped */ + MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_TCEN | XSPI_CR_FMODE), + (pCfg->TimeOutActivation | XSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)); + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Transfer Error callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_ErrorCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_XSPI_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Abort completed callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_AbortCpltCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_XSPI_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @brief FIFO Threshold callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_FifoThresholdCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_XSPI_FIFOThresholdCallback could be implemented in the user file + */ +} + +/** + * @brief Command completed callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_CmdCpltCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_XSPI_CmdCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_RxCpltCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_XSPI_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Transfer completed callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_TxCpltCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_XSPI_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_RxHalfCpltCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_XSPI_RxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_TxHalfCpltCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_XSPI_TxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Status Match callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_StatusMatchCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_XSPI_StatusMatchCallback could be implemented in the user file + */ +} + +/** + * @brief Timeout callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_TimeOutCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_XSPI_TimeOutCallback could be implemented in the user file + */ +} + +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User XSPI Callback + * To be used to override the weak predefined callback + * @param hxspi : XSPI handle + * @param CallbackID : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_XSPI_ERROR_CB_ID XSPI Error Callback ID + * @arg @ref HAL_XSPI_ABORT_CB_ID XSPI Abort Callback ID + * @arg @ref HAL_XSPI_FIFO_THRESHOLD_CB_ID XSPI FIFO Threshold Callback ID + * @arg @ref HAL_XSPI_CMD_CPLT_CB_ID XSPI Command Complete Callback ID + * @arg @ref HAL_XSPI_RX_CPLT_CB_ID XSPI Rx Complete Callback ID + * @arg @ref HAL_XSPI_TX_CPLT_CB_ID XSPI Tx Complete Callback ID + * @arg @ref HAL_XSPI_RX_HALF_CPLT_CB_ID XSPI Rx Half Complete Callback ID + * @arg @ref HAL_XSPI_TX_HALF_CPLT_CB_ID XSPI Tx Half Complete Callback ID + * @arg @ref HAL_XSPI_STATUS_MATCH_CB_ID XSPI Status Match Callback ID + * @arg @ref HAL_XSPI_TIMEOUT_CB_ID XSPI Timeout Callback ID + * @arg @ref HAL_XSPI_MSP_INIT_CB_ID XSPI MspInit callback ID + * @arg @ref HAL_XSPI_MSP_DEINIT_CB_ID XSPI MspDeInit callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_XSPI_RegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID, + pXSPI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hxspi->State == HAL_XSPI_STATE_READY) + { + switch (CallbackID) + { + case HAL_XSPI_ERROR_CB_ID : + hxspi->ErrorCallback = pCallback; + break; + case HAL_XSPI_ABORT_CB_ID : + hxspi->AbortCpltCallback = pCallback; + break; + case HAL_XSPI_FIFO_THRESHOLD_CB_ID : + hxspi->FifoThresholdCallback = pCallback; + break; + case HAL_XSPI_CMD_CPLT_CB_ID : + hxspi->CmdCpltCallback = pCallback; + break; + case HAL_XSPI_RX_CPLT_CB_ID : + hxspi->RxCpltCallback = pCallback; + break; + case HAL_XSPI_TX_CPLT_CB_ID : + hxspi->TxCpltCallback = pCallback; + break; + case HAL_XSPI_RX_HALF_CPLT_CB_ID : + hxspi->RxHalfCpltCallback = pCallback; + break; + case HAL_XSPI_TX_HALF_CPLT_CB_ID : + hxspi->TxHalfCpltCallback = pCallback; + break; + case HAL_XSPI_STATUS_MATCH_CB_ID : + hxspi->StatusMatchCallback = pCallback; + break; + case HAL_XSPI_TIMEOUT_CB_ID : + hxspi->TimeOutCallback = pCallback; + break; + case HAL_XSPI_MSP_INIT_CB_ID : + hxspi->MspInitCallback = pCallback; + break; + case HAL_XSPI_MSP_DEINIT_CB_ID : + hxspi->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hxspi->State == HAL_XSPI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_XSPI_MSP_INIT_CB_ID : + hxspi->MspInitCallback = pCallback; + break; + case HAL_XSPI_MSP_DEINIT_CB_ID : + hxspi->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a User XSPI Callback + * XSPI Callback is redirected to the weak predefined callback + * @param hxspi : XSPI handle + * @param CallbackID : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_XSPI_ERROR_CB_ID XSPI Error Callback ID + * @arg @ref HAL_XSPI_ABORT_CB_ID XSPI Abort Callback ID + * @arg @ref HAL_XSPI_FIFO_THRESHOLD_CB_ID XSPI FIFO Threshold Callback ID + * @arg @ref HAL_XSPI_CMD_CPLT_CB_ID XSPI Command Complete Callback ID + * @arg @ref HAL_XSPI_RX_CPLT_CB_ID XSPI Rx Complete Callback ID + * @arg @ref HAL_XSPI_TX_CPLT_CB_ID XSPI Tx Complete Callback ID + * @arg @ref HAL_XSPI_RX_HALF_CPLT_CB_ID XSPI Rx Half Complete Callback ID + * @arg @ref HAL_XSPI_TX_HALF_CPLT_CB_ID XSPI Tx Half Complete Callback ID + * @arg @ref HAL_XSPI_STATUS_MATCH_CB_ID XSPI Status Match Callback ID + * @arg @ref HAL_XSPI_TIMEOUT_CB_ID XSPI Timeout Callback ID + * @arg @ref HAL_XSPI_MSP_INIT_CB_ID XSPI MspInit callback ID + * @arg @ref HAL_XSPI_MSP_DEINIT_CB_ID XSPI MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hxspi->State == HAL_XSPI_STATE_READY) + { + switch (CallbackID) + { + case HAL_XSPI_ERROR_CB_ID : + hxspi->ErrorCallback = HAL_XSPI_ErrorCallback; + break; + case HAL_XSPI_ABORT_CB_ID : + hxspi->AbortCpltCallback = HAL_XSPI_AbortCpltCallback; + break; + case HAL_XSPI_FIFO_THRESHOLD_CB_ID : + hxspi->FifoThresholdCallback = HAL_XSPI_FifoThresholdCallback; + break; + case HAL_XSPI_CMD_CPLT_CB_ID : + hxspi->CmdCpltCallback = HAL_XSPI_CmdCpltCallback; + break; + case HAL_XSPI_RX_CPLT_CB_ID : + hxspi->RxCpltCallback = HAL_XSPI_RxCpltCallback; + break; + case HAL_XSPI_TX_CPLT_CB_ID : + hxspi->TxCpltCallback = HAL_XSPI_TxCpltCallback; + break; + case HAL_XSPI_RX_HALF_CPLT_CB_ID : + hxspi->RxHalfCpltCallback = HAL_XSPI_RxHalfCpltCallback; + break; + case HAL_XSPI_TX_HALF_CPLT_CB_ID : + hxspi->TxHalfCpltCallback = HAL_XSPI_TxHalfCpltCallback; + break; + case HAL_XSPI_STATUS_MATCH_CB_ID : + hxspi->StatusMatchCallback = HAL_XSPI_StatusMatchCallback; + break; + case HAL_XSPI_TIMEOUT_CB_ID : + hxspi->TimeOutCallback = HAL_XSPI_TimeOutCallback; + break; + case HAL_XSPI_MSP_INIT_CB_ID : + hxspi->MspInitCallback = HAL_XSPI_MspInit; + break; + case HAL_XSPI_MSP_DEINIT_CB_ID : + hxspi->MspDeInitCallback = HAL_XSPI_MspDeInit; + break; + default : + /* Update the error code */ + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hxspi->State == HAL_XSPI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_XSPI_MSP_INIT_CB_ID : + hxspi->MspInitCallback = HAL_XSPI_MspInit; + break; + case HAL_XSPI_MSP_DEINIT_CB_ID : + hxspi->MspDeInitCallback = HAL_XSPI_MspDeInit; + break; + default : + /* Update the error code */ + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + +/** + * @} + */ + +/** @defgroup XSPI_Exported_Functions_Group3 Peripheral Control and State functions + * @brief XSPI control and State functions + * +@verbatim + =============================================================================== + ##### Peripheral Control and State functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Check in run-time the state of the driver. + (+) Check the error code set during last operation. + (+) Abort any operation. + (+) Manage the Fifo threshold. + (+) Configure the timeout duration used in the driver. + +@endverbatim + * @{ + */ + +/** + * @brief Abort the current transmission. + * @param hxspi : XSPI handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t state; + uint32_t tickstart = HAL_GetTick(); + + /* Check if the state is in one of the busy or configured states */ + state = hxspi->State; + if (((state & XSPI_BUSY_STATE_MASK) != 0U) || ((state & XSPI_CFG_STATE_MASK) != 0U)) + { + /* Check if the DMA is enabled */ + if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) + { + /* Disable the DMA transfer on the XSPI side */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); + + /* Disable the DMA transmit on the DMA side */ + status = HAL_DMA_Abort(hxspi->hdmatx); + if (status != HAL_OK) + { + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + } + + /* Disable the DMA receive on the DMA side */ + status = HAL_DMA_Abort(hxspi->hdmarx); + if (status != HAL_OK) + { + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + } + } + + if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET) + { + /* Perform an abort of the XSPI */ + SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT); + + /* Wait until the transfer complete flag is set to go back in idle state */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, hxspi->Timeout); + + if (status == HAL_OK) + { + /* Clear transfer complete flag */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); + + /* Wait until the busy flag is reset to go back in idle state */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout); + + if (status == HAL_OK) + { + hxspi->State = HAL_XSPI_STATE_READY; + } + } + } + else + { + hxspi->State = HAL_XSPI_STATE_READY; + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Abort the current transmission (non-blocking function) + * @param hxspi : XSPI handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t state; + + /* Check if the state is in one of the busy or configured states */ + state = hxspi->State; + if (((state & XSPI_BUSY_STATE_MASK) != 0U) || ((state & XSPI_CFG_STATE_MASK) != 0U)) + { + /* Disable all interrupts */ + HAL_XSPI_DISABLE_IT(hxspi, (HAL_XSPI_IT_TO | HAL_XSPI_IT_SM | HAL_XSPI_IT_FT | HAL_XSPI_IT_TC | HAL_XSPI_IT_TE)); + + hxspi->State = HAL_XSPI_STATE_ABORT; + + /* Check if the DMA is enabled */ + if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) + { + /* Disable the DMA transfer on the XSPI side */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); + + /* Disable the DMA transmit on the DMA side */ + hxspi->hdmatx->XferAbortCallback = XSPI_DMAAbortCplt; + if (HAL_DMA_Abort_IT(hxspi->hdmatx) != HAL_OK) + { + hxspi->State = HAL_XSPI_STATE_READY; + + /* Abort callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->AbortCpltCallback(hxspi); +#else + HAL_XSPI_AbortCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + + /* Disable the DMA receive on the DMA side */ + hxspi->hdmarx->XferAbortCallback = XSPI_DMAAbortCplt; + if (HAL_DMA_Abort_IT(hxspi->hdmarx) != HAL_OK) + { + hxspi->State = HAL_XSPI_STATE_READY; + + /* Abort callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->AbortCpltCallback(hxspi); +#else + HAL_XSPI_AbortCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + } + else + { + if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET) + { + /* Clear transfer complete flag */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); + + /* Enable the transfer complete interrupts */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC); + + /* Perform an abort of the XSPI */ + SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT); + } + else + { + hxspi->State = HAL_XSPI_STATE_READY; + + /* Abort callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->AbortCpltCallback(hxspi); +#else + HAL_XSPI_AbortCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** @brief Set XSPI Fifo threshold. + * @param hxspi : XSPI handle. + * @param Threshold : Threshold of the Fifo. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_SetFifoThreshold(XSPI_HandleTypeDef *hxspi, uint32_t Threshold) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) + { + assert_param(IS_OCTOSPI_FIFO_THRESHOLD_BYTE(Threshold)); + } +#if defined(HSPI1) + else if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) + { + assert_param(IS_HSPI_FIFO_THRESHOLD_BYTE(Threshold)); + } +#endif /* HSPI1 */ + else + { + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Check the state */ + if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) + { + /* Synchronize initialization structure with the new fifo threshold value */ + hxspi->Init.FifoThresholdByte = Threshold; + + /* Configure new fifo threshold */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FTHRES, ((hxspi->Init.FifoThresholdByte - 1U) << XSPI_CR_FTHRES_Pos)); + + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** @brief Get XSPI Fifo threshold. + * @param hxspi : XSPI handle. + * @retval Fifo threshold + */ +uint32_t HAL_XSPI_GetFifoThreshold(const XSPI_HandleTypeDef *hxspi) +{ + return ((READ_BIT(hxspi->Instance->CR, XSPI_CR_FTHRES) >> XSPI_CR_FTHRES_Pos) + 1U); +} + +/** @brief Set XSPI Memory Type. + * @param hxspi : XSPI handle. + * @param Type : Memory Type. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_SetMemoryType(XSPI_HandleTypeDef *hxspi, uint32_t Type) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_XSPI_MEMORY_TYPE(Type)); + + /* Check the state */ + if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) + { + /* Synchronize initialization structure with the new memory type value */ + hxspi->Init.MemoryType = Type; + + /* Configure new memory type */ + MODIFY_REG(hxspi->Instance->DCR1, XSPI_DCR1_MTYP, hxspi->Init.MemoryType); + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** @brief Set XSPI Device Size. + * @param hxspi : XSPI handle. + * @param Size : Device Size. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_SetDeviceSize(XSPI_HandleTypeDef *hxspi, uint32_t Size) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_XSPI_MEMORY_SIZE(Size)); + + /* Check the state */ + if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) + { + /* Synchronize initialization structure with the new device size value */ + hxspi->Init.MemorySize = Size; + + /* Configure new device size */ + MODIFY_REG(hxspi->Instance->DCR1, XSPI_DCR1_DEVSIZE, + (hxspi->Init.MemorySize << XSPI_DCR1_DEVSIZE_Pos)); + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** @brief Set XSPI Clock prescaler. + * @param hxspi : XSPI handle. + * @param Prescaler : Clock prescaler. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_SetClockPrescaler(XSPI_HandleTypeDef *hxspi, uint32_t Prescaler) +{ + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_XSPI_CLK_PRESCALER(Prescaler)); + + /* Check the state */ + if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) + { + /* Synchronize initialization structure with the new clock prescaler value */ + hxspi->Init.ClockPrescaler = Prescaler; + + /* Configure clock prescaler */ + MODIFY_REG(hxspi->Instance->DCR2, XSPI_DCR2_PRESCALER, + ((hxspi->Init.ClockPrescaler) << XSPI_DCR2_PRESCALER_Pos)); + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** @brief Set XSPI timeout. + * @param hxspi : XSPI handle. + * @param Timeout : Timeout for the memory access. + * @retval HAL state + */ +HAL_StatusTypeDef HAL_XSPI_SetTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Timeout) +{ + hxspi->Timeout = Timeout; + return HAL_OK; +} + +/** + * @brief Return the XSPI error code. + * @param hxspi : XSPI handle + * @retval XSPI Error Code + */ +uint32_t HAL_XSPI_GetError(const XSPI_HandleTypeDef *hxspi) +{ + return hxspi->ErrorCode; +} + +/** + * @brief Return the XSPI handle state. + * @param hxspi : XSPI handle + * @retval HAL state + */ +uint32_t HAL_XSPI_GetState(const XSPI_HandleTypeDef *hxspi) +{ + /* Return XSPI handle state */ + return hxspi->State; +} + +/** + * @} + */ + +#if defined(OCTOSPIM) +/** @defgroup XSPI_Exported_Functions_Group4 IO Manager configuration function + * @brief XSPI IO Manager configuration function + * +@verbatim + =============================================================================== + ##### IO Manager configuration function ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Configure the IO manager. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the XSPI IO manager. + * @param hxspi : XSPI handle + * @param pCfg : Pointer to Configuration of the IO Manager for the instance + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *hxspi, XSPIM_CfgTypeDef *const pCfg, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t instance; + uint8_t index; + uint8_t xspi_enabled = 0U; + uint8_t other_instance; + XSPIM_CfgTypeDef IOM_cfg[OSPI_NB_INSTANCE]; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(Timeout); + + /* Check the parameters of the XSPI IO Manager configuration structure */ + assert_param(IS_XSPIM_PORT(pCfg->ClkPort)); + assert_param(IS_XSPIM_DQS_PORT(pCfg->DQSPort)); + assert_param(IS_XSPIM_PORT(pCfg->NCSPort)); + assert_param(IS_XSPIM_IO_PORT(pCfg->IOLowPort)); + assert_param(IS_XSPIM_IO_PORT(pCfg->IOHighPort)); + assert_param(IS_XSPIM_REQ2ACKTIME(pCfg->Req2AckTime)); + + if (hxspi->Instance == OCTOSPI1) + { + instance = 0U; + other_instance = 1U; + } + else if (hxspi->Instance == OCTOSPI2) + { + instance = 1U; + other_instance = 0U; + } + else + { + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /**************** Get current configuration of the instances ****************/ + for (index = 0U; index < OSPI_NB_INSTANCE; index++) + { + XSPIM_GetConfig(index + 1U, &(IOM_cfg[index])); + } + + if (status == HAL_OK) + { + /********** Disable both XSPI to configure XSPI IO Manager **********/ + if ((OCTOSPI1->CR & XSPI_CR_EN) != 0U) + { + CLEAR_BIT(OCTOSPI1->CR, XSPI_CR_EN); + xspi_enabled |= 0x1U; + } + if ((OCTOSPI2->CR & XSPI_CR_EN) != 0U) + { + CLEAR_BIT(OCTOSPI2->CR, XSPI_CR_EN); + xspi_enabled |= 0x2U; + } + + /***************** Deactivation of previous configuration *****************/ + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort - 1U)], OCTOSPIM_PCR_NCSEN); + if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U) + { + /* De-multiplexing should be performed */ + CLEAR_BIT(OCTOSPIM->CR, OCTOSPIM_CR_MUXEN); + + if (other_instance == 1U) + { + SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort - 1U)], OCTOSPIM_PCR_CLKSRC); + if (IOM_cfg[other_instance].DQSPort != 0U) + { + SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort - 1U)], OCTOSPIM_PCR_DQSSRC); + } + if (IOM_cfg[other_instance].IOLowPort != HAL_XSPIM_IOPORT_NONE) + { + SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort - 1U)& OSPI_IOM_PORT_MASK)], + OCTOSPIM_PCR_IOLSRC_1); + } + if (IOM_cfg[other_instance].IOHighPort != HAL_XSPIM_IOPORT_NONE) + { + SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort - 1U)& OSPI_IOM_PORT_MASK)], + OCTOSPIM_PCR_IOHSRC_1); + } + } + } + else + { + if (IOM_cfg[instance].ClkPort != 0U) + { + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort - 1U)], OCTOSPIM_PCR_CLKEN); + if (IOM_cfg[instance].DQSPort != 0U) + { + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort - 1U)], OCTOSPIM_PCR_DQSEN); + } + if (IOM_cfg[instance].IOLowPort != HAL_XSPIM_IOPORT_NONE) + { + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort - 1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN); + } + if (IOM_cfg[instance].IOHighPort != HAL_XSPIM_IOPORT_NONE) + { + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort - 1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN); + } + } + } + + /********************* Deactivation of other instance *********************/ + if ((pCfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (pCfg->DQSPort == IOM_cfg[other_instance].DQSPort) || + (pCfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (pCfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || + (pCfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) + { + if ((pCfg->ClkPort == IOM_cfg[other_instance].ClkPort) && + (pCfg->DQSPort == IOM_cfg[other_instance].DQSPort) && + (pCfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) && + (pCfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) + { + /* Multiplexing should be performed */ + SET_BIT(OCTOSPIM->CR, OCTOSPIM_CR_MUXEN); + } + else + { + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort - 1U)], OCTOSPIM_PCR_CLKEN); + if (IOM_cfg[other_instance].DQSPort != 0U) + { + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort - 1U)], OCTOSPIM_PCR_DQSEN); + } + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort - 1U)], OCTOSPIM_PCR_NCSEN); + if (IOM_cfg[other_instance].IOLowPort != HAL_XSPIM_IOPORT_NONE) + { + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort - 1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN); + } + if (IOM_cfg[other_instance].IOHighPort != HAL_XSPIM_IOPORT_NONE) + { + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort - 1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN); + } + } + } + + /******************** Activation of new configuration *********************/ + MODIFY_REG(OCTOSPIM->PCR[(pCfg->NCSPort - 1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC), + (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos))); + + if ((pCfg->Req2AckTime - 1U) > ((OCTOSPIM->CR & OCTOSPIM_CR_REQ2ACK_TIME) >> OCTOSPIM_CR_REQ2ACK_TIME_Pos)) + { + MODIFY_REG(OCTOSPIM->CR, OCTOSPIM_CR_REQ2ACK_TIME, ((pCfg->Req2AckTime - 1U) << OCTOSPIM_CR_REQ2ACK_TIME_Pos)); + } + + if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U) + { + MODIFY_REG(OCTOSPIM->PCR[(pCfg->ClkPort - 1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), OCTOSPIM_PCR_CLKEN); + if (pCfg->DQSPort != 0U) + { + MODIFY_REG(OCTOSPIM->PCR[(pCfg->DQSPort - 1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), OCTOSPIM_PCR_DQSEN); + } + + if ((pCfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U) + { + MODIFY_REG(OCTOSPIM->PCR[((pCfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)], + (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), OCTOSPIM_PCR_IOLEN); + } + else if (pCfg->IOLowPort != HAL_XSPIM_IOPORT_NONE) + { + MODIFY_REG(OCTOSPIM->PCR[((pCfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)], + (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), OCTOSPIM_PCR_IOHEN); + } + else + { + /* Nothing to do */ + } + + if ((pCfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U) + { + MODIFY_REG(OCTOSPIM->PCR[((pCfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)], + (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0)); + } + else if (pCfg->IOHighPort != HAL_XSPIM_IOPORT_NONE) + { + MODIFY_REG(OCTOSPIM->PCR[((pCfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)], + (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0)); + } + else + { + /* Nothing to do */ + } + } + else + { + MODIFY_REG(OCTOSPIM->PCR[(pCfg->ClkPort - 1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), + (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos))); + if (pCfg->DQSPort != 0U) + { + MODIFY_REG(OCTOSPIM->PCR[(pCfg->DQSPort - 1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), + (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos))); + } + + if ((pCfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U) + { + MODIFY_REG(OCTOSPIM->PCR[((pCfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)], + (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), + (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos + 1U)))); + } + else if (pCfg->IOLowPort != HAL_XSPIM_IOPORT_NONE) + { + MODIFY_REG(OCTOSPIM->PCR[((pCfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)], + (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), + (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos + 1U)))); + } + else + { + /* Nothing to do */ + } + + if ((pCfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U) + { + MODIFY_REG(OCTOSPIM->PCR[((pCfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)], + (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), + (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos + 1U)))); + } + else if (pCfg->IOHighPort != HAL_XSPIM_IOPORT_NONE) + { + MODIFY_REG(OCTOSPIM->PCR[((pCfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)], + (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), + (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos + 1U)))); + } + else + { + /* Nothing to do */ + } + } + + /******* Re-enable both XSPI after configure XSPI IO Manager ********/ + if ((xspi_enabled & 0x1U) != 0U) + { + SET_BIT(OCTOSPI1->CR, XSPI_CR_EN); + } + if ((xspi_enabled & 0x2U) != 0U) + { + SET_BIT(OCTOSPI2->CR, XSPI_CR_EN); + } + } + + return status; +} + +/** + * @} + */ + +#endif /* OCTOSPIM */ +/** @defgroup XSPI_Exported_Functions_Group5 Delay Block function + * @brief Delay block function + * +@verbatim + =============================================================================== + ##### Delay Block function ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Configure the delay block. + +@endverbatim + * @{ + */ + +/** + * @brief Set the Delay Block configuration. + * @param hxspi : XSPI handle. + * @param pdlyb_cfg: Pointer to DLYB configuration structure. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_XSPI_DLYB_SetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *const pdlyb_cfg) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Enable XSPI Free Running Clock (mandatory) */ + SET_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); + + /* Update XSPI state */ + hxspi->State = HAL_XSPI_STATE_BUSY_CMD; + + if (hxspi->Instance == OCTOSPI1) + { + /* Enable the DelayBlock */ + LL_DLYB_Enable(DLYB_OCTOSPI1); + + /* Set the Delay Block configuration */ + LL_DLYB_SetDelay(DLYB_OCTOSPI1, pdlyb_cfg); + status = HAL_OK; + } +#if defined(OCTOSPI2) + else if (hxspi->Instance == OCTOSPI2) + { + /* Enable the DelayBlock */ + LL_DLYB_Enable(DLYB_OCTOSPI2); + + /* Set the Delay Block configuration */ + LL_DLYB_SetDelay(DLYB_OCTOSPI2, pdlyb_cfg); + status = HAL_OK; + } +#endif /* OCTOSPI2 */ + else + { + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; + } + + /* Abort the current XSPI operation if exist */ + (void)HAL_XSPI_Abort(hxspi); + + /* Disable Free Running Clock */ + CLEAR_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); + + return status; +} + +/** + * @brief Get the Delay Block configuration. + * @param hxspi : XSPI handle. + * @param pdlyb_cfg: Pointer to DLYB configuration structure. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_XSPI_DLYB_GetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *const pdlyb_cfg) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + if (hxspi->Instance == OCTOSPI1) + { + LL_DLYB_GetDelay(DLYB_OCTOSPI1, pdlyb_cfg); + status = HAL_OK; + } +#if defined(OCTOSPI2) + else if (hxspi->Instance == OCTOSPI2) + { + LL_DLYB_GetDelay(DLYB_OCTOSPI2, pdlyb_cfg); + status = HAL_OK; + } +#endif /* OCTOSPI2 */ + else + { + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; + } + + return status; +} + +/** + * @brief Get the Delay line length value. + * @param hxspi : XSPI handle. + * @param pdlyb_cfg: Pointer to DLYB configuration structure. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_XSPI_DLYB_GetClockPeriod(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *const pdlyb_cfg) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Enable XSPI Free Running Clock (mandatory) */ + SET_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); + + /* Update XSPI state */ + hxspi->State = HAL_XSPI_STATE_BUSY_CMD; + + if (hxspi->Instance == OCTOSPI1) + { + /* Enable the DelayBlock */ + LL_DLYB_Enable(DLYB_OCTOSPI1); + + /* try to detect Period */ + if (LL_DLYB_GetClockPeriod(DLYB_OCTOSPI1, pdlyb_cfg) == (uint32_t)SUCCESS) + { + status = HAL_OK; + } + + /* Disable the DelayBlock */ + LL_DLYB_Disable(DLYB_OCTOSPI1); + } +#if defined(OCTOSPI2) + else if (hxspi->Instance == OCTOSPI2) + { + /* Enable the DelayBlock */ + LL_DLYB_Enable(DLYB_OCTOSPI2); + + /* try to detect Period */ + if (LL_DLYB_GetClockPeriod(DLYB_OCTOSPI2, pdlyb_cfg) == (uint32_t)SUCCESS) + { + status = HAL_OK; + } + + /* Disable the DelayBlock */ + LL_DLYB_Disable(DLYB_OCTOSPI2); + } +#endif /* OCTOSPI2 */ + else + { + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; + } + + /* Abort the current XSPI operation if exist */ + (void)HAL_XSPI_Abort(hxspi); + + /* Disable Free Running Clock */ + CLEAR_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); + + return status; +} + +/** + * @} + */ + +/** @defgroup XSPI_Exported_Functions_Group6 High-speed interface and calibration functions + * @brief XSPI high-speed interface and calibration functions + * +@verbatim + =============================================================================== + ##### High-speed interface and calibration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Get the delay values of the high-speed interface DLLs. + (+) Set a delay value for the high-speed interface DLLs. + +@endverbatim + * @{ + */ +#if defined(HSPI1) + +/** + * @brief Get the delay values of the high-speed interface DLLs. + * @param hxspi : XSPI handle + * @param pCfg : Current delay values corresponding to the DelayValueType field. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t reg = 0; + + if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) + { + /* Check the parameter specified in the structure */ + assert_param(IS_XSPI_DELAY_TYPE(pCfg->DelayValueType)); + + switch (pCfg->DelayValueType) + { + case HAL_XSPI_CAL_FULL_CYCLE_DELAY: + reg = hxspi->Instance->CALFCR; + pCfg->MaxCalibration = (reg & HSPI_CALFCR_CALMAX); + break; + case HAL_XSPI_CAL_FEEDBACK_CLK_DELAY: + reg = hxspi->Instance->CALMR; + break; + case HAL_XSPI_CAL_DATA_OUTPUT_DELAY: + reg = hxspi->Instance->CALSOR; + break; + case HAL_XSPI_CAL_DQS_INPUT_DELAY: + reg = hxspi->Instance->CALSIR; + break; + default: + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + break; + } + + if (status == HAL_OK) + { + pCfg->FineCalibrationUnit = (reg & HSPI_CALFCR_FINE); + pCfg->CoarseCalibrationUnit = ((reg & HSPI_CALFCR_COARSE) >> HSPI_CALFCR_COARSE_Pos); + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + + return status; +} + +/** + * @brief Set a delay value for the high-speed interface DLLs. + * @param hxspi : XSPI handle + * @param pCfg : Configuration of delay value specified in DelayValueType field. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) + { + /* Check the parameter specified in the structure */ + assert_param(IS_XSPI_DELAY_TYPE(pCfg->DelayValueType)); + assert_param(IS_XSPI_FINECAL_VALUE(pCfg->FineCalibrationUnit)); + assert_param(IS_XSPI_COARSECAL_VALUE(pCfg->CoarseCalibrationUnit)); + + /* Check if the state isn't in one of the busy states */ + if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) + { + switch (pCfg->DelayValueType) + { + case HAL_XSPI_CAL_FEEDBACK_CLK_DELAY: + MODIFY_REG(hxspi->Instance->CALMR, (HSPI_CALMR_COARSE | HSPI_CALMR_FINE), + (pCfg->FineCalibrationUnit | (pCfg->CoarseCalibrationUnit << HSPI_CALMR_COARSE_Pos))); + break; + case HAL_XSPI_CAL_DATA_OUTPUT_DELAY: + MODIFY_REG(hxspi->Instance->CALSOR, (HSPI_CALSOR_COARSE | HSPI_CALSOR_FINE), + (pCfg->FineCalibrationUnit | (pCfg->CoarseCalibrationUnit << HSPI_CALSOR_COARSE_Pos))); + break; + case HAL_XSPI_CAL_DQS_INPUT_DELAY: + MODIFY_REG(hxspi->Instance->CALSIR, (HSPI_CALSIR_COARSE | HSPI_CALSIR_FINE), + (pCfg->FineCalibrationUnit | (pCfg->CoarseCalibrationUnit << HSPI_CALSIR_COARSE_Pos))); + break; + default: + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + break; + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + + return status; +} + +#endif /* HSPI1 */ +/** + * @} + */ + +/** + @cond 0 + */ +/** + * @brief DMA XSPI process complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void XSPI_DMACplt(DMA_HandleTypeDef *hdma) +{ + XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); + hxspi->XferCount = 0; + + /* Disable the DMA transfer on the XSPI side */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Enable the XSPI transfer complete Interrupt */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC); +} + +/** + * @brief DMA XSPI process half complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void XSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma) +{ + XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); + hxspi->XferCount = (hxspi->XferCount >> 1); + + if (hxspi->State == HAL_XSPI_STATE_BUSY_RX) + { +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->RxHalfCpltCallback(hxspi); +#else + HAL_XSPI_RxHalfCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + else + { +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->TxHalfCpltCallback(hxspi); +#else + HAL_XSPI_TxHalfCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } +} + +/** + * @brief DMA XSPI communication error callback. + * @param hdma : DMA handle + * @retval None + */ +static void XSPI_DMAError(DMA_HandleTypeDef *hdma) +{ + XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); + hxspi->XferCount = 0; + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + + /* Disable the DMA transfer on the XSPI side */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); + + /* Abort the XSPI */ + if (HAL_XSPI_Abort_IT(hxspi) != HAL_OK) + { + /* Disable the interrupts */ + HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); + + hxspi->State = HAL_XSPI_STATE_READY; + + /* Error callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->ErrorCallback(hxspi); +#else + HAL_XSPI_ErrorCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } +} + +/** + * @brief DMA XSPI abort complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void XSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) +{ + XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); + hxspi->XferCount = 0; + + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_ABORT) + { + /* DMA abort called by XSPI abort */ + if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET) + { + /* Clear transfer complete flag */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); + + /* Enable the transfer complete interrupts */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC); + + /* Perform an abort of the XSPI */ + SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT); + } + else + { + hxspi->State = HAL_XSPI_STATE_READY; + + /* Abort callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->AbortCpltCallback(hxspi); +#else + HAL_XSPI_AbortCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + } + else + { + /* DMA abort called due to a transfer error interrupt */ + hxspi->State = HAL_XSPI_STATE_READY; + + /* Error callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->ErrorCallback(hxspi); +#else + HAL_XSPI_ErrorCallback(hxspi); +#endif /* defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } +} + +/** + * @brief Wait for a flag state until timeout. + * @param hxspi : XSPI handle + * @param Flag : Flag checked + * @param State : Value of the flag expected + * @param Timeout : Duration of the timeout + * @param Tickstart : Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef XSPI_WaitFlagStateUntilTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Flag, + FlagStatus State, uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is in expected state */ + while ((HAL_XSPI_GET_FLAG(hxspi, Flag)) != State) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hxspi->State = HAL_XSPI_STATE_ERROR; + hxspi->ErrorCode |= HAL_XSPI_ERROR_TIMEOUT; + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Configure the registers for the regular command mode. + * @param hxspi : XSPI handle + * @param pCmd : structure that contains the command configuration information + * @retval HAL status + */ +static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *pCmd) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t *ccr_reg; + __IO uint32_t *tcr_reg; + __IO uint32_t *ir_reg; + __IO uint32_t *abr_reg; + + /* Re-initialize the value of the functional mode */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, 0U); + + if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) + { + if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM) + { + assert_param(IS_OCTOSPI_IO_SELECT(pCmd->IOSelect)); + MODIFY_REG(hxspi->Instance->CR, OCTOSPI_CR_MSEL, pCmd->IOSelect); + } + } +#if defined(HSPI1) + else if (IS_HSPI_ALL_INSTANCE(hxspi->Instance)) + { + if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM) + { + assert_param(IS_HSPI_IO_SELECT(pCmd->IOSelect)); + MODIFY_REG(hxspi->Instance->CR, HSPI_CR_MSEL, pCmd->IOSelect); + } + } +#endif /* HSPI1 */ + else + { + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (pCmd->OperationType == HAL_XSPI_OPTYPE_WRITE_CFG) + { + ccr_reg = &(hxspi->Instance->WCCR); + tcr_reg = &(hxspi->Instance->WTCR); + ir_reg = &(hxspi->Instance->WIR); + abr_reg = &(hxspi->Instance->WABR); + } + else if (pCmd->OperationType == HAL_XSPI_OPTYPE_WRAP_CFG) + { + ccr_reg = &(hxspi->Instance->WPCCR); + tcr_reg = &(hxspi->Instance->WPTCR); + ir_reg = &(hxspi->Instance->WPIR); + abr_reg = &(hxspi->Instance->WPABR); + } + else + { + ccr_reg = &(hxspi->Instance->CCR); + tcr_reg = &(hxspi->Instance->TCR); + ir_reg = &(hxspi->Instance->IR); + abr_reg = &(hxspi->Instance->ABR); + } + + /* Configure the CCR register with DQS and SIOO modes */ + *ccr_reg = (pCmd->DQSMode | pCmd->SIOOMode); + + if (pCmd->AlternateBytesMode != HAL_XSPI_ALT_BYTES_NONE) + { + /* Configure the ABR register with alternate bytes value */ + *abr_reg = pCmd->AlternateBytes; + + /* Configure the CCR register with alternate bytes communication parameters */ + MODIFY_REG((*ccr_reg), (XSPI_CCR_ABMODE | XSPI_CCR_ABDTR | XSPI_CCR_ABSIZE), + (pCmd->AlternateBytesMode | pCmd->AlternateBytesDTRMode | pCmd->AlternateBytesWidth)); + } + + /* Configure the TCR register with the number of dummy cycles */ + MODIFY_REG((*tcr_reg), XSPI_TCR_DCYC, pCmd->DummyCycles); + + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) + { + /* Configure the DLR register with the number of data */ + hxspi->Instance->DLR = (pCmd->DataLength - 1U); + } + } + + if (pCmd->InstructionMode != HAL_XSPI_INSTRUCTION_NONE) + { + if (pCmd->AddressMode != HAL_XSPI_ADDRESS_NONE) + { + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + /* ---- Command with instruction, address and data ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (XSPI_CCR_IMODE | XSPI_CCR_IDTR | XSPI_CCR_ISIZE | + XSPI_CCR_ADMODE | XSPI_CCR_ADDTR | XSPI_CCR_ADSIZE | + XSPI_CCR_DMODE | XSPI_CCR_DDTR), + (pCmd->InstructionMode | pCmd->InstructionDTRMode | pCmd->InstructionWidth | + pCmd->AddressMode | pCmd->AddressDTRMode | pCmd->AddressWidth | + pCmd->DataMode | pCmd->DataDTRMode)); + } + else + { + /* ---- Command with instruction and address ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (XSPI_CCR_IMODE | XSPI_CCR_IDTR | XSPI_CCR_ISIZE | + XSPI_CCR_ADMODE | XSPI_CCR_ADDTR | XSPI_CCR_ADSIZE), + (pCmd->InstructionMode | pCmd->InstructionDTRMode | pCmd->InstructionWidth | + pCmd->AddressMode | pCmd->AddressDTRMode | pCmd->AddressWidth)); + + /* The DHQC bit is linked with DDTR bit which should be activated */ + if ((hxspi->Init.DelayHoldQuarterCycle == HAL_XSPI_DHQC_ENABLE) && + (pCmd->InstructionDTRMode == HAL_XSPI_INSTRUCTION_DTR_ENABLE)) + { + MODIFY_REG((*ccr_reg), XSPI_CCR_DDTR, HAL_XSPI_DATA_DTR_ENABLE); + } + } + /* Configure the IR register with the instruction value */ + *ir_reg = pCmd->Instruction; + + /* Configure the AR register with the address value */ + hxspi->Instance->AR = pCmd->Address; + } + else + { + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + /* ---- Command with instruction and data ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (XSPI_CCR_IMODE | XSPI_CCR_IDTR | XSPI_CCR_ISIZE | + XSPI_CCR_DMODE | XSPI_CCR_DDTR), + (pCmd->InstructionMode | pCmd->InstructionDTRMode | pCmd->InstructionWidth | + pCmd->DataMode | pCmd->DataDTRMode)); + } + else + { + /* ---- Command with only instruction ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (XSPI_CCR_IMODE | XSPI_CCR_IDTR | XSPI_CCR_ISIZE), + (pCmd->InstructionMode | pCmd->InstructionDTRMode | pCmd->InstructionWidth)); + + /* The DHQC bit is linked with DDTR bit which should be activated */ + if ((hxspi->Init.DelayHoldQuarterCycle == HAL_XSPI_DHQC_ENABLE) && + (pCmd->InstructionDTRMode == HAL_XSPI_INSTRUCTION_DTR_ENABLE)) + { + MODIFY_REG((*ccr_reg), XSPI_CCR_DDTR, HAL_XSPI_DATA_DTR_ENABLE); + } + } + + /* Configure the IR register with the instruction value */ + *ir_reg = pCmd->Instruction; + + } + } + else + { + if (pCmd->AddressMode != HAL_XSPI_ADDRESS_NONE) + { + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + /* ---- Command with address and data ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (XSPI_CCR_ADMODE | XSPI_CCR_ADDTR | XSPI_CCR_ADSIZE | + XSPI_CCR_DMODE | XSPI_CCR_DDTR), + (pCmd->AddressMode | pCmd->AddressDTRMode | pCmd->AddressWidth | + pCmd->DataMode | pCmd->DataDTRMode)); + } + else + { + /* ---- Command with only address ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (XSPI_CCR_ADMODE | XSPI_CCR_ADDTR | XSPI_CCR_ADSIZE), + (pCmd->AddressMode | pCmd->AddressDTRMode | pCmd->AddressWidth)); + } + + /* Configure the AR register with the instruction value */ + hxspi->Instance->AR = pCmd->Address; + } + else + { + /* ---- Invalid command configuration (no instruction, no address) ---- */ + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + } + + return status; +} + +#if defined(OCTOSPIM) +/** + * @brief Get the current IOM configuration for an XSPI instance. + * @param instance_nb : number of the instance + * @param pCfg : configuration of the IO Manager for the instance + * @retval HAL status + */ +static void XSPIM_GetConfig(uint8_t instance_nb, XSPIM_CfgTypeDef *const pCfg) +{ + uint32_t reg; + uint32_t value = 0U; + uint32_t index; + + /* Initialize the structure */ + pCfg->ClkPort = 0U; + pCfg->DQSPort = 0U; + pCfg->NCSPort = 0U; + pCfg->IOLowPort = 0U; + pCfg->IOHighPort = 0U; + + if (instance_nb == 2U) + { + if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) == 0U) + { + value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC | + OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1); + } + else + { + value = OCTOSPIM_PCR_NCSSRC; + } + } + + /* Get the information about the instance */ + for (index = 0U; index < OSPI_IOM_NB_PORTS; index ++) + { + reg = OCTOSPIM->PCR[index]; + + if ((reg & OCTOSPIM_PCR_CLKEN) != 0U) + { + /* The clock is enabled on this port */ + if ((reg & OCTOSPIM_PCR_CLKSRC) == (value & OCTOSPIM_PCR_CLKSRC)) + { + /* The clock correspond to the instance passed as parameter */ + pCfg->ClkPort = index + 1U; + } + } + + if ((reg & OCTOSPIM_PCR_DQSEN) != 0U) + { + /* The DQS is enabled on this port */ + if ((reg & OCTOSPIM_PCR_DQSSRC) == (value & OCTOSPIM_PCR_DQSSRC)) + { + /* The DQS correspond to the instance passed as parameter */ + pCfg->DQSPort = index + 1U; + } + } + + if ((reg & OCTOSPIM_PCR_NCSEN) != 0U) + { + /* The nCS is enabled on this port */ + if ((reg & OCTOSPIM_PCR_NCSSRC) == (value & OCTOSPIM_PCR_NCSSRC)) + { + /* The nCS correspond to the instance passed as parameter */ + pCfg->NCSPort = index + 1U; + } + } + + if ((reg & OCTOSPIM_PCR_IOLEN) != 0U) + { + /* The IO Low is enabled on this port */ + if ((reg & OCTOSPIM_PCR_IOLSRC_1) == (value & OCTOSPIM_PCR_IOLSRC_1)) + { + /* The IO Low correspond to the instance passed as parameter */ + if ((reg & OCTOSPIM_PCR_IOLSRC_0) == 0U) + { + pCfg->IOLowPort = (OCTOSPIM_PCR_IOLEN | (index + 1U)); + } + else + { + pCfg->IOLowPort = (OCTOSPIM_PCR_IOHEN | (index + 1U)); + } + } + } + + if ((reg & OCTOSPIM_PCR_IOHEN) != 0U) + { + /* The IO High is enabled on this port */ + if ((reg & OCTOSPIM_PCR_IOHSRC_1) == (value & OCTOSPIM_PCR_IOHSRC_1)) + { + /* The IO High correspond to the instance passed as parameter */ + if ((reg & OCTOSPIM_PCR_IOHSRC_0) == 0U) + { + pCfg->IOHighPort = (OCTOSPIM_PCR_IOLEN | (index + 1U)); + } + else + { + pCfg->IOHighPort = (OCTOSPIM_PCR_IOHEN | (index + 1U)); + } + } + } + } +} +#endif /* OCTOSPIM */ +/** + @endcond + */ + +/** + * @} + */ + +#endif /* HAL_XSPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HSPI || HSPI1 || HSPI2 || OCTOSPI || OCTOSPI1 || OCTOSPI2 */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_xspi.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_xspi.h new file mode 100644 index 00000000000..655df256073 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_hal_xspi.h @@ -0,0 +1,1373 @@ +/** + ****************************************************************************** + * @file stm32u5xx_hal_xspi.h + * @author MCD Application Team + * @brief Header file of XSPI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32U5xx_HAL_XSPI_H +#define STM32U5xx_HAL_XSPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32u5xx_hal_def.h" +#include "stm32u5xx_ll_dlyb.h" + +#if defined(HSPI) || defined(HSPI1) || defined(HSPI2)|| defined(OCTOSPI) || defined(OCTOSPI1)|| defined(OCTOSPI2) + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ + +/** @addtogroup XSPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup XSPI_Exported_Types XSPI Exported Types + * @{ + */ +#define HAL_XSPI_DLYB_CfgTypeDef LL_DLYB_CfgTypeDef + +/** + * @brief XSPI Init structure definition + */ +typedef struct +{ + uint32_t FifoThresholdByte; /*!< This is the threshold used by the Peripheral to generate the interrupt + indicating that data are available in reception or free place + is available in transmission. + For OCTOSPI, this parameter can be a value between 1 and 32. + For HSPI, this parameter can be a value between 1 and 64 */ + uint32_t MemoryMode; /*!< It Specifies the memory mode. + This parameter can be a value of @ref XSPI_MemoryMode */ + uint32_t MemoryType; /*!< It indicates the external device type connected to the XSPI. + This parameter can be a value of @ref XSPI_MemoryType */ + uint32_t MemorySize; /*!< It defines the size of the external device connected to the XSPI, + it corresponds to the number of address bits required to access + the external device. + This parameter can be a value of @ref XSPI_MemorySize*/ + uint32_t ChipSelectHighTimeCycle; /*!< It defines the minimum number of clocks which the chip select + must remain high between commands. + This parameter can be a value between 1 and 64U */ + uint32_t FreeRunningClock; /*!< It enables or not the free running clock. + This parameter can be a value of @ref XSPI_FreeRunningClock */ + uint32_t ClockMode; /*!< It indicates the level of clock when the chip select is released. + This parameter can be a value of @ref XSPI_ClockMode */ + uint32_t WrapSize; /*!< It indicates the wrap-size corresponding the external device configuration. + This parameter can be a value of @ref XSPI_WrapSize */ + uint32_t ClockPrescaler; /*!< It specifies the prescaler factor used for generating + the external clock based on the AHB clock. + This parameter can be a value between 0 and 255U */ + uint32_t SampleShifting; /*!< It allows to delay to 1/2 cycle the data sampling in order + to take in account external signal delays. + This parameter can be a value of @ref XSPI_SampleShifting */ + uint32_t DelayHoldQuarterCycle; /*!< It allows to hold to 1/4 cycle the data. + This parameter can be a value of @ref XSPI_DelayHoldQuarterCycle */ + uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and + defines the boundary of bytes to release the chip select. + This parameter can be a value of @ref XSPI_ChipSelectBoundary */ + uint32_t DelayBlockBypass; /*!< It enables the delay block bypass, so the sampling is not affected + by the delay block. + This parameter can be a value of @ref XSPI_DelayBlockBypass */ + uint32_t MaxTran; /*!< It enables the communication regulation feature. The chip select is + released every MaxTran+1 bytes when the other XSPI request the access + to the bus. + This parameter can be a value between 0 and 255U */ + uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every + Refresh+1 clock cycles. + This parameter can be a value between 0 and 0xFFFFFFFF */ +} XSPI_InitTypeDef; + +/** + * @brief HAL XSPI Handle Structure definition + */ +#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +typedef struct __XSPI_HandleTypeDef +#else +typedef struct +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ +{ + XSPI_TypeDef *Instance; /*!< XSPI registers base address */ + XSPI_InitTypeDef Init; /*!< XSPI initialization parameters */ + uint8_t *pBuffPtr; /*!< Address of the XSPI buffer for transfer */ + __IO uint32_t XferSize; /*!< Number of data to transfer */ + __IO uint32_t XferCount; /*!< Counter of data transferred */ + DMA_HandleTypeDef *hdmatx; /*!< Handle of the DMA channel used for transmit */ + DMA_HandleTypeDef *hdmarx; /*!< Handle of the DMA channel used for receive */ + __IO uint32_t State; /*!< Internal state of the XSPI HAL driver */ + __IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */ + uint32_t Timeout; /*!< Timeout used for the XSPI external device access */ +#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + void (* ErrorCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* AbortCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* FifoThresholdCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* CmdCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* RxCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* TxCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* RxHalfCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* TxHalfCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* StatusMatchCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* TimeOutCallback)(struct __XSPI_HandleTypeDef *hxspi); + + void (* MspInitCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* MspDeInitCallback)(struct __XSPI_HandleTypeDef *hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ +} XSPI_HandleTypeDef; + +/** + * @brief HAL XSPI Regular Command Structure definition + */ +typedef struct +{ + uint32_t OperationType; /*!< It indicates if the configuration applies to the common registers or + to the registers for the write operation (these registers are only + used for memory-mapped mode). + This parameter can be a value of @ref XSPI_OperationType */ + uint32_t IOSelect; /*!< It indicates the IOs used to exchange data with external memory. + This parameter can be a value of @ref XSPI_IOSelect */ + uint32_t Instruction; /*!< It contains the instruction to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFFU */ + uint32_t InstructionMode; /*!< It indicates the mode of the instruction. + This parameter can be a value of @ref XSPI_InstructionMode */ + uint32_t InstructionWidth; /*!< It indicates the width of the instruction. + This parameter can be a value of @ref XSPI_InstructionWidth */ + uint32_t InstructionDTRMode; /*!< It enables or not the DTR mode for the instruction phase. + This parameter can be a value of @ref XSPI_InstructionDTRMode */ + uint32_t Address; /*!< It contains the address to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t AddressMode; /*!< It indicates the address mode. Address mode precises number of lines + for address (except no address). + This parameter can be a value of @ref XSPI_AddressMode */ + uint32_t AddressWidth; /*!< It indicates the width of the address. + This parameter can be a value of @ref XSPI_AddressWidth */ + uint32_t AddressDTRMode; /*!< It enables or not the DTR mode for the address phase. + This parameter can be a value of @ref XSPI_AddressDTRMode */ + uint32_t AlternateBytes; /*!< It contains the alternate bytes to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes. + This parameter can be a value of @ref XSPI_AlternateBytesMode */ + uint32_t AlternateBytesWidth; /*!< It indicates the width of the alternate bytes. + This parameter can be a value of @ref XSPI_AlternateBytesWidth */ + uint32_t AlternateBytesDTRMode; /*!< It enables or not the DTR mode for the alternate bytes phase. + This parameter can be a value of @ref XSPI_AlternateBytesDTRMode */ + uint32_t DataMode; /*!< It indicates the data mode. Data mode precises number of lines + for data exchange (except no data). + This parameter can be a value of @ref XSPI_DataMode */ + uint32_t DataLength; /*!< It indicates the number of data transferred with this command. + This field is only used for indirect mode. + This parameter can be a value between 1 and 0xFFFFFFFFU */ + uint32_t DataDTRMode; /*!< It enables or not the DTR mode for the data phase. + This parameter can be a value of @ref XSPI_DataDTRMode */ + uint32_t DummyCycles; /*!< It indicates the number of dummy cycles inserted before data phase. + This parameter can be a value between 0 and 31U */ + uint32_t DQSMode; /*!< It enables or not the data strobe management. + This parameter can be a value of @ref XSPI_DQSMode */ + uint32_t SIOOMode; /*!< It enables or not the SIOO mode. When SIOO mode enabled, + instruction will be sent only once. + This parameter can be a value of @ref XSPI_SIOOMode */ +} XSPI_RegularCmdTypeDef; +/** + * @brief HAL XSPI Hyperbus Configuration Structure definition + */ +typedef struct +{ + uint32_t RWRecoveryTimeCycle; /*!< It indicates the number of cycles for the device read write recovery time. + This parameter can be a value between 0 and 255U */ + uint32_t AccessTimeCycle; /*!< It indicates the number of cycles for the device access time. + This parameter can be a value between 0 and 255U */ + uint32_t WriteZeroLatency; /*!< It enables or not the latency for the write access. + This parameter can be a value of @ref XSPI_WriteZeroLatency */ + uint32_t LatencyMode; /*!< It configures the latency mode. + This parameter can be a value of @ref XSPI_LatencyMode */ +} XSPI_HyperbusCfgTypeDef; + +/** + * @brief HAL XSPI Hyperbus Command Structure definition + */ +typedef struct +{ + uint32_t AddressSpace; /*!< It indicates the address space accessed by the command. + This parameter can be a value of @ref XSPI_AddressSpace */ + uint32_t Address; /*!< It contains the address to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t AddressWidth; /*!< It indicates the width of the address. + This parameter can be a value of @ref XSPI_AddressWidth */ + uint32_t DataLength; /*!< It indicates the number of data transferred with this command. + This field is only used for indirect mode. + This parameter can be a value between 1 and 0xFFFFFFFF + In case of autopolling mode, this parameter can be + any value between 1 and 4 */ + uint32_t DQSMode; /*!< It enables or not the data strobe management. + This parameter can be a value of @ref XSPI_DQSMode */ +#if defined(HSPI1) + uint32_t DataMode; /*!< It indicates the data mode. Data mode precises number of lines + for data exchange (except no data). + This parameter can be a value of @ref XSPI_DataMode */ +#endif /* HSPI1 */ +} XSPI_HyperbusCmdTypeDef; + +/** + * @brief HAL XSPI Auto Polling mode configuration structure definition + */ +typedef struct +{ + uint32_t MatchValue; /*!< Specifies the value to be compared with the masked status register to get + a match. + This parameter can be any value between 0 and 0xFFFFFFFFU */ + uint32_t MatchMask; /*!< Specifies the mask to be applied to the status bytes received. + This parameter can be any value between 0 and 0xFFFFFFFFU */ + uint32_t MatchMode; /*!< Specifies the method used for determining a match. + This parameter can be a value of @ref XSPI_MatchMode */ + uint32_t AutomaticStop; /*!< Specifies if automatic polling is stopped after a match. + This parameter can be a value of @ref XSPI_AutomaticStop */ + uint32_t IntervalTime; /*!< Specifies the number of clock cycles between two read during automatic + polling phases. + This parameter can be any value between 0 and 0xFFFFU */ +} XSPI_AutoPollingTypeDef; + +/** + * @brief HAL XSPI Memory Mapped mode configuration structure definition + */ +typedef struct +{ + uint32_t TimeOutActivation; /*!< Specifies if the timeout counter is enabled to release the chip select. + This parameter can be a value of @ref XSPI_TimeOutActivation */ + uint32_t TimeoutPeriodClock; /*!< Specifies the number of clock to wait when the FIFO is full before to + release the chip select. + This parameter can be any value between 0 and 0xFFFFU */ +} XSPI_MemoryMappedTypeDef; + +#if defined(OCTOSPIM) +/** + * @brief HAL XSPI IO Manager Configuration structure definition + */ +typedef struct +{ + uint32_t ClkPort; /*!< It indicates which port of the XSPI IO Manager is used for the CLK pins. + This parameter can be a value between 1 and 8 */ + uint32_t DQSPort; /*!< It indicates which port of the XSPI IO Manager is used for the DQS pin. + This parameter can be a value between 1 and 8, + 0 means that signal not used */ + uint32_t NCSPort; /*!< It indicates which port of the XSPI IO Manager is used for the NCS pin. + This parameter can be a value between 1 and 8 */ + uint32_t IOLowPort; /*!< It indicates which port of the XSPI IO Manager is used for the IO[3:0] pins. + This parameter can be a value of @ref XSPIM_IOPort */ + uint32_t IOHighPort; /*!< It indicates which port of the XSPI IO Manager is used for the IO[7:4] pins. + This parameter can be a value of @ref XSPIM_IOPort */ + uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) + expected if some signals are multiplexed in the XSPI IO Manager with the + other XSPI. + This parameter can be a value between 1 and 256 */ +} XSPIM_CfgTypeDef; + +#endif /* OCTOSPIM */ +#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +/** + * @brief HAL XSPI Callback ID enumeration definition + */ +typedef enum +{ + HAL_XSPI_ERROR_CB_ID = 0x00U, /*!< XSPI Error Callback ID */ + HAL_XSPI_ABORT_CB_ID = 0x01U, /*!< XSPI Abort Callback ID */ + HAL_XSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< XSPI FIFO Threshold Callback ID */ + HAL_XSPI_CMD_CPLT_CB_ID = 0x03U, /*!< XSPI Command Complete Callback ID */ + HAL_XSPI_RX_CPLT_CB_ID = 0x04U, /*!< XSPI Rx Complete Callback ID */ + HAL_XSPI_TX_CPLT_CB_ID = 0x05U, /*!< XSPI Tx Complete Callback ID */ + HAL_XSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< XSPI Rx Half Complete Callback ID */ + HAL_XSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< XSPI Tx Half Complete Callback ID */ + HAL_XSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< XSPI Status Match Callback ID */ + HAL_XSPI_TIMEOUT_CB_ID = 0x09U, /*!< XSPI Timeout Callback ID */ + HAL_XSPI_MSP_INIT_CB_ID = 0x0AU, /*!< XSPI MspInit Callback ID */ + HAL_XSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< XSPI MspDeInit Callback ID */ +} HAL_XSPI_CallbackIDTypeDef; + +/** + * @brief HAL XSPI Callback pointer definition + */ +typedef void (*pXSPI_CallbackTypeDef)(XSPI_HandleTypeDef *hxspi); + +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ +#if defined(HSPI_CALFCR_FINE) +/** + * @brief HAL XSPI High-speed interface calibration structure definition + */ +typedef struct +{ + uint32_t DelayValueType; /*!< It indicates which calibration is concerned by the configuration. + This parameter can be a value of @ref XSPI_DelayType */ + uint32_t FineCalibrationUnit; /*!< It indicates the fine calibration value of the delay. + This parameter can be a value between 0 and 0x7FU */ + uint32_t CoarseCalibrationUnit; /*!< It indicates the coarse calibration value of the delay. + This parameter can be a value between 0 and 0x1FU */ + uint32_t MaxCalibration; /*!< It indicates that the calibration is outside the range of DLL master. + It applies only when the DelayValueType is HAL_XSPI_CAL_FULL_CYCLE_DELAY. + This parameter can be a value of @ref XSPI_MaxCal */ +} XSPI_HSCalTypeDef; + +#endif /* HSPI_CALFCR_FINE */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup XSPI_Exported_Constants XSPI Exported Constants + * @{ + */ + +/** @defgroup XSPI_State XSPI State + * @{ + */ +#define HAL_XSPI_STATE_RESET (0x00000000U) /*!< Initial state */ +#define HAL_XSPI_STATE_READY (0x00000002U) /*!< Driver ready to be used */ +#define HAL_XSPI_STATE_HYPERBUS_INIT (0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */ +#define HAL_XSPI_STATE_CMD_CFG (0x00000004U) /*!< Command (regular or hyperbus) configured, ready for an action */ +#define HAL_XSPI_STATE_READ_CMD_CFG (0x00000014U) /*!< Read command configuration done, not the write command configuration */ +#define HAL_XSPI_STATE_WRITE_CMD_CFG (0x00000024U) /*!< Write command configuration done, not the read command configuration */ +#define HAL_XSPI_STATE_BUSY_CMD (0x00000008U) /*!< Command without data on-going */ +#define HAL_XSPI_STATE_BUSY_TX (0x00000018U) /*!< Indirect Tx on-going */ +#define HAL_XSPI_STATE_BUSY_RX (0x00000028U) /*!< Indirect Rx on-going */ +#define HAL_XSPI_STATE_BUSY_AUTO_POLLING (0x00000048U) /*!< Auto-polling on-going */ +#define HAL_XSPI_STATE_BUSY_MEM_MAPPED (0x00000088U) /*!< Memory-mapped on-going */ +#define HAL_XSPI_STATE_ABORT (0x00000100U) /*!< Abort on-going */ +#define HAL_XSPI_STATE_ERROR (0x00000200U) /*!< Blocking error, driver should be re-initialized */ +/** + * @} + */ + +/** @defgroup XSPI_ErrorCode XSPI Error Code + * @{ + */ +#define HAL_XSPI_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_XSPI_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */ +#define HAL_XSPI_ERROR_TRANSFER (0x00000002U) /*!< Transfer error */ +#define HAL_XSPI_ERROR_DMA (0x00000004U) /*!< DMA transfer error */ +#define HAL_XSPI_ERROR_INVALID_PARAM (0x00000008U) /*!< Invalid parameters error */ +#define HAL_XSPI_ERROR_INVALID_SEQUENCE (0x00000010U) /*!< Sequence is incorrect */ +#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +#define HAL_XSPI_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid callback error */ +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ +/** + * @} + */ + +/** @defgroup XSPI_MemoryMode XSPI Memory Mode + * @{ + */ +#define HAL_XSPI_SINGLE_MEM (0x00000000U) /*!< Dual-memory mode disabled */ +#define HAL_XSPI_DUAL_MEM (XSPI_CR_DMM) /*!< Dual mode enabled */ + +/** + * @} + */ + +/** @defgroup XSPI_MemoryType XSPI Memory Type + * @{ + */ +#define HAL_XSPI_MEMTYPE_MICRON (0x00000000U) /*!< Micron mode */ +#define HAL_XSPI_MEMTYPE_MACRONIX (XSPI_DCR1_MTYP_0) /*!< Macronix mode */ +#define HAL_XSPI_MEMTYPE_APMEM (XSPI_DCR1_MTYP_1) /*!< AP Memory mode */ +#define HAL_XSPI_MEMTYPE_MACRONIX_RAM ((XSPI_DCR1_MTYP_1 | XSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode*/ +#define HAL_XSPI_MEMTYPE_HYPERBUS (XSPI_DCR1_MTYP_2) /*!< Hyperbus mode */ +#define HAL_XSPI_MEMTYPE_APMEM_16BITS ((XSPI_DCR1_MTYP_2 | XSPI_DCR1_MTYP_1)) /*!< AP Memory mode */ + +/** + * @} + */ + +/** @defgroup XSPI_MemorySize XSPI Memory Size + * @{ + */ +#define HAL_XSPI_SIZE_16B (0x00000000U) /*!< 16 bits ( 2 Byte = 2^( 0+1)) */ +#define HAL_XSPI_SIZE_32B (0x00000001U) /*!< 32 bits ( 4 Byte = 2^( 1+1)) */ +#define HAL_XSPI_SIZE_64B (0x00000002U) /*!< 64 bits ( 8 Byte = 2^( 2+1)) */ +#define HAL_XSPI_SIZE_128B (0x00000003U) /*!< 128 bits ( 16 Byte = 2^( 3+1)) */ +#define HAL_XSPI_SIZE_256B (0x00000004U) /*!< 256 bits ( 32 Byte = 2^( 4+1)) */ +#define HAL_XSPI_SIZE_512B (0x00000005U) /*!< 512 bits ( 64 Byte = 2^( 5+1)) */ +#define HAL_XSPI_SIZE_1KB (0x00000006U) /*!< 1 Kbits (128 Byte = 2^( 6+1)) */ +#define HAL_XSPI_SIZE_2KB (0x00000007U) /*!< 2 Kbits (256 Byte = 2^( 7+1)) */ +#define HAL_XSPI_SIZE_4KB (0x00000008U) /*!< 4 Kbits (512 Byte = 2^( 8+1)) */ +#define HAL_XSPI_SIZE_8KB (0x00000009U) /*!< 8 Kbits ( 1 KByte = 2^( 9+1)) */ +#define HAL_XSPI_SIZE_16KB (0x0000000AU) /*!< 16 Kbits ( 2 KByte = 2^(10+1)) */ +#define HAL_XSPI_SIZE_32KB (0x0000000BU) /*!< 32 Kbits ( 4 KByte = 2^(11+1)) */ +#define HAL_XSPI_SIZE_64KB (0x0000000CU) /*!< 64 Kbits ( 8 KByte = 2^(12+1)) */ +#define HAL_XSPI_SIZE_128KB (0x0000000DU) /*!< 128 Kbits ( 16 KByte = 2^(13+1)) */ +#define HAL_XSPI_SIZE_256KB (0x0000000EU) /*!< 256 Kbits ( 32 KByte = 2^(14+1)) */ +#define HAL_XSPI_SIZE_512KB (0x0000000FU) /*!< 512 Kbits ( 64 KByte = 2^(15+1)) */ +#define HAL_XSPI_SIZE_1MB (0x00000010U) /*!< 1 Mbits (128 KByte = 2^(16+1)) */ +#define HAL_XSPI_SIZE_2MB (0x00000011U) /*!< 2 Mbits (256 KByte = 2^(17+1)) */ +#define HAL_XSPI_SIZE_4MB (0x00000012U) /*!< 4 Mbits (512 KByte = 2^(18+1)) */ +#define HAL_XSPI_SIZE_8MB (0x00000013U) /*!< 8 Mbits ( 1 MByte = 2^(19+1)) */ +#define HAL_XSPI_SIZE_16MB (0x00000014U) /*!< 16 Mbits ( 2 MByte = 2^(20+1)) */ +#define HAL_XSPI_SIZE_32MB (0x00000015U) /*!< 32 Mbits ( 4 MByte = 2^(21+1)) */ +#define HAL_XSPI_SIZE_64MB (0x00000016U) /*!< 64 Mbits ( 8 MByte = 2^(22+1)) */ +#define HAL_XSPI_SIZE_128MB (0x00000017U) /*!< 128 Mbits ( 16 MByte = 2^(23+1)) */ +#define HAL_XSPI_SIZE_256MB (0x00000018U) /*!< 256 Mbits ( 32 MByte = 2^(24+1)) */ +#define HAL_XSPI_SIZE_512MB (0x00000019U) /*!< 512 Mbits ( 64 MByte = 2^(25+1)) */ +#define HAL_XSPI_SIZE_1GB (0x0000001AU) /*!< 1 Gbits (128 MByte = 2^(26+1)) */ +#define HAL_XSPI_SIZE_2GB (0x0000001BU) /*!< 2 Gbits (256 MByte = 2^(27+1)) */ +#define HAL_XSPI_SIZE_4GB (0x0000001CU) /*!< 4 Gbits (256 MByte = 2^(28+1)) */ +#define HAL_XSPI_SIZE_8GB (0x0000001DU) /*!< 8 Gbits (256 MByte = 2^(29+1)) */ +#define HAL_XSPI_SIZE_16GB (0x0000001EU) /*!< 16 Gbits (256 MByte = 2^(30+1)) */ +#define HAL_XSPI_SIZE_32GB (0x0000001FU) /*!< 32 Gbits (256 MByte = 2^(31+1)) */ +/** + * @} + */ + +/** @defgroup XSPI_FreeRunningClock XSPI Free Running Clock + * @{ + */ +#define HAL_XSPI_FREERUNCLK_DISABLE (0x00000000U) /*!< CLK is not free running */ +#define HAL_XSPI_FREERUNCLK_ENABLE ((uint32_t)XSPI_DCR1_FRCK) /*!< CLK is always provided (running) */ +/** + * @} + */ + +/** @defgroup XSPI_ClockMode XSPI Clock Mode + * @{ + */ +#define HAL_XSPI_CLOCK_MODE_0 (0x00000000U) /*!< CLK must stay low while nCS is high */ +#define HAL_XSPI_CLOCK_MODE_3 ((uint32_t)XSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */ +/** + * @} + */ + +/** @defgroup XSPI_WrapSize XSPI Wrap-Size + * @{ + */ +#define HAL_XSPI_WRAP_NOT_SUPPORTED (0x00000000U) /*!< wrapped reads are not supported by the memory */ +#define HAL_XSPI_WRAP_16_BYTES ((uint32_t)XSPI_DCR2_WRAPSIZE_1) /*!< external memory supports wrap size of 16 bytes */ +#define HAL_XSPI_WRAP_32_BYTES ((uint32_t)(XSPI_DCR2_WRAPSIZE_0 | XSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes */ +#define HAL_XSPI_WRAP_64_BYTES ((uint32_t)XSPI_DCR2_WRAPSIZE_2) /*!< external memory supports wrap size of 64 bytes */ +#define HAL_XSPI_WRAP_128_BYTES ((uint32_t)(XSPI_DCR2_WRAPSIZE_0 | XSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */ +/** + * @} + */ + +/** @defgroup XSPI_SampleShifting XSPI Sample Shifting + * @{ + */ +#define HAL_XSPI_SAMPLE_SHIFT_NONE (0x00000000U) /*!< No shift */ +#define HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE ((uint32_t)XSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */ +/** + * @} + */ + +/** @defgroup XSPI_DelayHoldQuarterCycle XSPI Delay Hold Quarter Cycle + * @{ + */ +#define HAL_XSPI_DHQC_DISABLE (0x00000000U) /*!< No Delay */ +#define HAL_XSPI_DHQC_ENABLE ((uint32_t)XSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */ +/** + * @} + */ + +/** @defgroup XSPI_ChipSelectBoundary XSPI Chip Select Boundary + * @{ + */ +#define HAL_XSPI_BONDARYOF_NONE (0x00000000U) /*! CS boundary disabled */ +#define HAL_XSPI_BONDARYOF_16B (0x00000001U) /*!< 16 bits ( 2 Byte = 2^(1)) */ +#define HAL_XSPI_BONDARYOF_32B (0x00000002U) /*!< 32 bits ( 4 Byte = 2^(2)) */ +#define HAL_XSPI_BONDARYOF_64B (0x00000003U) /*!< 64 bits ( 8 Byte = 2^(3)) */ +#define HAL_XSPI_BONDARYOF_128B (0x00000004U) /*!< 128 bits ( 16 Byte = 2^(4)) */ +#define HAL_XSPI_BONDARYOF_256B (0x00000005U) /*!< 256 bits ( 32 Byte = 2^(5)) */ +#define HAL_XSPI_BONDARYOF_512B (0x00000006U) /*!< 512 bits ( 64 Byte = 2^(6)) */ +#define HAL_XSPI_BONDARYOF_1KB (0x00000007U) /*!< 1 Kbits (128 Byte = 2^(7)) */ +#define HAL_XSPI_BONDARYOF_2KB (0x00000008U) /*!< 2 Kbits (256 Byte = 2^(8)) */ +#define HAL_XSPI_BONDARYOF_4KB (0x00000009U) /*!< 4 Kbits (512 Byte = 2^(9)) */ +#define HAL_XSPI_BONDARYOF_8KB (0x0000000AU) /*!< 8 Kbits ( 1 KByte = 2^(10)) */ +#define HAL_XSPI_BONDARYOF_16KB (0x0000000BU) /*!< 16 Kbits ( 2 KByte = 2^(11)) */ +#define HAL_XSPI_BONDARYOF_32KB (0x0000000CU) /*!< 32 Kbits ( 4 KByte = 2^(12)) */ +#define HAL_XSPI_BONDARYOF_64KB (0x0000000DU) /*!< 64 Kbits ( 8 KByte = 2^(13)) */ +#define HAL_XSPI_BONDARYOF_128KB (0x0000000EU) /*!< 128 Kbits ( 16 KByte = 2^(14)) */ +#define HAL_XSPI_BONDARYOF_256KB (0x0000000FU) /*!< 256 Kbits ( 32 KByte = 2^(15)) */ +#define HAL_XSPI_BONDARYOF_512KB (0x00000010U) /*!< 512 Kbits ( 64 KByte = 2^(16)) */ +#define HAL_XSPI_BONDARYOF_1MB (0x00000011U) /*!< 1 Mbits (128 KByte = 2^(17)) */ +#define HAL_XSPI_BONDARYOF_2MB (0x00000012U) /*!< 2 Mbits (256 KByte = 2^(18)) */ +#define HAL_XSPI_BONDARYOF_4MB (0x00000013U) /*!< 4 Mbits (512 KByte = 2^(19)) */ +#define HAL_XSPI_BONDARYOF_8MB (0x00000014U) /*!< 8 Mbits ( 1 MByte = 2^(20)) */ +#define HAL_XSPI_BONDARYOF_16MB (0x00000015U) /*!< 16 Mbits ( 2 MByte = 2^(21)) */ +#define HAL_XSPI_BONDARYOF_32MB (0x00000016U) /*!< 32 Mbits ( 4 MByte = 2^(22)) */ +#define HAL_XSPI_BONDARYOF_64MB (0x00000017U) /*!< 64 Mbits ( 8 MByte = 2^(23)) */ +#define HAL_XSPI_BONDARYOF_128MB (0x00000018U) /*!< 128 Mbits ( 16 MByte = 2^(24)) */ +#define HAL_XSPI_BONDARYOF_256MB (0x00000019U) /*!< 256 Mbits ( 32 MByte = 2^(25)) */ +#define HAL_XSPI_BONDARYOF_512MB (0x0000001AU) /*!< 512 Mbits ( 64 MByte = 2^(26)) */ +#define HAL_XSPI_BONDARYOF_1GB (0x0000001BU) /*!< 1 Gbits (128 MByte = 2^(27)) */ +#define HAL_XSPI_BONDARYOF_2GB (0x0000001CU) /*!< 2 Gbits (256 MByte = 2^(28)) */ +#define HAL_XSPI_BONDARYOF_4GB (0x0000001DU) /*!< 4 Gbits (512 MByte = 2^(29)) */ +#define HAL_XSPI_BONDARYOF_8GB (0x0000001EU) /*!< 8 Gbits ( 1 GByte = 2^(30)) */ +#define HAL_XSPI_BONDARYOF_16GB (0x0000001FU) /*!< 16 Gbits ( 2 GByte = 2^(31)) */ +/** + * @} + */ + +/** @defgroup XSPI_DelayBlockBypass XSPI Delay Block Bypaas + * @{ + */ +#define HAL_XSPI_DELAY_BLOCK_ON (0x00000000U) /*!< Sampling clock is delayed by the delay block */ +#define HAL_XSPI_DELAY_BLOCK_BYPASS ((uint32_t)OCTOSPI_DCR1_DLYBYP) /*!< Delay block is bypassed */ +/** + * @} + */ + +/** @defgroup XSPI_OperationType XSPI Operation Type + * @{ + */ +#define HAL_XSPI_OPTYPE_COMMON_CFG (0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */ +#define HAL_XSPI_OPTYPE_READ_CFG (0x00000001U) /*!< Read configuration (memory-mapped mode) */ +#define HAL_XSPI_OPTYPE_WRITE_CFG (0x00000002U) /*!< Write configuration (memory-mapped mode) */ +#define HAL_XSPI_OPTYPE_WRAP_CFG (0x00000003U) /*!< Wrap configuration (memory-mapped mode) */ + +/** + * @} + */ + +/** @defgroup XSPI_IOSelect XSPI IO Select + * @{ + */ +#define HAL_XSPI_SELECT_IO_3_0 (0x00000000U) /*!< Data exchanged over IO[3:0] */ +#if defined(HSPI_CR_MSEL) +#define HAL_XSPI_SELECT_IO_7_4 ((uint32_t)HSPI_CR_MSEL_0 | OCTOSPI_CR_MSEL) /*!< Data exchanged over IO[7:4] */ +#define HAL_XSPI_SELECT_IO_11_8 ((uint32_t)HSPI_CR_MSEL_1) /*!< Data exchanged over IO[11:8] */ +#define HAL_XSPI_SELECT_IO_15_12 ((uint32_t)HSPI_CR_MSEL | OCTOSPI_CR_MSEL) /*!< Data exchanged over IO[15:12] */ +#define HAL_XSPI_SELECT_IO_7_0 (0x00000000U) /*!< Data exchanged over IO[7:0] */ +#define HAL_XSPI_SELECT_IO_15_8 ((uint32_t)HSPI_CR_MSEL_1) /*!< Data exchanged over IO[15:8] */ +#else +#define HAL_XSPI_SELECT_IO_7_4 ((uint32_t)OCTOSPI_CR_MSEL) /*!< Data exchanged over IO[7:4] */ +#define HAL_XSPI_SELECT_IO_7_0 (0x00000000U) /*!< Data exchanged over IO[7:0] */ +#endif /* HSPI_CR_MSEL */ +/** + * @} + */ + +/** @defgroup XSPI_InstructionMode XSPI Instruction Mode + * @{ + */ +#define HAL_XSPI_INSTRUCTION_NONE (0x00000000U) /*!< No instruction */ +#define HAL_XSPI_INSTRUCTION_1_LINE ((uint32_t)XSPI_CCR_IMODE_0) /*!< Instruction on a single line */ +#define HAL_XSPI_INSTRUCTION_2_LINES ((uint32_t)XSPI_CCR_IMODE_1) /*!< Instruction on two lines */ +#define HAL_XSPI_INSTRUCTION_4_LINES ((uint32_t)(XSPI_CCR_IMODE_0 | XSPI_CCR_IMODE_1)) /*!< Instruction on four lines */ +#define HAL_XSPI_INSTRUCTION_8_LINES ((uint32_t)XSPI_CCR_IMODE_2) /*!< Instruction on eight lines */ +/** + * @} + */ + +/** @defgroup XSPI_InstructionWidth XSPI Instruction Width + * @{ + */ +#define HAL_XSPI_INSTRUCTION_8_BITS (0x00000000U) /*!< 8-bit instruction */ +#define HAL_XSPI_INSTRUCTION_16_BITS ((uint32_t)XSPI_CCR_ISIZE_0) /*!< 16-bit instruction */ +#define HAL_XSPI_INSTRUCTION_24_BITS ((uint32_t)XSPI_CCR_ISIZE_1) /*!< 24-bit instruction */ +#define HAL_XSPI_INSTRUCTION_32_BITS ((uint32_t)XSPI_CCR_ISIZE) /*!< 32-bit instruction */ +/** + * @} + */ + +/** @defgroup XSPI_InstructionDTRMode XSPI Instruction DTR Mode + * @{ + */ +#define HAL_XSPI_INSTRUCTION_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for instruction phase */ +#define HAL_XSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)XSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */ +/** + * @} + */ + +/** @defgroup XSPI_AddressMode XSPI Address Mode + * @{ + */ +#define HAL_XSPI_ADDRESS_NONE (0x00000000U) /*!< No address */ +#define HAL_XSPI_ADDRESS_1_LINE ((uint32_t)XSPI_CCR_ADMODE_0) /*!< Address on a single line */ +#define HAL_XSPI_ADDRESS_2_LINES ((uint32_t)XSPI_CCR_ADMODE_1) /*!< Address on two lines */ +#define HAL_XSPI_ADDRESS_4_LINES ((uint32_t)(XSPI_CCR_ADMODE_0 | XSPI_CCR_ADMODE_1)) /*!< Address on four lines */ +#define HAL_XSPI_ADDRESS_8_LINES ((uint32_t)XSPI_CCR_ADMODE_2) /*!< Address on eight lines */ +/** + * @} + */ + +/** @defgroup XSPI_AddressWidth XSPI Address width + * @{ + */ +#define HAL_XSPI_ADDRESS_8_BITS (0x00000000U) /*!< 8-bit address */ +#define HAL_XSPI_ADDRESS_16_BITS ((uint32_t)XSPI_CCR_ADSIZE_0) /*!< 16-bit address */ +#define HAL_XSPI_ADDRESS_24_BITS ((uint32_t)XSPI_CCR_ADSIZE_1) /*!< 24-bit address */ +#define HAL_XSPI_ADDRESS_32_BITS ((uint32_t)XSPI_CCR_ADSIZE) /*!< 32-bit address */ +/** + * @} + */ + +/** @defgroup XSPI_AddressDTRMode XSPI Address DTR Mode + * @{ + */ +#define HAL_XSPI_ADDRESS_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for address phase */ +#define HAL_XSPI_ADDRESS_DTR_ENABLE ((uint32_t)XSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */ +/** + * @} + */ + +/** @defgroup XSPI_AlternateBytesMode XSPI Alternate Bytes Mode + * @{ + */ +#define HAL_XSPI_ALT_BYTES_NONE (0x00000000U) /*!< No alternate bytes */ +#define HAL_XSPI_ALT_BYTES_1_LINE ((uint32_t)XSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */ +#define HAL_XSPI_ALT_BYTES_2_LINES ((uint32_t)XSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */ +#define HAL_XSPI_ALT_BYTES_4_LINES ((uint32_t)(XSPI_CCR_ABMODE_0 | XSPI_CCR_ABMODE_1)) /*!< Alternate bytes on four lines */ +#define HAL_XSPI_ALT_BYTES_8_LINES ((uint32_t)XSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */ +/** + * @} + */ + +/** @defgroup XSPI_AlternateBytesWidth XSPI Alternate Bytes Width + * @{ + */ +#define HAL_XSPI_ALT_BYTES_8_BITS (0x00000000U) /*!< 8-bit alternate bytes */ +#define HAL_XSPI_ALT_BYTES_16_BITS ((uint32_t)XSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */ +#define HAL_XSPI_ALT_BYTES_24_BITS ((uint32_t)XSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */ +#define HAL_XSPI_ALT_BYTES_32_BITS ((uint32_t)XSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */ +/** + * @} + */ + +/** @defgroup XSPI_AlternateBytesDTRMode XSPI Alternate Bytes DTR Mode + * @{ + */ +#define HAL_XSPI_ALT_BYTES_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for alternate bytes phase */ +#define HAL_XSPI_ALT_BYTES_DTR_ENABLE ((uint32_t)XSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */ +/** + * @} + */ + +/** @defgroup XSPI_DataMode XSPI Data Mode + * @{ + */ +#define HAL_XSPI_DATA_NONE (0x00000000U) /*!< No data */ +#define HAL_XSPI_DATA_1_LINE ((uint32_t)XSPI_CCR_DMODE_0) /*!< Data on a single line */ +#define HAL_XSPI_DATA_2_LINES ((uint32_t)XSPI_CCR_DMODE_1) /*!< Data on two lines */ +#define HAL_XSPI_DATA_4_LINES ((uint32_t)(XSPI_CCR_DMODE_0 | XSPI_CCR_DMODE_1)) /*!< Data on four lines */ +#define HAL_XSPI_DATA_8_LINES ((uint32_t)XSPI_CCR_DMODE_2) /*!< Data on eight lines */ +#if defined(HSPI_CR_MSEL) +#define HAL_XSPI_DATA_16_LINES ((uint32_t)(XSPI_CCR_DMODE_0 | XSPI_CCR_DMODE_2)) /*!< Data on sixteen lines valid for HSPI only */ +#endif /* 16BITS_AVAILABILITY */ +/** + * @} + */ + +/** @defgroup XSPI_DataDTRMode XSPI Data DTR Mode + * @{ + */ +#define HAL_XSPI_DATA_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for data phase */ +#define HAL_XSPI_DATA_DTR_ENABLE ((uint32_t)XSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */ +/** + * @} + */ + +/** @defgroup XSPI_DQSMode XSPI DQS Mode + * @{ + */ +#define HAL_XSPI_DQS_DISABLE (0x00000000U) /*!< DQS disabled */ +#define HAL_XSPI_DQS_ENABLE ((uint32_t)XSPI_CCR_DQSE) /*!< DQS enabled */ +/** + * @} + */ + +/** @defgroup XSPI_SIOOMode XSPI SIOO Mode + * @{ + */ +#define HAL_XSPI_SIOO_INST_EVERY_CMD (0x00000000U) /*!< Send instruction on every transaction */ +#define HAL_XSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)XSPI_CCR_SIOO) /*!< Send instruction only for the first command */ +/** + * @} + */ + +/** @defgroup XSPI_WriteZeroLatency XSPI Hyperbus Write Zero Latency Activation + * @{ + */ +#define HAL_XSPI_LATENCY_ON_WRITE (0x00000000U) /*!< Latency on write accesses */ +#define HAL_XSPI_NO_LATENCY_ON_WRITE ((uint32_t)XSPI_HLCR_WZL) /*!< No latency on write accesses */ +/** + * @} + */ + +/** @defgroup XSPI_LatencyMode XSPI Hyperbus Latency Mode + * @{ + */ +#define HAL_XSPI_VARIABLE_LATENCY (0x00000000U) /*!< Variable initial latency */ +#define HAL_XSPI_FIXED_LATENCY ((uint32_t)XSPI_HLCR_LM) /*!< Fixed latency */ +/** + * @} + */ + +/** @defgroup XSPI_AddressSpace XSPI Hyperbus Address Space + * @{ + */ +#define HAL_XSPI_MEMORY_ADDRESS_SPACE (0x00000000U) /*!< HyperBus memory mode */ +#define HAL_XSPI_REGISTER_ADDRESS_SPACE ((uint32_t)XSPI_DCR1_MTYP_0) /*!< HyperBus register mode */ +/** + * @} + */ + +/** @defgroup XSPI_MatchMode XSPI Match Mode + * @{ + */ +#define HAL_XSPI_MATCH_MODE_AND (0x00000000U) /*!< AND match mode between unmasked bits */ +#define HAL_XSPI_MATCH_MODE_OR ((uint32_t)XSPI_CR_PMM) /*!< OR match mode between unmasked bits */ +/** + * @} + */ + +/** @defgroup XSPI_AutomaticStop XSPI Automatic Stop + * @{ + */ +#define HAL_XSPI_AUTOMATIC_STOP_DISABLE (0x00000000U) /*!< AutoPolling stops only with abort or XSPI disabling */ +#define HAL_XSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)XSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */ +/** + * @} + */ + +/** @defgroup XSPI_TimeOutActivation XSPI Timeout Activation + * @{ + */ +#define HAL_XSPI_TIMEOUT_COUNTER_DISABLE (0x00000000U) /*!< Timeout counter disabled, nCS remains active */ +#define HAL_XSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)XSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */ +/** + * @} + */ + +/** @defgroup XSPI_Flags XSPI Flags + * @{ + */ +#define HAL_XSPI_FLAG_BUSY XSPI_SR_BUSY /*!< Busy flag: operation is ongoing */ +#define HAL_XSPI_FLAG_TO XSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode */ +#define HAL_XSPI_FLAG_SM XSPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode */ +#define HAL_XSPI_FLAG_FT XSPI_SR_FTF /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete */ +#define HAL_XSPI_FLAG_TC XSPI_SR_TCF /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */ +#define HAL_XSPI_FLAG_TE XSPI_SR_TEF /*!< Transfer error flag: invalid address is being accessed */ +/** + * @} + */ + +/** @defgroup XSPI_Interrupts XSPI Interrupts + * @{ + */ +#define HAL_XSPI_IT_TO XSPI_CR_TOIE /*!< Interrupt on the timeout flag */ +#define HAL_XSPI_IT_SM XSPI_CR_SMIE /*!< Interrupt on the status match flag */ +#define HAL_XSPI_IT_FT XSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */ +#define HAL_XSPI_IT_TC XSPI_CR_TCIE /*!< Interrupt on the transfer complete flag */ +#define HAL_XSPI_IT_TE XSPI_CR_TEIE /*!< Interrupt on the transfer error flag */ +/** + * @} + */ + +/** @defgroup XSPI_Timeout_definition XSPI Timeout definition + * @{ + */ +#define HAL_XSPI_TIMEOUT_DEFAULT_VALUE (5000U) /* 5 s */ +/** + * @} + */ + +#if defined(OCTOSPIM) +/** @defgroup XSPIM_IOPort XSPI IO Manager IO Port + * @{ + */ +#define HAL_XSPIM_IOPORT_NONE (0x00000000U) /*!< IOs not used */ +#define HAL_XSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U)) /*!< Port 1 - IO[3:0] */ +#define HAL_XSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U)) /*!< Port 1 - IO[7:4] */ +#define HAL_XSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U)) /*!< Port 2 - IO[3:0] */ +#define HAL_XSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2U)) /*!< Port 2 - IO[7:4] */ +#define HAL_XSPIM_IOPORT_3_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x3U)) /*!< Port 3 - IO[3:0] */ +#define HAL_XSPIM_IOPORT_3_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x3U)) /*!< Port 3 - IO[7:4] */ +#define HAL_XSPIM_IOPORT_4_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x4U)) /*!< Port 4 - IO[3:0] */ +#define HAL_XSPIM_IOPORT_4_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x4U)) /*!< Port 4 - IO[7:4] */ +#define HAL_XSPIM_IOPORT_5_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x5U)) /*!< Port 5 - IO[3:0] */ +#define HAL_XSPIM_IOPORT_5_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x5U)) /*!< Port 5 - IO[7:4] */ +#define HAL_XSPIM_IOPORT_6_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x6U)) /*!< Port 6 - IO[3:0] */ +#define HAL_XSPIM_IOPORT_6_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x6U)) /*!< Port 6 - IO[7:4] */ +#define HAL_XSPIM_IOPORT_7_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x7U)) /*!< Port 7 - IO[3:0] */ +#define HAL_XSPIM_IOPORT_7_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x7U)) /*!< Port 7 - IO[7:4] */ +#define HAL_XSPIM_IOPORT_8_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x8U)) /*!< Port 8 - IO[3:0] */ +#define HAL_XSPIM_IOPORT_8_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x8U)) /*!< Port 8 - IO[7:4] */ +/** + * @} + */ + +#endif /* OCTOSPIM */ +#if defined(HSPI_CALFCR_FINE) + +/** @defgroup XSPI_DelayType XSPI Calibration Delay Type + * @{ + */ +#define HAL_XSPI_CAL_FULL_CYCLE_DELAY (0x00000000U) /*!< Delay value equivalent to full memory-clock cycle */ +#define HAL_XSPI_CAL_FEEDBACK_CLK_DELAY (0x00000001U) /*!< Delay value for the feedback clock when reading without DQS */ +#define HAL_XSPI_CAL_DATA_OUTPUT_DELAY (0x00000002U) /*!< Delay value for output data in DDR mode for write operations */ +#define HAL_XSPI_CAL_DQS_INPUT_DELAY (0x00000003U) /*!< Delay value for DQS input when sampling data for read operations */ +/** + * @} + */ + +/** @defgroup XSPI_MaxCal XSPI Calibration Maximal Value + * @{ + */ +#define HAL_XSPI_MAXCAL_NOT_REACHED (0x00000000U) /*!< Memory-clock perido inside the range of DLL master */ +#define HAL_XSPI_MAXCAL_REACHED ((uint32_t)HSPI_CALFCR_CALMAX) /*!< Memory-clock period outside the range of DLL master (max delay values used) */ +/** + * @} + */ + +#endif /* HSPI_CALFCR_FINE */ +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup XSPI_Exported_Macros XSPI Exported Macros + * @{ + */ +/** @brief Reset XSPI handle state. + * @param __HANDLE__ specifies the XSPI Handle. + * @retval None + */ +#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +#define HAL_XSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_XSPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define HAL_XSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_XSPI_STATE_RESET) +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + +/** @brief Enable the XSPI peripheral. + * @param __HANDLE__ specifies the XSPI Handle. + * @retval None + */ +#define HAL_XSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, XSPI_CR_EN) + +/** @brief Disable the XSPI peripheral. + * @param __HANDLE__ specifies the XSPI Handle. + * @retval None + */ +#define HAL_XSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, XSPI_CR_EN) + +/** @brief Enable the specified XSPI interrupt. + * @param __HANDLE__ specifies the XSPI Handle. + * @param __INTERRUPT__ specifies the XSPI interrupt source to enable. + * This parameter can be one of the following values: + * @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt + * @arg HAL_XSPI_IT_SM: XSPI Status match interrupt + * @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt + * @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt + * @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt + * @retval None + */ +#define HAL_XSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) + +/** @brief Disable the specified XSPI interrupt. + * @param __HANDLE__ specifies the XSPI Handle. + * @param __INTERRUPT__ specifies the XSPI interrupt source to disable. + * This parameter can be one of the following values: + * @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt + * @arg HAL_XSPI_IT_SM: XSPI Status match interrupt + * @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt + * @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt + * @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt + * @retval None + */ +#define HAL_XSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) + +/** @brief Check whether the specified XSPI interrupt source is enabled or not. + * @param __HANDLE__ specifies the XSPI Handle. + * @param __INTERRUPT__ specifies the XSPI interrupt source to check. + * This parameter can be one of the following values: + * @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt + * @arg HAL_XSPI_IT_SM: XSPI Status match interrupt + * @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt + * @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt + * @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define HAL_XSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\ + == (__INTERRUPT__)) + +/** + * @brief Check whether the selected XSPI flag is set or not. + * @param __HANDLE__ specifies the XSPI Handle. + * @param __FLAG__ specifies the XSPI flag to check. + * This parameter can be one of the following values: + * @arg HAL_XSPI_FLAG_BUSY: XSPI Busy flag + * @arg HAL_XSPI_FLAG_TO: XSPI Timeout flag + * @arg HAL_XSPI_FLAG_SM: XSPI Status match flag + * @arg HAL_XSPI_FLAG_FT: XSPI FIFO threshold flag + * @arg HAL_XSPI_FLAG_TC: XSPI Transfer complete flag + * @arg HAL_XSPI_FLAG_TE: XSPI Transfer error flag + * @retval None + */ +#define HAL_XSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \ + != 0U) ? SET : RESET) + +/** @brief Clears the specified XSPI's flag status. + * @param __HANDLE__ specifies the XSPI Handle. + * @param __FLAG__ specifies the XSPI clear register flag that needs to be set + * This parameter can be one of the following values: + * @arg HAL_XSPI_FLAG_TO: XSPI Timeout flag + * @arg HAL_XSPI_FLAG_SM: XSPI Status match flag + * @arg HAL_XSPI_FLAG_TC: XSPI Transfer complete flag + * @arg HAL_XSPI_FLAG_TE: XSPI Transfer error flag + * @retval None + */ +#define HAL_XSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup XSPI_Exported_Functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +/** @addtogroup XSPI_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_XSPI_Init(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_MspInit(XSPI_HandleTypeDef *hxspi); +HAL_StatusTypeDef HAL_XSPI_DeInit(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_MspDeInit(XSPI_HandleTypeDef *hxspi); + +/** + * @} + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup XSPI_Exported_Functions_Group2 + * @{ + */ +/* XSPI IRQ handler function */ +void HAL_XSPI_IRQHandler(XSPI_HandleTypeDef *hxspi); + +/* XSPI command configuration functions */ +HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd, + uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd); +HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCfgTypeDef *const pCfg, + uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCmdTypeDef *const pCmd, + uint32_t Timeout); + +/* XSPI indirect mode functions */ +HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); +HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); +HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); +HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); + +/* XSPI status flag polling mode functions */ +HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg, + uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg); + +/* XSPI memory-mapped mode functions */ +HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, XSPI_MemoryMappedTypeDef *const pCfg); + +/* Callback functions in non-blocking modes ***********************************/ +void HAL_XSPI_ErrorCallback(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_AbortCpltCallback(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_FifoThresholdCallback(XSPI_HandleTypeDef *hxspi); + +/* XSPI indirect mode Callback functions */ +void HAL_XSPI_CmdCpltCallback(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_RxCpltCallback(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_TxCpltCallback(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_RxHalfCpltCallback(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_TxHalfCpltCallback(XSPI_HandleTypeDef *hxspi); + +/* XSPI status flag polling mode functions */ +void HAL_XSPI_StatusMatchCallback(XSPI_HandleTypeDef *hxspi); + +/* XSPI memory-mapped mode functions */ +void HAL_XSPI_TimeOutCallback(XSPI_HandleTypeDef *hxspi); + +#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +/* XSPI callback registering/unregistering */ +HAL_StatusTypeDef HAL_XSPI_RegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID, + pXSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + +/** + * @} + */ + +/* Peripheral Control and State functions ************************************/ +/** @addtogroup XSPI_Exported_Functions_Group3 + * @{ + */ +HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi); +HAL_StatusTypeDef HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi); +HAL_StatusTypeDef HAL_XSPI_SetFifoThreshold(XSPI_HandleTypeDef *hxspi, uint32_t Threshold); +uint32_t HAL_XSPI_GetFifoThreshold(const XSPI_HandleTypeDef *hxspi); +HAL_StatusTypeDef HAL_XSPI_SetMemoryType(XSPI_HandleTypeDef *hxspi, uint32_t Type); +HAL_StatusTypeDef HAL_XSPI_SetDeviceSize(XSPI_HandleTypeDef *hxspi, uint32_t Size); +HAL_StatusTypeDef HAL_XSPI_SetClockPrescaler(XSPI_HandleTypeDef *hxspi, uint32_t Prescaler); +HAL_StatusTypeDef HAL_XSPI_SetTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Timeout); +uint32_t HAL_XSPI_GetError(const XSPI_HandleTypeDef *hxspi); +uint32_t HAL_XSPI_GetState(const XSPI_HandleTypeDef *hxspi); + +/** + * @} + */ + +#if defined(OCTOSPIM) +/* XSPI IO Manager configuration function ************************************/ +/** @addtogroup XSPI_Exported_Functions_Group4 + * @{ + */ +HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *hxspi, XSPIM_CfgTypeDef *const pCfg, uint32_t Timeout); + +/** + * @} + */ + +#endif /* OCTOSPIM */ +/* XSPI Delay Block functions ************************************/ +#if defined(OCTOSPIM) +/** @addtogroup XSPI_Exported_Functions_Group5 Delay Block function + * @{ + */ +#endif /* OCTOSPIM */ + +HAL_StatusTypeDef HAL_XSPI_DLYB_SetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *const pdlyb_cfg); +HAL_StatusTypeDef HAL_XSPI_DLYB_GetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *const pdlyb_cfg); +HAL_StatusTypeDef HAL_XSPI_DLYB_GetClockPeriod(XSPI_HandleTypeDef *hxspi, + HAL_XSPI_DLYB_CfgTypeDef *const pdlyb_cfg); + +/** + * @} + */ + +#if defined(HSPI_CALFCR_FINE) +/* XSPI high-speed interface and calibration functions ***********************/ +/** @addtogroup XSPI_Exported_Functions_Group6 + * @{ + */ +HAL_StatusTypeDef HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg); +HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg); + +/** + * @} + */ + +#endif /* HSPI_CALFCR_FINE */ +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** + @cond 0 + */ +#define IS_OCTOSPI_FIFO_THRESHOLD_BYTE(THRESHOLD) (((THRESHOLD) >= 1U) &&\ + ((THRESHOLD) <= ((OCTOSPI_CR_FTHRES >> OCTOSPI_CR_FTHRES_Pos)+1U))) + + +#if defined(HSPI1) +#define IS_HSPI_FIFO_THRESHOLD_BYTE(THRESHOLD) (((THRESHOLD) >= 1U) &&\ + ((THRESHOLD) <= ((HSPI_CR_FTHRES >> HSPI_CR_FTHRES_Pos)+1U))) +#endif /* HSPI1 */ +#define IS_XSPI_MEMORY_MODE(MODE) (((MODE) == HAL_XSPI_SINGLE_MEM) || \ + ((MODE) == HAL_XSPI_DUAL_MEM)) + +#define IS_XSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_XSPI_MEMTYPE_MICRON) || \ + ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX) || \ + ((TYPE) == HAL_XSPI_MEMTYPE_APMEM) || \ + ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX_RAM) || \ + ((TYPE) == HAL_XSPI_MEMTYPE_HYPERBUS) || \ + ((TYPE) == HAL_XSPI_MEMTYPE_APMEM_16BITS)) + +#define IS_XSPI_MEMORY_SIZE(SIZE) (((SIZE) == HAL_XSPI_SIZE_16B) || \ + ((SIZE) == HAL_XSPI_SIZE_32B) || \ + ((SIZE) == HAL_XSPI_SIZE_64B) || \ + ((SIZE) == HAL_XSPI_SIZE_128B) || \ + ((SIZE) == HAL_XSPI_SIZE_256B) || \ + ((SIZE) == HAL_XSPI_SIZE_512B) || \ + ((SIZE) == HAL_XSPI_SIZE_1KB) || \ + ((SIZE) == HAL_XSPI_SIZE_2KB) || \ + ((SIZE) == HAL_XSPI_SIZE_4KB) || \ + ((SIZE) == HAL_XSPI_SIZE_8KB) || \ + ((SIZE) == HAL_XSPI_SIZE_16KB) || \ + ((SIZE) == HAL_XSPI_SIZE_32KB) || \ + ((SIZE) == HAL_XSPI_SIZE_64KB) || \ + ((SIZE) == HAL_XSPI_SIZE_128KB) || \ + ((SIZE) == HAL_XSPI_SIZE_256KB) || \ + ((SIZE) == HAL_XSPI_SIZE_512KB) || \ + ((SIZE) == HAL_XSPI_SIZE_1MB) || \ + ((SIZE) == HAL_XSPI_SIZE_2MB) || \ + ((SIZE) == HAL_XSPI_SIZE_4MB) || \ + ((SIZE) == HAL_XSPI_SIZE_8MB) || \ + ((SIZE) == HAL_XSPI_SIZE_16MB) || \ + ((SIZE) == HAL_XSPI_SIZE_32MB) || \ + ((SIZE) == HAL_XSPI_SIZE_64MB) || \ + ((SIZE) == HAL_XSPI_SIZE_128MB) || \ + ((SIZE) == HAL_XSPI_SIZE_256MB) || \ + ((SIZE) == HAL_XSPI_SIZE_512MB) || \ + ((SIZE) == HAL_XSPI_SIZE_1GB) || \ + ((SIZE) == HAL_XSPI_SIZE_2GB) || \ + ((SIZE) == HAL_XSPI_SIZE_4GB) || \ + ((SIZE) == HAL_XSPI_SIZE_8GB) || \ + ((SIZE) == HAL_XSPI_SIZE_16GB) || \ + ((SIZE) == HAL_XSPI_SIZE_32GB)) + +#define IS_XSPI_CS_HIGH_TIME_CYCLE(TIME) (((TIME) >= 1U) && ((TIME) <= 64U)) + +#define IS_XSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_XSPI_FREERUNCLK_DISABLE) || \ + ((CLK) == HAL_XSPI_FREERUNCLK_ENABLE)) + +#define IS_XSPI_CLOCK_MODE(MODE) (((MODE) == HAL_XSPI_CLOCK_MODE_0) || \ + ((MODE) == HAL_XSPI_CLOCK_MODE_3)) + +#define IS_XSPI_WRAP_SIZE(SIZE) (((SIZE) == HAL_XSPI_WRAP_NOT_SUPPORTED) || \ + ((SIZE) == HAL_XSPI_WRAP_16_BYTES) || \ + ((SIZE) == HAL_XSPI_WRAP_32_BYTES) || \ + ((SIZE) == HAL_XSPI_WRAP_64_BYTES) || \ + ((SIZE) == HAL_XSPI_WRAP_128_BYTES)) + +#define IS_XSPI_CLK_PRESCALER(PRESCALER) ((PRESCALER) <= 255U) + +#define IS_XSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_XSPI_SAMPLE_SHIFT_NONE) || \ + ((CYCLE) == HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE)) + +#define IS_XSPI_DHQC(CYCLE) (((CYCLE) == HAL_XSPI_DHQC_DISABLE) || \ + ((CYCLE) == HAL_XSPI_DHQC_ENABLE)) + +#define IS_XSPI_CS_BOUND(SIZE) (((SIZE) == HAL_XSPI_BONDARYOF_NONE) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_16B) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_32B) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_64B) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_128B) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_256B) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_512B) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_1KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_2KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_4KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_8KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_16KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_32KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_64KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_128KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_256KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_512KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_1MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_2MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_4MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_8MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_16MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_32MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_64MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_128MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_256MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_512MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_1GB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_2GB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_4GB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_8GB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_16GB)) + +#define IS_XSPI_DLYB_BYPASS(DLYB) (((DLYB) == HAL_XSPI_DELAY_BLOCK_ON) || \ + ((DLYB) == HAL_XSPI_DELAY_BLOCK_BYPASS)) + + +#define IS_XSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U) + +#define IS_XSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_XSPI_OPTYPE_COMMON_CFG) || \ + ((TYPE) == HAL_XSPI_OPTYPE_READ_CFG) || \ + ((TYPE) == HAL_XSPI_OPTYPE_WRITE_CFG) || \ + ((TYPE) == HAL_XSPI_OPTYPE_WRAP_CFG)) + +#define IS_OCTOSPI_IO_SELECT(MEMSEL) (((MEMSEL) == HAL_XSPI_SELECT_IO_3_0) || \ + ((MEMSEL) == HAL_XSPI_SELECT_IO_7_4) || \ + ((MEMSEL) == HAL_XSPI_SELECT_IO_7_0)) + +#if defined(HSPI1) +#define IS_HSPI_IO_SELECT(MEMSEL) (((MEMSEL) == HAL_XSPI_SELECT_IO_3_0) || \ + ((MEMSEL) == HAL_XSPI_SELECT_IO_7_4) || \ + ((MEMSEL) == HAL_XSPI_SELECT_IO_11_8) || \ + ((MEMSEL) == HAL_XSPI_SELECT_IO_15_12) || \ + ((MEMSEL) == HAL_XSPI_SELECT_IO_7_0) || \ + ((MEMSEL) == HAL_XSPI_SELECT_IO_15_8)) + +#endif /* HSPI1 */ +#define IS_XSPI_INSTRUCTION(OPCODE) ((OPCODE) <= 0xFFFFFFFFU) + +#define IS_XSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_XSPI_INSTRUCTION_NONE) || \ + ((MODE) == HAL_XSPI_INSTRUCTION_1_LINE) || \ + ((MODE) == HAL_XSPI_INSTRUCTION_2_LINES) || \ + ((MODE) == HAL_XSPI_INSTRUCTION_4_LINES) || \ + ((MODE) == HAL_XSPI_INSTRUCTION_8_LINES)) + +#define IS_XSPI_INSTRUCTION_WIDTH(WIDTH) (((WIDTH) == HAL_XSPI_INSTRUCTION_8_BITS) || \ + ((WIDTH) == HAL_XSPI_INSTRUCTION_16_BITS) || \ + ((WIDTH) == HAL_XSPI_INSTRUCTION_24_BITS) || \ + ((WIDTH) == HAL_XSPI_INSTRUCTION_32_BITS)) + +#define IS_XSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_XSPI_INSTRUCTION_DTR_DISABLE) || \ + ((MODE) == HAL_XSPI_INSTRUCTION_DTR_ENABLE)) + +#define IS_XSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_XSPI_ADDRESS_NONE) || \ + ((MODE) == HAL_XSPI_ADDRESS_1_LINE) || \ + ((MODE) == HAL_XSPI_ADDRESS_2_LINES) || \ + ((MODE) == HAL_XSPI_ADDRESS_4_LINES) || \ + ((MODE) == HAL_XSPI_ADDRESS_8_LINES)) + +#define IS_XSPI_ADDRESS_WIDTH(WIDTH) (((WIDTH) == HAL_XSPI_ADDRESS_8_BITS) || \ + ((WIDTH) == HAL_XSPI_ADDRESS_16_BITS) || \ + ((WIDTH) == HAL_XSPI_ADDRESS_24_BITS) || \ + ((WIDTH) == HAL_XSPI_ADDRESS_32_BITS)) + +#define IS_XSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_XSPI_ADDRESS_DTR_DISABLE) || \ + ((MODE) == HAL_XSPI_ADDRESS_DTR_ENABLE)) + +#define IS_XSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_XSPI_ALT_BYTES_NONE) || \ + ((MODE) == HAL_XSPI_ALT_BYTES_1_LINE) || \ + ((MODE) == HAL_XSPI_ALT_BYTES_2_LINES) || \ + ((MODE) == HAL_XSPI_ALT_BYTES_4_LINES) || \ + ((MODE) == HAL_XSPI_ALT_BYTES_8_LINES)) + +#define IS_XSPI_ALT_BYTES_WIDTH(WIDTH) (((WIDTH) == HAL_XSPI_ALT_BYTES_8_BITS) || \ + ((WIDTH) == HAL_XSPI_ALT_BYTES_16_BITS) || \ + ((WIDTH) == HAL_XSPI_ALT_BYTES_24_BITS) || \ + ((WIDTH) == HAL_XSPI_ALT_BYTES_32_BITS)) + +#define IS_XSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_XSPI_ALT_BYTES_DTR_DISABLE) || \ + ((MODE) == HAL_XSPI_ALT_BYTES_DTR_ENABLE)) + +#define IS_OCTOSPI_DATA_MODE(MODE) (((MODE) == HAL_XSPI_DATA_NONE) || \ + ((MODE) == HAL_XSPI_DATA_1_LINE) || \ + ((MODE) == HAL_XSPI_DATA_2_LINES) || \ + ((MODE) == HAL_XSPI_DATA_4_LINES) || \ + ((MODE) == HAL_XSPI_DATA_8_LINES)) + +#if defined(HSPI1) +#define IS_HSPI_DATA_MODE(TYPE,MODE) (((TYPE) == (HAL_XSPI_MEMTYPE_HYPERBUS)) ? \ + (((MODE) == HAL_XSPI_DATA_8_LINES) || \ + ((MODE) == HAL_XSPI_DATA_16_LINES)): \ + (((MODE) == HAL_XSPI_DATA_NONE) || \ + ((MODE) == HAL_XSPI_DATA_1_LINE) || \ + ((MODE) == HAL_XSPI_DATA_2_LINES) || \ + ((MODE) == HAL_XSPI_DATA_4_LINES) || \ + ((MODE) == HAL_XSPI_DATA_8_LINES) || \ + ((MODE) == HAL_XSPI_DATA_16_LINES))) + +#endif /* HSPI1 */ +#define IS_XSPI_DATA_LENGTH(NUMBER) ((NUMBER) >= 1U) + +#define IS_XSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_XSPI_DATA_DTR_DISABLE) || \ + ((MODE) == HAL_XSPI_DATA_DTR_ENABLE)) + +#define IS_XSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U) + +#define IS_XSPI_DQS_MODE(MODE) (((MODE) == HAL_XSPI_DQS_DISABLE) || \ + ((MODE) == HAL_XSPI_DQS_ENABLE)) + +#define IS_XSPI_SIOO_MODE(MODE) (((MODE) == HAL_XSPI_SIOO_INST_EVERY_CMD) || \ + ((MODE) == HAL_XSPI_SIOO_INST_ONLY_FIRST_CMD)) + +#define IS_XSPI_RW_RECOVERY_TIME_CYCLE(CYCLE) ((CYCLE) <= 255U) + +#define IS_XSPI_ACCESS_TIME_CYCLE(CYCLE) ((CYCLE) <= 255U) + +#define IS_XSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_XSPI_LATENCY_ON_WRITE) || \ + ((MODE) == HAL_XSPI_NO_LATENCY_ON_WRITE)) + +#define IS_XSPI_LATENCY_MODE(MODE) (((MODE) == HAL_XSPI_VARIABLE_LATENCY) || \ + ((MODE) == HAL_XSPI_FIXED_LATENCY)) + +#define IS_XSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_XSPI_MEMORY_ADDRESS_SPACE) || \ + ((SPACE) == HAL_XSPI_REGISTER_ADDRESS_SPACE)) + +#define IS_XSPI_MATCH_MODE(MODE) (((MODE) == HAL_XSPI_MATCH_MODE_AND) || \ + ((MODE) == HAL_XSPI_MATCH_MODE_OR)) + +#define IS_XSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_XSPI_AUTOMATIC_STOP_ENABLE) || \ + ((MODE) == HAL_XSPI_AUTOMATIC_STOP_DISABLE)) + +#define IS_XSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU) + +#define IS_XSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) + +#define IS_XSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_XSPI_TIMEOUT_COUNTER_DISABLE) || \ + ((MODE) == HAL_XSPI_TIMEOUT_COUNTER_ENABLE)) + +#define IS_XSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) + +#if defined(OCTOSPIM) +#define IS_XSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) + +#define IS_XSPIM_DQS_PORT(NUMBER) ((NUMBER) <= 8U) + +#define IS_XSPIM_IO_PORT(PORT) (((PORT) == HAL_XSPIM_IOPORT_1_LOW) || \ + ((PORT) == HAL_XSPIM_IOPORT_1_HIGH) || \ + ((PORT) == HAL_XSPIM_IOPORT_2_LOW) || \ + ((PORT) == HAL_XSPIM_IOPORT_2_HIGH) || \ + ((PORT) == HAL_XSPIM_IOPORT_3_LOW) || \ + ((PORT) == HAL_XSPIM_IOPORT_3_HIGH) || \ + ((PORT) == HAL_XSPIM_IOPORT_4_LOW) || \ + ((PORT) == HAL_XSPIM_IOPORT_4_HIGH) || \ + ((PORT) == HAL_XSPIM_IOPORT_5_LOW) || \ + ((PORT) == HAL_XSPIM_IOPORT_5_HIGH) || \ + ((PORT) == HAL_XSPIM_IOPORT_6_LOW) || \ + ((PORT) == HAL_XSPIM_IOPORT_6_HIGH) || \ + ((PORT) == HAL_XSPIM_IOPORT_7_LOW) || \ + ((PORT) == HAL_XSPIM_IOPORT_7_HIGH) || \ + ((PORT) == HAL_XSPIM_IOPORT_8_LOW) || \ + ((PORT) == HAL_XSPIM_IOPORT_8_HIGH)) + +#define IS_XSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U)) + +#endif /* OCTOSPIM */ +#define IS_XSPI_DELAY_TYPE(TYPE) (((TYPE) == HAL_XSPI_CAL_FULL_CYCLE_DELAY) || \ + ((TYPE) == HAL_XSPI_CAL_FEEDBACK_CLK_DELAY) || \ + ((TYPE) == HAL_XSPI_CAL_DATA_OUTPUT_DELAY) || \ + ((TYPE) == HAL_XSPI_CAL_DQS_INPUT_DELAY)) + +#define IS_XSPI_FINECAL_VALUE(VALUE) ((VALUE) <= 0x7FU) + +#define IS_XSPI_COARSECAL_VALUE(VALUE) ((VALUE) <= 0x1FU) + +/** + @endcond + */ + +/* End of private macros -----------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HSPI || HSPI1 || HSPI2 || OCTOSPI || OCTOSPI1 || OCTOSPI2 */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5xx_HAL_XSPI_H */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_adc.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_adc.c index 41dbb303b41..385d3ede35a 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_adc.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_adc.c @@ -288,6 +288,52 @@ || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ ) +#if defined(ADC_MULTIMODE_SUPPORT) +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* multimode. */ +#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ + (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ + ) + +#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \ + (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \ + || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_32_10B) \ + || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_8B) \ + ) + +#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \ + (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \ + ) + +#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \ + (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ + || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ + || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ + ) + +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ @@ -313,26 +359,26 @@ * all ADC instances belonging to the common ADC instance. * To de-initialize only 1 ADC instance, use * function @ref LL_ADC_DeInit(). - * @param pADCxyCOMMON ADC common instance + * @param pADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC common registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *pADCxyCOMMON) +ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *pADCxy_COMMON) { /* Check the parameters */ - assert_param(IS_ADC_COMMON_INSTANCE(pADCxyCOMMON)); + assert_param(IS_ADC_COMMON_INSTANCE(pADCxy_COMMON)); - if (pADCxyCOMMON == ADC12_COMMON) + if (pADCxy_COMMON == ADC12_COMMON) { /* Force reset of ADC clock (core clock) */ - LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC1); + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC12); /* Release reset of ADC clock (core clock) */ - LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC1); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC12); } - else /*if ( pADCxyCOMMON == ADC4_COMMON)*/ + else /*if ( pADCxy_COMMON == ADC4_COMMON)*/ { /* Force reset of ADC clock (core clock) */ LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_ADC4); @@ -352,33 +398,76 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *pADCxyCOMMON) * ADC instances state: * All ADC instances belonging to the same ADC common instance * must be disabled. - * @param pADCxyCOMMON ADC common instance + * @param pADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param pADC_CommonInit Pointer to a @ref LL_ADC_CommonInitTypeDef structure + * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC common registers are initialized * - ERROR: ADC common registers are not initialized */ -ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *pADCxyCOMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInit) +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *pADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ - assert_param(IS_ADC_COMMON_INSTANCE(pADCxyCOMMON)); - assert_param(IS_LL_ADC_CLOCK(pADC_CommonInit->CommonClock)); + assert_param(IS_ADC_COMMON_INSTANCE(pADCxy_COMMON)); + assert_param(IS_LL_ADC_CLOCK(pADC_CommonInitStruct->CommonClock)); + +#if defined(ADC_MULTIMODE_SUPPORT) + assert_param(IS_LL_ADC_MULTI_MODE(pADC_CommonInitStruct->Multimode)); + if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + { + assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(pADC_CommonInitStruct->MultiDMATransfer)); + assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(pADC_CommonInitStruct->MultiTwoSamplingDelay)); + } +#endif /* ADC_MULTIMODE_SUPPORT */ /* Note: Hardware constraint (refer to description of functions */ /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ /* On this STM32 series, setting of these features is conditioned to */ /* ADC state: */ /* All ADC instances of the ADC common group must be disabled. */ - if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(pADCxyCOMMON) == 0UL) + if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(pADCxy_COMMON) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - common to several ADC */ /* (all ADC instances belonging to the same ADC common instance) */ /* - Set ADC clock (conversion clock) */ - LL_ADC_SetCommonClock(pADCxyCOMMON, pADC_CommonInit->CommonClock); + /* - multimode (if several ADC instances available on the */ + /* selected device) */ + /* - Set ADC multimode configuration */ + /* - Set ADC multimode DMA transfer */ + /* - Set ADC multimode: delay between 2 sampling phases */ +#if defined(ADC_MULTIMODE_SUPPORT) + if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + { + MODIFY_REG(pADCxy_COMMON->CCR, + ADC_CCR_PRESC + | ADC_CCR_DUAL + | ADC_CCR_DAMDF + | ADC_CCR_DELAY + , + pADC_CommonInitStruct->CommonClock + | pADC_CommonInitStruct->Multimode + | pADC_CommonInitStruct->MultiDMATransfer + | pADC_CommonInitStruct->MultiTwoSamplingDelay + ); + } + else + { + MODIFY_REG(pADCxy_COMMON->CCR, + ADC_CCR_PRESC + | ADC_CCR_DUAL + | ADC_CCR_DAMDF + | ADC_CCR_DELAY + , + pADC_CommonInitStruct->CommonClock + | LL_ADC_MULTI_INDEPENDENT + ); + } +#else + LL_ADC_SetCommonClock(pADCxy_COMMON, pADC_CommonInitStruct->CommonClock); +#endif /* ADC_MULTIMODE_SUPPORT */ } else { @@ -392,17 +481,23 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *pADCxyCOMMON, LL_ADC_CommonIni /** * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. - * @param pADC_CommonInit Pointer to a @ref LL_ADC_CommonInitTypeDef structure + * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure * whose fields will be set to default values. * @retval None */ -void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInit) +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct) { - /* Set pADC_CommonInit fields to default values */ + /* Set pADC_CommonInitStruct fields to default values */ /* Set fields of ADC common */ /* (all ADC instances belonging to the same ADC common instance) */ - pADC_CommonInit->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2; - + pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2; + +#if defined(ADC_MULTIMODE_SUPPORT) + /* Set fields of ADC multimode */ + pADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; + pADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; + pADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE; +#endif /* ADC_MULTIMODE_SUPPORT */ } /** @@ -490,7 +585,6 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *pADCx) (LL_ADC_IT_AWD3 | LL_ADC_IT_AWD2 | LL_ADC_IT_AWD1 - | LL_ADC_IT_JQOVF | LL_ADC_IT_OVR | LL_ADC_IT_JEOS | LL_ADC_IT_JEOC @@ -506,7 +600,6 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *pADCx) (LL_ADC_FLAG_AWD3 | LL_ADC_FLAG_AWD2 | LL_ADC_FLAG_AWD1 - | LL_ADC_FLAG_JQOVF | LL_ADC_FLAG_OVR | LL_ADC_FLAG_JEOS | LL_ADC_FLAG_JEOC @@ -783,11 +876,11 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *pADCx, LL_ADC_InitTypeDef *pADC_InitStruct) else { MODIFY_REG(pADCx->CFGR1, - ADC_CFGR1_RES | ADC4_CFGR1_ALIGN | ADC4_CFGR1_WAIT, - __LL_ADC_RESOLUTION_ADC1_TO_ADC4(pADC_InitStruct->Resolution) - | pADC_InitStruct->DataAlignment + ADC4_CFGR1_ALIGN | ADC4_CFGR1_WAIT, + pADC_InitStruct->DataAlignment | pADC_InitStruct->LowPowerMode ); + LL_ADC_SetResolution(pADCx, pADC_InitStruct->Resolution); } } else @@ -805,7 +898,7 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *pADCx, LL_ADC_InitTypeDef *pADC_InitStruct) * whose fields will be set to default values. * @retval None */ -void LL_ADC_StructInit(ADC_TypeDef *pADCx, LL_ADC_InitTypeDef *pADC_InitStruct) +void LL_ADC_StructInit(const ADC_TypeDef *pADCx, LL_ADC_InitTypeDef *pADC_InitStruct) { /* Set pADC_InitStruct fields to default values */ /* Set fields of ADC instance */ @@ -860,13 +953,7 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *pADCx, LL_ADC_REG_InitTypeDef *pADC_Reg /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(pADCx)); - if (pADCx == ADC1) - { - assert_param(IS_LL_ADC_REG_TRIG_SOURCE(pADC_RegInitStruct->TriggerSource)); - assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength)); - assert_param(IS_LL_ADC_REG_DATA_TRANSFER_MODE(pADC_RegInitStruct->DataTransferMode)); - } - else + if (pADCx == ADC4) { assert_param(IS_LL_ADC4_REG_TRIG_SOURCE(pADC_RegInitStruct->TriggerSource)); assert_param(IS_LL_ADC4_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength)); @@ -883,6 +970,13 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *pADCx, LL_ADC_REG_InitTypeDef *pADC_Reg || (pADC_RegInitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); } } + else /* ADC1 or ADC2 */ + { + assert_param(IS_LL_ADC_REG_TRIG_SOURCE(pADC_RegInitStruct->TriggerSource)); + assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength)); + assert_param(IS_LL_ADC_REG_DATA_TRANSFER_MODE(pADC_RegInitStruct->DataTransferMode)); + } + if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont)); @@ -1015,7 +1109,7 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *pADCx, LL_ADC_REG_InitTypeDef *pADC_Reg * whose fields will be set to default values. * @retval None */ -void LL_ADC_REG_StructInit(ADC_TypeDef *pADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct) +void LL_ADC_REG_StructInit(const ADC_TypeDef *pADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct) { /* Set pADC_RegInitStruct fields to default values */ /* Set fields of ADC group regular */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_adc.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_adc.h index 0b94df71b69..8d97c40f7a7 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_adc.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_adc.h @@ -60,7 +60,11 @@ extern "C" { #define ADC_CALIB_MODE_BINARY_MASK (ADC_CALIB_FACTOR_REGOFFSET_MASK) /* Mask to get binary value of calibration mode: 0 for offset, 1 for linearity */ - +/* Internal algorithm for resolution parameters */ +/* ADC instances ADC1, ADC2 and ADC4 do not have same resolution and same bitfield value for equivalent resolution + in ADC bitfield ADC_CFGR1_RES_1 */ +#define ADC_RESOLUTION_ADC4_PROCESSING (1UL) /* Value to be subtracted to literals LL_ADC_RESOLUTION_xB + to have equivalent setting for ADC4 */ /* Internal mask for ADC group regular sequencer: */ /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ @@ -467,6 +471,10 @@ extern "C" { #define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR1_AWD1EN_Pos) #define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR1_JAWD1EN_Pos) +/* ADC instance differentiation between ADC1 and ADC4 oversampling ratio */ +#define ADC4_OVERSAMPLING_RATIO_PARAMETER (0x80000000UL) +#define ADC4_OVERSAMPLING_RATIO_PARAMETER_MASK (ADC4_OVERSAMPLING_RATIO_PARAMETER) + /* ADC registers bits groups */ #define ADC_CR_BITS_PROPERTY_RS ( ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART \ | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": @@ -558,10 +566,31 @@ extern "C" { */ typedef struct { - uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. - This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE - This feature can be modified afterwards using unitary function - @ref LL_ADC_SetCommonClock(). */ + uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. + This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetCommonClock(). */ + +#if defined(ADC_MULTIMODE_SUPPORT) + uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode + or multimode (for devices with several ADC instances). + This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE + + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetMultimode(). */ + + uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA. + This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER + + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetMultiDMATransfer(). */ + + uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases. + This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY + + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetMultiTwoSamplingDelay(). */ +#endif /* ADC_MULTIMODE_SUPPORT */ } LL_ADC_CommonInitTypeDef; @@ -759,7 +788,6 @@ typedef struct #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */ #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */ #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */ -#define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */ #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */ #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */ #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */ @@ -790,10 +818,6 @@ typedef struct of sequence conversions */ #define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of sequence conversions */ -#define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected - contexts queue overflow */ -#define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected - contexts queue overflow */ #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */ #define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 @@ -826,8 +850,6 @@ typedef struct unitary conversion */ #define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */ -#define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts - queue overflow */ #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */ #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */ #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */ @@ -976,20 +998,20 @@ single-ended and differential modes. */ /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution * @{ */ -#define LL_ADC_RESOLUTION_14B (0x00000000UL) /*!< ADC resolution 14 bits */ +#define LL_ADC_RESOLUTION_14B (0x00000000UL) /*!< ADC resolution 14 bits (ADC1, ADC2 only) */ #define LL_ADC_RESOLUTION_12B ( ADC_CFGR1_RES_0) /*!< ADC resolution 12 bits */ #define LL_ADC_RESOLUTION_10B (ADC_CFGR1_RES_1 ) /*!< ADC resolution 10 bits */ #define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 8 bits */ -#define LL_ADC_RESOLUTION_6B (0x0000FFFFUL) /*!< ADC resolution 6 bits, Internal value - used to differentiate 8B to 6B resolutions - for ADC1 and ADC4 respectively */ - -/* Internal values only, please do not use */ -#define LL_ADC_RESOLUTION_12B_ADC4 (0x00000000UL) /*!< ADC resolution 12 bits */ -#define LL_ADC_RESOLUTION_10B_ADC4 ( ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */ -#define LL_ADC_RESOLUTION_8B_ADC4 (ADC_CFGR1_RES_1 ) /*!< ADC resolution 8 bits */ -#define LL_ADC_RESOLUTION_6B_ADC4 (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 6 bits */ +#define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 \ + << ADC_RESOLUTION_ADC4_PROCESSING) /*!< ADC resolution 6 bits (ADC4 only) + (value shift out of ADC_CFGR1_RES range, + post-processing when applied with ADC4) */ +/* Legacy literals */ +#define LL_ADC_RESOLUTION_12B_ADC4 LL_ADC_RESOLUTION_12B +#define LL_ADC_RESOLUTION_10B_ADC4 LL_ADC_RESOLUTION_10B +#define LL_ADC_RESOLUTION_8B_ADC4 LL_ADC_RESOLUTION_8B +#define LL_ADC_RESOLUTION_6B_ADC4 LL_ADC_RESOLUTION_6B /** * @} */ @@ -1030,7 +1052,7 @@ single-ended and differential modes. */ /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode * @{ */ -#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */ +#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */ #define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */ /** * @} @@ -1039,8 +1061,8 @@ single-ended and differential modes. */ /** @defgroup ADC_LL_EC_AUTOPOWEROFF_MODE ADC instance - Low power mode auto power-off * @{ */ -#define LL_ADC_LP_AUTOPOWEROFF_DISABLE (0x00000000UL) /*!< ADC low power mode auto power-off disabled */ -#define LL_ADC_LP_AUTOPOWEROFF_ENABLE (ADC4_PW_AUTOFF) /*!< ADC low power mode auto power-off enabled: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLPModeAutoPowerOff(). It can be combined with mode low power mode auto wait. */ +#define LL_ADC_LP_AUTOPOWEROFF_DISABLE (0x00000000UL) /*!< ADC low power mode auto power-off disabled */ +#define LL_ADC_LP_AUTOPOWEROFF_ENABLE (ADC4_PWRR_AUTOFF) /*!< ADC low power mode auto power-off enabled: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLPModeAutoPowerOff(). It can be combined with mode low power mode auto wait. */ /** * @} */ @@ -1048,8 +1070,18 @@ single-ended and differential modes. */ /** @defgroup ADC_LL_EC_AUTONOMOUS_DEEP_POWER_DOWN_MODE ADC instance - Autonomous deep power down mode * @{ */ -#define LL_ADC_LP_AUTONOMOUS_DPD_DISABLE (0x00000000UL) /*!< ADC deep power down in autonomous mode disabled */ -#define LL_ADC_LP_AUTONOMOUS_DPD_ENABLE (ADC4_PW_DPD) /*!< ADC deep power down in autonomous mode enabled */ +#define LL_ADC_LP_AUTONOMOUS_DPD_DISABLE (0x00000000UL) /*!< ADC deep power down in autonomous mode disabled */ +#define LL_ADC_LP_AUTONOMOUS_DPD_ENABLE (ADC4_PWRR_DPD) /*!< ADC deep power down in autonomous mode enabled */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_VREF_PROTECTION_MODE ADC instance - VREF protection mode + * @{ + */ +#define LL_ADC_VREF_PROT_DISABLE (0x00000000UL) /*!< ADC Vref+ protection disabled */ +#define LL_ADC_VREF_PROT_FIRST_SAMP_ENABLE (ADC4_PWRR_VREFPROT) /*!< ADC Vref+ protection enabled: In case of simultaneous sampling phase of ADC4 and ADC1/2, ADC4 is put on hold during one ADC4 clock cycle to avoid noise on Vref+. */ +#define LL_ADC_VREF_PROT_SECOND_SAMP_ENABLE (ADC4_PWRR_VREFPROT | ADC4_PWRR_VREFSECSMP) /*!< ADC Vref+ protection enabled: In case of simultaneous sampling phase of ADC4 and ADC1/2, ADC4 is put on hold during two ADC4 clock cycles to avoid noise on Vref+. */ /** * @} */ @@ -1200,13 +1232,13 @@ single-ended and differential modes. */ | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \ | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_EXTI_LINE15 (ADC_CFGR1_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_LPTIM1_CH1 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 CH1 event. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_EXTI_LINE15 (ADC_CFGR1_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 15 event. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_LPTIM1_CH1 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 channel 1 event. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_LPTIM2_CH1 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \ - | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 CH1 event. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_LPTIM3_CH1 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 CH1 event. Trigger edge set to rising edge (default setting). */ + | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 channel 1 event. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_LPTIM3_CH1 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 channel 1 event. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_LPTIM4_OUT (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 \ - | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM4 event OUT. Trigger edge set to rising edge (default setting). */ + | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM4 OUT event. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2_ADC4 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM1_CH4_ADC4 (ADC4_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ @@ -1493,14 +1525,17 @@ single-ended and differential modes. */ /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time * @{ */ -#define LL_ADC_SAMPLINGTIME_5CYCLE (0x00000000UL) /*!< Sampling time 5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_5CYCLES (0x00000000UL) /*!< Sampling time 5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_6CYCLES ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_12CYCLES ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_20CYCLES ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 20 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_36CYCLES (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 36 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_68CYCLES (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 68 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_391CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 391.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_391CYCLES (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 391 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_814CYCLES (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 814 ADC clock cycles */ + +#define LL_ADC_SAMPLINGTIME_5CYCLE LL_ADC_SAMPLINGTIME_5CYCLES /*!< Keep old definition for compatibility */ +#define LL_ADC_SAMPLINGTIME_391CYCLES_5 LL_ADC_SAMPLINGTIME_391CYCLES /*!< Keep old definition for compatibility */ /** * @} */ @@ -1515,7 +1550,9 @@ single-ended and differential modes. */ #define LL_ADC4_SAMPLINGTIME_19CYCLES_5 (ADC4_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */ #define LL_ADC4_SAMPLINGTIME_39CYCLES_5 (ADC4_SMPR_SMP1_2 | ADC4_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */ #define LL_ADC4_SAMPLINGTIME_79CYCLES_5 (ADC4_SMPR_SMP1_2 | ADC4_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */ -#define LL_ADC4_SAMPLINGTIME_160CYCLES_5 (ADC4_SMPR_SMP1_2 | ADC4_SMPR_SMP1_1 | ADC4_SMPR_SMP1_0) /*!< Sampling time 160.5 ADC clock cycles */ +#define LL_ADC4_SAMPLINGTIME_814CYCLES_5 (ADC4_SMPR_SMP1_2 | ADC4_SMPR_SMP1_1 | ADC4_SMPR_SMP1_0) /*!< Sampling time 814.5 ADC clock cycles */ + +#define LL_ADC4_SAMPLINGTIME_160CYCLES_5 LL_ADC4_SAMPLINGTIME_814CYCLES_5 /*!< Keep old definition for compatibility */ /** * @} */ @@ -1740,14 +1777,14 @@ single-ended and differential modes. */ /** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config * @{ */ -#define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt */ -#define LL_ADC_AWD_FILTERING_2SAMPLES ( ADC_HTR_AWDFILT_0) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define LL_ADC_AWD_FILTERING_3SAMPLES ( ADC_HTR_AWDFILT_1 ) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define LL_ADC_AWD_FILTERING_4SAMPLES ( ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define LL_ADC_AWD_FILTERING_5SAMPLES (ADC_HTR_AWDFILT_2 ) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define LL_ADC_AWD_FILTERING_6SAMPLES (ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_0) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define LL_ADC_AWD_FILTERING_7SAMPLES (ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1 ) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */ -#define LL_ADC_AWD_FILTERING_8SAMPLES (ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog watchdog no filtering, one out-of-window sample is needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_2SAMPLES ( ADC_HTR_AWDFILT_0) /*!< ADC analog watchdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_3SAMPLES ( ADC_HTR_AWDFILT_1 ) /*!< ADC analog watchdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_4SAMPLES ( ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0) /*!< ADC analog watchdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_5SAMPLES (ADC_HTR_AWDFILT_2 ) /*!< ADC analog watchdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_6SAMPLES (ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_0) /*!< ADC analog watchdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_7SAMPLES (ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1 ) /*!< ADC analog watchdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_8SAMPLES (ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0) /*!< ADC analog watchdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */ /** * @} */ @@ -1775,14 +1812,14 @@ single-ended and differential modes. */ /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio * @{ */ -#define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_4 ( ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_8 ( ADC4_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_16 ( ADC4_CFGR2_OVSR_1 | ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_32 (ADC4_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_64 (ADC4_CFGR2_OVSR_2 | ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_128 (ADC4_CFGR2_OVSR_2 | ADC4_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_256 (ADC4_CFGR2_OVSR_2 | ADC4_CFGR2_OVSR_1 | ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define LL_ADC_OVS_RATIO_2 (ADC4_OVERSAMPLING_RATIO_PARAMETER | 0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define LL_ADC_OVS_RATIO_4 (ADC4_OVERSAMPLING_RATIO_PARAMETER | ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define LL_ADC_OVS_RATIO_8 (ADC4_OVERSAMPLING_RATIO_PARAMETER | ADC4_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define LL_ADC_OVS_RATIO_16 (ADC4_OVERSAMPLING_RATIO_PARAMETER | ADC4_CFGR2_OVSR_1 | ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define LL_ADC_OVS_RATIO_32 (ADC4_OVERSAMPLING_RATIO_PARAMETER | ADC4_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define LL_ADC_OVS_RATIO_64 (ADC4_OVERSAMPLING_RATIO_PARAMETER | ADC4_CFGR2_OVSR_2 | ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define LL_ADC_OVS_RATIO_128 (ADC4_OVERSAMPLING_RATIO_PARAMETER | ADC4_CFGR2_OVSR_2 | ADC4_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define LL_ADC_OVS_RATIO_256 (ADC4_OVERSAMPLING_RATIO_PARAMETER | ADC4_CFGR2_OVSR_2 | ADC4_CFGR2_OVSR_1 | ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ /** * @} */ @@ -1835,19 +1872,24 @@ single-ended and differential modes. */ /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases * @{ */ -#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5 (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1.5 ADC clock cycle for all resolution */ -#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5 ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2.5 ADC clock cycles for all resolution */ -#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5 ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3.5 ADC clock cycles for all resolution */ -#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 ( ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4.5 ADC clock cycles for 16, 14, 12 or 10 bits resolution */ -#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS ( ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4.5 ADC clock cycles for 8 bits resolution */ -#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 16, 14, 12 bits resolution */ -#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS ( ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 10 bits resolution */ -#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles for 10 or 8 bits resolution */ -#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 ( ADC_CCR_DELAY_2 |ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 16 or 14 bits resolution */ -#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS ( ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 12 bits resolution */ -#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 ( ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 7.5 ADC clock cycles for 16 bits resolution */ -#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles for 12 bits resolution */ -#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles for 16 or 14 bits resolution */ +#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle for all resolution */ +#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles for all resolution */ +#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles for all resolution */ +#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles for all resolution */ +#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles for all resolution */ +#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 |ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles for all resolution */ +#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2|ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles for all resolution */ +#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles for all resolution */ +#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles for all resolution */ +#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 |ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles for all resolution */ +#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 |ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles for all resolution */ +#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 |ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles for all resolution */ +#define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles for all resolution */ +#define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES_8_BITS (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles for 8 bits resolution */ +#define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2 |ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles for all resolution */ +#define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2|ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles for all resolution */ +#define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES_10_BITS (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles for 10 bits resolution */ +#define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles for all resolution */ /** * @} */ @@ -1917,15 +1959,14 @@ single-ended and differential modes. */ /* Unit: ADC clock cycles. */ #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */ -/* Fixed timeout value for ADC linearity word bit set/clear delay. */ -/* Values defined to be higher than worst cases: low clock frequency, */ -/* maximum prescalers. */ -/* Ex of profile low frequency : f_ADC at 4,577 Khz (minimum value */ -/* according to Data sheet), linearity set/clear bit delay MAX = 6 / f_ADC + 3 cycles AHB */ -/* 6 / 4577 = 1,311ms */ -/* At maximum CPU speed (400 MHz), this means */ -/* 3.58 * 400 MHz = 524400 CPU cycles */ -#define ADC_LINEARITY_BIT_TOGGLE_TIMEOUT (524400UL) /*!< ADC linearity set/clear bit delay */ +/* Fixed timeout value for ADC linearity word bit set/clear delay. */ +/* Values defined to be higher than worst cases: maximum ratio between ADC */ +/* and CPU clock frequencies. */ +/* Example of profile low frequency : ADC frequency minimum 140kHz (cf */ +/* datasheet for ADC4), CPU frequency 160MHz. */ +/* Calibration time max = 25502 / fADC (refer to datasheet) */ +/* = 29M CPU cycles */ +#define ADC_LINEARITY_BIT_TOGGLE_TIMEOUT (29000000UL) /*!< ADC linearity calibration set/clear bit delay */ /** * @} @@ -1998,7 +2039,7 @@ single-ended and differential modes. */ * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) @@ -2047,7 +2088,7 @@ single-ended and differential modes. */ * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) @@ -2074,57 +2115,6 @@ single-ended and differential modes. */ (ADC_SMPR2_REGOFFSET)) \ ) -/** - * @brief Helper macro to convert ADC1 resolution to ADC4 resolution bit values. - * @note Example 1: - * __LL_ADC_RESOLUTION_ADC1_TO_ADC4(LL_ADC_RESOLUTION_6B) - * will return a data equivalent to "(ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0)". - * @note Example 2: - * __LL_ADC_RESOLUTION_ADC1_TO_ADC4(LL_ADC_RESOLUTION_10B) - * will return a data equivalent to "(ADC_CFGR1_RES_0)". - * @param __RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval Returned value can be one of the following values: - * @arg 0x00000000UL (value correspodning to ADC4 12 bits) - * @arg ADC_CFGR1_RES_0 = 0x00000004UL (value correspodning to ADC4 10 bits) - * @arg ADC_CFGR1_RES_1 = 0x00000008UL (value corresponding to ADC4 8 bits) - * @arg ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0 = 0x0000000CUL (value corresponding to ADC4 6 bits) - */ - -#define __LL_ADC_RESOLUTION_ADC1_TO_ADC4(__RESOLUTION__) \ - (((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ - ? ((LL_ADC_RESOLUTION_8B)) \ - : ((((__RESOLUTION__)-1UL) & ADC_CFGR1_RES_Msk)) \ - ) - -/** - * @brief Helper macro to convert ADC4 resolution bit values to ADC1 resolution. - * @note Example 1: - * __LL_ADC_RESOLUTION_ADC4_TO_ADC1((ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0)) - * will return a data equivalent to "LL_ADC_RESOLUTION_6B". - * @note Example 2: - * __LL_ADC_RESOLUTION_ADC1_TO_ADC4((ADC_CFGR1_RES_0)) - * will return a data equivalent to "LL_ADC_RESOLUTION_10B". - * @param __RESOLUTION__ This parameter can be one of the following values: - * @arg 0x00000000UL (value correspodning to ADC4 12 bits) - * @arg ADC_CFGR1_RES_0 = 0x00000004UL (value correspodning to ADC4 10 bits) - * @arg ADC_CFGR1_RES_1 = 0x00000008UL (value corresponding to ADC4 8 bits) - * @arg ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0 = 0x0000000CUL (value corresponding to ADC4 6 bits) - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - */ - -#define __LL_ADC_RESOLUTION_ADC4_TO_ADC1(__RESOLUTION__) \ - (((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ - ? ((LL_ADC_RESOLUTION_6B)) \ - : ((((((__RESOLUTION__) >> ADC_CFGR1_RES_Pos) + 1UL) << ADC_CFGR1_RES_Pos) & ADC_CFGR1_RES_Msk)) \ - ) /** * @brief Helper macro to determine whether the selected channel * corresponds to literal definitions of driver. @@ -2163,7 +2153,7 @@ single-ended and differential modes. */ * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) @@ -2217,7 +2207,7 @@ single-ended and differential modes. */ * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) @@ -2270,7 +2260,7 @@ single-ended and differential modes. */ * parameters definitions of driver. * @param __ADC_INSTANCE__ ADC instance * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) @@ -2286,10 +2276,12 @@ single-ended and differential modes. */ */ #if defined(ADC2) #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ - ((((__ADC_INSTANCE__) == ADC4) &&( ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC4) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC4) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC4) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT_ADC4) ) \ + ((((__ADC_INSTANCE__) == ADC4) \ + &&(((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC4) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC4) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC4) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT_ADC4) ) \ ) \ || \ (((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2) \ @@ -2301,7 +2293,8 @@ single-ended and differential modes. */ #else #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ ((((__ADC_INSTANCE__) == ADC4) \ - &&(((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC4) || \ + &&(((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC4) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC4) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC4) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT_ADC4) ) \ @@ -2344,7 +2337,7 @@ single-ended and differential modes. */ * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) @@ -2445,7 +2438,7 @@ single-ended and differential modes. */ * @arg @ref LL_ADC_AWD_CH_VCORE_REG (2) * * (0) On STM32U5, parameter available only on analog watchdog number: AWD1. - * (1) On STM32U5, parameter available only on ADC instance: ADC1/2. + * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2. * (2) On STM32U5, parameter available only on ADC instance: ADC4. */ #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ @@ -2461,7 +2454,7 @@ single-ended and differential modes. */ /** * @brief Helper macro to set the value of ADC analog watchdog threshold high * or low in function of ADC resolution, when ADC resolution is - * different of 14 bits in case of ADC1 and 12 bits in case of ADC4. + * different of 14 bits in case of ADC1 or ADC2, 12 bits in case of ADC4. * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds(). * Example, with a ADC resolution of 8 bits, to set the value of * analog watchdog threshold high (on 8 bits): @@ -2471,31 +2464,31 @@ single-ended and differential modes. */ * ); * @param __ADC_INSTANCE__ ADC instance * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_14B (1) + * @arg @ref LL_ADC_RESOLUTION_14B (1) * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B (2) - * @param __AWD_THRESHOLD__ Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF, In case of ADC1 insatnce - * __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF, In case of ADC4 insatnce - * @retval In case of ADC1 insatnce, Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF - * In case of ADC4 insatnce, Value between Min_Data=0x000 and Max_Data=0xFFF - * - * (1): Only for ADC1 instance - * (2): Only for ADC4 insatnce - */ -#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_INSTANCE__, __ADC_RESOLUTION__, __AWD_THRESHOLD__) \ - (((__ADC_INSTANCE__) == ADC1) \ - ? ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \ - : \ - ((__AWD_THRESHOLD__) << ((__LL_ADC_RESOLUTION_ADC1_TO_ADC4(__ADC_RESOLUTION__)) \ - >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \ + * @arg @ref LL_ADC_RESOLUTION_6B (2) + * (1): Specific to ADC instance: ADC1, ADC2 + * (2): Specific to ADC instance: ADC4 + * @param __AWD_THRESHOLD__ Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF, In case of ADC1 instance + * __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF, In case of ADC4 instance + * @retval In case of ADC1 instance, Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF + * In case of ADC4 instance, Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_INSTANCE__, __ADC_RESOLUTION__, __AWD_THRESHOLD__) \ + (((__ADC_INSTANCE__) == ADC4) \ + ? \ + ((__AWD_THRESHOLD__) << (((((__ADC_RESOLUTION__) - ADC_RESOLUTION_ADC4_PROCESSING) & ADC_CFGR1_RES)) \ + >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \ + : \ + ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \ ) /** * @brief Helper macro to get the value of ADC analog watchdog threshold high * or low in function of ADC resolution, when ADC resolution is - * different of 14 bits in case of ADC1 and 12 bits in case of ADC4. + * different of 14 bits in case of ADC1 or ADC2, 12 bits in case of ADC4. * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). * Example, with a ADC resolution of 8 bits, to get the value of * analog watchdog threshold high (on 8 bits): @@ -2505,25 +2498,25 @@ single-ended and differential modes. */ * ); * @param __ADC_INSTANCE__ ADC instance * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_14B (1) + * @arg @ref LL_ADC_RESOLUTION_14B (1) * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B (2) - * @param __AWD_THRESHOLD__ Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF, In case of ADC1 insatnce - * __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF, In case of ADC4 insatnce - * @retval In case of ADC1 insatnce, Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF - * In case of ADC4 insatnce, Value between Min_Data=0x000 and Max_Data=0xFFF - * - * (1): Only for ADC1 instance - * (2): Only for ADC4 insatnce - */ -#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_INSTANCE__, __ADC_RESOLUTION__, __AWD_THRESHOLD__) \ - (((__ADC_INSTANCE__) == ADC1) \ - ? ((__AWD_THRESHOLD__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \ - : \ - ((__AWD_THRESHOLD__) >> ((__LL_ADC_RESOLUTION_ADC1_TO_ADC4(__ADC_RESOLUTION__)) \ - >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \ + * @arg @ref LL_ADC_RESOLUTION_6B (2) + * (1): Specific to ADC instance: ADC1, ADC2 + * (2): Specific to ADC instance: ADC4 + * @param __AWD_THRESHOLD__ Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF, In case of ADC1 instance + * __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF, In case of ADC4 instance + * @retval In case of ADC1 instance, Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF + * In case of ADC4 instance, Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_INSTANCE__, __ADC_RESOLUTION__, __AWD_THRESHOLD__) \ + (((__ADC_INSTANCE__) == ADC4) \ + ? \ + ((__AWD_THRESHOLD__) >> (((((__ADC_RESOLUTION__) - ADC_RESOLUTION_ADC4_PROCESSING) & ADC_CFGR1_RES)) \ + >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \ + : \ + ((__AWD_THRESHOLD__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \ ) /** @@ -2588,8 +2581,13 @@ single-ended and differential modes. */ * @param __ADCx__ ADC instance * @retval ADC common register instance */ +#if defined(ADC2) +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ + ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) ? (ADC12_COMMON) : (ADC4_COMMON)) +#else #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ (((__ADCx__) == ADC1) ? (ADC12_COMMON) : (ADC4_COMMON)) +#endif /* ADC2 */ /** * @brief Helper macro to check if all ADC instances sharing the same @@ -2631,13 +2629,8 @@ single-ended and differential modes. */ * @arg @ref LL_ADC_RESOLUTION_6B * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data) */ -#define __LL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__) \ - (((__ADC_INSTANCE__) == ADC1) \ - ?((0x3FFFUL) >> (((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) & 0x6UL)) \ - : \ - ((0xFFFUL) >> ((__LL_ADC_RESOLUTION_ADC1_TO_ADC4(__ADC_RESOLUTION__) \ - >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) & 0x6UL)) \ - ) +#define __LL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__) \ + (0x3FFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) /** * @brief Helper macro to convert the ADC conversion data from @@ -2646,31 +2639,26 @@ single-ended and differential modes. */ * @param __DATA__ ADC conversion data to be converted * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted * This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_14B (1) - * @arg @ref LL_ADC_RESOLUTION_12B (2) - * @arg @ref LL_ADC_RESOLUTION_10B (2) - * @arg @ref LL_ADC_RESOLUTION_8B (2) + * @arg @ref LL_ADC_RESOLUTION_14B + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion * This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_14B (1) - * @arg @ref LL_ADC_RESOLUTION_12B (2) - * @arg @ref LL_ADC_RESOLUTION_10B (2) - * @arg @ref LL_ADC_RESOLUTION_8B (2) - * (1): Specific to ADC1 instance - * (2): Common to all instances but different bits positions + * @arg @ref LL_ADC_RESOLUTION_14B + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B * @retval ADC conversion data to the requested resolution */ #define __LL_ADC_CONVERT_DATA_RESOLUTION(__ADC_INSTANCE__, __DATA__,\ __ADC_RESOLUTION_CURRENT__,\ - __ADC_RESOLUTION_TARGET__) \ -(((__ADC_INSTANCE__) == ADC1) \ - ?((__DATA__) \ - << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \ - >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \ - : \ - ((__DATA__) \ - << ((__LL_ADC_RESOLUTION_ADC1_TO_ADC4(__ADC_RESOLUTION_CURRENT__)) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \ - >> ((__LL_ADC_RESOLUTION_ADC1_TO_ADC4(__ADC_RESOLUTION_TARGET__)) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \ + __ADC_RESOLUTION_TARGET__) \ +(((__DATA__) \ + << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \ + >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \ ) /** @@ -2685,13 +2673,12 @@ single-ended and differential modes. */ * @param __ADC_INSTANCE__ ADC instance * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_14B (1) - * @arg @ref LL_ADC_RESOLUTION_12B (3) - * @arg @ref LL_ADC_RESOLUTION_10B (3) - * @arg @ref LL_ADC_RESOLUTION_8B (3) + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B (2) - * (1): Specific to ADC1 instance - * (2): Specific to ADC4 instance - * (3): Common to all instances but different bits positions + * (1): Specific to ADC instance: ADC1, ADC2 + * (2): Specific to ADC instance: ADC4 * @retval ADC conversion data equivalent voltage value (unit: mVolt) */ #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__ADC_INSTANCE__, __VREFANALOG_VOLTAGE__,\ @@ -2722,27 +2709,21 @@ single-ended and differential modes. */ * of internal voltage reference VrefInt (unit: digital value). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_14B (1) - * @arg @ref LL_ADC_RESOLUTION_12B (3) - * @arg @ref LL_ADC_RESOLUTION_10B (3) - * @arg @ref LL_ADC_RESOLUTION_8B (3) + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B (2) - * (1): Specific to ADC1 instance - * (2): Specific to ADC4 instance - * (3): Common to all instances but different bits positions + * (1): Specific to ADC instance: ADC1, ADC2 + * (2): Specific to ADC instance: ADC4 * @retval Analog reference voltage (unit: mV) */ #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__ADC_INSTANCE__, __VREFINT_ADC_DATA__, \ __ADC_RESOLUTION__) \ -(((__ADC_INSTANCE__) == ADC1) \ - ?((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ - / __LL_ADC_CONVERT_DATA_RESOLUTION((__ADC_INSTANCE__), (__VREFINT_ADC_DATA__),\ - (__ADC_RESOLUTION__), \ - LL_ADC_RESOLUTION_14B) \ - : \ - ((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ - / __LL_ADC_CONVERT_DATA_RESOLUTION((__ADC_INSTANCE__), (__VREFINT_ADC_DATA__),\ - (__ADC_RESOLUTION__), \ - LL_ADC_RESOLUTION_12B) \ +(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ + / __LL_ADC_CONVERT_DATA_RESOLUTION((__ADC_INSTANCE__), \ + (__VREFINT_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_14B) \ ) /** @@ -2786,40 +2767,27 @@ single-ended and differential modes. */ * sensor voltage has been measured. * This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_14B (1) - * @arg @ref LL_ADC_RESOLUTION_12B (3) - * @arg @ref LL_ADC_RESOLUTION_10B (3) - * @arg @ref LL_ADC_RESOLUTION_8B (3) + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B (2) - * (1): Specific to ADC1 instance - * (2): Specific to ADC4 instance - * (3): Common to all instances but different bits positions + * (1): Specific to ADC instance: ADC1, ADC2 + * (2): Specific to ADC instance: ADC4 * @retval Temperature (unit: degree Celsius) */ -#define __LL_ADC_CALC_TEMPERATURE(__ADC_INSTANCE__, __VREFANALOG_VOLTAGE__, \ - __TEMPSENSOR_ADC_DATA__, \ - __ADC_RESOLUTION__) \ -(((__ADC_INSTANCE__) == ADC1) \ - ?(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__ADC_INSTANCE__), (__TEMPSENSOR_ADC_DATA__), \ - (__ADC_RESOLUTION__), \ - LL_ADC_RESOLUTION_14B) \ - * (__VREFANALOG_VOLTAGE__)) \ - / TEMPSENSOR_CAL_VREFANALOG) \ - - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ - ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ - ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ - ) + TEMPSENSOR_CAL1_TEMP \ - ) \ - : \ - (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__ADC_INSTANCE__), (__TEMPSENSOR_ADC_DATA__), \ - (__ADC_RESOLUTION__), \ - LL_ADC_RESOLUTION_12B) \ - * (__VREFANALOG_VOLTAGE__)) \ - / TEMPSENSOR_CAL_VREFANALOG) \ - - (int32_t) (*TEMPSENSOR_CAL1_ADDR >> 2 )) \ - ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ - ) / (int32_t)((int32_t)(*TEMPSENSOR_CAL2_ADDR >> 2 ) - (int32_t)(*TEMPSENSOR_CAL1_ADDR >> 2) ) \ - ) + TEMPSENSOR_CAL1_TEMP \ - ) \ +#define __LL_ADC_CALC_TEMPERATURE(__ADC_INSTANCE__, __VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ +(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__ADC_INSTANCE__), \ + (__TEMPSENSOR_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_14B) \ + * (__VREFANALOG_VOLTAGE__)) \ + / TEMPSENSOR_CAL_VREFANALOG) \ + - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ + ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ + ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ + ) + TEMPSENSOR_CAL1_TEMP \ ) /** @@ -2866,13 +2834,12 @@ single-ended and differential modes. */ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. * This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_14B (1) - * @arg @ref LL_ADC_RESOLUTION_12B (3) - * @arg @ref LL_ADC_RESOLUTION_10B (3) - * @arg @ref LL_ADC_RESOLUTION_8B (3) + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B (2) - * (1): Specific to ADC1 instance - * (2): Specific to ADC4 instance - * (3): Common to all instances but different bits positions + * (1): Specific to ADC instance: ADC1, ADC2 + * (2): Specific to ADC instance: ADC4 * @retval Temperature (unit: degree Celsius) */ #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__ADC_INSTANCE__, __TEMPSENSOR_TYP_AVGSLOPE__, \ @@ -2884,7 +2851,7 @@ single-ended and differential modes. */ ((( ((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ / __LL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__)) \ * 1000UL) \ - - \ + - \ (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ * 1000UL) \ ) \ @@ -2939,7 +2906,7 @@ single-ended and differential modes. */ * (1) Available on devices with several ADC instances. * @retval ADC register address */ -__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t RegisterValue) +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t RegisterValue) { uint32_t data_reg_addr; @@ -2982,7 +2949,7 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Regis * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA * @retval ADC register address */ -__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t RegisterValue) +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t RegisterValue) { /* Prevent unused argument(s) compilation warning */ (void)(RegisterValue); @@ -3057,7 +3024,7 @@ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uin * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC)); } @@ -3190,7 +3157,7 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_CO * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN)); } @@ -3227,30 +3194,28 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCx * ADC state: * ADC must be enabled, without calibration on going, without conversion * on going on group regular. - * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationOffsetFactor - * CALFACT CALFACT_D LL_ADC_SetCalibrationOffsetFactor * @param ADCx ADC instance * @param SingleDiff This parameter can be one of the following values: * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED - * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F + * @param CalibrationFactor Value between Min_Data=0x0000 and Max_Data=0xFFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor) { - if (ADCx == ADC1) + if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */ { - CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF | ADC_CALFACT_CAPTURE_COEF); - MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, 0UL); /* CalibIndex == 0*/ + /* Note: Bitfields ADC_CALFACT_LATCH_COEF and ADC_CALFACT_CAPTURE_COEF have property "wr1", + therefore they are not cleared in this function. */ + MODIFY_REG(ADCx->CR, ADC_CR_CALINDEX, (0UL << ADC_CR_CALINDEX_Pos)); /* CalibIndex == 0 */ MODIFY_REG(ADCx->CALFACT2, SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK, CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) \ >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) \ & ~(SingleDiff & ADC_CALFACT2_CALFACT_S))); SET_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF); - CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF); } else { @@ -3268,13 +3233,11 @@ __STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32 * single-ended and differential modes * Calibration of linearity is common to both * single-ended and differential modes - * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationOffsetFactor - * CALFACT CALFACT_D LL_ADC_GetCalibrationOffsetFactor * @param ADCx ADC instance * @param SingleDiff This parameter can be one of the following values: * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED - * @retval Value between Min_Data=0x00 and Max_Data=0x7F + * @retval Value between Min_Data=0x0000 and Max_Data=0xFFFF */ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff) { @@ -3282,15 +3245,15 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, ui /* "SingleDiff". */ /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */ /* containing other bits reserved for other purpose. */ - if (ADCx == ADC1) + if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */ { + /* Note: Bitfields ADC_CALFACT_LATCH_COEF and ADC_CALFACT_CAPTURE_COEF have property "wr1", + therefore they are not cleared in this function. */ uint32_t temp_CalibOffset; SET_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF); - CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF); - MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, 0UL); /* CalibIndex == 0*/ + MODIFY_REG(ADCx->CR, ADC_CR_CALINDEX, (0UL << ADC_CR_CALINDEX_Pos)); /* CalibIndex == 0 */ temp_CalibOffset = (READ_BIT(ADCx->CALFACT2, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) \ >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)); - CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF); return temp_CalibOffset; } else @@ -3304,13 +3267,14 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, ui * @note This function is intended to set linear calibration parameters * without having to perform a new calibration using * @ref LL_ADC_StartCalibration(). + * @note On STM32U5, this feature is available on ADC instances: ADC1, ADC2. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled, without calibration on going, without conversion * on going on group regular. * @rmtoll CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor * CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor - * @param ADCx ADC instance + * @param ADCx ADC instance (on STM32U5, feature available on ADC instances: ADC1, ADC2) * @param LinearityWord This parameter can be one of the following values: * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX1 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX2 @@ -3325,25 +3289,22 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, ui __STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord, uint32_t CalibrationFactor) { - /* Before using this! - Make sure ADEN = 1, ADSTART = 0 and JADSTART = 0 (ADC enabled and no conversion is ongoing). - --> This should be checked by application. - */ - CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF | ADC_CALFACT_CAPTURE_COEF); - MODIFY_REG(ADCx->CR, (ADC_CR_CALINDEX3 | ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1 | ADC_CR_CALINDEX0), - LinearityWord); /* LinearityWord == CalibIndex (1 to 8 for linearity reading)*/ + /* Note: Bitfields ADC_CALFACT_LATCH_COEF and ADC_CALFACT_CAPTURE_COEF have property "wr1", + therefore they are not cleared in this function. */ + MODIFY_REG(ADCx->CR, (ADC_CR_CALINDEX), + LinearityWord); /* LinearityWord == CalibIndex (1 to 7 for linearity reading) */ MODIFY_REG(ADCx->CALFACT2, ADC_CALFACT2_CALFACT, CalibrationFactor); SET_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF); - CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF); } /** * @brief Get ADC Linear calibration factor in the mode single-ended. * @note Calibration factors are set by hardware after performing * a calibration run using function @ref LL_ADC_StartCalibration(). + * @note On STM32U5, this feature is available on ADC instances: ADC1, ADC2. * @rmtoll CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor * CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor - * @param ADCx ADC instance + * @param ADCx ADC instance (on STM32U5, feature available on ADC instances: ADC1, ADC2) * @param LinearityWord This parameter can be one of the following values: * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX1 * @arg @ref LL_ADC_CALIB_LINEARITY_INDEX2 @@ -3357,12 +3318,13 @@ __STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord) { uint32_t temp_calib_linearity; + + /* Note: Bitfields ADC_CALFACT_LATCH_COEF and ADC_CALFACT_CAPTURE_COEF have property "wr1", + therefore they are not cleared in this function. */ SET_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF); - CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF); - MODIFY_REG(ADCx->CR, (ADC_CR_CALINDEX3 | ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1 | ADC_CR_CALINDEX0), - LinearityWord); /* LinearityWord == CalibIndex (1 to 8 for linearity reading)*/ + MODIFY_REG(ADCx->CR, (ADC_CR_CALINDEX), + LinearityWord); /* LinearityWord == CalibIndex (1 to 7 for linearity reading) */ temp_calib_linearity = (uint32_t)(READ_BIT(ADCx->CALFACT2, ADC_CALFACT2_CALFACT_Msk)); - CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF); return temp_calib_linearity; } /** @@ -3373,31 +3335,27 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, ui * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. - * @note if ADC4 instance __LL_ADC_RESOLUTION_ADC1_TO_ADC4() is used to - * convert ADC1 to ADC4 resolution * @rmtoll CFGR RES LL_ADC_SetResolution * @param ADCx ADC instance * @param Resolution This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_14B (1) - * @arg @ref LL_ADC_RESOLUTION_12B (3) - * @arg @ref LL_ADC_RESOLUTION_10B (3) - * @arg @ref LL_ADC_RESOLUTION_8B (3) + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B (2) - * (1): Specific to ADC1 instance - * (2): Specific to ADC4 instance - * (3): Common to all instances but different bits positions + * (1): Specific to ADC instance: ADC1, ADC2 + * (2): Specific to ADC instance: ADC4 * @retval None */ __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution) { - if (ADCx == ADC1) + uint32_t tmp_resolution = Resolution; + if (ADCx == ADC4) { - MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution); - } - else /* ADCx == ADC4 */ - { - MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, __LL_ADC_RESOLUTION_ADC1_TO_ADC4(Resolution)); + tmp_resolution = ((tmp_resolution - ADC_RESOLUTION_ADC4_PROCESSING) & ADC_CFGR1_RES); } + + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, tmp_resolution); } /** @@ -3408,33 +3366,23 @@ __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_14B (1) - * @arg @ref LL_ADC_RESOLUTION_12B (3) - * @arg @ref LL_ADC_RESOLUTION_10B (3) - * @arg @ref LL_ADC_RESOLUTION_8B (3) + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B (2) - * (1): Specific to ADC1 instance - * (2): Specific to ADC4 instance - * (3): Common to all instances but different bits positions + * (1): Specific to ADC instance: ADC1, ADC2 + * (2): Specific to ADC instance: ADC4 */ -__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx) { - if (ADCx == ADC1) - { - return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES)); - } - else /* ADCx == ADC4 */ + uint32_t tmp_resolution = (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES)); + + if (ADCx == ADC4) { - uint32_t temp_Resolution; - temp_Resolution = (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES)); - if (temp_Resolution == (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0)) - { - return LL_ADC_RESOLUTION_6B; - } - else - { - return __LL_ADC_RESOLUTION_ADC4_TO_ADC1(temp_Resolution); - } + tmp_resolution = (tmp_resolution + (ADC_RESOLUTION_ADC4_PROCESSING << ADC_CFGR1_RES_Pos)); } + + return tmp_resolution; } /** @@ -3467,7 +3415,7 @@ __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAli * @arg @ref LL_ADC_DATA_ALIGN_RIGHT * @arg @ref LL_ADC_DATA_ALIGN_LEFT */ -__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_ALIGN)); } @@ -3532,7 +3480,7 @@ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPower else { MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_WAIT, LowPowerMode); - MODIFY_REG(ADCx->PW, ADC4_PW_AUTOFF, LowPowerMode); + MODIFY_REG(ADCx->PWRR, ADC4_PWRR_AUTOFF, LowPowerMode); } } @@ -3582,7 +3530,7 @@ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPower * @arg @ref LL_ADC_LP_MODE_NONE * @arg @ref LL_ADC_LP_AUTOWAIT */ -__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx) { if (ADCx != ADC4) /* ADC1 or ADC2 */ { @@ -3655,7 +3603,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) @@ -3663,7 +3611,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2) * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2) * - * (1) On STM32U5, parameter available only on ADC instance: ADC1/2. + * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2. * (2) On STM32U5, parameter available only on ADC instance: ADC4. * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). @@ -3728,7 +3676,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) @@ -3736,7 +3684,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2) * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2) * - * (1) On STM32U5, parameter available only on ADC instance: ADC1/2. + * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2. * (2) On STM32U5, parameter available only on ADC instance: ADC4. * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). @@ -3744,7 +3692,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); @@ -3770,7 +3718,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Off * @arg @ref LL_ADC_OFFSET_4 * @retval Value between Min_Data=0x000 and Max_Data=0x1FFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); @@ -3823,7 +3771,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, u * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); @@ -3872,7 +3820,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_ * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSAT); @@ -3920,7 +3868,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetUnsignedSaturation(ADC_TypeDef *ADCx, uint3 * @arg @ref LL_ADC_OFFSET_UNSIGNED_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetUnsignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetUnsignedSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_USAT); @@ -3961,7 +3909,7 @@ __STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx, uint32_t Gain * 0 Gain compensation is disabled * 1 -> 16393 Gain compensation is enabled with returned value */ -__STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMP) == ADC_GCOMP_GCOMP) \ ? READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF) : 0UL); @@ -4013,7 +3961,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(ADC_TypeDef *ADCx) * @arg @ref LL_ADC4_SAMPLINGTIME_19CYCLES_5 * @arg @ref LL_ADC4_SAMPLINGTIME_39CYCLES_5 * @arg @ref LL_ADC4_SAMPLINGTIME_79CYCLES_5 - * @arg @ref LL_ADC4_SAMPLINGTIME_160CYCLES_5 + * @arg @ref LL_ADC4_SAMPLINGTIME_814CYCLES_5 * @retval None */ __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY, @@ -4047,9 +3995,9 @@ __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uin * @arg @ref LL_ADC4_SAMPLINGTIME_19CYCLES_5 * @arg @ref LL_ADC4_SAMPLINGTIME_39CYCLES_5 * @arg @ref LL_ADC4_SAMPLINGTIME_79CYCLES_5 - * @arg @ref LL_ADC4_SAMPLINGTIME_160CYCLES_5 + * @arg @ref LL_ADC4_SAMPLINGTIME_814CYCLES_5 */ -__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY) +__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef *ADCx, uint32_t SamplingTimeY) { return (uint32_t)((READ_BIT(ADCx->SMPR1, ADC4_SMPR_SMP1 << (SamplingTimeY & ADC4_SAMPLING_TIME_SMP_SHIFT_MASK))) >> (SamplingTimeY & ADC4_SAMPLING_TIME_SMP_SHIFT_MASK)); @@ -4103,7 +4051,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, */ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) { - if (ADCx == ADC1) + if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */ { MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource); } @@ -4150,9 +4098,9 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_CH1 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_CH1 */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx) { - if (ADCx == ADC1) + if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */ { __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN); @@ -4195,7 +4143,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL); } @@ -4230,7 +4178,7 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t Exter * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN)); } @@ -4263,7 +4211,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode) { - if (ADCx == ADC1) + if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */ { MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, (TriggerFrequencyMode >> 2U)); } @@ -4281,9 +4229,9 @@ __STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH * @arg @ref LL_ADC_TRIGGER_FREQ_LOW */ -__STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(const ADC_TypeDef *ADCx) { - if (ADCx == ADC1) + if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */ { return (uint32_t)((READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG)) << 2U); } @@ -4326,7 +4274,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t Samp * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG)); } @@ -4427,7 +4375,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE * @note On this STM32U5 series, this is applicable on ADC4 only. */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_CHSELRMOD)); } @@ -4484,6 +4432,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS + * Note: Specific case for ADC4, use literals LL_ADC4_REG_SEQ_SCAN_x * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) @@ -4546,8 +4495,9 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS + * Note: Specific case for ADC4, use literals LL_ADC4_REG_SEQ_SCAN_x */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx) { if (ADCx != ADC4) /* ADC1 or ADC2 */ { @@ -4563,7 +4513,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) /* Parse register for end of sequence identifier */ /* Note: Value "0xF0UL" corresponds to bitfield of sequencer 2nd rank (ADC_CHSELR_SQ2), value "4" to length of end of sequence - indentifier (0xF)*/ + identifier (0xF)*/ for (rank_index = 0UL; rank_index <= (28U - 4U); rank_index += 4U) { rank_shifted = (uint32_t)(0xF0UL << rank_index); @@ -4628,7 +4578,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN | ADC_CFGR1_DISCNUM)); } @@ -4687,6 +4637,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_REG_RANK_14 * @arg @ref LL_ADC_REG_RANK_15 * @arg @ref LL_ADC_REG_RANK_16 + * Note: Specific case for ADC4, use literals LL_ADC_REG_RANK_x_ADC4 * @param Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 (3) * @arg @ref LL_ADC_CHANNEL_1 (3) @@ -4708,7 +4659,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) @@ -4716,7 +4667,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2) * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2) * - * (1) On STM32U5, parameter available only on ADC instance: ADC1/2. + * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2. * (2) On STM32U5, parameter available only on ADC instance: ADC4. * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). @@ -4800,6 +4751,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_REG_RANK_14 * @arg @ref LL_ADC_REG_RANK_15 * @arg @ref LL_ADC_REG_RANK_16 + * Note: Specific case for ADC4, use literals LL_ADC_REG_RANK_x_ADC4 * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 (3) * @arg @ref LL_ADC_CHANNEL_1 (3) @@ -4821,7 +4773,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) @@ -4829,7 +4781,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2) * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2) * - * (1) On STM32U5, parameter available only on ADC instance: ADC1/2. + * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2. * (2) On STM32U5, parameter available only on ADC instance: ADC4. * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). @@ -4837,7 +4789,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { if (ADCx != ADC4) /* ADC1 or ADC2 */ { @@ -4895,7 +4847,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uin * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_SCANDIR)); } @@ -5226,7 +5178,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Ch * only if sequencer is set in mode "not fully configurable", * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(const ADC_TypeDef *ADCx) { uint32_t channels_bitfield = READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL); @@ -5329,7 +5281,7 @@ __STATIC_INLINE void LL_ADC_SetChannelPreselection(ADC_TypeDef *ADCx, uint32_t C * * @note User helper macro @ref __LL_ADC_DECIMAL_NB_TO_CHANNEL(). */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelPreselection(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetChannelPreselection(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->PCSEL, ADC_PCSEL_PCSEL)); } @@ -5354,7 +5306,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelPreselection(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_SetLPModeAutoPowerOff(ADC_TypeDef *ADCx, uint32_t LowPowerMode) { - MODIFY_REG(ADCx->PW, ADC4_PW_AUTOFF, LowPowerMode); + MODIFY_REG(ADCx->PWRR, ADC4_PWRR_AUTOFF, LowPowerMode); } /** @@ -5371,9 +5323,9 @@ __STATIC_INLINE void LL_ADC_SetLPModeAutoPowerOff(ADC_TypeDef *ADCx, uint32_t Lo * @arg @ref LL_ADC_LP_AUTOPOWEROFF_DISABLE * @arg @ref LL_ADC_LP_AUTOPOWEROFF_ENABLE */ -__STATIC_INLINE uint32_t LL_ADC_GetLPModeAutoPowerOff(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetLPModeAutoPowerOff(const ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->PW, ADC4_PW_AUTOFF)); + return (uint32_t)(READ_BIT(ADCx->PWRR, ADC4_PWRR_AUTOFF)); } /** @@ -5390,7 +5342,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetLPModeAutoPowerOff(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_SetLPModeAutonomousDPD(ADC_TypeDef *ADCx, uint32_t LowPowerMode) { - MODIFY_REG(ADCx->PW, ADC4_PW_DPD, LowPowerMode); + MODIFY_REG(ADCx->PWRR, ADC4_PWRR_DPD, LowPowerMode); } /** @@ -5401,9 +5353,44 @@ __STATIC_INLINE void LL_ADC_SetLPModeAutonomousDPD(ADC_TypeDef *ADCx, uint32_t L * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_DISABLE * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_ENABLE */ -__STATIC_INLINE uint32_t LL_ADC_GetLPModeAutonomousDPD(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetLPModeAutonomousDPD(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->PWRR, ADC4_PWRR_DPD)); +} + +/** + * @brief Set ADC VREF protection when multiple ADCs are working simultaneously + * @note In case of simultaneous sampling phase of ADC4 and ADC1/2, + * ADC4 is put on hold during one or two ADC4 clock cycles to avoid noise on Vref+. + * ADC state: + * ADC must be disabled. + * @rmtoll PWRR VREFPROT LL_ADC_SetVrefProtection + * PWRR VREFSECSMP LL_ADC_SetVrefProtection + * @param ADCx ADC instance + * @param VrefProtection This parameter can be one of the following values: + * @arg @ref LL_ADC_VREF_PROT_DISABLE + * @arg @ref LL_ADC_VREF_PROT_FIRST_SAMP_ENABLE + * @arg @ref LL_ADC_VREF_PROT_SECOND_SAMP_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetVrefProtection(ADC_TypeDef *ADCx, uint32_t VrefProtection) +{ + MODIFY_REG(ADCx->PWRR, ADC4_PWRR_VREFPROT | ADC4_PWRR_VREFSECSMP, VrefProtection); +} + +/** + * @brief ADC VREF protection when multiple ADCs are working simultaneously + * @rmtoll PWRR VREFPROT LL_ADC_GetVrefProtection + * PWRR VREFSECSMP LL_ADC_GetVrefProtection + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_VREF_PROT_DISABLE + * @arg @ref LL_ADC_VREF_PROT_FIRST_SAMP_ENABLE + * @arg @ref LL_ADC_VREF_PROT_SECOND_SAMP_ENABLE + */ +__STATIC_INLINE uint32_t LL_ADC_GetVrefProtection(const ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->PW, ADC4_PW_DPD)); + return (uint32_t)(READ_BIT(ADCx->PWRR, ADC4_PWRR_VREFPROT | ADC4_PWRR_VREFSECSMP)); } /** @@ -5442,10 +5429,11 @@ __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Co * @arg @ref LL_ADC_REG_CONV_SINGLE * @arg @ref LL_ADC_REG_CONV_CONTINUOUS */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT)); } + /** * @brief Set ADC data transfer mode * @note Conversion data can be either: @@ -5455,7 +5443,11 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) * - Transferred to MDF data register * @rmtoll CFGR DMNGT LL_ADC_REG_SetDataTransferMode * @param ADCx ADC instance - * @param DataTransferMode Select Data Management configuration + * @param DataTransferMode This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_DR_TRANSFER + * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + * @arg @ref LL_ADC_REG_MDF_TRANSFER * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode) @@ -5478,7 +5470,7 @@ __STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED * @arg @ref LL_ADC_REG_MDF_TRANSFER */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMNGT)); } @@ -5549,7 +5541,7 @@ __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATr * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_DMAEN | ADC4_CFGR1_DMACFG)); } @@ -5588,7 +5580,7 @@ __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD)); } @@ -5685,7 +5677,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1 */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx) { __IO uint32_t trigger_source = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); @@ -5712,7 +5704,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ -__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL); } @@ -5747,7 +5739,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t Exter * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN)); } @@ -5794,7 +5786,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); } @@ -5827,7 +5819,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_JDISCEN)); } @@ -5878,7 +5870,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) @@ -5886,7 +5878,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2) * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2) * - * (1) On STM32U5, parameter available only on ADC instance: ADC1/2. + * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2. * (2) On STM32U5, parameter available only on ADC instance: ADC4. * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). @@ -5951,7 +5943,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) @@ -5959,7 +5951,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2) * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2) * - * (1) On STM32U5, parameter available only on ADC instance: ADC1/2. + * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2. * (2) On STM32U5, parameter available only on ADC instance: ADC4. * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). @@ -5967,7 +5959,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { return (uint32_t)((READ_BIT(ADCx->JSQR, (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \ @@ -6020,7 +6012,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_JAUTO)); } @@ -6113,13 +6105,13 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2) * - * (1) On STM32U5, parameter available only on ADC instance: ADC1/2. + * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2. * (2) On STM32U5, parameter available only on ADC instance: ADC4. * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). @@ -6144,7 +6136,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) @@ -6152,7 +6144,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2) * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2) * - * (1) On STM32U5, parameter available only on ADC instance: ADC1/2. + * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2. * (2) On STM32U5, parameter available only on ADC instance: ADC4. * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). @@ -6177,7 +6169,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) @@ -6185,7 +6177,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2) * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2) * - * (1) On STM32U5, parameter available only on ADC instance: ADC1/2. + * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2. * (2) On STM32U5, parameter available only on ADC instance: ADC4. * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). @@ -6210,7 +6202,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) @@ -6218,7 +6210,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2) * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2) * - * (1) On STM32U5, parameter available only on ADC instance: ADC1/2. + * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2. * (2) On STM32U5, parameter available only on ADC instance: ADC4. * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). @@ -6339,7 +6331,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) @@ -6347,22 +6339,24 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2) * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2) * - * (1) On STM32U5, parameter available only on ADC instance: ADC1/2. + * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2. * (2) On STM32U5, parameter available only on ADC instance: ADC4. * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). * @param SamplingTime This parameter can be one of the following values, In case of ADC1 instance: - * @arg @ref LL_ADC_SAMPLINGTIME_5CYCLE - * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_20CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_36CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_68CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_391CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_814CYCLES - * @param SamplingTime This parameter can be one of the following values, In case of ADC4 instance: - * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 - * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 + * @arg @ref LL_ADC_SAMPLINGTIME_5CYCLES (1) + * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES (1) + * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES (1) + * @arg @ref LL_ADC_SAMPLINGTIME_20CYCLES (1) + * @arg @ref LL_ADC_SAMPLINGTIME_36CYCLES (1) + * @arg @ref LL_ADC_SAMPLINGTIME_68CYCLES (1) + * @arg @ref LL_ADC_SAMPLINGTIME_391CYCLES (1) + * @arg @ref LL_ADC_SAMPLINGTIME_814CYCLES (1) + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 (2) + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 (2) + * + * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2. + * (2) On STM32U5, parameter available only on ADC instance: ADC4. * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) @@ -6388,8 +6382,8 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C /* other bits reserved for other purpose. It needs to be converted to decimal */ /* to select the bit position */ MODIFY_REG(ADCx->SMPR1, - ADC4_SAMPLING_TIME_CH_MASK, - ((1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel)) << ADC4_SMPR_SMPSEL0_BITOFFSET_POS) \ + ((Channel & ADC_CHANNEL_ID_BITFIELD_MASK) << ADC4_SMPR_SMPSEL0_BITOFFSET_POS), + ((Channel & ADC_CHANNEL_ID_BITFIELD_MASK) << ADC4_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTime & ADC4_SAMPLING_TIME_CH_MASK) ); } @@ -6447,7 +6441,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_VREFINT * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) @@ -6455,24 +6449,26 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2) * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2) * - * (1) On STM32U5, parameter available only on ADC instance: ADC1/2. + * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2. * (2) On STM32U5, parameter available only on ADC instance: ADC4. * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). * @retval In case of ADC1 insatnace, Returned value can be one of the following values: - * @arg @ref LL_ADC_SAMPLINGTIME_5CYCLE - * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_20CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_36CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_68CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_391CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_814CYCLES - * @retval In case of ADC4 insatnce, Returned value can be one of the following values: - * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 - * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 + * @arg @ref LL_ADC_SAMPLINGTIME_5CYCLES (1) + * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES (1) + * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES (1) + * @arg @ref LL_ADC_SAMPLINGTIME_20CYCLES (1) + * @arg @ref LL_ADC_SAMPLINGTIME_36CYCLES (1) + * @arg @ref LL_ADC_SAMPLINGTIME_68CYCLES (1) + * @arg @ref LL_ADC_SAMPLINGTIME_391CYCLES (1) + * @arg @ref LL_ADC_SAMPLINGTIME_814CYCLES (1) + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 (2) + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 (2) + * + * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2. + * (2) On STM32U5, parameter available only on ADC instance: ADC4. */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel) { if (ADCx != ADC4) /* (ADCx == ADC1) || (ADCx == ADC2) */ { @@ -6607,7 +6603,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Cha * @arg @ref LL_ADC_CHANNEL_19 * @retval 0: channel in single-ended mode, else: channel in differential mode */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, uint32_t Channel) { return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK))); } @@ -6743,7 +6739,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC4_REG (0)(2) * * (0) On STM32U5, parameter available only on analog watchdog number: AWD1. - * (1) On STM32U5, parameter available only on ADC instance: ADC1/2. + * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2. * (2) On STM32U5, parameter available only on ADC instance: ADC4. * @retval None */ @@ -6907,7 +6903,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * * (0) On STM32U5, parameter available only on analog watchdog number: AWD1. */ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy) { const __IO uint32_t *preg; @@ -6946,7 +6942,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint } else { - if (ADCx == ADC1) + if (ADCx != ADC4) { if ((analog_wd_monit_channels & 0x000FFFFFUL) == 0x000FFFFFUL) { @@ -7046,7 +7042,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW /* "AWDThresholdsHighLow" and "AWDy". */ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ /* containing other bits reserved for other purpose. */ - if (ADCx == ADC1) + if (ADCx != ADC4) /* ADCx == ADC1 or ADCx == ADC2 */ { if (AWDy == LL_ADC_AWD1) { @@ -7061,7 +7057,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdValue); } - else /* ADCx == ADC4 */ + else /* ADCx == ADC4 */ { if (AWDy == LL_ADC_AWD1) { @@ -7105,10 +7101,11 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW * @retval In case of ADC1 instance, Value between Min_Data=0x000 and Max_Data=0x1FFFFFF * @retval In case of ADC1 instance, Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, uint32_t AWDy, + uint32_t AWDThresholdsHighLow) { const __IO uint32_t *preg; - if (ADCx == ADC1) + if (ADCx != ADC4) /* ADCx == ADC1 or ADCx == ADC2 */ { if (AWDy == LL_ADC_AWD1) { @@ -7122,7 +7119,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_ return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT)); } - else + else /* ADCx == ADC4 */ { if (AWDy == LL_ADC_AWD1) { @@ -7300,7 +7297,7 @@ __STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES */ -__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy) +__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef *ADCx, uint32_t AWDy) { /* Prevent unused argument(s) compilation warning */ (void)(AWDy); @@ -7342,7 +7339,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, */ __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope) { - if (ADCx == ADC1) + if (ADCx != ADC4) { MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope); } @@ -7372,9 +7369,9 @@ __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t Ovs * @arg @ref LL_ADC_OVS_GRP_INJECTED * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx) { - if (ADCx == ADC1) + if (ADCx != ADC4) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM)); } @@ -7425,7 +7422,7 @@ __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t O * @arg @ref LL_ADC_OVS_REG_CONT * @arg @ref LL_ADC_OVS_REG_DISCONT */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS)); } @@ -7443,8 +7440,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift * @param ADCx ADC instance - * @param Ratio This parameter can be in the range from 1 to 1024 in case of ADC1 instance. - * @param Ratio This parameter can be one of the following values, in case of ADC4 : + * @param Ratio For ADC instance ADC1, ADC2: This parameter can be in the range from 1 to 1024. + * For ADC instance ADC4: This parameter can be one of the following values: * @arg @ref LL_ADC_OVS_RATIO_2 * @arg @ref LL_ADC_OVS_RATIO_4 * @arg @ref LL_ADC_OVS_RATIO_8 @@ -7472,32 +7469,42 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift) { - if (ADCx == ADC1) + if (ADCx != ADC4) { MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos)))); } else /* ADCx == ADC4 */ { - MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC4_CFGR2_OVSR), (Shift | Ratio)); + MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC4_CFGR2_OVSR), + (Shift | (Ratio & ~ADC4_OVERSAMPLING_RATIO_PARAMETER_MASK))); } } /** - * @brief Get ADC oversampling ratio - * (impacting both ADC groups regular and injected) - * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio - * @param ADCx ADC instance - * @retval Ratio This parameter can be in the from 1 to 1024. + * @brief Get ADC oversampling ratio + * (impacting both ADC groups regular and injected) + * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio + * @param ADCx ADC instance + * @retval Ratio This parameter can be a value from 1 to 1024 in the case of ADC1/2, + * In the case of ADC4 can be one of the following values: + * @arg @ref LL_ADC_OVS_RATIO_2 + * @arg @ref LL_ADC_OVS_RATIO_4 + * @arg @ref LL_ADC_OVS_RATIO_8 + * @arg @ref LL_ADC_OVS_RATIO_16 + * @arg @ref LL_ADC_OVS_RATIO_32 + * @arg @ref LL_ADC_OVS_RATIO_64 + * @arg @ref LL_ADC_OVS_RATIO_128 + * @arg @ref LL_ADC_OVS_RATIO_256 */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx) { - if (ADCx == ADC1) + if (ADCx != ADC4) { return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)) + (1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos); } else /* ADCx == ADC4 */ { - return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC4_CFGR2_OVSR)); + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC4_CFGR2_OVSR) | ADC4_OVERSAMPLING_RATIO_PARAMETER); } } @@ -7522,11 +7529,237 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) * * (1): Only for ADC1 instance. */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); } +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Set ADC multimode configuration to operate in independent mode + * or multimode (for devices with several ADC instances). + * @note If multimode configuration: the selected ADC instance is + * either master or slave depending on hardware. + * Refer to reference manual. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * This check can be done with function @ref LL_ADC_IsEnabled() for each + * ADC instance or by using helper macro + * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). + * @rmtoll CCR DUAL LL_ADC_SetMultimode + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param Multimode This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_INDEPENDENT + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL + * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode); +} + +/** + * @brief Get ADC multimode configuration to operate in independent mode + * or multimode (for devices with several ADC instances). + * @note If multimode configuration: the selected ADC instance is + * either master or slave depending on hardware. + * Refer to reference manual. + * @rmtoll CCR DUAL LL_ADC_GetMultimode + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_MULTI_INDEPENDENT + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL + * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM + */ +__STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); +} + +/** + * @brief Set ADC multimode conversion data transfer: no transfer + * or transfer by DMA. + * @note If ADC multimode transfer by DMA is not selected: + * each ADC uses its own DMA channel, with its individual + * DMA transfer settings. + * If ADC multimode transfer by DMA is selected: + * One DMA channel is used for both ADC (DMA of ADC master) + * Specifies the DMA requests mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note How to retrieve multimode conversion data: + * Whatever multimode transfer by DMA setting: using function + * @ref LL_ADC_REG_ReadMultiConversionData32(). + * If ADC multimode transfer by DMA is selected: conversion data + * is a raw data with ADC master and slave concatenated. + * A macro is available to get the conversion data of + * ADC master or ADC slave: see helper macro + * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled + * or enabled without conversion on going on group regular. + * @rmtoll CCR DAMDF LL_ADC_GetMultiDMATransfer\n + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param MultiDMATransfer This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC + * @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B + * @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DAMDF, MultiDMATransfer); +} + +/** + * @brief Get ADC multimode conversion data transfer: no transfer + * or transfer by DMA. + * @note If ADC multimode transfer by DMA is not selected: + * each ADC uses its own DMA channel, with its individual + * DMA transfer settings. + * If ADC multimode transfer by DMA is selected: + * One DMA channel is used for both ADC (DMA of ADC master) + * Specifies the DMA requests mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note How to retrieve multimode conversion data: + * Whatever multimode transfer by DMA setting: using function + * @ref LL_ADC_REG_ReadMultiConversionData32(). + * If ADC multimode transfer by DMA is selected: conversion data + * is a raw data with ADC master and slave concatenated. + * A macro is available to get the conversion data of + * ADC master or ADC slave: see helper macro + * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). + * @rmtoll CCR DAMDF LL_ADC_GetMultiDMATransfer\n + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC + * @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B + * @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B + */ +__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DAMDF)); +} + +/** + * @brief Set ADC multimode delay between 2 sampling phases. + * @note The sampling delay range depends on ADC resolution: + * - ADC resolution 14 bits can have maximum delay of 16 cycles. + * - ADC resolution 12 bits can have maximum delay of 16 cycles. + * - ADC resolution 10 bits can have maximum delay of 15 cycles. + * - ADC resolution 8 bits can have maximum delay of 13 cycles. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * This check can be done with function @ref LL_ADC_IsEnabled() for each + * ADC instance or by using helper macro helper macro + * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). + * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param MultiTwoSamplingDelay This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES_8_BITS + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (1) + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (1) + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES_10_BITS + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (2) + * + * (1) Parameter available only if ADC resolution is 14, 12 or 10 bits. + * (2) Parameter available only if ADC resolution is 14 or 12 bits. + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay); +} + +/** + * @brief Get ADC multimode delay between 2 sampling phases. + * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES_8_BITS + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (1) + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (1) + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES_10_BITS + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (2) + * + * (1) Parameter available only if ADC resolution is 14, 12 or 10 bits. + * (2) Parameter available only if ADC resolution is 14 or 12 bits. + */ +__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY)); +} + +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @} @@ -7583,7 +7816,7 @@ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: deep power down is disabled, 1: deep power down is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); } @@ -7630,7 +7863,7 @@ __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); } @@ -7686,7 +7919,7 @@ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); } @@ -7697,7 +7930,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no ADC disable command on going. */ -__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); } @@ -7755,7 +7988,7 @@ __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t Calibra * @param ADCx ADC instance * @retval 0: calibration complete, 1: calibration in progress. */ -__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); } @@ -7820,7 +8053,7 @@ __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); } @@ -7831,7 +8064,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no command of conversion stop is on going on ADC group regular. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL); } @@ -7845,7 +8078,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7860,7 +8093,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7875,7 +8108,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0x3FF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7890,7 +8123,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7905,7 +8138,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7920,7 +8153,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx) { return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7947,7 +8180,8 @@ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_MULTI_MASTER_SLAVE * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) +__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef *ADCxy_COMMON, + uint32_t ConversionData) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, ConversionData) >> (POSITION_VAL(ConversionData) & 0x1FUL)); } @@ -8010,7 +8244,7 @@ __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ -__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); } @@ -8021,7 +8255,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no command of conversion stop is on going on ADC group injected. */ -__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL); } @@ -8043,7 +8277,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \ >> ADC_JDRX_REGOFFSET_POS)); @@ -8069,7 +8303,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0xFFFF */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \ >> ADC_JDRX_REGOFFSET_POS)); @@ -8095,7 +8329,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0x3FFF */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \ >> ADC_JDRX_REGOFFSET_POS)); @@ -8121,7 +8355,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \ >> ADC_JDRX_REGOFFSET_POS)); @@ -8147,7 +8381,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \ >> ADC_JDRX_REGOFFSET_POS)); @@ -8173,7 +8407,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \ >> ADC_JDRX_REGOFFSET_POS)); @@ -8198,7 +8432,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32 * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL); } @@ -8209,7 +8443,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL); } @@ -8220,7 +8454,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL); } @@ -8231,7 +8465,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL); } @@ -8242,7 +8476,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL); } @@ -8253,7 +8487,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL); } @@ -8264,29 +8498,18 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL); } -/** - * @brief Get flag ADC group injected contexts queue overflow. - * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL); -} - /** * @brief Get flag ADC analog watchdog 1 flag * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1 * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL); } @@ -8297,7 +8520,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL); } @@ -8308,7 +8531,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); } @@ -8393,17 +8616,6 @@ __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx) WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS); } -/** - * @brief Clear flag ADC group injected contexts queue overflow. - * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF); -} - /** * @brief Clear flag ADC analog watchdog 1. * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1 @@ -8523,17 +8735,6 @@ __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx) SET_BIT(ADCx->IER, LL_ADC_IT_JEOS); } -/** - * @brief Enable interruption ADC group injected context queue overflow. - * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF); -} - /** * @brief Enable interruption ADC analog watchdog 1. * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1 @@ -8655,17 +8856,6 @@ __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx) CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS); } -/** - * @brief Disable interruption ADC group injected context queue overflow. - * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF); -} - /** * @brief Disable interruption ADC analog watchdog 1. * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1 @@ -8717,7 +8907,7 @@ __STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL); } @@ -8729,7 +8919,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL); } @@ -8741,7 +8931,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL); } @@ -8753,7 +8943,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL); } @@ -8765,7 +8955,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL); } @@ -8777,7 +8967,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL); } @@ -8789,23 +8979,11 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL); } -/** - * @brief Get state of interruption ADC group injected context queue overflow interrupt state - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL); -} - /** * @brief Get state of interruption ADC analog watchdog 1 * (0: interrupt disabled, 1: interrupt enabled). @@ -8813,7 +8991,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL); } @@ -8825,7 +9003,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL); } @@ -8837,7 +9015,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL); } @@ -8849,7 +9027,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL); } @@ -8864,9 +9042,9 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef *ADCx) */ /* Initialization of some features of ADC common parameters and multimode */ -ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *pADCxyCOMMON); -ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *pADCxyCOMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInit); -void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInit); +ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *pADCxy_COMMON); +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *pADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct); +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct); /* De-initialization of ADC instance, ADC group regular and ADC group injected */ /* (availability of ADC group injected depends on STM32 families) */ @@ -8874,11 +9052,11 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *pADCx); /* Initialization of some features of ADC instance */ ErrorStatus LL_ADC_Init(ADC_TypeDef *pADCx, LL_ADC_InitTypeDef *pADC_InitStruct); -void LL_ADC_StructInit(ADC_TypeDef *pADCx, LL_ADC_InitTypeDef *pADC_InitStruct); +void LL_ADC_StructInit(const ADC_TypeDef *pADCx, LL_ADC_InitTypeDef *pADC_InitStruct); /* Initialization of some features of ADC instance and ADC group regular */ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *pADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct); -void LL_ADC_REG_StructInit(ADC_TypeDef *pADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct); +void LL_ADC_REG_StructInit(const ADC_TypeDef *pADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct); /* Initialization of some features of ADC instance and ADC group injected */ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *pADCx, LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct); diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_bus.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_bus.h index 873bc46027d..5fae597c169 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_bus.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_bus.h @@ -78,9 +78,21 @@ extern "C" { #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN #define LL_AHB1_GRP1_PERIPH_RAMCFG RCC_AHB1ENR_RAMCFGEN +#if defined(DMA2D) #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN +#endif /* DMA2D */ +#if defined(GFXMMU) +#define LL_AHB1_GRP1_PERIPH_GFXMMU RCC_AHB1ENR_GFXMMUEN +#endif /* defined(GFXMMU) */ +#if defined(GPU2D) +#define LL_AHB1_GRP1_PERIPH_GPU2D RCC_AHB1ENR_GPU2DEN +#endif /* defined(GPU2D) */ +#if defined(DCACHE2) +#define LL_AHB1_GRP1_PERIPH_DCACHE2 RCC_AHB1ENR_DCACHE2EN +#endif /* defined(DCACHE2) */ #define LL_AHB1_GRP1_PERIPH_GTZC1 RCC_AHB1ENR_GTZC1EN #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN +#define LL_AHB1_GRP1_PERIPH_ICACHE1 RCC_AHB1SMENR_ICACHESMEN #define LL_AHB1_GRP1_PERIPH_DCACHE1 RCC_AHB1ENR_DCACHE1EN #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1ENR_SRAM1EN /** @@ -96,13 +108,31 @@ extern "C" { #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR1_GPIOCEN #define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR1_GPIODEN #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR1_GPIOEEN +#if defined(GPIOF) #define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR1_GPIOFEN +#endif /* GPIOF */ #define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR1_GPIOGEN #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR1_GPIOHEN +#if defined (GPIOI) #define LL_AHB2_GRP1_PERIPH_GPIOI RCC_AHB2ENR1_GPIOIEN -#define LL_AHB2_GRP1_PERIPH_ADC1 RCC_AHB2ENR1_ADC1EN +#endif /* GPIOI */ +#if defined (GPIOJ) +#define LL_AHB2_GRP1_PERIPH_GPIOJ RCC_AHB2ENR1_GPIOJEN +#endif /* defined (GPIOJ) */ +#define LL_AHB2_GRP1_PERIPH_ADC12 RCC_AHB2ENR1_ADC12EN #define LL_AHB2_GRP1_PERIPH_DCMI_PSSI RCC_AHB2ENR1_DCMI_PSSIEN -#define LL_AHB2_GRP1_PERIPH_USBFS RCC_AHB2ENR1_OTGEN +#if defined(USB_OTG_FS) +#define LL_AHB2_GRP1_PERIPH_OTG_FS RCC_AHB2ENR1_OTGEN +/* Legacy define */ +#define LL_AHB2_GRP1_PERIPH_USBFS LL_AHB2_GRP1_PERIPH_OTG_FS +#elif defined(USB_OTG_HS) +#define LL_AHB2_GRP1_PERIPH_OTG_HS RCC_AHB2ENR1_OTGEN +/* Legacy define */ +#define LL_AHB2_GRP1_PERIPH_USBHS LL_AHB2_GRP1_PERIPH_OTG_HS +#endif /* defined(USB_OTG_HS) */ +#if defined(RCC_AHB2ENR1_USBPHYCEN) +#define LL_AHB2_GRP1_PERIPH_USBPHY RCC_AHB2ENR1_USBPHYCEN +#endif /* defined(RCC_AHB2ENR1_USBPHYCEN) */ #if defined(AES) #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR1_AESEN #endif /* AES */ @@ -114,13 +144,21 @@ extern "C" { #if defined(SAES) #define LL_AHB2_GRP1_PERIPH_SAES RCC_AHB2ENR1_SAESEN #endif /* SAES */ +#if defined(OCTOSPIM) #define LL_AHB2_GRP1_PERIPH_OCTOSPIM RCC_AHB2ENR1_OCTOSPIMEN +#endif /* OCTOSPIM */ #define LL_AHB2_GRP1_PERIPH_OTFDEC1 RCC_AHB2ENR1_OTFDEC1EN +#if defined (OTFDEC2) #define LL_AHB2_GRP1_PERIPH_OTFDEC2 RCC_AHB2ENR1_OTFDEC2EN +#endif /* OTFDEC2 */ #define LL_AHB2_GRP1_PERIPH_SDMMC1 RCC_AHB2ENR1_SDMMC1EN +#if defined(SDMMC2) #define LL_AHB2_GRP1_PERIPH_SDMMC2 RCC_AHB2ENR1_SDMMC2EN +#endif /* SDMMC2 */ #define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2ENR1_SRAM2EN +#if defined(SRAM3_BASE) #define LL_AHB2_GRP1_PERIPH_SRAM3 RCC_AHB2ENR1_SRAM3EN +#endif /* SRAM3_BASE */ /** * @} @@ -137,7 +175,8 @@ extern "C" { #define LL_AHB3_GRP1_PERIPH_LPDMA1 RCC_AHB3ENR_LPDMA1EN #define LL_AHB3_GRP1_PERIPH_ADF1 RCC_AHB3ENR_ADF1EN #define LL_AHB3_GRP1_PERIPH_GTZC2 RCC_AHB3ENR_GTZC2EN -#define LL_AHB3_GRP1_PERIPH_SRAM4 RCC_AHB3SMENR_SRAM4SMEN +#define LL_AHB3_GRP1_PERIPH_SRAM4 RCC_AHB3ENR_SRAM4EN + /** * @} */ @@ -146,9 +185,22 @@ extern "C" { * @{ */ #define LL_AHB2_GRP2_PERIPH_ALL 0xFFFFFFFFU +#if defined(FMC_BASE) #define LL_AHB2_GRP2_PERIPH_FSMC RCC_AHB2ENR2_FSMCEN +#endif /* FMC_BASE */ #define LL_AHB2_GRP2_PERIPH_OCTOSPI1 RCC_AHB2ENR2_OCTOSPI1EN +#if defined(OCTOSPI2) #define LL_AHB2_GRP2_PERIPH_OCTOSPI2 RCC_AHB2ENR2_OCTOSPI2EN +#endif /* OCTOSPI2 */ +#if defined(HSPI1) +#define LL_AHB2_GRP2_PERIPH_HSPI1 RCC_AHB2ENR2_HSPI1EN +#endif /* defined(HSPI1) */ +#if defined(SRAM6_BASE) +#define LL_AHB2_GRP2_PERIPH_SRAM6 RCC_AHB2ENR2_SRAM6EN +#endif /* SRAM6_BASE */ +#if defined(SRAM5_BASE) +#define LL_AHB2_GRP2_PERIPH_SRAM5 RCC_AHB2ENR2_SRAM5EN +#endif /* SRAM5_BASE */ /** * @} */ @@ -165,13 +217,18 @@ extern "C" { #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN +#if defined(USART2) #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN +#endif /* USART2 */ #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN +#if defined(USART6) +#define LL_APB1_GRP1_PERIPH_USART6 RCC_APB1ENR1_USART6EN +#endif /* defined(USART6) */ /** * @} */ @@ -184,7 +241,15 @@ extern "C" { #define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN #define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN #define LL_APB1_GRP2_PERIPH_FDCAN1 RCC_APB1ENR2_FDCAN1EN +#if defined(UCPD1) #define LL_APB1_GRP2_PERIPH_UCPD1 RCC_APB1ENR2_UCPD1EN +#endif /* UCPD1 */ +#if defined(I2C5) +#define LL_APB1_GRP2_PERIPH_I2C5 RCC_APB1ENR2_I2C5EN +#endif /* defined(I2C5) */ +#if defined(I2C6) +#define LL_APB1_GRP2_PERIPH_I2C6 RCC_APB1ENR2_I2C6EN +#endif /* defined(I2C6) */ /** * @} */ @@ -201,7 +266,18 @@ extern "C" { #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN +#if defined(SAI2) #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN +#endif /* SAI2 */ +#if defined(USB_DRD_FS) +#define LL_APB2_GRP1_PERIPH_USB_FS RCC_APB2ENR_USBEN +#endif /* USB_DRD_FS */ +#if defined(LTDC) +#define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN +#endif /* defined(LTDC) */ +#if defined(DSI) +#define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIHOSTEN +#endif /* defined(DSI) */ /** * @} */ @@ -228,27 +304,49 @@ extern "C" { /** @defgroup BUS_LL_EC_SRDAMR_GRP1_PERIPH SRDAMR GRP1 PERIPH * @{ */ -#define LL_SRDAMR_GRP1_PERIPH_ALL 0xFFFFFFFFU -#define LL_SRDAMR_GRP1_PERIPH_SPI3AMEN RCC_SRDAMR_SPI3AMEN -#define LL_SRDAMR_GRP1_PERIPH_LPUART1AMEN RCC_SRDAMR_LPUART1AMEN -#define LL_SRDAMR_GRP1_PERIPH_I2C3AMEN RCC_SRDAMR_I2C3AMEN -#define LL_SRDAMR_GRP1_PERIPH_LPTIM1AMEN RCC_SRDAMR_LPTIM1AMEN -#define LL_SRDAMR_GRP1_PERIPH_LPTIM3AMEN RCC_SRDAMR_LPTIM3AMEN -#define LL_SRDAMR_GRP1_PERIPH_LPTIM4AMEN RCC_SRDAMR_LPTIM4AMEN -#define LL_SRDAMR_GRP1_PERIPH_OPAMPAMEN RCC_SRDAMR_OPAMPAMEN -#define LL_SRDAMR_GRP1_PERIPH_COMPAMEN RCC_SRDAMR_COMPAMEN -#define LL_SRDAMR_GRP1_PERIPH_VREFAMEN RCC_SRDAMR_VREFAMEN -#define LL_SRDAMR_GRP1_PERIPH_RTCAPBAMEN RCC_SRDAMR_RTCAPBAMEN -#define LL_SRDAMR_GRP1_PERIPH_ADC4AMEN RCC_SRDAMR_ADC4AMEN -#define LL_SRDAMR_GRP1_PERIPH_LPGPIO1AMEN RCC_SRDAMR_LPGPIO1AMEN -#define LL_SRDAMR_GRP1_PERIPH_DAC1AMEN RCC_SRDAMR_DAC1AMEN -#define LL_SRDAMR_GRP1_PERIPH_LPDMA1AMEN RCC_SRDAMR_LPDMA1AMEN -#define LL_SRDAMR_GRP1_PERIPH_ADF1AMEN RCC_SRDAMR_ADF1AMEN -#define LL_SRDAMR_GRP1_PERIPH_SRAM4AMEN RCC_SRDAMR_SRAM4AMEN +#define LL_SRDAMR_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_SRDAMR_GRP1_PERIPH_SPI3 RCC_SRDAMR_SPI3AMEN +#define LL_SRDAMR_GRP1_PERIPH_LPUART1 RCC_SRDAMR_LPUART1AMEN +#define LL_SRDAMR_GRP1_PERIPH_I2C3 RCC_SRDAMR_I2C3AMEN +#define LL_SRDAMR_GRP1_PERIPH_LPTIM1 RCC_SRDAMR_LPTIM1AMEN +#define LL_SRDAMR_GRP1_PERIPH_LPTIM3 RCC_SRDAMR_LPTIM3AMEN +#define LL_SRDAMR_GRP1_PERIPH_LPTIM4 RCC_SRDAMR_LPTIM4AMEN +#define LL_SRDAMR_GRP1_PERIPH_OPAMP RCC_SRDAMR_OPAMPAMEN +#define LL_SRDAMR_GRP1_PERIPH_COMP RCC_SRDAMR_COMPAMEN +#define LL_SRDAMR_GRP1_PERIPH_VREF RCC_SRDAMR_VREFAMEN +#define LL_SRDAMR_GRP1_PERIPH_RTCAPB RCC_SRDAMR_RTCAPBAMEN +#define LL_SRDAMR_GRP1_PERIPH_ADC4 RCC_SRDAMR_ADC4AMEN +#define LL_SRDAMR_GRP1_PERIPH_LPGPIO1 RCC_SRDAMR_LPGPIO1AMEN +#define LL_SRDAMR_GRP1_PERIPH_DAC1 RCC_SRDAMR_DAC1AMEN +#define LL_SRDAMR_GRP1_PERIPH_LPDMA1 RCC_SRDAMR_LPDMA1AMEN +#define LL_SRDAMR_GRP1_PERIPH_ADF1 RCC_SRDAMR_ADF1AMEN +#define LL_SRDAMR_GRP1_PERIPH_SRAM4 RCC_SRDAMR_SRAM4AMEN +/** + * @} + */ +/** @defgroup LL_RCC_Aliased_Constants LL RCC Aliased Constants maintained for legacy purpose + * @{ + */ +#define LL_AHB2_GRP1_PERIPH_ADC1 LL_AHB2_GRP1_PERIPH_ADC12 +#define LL_SRDAMR_GRP1_PERIPH_SPI3AMEN LL_SRDAMR_GRP1_PERIPH_SPI3 +#define LL_SRDAMR_GRP1_PERIPH_LPUART1AMEN LL_SRDAMR_GRP1_PERIPH_LPUART1 +#define LL_SRDAMR_GRP1_PERIPH_I2C3AMEN LL_SRDAMR_GRP1_PERIPH_I2C3 +#define LL_SRDAMR_GRP1_PERIPH_LPTIM1AMEN LL_SRDAMR_GRP1_PERIPH_LPTIM1 +#define LL_SRDAMR_GRP1_PERIPH_LPTIM3AMEN LL_SRDAMR_GRP1_PERIPH_LPTIM3 +#define LL_SRDAMR_GRP1_PERIPH_LPTIM4AMEN LL_SRDAMR_GRP1_PERIPH_LPTIM4 +#define LL_SRDAMR_GRP1_PERIPH_OPAMPAMEN LL_SRDAMR_GRP1_PERIPH_OPAMP +#define LL_SRDAMR_GRP1_PERIPH_COMPAMEN LL_SRDAMR_GRP1_PERIPH_COMP +#define LL_SRDAMR_GRP1_PERIPH_VREFAMEN LL_SRDAMR_GRP1_PERIPH_VREF +#define LL_SRDAMR_GRP1_PERIPH_RTCAPBAMEN LL_SRDAMR_GRP1_PERIPH_RTCAPB +#define LL_SRDAMR_GRP1_PERIPH_ADC4AMEN LL_SRDAMR_GRP1_PERIPH_ADC4 +#define LL_SRDAMR_GRP1_PERIPH_LPGPIO1AMEN LL_SRDAMR_GRP1_PERIPH_LPGPIO1 +#define LL_SRDAMR_GRP1_PERIPH_DAC1AMEN LL_SRDAMR_GRP1_PERIPH_DAC1 +#define LL_SRDAMR_GRP1_PERIPH_LPDMA1AMEN LL_SRDAMR_GRP1_PERIPH_LPDMA1 +#define LL_SRDAMR_GRP1_PERIPH_ADF1AMEN LL_SRDAMR_GRP1_PERIPH_ADF1 +#define LL_SRDAMR_GRP1_PERIPH_SRAM4AMEN LL_SRDAMR_GRP1_PERIPH_SRAM4 /** * @} */ - /** * @} */ @@ -262,6 +360,20 @@ extern "C" { /** @defgroup BUS_LL_EF_AHB1 AHB1 * @{ */ + +/** + * @brief Enable AHB1 bus clock. + * @rmtoll CFGR2 AHB1DIS LL_AHB1_GRP1_EnableBusClock + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableBusClock(void) +{ + __IO uint32_t tmpreg; + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); + (void)(tmpreg); +} + /** * @brief Enable AHB1 peripherals clock. * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_EnableClock\n @@ -273,6 +385,9 @@ extern "C" { * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n * AHB1ENR RAMCFGEN LL_AHB1_GRP1_EnableClock\n * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GFXMMUEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPU2DEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DCACHE2EN LL_AHB1_GRP1_EnableClock\n * AHB1ENR GTZC1EN LL_AHB1_GRP1_EnableClock\n * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n * AHB1ENR DCACHE1EN LL_AHB1_GRP1_EnableClock\n @@ -287,11 +402,16 @@ extern "C" { * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) @@ -314,6 +434,9 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR RAMCFGEN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GFXMMUEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPU2DEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DCACHE2EN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR GTZC1EN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR DCACHEEN LL_AHB1_GRP1_IsEnabledClock\n @@ -328,11 +451,16 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). */ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) @@ -340,6 +468,17 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); } +/** + * @brief Disable AHB1 bus clock. + * @note except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1. + * @rmtoll CFGR2 AHB1DIS LL_AHB1_GRP1_DisableBusClock + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableBusClock(void) +{ + SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); +} + /** * @brief Disable AHB1 peripherals clock. * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_DisableClock\n @@ -351,10 +490,13 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n * AHB1ENR RAMCFGEN LL_AHB1_GRP1_DisableClock\n * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GFXMMUEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPU2DEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DCACHE2EN LL_AHB1_GRP1_DisableClock\n * AHB1ENR GTZC1EN LL_AHB1_GRP1_DisableClock\n * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n * AHB1ENR DCACHEEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR SRAM1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR SRAM1EN LL_AHB1_GRP1_DisableClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 @@ -365,11 +507,16 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) @@ -387,6 +534,9 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ForceReset\n * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ForceReset\n * AHB1RSTR DMA2DRSTR LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GFXMMURSTR LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPU2DRSTR LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DCACHE2RSTR LL_AHB1_GRP1_ForceReset\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 @@ -396,7 +546,11 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) @@ -414,6 +568,9 @@ __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ReleaseReset\n * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ReleaseReset\n * AHB1RSTR DMA2DRSTR LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GFXMMURSTR LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPU2DRSTR LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DCACHE2RSTR LL_AHB1_GRP1_ReleaseReset\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 @@ -423,7 +580,12 @@ __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) @@ -442,8 +604,12 @@ __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR GPU2DSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR DCACHE2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR BKPSRAMSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR ICACHESMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR DCACHESMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: @@ -456,11 +622,17 @@ __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_ICACHE1 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) @@ -483,9 +655,14 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) * AHB1SMENR TSCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR GPU2DSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR DCACHE2SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n * AHB1SMENR BKPSRAMSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR ICACHESMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n * AHB1SMENR DCACHESMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 @@ -496,11 +673,17 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_ICACHE1 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). */ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) @@ -519,9 +702,14 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_DisableClockStopSleep\n * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR GPU2DSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR DCACHE2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n * AHB1SMENR BKPSRAMSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR ICACHESMEN LL_AHB1_GRP1_DisableClockStopSleep\n * AHB1SMENR DCACHESMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 @@ -532,11 +720,17 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_ICACHE1 * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) @@ -551,6 +745,20 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) /** @defgroup BUS_LL_EF_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH * @{ */ + +/** + * @brief Enable AHB2_1 bus clock. + * @rmtoll CFGR2 AHB2DIS1 LL_AHB2_GRP1_EnableBusClock + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableBusClock(void) +{ + __IO uint32_t tmpreg; + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); + (void)(tmpreg); +} + /** * @brief Enable AHB2 peripherals clock. * @rmtoll AHB2ENR1 GPIOAEN LL_AHB2_GRP1_EnableClock\n @@ -562,9 +770,11 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) * AHB2ENR1 GPIOGEN LL_AHB2_GRP1_EnableClock\n * AHB2ENR1 GPIOHEN LL_AHB2_GRP1_EnableClock\n * AHB2ENR1 GPIOIEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 ADC1EN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 GPIOJEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 ADC12EN LL_AHB2_GRP1_EnableClock\n * AHB2ENR1 DCMI_PSSIEN LL_AHB2_GRP1_EnableClock\n * AHB2ENR1 OTGEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR1 USBPHYCEN LL_AHB2_GRP1_EnableClock\n * AHB2ENR1 AESEN LL_AHB2_GRP1_EnableClock\n * AHB2ENR1 HASHEN LL_AHB2_GRP1_EnableClock\n * AHB2ENR1 RNGEN LL_AHB2_GRP1_EnableClock\n @@ -584,25 +794,30 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI - * @arg @ref LL_AHB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI - * @arg @ref LL_AHB2_GRP1_PERIPH_USBFS + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG * @arg @ref LL_AHB2_GRP1_PERIPH_PKA - * @arg @ref LL_AHB2_GRP1_PERIPH_SAES - * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 - * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) @@ -625,9 +840,11 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) * AHB2ENR1 GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n * AHB2ENR1 GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n * AHB2ENR1 GPIOIEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 ADC1EN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 GPIOJEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 ADC12EN LL_AHB2_GRP1_IsEnabledClock\n * AHB2ENR1 DCMI_PSSIEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 OTGFSEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 OTGEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 USBPHYCEN LL_AHB2_GRP1_IsEnabledClock\n * AHB2ENR1 AESEN LL_AHB2_GRP1_IsEnabledClock\n * AHB2ENR1 HASHEN LL_AHB2_GRP1_IsEnabledClock\n * AHB2ENR1 RNGEN LL_AHB2_GRP1_IsEnabledClock\n @@ -638,6 +855,8 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) * AHB2ENR1 OTFDEC2EN LL_AHB2_GRP1_IsEnabledClock\n * AHB2ENR1 SDMMC1EN LL_AHB2_GRP1_IsEnabledClock\n * AHB2ENR1 SDMMC2EN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 SRAM2EN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR1 SRAM3EN LL_AHB2_GRP1_IsEnabledClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_ALL * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA @@ -645,25 +864,30 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI - * @arg @ref LL_AHB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI - * @arg @ref LL_AHB2_GRP1_PERIPH_USBFS + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG * @arg @ref LL_AHB2_GRP1_PERIPH_PKA - * @arg @ref LL_AHB2_GRP1_PERIPH_SAES - * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 - * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) + * + * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). */ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) @@ -671,6 +895,17 @@ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) return ((READ_BIT(RCC->AHB2ENR1, Periphs) == Periphs) ? 1UL : 0UL); } +/** + * @brief Disable AHB2_1 bus clock. + * @note except for SRAM2 and SRAM3. + * @rmtoll CFGR2 AHB2DIS1 LL_AHB2_GRP1_DisableBusClock + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_DisableBusClock(void) +{ + SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); +} + /** * @brief Disable AHB2 peripherals clock. * @rmtoll AHB2ENR1 GPIOAEN LL_AHB2_GRP1_DisableClock\n @@ -682,9 +917,11 @@ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) * AHB2ENR1 GPIOGEN LL_AHB2_GRP1_DisableClock\n * AHB2ENR1 GPIOHEN LL_AHB2_GRP1_DisableClock\n * AHB2ENR1 GPIOIEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 ADC1EN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 GPIOJEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 ADC12EN LL_AHB2_GRP1_DisableClock\n * AHB2ENR1 DCMI_PSSIEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 OTGEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 OTGEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 USBPHYCEN LL_AHB2_GRP1_DisableClock\n * AHB2ENR1 AESEN LL_AHB2_GRP1_DisableClock\n * AHB2ENR1 HASHEN LL_AHB2_GRP1_DisableClock\n * AHB2ENR1 RNGEN LL_AHB2_GRP1_DisableClock\n @@ -695,6 +932,8 @@ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) * AHB2ENR1 OTFDEC2EN LL_AHB2_GRP1_DisableClock\n * AHB2ENR1 SDMMC1EN LL_AHB2_GRP1_DisableClock\n * AHB2ENR1 SDMMC2EN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 SRAM2EN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR1 SRAM3EN LL_AHB2_GRP1_DisableClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_ALL * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA @@ -702,23 +941,30 @@ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI - * @arg @ref LL_AHB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI - * @arg @ref LL_AHB2_GRP1_PERIPH_USBFS + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG * @arg @ref LL_AHB2_GRP1_PERIPH_PKA - * @arg @ref LL_AHB2_GRP1_PERIPH_SAES - * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) @@ -735,11 +981,13 @@ __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) * AHB2RSTR1 GPIOERST LL_AHB2_GRP1_ForceReset\n * AHB2RSTR1 GPIOFRST LL_AHB2_GRP1_ForceReset\n * AHB2RSTR1 GPIOGRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 GPIOHRST LL_AHB2_GRP1_ForceResetn + * AHB2RSTR1 GPIOHRST LL_AHB2_GRP1_ForceReset\n * AHB2RSTR1 GPIOIRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 ADC1RST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 GPIOJRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 ADC12RST LL_AHB2_GRP1_ForceReset\n * AHB2RSTR1 DCMI_PSSIRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 OTGRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 OTGRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 USBPHYCRST LL_AHB2_GRP1_ForceReset\n * AHB2RSTR1 AESRST LL_AHB2_GRP1_ForceReset\n * AHB2RSTR1 HASHRST LL_AHB2_GRP1_ForceReset\n * AHB2RSTR1 RNGRST LL_AHB2_GRP1_ForceReset\n @@ -748,6 +996,8 @@ __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) * AHB2RSTR1 OCTOSPIMRST LL_AHB2_GRP1_ForceReset\n * AHB2RSTR1 OTFDEC1RST LL_AHB2_GRP1_ForceReset\n * AHB2RSTR1 OTFDEC2RST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 SDMMC1RST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR1 SDMMC2RST LL_AHB2_GRP1_ForceReset\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_ALL * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA @@ -755,23 +1005,28 @@ __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI - * @arg @ref LL_AHB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI - * @arg @ref LL_AHB2_GRP1_PERIPH_USBFS + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG * @arg @ref LL_AHB2_GRP1_PERIPH_PKA - * @arg @ref LL_AHB2_GRP1_PERIPH_SAES - * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) @@ -788,11 +1043,13 @@ __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) * AHB2RSTR1 GPIOERST LL_AHB2_GRP1_ReleaseReset\n * AHB2RSTR1 GPIOFRST LL_AHB2_GRP1_ReleaseReset\n * AHB2RSTR1 GPIOGRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 GPIOHRST LL_AHB2_GRP1_ReleaseResetn + * AHB2RSTR1 GPIOHRST LL_AHB2_GRP1_ReleaseReset\n * AHB2RSTR1 GPIOIRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 ADC1RST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 GPIOJRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 ADC12RST LL_AHB2_GRP1_ReleaseReset\n * AHB2RSTR1 DCMI_PSSIRST LL_AHB2_GRP1_ReleaseReset\n * AHB2RSTR1 OTGRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR1 USBPHYCRST LL_AHB2_GRP1_ReleaseReset\n * AHB2RSTR1 AESRST LL_AHB2_GRP1_ReleaseReset\n * AHB2RSTR1 HASHRST LL_AHB2_GRP1_ReleaseReset\n * AHB2RSTR1 RNGRST LL_AHB2_GRP1_ReleaseReset\n @@ -810,23 +1067,28 @@ __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI - * @arg @ref LL_AHB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI - * @arg @ref LL_AHB2_GRP1_PERIPH_USBFS + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG * @arg @ref LL_AHB2_GRP1_PERIPH_PKA - * @arg @ref LL_AHB2_GRP1_PERIPH_SAES - * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) @@ -843,11 +1105,13 @@ __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) * AHB2SMENR1 GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR1 GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR1 GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleepn + * AHB2SMENR1 GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR1 GPIOISMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 ADC1SMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 GPIOJSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 ADC12SMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR1 DCMI_PSSISMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR1 OTGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2ENR1 USBPHYCEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR1 AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR1 HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR1 RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n @@ -858,8 +1122,8 @@ __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) * AHB2SMENR1 OTFDEC2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR1 SDMMC1SMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR1 SDMMC2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR1 SRAM3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 SRAM4SMEN LL_AHB2_GRP1_EnableClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_ALL * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA @@ -867,25 +1131,30 @@ __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI - * @arg @ref LL_AHB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI - * @arg @ref LL_AHB2_GRP1_PERIPH_USBFS + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG * @arg @ref LL_AHB2_GRP1_PERIPH_PKA - * @arg @ref LL_AHB2_GRP1_PERIPH_SAES - * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 - * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) @@ -906,11 +1175,13 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) * AHB2SMENR1 GPIOESMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n * AHB2SMENR1 GPIOFSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n * AHB2SMENR1 GPIOGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 GPIOHSMEN LL_AHB2_GRP1_IsEnabledClockStopSleepn + * AHB2SMENR1 GPIOHSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n * AHB2SMENR1 GPIOISMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 ADC1SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 GPIOJSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 ADC12SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n * AHB2SMENR1 DCMI_PSSISMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n * AHB2SMENR1 OTGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 USBPHYCMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n * AHB2SMENR1 AESSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n * AHB2SMENR1 HASHSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n * AHB2SMENR1 RNGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n @@ -921,8 +1192,8 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) * AHB2SMENR1 OTFDEC2SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n * AHB2SMENR1 SDMMC1SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n * AHB2SMENR1 SDMMC2SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR1 SRAM2SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n * AHB2SMENR1 SRAM3SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 SRAM4SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_ALL * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA @@ -930,25 +1201,30 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI - * @arg @ref LL_AHB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI - * @arg @ref LL_AHB2_GRP1_PERIPH_USBFS + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG * @arg @ref LL_AHB2_GRP1_PERIPH_PKA - * @arg @ref LL_AHB2_GRP1_PERIPH_SAES - * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 - * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) + * + * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). */ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) @@ -965,11 +1241,13 @@ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * AHB2SMENR1 GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR1 GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR1 GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleepn + * AHB2SMENR1 GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR1 GPIOISMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 ADC1SMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 GPIOJSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 ADC12SMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR1 DCMI_PSSISMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR1 OTGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 USBPHYCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR1 AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR1 HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR1 RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n @@ -980,8 +1258,8 @@ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * AHB2SMENR1 OTFDEC2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR1 SDMMC1SMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR1 SDMMC2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 SRAM3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 SRAM4SMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR1 SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR1 SRAM3SMEN LL_AHB2_GRP1_DisableClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_ALL * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA @@ -989,25 +1267,30 @@ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI - * @arg @ref LL_AHB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI - * @arg @ref LL_AHB2_GRP1_PERIPH_USBFS + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) * @arg @ref LL_AHB2_GRP1_PERIPH_AES * @arg @ref LL_AHB2_GRP1_PERIPH_HASH * @arg @ref LL_AHB2_GRP1_PERIPH_RNG * @arg @ref LL_AHB2_GRP1_PERIPH_PKA - * @arg @ref LL_AHB2_GRP1_PERIPH_SAES - * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 - * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs) @@ -1022,6 +1305,20 @@ __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs) /** @defgroup BUS_LL_EF_AHB3 AHB3 * @{ */ + +/** + * @brief Enable AHB3 bus clock. + * @rmtoll CFGR2 AHB3DIS LL_AHB3_GRP1_EnableBusClock + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_EnableBusClock(void) +{ + __IO uint32_t tmpreg; + CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); + tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); + (void)(tmpreg); +} + /** * @brief Enable AHB3 peripherals clock. * @rmtoll AHB3ENR LPGPIO1EN LL_AHB3_GRP1_EnableClock\n @@ -1031,6 +1328,7 @@ __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs) * AHB3ENR LPDMA1EN LL_AHB3_GRP1_EnableClock\n * AHB3ENR ADF1EN LL_AHB3_GRP1_EnableClock\n * AHB3ENR GTZC2EN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR SRAM4EN LL_AHB3_GRP1_EnableClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB3_GRP1_PERIPH_ALL * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1 @@ -1040,6 +1338,7 @@ __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs) * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1 * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1 * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2 + * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4 * @retval None */ __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) @@ -1060,6 +1359,7 @@ __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) * AHB3ENR LPDMA1EN LL_AHB3_GRP1_IsEnabledClock\n * AHB3ENR ADF1EN LL_AHB3_GRP1_IsEnabledClock\n * AHB3ENR GTZC2EN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR SRAM4EN LL_AHB3_GRP1_IsEnabledClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB3_GRP1_PERIPH_ALL * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1 @@ -1069,6 +1369,7 @@ __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1 * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1 * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2 + * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4 * @retval State of Periphs (1 or 0). */ __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) @@ -1076,6 +1377,16 @@ __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL); } +/** + * @brief Disable AHB3 bus clock. + * @rmtoll CFGR2 AHB3DIS LL_AHB3_GRP1_DisableBusClock + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_DisableBusClock(void) +{ + SET_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); +} + /** * @brief Disable AHB3 peripherals clock. * @rmtoll AHB3ENR LPGPIO1EN LL_AHB3_GRP1_DisableClock\n @@ -1085,6 +1396,7 @@ __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) * AHB3ENR LPDMA1EN LL_AHB3_GRP1_DisableClock\n * AHB3ENR ADF1EN LL_AHB3_GRP1_DisableClock\n * AHB3ENR GTZC2EN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR SRAM4EN LL_AHB3_GRP1_DisableClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB3_GRP1_PERIPH_ALL * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1 @@ -1094,6 +1406,7 @@ __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1 * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1 * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2 + * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4 * @retval None */ __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) @@ -1191,7 +1504,7 @@ __STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs) * AHB3SMENR LPDMA1SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n * AHB3SMENR ADF1SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n * AHB3SMENR GTZC2SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n - * AHB3SMENR SRAM4SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep + * AHB3SMENR SRAM4SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB3_GRP1_PERIPH_ALL * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1 @@ -1218,7 +1531,7 @@ __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * AHB3SMENR LPDMA1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n * AHB3SMENR ADF1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n * AHB3SMENR GTZC2SMEN LL_AHB3_GRP1_DisableClockStopSleep\n - * AHB3SMENR SRAM4SMEN LL_AHB3_GRP1_EnableClockStopSleep + * AHB3SMENR SRAM4SMEN LL_AHB3_GRP1_DisableClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB3_GRP1_PERIPH_ALL * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1 @@ -1243,16 +1556,39 @@ __STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs) /** @defgroup BUS_LL_EF_AHB2_GRP2_PERIPH AHB2 GRP2 PERIPH * @{ */ + +/** + * @brief Enable AHB2_2 bus clock. + * @rmtoll CFGR2 AHB2DIS2 LL_AHB2_GRP2_EnableBusClock + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP2_EnableBusClock(void) +{ + __IO uint32_t tmpreg; + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); + (void)(tmpreg); +} + /** * @brief Enable AHB2 peripherals clock. * @rmtoll AHB2ENR2 FSMCEN LL_AHB2_GRP2_EnableClock\n * AHB2ENR2 OCTOSPI1EN LL_AHB2_GRP2_EnableClock\n * AHB2ENR2 OCTOSPI2EN LL_AHB2_GRP2_EnableClock\n + * AHB2ENR2 HSPI1EN LL_AHB2_GRP2_EnableClock\n + * AHB2ENR2 SRAM6EN LL_AHB2_GRP2_EnableClock\n + * AHB2ENR2 SRAM5EN LL_AHB2_GRP2_EnableClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP2_PERIPH_ALL - * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC + * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*) + * + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB2_GRP2_EnableClock(uint32_t Periphs) @@ -1265,15 +1601,23 @@ __STATIC_INLINE void LL_AHB2_GRP2_EnableClock(uint32_t Periphs) } /** - * @brief Check if AHB4 peripheral clock is enabled or not + * @brief Check if AHB2 peripheral clock is enabled or not * @rmtoll AHB2ENR2 FSMCEN LL_AHB2_GRP2_IsEnabledClock\n * AHB2ENR2 OCTOSPI1EN LL_AHB2_GRP2_IsEnabledClock\n * AHB2ENR2 OCTOSPI2EN LL_AHB2_GRP2_IsEnabledClock\n + * AHB2ENR2 HSPI1EN LL_AHB2_GRP2_IsEnabledClock\n + * AHB2ENR2 SRAM6EN LL_AHB2_GRP2_DisableClock\n + * AHB2ENR2 SRAM5EN LL_AHB2_GRP2_IsEnabledClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP2_PERIPH_ALL - * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC + * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*) + * + * (*) value not defined in all devices. * @retval None * @retval State of Periphs (1 or 0). */ @@ -1283,15 +1627,33 @@ __STATIC_INLINE uint32_t LL_AHB2_GRP2_IsEnabledClock(uint32_t Periphs) } /** - * @brief Disable AHB4 peripherals clock. + * @brief Disable AHB2_2 bus clock. + * @rmtoll CFGR2 AHB2DIS2 LL_AHB2_GRP2_DisableBusClock + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP2_DisableBusClock(void) +{ + SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); +} + +/** + * @brief Disable AHB2 peripherals clock. * @rmtoll AHB2ENR2 FSMCEN LL_AHB2_GRP2_DisableClock\n * AHB2ENR2 OCTOSPI1EN LL_AHB2_GRP2_DisableClock\n * AHB2ENR2 OCTOSPI2EN LL_AHB2_GRP2_DisableClock\n + * AHB2ENR2 HSPI1EN LL_AHB2_GRP2_DisableClock\n + * AHB2ENR2 SRAM6EN LL_AHB2_GRP2_DisableClock\n + * AHB2ENR2 SRAM5EN LL_AHB2_GRP2_DisableClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP2_PERIPH_ALL - * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC + * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB2_GRP2_DisableClock(uint32_t Periphs) @@ -1300,15 +1662,19 @@ __STATIC_INLINE void LL_AHB2_GRP2_DisableClock(uint32_t Periphs) } /** - * @brief Force AHB4 peripherals reset. + * @brief Force AHB2 peripherals reset. * @rmtoll AHB2RSTR2 FSMCRST LL_AHB2_GRP2_ForceReset\n * AHB2RSTR2 OCTOSPI1RST LL_AHB2_GRP2_ForceReset\n * AHB2RSTR2 OCTOSPI2RST LL_AHB2_GRP2_ForceReset\n + * AHB2RSTR2 HSPI1RST LL_AHB2_GRP2_ForceReset\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP2_PERIPH_ALL - * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC + * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB2_GRP2_ForceReset(uint32_t Periphs) @@ -1317,15 +1683,19 @@ __STATIC_INLINE void LL_AHB2_GRP2_ForceReset(uint32_t Periphs) } /** - * @brief Release AHB4 peripherals reset. + * @brief Release AHB2 peripherals reset. * @rmtoll AHB2RSTR2 FSMCRST LL_AHB2_GRP2_ReleaseReset\n * AHB2RSTR2 OCTOSPI1RST LL_AHB2_GRP2_ReleaseReset\n * AHB2RSTR2 OCTOSPI2RST LL_AHB2_GRP2_ReleaseReset\n + * AHB2RSTR2 HSPI1RST LL_AHB2_GRP2_ReleaseReset\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP2_PERIPH_ALL - * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC + * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB2_GRP2_ReleaseReset(uint32_t Periphs) @@ -1334,15 +1704,23 @@ __STATIC_INLINE void LL_AHB2_GRP2_ReleaseReset(uint32_t Periphs) } /** - * @brief Enable AHB4 peripheral clocks in Sleep and Stop modes + * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes * @rmtoll AHB2SMENR2 FSMCSMEN LL_AHB2_GRP2_EnableClockStopSleep\n * AHB2SMENR2 OCTOSPI1SMEN LL_AHB2_GRP2_EnableClockStopSleep\n * AHB2SMENR2 OCTOSPI2SMEN LL_AHB2_GRP2_EnableClockStopSleep\n + * AHB2SMENR2 HSPI1SMEN LL_AHB2_GRP2_EnableClockStopSleep\n + * AHB2SMENR2 SRAM6SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n + * AHB2SMENR2 SRAM5SMEN LL_AHB2_GRP2_EnableClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP2_PERIPH_ALL - * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC + * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB2_GRP2_EnableClockStopSleep(uint32_t Periphs) @@ -1355,15 +1733,23 @@ __STATIC_INLINE void LL_AHB2_GRP2_EnableClockStopSleep(uint32_t Periphs) } /** - * @brief Check if AHB4 peripheral clocks in Sleep and Stop modes is enabled or not + * @brief Check if AHB2 peripheral clocks in Sleep and Stop modes is enabled or not * @rmtoll AHB2SMENR2 FSMCSMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n * AHB2SMENR2 OCTOSPI1SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n * AHB2SMENR2 OCTOSPI2SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n + * AHB2SMENR2 HSPI1SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n + * AHB2SMENR2 SRAM6SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n + * AHB2SMENR2 SRAM5SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP2_PERIPH_ALL - * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC + * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*) + * + * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). */ __STATIC_INLINE uint32_t LL_AHB2_GRP2_IsEnabledClockStopSleep(uint32_t Periphs) @@ -1372,15 +1758,23 @@ __STATIC_INLINE uint32_t LL_AHB2_GRP2_IsEnabledClockStopSleep(uint32_t Periphs) } /** - * @brief Disable AHB4 peripheral clocks in Sleep and Stop modes + * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes * @rmtoll AHB2SMENR2 FSMCSMEN LL_AHB2_GRP2_DisableClockStopSleep\n * AHB2SMENR2 OCTOSPI1SMEN LL_AHB2_GRP2_DisableClockStopSleep\n * AHB2SMENR2 OCTOSPI2SMEN LL_AHB2_GRP2_DisableClockStopSleep\n + * AHB2SMENR2 HSPI1SMEN LL_AHB2_GRP2_DisableClockStopSleep\n + * AHB2SMENR2 SRAM6SMEN LL_AHB2_GRP2_DisableClockStopSleep\n + * AHB2SMENR2 SRAM5SMEN LL_AHB2_GRP2_DisableClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP2_PERIPH_ALL - * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC + * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 + * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*) + * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB2_GRP2_DisableClockStopSleep(uint32_t Periphs) @@ -1396,6 +1790,19 @@ __STATIC_INLINE void LL_AHB2_GRP2_DisableClockStopSleep(uint32_t Periphs) * @{ */ +/** + * @brief Enable APB1 bus clock. + * @rmtoll CFGR2 APB1DIS LL_APB1_GRP1_EnableBusClock + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableBusClock(void) +{ + __IO uint32_t tmpreg; + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); + (void)(tmpreg); +} + /** * @brief Enable APB1 peripherals clock. * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n @@ -1412,7 +1819,8 @@ __STATIC_INLINE void LL_AHB2_GRP2_DisableClockStopSleep(uint32_t Periphs) * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock + * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 USART6N LL_APB1_GRP1_EnableClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 @@ -1423,13 +1831,16 @@ __STATIC_INLINE void LL_AHB2_GRP2_DisableClockStopSleep(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USART3 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) @@ -1444,15 +1855,19 @@ __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) /** * @brief Enable APB1 peripherals clock. * @rmtoll APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n + * APB1ENR2 I2C5EN LL_APB1_GRP2_EnableClock\n + * APB1ENR2 I2C6EN LL_APB1_GRP2_EnableClock\n * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock\n * APB1ENR2 FDCAN1EN LL_APB1_GRP2_EnableClock\n * APB1ENR2 UCPD1EN LL_APB1_GRP2_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 + * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 - * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) * @retval None */ __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) @@ -1481,6 +1896,7 @@ __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 USART6EN LL_APB1_GRP1_IsEnabledClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 @@ -1491,13 +1907,16 @@ __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USART3 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * + * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). */ __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) @@ -1508,15 +1927,19 @@ __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) /** * @brief Check if APB1 peripheral clock is enabled or not * @rmtoll APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n + * APB1ENR2 I2C5EN LL_APB1_GRP2_IsEnabledClock\n + * APB1ENR2 I2C6EN LL_APB1_GRP2_IsEnabledClock\n * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock\n * APB1ENR2 FDCAN1EN LL_APB1_GRP2_IsEnabledClock\n * APB1ENR2 UCPD1EN LL_APB1_GRP2_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 + * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 - * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) * @retval State of Periphs (1 or 0). */ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) @@ -1524,6 +1947,17 @@ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL); } +/** + * @brief Disable APB1 bus clock. + * @note except for IWDG. + * @rmtoll CFGR2 APB1DIS LL_APB1_GRP1_DisableBusClock + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableBusClock(void) +{ + SET_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); +} + /** * @brief Disable APB1 peripherals clock. * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n @@ -1541,6 +1975,7 @@ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n * APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 USART6EN LL_APB1_GRP1_DisableClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 @@ -1551,13 +1986,16 @@ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USART3 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) @@ -1568,15 +2006,19 @@ __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) /** * @brief Disable APB1 peripherals clock. * @rmtoll APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n + * APB1ENR2 I2C5EN LL_APB1_GRP2_DisableClock\n + * APB1ENR2 I2C6EN LL_APB1_GRP2_DisableClock\n * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock\n * APB1ENR2 FDCAN1EN LL_APB1_GRP2_DisableClock\n - * APB1ENR2 UCPD1EN LL_APB1_GRP2_DisableClock + * APB1ENR2 UCPD1EN LL_APB1_GRP2_DisableClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 + * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 - * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) * @retval None */ __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) @@ -1600,6 +2042,7 @@ __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n * APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 USART6RST LL_APB1_GRP1_ForceReset\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 @@ -1609,13 +2052,16 @@ __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USART3 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) @@ -1626,15 +2072,21 @@ __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) /** * @brief Force APB1 peripherals reset. * @rmtoll APB1RSTR2 I2C4RST LL_APB1_GRP2_DisableClock\n + * APB1RSTR2 I2C5RST LL_APB1_GRP2_DisableClock\n + * APB1RSTR2 I2C6RST LL_APB1_GRP2_DisableClock\n * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_DisableClock\n * APB1RSTR2 FDCAN1RST LL_APB1_GRP2_DisableClock\n - * APB1RSTR2 UCPDRST LL_APB1_GRP2_DisableClock + * APB1RSTR2 UCPDRST LL_APB1_GRP2_DisableClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 + * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 - * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) @@ -1657,7 +2109,8 @@ __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset + * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 USART6RST LL_APB1_GRP1_ReleaseReset\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 @@ -1667,13 +2120,16 @@ __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USART3 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) @@ -1684,15 +2140,21 @@ __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) /** * @brief Release APB1 peripherals reset. * @rmtoll APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n + * APB1RSTR2 I2C5RST LL_APB1_GRP2_ReleaseReset\n + * APB1RSTR2 I2C6RST LL_APB1_GRP2_ReleaseReset\n * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset\n * APB1RSTR2 FDCAN1RST LL_APB1_GRP2_ReleaseReset\n - * APB1RSTR2 UCPD1RST LL_APB1_GRP2_ReleaseReset + * APB1RSTR2 UCPD1RST LL_APB1_GRP2_ReleaseReset\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 + * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 - * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) @@ -1715,7 +2177,8 @@ __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) * APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n - * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep + * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 USART6SMEN LL_APB1_GRP1_EnableClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 @@ -1725,13 +2188,16 @@ __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USART3 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs) @@ -1758,7 +2224,8 @@ __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs) * APB1SMENR1 UART5SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n - * APB1SMENR1 CRSSMEN LL_APB1_GRP1_IsEnabledClockStopSleep + * APB1SMENR1 CRSSMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n + * APB1SMENR1 USART6SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 @@ -1768,13 +2235,16 @@ __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USART3 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * + * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). */ __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) @@ -1797,7 +2267,8 @@ __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n - * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep + * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 USART6SMEN LL_APB1_GRP1_DisableClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 @@ -1807,13 +2278,16 @@ __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USART3 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 * @arg @ref LL_APB1_GRP1_PERIPH_CRS + * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs) @@ -1824,15 +2298,21 @@ __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs) /** * @brief Enable APB1 peripheral clocks in Sleep and Stop modes * @rmtoll APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n + * APB1SMENR2 I2C5SMEN LL_APB1_GRP2_EnableClockStopSleep\n + * APB1SMENR2 I2C6SMEN LL_APB1_GRP2_EnableClockStopSleep\n * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep\n * APB1SMENR2 FDCAN1SMEN LL_APB1_GRP2_EnableClockStopSleep\n - * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_EnableClockStopSleep + * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_EnableClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 + * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 - * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs) @@ -1847,15 +2327,21 @@ __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs) /** * @brief Check if APB1 peripheral clocks in Sleep and Stop modes is enabled or not * @rmtoll APB1SMENR2 I2C4SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n + * APB1SMENR2 I2C5SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n + * APB1SMENR2 I2C6SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n * APB1SMENR2 FDCAN1SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_IsEnabledClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 + * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 - * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) + * + * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). */ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClockStopSleep(uint32_t Periphs) @@ -1866,15 +2352,21 @@ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClockStopSleep(uint32_t Periphs) /** * @brief Disable APB1 peripheral clocks in Sleep and Stop modes * @rmtoll APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n + * APB1SMENR2 I2C5SMEN LL_APB1_GRP2_DisableClockStopSleep\n + * APB1SMENR2 I2C6SMEN LL_APB1_GRP2_DisableClockStopSleep\n * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep\n * APB1SMENR2 FDCAN1SMEN LL_APB1_GRP2_DisableClockStopSleep\n * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_DisableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP2_PERIPH_ALL * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 + * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 - * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) @@ -1890,6 +2382,19 @@ __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) * @{ */ +/** + * @brief Enable APB2 bus clock. + * @rmtoll CFGR2 APB2DIS LL_APB2_GRP1_EnableBusClock + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableBusClock(void) +{ + __IO uint32_t tmpreg; + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); + tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); + (void)(tmpreg); +} + /** * @brief Enable APB2 peripherals clock. * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n @@ -1901,6 +2406,9 @@ __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USBEN LL_APB2_GRP1_EnableClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n + * APB2ENR DSIHOSTEN LL_APB2_GRP1_EnableClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_ALL * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 @@ -1911,7 +2419,12 @@ __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) @@ -1934,6 +2447,9 @@ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USBEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR DSIHOSTEN LL_APB2_GRP1_IsEnabledClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_ALL * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 @@ -1944,7 +2460,12 @@ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). */ __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) @@ -1952,6 +2473,16 @@ __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL); } +/** + * @brief Disable APB2 bus clock. + * @rmtoll CFGR2 APB2DIS LL_APB2_GRP1_DisableBusClock + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_DisableBusClock(void) +{ + SET_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); +} + /** * @brief Disable APB2 peripherals clock. * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n @@ -1963,6 +2494,9 @@ __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USBEN LL_APB2_GRP1_DisableClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n + * APB2ENR DSIHOSTEN LL_APB2_GRP1_DisableClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_ALL * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 @@ -1973,7 +2507,12 @@ __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) @@ -1992,6 +2531,9 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USBRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR DSIHOSTRST LL_APB2_GRP1_ForceReset\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_ALL * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 @@ -2002,7 +2544,13 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) @@ -2020,7 +2568,10 @@ __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset + * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USBRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR DSIHOSTRST LL_APB2_GRP1_ReleaseReset\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_ALL * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 @@ -2031,7 +2582,13 @@ __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) @@ -2049,7 +2606,12 @@ __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n - * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep + * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR USBSMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR LTDCSMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR DSIHOSTSMEN LL_APB2_GRP1_EnableClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_ALL * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 @@ -2060,7 +2622,12 @@ __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs) @@ -2083,7 +2650,10 @@ __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs) * APB2SMENR TIM16SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n * APB2SMENR TIM17SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n * APB2SMENR SAI1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n - * APB2SMENR SAI2SMEN LL_APB2_GRP1_IsEnabledClockStopSleep + * APB2SMENR SAI2SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n + * APB2SMENR USBSMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n + * APB2SMENR LTDCSMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n + * APB2SMENR DSIHOSTSMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_ALL * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 @@ -2094,7 +2664,12 @@ __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). */ __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) @@ -2112,7 +2687,10 @@ __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n - * APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep + * APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR USBSMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR LTDCSMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR DSIHOSTSMEN LL_APB2_GRP1_DisableClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_ALL * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 @@ -2123,7 +2701,12 @@ __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs) @@ -2140,6 +2723,19 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs) * @{ */ +/** + * @brief Enable APB3 bus clock. + * @rmtoll CFGR2 APB3DIS LL_APB3_GRP1_EnableBusClock + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_EnableBusClock(void) +{ + __IO uint32_t tmpreg; + CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); + tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); + (void)(tmpreg); +} + /** * @brief Enable APB3 peripherals clock. * @rmtoll APB3ENR SYSCFGEN LL_APB3_GRP1_EnableClock\n @@ -2152,7 +2748,7 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs) * APB3ENR OPAMPEN LL_APB3_GRP1_EnableClock\n * APB3ENR COMPEN LL_APB3_GRP1_EnableClock\n * APB3ENR VREFEN LL_APB3_GRP1_EnableClock\n - * APB3ENR RTCAPBEN LL_APB3_GRP1_EnableClock + * APB3ENR RTCAPBEN LL_APB3_GRP1_EnableClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB3_GRP1_PERIPH_ALL * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG @@ -2189,7 +2785,7 @@ __STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs) * APB3ENR OPAMPEN LL_APB3_GRP1_IsEnabledClock\n * APB3ENR COMPEN LL_APB3_GRP1_IsEnabledClock\n * APB3ENR VREFEN LL_APB3_GRP1_IsEnabledClock\n - * APB3ENR RTCAPBEN LL_APB3_GRP1_IsEnabledClock + * APB3ENR RTCAPBEN LL_APB3_GRP1_IsEnabledClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB3_GRP1_PERIPH_ALL * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG @@ -2210,6 +2806,16 @@ __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs) return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs) ? 1UL : 0UL); } +/** + * @brief Disable APB3 bus clock. + * @rmtoll CFGR2 APB3DIS LL_APB3_GRP1_DisableBusClock + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_DisableBusClock(void) +{ + SET_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); +} + /** * @brief Disable APB2 peripherals clock. * @rmtoll APB3ENR SYSCFGEN LL_APB3_GRP1_DisableClock\n @@ -2222,7 +2828,7 @@ __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs) * APB3ENR OPAMPEN LL_APB3_GRP1_DisableClock\n * APB3ENR COMPEN LL_APB3_GRP1_DisableClock\n * APB3ENR VREFEN LL_APB3_GRP1_DisableClock\n - * APB3ENR RTCAPBEN LL_APB3_GRP1_DisableClock + * APB3ENR RTCAPBEN LL_APB3_GRP1_DisableClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB3_GRP1_PERIPH_ALL * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG @@ -2255,7 +2861,7 @@ __STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs) * APB3RSTR OPAMPRST LL_APB3_GRP1_ForceReset\n * APB3RSTR COMPRST LL_APB3_GRP1_ForceReset\n * APB3RSTR VREFRST LL_APB3_GRP1_ForceReset\n - * APB3RSTR RTCAPBRST LL_APB3_GRP1_ForceReset + * APB3RSTR RTCAPBRST LL_APB3_GRP1_ForceReset\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB3_GRP1_PERIPH_ALL * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG @@ -2288,7 +2894,7 @@ __STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs) * APB3RSTR OPAMPRST LL_APB3_GRP1_ReleaseReset\n * APB3RSTR COMPRST LL_APB3_GRP1_ReleaseReset\n * APB3RSTR VREFRST LL_APB3_GRP1_ReleaseReset\n - * APB3RSTR RTCAPBRST LL_APB3_GRP1_ReleaseReset + * APB3RSTR RTCAPBRST LL_APB3_GRP1_ReleaseReset\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB3_GRP1_PERIPH_ALL * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG @@ -2321,7 +2927,7 @@ __STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs) * APB3SMENR OPAMPSMEN LL_APB3_GRP1_EnableClockStopSleep\n * APB3SMENR COMPSMEN LL_APB3_GRP1_EnableClockStopSleep\n * APB3SMENR VREFSMEN LL_APB3_GRP1_EnableClockStopSleep\n - * APB3SMENR RTCAPBSMEN LL_APB3_GRP1_EnableClockStopSleep + * APB3SMENR RTCAPBSMEN LL_APB3_GRP1_EnableClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB3_GRP1_PERIPH_ALL * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG @@ -2359,7 +2965,7 @@ __STATIC_INLINE void LL_APB3_GRP1_EnableClockStopSleep(uint32_t Periphs) * APB3SMENR OPAMPSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n * APB3SMENR COMPSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n * APB3SMENR VREFSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n - * APB3SMENR RTCAPBSMEN LL_APB3_GRP1_IsEnabledClockStopSleep + * APB3SMENR RTCAPBSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB3_GRP1_PERIPH_ALL * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG @@ -2392,7 +2998,7 @@ __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * APB3SMENR OPAMPSMEN LL_APB3_GRP1_DisableClockStopSleep\n * APB3SMENR COMPSMEN LL_APB3_GRP1_DisableClockStopSleep\n * APB3SMENR VREFSMEN LL_APB3_GRP1_DisableClockStopSleep\n - * APB3SMENR RTCAPBSMEN LL_APB3_GRP1_DisableClockStopSleep + * APB3SMENR RTCAPBSMEN LL_APB3_GRP1_DisableClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB3_GRP1_PERIPH_ALL * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG @@ -2417,48 +3023,48 @@ __STATIC_INLINE void LL_APB3_GRP1_DisableClockStopSleep(uint32_t Periphs) * @} */ -/** @defgroup BUS_LL_EF_S2DAMR S2DAMR +/** @defgroup BUS_LL_EF_SRDAMR SRDAMR * @{ */ /** * @brief Enable SRDAMR peripheral clocks in autonomous mode - * @rmtoll S2DAMR SPI3AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * S2DAMR LPUART1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * S2DAMR I2C3AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * S2DAMR LPTIM1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * S2DAMR LPTIM3AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * S2DAMR LPTIM4AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * S2DAMR OPAMPAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * S2DAMR COMPAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * S2DAMR VREFAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * S2DAMR VREFRST LL_SRDAMR_GRP1_EnableAutonomousClock\n - * S2DAMR RTCAPBAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * S2DAMR ADC4AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * S2DAMR LPGPIO1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * S2DAMR DAC1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * S2DAMR LPDMA1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * S2DAMR ADF1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * S2DAMR SRAM4AMEN LL_SRDAMR_GRP1_EnableAutonomousClock + * @rmtoll SRDAMR SPI3AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR LPUART1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR I2C3AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR LPTIM1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR LPTIM3AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR LPTIM4AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR OPAMPAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR COMPAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR VREFAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR VREFRST LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR RTCAPBAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR ADC4AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR LPGPIO1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR DAC1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR LPDMA1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR ADF1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n + * SRDAMR SRAM4AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_SRDAMR_GRP1_PERIPH_ALL - * @arg @ref LL_SRDAMR_GRP1_PERIPH_SPI3AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPUART1AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_I2C3AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM1AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM3AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM4AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_OPAMPAMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_COMPAMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_VREFAMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_RTCAPBAMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADC4AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPGPIO1AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_DAC1AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPDMA1AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADF1AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_SRAM4AMEN - * @retval None + * @arg @ref LL_SRDAMR_GRP1_PERIPH_SPI3 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPUART1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_I2C3 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_OPAMP + * @arg @ref LL_SRDAMR_GRP1_PERIPH_COMP + * @arg @ref LL_SRDAMR_GRP1_PERIPH_VREF + * @arg @ref LL_SRDAMR_GRP1_PERIPH_RTCAPB + * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADC4 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPGPIO1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_DAC1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPDMA1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADF1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_SRAM4 + * @retval None */ __STATIC_INLINE void LL_SRDAMR_GRP1_EnableAutonomousClock(uint32_t Periphs) { @@ -2470,42 +3076,42 @@ __STATIC_INLINE void LL_SRDAMR_GRP1_EnableAutonomousClock(uint32_t Periphs) } /** - * @brief Check if S2DAMR peripheral clock is enabled or not - * @rmtoll S2DAMR SPI3AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * S2DAMR LPUART1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * S2DAMR I2C3AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * S2DAMR LPTIM1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * S2DAMR LPTIM3AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * S2DAMR LPTIM4AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * S2DAMR OPAMPAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * S2DAMR COMPAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * S2DAMR VREFAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * S2DAMR VREFRST LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * S2DAMR RTCAPBAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * S2DAMR ADC4AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * S2DAMR LPGPIO1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * S2DAMR DAC1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * S2DAMR LPDMA1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * S2DAMR ADF1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * S2DAMR SRAM4AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock + * @brief Check if SRDAMR peripheral clock is enabled or not + * @rmtoll SRDAMR SPI3AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR LPUART1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR I2C3AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR LPTIM1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR LPTIM3AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR LPTIM4AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR OPAMPAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR COMPAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR VREFAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR VREFRST LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR RTCAPBAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR ADC4AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR LPGPIO1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR DAC1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR LPDMA1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR ADF1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n + * SRDAMR SRAM4AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_SRDAMR_GRP1_PERIPH_ALL - * @arg @ref LL_SRDAMR_GRP1_PERIPH_SPI3AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPUART1AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_I2C3AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM1AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM3AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM4AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_OPAMPAMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_COMPAMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_VREFAMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_RTCAPBAMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADC4AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPGPIO1AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_DAC1AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPDMA1AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADF1AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_SRAM4AMEN + * @arg @ref LL_SRDAMR_GRP1_PERIPH_SPI3 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPUART1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_I2C3 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_OPAMP + * @arg @ref LL_SRDAMR_GRP1_PERIPH_COMP + * @arg @ref LL_SRDAMR_GRP1_PERIPH_VREF + * @arg @ref LL_SRDAMR_GRP1_PERIPH_RTCAPB + * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADC4 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPGPIO1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_DAC1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPDMA1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADF1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_SRAM4 * @retval State of Periphs (1 or 0). */ __STATIC_INLINE uint32_t LL_SRDAMR_GRP1_IsEnabledAutonomousClock(uint32_t Periphs) @@ -2514,42 +3120,42 @@ __STATIC_INLINE uint32_t LL_SRDAMR_GRP1_IsEnabledAutonomousClock(uint32_t Periph } /** - * @brief Disable S2DAMR peripheral clocks in Sleep and Stop modes - * @rmtoll S2DAMR SPI3AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * S2DAMR LPUART1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * S2DAMR I2C3AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * S2DAMR LPTIM1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * S2DAMR LPTIM3AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * S2DAMR LPTIM4AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * S2DAMR OPAMPAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * S2DAMR COMPAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * S2DAMR VREFAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * S2DAMR VREFRST LL_SRDAMR_GRP1_DisableAutonomousClock\n - * S2DAMR RTCAPBAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * S2DAMR ADC4AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * S2DAMR LPGPIO1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * S2DAMR DAC1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * S2DAMR LPDMA1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * S2DAMR ADF1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * S2DAMR SRAM4AMEN LL_SRDAMR_GRP1_DisableAutonomousClock + * @brief Disable SRDAMR peripheral clocks in Sleep and Stop modes + * @rmtoll SRDAMR SPI3AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR LPUART1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR I2C3AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR LPTIM1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR LPTIM3AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR LPTIM4AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR OPAMPAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR COMPAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR VREFAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR VREFRST LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR RTCAPBAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR ADC4AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR LPGPIO1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR DAC1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR LPDMA1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR ADF1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n + * SRDAMR SRAM4AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_SRDAMR_GRP1_PERIPH_ALL - * @arg @ref LL_SRDAMR_GRP1_PERIPH_SPI3AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPUART1AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_I2C3AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM1AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM3AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM4AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_OPAMPAMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_COMPAMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_VREFAMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_RTCAPBAMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADC4AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPGPIO1AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_DAC1AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPDMA1AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADF1AMEN - * @arg @ref LL_SRDAMR_GRP1_PERIPH_SRAM4AMEN + * @arg @ref LL_SRDAMR_GRP1_PERIPH_SPI3 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPUART1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_I2C3 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_OPAMP + * @arg @ref LL_SRDAMR_GRP1_PERIPH_COMP + * @arg @ref LL_SRDAMR_GRP1_PERIPH_VREF + * @arg @ref LL_SRDAMR_GRP1_PERIPH_RTCAPB + * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADC4 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPGPIO1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_DAC1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPDMA1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADF1 + * @arg @ref LL_SRDAMR_GRP1_PERIPH_SRAM4 * @retval None */ __STATIC_INLINE void LL_SRDAMR_GRP1_DisableAutonomousClock(uint32_t Periphs) diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_comp.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_comp.c index 8bb9c244716..9cea9be38bd 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_comp.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_comp.c @@ -55,20 +55,31 @@ || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER) \ ) -/* Note: On this STM32 series, comparator input plus parameters are */ +/* Note: On this STM32 series, comparator input plus parameters are */ /* the same on all COMP instances. */ /* However, comparator instance kept as macro parameter for */ -/* compatibility with other STM32 families. */ +/* compatibility with other STM32 series. */ +#if defined(COMP_CSR_INPSEL_2) #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \ (((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO3) \ + || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO4) \ + || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO5) \ + || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO6) \ ) +#else +#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \ + (((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \ + || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \ + || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO3) \ + ) +#endif /* COMP_CSR_INPSEL_2 */ -/* Note: On this STM32 series, comparator input minus parameters are */ +/* Note: On this STM32 series, comparator input minus parameters are */ /* the same on all COMP instances. */ /* However, comparator instance kept as macro parameter for */ -/* compatibility with other STM32 families. */ +/* compatibility with other STM32 series. */ #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \ @@ -101,7 +112,6 @@ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5) \ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1) \ ) - /** * @} */ @@ -166,7 +176,7 @@ ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx) * - SUCCESS: COMP registers are initialized * - ERROR: COMP registers are not initialized */ -ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct) +ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, const LL_COMP_InitTypeDef *COMP_InitStruct) { ErrorStatus status = SUCCESS; @@ -252,4 +262,3 @@ void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct) */ #endif /* USE_FULL_LL_DRIVER */ - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_comp.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_comp.h index b5b200e7612..ccca448950a 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_comp.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_comp.h @@ -54,7 +54,7 @@ extern "C" { defined as reference register */ #define LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK (0x00000001UL) /* Register of COMP instance even (COMP2_CSR, ...) offset vs register of COMP instance odd */ -#define LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK (LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK\ +#define LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK (LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK \ | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK) #define LL_COMP_WINDOWMODE_COMPX_SETTING_MASK (COMP_CSR_WINMODE) #define LL_COMP_WINDOWOUTPUT_COMPX_SETTING_MASK (COMP_CSR_WINOUT) @@ -102,33 +102,33 @@ typedef struct { uint32_t PowerMode; /*!< Set comparator operating mode to adjust power and speed. This parameter can be a value of @ref COMP_LL_EC_POWERMODE - This feature can be modified afterwards using - unitary function @ref LL_COMP_SetPowerMode(). */ + This feature can be modified afterwards using unitary + function @ref LL_COMP_SetPowerMode(). */ uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input). This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS - This feature can be modified afterwards using - unitary function @ref LL_COMP_SetInputPlus(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetInputPlus(). */ uint32_t InputMinus; /*!< Set comparator input minus (inverting input). This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS - This feature can be modified afterwards using - unitary function @ref LL_COMP_SetInputMinus(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetInputMinus(). */ uint32_t InputHysteresis; /*!< Set comparator hysteresis mode of the input minus. This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS - This feature can be modified afterwards using - unitary function @ref LL_COMP_SetInputHysteresis(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetInputHysteresis(). */ uint32_t OutputPolarity; /*!< Set comparator output polarity. This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY - This feature can be modified afterwards using - unitary function @ref LL_COMP_SetOutputPolarity(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetOutputPolarity(). */ uint32_t OutputBlankingSource; /*!< Set comparator blanking source. This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE - This feature can be modified afterwards using - unitary function @ref LL_COMP_SetOutputBlankingSource(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetOutputBlankingSource(). */ } LL_COMP_InitTypeDef; @@ -142,12 +142,13 @@ typedef struct * @{ */ +#if defined(COMP_WINDOW_MODE_SUPPORT) /** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode * @{ */ #define LL_COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators 1 and 2 are independent */ #define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */ -#define LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK) /*!< Window mode enable: if used from COMP1 or COMP2 instance, comparators instances pair COMP1 and COMP2 have their input plus connected together, the common input is COMP2 input plus (COMP1 input plus is no more accessible) */ +#define LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK) /*!< Window mode enable: if used from COMP1 or COMP2 instance, comparators instances pair COMP1 and COMP2 have their input plus connected together, the common input is COMP2 input plus (COMP1 input plus is no more accessible). */ /** * @} */ @@ -156,19 +157,20 @@ typedef struct * @{ */ #define LL_COMP_WINDOWOUTPUT_EACH_COMP (0x00000000UL) /*!< Window output default mode: Comparators output are indicating each their own state. To know window mode state: each comparator output must be read, if "((COMPx exclusive or COMPy) == 1)" then monitored signal is within comparators window. The same way, if both comparators output are high, then monitored signal is below window. */ -#define LL_COMP_WINDOWOUTPUT_COMP1 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK) /*!< Window output synthetized on COMP1 output: COMP1 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */ -#define LL_COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK) /*!< Window output synthetized on COMP2 output: COMP2 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */ -#define LL_COMP_WINDOWOUTPUT_BOTH (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK | LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK) /*!< Window output synthetized on both comparators output of pair of comparator selected (COMP1 and COMP2): both comparators outputs are no more indicating their own state, but global window mode state (logical high means monitored signal is within comparators window). This is a specific configuration (technically possible but not relevant from application point of view: 2 comparators output used for the same signal level), standard configuration for window mode is one of the settings above. */ +#define LL_COMP_WINDOWOUTPUT_COMP1 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK) /*!< Window output synthesized on COMP1 output: COMP1 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). Note: impacts only comparator output signal level (COMPx_OUT propagated to GPIO, EXTI lines, timers, ...), does not impact output digital state of comparator (COMPx_VALUE) always reflecting each comparator output state.*/ +#define LL_COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK) /*!< Window output synthesized on COMP2 output: COMP2 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). Note: impacts only comparator output signal level (COMPx_OUT propagated to GPIO, EXTI lines, timers, ...), does not impact output digital state of comparator (COMPx_VALUE) always reflecting each comparator output state.*/ +#define LL_COMP_WINDOWOUTPUT_BOTH (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK | LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK) /*!< Window output synthesized on both comparators output of pair of comparator selected (COMP1 and COMP2): both comparators outputs are no more indicating their own state, but global window mode state (logical high means monitored signal is within comparators window). This is a specific configuration (technically possible but not relevant from application point of view: 2 comparators output used for the same signal level), standard configuration for window mode is one of the settings above. */ /** * @} */ +#endif /* COMP_WINDOW_MODE_SUPPORT */ /** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode * @{ */ -#define LL_COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< COMP power mode to high speed */ -#define LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< COMP power mode to medium speed */ -#define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0) /*!< COMP power mode to ultra-low power */ +#define LL_COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< COMP power mode to high speed */ +#define LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< COMP power mode to medium speed */ +#define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0) /*!< COMP power mode to ultra-low power */ /** * @} */ @@ -179,6 +181,11 @@ typedef struct #define LL_COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */ #define LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */ #define LL_COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA2 for COMP1) */ +#if defined(COMP_CSR_INPSEL_2) +#define LL_COMP_INPUT_PLUS_IO4 (COMP_CSR_INPSEL_1 | COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO4 (pin PB3 for COMP1) */ +#define LL_COMP_INPUT_PLUS_IO5 (COMP_CSR_INPSEL_2) /*!< Comparator input plus connected to IO5 (pin PB4 for COMP1) */ +#define LL_COMP_INPUT_PLUS_IO6 (COMP_CSR_INPSEL_2 | COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO6 (pin PB6 for COMP1) */ +#endif /* COMP_CSR_INPSEL_2 */ /** * @} */ @@ -186,14 +193,14 @@ typedef struct /** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection * @{ */ -#define LL_COMP_INPUT_MINUS_1_4VREFINT (0x00000000UL ) /*!< Comparator input minus connected to 1/4 VrefInt */ -#define LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt */ -#define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to 3/4 VrefInt */ -#define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to VrefInt */ -#define LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */ -#define LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */ -#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */ -#define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2) */ +#define LL_COMP_INPUT_MINUS_1_4VREFINT (0x00000000UL) /*!< Comparator input minus connected to 1/4 VrefInt */ +#define LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt */ +#define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to 3/4 VrefInt */ +#define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to VrefInt */ +#define LL_COMP_INPUT_MINUS_DAC1_CH1 ( COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */ +#define LL_COMP_INPUT_MINUS_DAC1_CH2 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */ +#define LL_COMP_INPUT_MINUS_IO1 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */ +#define LL_COMP_INPUT_MINUS_IO2 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2) */ /** * @} */ @@ -221,13 +228,13 @@ typedef struct /** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source * @{ */ -#define LL_COMP_BLANKINGSRC_NONE ( 0x00000000UL) /*!CSR_ODD, @@ -373,12 +381,12 @@ __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COM * (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() ) * @retval Returned value can be one of the following values: * @arg @ref LL_COMP_WINDOWMODE_DISABLE - * @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (1) + * @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON * @arg @ref LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (1) * - * (1) Parameter available on all STM32U5 devices, must be used with comparator common instance COMP12_COMMON + * (1) Parameter not available on all STM32U5 devices */ -__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON) +__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(const COMP_Common_TypeDef *COMPxy_COMMON) { /* Note: On this STM32 series, window mode can be set from any instance */ /* of the pair of comparator instances. */ @@ -444,7 +452,7 @@ __STATIC_INLINE void LL_COMP_SetCommonWindowOutput(COMP_Common_TypeDef *COMPxy_C * * (1) Parameter available on all STM32U5 devices, must be used with comparator common instance COMP12_COMMON */ -__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowOutput(COMP_Common_TypeDef *COMPxy_COMMON) +__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowOutput(const COMP_Common_TypeDef *COMPxy_COMMON) { const uint32_t window_output_comp_odd = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINOUT); const uint32_t window_output_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINOUT); @@ -455,11 +463,11 @@ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowOutput(COMP_Common_TypeDef *COMP | ((window_output_comp_even >> COMP_CSR_WINOUT_Pos) * LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK) | (window_output_comp_odd + window_output_comp_even)); } - /** * @} */ +#endif /* COMP2 */ /** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes * @{ */ @@ -488,7 +496,7 @@ __STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMod * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER */ -__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_PWRMODE)); } @@ -531,7 +539,9 @@ __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx) */ __STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus) { - MODIFY_REG(COMPx->CSR, COMP_CSR_INMSEL | COMP_CSR_INPSEL, InputMinus | InputPlus); + MODIFY_REG(COMPx->CSR, + COMP_CSR_INMSEL | COMP_CSR_INPSEL, + InputMinus | InputPlus); } /** @@ -564,7 +574,7 @@ __STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlu * @arg @ref LL_COMP_INPUT_PLUS_IO2 * @arg @ref LL_COMP_INPUT_PLUS_IO3 */ -__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INPSEL)); } @@ -614,7 +624,7 @@ __STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMi * @arg @ref LL_COMP_INPUT_MINUS_IO1 * @arg @ref LL_COMP_INPUT_MINUS_IO2 */ -__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INMSEL)); } @@ -645,7 +655,7 @@ __STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t In * @arg @ref LL_COMP_HYSTERESIS_MEDIUM * @arg @ref LL_COMP_HYSTERESIS_HIGH */ -__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_HYST)); } @@ -680,7 +690,7 @@ __STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t Out * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED * @arg @ref LL_COMP_OUTPUTPOL_INVERTED */ -__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_POLARITY)); } @@ -691,7 +701,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx) * Refer to description of parameters or to reference manual. * @note Availability of parameters of blanking source from timer * depends on timers availability on the selected device. - * @rmtoll CSR BLANKSEL LL_COMP_SetOutputBlankingSource + * @rmtoll CSR BLANKSEL LL_COMP_SetOutputBlankingSource * @param COMPx Comparator instance * @param BlankingSource This parameter can be one of the following values: * @arg @ref LL_COMP_BLANKINGSRC_NONE @@ -714,7 +724,7 @@ __STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32 * depends on timers availability on the selected device. * @note Blanking source may be specific to each comparator instance. * Refer to description of parameters or to reference manual. - * @rmtoll CSR BLANKSEL LL_COMP_GetOutputBlankingSource + * @rmtoll CSR BLANKSEL LL_COMP_GetOutputBlankingSource * @param COMPx Comparator instance * @retval Returned value can be one of the following values: * @arg @ref LL_COMP_BLANKINGSRC_NONE @@ -725,7 +735,7 @@ __STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32 * @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5 * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1 */ -__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_BLANKSEL)); } @@ -770,7 +780,7 @@ __STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsEnabled(const COMP_TypeDef *COMPx) { return ((READ_BIT(COMPx->CSR, COMP_CSR_EN) == (COMP_CSR_EN)) ? 1UL : 0UL); } @@ -797,7 +807,7 @@ __STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsLocked(const COMP_TypeDef *COMPx) { return ((READ_BIT(COMPx->CSR, COMP_CSR_LOCK) == (COMP_CSR_LOCK)) ? 1UL : 0UL); } @@ -822,7 +832,7 @@ __STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_OUTPUT_LEVEL_LOW * @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH */ -__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_VALUE) >> LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS); @@ -838,7 +848,7 @@ __STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx) */ ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx); -ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct); +ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, const LL_COMP_InitTypeDef *COMP_InitStruct); void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct); /** @@ -869,4 +879,3 @@ void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct); #endif #endif /* STM32U5xx_LL_COMP_H */ - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_cordic.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_cordic.c index 2aac578ca7d..e8da94cf983 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_cordic.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_cordic.c @@ -58,7 +58,7 @@ * - SUCCESS: CORDIC registers are de-initialized * - ERROR: CORDIC registers are not de-initialized */ -ErrorStatus LL_CORDIC_DeInit(CORDIC_TypeDef *CORDICx) +ErrorStatus LL_CORDIC_DeInit(const CORDIC_TypeDef *CORDICx) { ErrorStatus status = SUCCESS; diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_cordic.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_cordic.h index 4f6037abd8d..3920592b68f 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_cordic.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_cordic.h @@ -241,13 +241,13 @@ extern "C" { * - @ref LL_CORDIC_SetNbRead() * - @ref LL_CORDIC_SetInSize() * - @ref LL_CORDIC_SetOutSize() - * @rmtoll CSR FUNC LL_CORDIC_Configure\n - * CSR PRECISION LL_CORDIC_Configure\n - * CSR SCALE LL_CORDIC_Configure\n - * CSR NARGS LL_CORDIC_Configure\n - * CSR NRES LL_CORDIC_Configure\n - * CSR ARGSIZE LL_CORDIC_Configure\n - * CSR RESIZE LL_CORDIC_Configure + * @rmtoll CSR FUNC LL_CORDIC_Config\n + * CSR PRECISION LL_CORDIC_Config\n + * CSR SCALE LL_CORDIC_Config\n + * CSR NARGS LL_CORDIC_Config\n + * CSR NRES LL_CORDIC_Config\n + * CSR ARGSIZE LL_CORDIC_Config\n + * CSR RESIZE LL_CORDIC_Config * @param CORDICx CORDIC instance * @param Function parameter can be one of the following values: * @arg @ref LL_CORDIC_FUNCTION_COSINE @@ -347,7 +347,7 @@ __STATIC_INLINE void LL_CORDIC_SetFunction(CORDIC_TypeDef *CORDICx, uint32_t Fun * @arg @ref LL_CORDIC_FUNCTION_NATURALLOG * @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT */ -__STATIC_INLINE uint32_t LL_CORDIC_GetFunction(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_GetFunction(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_FUNC)); } @@ -400,7 +400,7 @@ __STATIC_INLINE void LL_CORDIC_SetPrecision(CORDIC_TypeDef *CORDICx, uint32_t Pr * @arg @ref LL_CORDIC_PRECISION_14CYCLES * @arg @ref LL_CORDIC_PRECISION_15CYCLES */ -__STATIC_INLINE uint32_t LL_CORDIC_GetPrecision(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_GetPrecision(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_PRECISION)); } @@ -439,7 +439,7 @@ __STATIC_INLINE void LL_CORDIC_SetScale(CORDIC_TypeDef *CORDICx, uint32_t Scale) * @arg @ref LL_CORDIC_SCALE_6 * @arg @ref LL_CORDIC_SCALE_7 */ -__STATIC_INLINE uint32_t LL_CORDIC_GetScale(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_GetScale(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_SCALE)); } @@ -466,7 +466,7 @@ __STATIC_INLINE void LL_CORDIC_SetNbWrite(CORDIC_TypeDef *CORDICx, uint32_t NbWr * @arg @ref LL_CORDIC_NBWRITE_1 * @arg @ref LL_CORDIC_NBWRITE_2 */ -__STATIC_INLINE uint32_t LL_CORDIC_GetNbWrite(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_GetNbWrite(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_NARGS)); } @@ -493,7 +493,7 @@ __STATIC_INLINE void LL_CORDIC_SetNbRead(CORDIC_TypeDef *CORDICx, uint32_t NbRea * @arg @ref LL_CORDIC_NBREAD_1 * @arg @ref LL_CORDIC_NBREAD_2 */ -__STATIC_INLINE uint32_t LL_CORDIC_GetNbRead(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_GetNbRead(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_NRES)); } @@ -520,7 +520,7 @@ __STATIC_INLINE void LL_CORDIC_SetInSize(CORDIC_TypeDef *CORDICx, uint32_t InSiz * @arg @ref LL_CORDIC_INSIZE_32BITS * @arg @ref LL_CORDIC_INSIZE_16BITS */ -__STATIC_INLINE uint32_t LL_CORDIC_GetInSize(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_GetInSize(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_ARGSIZE)); } @@ -547,7 +547,7 @@ __STATIC_INLINE void LL_CORDIC_SetOutSize(CORDIC_TypeDef *CORDICx, uint32_t OutS * @arg @ref LL_CORDIC_OUTSIZE_32BITS * @arg @ref LL_CORDIC_OUTSIZE_16BITS */ -__STATIC_INLINE uint32_t LL_CORDIC_GetOutSize(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_GetOutSize(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_RESSIZE)); } @@ -588,7 +588,7 @@ __STATIC_INLINE void LL_CORDIC_DisableIT(CORDIC_TypeDef *CORDICx) * @param CORDICx CORDIC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledIT(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledIT(const CORDIC_TypeDef *CORDICx) { return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_IEN) == (CORDIC_CSR_IEN)) ? 1U : 0U); } @@ -629,7 +629,7 @@ __STATIC_INLINE void LL_CORDIC_DisableDMAReq_RD(CORDIC_TypeDef *CORDICx) * @param CORDICx CORDIC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_RD(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_RD(const CORDIC_TypeDef *CORDICx) { return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAREN) == (CORDIC_CSR_DMAREN)) ? 1U : 0U); } @@ -662,7 +662,7 @@ __STATIC_INLINE void LL_CORDIC_DisableDMAReq_WR(CORDIC_TypeDef *CORDICx) * @param CORDICx CORDIC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_WR(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_WR(const CORDIC_TypeDef *CORDICx) { return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN) == (CORDIC_CSR_DMAWEN)) ? 1U : 0U); } @@ -677,7 +677,7 @@ __STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_WR(CORDIC_TypeDef *CORDICx) * @arg @ref LL_CORDIC_DMA_REG_DATA_OUT * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_CORDIC_DMA_GetRegAddr(CORDIC_TypeDef *CORDICx, uint32_t Direction) +__STATIC_INLINE uint32_t LL_CORDIC_DMA_GetRegAddr(const CORDIC_TypeDef *CORDICx, uint32_t Direction) { uint32_t data_reg_addr; @@ -709,7 +709,7 @@ __STATIC_INLINE uint32_t LL_CORDIC_DMA_GetRegAddr(CORDIC_TypeDef *CORDICx, uint3 * @param CORDICx CORDIC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_CORDIC_IsActiveFlag_RRDY(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_IsActiveFlag_RRDY(const CORDIC_TypeDef *CORDICx) { return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_RRDY) == (CORDIC_CSR_RRDY)) ? 1U : 0U); } @@ -740,7 +740,7 @@ __STATIC_INLINE void LL_CORDIC_WriteData(CORDIC_TypeDef *CORDICx, uint32_t InDat * @param CORDICx CORDIC Instance * @retval 32-bit output data of CORDIC processing. */ -__STATIC_INLINE uint32_t LL_CORDIC_ReadData(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_ReadData(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_REG(CORDICx->RDATA)); } @@ -755,7 +755,7 @@ __STATIC_INLINE uint32_t LL_CORDIC_ReadData(CORDIC_TypeDef *CORDICx) /** @defgroup CORDIC_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_CORDIC_DeInit(CORDIC_TypeDef *CORDICx); +ErrorStatus LL_CORDIC_DeInit(const CORDIC_TypeDef *CORDICx); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_cortex.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_cortex.h index 517979480cb..e936e62a624 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_cortex.h @@ -55,6 +55,15 @@ extern "C" { /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ +/** @defgroup CORTEX_LL_EC_REGION_ACCESS CORTEX LL MPU Region Access Attributes + * @{ + */ +/* Register MPU_RBAR (Cortex-M33) : bits [4:0] */ +#define MPU_ACCESS_MSK (MPU_RBAR_SH_Msk|MPU_RBAR_AP_Msk|MPU_RBAR_XN_Msk) +/** + * @} + */ + /* Private macros ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ @@ -98,9 +107,9 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Attributes CORTEX LL MPU Attributes * @{ */ -#define LL_MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ -#define LL_MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ -#define LL_MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ +#define LL_MPU_DEVICE_NGNRNE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ +#define LL_MPU_DEVICE_NGNRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ +#define LL_MPU_DEVICE_NGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ #define LL_MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ #define LL_MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ @@ -433,11 +442,11 @@ __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) } /** - * @brief Get Constant number - * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant - * @retval Value should be equal to 0xF for Cortex-M33 devices + * @brief Get Architecture version + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture + * @retval Value should be equal to 0xF for Cortex-M33 ("ARMv8-M with Main Extension") */ -__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) +__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) { return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); } @@ -525,7 +534,7 @@ __STATIC_INLINE void LL_MPU_Disable(void) { /* Make sure outstanding transfers are done */ __DMB(); - /* Disable MPU*/ + /* Disable MPU */ WRITE_REG(MPU->CTRL, 0U); } @@ -593,7 +602,7 @@ __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) /** * @brief Check if MPU region is enabled or not - * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabledRegion + * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabled_Region * @param Region This parameter can be one of the following values: * @arg @ref LL_MPU_REGION_NUMBER0 * @arg @ref LL_MPU_REGION_NUMBER1 @@ -608,7 +617,11 @@ __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) */ __STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region(uint32_t Region) { - return ((READ_BIT(MPU->RNR, Region) == (Region)) ? 1UL : 0UL); + /* Set region index */ + WRITE_REG(MPU->RNR, Region); + + /* Return MPU region status */ + return ((READ_BIT(MPU->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL); } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -638,7 +651,7 @@ __STATIC_INLINE void LL_MPU_EnableRegion_NS(uint32_t Region) /** * @brief Check if non-secure MPU region is enabled or not - * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnableRegion_NS + * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabled_Region_NS * @param Region This parameter can be one of the following values: * @arg @ref LL_MPU_REGION_NUMBER0 * @arg @ref LL_MPU_REGION_NUMBER1 @@ -653,7 +666,11 @@ __STATIC_INLINE void LL_MPU_EnableRegion_NS(uint32_t Region) */ __STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region_NS(uint32_t Region) { - return ((READ_BIT(MPU_NS->RNR, Region) == (Region)) ? 1UL : 0UL); + /* Set region index */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Return non-secure MPU region status */ + return ((READ_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL); } #endif /* __ARM_FEATURE_CMSE */ @@ -751,18 +768,17 @@ __STATIC_INLINE void LL_MPU_DisableRegion_NS(uint32_t Region) __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress, uint32_t LimitAddress) { - /* Set Region number */ + /* Set region index */ WRITE_REG(MPU->RNR, Region); /* Set base address */ MPU->RBAR |= Attributes; - /* Set base address */ - MPU->RBAR |= (BaseAddress & 0xFFFFFFE0U); - /* Set limit address */ - MPU->RLAR |= (LimitAddress & 0xFFFFFFE0U); - /* Configure MPU */ - MPU->RLAR |= (MPU_RLAR_EN_Msk | AttrIndx); + /* Set region base address and region access attributes */ + WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes)); + + /* Set region limit address, memory attributes index and enable region */ + WRITE_REG(MPU->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk)); } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -811,16 +827,11 @@ __STATIC_INLINE void LL_MPU_ConfigRegion_NS(uint32_t Region, uint32_t Attributes /* Set Region number */ WRITE_REG(MPU_NS->RNR, Region); - /* Set base address */ - MPU_NS->RBAR |= Attributes; - - /* Set base address */ - MPU_NS->RBAR |= (BaseAddress & 0xFFFFFFE0U); + /* Set region base address and region access attributes */ + WRITE_REG(MPU_NS->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes)); - /* Set limit address */ - MPU_NS->RLAR |= (LimitAddress & 0xFFFFFFE0U); - /* Configure MPU */ - MPU_NS->RLAR |= (MPU_RLAR_EN_Msk | AttrIndx); + /* Set region limit address, memory attributes index and enable region */ + WRITE_REG(MPU_NS->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk)); } #endif /* __ARM_FEATURE_CMSE */ @@ -847,11 +858,12 @@ __STATIC_INLINE void LL_MPU_ConfigRegionAddress(uint32_t Region, uint32_t BaseAd { /* Set Region number */ WRITE_REG(MPU->RNR, Region); - /* Set base address */ - MPU->RBAR |= (BaseAddress & 0xFFFFFFE0U) ; - /* Set limit address */ - MPU->RLAR |= (LimitAddress & 0xFFFFFFE0U); + /* Modify region base address */ + MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); + + /* Modify region limit address */ + MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) @@ -878,11 +890,12 @@ __STATIC_INLINE void LL_MPU_ConfigRegionAddress_NS(uint32_t Region, uint32_t Bas { /* Set Region number */ WRITE_REG(MPU_NS->RNR, Region); + /* Set base address */ - MPU_NS->RBAR |= (BaseAddress & 0xFFFFFFE0U); + MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); /* Set limit address */ - MPU_NS->RLAR |= (LimitAddress & 0xFFFFFFE0U); + MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); } #endif /* __ARM_FEATURE_CMSE */ @@ -904,15 +917,17 @@ __STATIC_INLINE void LL_MPU_ConfigRegionAddress_NS(uint32_t Region, uint32_t Bas */ __STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attributes) { + /* When selected index is in range [0;3] */ if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4) { - /* Program MPU_MAIR0 */ - WRITE_REG(MPU->MAIR0, (Attributes << (AttIndex * 8U))); + /* Modify Attr field of MPU_MAIR0 accordingly */ + MODIFY_REG(MPU->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); } + /* When selected index is in range [4;7] */ else { - /* Program MPU_MAIR1 */ - WRITE_REG(MPU->MAIR1, (Attributes << ((AttIndex - 4U) * 8U))); + /* Modify Attr field of MPU_MAIR1 accordingly */ + MODIFY_REG(MPU->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); } } @@ -935,15 +950,17 @@ __STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attrib */ __STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Attributes) { + /* When selected index is in range [0;3] */ if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4) { - /* Program MPU_MAIR0 */ - WRITE_REG(MPU_NS->MAIR0, (Attributes << (AttIndex * 8U))); + /* Modify Attr field of MPU_MAIR0_NS accordingly */ + MODIFY_REG(MPU_NS->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); } + /* When selected index is in range [4;7] */ else { - /* Program MPU_MAIR1 */ - WRITE_REG(MPU_NS->MAIR1, (Attributes << ((AttIndex - 4U) * 8U))); + /* Modify Attr field of MPU_MAIR1_NS accordingly */ + MODIFY_REG(MPU_NS->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); } } #endif /* __ARM_FEATURE_CMSE */ @@ -969,8 +986,9 @@ __STATIC_INLINE void LL_MPU_SetRegionLimitAddress(uint32_t Region, uint32_t Limi { /* Set Region number */ WRITE_REG(MPU->RNR, Region); + /* Set limit address */ - MPU->RLAR |= (LimitAddress & 0xFFFFFFE0U); + MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); } /** @@ -991,6 +1009,7 @@ __STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress(uint32_t Region) { /* Set Region number */ WRITE_REG(MPU->RNR, Region); + return (READ_REG(MPU->RLAR & MPU_RLAR_LIMIT_Msk)); } @@ -1015,8 +1034,9 @@ __STATIC_INLINE void LL_MPU_SetRegionBaseAddress(uint32_t Region, uint32_t BaseA { /* Set Region number */ WRITE_REG(MPU->RNR, Region); + /* Set base address */ - MPU->RBAR |= (BaseAddress & 0xFFFFFFE0U); + MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); } /** @@ -1037,6 +1057,7 @@ __STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress(uint32_t Region) { /* Set Region number */ WRITE_REG(MPU->RNR, Region); + return (READ_REG(MPU->RBAR & MPU_RBAR_BASE_Msk)); } @@ -1068,8 +1089,9 @@ __STATIC_INLINE void LL_MPU_SetRegionAccess(uint32_t Region, uint32_t Attributes { /* Set Region number */ WRITE_REG(MPU->RNR, Region); + /* Set base address */ - MPU->RBAR |= Attributes; + MODIFY_REG(MPU->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK)); } /** @@ -1093,6 +1115,7 @@ __STATIC_INLINE uint32_t LL_MPU_GetRegionAccess(uint32_t Region) { /* Set Region number */ WRITE_REG(MPU->RNR, Region); + return (READ_REG(MPU->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk))); } @@ -1118,8 +1141,9 @@ __STATIC_INLINE void LL_MPU_SetRegionLimitAddress_NS(uint32_t Region, uint32_t L { /* Set Region number */ WRITE_REG(MPU_NS->RNR, Region); + /* Set limit address */ - MPU_NS->RLAR |= (LimitAddress & 0xFFFFFFE0U); + MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); } /** @@ -1140,6 +1164,7 @@ __STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress_NS(uint32_t Region) { /* Set Region number */ WRITE_REG(MPU_NS->RNR, Region); + return (READ_REG(MPU_NS->RLAR & MPU_RLAR_LIMIT_Msk)); } @@ -1164,8 +1189,9 @@ __STATIC_INLINE void LL_MPU_SetRegionBaseAddress_NS(uint32_t Region, uint32_t Ba { /* Set Region number */ WRITE_REG(MPU_NS->RNR, Region); + /* Set base address */ - MPU_NS->RBAR |= (BaseAddress & 0xFFFFFFE0U); + MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); } /** @@ -1186,6 +1212,7 @@ __STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress_NS(uint32_t Region) { /* Set Region number */ WRITE_REG(MPU_NS->RNR, Region); + return (READ_REG(MPU_NS->RBAR & MPU_RBAR_BASE_Msk)); } @@ -1217,8 +1244,9 @@ __STATIC_INLINE void LL_MPU_SetRegionAccess_NS(uint32_t Region, uint32_t Attribu { /* Set Region number */ WRITE_REG(MPU_NS->RNR, Region); + /* Set base address Attributes */ - MPU_NS->RBAR |= Attributes; + MODIFY_REG(MPU_NS->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK)); } /** @@ -1242,6 +1270,7 @@ __STATIC_INLINE uint32_t LL_MPU_GetRegionAccess_NS(uint32_t Region) { /* Set Region number */ WRITE_REG(MPU_NS->RNR, Region); + return (READ_REG(MPU_NS->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk))); } #endif /* __ARM_FEATURE_CMSE */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_crc.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_crc.c index 8b5e7fc7ade..c5eb5a06874 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_crc.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_crc.c @@ -101,4 +101,3 @@ ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx) */ #endif /* USE_FULL_LL_DRIVER */ - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_crc.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_crc.h index 95fb5b36b1d..a16a98c0180 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_crc.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_crc.h @@ -235,7 +235,7 @@ __STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t } /** - * @brief Configure the reversal of the bit order of the Output data + * @brief Return type of reversal of the bit order of the Output data * @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode * @param CRCx CRC Instance * @retval Returned value can be one of the following values: diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dac.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dac.c index 98833f9b736..89c42c62ab1 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dac.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dac.c @@ -59,8 +59,8 @@ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_OUT) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM3_OUT) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_CH1) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM3_CH1) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ ) @@ -182,7 +182,7 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) * - SUCCESS: DAC registers are initialized * - ERROR: DAC registers are not initialized */ -ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct) +ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct) { ErrorStatus status = SUCCESS; diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dac.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dac.h index 94d9c086535..1b55ccce8ce 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dac.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dac.h @@ -295,9 +295,12 @@ typedef struct #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */ #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */ #define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */ -#define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 TRGO. */ -#define LL_DAC_TRIG_EXT_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM3 TRGO. */ +#define LL_DAC_TRIG_EXT_LPTIM1_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 CH1. */ +#define LL_DAC_TRIG_EXT_LPTIM3_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM3 CH1. */ #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */ + +#define LL_DAC_TRIG_EXT_LPTIM1_OUT LL_DAC_TRIG_EXT_LPTIM1_CH1 /*!< Keep old definition for compatibility */ +#define LL_DAC_TRIG_EXT_LPTIM3_OUT LL_DAC_TRIG_EXT_LPTIM3_CH1 /*!< Keep old definition for compatibility */ /** * @} */ @@ -596,7 +599,7 @@ __STATIC_INLINE void LL_DAC_SetHighFrequencyMode(DAC_TypeDef *DACx, uint32_t Hig * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ */ -__STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(const DAC_TypeDef *DACx) { return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_HFSEL)); } @@ -604,6 +607,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(DAC_TypeDef *DACx) * @} */ + /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels * @{ */ @@ -642,7 +646,7 @@ __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uin * @arg @ref LL_DAC_MODE_NORMAL_OPERATION * @arg @ref LL_DAC_MODE_CALIBRATION */ -__STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -681,7 +685,7 @@ __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_CHANNEL_2 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F */ -__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -712,8 +716,8 @@ __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO - * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT - * @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT + * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_CH1 + * @arg @ref LL_DAC_TRIG_EXT_LPTIM3_CH1 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 * @retval None */ @@ -746,11 +750,11 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO - * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT - * @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT + * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_CH1 + * @arg @ref LL_DAC_TRIG_EXT_LPTIM3_CH1 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 */ -__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -793,7 +797,7 @@ __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DA * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -859,7 +863,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -926,7 +930,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1024,7 +1028,7 @@ __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channe * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD */ -__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1067,7 +1071,7 @@ __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Chan * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE */ -__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1126,7 +1130,7 @@ __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_ * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL */ -__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1168,7 +1172,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32 * @arg @ref LL_DAC_CHANNEL_2 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ -__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); @@ -1206,7 +1210,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_CHANNEL_2 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ -__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1243,7 +1247,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint3 * @arg @ref LL_DAC_CHANNEL_2 * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1289,7 +1293,7 @@ __STATIC_INLINE void LL_DAC_SetSignedFormat(DAC_TypeDef *DACx, uint32_t DAC_Chan * @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE * @arg @ref LL_DAC_SIGNED_FORMAT_DISABLE */ -__STATIC_INLINE uint32_t LL_DAC_GetSignedFormat(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_GetSignedFormat(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_SINFORMAT1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -1351,7 +1355,7 @@ __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channe * @arg @ref LL_DAC_CHANNEL_2 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return ((READ_BIT(DACx->CR, DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) @@ -1401,7 +1405,7 @@ __STATIC_INLINE void LL_DAC_DisableDMADoubleDataMode(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_CHANNEL_2 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsDMADoubleDataModeEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_IsDMADoubleDataModeEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return ((READ_BIT(DACx->MCR, DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) @@ -1440,7 +1444,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMADoubleDataModeEnabled(DAC_TypeDef *DACx, ui * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED * @retval DAC register address */ -__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) +__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) { /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ /* DAC channel selected. */ @@ -1501,7 +1505,7 @@ __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) * @arg @ref LL_DAC_CHANNEL_2 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return ((READ_BIT(DACx->CR, DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) @@ -1519,7 +1523,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channe * @arg @ref LL_DAC_CHANNEL_2 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsReady(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_IsReady(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return ((READ_BIT(DACx->SR, DAC_SR_DAC1RDY << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) @@ -1577,7 +1581,7 @@ __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Chann * @arg @ref LL_DAC_CHANNEL_2 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { return ((READ_BIT(DACx->CR, DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) @@ -1750,7 +1754,7 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint * @arg @ref LL_DAC_CHANNEL_2 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) +__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel) { __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); @@ -1765,13 +1769,14 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management * @{ */ + /** * @brief Get DAC calibration offset flag for DAC channel 1 * @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1 * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL); } @@ -1783,7 +1788,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL); } @@ -1795,7 +1800,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL); } @@ -1806,7 +1811,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL); } @@ -1818,7 +1823,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC1RDY(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC1RDY(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DAC1RDY) == (LL_DAC_FLAG_DAC1RDY)) ? 1UL : 0UL); } @@ -1830,7 +1835,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC1RDY(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC2RDY(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC2RDY(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DAC2RDY) == (LL_DAC_FLAG_DAC2RDY)) ? 1UL : 0UL); } @@ -1842,7 +1847,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC2RDY(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT1(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT1(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT1) == (LL_DAC_FLAG_DORSTAT1)) ? 1UL : 0UL); } @@ -1854,7 +1859,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT1(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT2(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT2(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT2) == (LL_DAC_FLAG_DORSTAT2)) ? 1UL : 0UL); } @@ -1865,7 +1870,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT2(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL); } @@ -1877,7 +1882,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL); } @@ -1969,7 +1974,7 @@ __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL); } @@ -1981,7 +1986,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL); } @@ -2015,7 +2020,7 @@ __STATIC_INLINE void LL_DAC_DisableAutonomousMode(DAC_TypeDef *DACx) * @param DACx DAC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DAC_IsAutonomousModeEnabled(DAC_TypeDef *DACx) +__STATIC_INLINE uint32_t LL_DAC_IsAutonomousModeEnabled(const DAC_TypeDef *DACx) { return ((READ_BIT(DACx->AUTOCR, DAC_AUTOCR_AUTOMODE) == (DAC_AUTOCR_AUTOMODE)) ? 1UL : 0UL); } @@ -2030,7 +2035,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsAutonomousModeEnabled(DAC_TypeDef *DACx) */ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx); -ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct); +ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct); void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); /** diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dcache.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dcache.h index 911e0f5df85..aa325e59832 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dcache.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dcache.h @@ -31,7 +31,7 @@ extern "C" { * @{ */ -#if defined (DCACHE1) +#if defined (DCACHE1) || defined (DCACHE2) /** @defgroup DCACHE_LL DCACHE * @{ @@ -40,7 +40,10 @@ extern "C" { /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @addtogroup DCACHE_Private_Constants DCACHE Private Constants +/** @defgroup DCACHE_Exported_Constants DCACHE Exported Constants + * @{ + */ +/** @defgroup DCACHE_Command_Operation Command Operation * @{ */ #define LL_DCACHE_COMMAND_NO_OPERATION (0x00000000) @@ -108,6 +111,10 @@ extern "C" { * @} */ +/** + * @} + */ + /* Exported macros --------------------------------------------------------*/ /** @defgroup DCACHE_LL_Exported_Macros DCACHE Exported Macros * @{ @@ -178,7 +185,7 @@ __STATIC_INLINE void LL_DCACHE_Disable(DCACHE_TypeDef *DCACHEx) * @param DCACHEx DCACHE instance * @retval 0: DCACHE is disabled, 1: DCACHE is enabled. */ -__STATIC_INLINE uint32_t LL_DCACHE_IsEnabled(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_IsEnabled(const DCACHE_TypeDef *DCACHEx) { return ((READ_BIT(DCACHEx->CR, DCACHE_CR_EN) == (DCACHE_CR_EN)) ? 1UL : 0UL); } @@ -201,7 +208,7 @@ __STATIC_INLINE void LL_DCACHE_SetStartAddress(DCACHE_TypeDef *DCACHEx, uint32_t * @param DCACHEx DCACHE instance * @retval Start address of dcache command */ -__STATIC_INLINE uint32_t LL_DCACHE_GetStartAddress(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_GetStartAddress(const DCACHE_TypeDef *DCACHEx) { return (uint32_t)(READ_REG(DCACHEx->CMDRSADDRR)); } @@ -224,7 +231,7 @@ __STATIC_INLINE void LL_DCACHE_SetEndAddress(DCACHE_TypeDef *DCACHEx, uint32_t a * @param DCACHEx DCACHE instance * @retval End address of dcache command */ -__STATIC_INLINE uint32_t LL_DCACHE_GetEndAddress(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_GetEndAddress(const DCACHE_TypeDef *DCACHEx) { return (uint32_t)(READ_REG(DCACHEx->CMDREADDRR)); } @@ -234,8 +241,11 @@ __STATIC_INLINE uint32_t LL_DCACHE_GetEndAddress(DCACHE_TypeDef *DCACHEx) * @rmtoll CR CACHECMD LL_DCACHE_SetCommand * @param DCACHEx DCACHE instance * @param Command command to be applied for the dcache - * LL_DCACHE_COMMAND_INVALIDATE_BY_ADDR, LL_DCACHE_COMMAND_CLEAN_BY_ADDR, - * LL_DCACHE_COMMAND_CLEAN_INVALIDATE_BY_ADDR,LL_DCACHE_COMMAND_NO_OPERATION + * Command can be one of the following values: + * @arg @ref LL_DCACHE_COMMAND_INVALIDATE_BY_ADDR + * @arg @ref LL_DCACHE_COMMAND_CLEAN_BY_ADDR + * @arg @ref LL_DCACHE_COMMAND_CLEAN_INVALIDATE_BY_ADDR + * @arg @ref LL_DCACHE_COMMAND_NO_OPERATION * @retval None */ __STATIC_INLINE void LL_DCACHE_SetCommand(DCACHE_TypeDef *DCACHEx, uint32_t Command) @@ -254,7 +264,7 @@ __STATIC_INLINE void LL_DCACHE_SetCommand(DCACHE_TypeDef *DCACHEx, uint32_t Comm * @arg @ref LL_DCACHE_COMMAND_INVALIDATE_BY_ADDR * @arg @ref LL_DCACHE_COMMAND_CLEAN_INVALIDATE_BY_ADDR */ -__STATIC_INLINE uint32_t LL_DCACHE_GetCommand(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_GetCommand(const DCACHE_TypeDef *DCACHEx) { /*Get Dcache Command */ return (uint32_t)(READ_BIT(DCACHEx->CR, DCACHE_CR_CACHECMD)); @@ -276,7 +286,9 @@ __STATIC_INLINE void LL_DCACHE_StartCommand(DCACHE_TypeDef *DCACHEx) * @rmtoll CR HBURST LL_DCACHE_SetReadBurstType * @param DCACHEx DCACHE instance * @param ReadBurstType Burst type to be applied for Data Cache - * LL_DCACHE_READ_BURST_WRAP, LL_DCACHE_READ_BURST_INCR. + * Burst type can be one of the following values: + * @arg @ref LL_DCACHE_READ_BURST_WRAP + * @arg @ref LL_DCACHE_READ_BURST_INCR * @retval None */ __STATIC_INLINE void LL_DCACHE_SetReadBurstType(DCACHE_TypeDef *DCACHEx, uint32_t ReadBurstType) @@ -292,7 +304,7 @@ __STATIC_INLINE void LL_DCACHE_SetReadBurstType(DCACHE_TypeDef *DCACHEx, uint32_ * @arg @ref LL_DCACHE_READ_BURST_WRAP * @arg @ref LL_DCACHE_READ_BURST_INCR */ -__STATIC_INLINE uint32_t LL_DCACHE_GetReadBurstType(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_GetReadBurstType(const DCACHE_TypeDef *DCACHEx) { return (uint32_t)(READ_BIT(DCACHEx->CR, DCACHE_CR_HBURST)); } @@ -363,7 +375,7 @@ __STATIC_INLINE void LL_DCACHE_DisableMonitors(DCACHE_TypeDef *DCACHEx, uint32_t * @arg LL_DCACHE_MONITOR_ALL * @retval State of parameter value (1 or 0). */ -__STATIC_INLINE uint32_t LL_DCACHE_IsEnabledMonitors(DCACHE_TypeDef *DCACHEx, uint32_t Monitors) +__STATIC_INLINE uint32_t LL_DCACHE_IsEnabledMonitors(const DCACHE_TypeDef *DCACHEx, uint32_t Monitors) { return (((READ_BIT(DCACHEx->CR, (DCACHE_CR_WMISSMEN | DCACHE_CR_WHITMEN | DCACHE_CR_RMISSMEN | DCACHE_CR_RHITMEN))\ & Monitors) == (Monitors)) ? 1UL : 0UL); @@ -397,7 +409,7 @@ __STATIC_INLINE void LL_DCACHE_ResetMonitors(DCACHE_TypeDef *DCACHEx, uint32_t M * @param DCACHEx DCACHE instance * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetReadHitValue(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetReadHitValue(const DCACHE_TypeDef *DCACHEx) { return DCACHEx->RHMONR; } @@ -408,7 +420,7 @@ __STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetReadHitValue(DCACHE_TypeDef *DCACH * @param DCACHEx DCACHE instance * @retval Value between Min_Data=0 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetReadMissValue(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetReadMissValue(const DCACHE_TypeDef *DCACHEx) { return DCACHEx->RMMONR; } @@ -419,7 +431,7 @@ __STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetReadMissValue(DCACHE_TypeDef *DCAC * @param DCACHEx DCACHE instance * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetWriteHitValue(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetWriteHitValue(const DCACHE_TypeDef *DCACHEx) { return DCACHEx->WHMONR; } @@ -430,7 +442,7 @@ __STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetWriteHitValue(DCACHE_TypeDef *DCAC * @param DCACHEx DCACHE instance * @retval Value between Min_Data=0 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetWriteMissValue(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetWriteMissValue(const DCACHE_TypeDef *DCACHEx) { return DCACHEx->WMMONR; } @@ -471,7 +483,7 @@ __STATIC_INLINE void LL_DCACHE_DisableIT_BSYEND(DCACHE_TypeDef *DCACHEx) * @param DCACHEx DCACHE instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DCACHE_IsEnabledIT_BSYEND(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_IsEnabledIT_BSYEND(const DCACHE_TypeDef *DCACHEx) { return ((READ_BIT(DCACHEx->IER, DCACHE_IER_BSYENDIE) == (DCACHE_IER_BSYENDIE)) ? 1UL : 0UL); } @@ -504,7 +516,7 @@ __STATIC_INLINE void LL_DCACHE_DisableIT_ERR(DCACHE_TypeDef *DCACHEx) * @param DCACHEx DCACHE instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DCACHE_IsEnabledIT_ERR(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_IsEnabledIT_ERR(const DCACHE_TypeDef *DCACHEx) { return ((READ_BIT(DCACHEx->IER, DCACHE_IER_ERRIE) == (DCACHE_IER_ERRIE)) ? 1UL : 0UL); } @@ -537,7 +549,7 @@ __STATIC_INLINE void LL_DCACHE_DisableIT_CMDEND(DCACHE_TypeDef *DCACHEx) * @param DCACHEx DCACHE instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DCACHE_IsEnabledIT_CMDEND(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_IsEnabledIT_CMDEND(const DCACHE_TypeDef *DCACHEx) { return ((READ_BIT(DCACHEx->IER, DCACHE_IER_CMDENDIE) == (DCACHE_IER_CMDENDIE)) ? 1UL : 0UL); } @@ -581,7 +593,7 @@ __STATIC_INLINE void LL_DCACHE_ClearFlag_CMDEND(DCACHE_TypeDef *DCACHEx) * @param DCACHEx DCACHE instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_BUSY(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_BUSY(const DCACHE_TypeDef *DCACHEx) { return ((READ_BIT(DCACHEx->SR, DCACHE_SR_BUSYF) == (DCACHE_SR_BUSYF)) ? 1UL : 0UL); } @@ -592,7 +604,7 @@ __STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_BUSY(DCACHE_TypeDef *DCACHEx) * @param DCACHEx DCACHE instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_BSYEND(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_BSYEND(const DCACHE_TypeDef *DCACHEx) { return ((READ_BIT(DCACHEx->SR, DCACHE_SR_BSYENDF) == (DCACHE_SR_BSYENDF)) ? 1UL : 0UL); } @@ -603,7 +615,7 @@ __STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_BSYEND(DCACHE_TypeDef *DCACHEx) * @param DCACHEx DCACHE instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_ERR(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_ERR(const DCACHE_TypeDef *DCACHEx) { return ((READ_BIT(DCACHEx->SR, DCACHE_SR_ERRF) == (DCACHE_SR_ERRF)) ? 1UL : 0UL); } @@ -614,7 +626,7 @@ __STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_ERR(DCACHE_TypeDef *DCACHEx) * @param DCACHEx DCACHE instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_BUSYCMD(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_BUSYCMD(const DCACHE_TypeDef *DCACHEx) { return ((READ_BIT(DCACHEx->SR, DCACHE_SR_BUSYCMDF) == (DCACHE_SR_BUSYCMDF)) ? 1UL : 0UL); } @@ -625,7 +637,7 @@ __STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_BUSYCMD(DCACHE_TypeDef *DCACHEx) * @param DCACHEx DCACHE instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_CMDEND(DCACHE_TypeDef *DCACHEx) +__STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_CMDEND(const DCACHE_TypeDef *DCACHEx) { return ((READ_BIT(DCACHEx->SR, DCACHE_SR_CMDENDF) == (DCACHE_SR_CMDENDF)) ? 1UL : 0UL); } @@ -642,7 +654,7 @@ __STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_CMDEND(DCACHE_TypeDef *DCACHEx) * @} */ -#endif /* defined(DCACHE1) */ +#endif /* DCACHE1 || DCACHE2 */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dlyb.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dlyb.c index 7cec0a7381d..723723c70f3 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dlyb.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dlyb.c @@ -55,12 +55,12 @@ * @{ */ -/** @defgroup DLYB DLYB +/** @defgroup DLYB_LL DLYB * @brief DLYB LL module driver. * @{ */ -#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_QSPI_MODULE_ENABLED)|| defined(HAL_OSPI_MODULE_ENABLED) +#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_OSPI_MODULE_ENABLED) || defined(HAL_XSPI_MODULE_ENABLED) /** @cond 0 @@ -230,7 +230,7 @@ uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_c /** * @} */ -#endif /* HAL_SD_MODULE_ENABLED || HAL_QSPI_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED */ +#endif /* HAL_SD_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED || HAL_XSPI_MODULE_ENABLED */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dlyb.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dlyb.h index 1c9494e0351..5b1774c9df0 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dlyb.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dlyb.h @@ -31,14 +31,10 @@ extern "C" { * @{ */ -#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_QSPI_MODULE_ENABLED)|| defined(HAL_OSPI_MODULE_ENABLED) - -/** @addtogroup DLYB - * @{ - */ +#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_OSPI_MODULE_ENABLED) || defined(HAL_XSPI_MODULE_ENABLED) /* Exported types ------------------------------------------------------------*/ -/** @defgroup DLYB_LL_Exported_Types DLYB Exported Types +/** @defgroup DLYB_LL DLYB * @{ */ @@ -55,17 +51,17 @@ typedef struct This parameter can be a value between 0 and DLYB_MAX_SELECT */ } LL_DLYB_CfgTypeDef; -/** - * @} - */ - /* Exported constants --------------------------------------------------------*/ /** @defgroup DLYB_Exported_Constants DLYB Exported Constants * @{ */ #define DLYB_MAX_UNIT ((uint32_t)0x00000080U) /*!< Max UNIT value (128) */ -#define DLYB_MAX_SELECT ((uint32_t)0x0000000CU) /*!< Max SELECT value (12) */ +#define DLYB_MAX_SELECT ((uint32_t)0x0000000CU) /*!< Max SELECT value (12) */ + +/** + * @} + */ /** @defgroup DLYB_LL_Flags DLYB Flags * @{ @@ -73,10 +69,6 @@ typedef struct #define DLYB_FLAG_LNGF DLYB_CFGR_LNGF -/** - * @} - */ - /** * @} */ @@ -116,8 +108,7 @@ __STATIC_INLINE void LL_DLYB_Disable(DLYB_TypeDef *DLYBx) * @} */ - -/** @addtogroup DLYB_Control_Functions DLYB Control functions +/** @defgroup DLYB_Control_Functions DLYB Control functions * @{ */ @@ -137,7 +128,7 @@ uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_c * @} */ -#endif /* HAL_SD_MODULE_ENABLED || HAL_QSPI_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED */ +#endif /* HAL_SD_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED || HAL_XSPI_MODULE_ENABLED */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dma.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dma.c index 3286a2e0334..9f15910b2ae 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dma.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dma.c @@ -160,9 +160,13 @@ #define IS_LL_DMA_BLKHW_REQUEST(__VALUE__) (((__VALUE__) == LL_DMA_HWREQUEST_SINGLEBURST) || \ ((__VALUE__) == LL_DMA_HWREQUEST_BLK)) -#define IS_LL_DMA_TRIGGER_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_TRIGGER_TIM15_TRGO) +#define IS_LL_DMA_TRIGGER_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_TRIGGER_ADC1_AWD1) +#if defined (LL_GPDMA1_REQUEST_ADC2) +#define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_ADC2) +#else #define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_LPTIM3_UE) +#endif /* LL_GPDMA1_REQUEST_ADC2 */ #define IS_LL_DMA_TRANSFER_EVENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TCEM_BLK_TRANSFER) || \ ((__VALUE__) == LL_DMA_TCEM_RPT_BLK_TRANSFER) || \ @@ -645,7 +649,7 @@ void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) DMA_InitStruct->BlkRptDestAddrOffset = 0x00000000U; DMA_InitStruct->LinkedListBaseAddr = 0x00000000U; DMA_InitStruct->LinkedListAddrOffset = 0x00000000U; -}; +} /** * @brief Set each @ref LL_DMA_InitLinkedListTypeDef field to default value. @@ -660,7 +664,7 @@ void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruc DMA_InitLinkedListStruct->LinkStepMode = LL_DMA_LSM_FULL_EXECUTION; DMA_InitLinkedListStruct->TransferEventMode = LL_DMA_TCEM_LAST_LLITEM_TRANSFER; DMA_InitLinkedListStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0; -}; +} /** * @brief De-initialize the DMA linked list. @@ -814,7 +818,7 @@ void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct) LL_DMA_UPDATE_CDAR | LL_DMA_UPDATE_CTR3 | \ LL_DMA_UPDATE_CBR2 | LL_DMA_UPDATE_CLLR); DMA_InitNodeStruct->NodeType = LL_DMA_GPDMA_LINEAR_NODE; -}; +} /** * @brief Initializes DMA linked list node according to the specified diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dma.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dma.h index 27a996e0588..8687c0d2d05 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dma.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dma.h @@ -988,8 +988,10 @@ typedef struct #define LL_GPDMA1_REQUEST_I2C4_EVC 23U /*!< GPDMA1 HW Request is I2C4_EVC */ #define LL_GPDMA1_REQUEST_USART1_RX 24U /*!< GPDMA1 HW Request is USART1_RX */ #define LL_GPDMA1_REQUEST_USART1_TX 25U /*!< GPDMA1 HW Request is USART1_TX */ +#if defined (USART2) #define LL_GPDMA1_REQUEST_USART2_RX 26U /*!< GPDMA1 HW Request is USART2_RX */ #define LL_GPDMA1_REQUEST_USART2_TX 27U /*!< GPDMA1 HW Request is USART2_TX */ +#endif /* USART2 */ #define LL_GPDMA1_REQUEST_USART3_RX 28U /*!< GPDMA1 HW Request is USART3_RX */ #define LL_GPDMA1_REQUEST_USART3_TX 29U /*!< GPDMA1 HW Request is USART3_TX */ #define LL_GPDMA1_REQUEST_UART4_RX 30U /*!< GPDMA1 HW Request is UART4_RX */ @@ -1000,10 +1002,14 @@ typedef struct #define LL_GPDMA1_REQUEST_LPUART1_TX 35U /*!< GPDMA1 HW Request is LPUART1_TX */ #define LL_GPDMA1_REQUEST_SAI1_A 36U /*!< GPDMA1 HW Request is SAI1_A */ #define LL_GPDMA1_REQUEST_SAI1_B 37U /*!< GPDMA1 HW Request is SAI1_B */ +#if defined (SAI2) #define LL_GPDMA1_REQUEST_SAI2_A 38U /*!< GPDMA1 HW Request is SAI2_A */ #define LL_GPDMA1_REQUEST_SAI2_B 39U /*!< GPDMA1 HW Request is SAI2_B */ +#endif /* SAI2 */ #define LL_GPDMA1_REQUEST_OCTOSPI1 40U /*!< GPDMA1 HW Request is OCTOSPI1 */ +#if defined (OCTOSPI2) #define LL_GPDMA1_REQUEST_OCTOSPI2 41U /*!< GPDMA1 HW Request is OCTOSPI2 */ +#endif /* OCTOSPI2 */ #define LL_GPDMA1_REQUEST_TIM1_CH1 42U /*!< GPDMA1 HW Request is TIM1_CH1 */ #define LL_GPDMA1_REQUEST_TIM1_CH2 43U /*!< GPDMA1 HW Request is TIM1_CH2 */ #define LL_GPDMA1_REQUEST_TIM1_CH3 44U /*!< GPDMA1 HW Request is TIM1_CH3 */ @@ -1048,12 +1054,14 @@ typedef struct #define LL_GPDMA1_REQUEST_TIM16_UP 83U /*!< GPDMA1 HW Request is TIM16_UP */ #define LL_GPDMA1_REQUEST_TIM17_CH1 84U /*!< GPDMA1 HW Request is TIM17_CH1 */ #define LL_GPDMA1_REQUEST_TIM17_UP 85U /*!< GPDMA1 HW Request is TIM17_UP */ -#define LL_GPDMA1_REQUEST_DCMI 86U /*!< GPDMA1 HW Request is DCMI */ +#define LL_GPDMA1_REQUEST_DCMI_PSSI 86U /*!< GPDMA1 HW Request is DCMI_PSSI */ #define LL_GPDMA1_REQUEST_AES_IN 87U /*!< GPDMA1 HW Request is AES_IN */ #define LL_GPDMA1_REQUEST_AES_OUT 88U /*!< GPDMA1 HW Request is AES_OUT */ #define LL_GPDMA1_REQUEST_HASH_IN 89U /*!< GPDMA1 HW Request is HASH_IN */ +#if defined (UCPD1) #define LL_GPDMA1_REQUEST_UCPD1_TX 90U /*!< GPDMA1 HW Request is UCPD1_TX */ #define LL_GPDMA1_REQUEST_UCPD1_RX 91U /*!< GPDMA1 HW Request is UCPD1_RX */ +#endif /* UCPD1 */ #define LL_GPDMA1_REQUEST_MDF1_FLT0 92U /*!< GPDMA1 HW Request is MDF1_FLT0 */ #define LL_GPDMA1_REQUEST_MDF1_FLT1 93U /*!< GPDMA1 HW Request is MDF1_FLT1 */ #define LL_GPDMA1_REQUEST_MDF1_FLT2 94U /*!< GPDMA1 HW Request is MDF1_FLT2 */ @@ -1076,6 +1084,29 @@ typedef struct #define LL_GPDMA1_REQUEST_LPTIM3_IC1 111U /*!< GPDMA1 HW Request is LPTIM3_IC1 */ #define LL_GPDMA1_REQUEST_LPTIM3_IC2 112U /*!< GPDMA1 HW Request is LPTIM3_IC2 */ #define LL_GPDMA1_REQUEST_LPTIM3_UE 113U /*!< GPDMA1 HW Request is LPTIM3_UE */ +#if defined (HSPI1_BASE) +#define LL_GPDMA1_REQUEST_HSPI1 114U /*!< GPDMA1 HW request is HSPI1 */ +#endif /* defined (HSPI1_BASE) */ +#if defined (I2C5) +#define LL_GPDMA1_REQUEST_I2C5_RX 115U /*!< GPDMA1 HW request is I2C5_RX */ +#define LL_GPDMA1_REQUEST_I2C5_TX 116U /*!< GPDMA1 HW request is I2C5_TX */ +#define LL_GPDMA1_REQUEST_I2C5_EVC 117U /*!< GPDMA1 HW request is I2C5_EVC */ +#endif /* defined (I2C5) */ +#if defined (I2C6) +#define LL_GPDMA1_REQUEST_I2C6_RX 118U /*!< GPDMA1 HW request is I2C6_RX */ +#define LL_GPDMA1_REQUEST_I2C6_TX 119U /*!< GPDMA1 HW request is I2C6_TX */ +#define LL_GPDMA1_REQUEST_I2C6_EVC 120U /*!< GPDMA1 HW request is I2C6_EVC */ +#endif /* defined (I2C6) */ +#if defined (USART6) +#define LL_GPDMA1_REQUEST_USART6_RX 121U /*!< GPDMA1 HW request is USART6_RX */ +#define LL_GPDMA1_REQUEST_USART6_TX 122U /*!< GPDMA1 HW request is USART6_TX */ +#endif /* defined (USART6) */ +#if defined (ADC2) +#define LL_GPDMA1_REQUEST_ADC2 123U /*!< GPDMA1 HW request is ADC2 */ +#endif /* defined (ADC2) */ + +/* GPDMA1 Hardware Requests aliases */ +#define LL_GPDMA1_REQUEST_DCMI LL_GPDMA1_REQUEST_DCMI_PSSI /* LPDMA1 Hardware Requests */ #define LL_LPDMA1_REQUEST_LPUART1_RX 0U /*!< LPDMA1 HW Request is LPUART1_RX */ @@ -1148,6 +1179,33 @@ typedef struct #define LL_GPDMA1_TRIGGER_TIM15_TRGO 43U /*!< GPDMA1 HW Trigger is TIM15_TRGO */ #define LL_GPDMA1_TRIGGER_ADC4_AWD1 57U /*!< GPDMA1 HW Trigger is ADC4_AWD1 */ #define LL_GPDMA1_TRIGGER_ADC1_AWD1 58U /*!< GPDMA1 HW Trigger is ADC1_AWD1 */ +#if defined (TIM3_TRGO_TRIGGER_SUPPORT) +#define LL_GPDMA1_TRIGGER_TIM3_TRGO 44U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ +#endif /* defined (TIM3_TRGO_TRIGGER_SUPPORT) */ +#if defined (TIM4_TRGO_TRIGGER_SUPPORT) +#define LL_GPDMA1_TRIGGER_TIM4_TRGO 45U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */ +#endif /* defined (TIM4_TRGO_TRIGGER_SUPPORT) */ +#if defined (TIM5_TRGO_TRIGGER_SUPPORT) +#define LL_GPDMA1_TRIGGER_TIM5_TRGO 46U /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */ +#endif /* defined (TIM5_TRGO_TRIGGER_SUPPORT) */ +#if defined (LTDC) +#define LL_GPDMA1_TRIGGER_LTDC_LI 47U /*!< GPDMA1 HW Trigger signal is LTDC_LI */ +#endif /* defined (LTDC) */ +#if defined (DSI) +#define LL_GPDMA1_TRIGGER_DSI_TE 48U /*!< GPDMA1 HW Trigger signal is DSI_TE */ +#define LL_GPDMA1_TRIGGER_DSI_ER 49U /*!< GPDMA1 HW Trigger signal is DSI_ER */ +#endif /* defined (DSI) */ +#if defined (DMA2D) +#define LL_GPDMA1_TRIGGER_DMA2D_TC 50U /*!< GPDMA1 HW Trigger signal is DMA2D_TC */ +#define LL_GPDMA1_TRIGGER_DMA2D_CTC 51U /*!< GPDMA1 HW Trigger signal is DMA2D_CTC */ +#define LL_GPDMA1_TRIGGER_DMA2D_TW 52U /*!< GPDMA1 HW Trigger signal is DMA2D_TW */ +#endif /* defined (DMA2D) */ +#if defined (GPU2D) +#define LL_GPDMA1_TRIGGER_GPU2D_FLAG0 53U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG0 */ +#define LL_GPDMA1_TRIGGER_GPU2D_FLAG1 54U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG1 */ +#define LL_GPDMA1_TRIGGER_GPU2D_FLAG2 55U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG2 */ +#define LL_GPDMA1_TRIGGER_GPU2D_FLAG3 56U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG3 */ +#endif /* defined (GPU2D) */ /* LPDMA1 triggers */ #define LL_LPDMA1_TRIGGER_EXTI_LINE0 0U /*!< LPDMA1 HW Trigger is EXTI_LINE0 */ @@ -1167,6 +1225,7 @@ typedef struct #define LL_LPDMA1_TRIGGER_RTC_ALRA_TRG 14U /*!< LPDMA1 HW Trigger is RTC_ALRA_TRG */ #define LL_LPDMA1_TRIGGER_RTC_ALRB_TRG 15U /*!< LPDMA1 HW Trigger is RTC_ALRB_TRG */ #define LL_LPDMA1_TRIGGER_RTC_WUT_TRG 16U /*!< LPDMA1 HW Trigger is RTC_WUT_TRG */ +#define LL_LPDMA1_TRIGGER_ADC4_AWD1 17U /*!< LPDMA1 HW Trigger is ADC4_AWD1 */ #define LL_LPDMA1_TRIGGER_LPDMA1_CH0_TCF 18U /*!< LPDMA1 HW Trigger is LPDMA1_CH0_TCF */ #define LL_LPDMA1_TRIGGER_LPDMA1_CH1_TCF 19U /*!< LPDMA1 HW Trigger is LPDMA1_CH1_TCF */ #define LL_LPDMA1_TRIGGER_LPDMA1_CH2_TCF 20U /*!< LPDMA1 HW Trigger is LPDMA1_CH2_TCF */ @@ -2471,7 +2530,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDestBurstLength(DMA_TypeDef *DMAx, uint32_t C { uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, - DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U); + DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U); } /** @@ -2510,7 +2569,7 @@ __STATIC_INLINE void LL_DMA_SetDestIncMode(DMA_TypeDef *DMAx, uint32_t Channel, /** * @brief Get destination increment mode. * @note This API is used for all available DMA channels. - * @rmtoll CTR1 DINC LL_DMA_GetDestinationIncMode + * @rmtoll CTR1 DINC LL_DMA_GetDestIncMode * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_0 @@ -2804,7 +2863,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetSrcBurstLength(DMA_TypeDef *DMAx, uint32_t Ch { uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, - DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U); + DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U); } /** @@ -3383,8 +3442,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(DMA_TypeDef *DMAx, uint32_t Chan * @arg @ref LL_GPDMA1_REQUEST_I2C4_EVC * @arg @ref LL_GPDMA1_REQUEST_USART1_RX * @arg @ref LL_GPDMA1_REQUEST_USART1_TX - * @arg @ref LL_GPDMA1_REQUEST_USART2_RX - * @arg @ref LL_GPDMA1_REQUEST_USART2_TX + * @arg @ref LL_GPDMA1_REQUEST_USART2_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART2_TX (*) * @arg @ref LL_GPDMA1_REQUEST_USART3_RX * @arg @ref LL_GPDMA1_REQUEST_USART3_TX * @arg @ref LL_GPDMA1_REQUEST_UART4_RX @@ -3395,10 +3454,10 @@ __STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(DMA_TypeDef *DMAx, uint32_t Chan * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX * @arg @ref LL_GPDMA1_REQUEST_SAI1_A * @arg @ref LL_GPDMA1_REQUEST_SAI1_B - * @arg @ref LL_GPDMA1_REQUEST_SAI2_A - * @arg @ref LL_GPDMA1_REQUEST_SAI2_B + * @arg @ref LL_GPDMA1_REQUEST_SAI2_A (*) + * @arg @ref LL_GPDMA1_REQUEST_SAI2_B (*) * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1 - * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI2 + * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI2 (*) * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3 @@ -3443,12 +3502,12 @@ __STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(DMA_TypeDef *DMAx, uint32_t Chan * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1 * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP - * @arg @ref LL_GPDMA1_REQUEST_DCMI + * @arg @ref LL_GPDMA1_REQUEST_DCMI_PSSI * @arg @ref LL_GPDMA1_REQUEST_AES_IN * @arg @ref LL_GPDMA1_REQUEST_AES_OUT * @arg @ref LL_GPDMA1_REQUEST_HASH_IN - * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX - * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX + * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX (*) * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT0 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT1 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT2 @@ -3471,6 +3530,16 @@ __STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(DMA_TypeDef *DMAx, uint32_t Chan * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE + * @arg @ref LL_GPDMA1_REQUEST_HSPI1 (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C5_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C5_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C5_EVC (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C6_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C6_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C6_EVC (*) + * @arg @ref LL_GPDMA1_REQUEST_USART6_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART6_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_ADC2 (*) * * @arg @ref LL_LPDMA1_REQUEST_LPUART1_RX * @arg @ref LL_LPDMA1_REQUEST_LPUART1_TX @@ -3489,6 +3558,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(DMA_TypeDef *DMAx, uint32_t Chan * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC1 * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC2 * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_UE + * + * @note (*) Availability depends on devices. * @retval None. */ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) @@ -3547,8 +3618,8 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_GPDMA1_REQUEST_I2C4_EVC * @arg @ref LL_GPDMA1_REQUEST_USART1_RX * @arg @ref LL_GPDMA1_REQUEST_USART1_TX - * @arg @ref LL_GPDMA1_REQUEST_USART2_RX - * @arg @ref LL_GPDMA1_REQUEST_USART2_TX + * @arg @ref LL_GPDMA1_REQUEST_USART2_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART2_TX (*) * @arg @ref LL_GPDMA1_REQUEST_USART3_RX * @arg @ref LL_GPDMA1_REQUEST_USART3_TX * @arg @ref LL_GPDMA1_REQUEST_UART4_RX @@ -3559,10 +3630,10 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX * @arg @ref LL_GPDMA1_REQUEST_SAI1_A * @arg @ref LL_GPDMA1_REQUEST_SAI1_B - * @arg @ref LL_GPDMA1_REQUEST_SAI2_A - * @arg @ref LL_GPDMA1_REQUEST_SAI2_B + * @arg @ref LL_GPDMA1_REQUEST_SAI2_A (*) + * @arg @ref LL_GPDMA1_REQUEST_SAI2_B (*) * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1 - * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI2 + * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI2 (*) * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3 @@ -3607,12 +3678,12 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1 * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP - * @arg @ref LL_GPDMA1_REQUEST_DCMI + * @arg @ref LL_GPDMA1_REQUEST_DCMI_PSSI * @arg @ref LL_GPDMA1_REQUEST_AES_IN * @arg @ref LL_GPDMA1_REQUEST_AES_OUT * @arg @ref LL_GPDMA1_REQUEST_HASH_IN - * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX - * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX + * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX (*) * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT0 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT1 * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT2 @@ -3635,6 +3706,16 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE + * @arg @ref LL_GPDMA1_REQUEST_HSPI1 (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C5_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C5_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C5_EVC (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C6_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C6_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C6_EVC (*) + * @arg @ref LL_GPDMA1_REQUEST_USART6_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART6_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_ADC2 (*) * * @arg @ref LL_LPDMA1_REQUEST_LPUART1_RX * @arg @ref LL_LPDMA1_REQUEST_LPUART1_TX @@ -3653,6 +3734,8 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC1 * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC2 * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_UE + * + * @note (*) Availability depends on devices. */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) { @@ -3723,6 +3806,21 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Ch * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH3_TCF * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO (*) + * @arg @ref LL_GPDMA1_TRIGGER_TIM4_TRGO (*) + * @arg @ref LL_GPDMA1_TRIGGER_TIM5_TRGO (*) + * @arg @ref LL_GPDMA1_TRIGGER_LTDC_LI (*) + * @arg @ref LL_GPDMA1_TRIGGER_DSI_TE (*) + * @arg @ref LL_GPDMA1_TRIGGER_DSI_ER (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TC (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_CTC (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TW (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG0 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG1 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG2 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG3 (*) + * @arg @ref LL_GPDMA1_TRIGGER_ADC4_AWD1 + * @arg @ref LL_GPDMA1_TRIGGER_ADC1_AWD1 * * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE0 * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE1 @@ -3741,6 +3839,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Ch * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRA_TRG * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRB_TRG * @arg @ref LL_LPDMA1_TRIGGER_RTC_WUT_TRG + * @arg @ref LL_LPDMA1_TRIGGER_ADC4_AWD1 * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH0_TCF * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH1_TCF * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH2_TCF @@ -3755,6 +3854,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Ch * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH13_TCF * @arg @ref LL_LPDMA1_TRIGGER_TIM2_TRGO * @arg @ref LL_LPDMA1_TRIGGER_TIM15_TRGO + * @note (*) Availability depends on devices. * @retval None. */ __STATIC_INLINE void LL_DMA_SetHWTrigger(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Trigger) @@ -3827,6 +3927,21 @@ __STATIC_INLINE void LL_DMA_SetHWTrigger(DMA_TypeDef *DMAx, uint32_t Channel, ui * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH3_TCF * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO (*) + * @arg @ref LL_GPDMA1_TRIGGER_TIM4_TRGO (*) + * @arg @ref LL_GPDMA1_TRIGGER_TIM5_TRGO (*) + * @arg @ref LL_GPDMA1_TRIGGER_LTDC_LI (*) + * @arg @ref LL_GPDMA1_TRIGGER_DSI_TE (*) + * @arg @ref LL_GPDMA1_TRIGGER_DSI_ER (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TC (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_CTC (*) + * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TW (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG0 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG1 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG2 (*) + * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG3 (*) + * @arg @ref LL_GPDMA1_TRIGGER_ADC4_AWD1 + * @arg @ref LL_GPDMA1_TRIGGER_ADC1_AWD1 * * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE0 * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE1 @@ -3845,6 +3960,7 @@ __STATIC_INLINE void LL_DMA_SetHWTrigger(DMA_TypeDef *DMAx, uint32_t Channel, ui * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRA_TRG * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRB_TRG * @arg @ref LL_LPDMA1_TRIGGER_RTC_WUT_TRG + * @arg @ref LL_LPDMA1_TRIGGER_ADC4_AWD1 * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH0_TCF * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH1_TCF * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH2_TCF @@ -3859,6 +3975,7 @@ __STATIC_INLINE void LL_DMA_SetHWTrigger(DMA_TypeDef *DMAx, uint32_t Channel, ui * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH13_TCF * @arg @ref LL_LPDMA1_TRIGGER_TIM2_TRGO * @arg @ref LL_LPDMA1_TRIGGER_TIM15_TRGO + * @note (*) Availability depends on devices. */ __STATIC_INLINE uint32_t LL_DMA_GetHWTrigger(DMA_TypeDef *DMAx, uint32_t Channel) { @@ -4430,7 +4547,7 @@ __STATIC_INLINE void LL_DMA_SetSrcAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Ch /** * @brief Get source address offset. * @note This API is used only for 2D addressing channels. - * @rmtoll CTR3 SAO LL_DMA_GetSrcAddressUpdateValue + * @rmtoll CTR3 SAO LL_DMA_GetSrcAddrUpdateValue * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_12 @@ -4552,14 +4669,14 @@ __STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdateValue(DMA_TypeDef *DMAx, u * @brief Configure registers update and node address offset during the link transfer. * @note This API is used for all available DMA channels. * For linear addressing channels, UT3 and UB2 fields are discarded. - * @rmtoll CLLR UT1 LL_DMA_ConfigRegistersUpdate\n - * @rmtoll CLLR UT2 LL_DMA_ConfigRegistersUpdate\n - * @rmtoll CLLR UB1 LL_DMA_ConfigRegistersUpdate\n - * @rmtoll CLLR USA LL_DMA_ConfigRegistersUpdate\n - * @rmtoll CLLR UDA LL_DMA_ConfigRegistersUpdate\n - * @rmtoll CLLR UT3 LL_DMA_ConfigRegistersUpdate\n - * @rmtoll CLLR UB2 LL_DMA_ConfigRegistersUpdate\n - * @rmtoll CLLR ULL LL_DMA_ConfigRegistersUpdate + * @rmtoll CLLR UT1 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UT2 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UB1 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR USA LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UDA LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UT3 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UB2 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR ULL LL_DMA_ConfigLinkUpdate * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_0 @@ -5500,7 +5617,7 @@ __STATIC_INLINE void LL_DMA_DisableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t /** * @brief Check if DMA Channel privilege is enabled. * @note This API is used for all available DMA channels. - * @rmtoll PRIVCFGR PRIVx LL_DMA_IsEnabledChannelPrivileged + * @rmtoll PRIVCFGR PRIVx LL_DMA_IsEnabledChannelPrivilege * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_0 @@ -6057,7 +6174,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_IDLE(DMA_TypeDef *DMAx, uint32_t Ch /** * @brief Check if nsecure masked interrupt is active. * @note This API is used for all available DMA channels. - * @rmtoll MISR MISx LL_DMA_IsEnableIT_MIS + * @rmtoll MISR MISx LL_DMA_IsActiveFlag_MIS * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_0 @@ -6088,7 +6205,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_MIS(DMA_TypeDef *DMAx, uint32_t Cha /** * @brief Check if secure masked interrupt is active. * @note This API is used for all available DMA channels. - * @rmtoll SMISR MISx LL_DMA_IsEnableIT_SMIS + * @rmtoll SMISR MISx LL_DMA_IsActiveFlag_SMIS * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_0 diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dma2d.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dma2d.c index ef330946341..95fd2de4c70 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dma2d.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dma2d.c @@ -110,6 +110,11 @@ ((MODE) == LL_DMA2D_ALPHA_MODE_REPLACE) || \ ((MODE) == LL_DMA2D_ALPHA_MODE_COMBINE)) +#if defined(DMA2D_FGPFCCR_CSS) +#define IS_LL_DMA2D_CHROMA_SUB_SAMPLING(CSS) (((CSS) == LL_DMA2D_CSS_444) || \ + ((CSS) == LL_DMA2D_CSS_422) || \ + ((CSS) == LL_DMA2D_CSS_420)) +#endif /* DMA2D_FGPFCCR_CSS */ /** * @} @@ -133,7 +138,7 @@ * - SUCCESS: DMA2D registers are de-initialized * - ERROR: DMA2D registers are not de-initialized */ -ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx) +ErrorStatus LL_DMA2D_DeInit(const DMA2D_TypeDef *DMA2Dx) { ErrorStatus status = SUCCESS; @@ -290,6 +295,9 @@ void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D assert_param(IS_LL_DMA2D_ALPHA(DMA2D_LayerCfg->Alpha)); assert_param(IS_LL_DMA2D_ALPHAINV(DMA2D_LayerCfg->AlphaInversionMode)); assert_param(IS_LL_DMA2D_RBSWAP(DMA2D_LayerCfg->RBSwapMode)); +#if defined(DMA2D_FGPFCCR_CSS) + assert_param(IS_LL_DMA2D_CHROMA_SUB_SAMPLING(DMA2D_LayerCfg->ChromaSubSampling)); +#endif /* DMA2D_FGPFCCR_CSS */ if (LayerIdx == 0U) @@ -324,6 +332,17 @@ void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D /* Configure the foreground line offset */ LL_DMA2D_FGND_SetLineOffset(DMA2Dx, DMA2D_LayerCfg->LineOffset); +#if defined(DMA2D_FGPFCCR_CSS) + /* Configure the foreground Alpha value, Alpha mode, RB swap, Alpha inversion + CLUT size, CLUT Color mode and Color mode */ + MODIFY_REG(DMA2Dx->FGPFCCR, \ + (DMA2D_FGPFCCR_ALPHA | DMA2D_FGPFCCR_RBS | DMA2D_FGPFCCR_AI | DMA2D_FGPFCCR_CSS | DMA2D_FGPFCCR_AM | \ + DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM | DMA2D_FGPFCCR_CM), \ + ((DMA2D_LayerCfg->Alpha << DMA2D_FGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->RBSwapMode | \ + DMA2D_LayerCfg->AlphaInversionMode | DMA2D_LayerCfg->ChromaSubSampling | \ + DMA2D_LayerCfg->AlphaMode | (DMA2D_LayerCfg->CLUTSize << DMA2D_FGPFCCR_CS_Pos) | \ + DMA2D_LayerCfg->CLUTColorMode | DMA2D_LayerCfg->ColorMode)); +#else /* Configure the foreground Alpha value, Alpha mode, RB swap, Alpha inversion CLUT size, CLUT Color mode and Color mode */ MODIFY_REG(DMA2Dx->FGPFCCR, \ @@ -333,6 +352,7 @@ void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D DMA2D_LayerCfg->AlphaInversionMode | DMA2D_LayerCfg->AlphaMode | \ (DMA2D_LayerCfg->CLUTSize << DMA2D_FGPFCCR_CS_Pos) | DMA2D_LayerCfg->CLUTColorMode | \ DMA2D_LayerCfg->ColorMode)); +#endif /* DMA2D_FGPFCCR_CSS */ /* Configure the foreground color */ LL_DMA2D_FGND_SetColor(DMA2Dx, DMA2D_LayerCfg->Red, DMA2D_LayerCfg->Green, DMA2D_LayerCfg->Blue); @@ -364,6 +384,9 @@ void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg) DMA2D_LayerCfg->CLUTMemoryAddress = 0x0U; DMA2D_LayerCfg->AlphaInversionMode = LL_DMA2D_ALPHA_REGULAR; DMA2D_LayerCfg->RBSwapMode = LL_DMA2D_RB_MODE_REGULAR; +#if defined(DMA2D_FGPFCCR_CSS) + DMA2D_LayerCfg->ChromaSubSampling = LL_DMA2D_CSS_444; +#endif /* DMA2D_FGPFCCR_CSS */ } /** @@ -433,7 +456,7 @@ void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DM * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 * @retval Output Blue color value between Min_Data=0 and Max_Data=0xFF */ -uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +uint32_t LL_DMA2D_GetOutputBlueColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { uint32_t color; @@ -477,7 +500,7 @@ uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 * @retval Output Green color value between Min_Data=0 and Max_Data=0xFF */ -uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +uint32_t LL_DMA2D_GetOutputGreenColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { uint32_t color; @@ -521,7 +544,7 @@ uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 * @retval Output Red color value between Min_Data=0 and Max_Data=0xFF */ -uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +uint32_t LL_DMA2D_GetOutputRedColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { uint32_t color; @@ -565,7 +588,7 @@ uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 * @retval Output Alpha color value between Min_Data=0 and Max_Data=0xFF */ -uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +uint32_t LL_DMA2D_GetOutputAlphaColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { uint32_t color; @@ -626,5 +649,3 @@ void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t Nb */ #endif /* USE_FULL_LL_DRIVER */ - - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dma2d.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dma2d.h index abf5aad25ec..ef89e0600ce 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dma2d.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_dma2d.h @@ -285,6 +285,14 @@ typedef struct - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer, - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */ +#if defined(DMA2D_FGPFCCR_CSS) + uint32_t ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode + This parameter is applicable for foreground layer only. + This parameter can be one value of @ref DMA2D_LL_CHROMA_SUB_SAMPLING + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetChrSubSampling() for foreground layer. */ +#endif /* DMA2D_FGPFCCR_CSS */ } LL_DMA2D_LayerCfgTypeDef; @@ -439,6 +447,9 @@ typedef struct #define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /*!< L4 */ #define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3) /*!< A8 */ #define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< A4 */ +#if defined(DMA2D_FGPFCCR_CSS) +#define LL_DMA2D_INPUT_MODE_YCBCR (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< YCbCr */ +#endif /* DMA2D_FGPFCCR_CSS */ /** * @} */ @@ -502,6 +513,17 @@ typedef struct * @} */ +#if defined(DMA2D_FGPFCCR_CSS) +/** @defgroup DMA2D_LL_CHROMA_SUB_SAMPLING Chroma Sub Sampling + * @{ + */ +#define LL_DMA2D_CSS_444 0x00000000U /*!< No chroma sub-sampling 4:4:4 */ +#define LL_DMA2D_CSS_422 DMA2D_FGPFCCR_CSS_0 /*!< chroma sub-sampling 4:2:2 */ +#define LL_DMA2D_CSS_420 DMA2D_FGPFCCR_CSS_1 /*!< chroma sub-sampling 4:2:0 */ +/** + * @} + */ +#endif /* DMA2D_FGPFCCR_CSS */ /** * @} @@ -566,7 +588,7 @@ __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL); } @@ -603,7 +625,7 @@ __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL); } @@ -628,7 +650,7 @@ __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL); } @@ -663,7 +685,7 @@ __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode) * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG */ -__STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE)); } @@ -696,7 +718,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM)); } @@ -723,7 +745,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_ * @arg @ref LL_DMA2D_RB_MODE_REGULAR * @arg @ref LL_DMA2D_RB_MODE_SWAP */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS)); } @@ -750,7 +772,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint3 * @arg @ref LL_DMA2D_ALPHA_REGULAR * @arg @ref LL_DMA2D_ALPHA_INVERTED */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI)); } @@ -778,7 +800,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB)); } @@ -805,7 +827,7 @@ __STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES */ -__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM)); } @@ -828,7 +850,7 @@ __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t Line * @param DMA2Dx DMA2D Instance * @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO)); } @@ -851,7 +873,7 @@ __STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint * @param DMA2Dx DMA2D Instance * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos); } @@ -874,7 +896,7 @@ __STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrO * @param DMA2Dx DMA2D Instance * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL)); } @@ -897,7 +919,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t O * @param DMA2Dx DMA2D Instance * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR)); } @@ -934,7 +956,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t Out * @param DMA2Dx DMA2D Instance * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \ (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1))); @@ -958,7 +980,7 @@ __STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t L * @param DMA2Dx DMA2D Instance * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW)); } @@ -981,7 +1003,7 @@ __STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTi * @param DMA2Dx DMA2D Instance * @retval Dead time value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos); } @@ -1014,7 +1036,7 @@ __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL); } @@ -1041,7 +1063,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t Me * @param DMA2Dx DMA2D Instance * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR)); } @@ -1063,7 +1085,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL); } @@ -1108,7 +1130,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_INPUT_MODE_A8 * @arg @ref LL_DMA2D_INPUT_MODE_A4 */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM)); } @@ -1137,7 +1159,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM)); } @@ -1160,7 +1182,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alph * @param DMA2Dx DMA2D Instance * @retval Alpha value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos); } @@ -1187,7 +1209,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_RB_MODE_REGULAR * @arg @ref LL_DMA2D_RB_MODE_SWAP */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS)); } @@ -1214,7 +1236,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32 * @arg @ref LL_DMA2D_ALPHA_REGULAR * @arg @ref LL_DMA2D_ALPHA_INVERTED */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI)); } @@ -1237,7 +1259,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO)); } @@ -1277,7 +1299,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t R * @param DMA2Dx DMA2D Instance * @retval Red color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos); } @@ -1300,7 +1322,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Green color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos); } @@ -1323,7 +1345,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Blue color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE)); } @@ -1346,7 +1368,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_ * @param DMA2Dx DMA2D Instance * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR)); } @@ -1369,7 +1391,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t C * @param DMA2Dx DMA2D Instance * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos); } @@ -1396,11 +1418,41 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint3 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM)); } +#if defined(DMA2D_FGPFCCR_CSS) +/** + * @brief Set DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode). + * @rmtoll FGPFCCR CSS LL_DMA2D_FGND_SetChrSubSampling + * @param DMA2Dx DMA2D Instance + * @param ChromaSubSampling This parameter can be one of the following values: + * @arg @ref LL_DMA2D_CSS_444 + * @arg @ref LL_DMA2D_CSS_422 + * @arg @ref LL_DMA2D_CSS_420 + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetChrSubSampling(DMA2D_TypeDef *DMA2Dx, uint32_t ChromaSubSampling) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS, ChromaSubSampling); +} + +/** + * @brief Return DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode). + * @rmtoll FGPFCCR CSS LL_DMA2D_FGND_GetChrSubSampling + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_CSS_444 + * @arg @ref LL_DMA2D_CSS_422 + * @arg @ref LL_DMA2D_CSS_420 + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS)); +} +#endif /* DMA2D_FGPFCCR_CSS */ /** * @} */ @@ -1427,7 +1479,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t Me * @param DMA2Dx DMA2D Instance * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR)); } @@ -1449,7 +1501,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL); } @@ -1494,7 +1546,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_INPUT_MODE_A8 * @arg @ref LL_DMA2D_INPUT_MODE_A4 */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM)); } @@ -1523,7 +1575,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM)); } @@ -1546,7 +1598,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alph * @param DMA2Dx DMA2D Instance * @retval Alpha value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos); } @@ -1573,7 +1625,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_RB_MODE_REGULAR * @arg @ref LL_DMA2D_RB_MODE_SWAP */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS)); } @@ -1600,7 +1652,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32 * @arg @ref LL_DMA2D_ALPHA_REGULAR * @arg @ref LL_DMA2D_ALPHA_INVERTED */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI)); } @@ -1623,7 +1675,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO)); } @@ -1663,7 +1715,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t R * @param DMA2Dx DMA2D Instance * @retval Red color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos); } @@ -1686,7 +1738,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Green color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos); } @@ -1709,7 +1761,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Blue color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE)); } @@ -1732,7 +1784,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_ * @param DMA2Dx DMA2D Instance * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR)); } @@ -1755,7 +1807,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t C * @param DMA2Dx DMA2D Instance * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos); } @@ -1782,7 +1834,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint3 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM)); } @@ -1806,7 +1858,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL); } @@ -1817,7 +1869,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL); } @@ -1828,7 +1880,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL); } @@ -1839,7 +1891,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL); } @@ -1850,7 +1902,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL); } @@ -1861,7 +1913,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL); } @@ -2078,7 +2130,7 @@ __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL); } @@ -2089,7 +2141,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL); } @@ -2100,7 +2152,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL); } @@ -2111,7 +2163,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL); } @@ -2122,7 +2174,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL); } @@ -2133,7 +2185,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL); } @@ -2149,16 +2201,16 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx) * @{ */ -ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx); +ErrorStatus LL_DMA2D_DeInit(const DMA2D_TypeDef *DMA2Dx); ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct); void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct); void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx); void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg); void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct); -uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); -uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); -uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); -uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputBlueColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputGreenColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputRedColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputAlphaColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines); /** @@ -2185,4 +2237,3 @@ void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t Nb #endif #endif /* STM32U5xx_LL_DMA2D_H */ - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_exti.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_exti.c index 7ca507356c8..07067fe319b 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_exti.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_exti.c @@ -79,7 +79,7 @@ ErrorStatus LL_EXTI_DeInit(void) { /* Interrupt mask register set to default reset values */ - LL_EXTI_WriteReg(IMR1, 0xFF9E0000U); + LL_EXTI_WriteReg(IMR1, 0x00000000U); /* Event mask register set to default reset values */ LL_EXTI_WriteReg(EMR1, 0x00000000U); /* Rising Trigger selection register set to default reset values */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_exti.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_exti.h index 7101af1332c..bbceea0dffe 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_exti.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_exti.h @@ -103,12 +103,25 @@ typedef struct #define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */ #define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */ #define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */ +#if defined(EXTI_IMR1_IM18) #define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */ +#endif /* EXTI_IMR1_IM18 */ #define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */ #define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */ #define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */ #define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */ -#define LL_EXTI_LINE_ALL_0_31 0x007FFFFFU /*!< ALL Extended line */ +#define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */ +#if defined(EXTI_IMR1_IM24) +#define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */ +#endif /* EXTI_IMR1_IM24 */ +#if defined(EXTI_IMR1_IM25) +#define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */ +#endif /* EXTI_IMR1_IM25 */ +#if defined(EXTI_IMR1_IM24) && defined(EXTI_IMR1_IM25) +#define LL_EXTI_LINE_ALL_0_31 0x03FFFFFFU /*!< ALL Extended line */ +#else +#define LL_EXTI_LINE_ALL_0_31 0x00FFFFFFU /*!< ALL Extended line */ +#endif /* defined(EXTI_IMR1_IM24) && defined(EXTI_IMR1_IM25) */ #if defined(USE_FULL_LL_DRIVER) #define LL_EXTI_LINE_NONE 0x00000000U /*!< None Extended line */ @@ -122,10 +135,17 @@ typedef struct #define LL_EXTI_EXTI_PORTC EXTI_EXTICR1_EXTI0_1 /*!< EXTI PORT C */ #define LL_EXTI_EXTI_PORTD (EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT D */ #define LL_EXTI_EXTI_PORTE EXTI_EXTICR1_EXTI0_2 /*!< EXTI PORT E */ +#if defined(GPIOF) #define LL_EXTI_EXTI_PORTF (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT F */ +#endif /* GPIOF */ #define LL_EXTI_EXTI_PORTG (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_1) /*!< EXTI PORT G */ #define LL_EXTI_EXTI_PORTH (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT H */ +#if defined(GPIOI) #define LL_EXTI_EXTI_PORTI EXTI_EXTICR1_EXTI0_3 /*!< EXTI PORT I */ +#endif /* GPIOI */ +#if defined(GPIOJ) +#define LL_EXTI_EXTI_PORTJ (EXTI_EXTICR1_EXTI0_3 | EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT J */ +#endif /* GPIOJ */ /** * @} @@ -260,6 +280,9 @@ typedef struct * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval None @@ -299,6 +322,9 @@ __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval None @@ -338,6 +364,9 @@ __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). @@ -382,6 +411,9 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval None @@ -419,6 +451,9 @@ __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval None @@ -455,6 +490,9 @@ __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). @@ -507,6 +545,9 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -549,6 +590,9 @@ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -585,6 +629,9 @@ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -635,6 +682,9 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -676,6 +726,9 @@ __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -711,6 +764,9 @@ __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -759,6 +815,9 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -804,6 +863,9 @@ __STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -841,6 +903,9 @@ __STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @note Please check each device line mapping for EXTI Line availability * @retval @note This bit is set when the selected edge event arrives on the interrupt */ @@ -878,6 +943,9 @@ __STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -915,6 +983,9 @@ __STATIC_INLINE void LL_EXTI_ClearFallingFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -952,6 +1023,9 @@ __STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @note Please check each device line mapping for EXTI Line availability * @retval @note This bit is set when the selected edge event arrives on the interrupt */ @@ -989,6 +1063,9 @@ __STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -1028,10 +1105,11 @@ __STATIC_INLINE void LL_EXTI_ClearRisingFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_EXTI_PORTC * @arg @ref LL_EXTI_EXTI_PORTD * @arg @ref LL_EXTI_EXTI_PORTE - * @arg @ref LL_EXTI_EXTI_PORTF + * @arg @ref LL_EXTI_EXTI_PORTF (*) * @arg @ref LL_EXTI_EXTI_PORTG * @arg @ref LL_EXTI_EXTI_PORTH - * @arg @ref LL_EXTI_EXTI_PORTI + * @arg @ref LL_EXTI_EXTI_PORTI (*) + * @arg @ref LL_EXTI_EXTI_PORTJ (*) * * (*) value not defined in all devices * @param Line This parameter can be one of the following values: @@ -1100,10 +1178,13 @@ __STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line) * @arg @ref LL_EXTI_EXTI_PORTC * @arg @ref LL_EXTI_EXTI_PORTD * @arg @ref LL_EXTI_EXTI_PORTE - * @arg @ref LL_EXTI_EXTI_PORTF + * @arg @ref LL_EXTI_EXTI_PORTF (*) * @arg @ref LL_EXTI_EXTI_PORTG * @arg @ref LL_EXTI_EXTI_PORTH - * @arg @ref LL_EXTI_EXTI_PORTI + * @arg @ref LL_EXTI_EXTI_PORTI (*) + * @arg @ref LL_EXTI_EXTI_PORTJ (*) + * + * (*) value not defined in all devices */ __STATIC_INLINE uint32_t LL_EXTI_GetEXTISource(uint32_t Line) { @@ -1148,6 +1229,9 @@ __STATIC_INLINE uint32_t LL_EXTI_GetEXTISource(uint32_t Line) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval None @@ -1184,6 +1268,9 @@ __STATIC_INLINE void LL_EXTI_EnableSecure_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval None @@ -1222,6 +1309,9 @@ __STATIC_INLINE void LL_EXTI_DisableSecure_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). @@ -1266,6 +1356,9 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledSecure_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval None @@ -1302,6 +1395,9 @@ __STATIC_INLINE void LL_EXTI_EnablePrivilege_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval None @@ -1338,6 +1434,9 @@ __STATIC_INLINE void LL_EXTI_DisablePrivilege_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 (*) + * @arg @ref LL_EXTI_LINE_25 (*) * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). @@ -1347,6 +1446,28 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledPrivilege_0_31(uint32_t ExtiLine) return ((READ_BIT(EXTI->PRIVCFGR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock the secure and privilege configuration registers. + * @rmtoll LOCKR LOCK LL_EXTI_LockAttributes + * @retval None + */ +__STATIC_INLINE void LL_EXTI_LockAttributes(void) +{ + SET_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK); +} + +/** + * @brief Return the secure and privilege configuration registers LOCK status + * @rmtoll LOCKR LOCK LL_EXTI_GetLockAttributes + * @retval 1 if the secure and privilege configuration registers have been locked else 0. + */ +__STATIC_INLINE uint32_t LL_EXTI_GetLockAttributes(void) +{ + return READ_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK); +} +#endif /* __ARM_FEATURE_CMSE */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_fmac.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_fmac.c index ecef33c58e6..efc43f5848d 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_fmac.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_fmac.c @@ -90,7 +90,7 @@ ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx) * - SUCCESS: FMAC registers are de-initialized * - ERROR: FMAC registers are not de-initialized */ -ErrorStatus LL_FMAC_DeInit(FMAC_TypeDef *FMACx) +ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx) { ErrorStatus status = SUCCESS; diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_fmac.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_fmac.h index 5e5d868454b..970aeb93872 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_fmac.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_fmac.h @@ -48,11 +48,12 @@ extern "C" { * @brief Flag defines which can be used with LL_FMAC_ReadReg function * @{ */ -#define LL_FMAC_SR_SAT FMAC_SR_SAT /*!< Saturation Error Flag (this helps in debugging a filter) */ -#define LL_FMAC_SR_UNFL FMAC_SR_UNFL /*!< Underflow Error Flag */ -#define LL_FMAC_SR_OVFL FMAC_SR_OVFL /*!< Overflow Error Flag */ -#define LL_FMAC_SR_X1FULL FMAC_SR_X1FULL /*!< X1 Buffer Full Flag */ -#define LL_FMAC_SR_YEMPTY FMAC_SR_YEMPTY /*!< Y Buffer Empty Flag */ +#define LL_FMAC_SR_SAT FMAC_SR_SAT /*!< Saturation Error Flag + (this helps in debugging a filter) */ +#define LL_FMAC_SR_UNFL FMAC_SR_UNFL /*!< Underflow Error Flag */ +#define LL_FMAC_SR_OVFL FMAC_SR_OVFL /*!< Overflow Error Flag */ +#define LL_FMAC_SR_X1FULL FMAC_SR_X1FULL /*!< X1 Buffer Full Flag */ +#define LL_FMAC_SR_YEMPTY FMAC_SR_YEMPTY /*!< Y Buffer Empty Flag */ /** * @} */ @@ -61,11 +62,12 @@ extern "C" { * @brief IT defines which can be used with LL_FMAC_ReadReg and LL_FMAC_WriteReg functions * @{ */ -#define LL_FMAC_CR_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable (this helps in debugging a filter) */ -#define LL_FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */ -#define LL_FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */ -#define LL_FMAC_CR_WIEN FMAC_CR_WIEN /*!< Write Interrupt Enable */ -#define LL_FMAC_CR_RIEN FMAC_CR_RIEN /*!< Read Interrupt Enable */ +#define LL_FMAC_CR_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable + (this helps in debugging a filter) */ +#define LL_FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */ +#define LL_FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */ +#define LL_FMAC_CR_WIEN FMAC_CR_WIEN /*!< Write Interrupt Enable */ +#define LL_FMAC_CR_RIEN FMAC_CR_RIEN /*!< Read Interrupt Enable */ /** * @} */ @@ -74,10 +76,14 @@ extern "C" { * @brief Watermark defines that can be used for buffer full (input) or buffer empty (output) * @{ */ -#define LL_FMAC_WM_0_THRESHOLD_1 0x00000000U /*!< Buffer full/empty flag set if there is less than 1 free/unread space. */ -#define LL_FMAC_WM_1_THRESHOLD_2 0x01000000U /*!< Buffer full/empty flag set if there are less than 2 free/unread spaces. */ -#define LL_FMAC_WM_2_THRESHOLD_4 0x02000000U /*!< Buffer full/empty flag set if there are less than 4 free/unread spaces. */ -#define LL_FMAC_WM_3_THRESHOLD_8 0x03000000U /*!< Buffer full/empty flag set if there are less than 8 free/empty spaces. */ +#define LL_FMAC_WM_0_THRESHOLD_1 0x00000000U /*!< Buffer full/empty flag set if there + is less than 1 free/unread space. */ +#define LL_FMAC_WM_1_THRESHOLD_2 0x01000000U /*!< Buffer full/empty flag set if there + are less than 2 free/unread spaces. */ +#define LL_FMAC_WM_2_THRESHOLD_4 0x02000000U /*!< Buffer full/empty flag set if there + are less than 4 free/unread spaces. */ +#define LL_FMAC_WM_3_THRESHOLD_8 0x03000000U /*!< Buffer full/empty flag set if there + are less than 8 free/empty spaces. */ /** * @} */ @@ -85,11 +91,11 @@ extern "C" { /** @defgroup FMAC_LL_EC_FUNC FMAC functions * @{ */ -#define LL_FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */ -#define LL_FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */ -#define LL_FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */ -#define LL_FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */ -#define LL_FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */ +#define LL_FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */ +#define LL_FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */ +#define LL_FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */ +#define LL_FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */ +#define LL_FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */ /** * @} */ @@ -97,8 +103,8 @@ extern "C" { /** @defgroup FMAC_LL_EC_PROCESSING FMAC processing * @{ */ -#define LL_FMAC_PROCESSING_STOP 0x00U /*!< Stop FMAC Processing */ -#define LL_FMAC_PROCESSING_START 0x01U /*!< Start FMAC Processing */ +#define LL_FMAC_PROCESSING_STOP 0x00U /*!< Stop FMAC Processing */ +#define LL_FMAC_PROCESSING_START 0x01U /*!< Start FMAC Processing */ /** * @} */ @@ -178,7 +184,7 @@ __STATIC_INLINE void LL_FMAC_SetX1FullWatermark(FMAC_TypeDef *FMACx, uint32_t Wa * @arg @ref LL_FMAC_WM_2_THRESHOLD_4 * @arg @ref LL_FMAC_WM_3_THRESHOLD_8 */ -__STATIC_INLINE uint32_t LL_FMAC_GetX1FullWatermark(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_GetX1FullWatermark(const FMAC_TypeDef *FMACx) { return (uint32_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM)); } @@ -203,7 +209,7 @@ __STATIC_INLINE void LL_FMAC_SetX1BufferSize(FMAC_TypeDef *FMACx, uint8_t Buffer * @retval uint8_t Number of 16-bit words allocated to the input buffer * (including the optional "headroom") (value between Min_Data=0x01 and Max_Data=0xFF). */ -__STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(const FMAC_TypeDef *FMACx) { return (uint8_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BUF_SIZE) >> FMAC_X1BUFCFG_X1_BUF_SIZE_Pos); } @@ -228,7 +234,7 @@ __STATIC_INLINE void LL_FMAC_SetX1Base(FMAC_TypeDef *FMACx, uint8_t Base) * @retval uint8_t Base address of the input buffer (X1) within the internal memory * (value between Min_Data=0x00 and Max_Data=0xFF). */ -__STATIC_INLINE uint8_t LL_FMAC_GetX1Base(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint8_t LL_FMAC_GetX1Base(const FMAC_TypeDef *FMACx) { return (uint8_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BASE) >> FMAC_X1BUFCFG_X1_BASE_Pos); } @@ -253,7 +259,7 @@ __STATIC_INLINE void LL_FMAC_SetX2BufferSize(FMAC_TypeDef *FMACx, uint8_t Buffer * @retval uint8_t Number of 16-bit words allocated to the coefficient buffer * (value between Min_Data=0x01 and Max_Data=0xFF). */ -__STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(const FMAC_TypeDef *FMACx) { return (uint8_t)(READ_BIT(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BUF_SIZE) >> FMAC_X2BUFCFG_X2_BUF_SIZE_Pos); } @@ -278,7 +284,7 @@ __STATIC_INLINE void LL_FMAC_SetX2Base(FMAC_TypeDef *FMACx, uint8_t Base) * @retval uint8_t Base address of the coefficient buffer (X2) within the internal memory * (value between Min_Data=0x00 and Max_Data=0xFF). */ -__STATIC_INLINE uint8_t LL_FMAC_GetX2Base(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint8_t LL_FMAC_GetX2Base(const FMAC_TypeDef *FMACx) { return (uint8_t)(READ_BIT(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE) >> FMAC_X2BUFCFG_X2_BASE_Pos); } @@ -309,7 +315,7 @@ __STATIC_INLINE void LL_FMAC_SetYEmptyWatermark(FMAC_TypeDef *FMACx, uint32_t Wa * @arg @ref LL_FMAC_WM_2_THRESHOLD_4 * @arg @ref LL_FMAC_WM_3_THRESHOLD_8 */ -__STATIC_INLINE uint32_t LL_FMAC_GetYEmptyWatermark(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_GetYEmptyWatermark(const FMAC_TypeDef *FMACx) { return (uint32_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM)); } @@ -334,7 +340,7 @@ __STATIC_INLINE void LL_FMAC_SetYBufferSize(FMAC_TypeDef *FMACx, uint8_t BufferS * @retval uint8_t Number of 16-bit words allocated to the output buffer * (including the optional "headroom" - value between Min_Data=0x01 and Max_Data=0xFF). */ -__STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(const FMAC_TypeDef *FMACx) { return (uint8_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BUF_SIZE) >> FMAC_YBUFCFG_Y_BUF_SIZE_Pos); } @@ -359,7 +365,7 @@ __STATIC_INLINE void LL_FMAC_SetYBase(FMAC_TypeDef *FMACx, uint8_t Base) * @retval uint8_t Base address of the output buffer (Y) within the internal memory * (value between Min_Data=0x00 and Max_Data=0xFF). */ -__STATIC_INLINE uint8_t LL_FMAC_GetYBase(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint8_t LL_FMAC_GetYBase(const FMAC_TypeDef *FMACx) { return (uint8_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BASE) >> FMAC_YBUFCFG_Y_BASE_Pos); } @@ -392,7 +398,7 @@ __STATIC_INLINE void LL_FMAC_DisableStart(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsEnabledStart(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsEnabledStart(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->PARAM, FMAC_PARAM_START) == (FMAC_PARAM_START)) ? 1UL : 0UL); } @@ -425,7 +431,7 @@ __STATIC_INLINE void LL_FMAC_SetFunction(FMAC_TypeDef *FMACx, uint32_t Function) * @arg @ref LL_FMAC_FUNC_CONVO_FIR * @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1 */ -__STATIC_INLINE uint32_t LL_FMAC_GetFunction(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_GetFunction(const FMAC_TypeDef *FMACx) { return (uint32_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_FUNC)); } @@ -449,7 +455,7 @@ __STATIC_INLINE void LL_FMAC_SetParamR(FMAC_TypeDef *FMACx, uint8_t Param) * @param FMACx FMAC instance * @retval uint8_t Parameter R (gain, etc.) (value between Min_Data=0x00 and Max_Data=0xFF). */ -__STATIC_INLINE uint8_t LL_FMAC_GetParamR(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint8_t LL_FMAC_GetParamR(const FMAC_TypeDef *FMACx) { return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_R) >> FMAC_PARAM_R_Pos); } @@ -473,7 +479,7 @@ __STATIC_INLINE void LL_FMAC_SetParamQ(FMAC_TypeDef *FMACx, uint8_t Param) * @param FMACx FMAC instance * @retval uint8_t Parameter Q (vector length, etc.) (value between Min_Data=0x00 and Max_Data=0xFF). */ -__STATIC_INLINE uint8_t LL_FMAC_GetParamQ(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint8_t LL_FMAC_GetParamQ(const FMAC_TypeDef *FMACx) { return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_Q) >> FMAC_PARAM_Q_Pos); } @@ -498,7 +504,7 @@ __STATIC_INLINE void LL_FMAC_SetParamP(FMAC_TypeDef *FMACx, uint8_t Param) * @retval uint8_t Parameter P (vector length, number of filter taps, etc.) * (value between Min_Data=0x00 and Max_Data=0xFF). */ -__STATIC_INLINE uint8_t LL_FMAC_GetParamP(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint8_t LL_FMAC_GetParamP(const FMAC_TypeDef *FMACx) { return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_P)); } @@ -528,7 +534,7 @@ __STATIC_INLINE void LL_FMAC_EnableReset(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsEnabledReset(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsEnabledReset(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->CR, FMAC_CR_RESET) == (FMAC_CR_RESET)) ? 1UL : 0UL); } @@ -569,7 +575,7 @@ __STATIC_INLINE void LL_FMAC_DisableClipping(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsEnabledClipping(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsEnabledClipping(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->CR, FMAC_CR_CLIPEN) == (FMAC_CR_CLIPEN)) ? 1UL : 0UL); } @@ -610,7 +616,7 @@ __STATIC_INLINE void LL_FMAC_DisableDMAReq_WRITE(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_WRITE(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_WRITE(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->CR, FMAC_CR_DMAWEN) == (FMAC_CR_DMAWEN)) ? 1UL : 0UL); } @@ -643,7 +649,7 @@ __STATIC_INLINE void LL_FMAC_DisableDMAReq_READ(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_READ(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_READ(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->CR, FMAC_CR_DMAREN) == (FMAC_CR_DMAREN)) ? 1UL : 0UL); } @@ -684,7 +690,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_SAT(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_SAT(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_SAT(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->CR, FMAC_CR_SATIEN) == (FMAC_CR_SATIEN)) ? 1UL : 0UL); } @@ -717,7 +723,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_UNFL(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_UNFL(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_UNFL(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->CR, FMAC_CR_UNFLIEN) == (FMAC_CR_UNFLIEN)) ? 1UL : 0UL); } @@ -750,7 +756,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_OVFL(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_OVFL(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_OVFL(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->CR, FMAC_CR_OVFLIEN) == (FMAC_CR_OVFLIEN)) ? 1UL : 0UL); } @@ -783,7 +789,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_WR(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_WR(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_WR(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->CR, FMAC_CR_WIEN) == (FMAC_CR_WIEN)) ? 1UL : 0UL); } @@ -816,7 +822,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_RD(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->CR, FMAC_CR_RIEN) == (FMAC_CR_RIEN)) ? 1UL : 0UL); } @@ -835,7 +841,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->SR, FMAC_SR_SAT) == (FMAC_SR_SAT)) ? 1UL : 0UL); } @@ -846,7 +852,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->SR, FMAC_SR_UNFL) == (FMAC_SR_UNFL)) ? 1UL : 0UL); } @@ -857,7 +863,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->SR, FMAC_SR_OVFL) == (FMAC_SR_OVFL)) ? 1UL : 0UL); } @@ -868,7 +874,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->SR, FMAC_SR_X1FULL) == (FMAC_SR_X1FULL)) ? 1UL : 0UL); } @@ -879,7 +885,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(FMAC_TypeDef *FMACx) * @param FMACx FMAC instance * @retval uint32_t State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_YEMPTY(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_YEMPTY(const FMAC_TypeDef *FMACx) { return ((READ_BIT(FMACx->SR, FMAC_SR_YEMPTY) == (FMAC_SR_YEMPTY)) ? 1UL : 0UL); } @@ -911,7 +917,7 @@ __STATIC_INLINE void LL_FMAC_WriteData(FMAC_TypeDef *FMACx, uint16_t InData) * @param FMACx FMAC instance * @retval uint16_t 16-bit output data of FMAC processing (value between Min_Data=0x0000 and Max_Data=0xFFFF). */ -__STATIC_INLINE uint16_t LL_FMAC_ReadData(FMAC_TypeDef *FMACx) +__STATIC_INLINE uint16_t LL_FMAC_ReadData(const FMAC_TypeDef *FMACx) { return (uint16_t)(READ_REG(FMACx->RDATA)); } @@ -1034,7 +1040,7 @@ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint * @{ */ ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx); -ErrorStatus LL_FMAC_DeInit(FMAC_TypeDef *FMACx); +ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx); /** diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_fmc.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_fmc.c index 9605fab35b3..9f6b93e1932 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_fmc.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_fmc.c @@ -795,4 +795,3 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui /** * @} */ - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_fmc.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_fmc.h index 5054924d143..489c3047198 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_fmc.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_fmc.h @@ -479,11 +479,13 @@ typedef struct * @} */ +#if defined(FMC_BCR1_WFDIS) /** @defgroup FMC_Write_FIFO FMC Write FIFO * @{ */ #define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS #define FMC_WRITE_FIFO_ENABLE (0x00000000U) +#endif /* FMC_BCR1_WFDIS */ /** * @} */ @@ -828,4 +830,3 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u #endif #endif /* STM32U5xx_LL_FMC_H */ - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_gpio.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_gpio.c index 787238f5174..11d9c1917f3 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_gpio.c @@ -31,7 +31,7 @@ */ #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || \ - defined (GPIOG) || defined (GPIOH) || defined (GPIOI) + defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) /** @addtogroup GPIO_LL * @{ @@ -101,7 +101,7 @@ * - SUCCESS: GPIO registers are de-initialized * - ERROR: Wrong GPIO Port */ -ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) +ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx) { ErrorStatus status = SUCCESS; @@ -166,6 +166,13 @@ ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOI); } #endif /* GPIOI */ +#if defined(GPIOJ) + else if (GPIOx == GPIOJ) + { + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOJ); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOJ); + } +#endif /* GPIOJ */ else { status = ERROR; @@ -206,9 +213,6 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru if (currentpin != 0U) { - /* Pin Mode configuration */ - LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) { /* Check Speed mode parameters */ @@ -216,6 +220,12 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru /* Speed mode configuration */ LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); + + /* Check Output mode parameters */ + assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + + /* Output mode configuration*/ + LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); } /* Pull-up Pull down resistor configuration*/ @@ -236,19 +246,12 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); } } + + /* Pin Mode configuration */ + LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); } pinpos++; } - - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) - { - /* Check Output mode parameters */ - assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); - - /* Output mode configuration*/ - LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); - - } return (SUCCESS); } @@ -283,7 +286,7 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) */ #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || \ - defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) */ + defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_gpio.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_gpio.h index d19a9861b61..65e5f608f15 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_gpio.h @@ -32,7 +32,7 @@ extern "C" { */ #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || \ - defined (GPIOG) || defined (GPIOH) || defined (GPIOI) + defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) /** @defgroup GPIO_LL GPIO * @{ @@ -314,7 +314,7 @@ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 * @arg @ref LL_GPIO_MODE_ALTERNATE * @arg @ref LL_GPIO_MODE_ANALOG */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); @@ -383,7 +383,7 @@ __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinM * @arg @ref LL_GPIO_OUTPUT_PUSHPULL * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin)); } @@ -457,7 +457,7 @@ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint * @arg @ref LL_GPIO_SPEED_FREQ_HIGH * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); @@ -523,7 +523,7 @@ __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 * @arg @ref LL_GPIO_PULL_UP * @arg @ref LL_GPIO_PULL_DOWN */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); @@ -600,7 +600,7 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uin * @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_15 */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); @@ -678,7 +678,7 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, ui * @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_15 */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U)); @@ -748,7 +748,7 @@ __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -759,7 +759,7 @@ __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMa * @param GPIOx GPIO Port * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(const GPIO_TypeDef *GPIOx) { return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); } @@ -778,7 +778,7 @@ __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) * @param GPIOx GPIO Port * @retval Input data register value of port */ -__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(const GPIO_TypeDef *GPIOx) { return (uint32_t)(READ_REG(GPIOx->IDR)); } @@ -807,7 +807,7 @@ __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -817,6 +817,7 @@ __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t Pin * @rmtoll ODR ODy LL_GPIO_WriteOutputPort * @param GPIOx GPIO Port * @param PortValue Level value for each pin of the port + * Value between 0 and 0xFFFF * @retval None */ __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) @@ -830,7 +831,7 @@ __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortV * @param GPIOx GPIO Port * @retval Output data register value of port */ -__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(const GPIO_TypeDef *GPIOx) { return (uint32_t)(READ_REG(GPIOx->ODR)); } @@ -859,7 +860,7 @@ __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -1041,7 +1042,7 @@ __STATIC_INLINE void LL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uin * @arg @ref LL_GPIO_PIN_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsEnabledHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsEnabledHighSPeedLowVoltage(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->HSLVR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -1133,7 +1134,7 @@ __STATIC_INLINE void LL_GPIO_DisablePinSecure(GPIO_TypeDef *GPIOx, uint32_t PinM * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsEnabledPinSecure(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsEnabledPinSecure(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->SECCFGR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -1148,7 +1149,7 @@ __STATIC_INLINE uint32_t LL_GPIO_IsEnabledPinSecure(GPIO_TypeDef *GPIOx, uint32_ * @{ */ -ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx); ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); @@ -1166,7 +1167,7 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); */ #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || \ - defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) */ + defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ)*/ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_i2c.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_i2c.c index a00108a80c2..22d3ad89703 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_i2c.c @@ -30,7 +30,7 @@ * @{ */ -#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4) +#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4) || defined (I2C5) || defined (I2C6) /** @defgroup I2C_LL I2C * @{ @@ -83,7 +83,7 @@ * - SUCCESS: I2C registers are de-initialized * - ERROR: I2C registers are not de-initialized */ -ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx) +ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx) { ErrorStatus status = SUCCESS; @@ -123,6 +123,26 @@ ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx) /* Release reset of I2C clock */ LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_I2C4); } +#if defined(I2C5) + else if (I2Cx == I2C5) + { + /* Force reset of I2C clock */ + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_I2C5); + + /* Release reset of I2C clock */ + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_I2C5); + } +#endif /* I2C5 */ +#if defined(I2C6) + else if (I2Cx == I2C6) + { + /* Force reset of I2C clock */ + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_I2C6); + + /* Release reset of I2C clock */ + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_I2C6); + } +#endif /* I2C6 */ else { status = ERROR; @@ -139,7 +159,7 @@ ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx) * - SUCCESS: I2C registers are initialized * - ERROR: Not applicable */ -ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct) +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct) { /* Check the I2C Instance I2Cx */ assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); @@ -231,7 +251,7 @@ void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct) * @} */ -#endif /* I2C1 || I2C2 || I2C3 || I2C4 */ +#endif /* I2C1 || I2C2 || I2C3 || I2C4 || I2C5 || I2C6 */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_i2c.h index c8c073a48d3..95125c7da53 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_i2c.h @@ -31,7 +31,7 @@ extern "C" { * @{ */ -#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4) +#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4) || defined (I2C5) || defined (I2C6) /** @defgroup I2C_LL I2C * @{ @@ -52,11 +52,9 @@ extern "C" { /** @defgroup I2C_LL_Private_Macros I2C Private Macros * @{ */ -#define IS_LL_I2C_GRP1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) ||\ - ((__INSTANCE__) == I2C2) ||\ - ((__INSTANCE__) == I2C4)) +#define IS_LL_I2C_GRP1_INSTANCE(__INSTANCE__) IS_I2C_GRP1_INSTANCE(__INSTANCE__) -#define IS_LL_I2C_GRP2_INSTANCE(__INSTANCE__) ((__INSTANCE__) == I2C3) +#define IS_LL_I2C_GRP2_INSTANCE(__INSTANCE__) IS_I2C_GRP2_INSTANCE(__INSTANCE__) /** * @} */ @@ -69,45 +67,45 @@ extern "C" { typedef struct { uint32_t PeripheralMode; /*!< Specifies the peripheral mode. - This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE + This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE. This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */ uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values. This parameter must be set by referring to the STM32CubeMX Tool and - the helper macro @ref __LL_I2C_CONVERT_TIMINGS() + the helper macro @ref __LL_I2C_CONVERT_TIMINGS(). This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */ uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. - This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION + This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION. This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ uint32_t DigitalFilter; /*!< Configures the digital noise filter. - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F. This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */ uint32_t OwnAddress1; /*!< Specifies the device own address 1. - This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF + This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF. This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. - This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE + This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE. This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */ uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). - This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1 + This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1. This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ @@ -262,22 +260,21 @@ typedef struct /** @defgroup I2C_LL_EC_MODE Transfer End Mode * @{ */ -/*!< Enable I2C Reload mode. */ -#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD -/*!< Enable I2C Automatic end mode with no HW PEC comparison. */ -#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND -/*!< Enable I2C Software end mode with no HW PEC comparison. */ -#define LL_I2C_MODE_SOFTEND 0x00000000U -/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD -/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND -/*!< Enable SMBUS Software end mode with HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND -/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ +#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */ +#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode + with no HW PEC comparison. */ +#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode + with no HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode + with HW PEC comparison. */ #define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) -/*!< Enable SMBUS Software end mode with HW PEC comparison. */ +/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ #define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) +/*!< Enable SMBUS Software end mode with HW PEC comparison. */ /** * @} */ @@ -285,22 +282,23 @@ typedef struct /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation * @{ */ -/*!< Don't Generate Stop and Start condition. */ #define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U -/*!< Generate Stop condition (Size should be set to 0). */ +/*!< Don't Generate Stop and Start condition. */ #define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) -/*!< Generate Start for read request. */ +/*!< Generate Stop condition (Size should be set to 0). */ #define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) -/*!< Generate Start for write request. */ +/*!< Generate Start for read request. */ #define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) -/*!< Generate Restart for read request, slave 7Bit address. */ +/*!< Generate Start for write request. */ #define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) -/*!< Generate Restart for write request, slave 7Bit address. */ +/*!< Generate Restart for read request, slave 7Bit address. */ #define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Restart for write request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \ + I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */ -#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) -/*!< Generate Restart for write request, slave 10Bit address.*/ #define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Restart for write request, slave 10Bit address.*/ /** * @} */ @@ -308,8 +306,10 @@ typedef struct /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction * @{ */ -#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */ -#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/ +#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, + slave enters receiver mode. */ +#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, + slave enters transmitter mode.*/ /** * @} */ @@ -317,8 +317,10 @@ typedef struct /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data * @{ */ -#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ -#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for + transmission */ +#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for + reception */ /** * @} */ @@ -326,10 +328,10 @@ typedef struct /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout * @{ */ -#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level - timeout. */ -#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA - high level timeout.*/ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect + SCL low level timeout. */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect + both SCL and SDA high level timeout.*/ /** * @} */ @@ -337,10 +339,12 @@ typedef struct /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection * @{ */ -#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ -#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */ +#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ +#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) + enable bit */ #define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \ - I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB enable bits */ + I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB +(extended clock) enable bits */ /** * @} */ @@ -349,58 +353,58 @@ typedef struct * @brief I2C Autonomous Trigger selection * @{ */ -#define LL_I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2 and I2C4 */ +#define LL_I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2, I2C4, I2C5, I2C6 (depends on Product) */ #define LL_I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ -/*!< HW Trigger signal is GPDMA_CH0_TRG */ #define LL_I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x00000000U)) -/*!< HW Trigger signal is GPDMA_CH1_TRG */ +/*!< HW Trigger signal is GPDMA_CH0_TRG */ #define LL_I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is GPDMA_CH2_TRG */ +/*!< HW Trigger signal is GPDMA_CH1_TRG */ #define LL_I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is GPDMA_CH3_TRG */ +/*!< HW Trigger signal is GPDMA_CH2_TRG */ #define LL_I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is EXTI5_TRG */ +/*!< HW Trigger signal is GPDMA_CH3_TRG */ #define LL_I2C_GRP1_EXTI5_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is EXTI9_TRG */ +/*!< HW Trigger signal is EXTI5_TRG */ #define LL_I2C_GRP1_EXTI9_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPTIM1_CH1_TRG */ +/*!< HW Trigger signal is EXTI9_TRG */ #define LL_I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPTIM2_CH1_TRG */ +/*!< HW Trigger signal is LPTIM1_CH1_TRG */ #define LL_I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is COMP1_TRG */ +/*!< HW Trigger signal is LPTIM2_CH1_TRG */ #define LL_I2C_GRP1_COMP1_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is COMP2_TRG */ +/*!< HW Trigger signal is COMP1_TRG */ #define LL_I2C_GRP1_COMP2_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is RTC_ALRA_TRG */ +/*!< HW Trigger signal is COMP2_TRG */ #define LL_I2C_GRP1_RTC_ALRA_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is RTC_WUT_TRG */ +/*!< HW Trigger signal is RTC_ALRA_TRG */ #define LL_I2C_GRP1_RTC_WUT_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_WUT_TRG */ -/*!< HW Trigger signal is LPDMA_CH0_TRG */ #define LL_I2C_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x00000000U)) -/*!< HW Trigger signal is LPDMA_CH1_TRG */ +/*!< HW Trigger signal is LPDMA_CH0_TRG */ #define LL_I2C_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPDMA_CH2_TRG */ +/*!< HW Trigger signal is LPDMA_CH1_TRG */ #define LL_I2C_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPDMA_CH3_TRG */ +/*!< HW Trigger signal is LPDMA_CH2_TRG */ #define LL_I2C_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is EXTI5_TRG */ +/*!< HW Trigger signal is LPDMA_CH3_TRG */ #define LL_I2C_GRP2_EXTI5_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is EXTI8_TRG */ +/*!< HW Trigger signal is EXTI5_TRG */ #define LL_I2C_GRP2_EXTI8_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPTIM1_CH1_TRG */ +/*!< HW Trigger signal is EXTI8_TRG */ #define LL_I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPTIM3_CH1_TRG */ +/*!< HW Trigger signal is LPTIM1_CH1_TRG */ #define LL_I2C_GRP2_LPTIM3_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is COMP1_TRG */ +/*!< HW Trigger signal is LPTIM3_CH1_TRG */ #define LL_I2C_GRP2_COMP1_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is COMP2_TRG */ +/*!< HW Trigger signal is COMP1_TRG */ #define LL_I2C_GRP2_COMP2_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is RTC_ALRA_TRG */ +/*!< HW Trigger signal is COMP2_TRG */ #define LL_I2C_GRP2_RTC_ALRA_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is RTC_WUT_TRG */ +/*!< HW Trigger signal is RTC_ALRA_TRG */ #define LL_I2C_GRP2_RTC_WUT_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_WUT_TRG */ /** * @} */ @@ -453,23 +457,23 @@ typedef struct */ /** * @brief Configure the SDA setup, hold time and the SCL high, low period. - * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. - * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. - (tscldel = (SCLDEL+1)xtpresc) - * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. - (tsdadel = SDADELxtpresc) - * @param __SCL_H_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. - (tsclh = (SCLH+1)xtpresc) - * @param __SCL_L_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. - (tscll = (SCLL+1)xtpresc) + * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tscldel = (SCLDEL+1)xtpresc) + * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tsdadel = SDADELxtpresc) + * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tsclh = (SCLH+1)xtpresc) + * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tscll = (SCLL+1)xtpresc) * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCL_H_PERIOD__, __SCL_L_PERIOD__) \ - ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ - (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ - (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ - (((uint32_t)(__SCL_H_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ - (((uint32_t)(__SCL_L_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) +#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \ + ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ + (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ + (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ + (((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ + (((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) /** * @} */ @@ -518,7 +522,7 @@ __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL); } @@ -534,7 +538,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) * @arg @ref LL_I2C_ANALOGFILTER_ENABLE * @arg @ref LL_I2C_ANALOGFILTER_DISABLE * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) - and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). * This parameter is used to configure the digital noise filter on SDA and SCL input. * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. * @retval None @@ -551,7 +555,7 @@ __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilt * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter * @param I2Cx I2C Instance. * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) - and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). * This parameter is used to configure the digital noise filter on SDA and SCL input. * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. * @retval None @@ -567,7 +571,7 @@ __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t Digital * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos); } @@ -602,7 +606,7 @@ __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL); } @@ -635,7 +639,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL); } @@ -668,7 +672,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL); } @@ -683,7 +687,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction) +__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction) { uint32_t data_reg_addr; @@ -731,7 +735,7 @@ __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL); } @@ -764,7 +768,7 @@ __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL); } @@ -804,7 +808,7 @@ __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL); } @@ -839,11 +843,112 @@ __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL); } +/** + * @brief Enable I2C Fast Mode Plus (FMP = 1). + * @note 20mA I/O drive enable + * @rmtoll CR1 FMP LL_I2C_EnableFastModePlus + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableFastModePlus(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_FMP); +} + +/** + * @brief Disable I2C Fast Mode Plus (FMP = 0). + * @note 20mA I/O drive disable + * @rmtoll CR1 FMP LL_I2C_DisableFastModePlus + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableFastModePlus(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_FMP); +} + +/** + * @brief Check if the I2C Fast Mode Plus is enabled or disabled. + * @rmtoll CR1 FMP LL_I2C_IsEnabledFastModePlus + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledFastModePlus(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_FMP) == (I2C_CR1_FMP)) ? 1UL : 0UL); +} + +/** + * @brief Enable automatic clear of ADDR flag. + * @rmtoll CR1 ADDRACLR LL_I2C_EnableAutoClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAutoClearFlag_ADDR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR); +} + +/** + * @brief Disable automatic clear of ADDR flag. + * @rmtoll CR1 ADDRACLR LL_I2C_DisableAutoClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAutoClearFlag_ADDR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR); +} + +/** + * @brief Check if the automatic clear of ADDR flag is enabled or disabled. + * @rmtoll CR1 ADDRACLR LL_I2C_IsEnabledAutoClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_ADDR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR) == (I2C_CR1_ADDRACLR)) ? 1UL : 0UL); +} + +/** + * @brief Enable automatic clear of STOP flag. + * @rmtoll CR1 STOPFACLR LL_I2C_EnableAutoClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAutoClearFlag_STOP(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR); +} + +/** + * @brief Disable automatic clear of STOP flag. + * @rmtoll CR1 STOPFACLR LL_I2C_DisableAutoClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAutoClearFlag_STOP(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR); +} + +/** + * @brief Check if the automatic clear of STOP flag is enabled or disabled. + * @rmtoll CR1 STOPFACLR LL_I2C_IsEnabledAutoClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_STOP(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR) == (I2C_CR1_STOPFACLR)) ? 1UL : 0UL); +} + /** * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode. * @note Changing this bit is not allowed, when the START bit is set. @@ -867,7 +972,7 @@ __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT */ -__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10)); } @@ -916,7 +1021,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL); } @@ -972,7 +1077,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL); } @@ -997,7 +1102,7 @@ __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos); } @@ -1008,7 +1113,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos); } @@ -1019,7 +1124,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos); } @@ -1030,7 +1135,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos); } @@ -1041,7 +1146,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos); } @@ -1078,7 +1183,7 @@ __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) * @arg @ref LL_I2C_MODE_SMBUS_DEVICE * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP */ -__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN)); } @@ -1127,7 +1232,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL); } @@ -1166,7 +1271,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL); } @@ -1217,7 +1322,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t Timeout * @param I2Cx I2C Instance. * @retval Value between Min_Data=0 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA)); } @@ -1249,7 +1354,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t Tim * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE)); } @@ -1277,7 +1382,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout * @param I2Cx I2C Instance. * @retval Value between Min_Data=0 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos); } @@ -1331,9 +1436,10 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout) { - return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL); + return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \ + (ClockTimeout)) ? 1UL : 0UL); } /** @@ -1372,7 +1478,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); } @@ -1405,7 +1511,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL); } @@ -1438,7 +1544,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL); } @@ -1471,7 +1577,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL); } @@ -1504,7 +1610,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL); } @@ -1543,7 +1649,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL); } @@ -1594,7 +1700,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); } @@ -1615,7 +1721,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL); } @@ -1628,7 +1734,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL); } @@ -1641,7 +1747,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL); } @@ -1654,7 +1760,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL); } @@ -1667,7 +1773,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL); } @@ -1680,7 +1786,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL); } @@ -1693,7 +1799,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL); } @@ -1706,7 +1812,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL); } @@ -1719,7 +1825,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL); } @@ -1732,7 +1838,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL); } @@ -1745,7 +1851,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL); } @@ -1760,7 +1866,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL); } @@ -1775,7 +1881,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL); } @@ -1791,7 +1897,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL); } @@ -1804,7 +1910,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL); } @@ -1965,7 +2071,7 @@ __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL); } @@ -2000,7 +2106,7 @@ __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL); } @@ -2024,7 +2130,7 @@ __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t Transfer * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos); } @@ -2101,7 +2207,7 @@ __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL); } @@ -2129,7 +2235,7 @@ __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t Trans * @arg @ref LL_I2C_REQUEST_WRITE * @arg @ref LL_I2C_REQUEST_READ */ -__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN)); } @@ -2153,7 +2259,7 @@ __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0x3F */ -__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD)); } @@ -2201,7 +2307,8 @@ __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr { MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | - I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, + I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | + I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request); } @@ -2215,7 +2322,7 @@ __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr * @arg @ref LL_I2C_DIRECTION_WRITE * @arg @ref LL_I2C_DIRECTION_READ */ -__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR)); } @@ -2226,7 +2333,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0x3F */ -__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1); } @@ -2256,7 +2363,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL); } @@ -2269,7 +2376,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC)); } @@ -2280,7 +2387,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx) { return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA)); } @@ -2333,7 +2440,7 @@ __STATIC_INLINE void LL_I2C_Disable_SelectedTrigger(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabled_SelectedTrigger(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabled_SelectedTrigger(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGEN) == (I2C_AUTOCR_TRIGEN)) ? 1UL : 0UL); } @@ -2360,7 +2467,7 @@ __STATIC_INLINE void LL_I2C_SetTriggerPolarity(I2C_TypeDef *I2Cx, uint32_t Polar * @arg @ref LL_I2C_TRIG_POLARITY_RISING * @arg @ref LL_I2C_TRIG_POLARITY_FALLING */ -__STATIC_INLINE uint32_t LL_I2C_GetTriggerPolarity(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetTriggerPolarity(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGPOL)); } @@ -2431,7 +2538,7 @@ __STATIC_INLINE void LL_I2C_SetSelectedTrigger(I2C_TypeDef *I2Cx, uint32_t Trigg * @arg @ref LL_I2C_GRP2_RTC_ALRA_TRG * @arg @ref LL_I2C_GRP2_RTC_WUT_TRG */ -__STATIC_INLINE uint32_t LL_I2C_GetSelectedTrigger(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSelectedTrigger(const I2C_TypeDef *I2Cx) { if (IS_LL_I2C_GRP2_INSTANCE(I2Cx)) { @@ -2452,8 +2559,8 @@ __STATIC_INLINE uint32_t LL_I2C_GetSelectedTrigger(I2C_TypeDef *I2Cx) * @{ */ -ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct); -ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx); +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct); +ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx); void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); @@ -2470,7 +2577,7 @@ void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); * @} */ -#endif /* I2C1 || I2C2 || I2C3 || I2C4 */ +#endif /* I2C1 || I2C2 || I2C3 || I2C4 || I2C5 || I2C6 */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_icache.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_icache.c index b8d8c58131c..3d9cf8f1735 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_icache.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_icache.c @@ -39,7 +39,7 @@ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ -/** @addtogroup ICACHE_LL_Private_Macros +/** @defgroup ICACHE_LL_Private_Macros ICACHE Private Macros * @{ */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_iwdg.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_iwdg.h index d0be093275d..8e0ce602733 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_iwdg.h @@ -214,7 +214,7 @@ __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescale * @arg @ref LL_IWDG_PRESCALER_512 * @arg @ref LL_IWDG_PRESCALER_1024 */ -__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->PR)); } @@ -237,7 +237,7 @@ __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Coun * @param IWDGx IWDG Instance * @retval Value between Min_Data=0 and Max_Data=0x0FFF */ -__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->RLR)); } @@ -260,7 +260,7 @@ __STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window) * @param IWDGx IWDG Instance * @retval Value between Min_Data=0 and Max_Data=0x0FFF */ -__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetWindow(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->WINR)); } @@ -291,7 +291,7 @@ __STATIC_INLINE void LL_IWDG_SetEwiTime(IWDG_TypeDef *IWDGx, uint32_t Time) * @param IWDGx IWDG Instance * @retval Value between Min_Data=0 and Max_Data=0x0FFF */ -__STATIC_INLINE uint32_t LL_IWDG_GetEwiTime(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetEwiTime(const IWDG_TypeDef *IWDGx) { return (READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIT)); } @@ -320,11 +320,11 @@ __STATIC_INLINE void LL_IWDG_DisableIT_EWI(IWDG_TypeDef *IWDGx) /** * @brief Indicates whether Early wakeup interrupt is enable - * @rmtoll EWCR EWIE LL_IWDG_IsEnableIT_EWI + * @rmtoll EWCR EWIE LL_IWDG_IsEnabledIT_EWI * @param IWDGx IWDG Instance * @retval None */ -__STATIC_INLINE uint32_t LL_IWDG_IsEnableIT_EWI(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsEnabledIT_EWI(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE) == (IWDG_EWCR_EWIE)) ? 1UL : 0UL); } @@ -343,7 +343,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsEnableIT_EWI(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL); } @@ -354,7 +354,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL); } @@ -365,7 +365,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL); } @@ -376,7 +376,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_EWU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_EWU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_EWU) == (IWDG_SR_EWU)) ? 1UL : 0UL); } @@ -390,7 +390,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_EWU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bits (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsReady(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU | IWDG_SR_EWU) == 0U) ? 1UL : 0UL); } @@ -401,7 +401,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_EWIF(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_EWIF(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_EWIF) == (IWDG_SR_EWIF)) ? 1UL : 0UL); } diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lpgpio.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lpgpio.c index 2a81d437526..5b72a71cbf7 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lpgpio.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lpgpio.c @@ -70,7 +70,7 @@ * - SUCCESS: LPGPIO registers are de-initialized * - ERROR: Wrong LPGPIO Port */ -ErrorStatus LL_LPGPIO_DeInit(GPIO_TypeDef *LPGPIOx) +ErrorStatus LL_LPGPIO_DeInit(const GPIO_TypeDef *LPGPIOx) { ErrorStatus status = SUCCESS; diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lpgpio.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lpgpio.h index dc886319ec3..4a260291176 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lpgpio.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lpgpio.h @@ -224,7 +224,7 @@ __STATIC_INLINE void LL_LPGPIO_SetPinMode(GPIO_TypeDef *LPGPIOx, uint32_t Pin, u * @arg @ref LL_LPGPIO_MODE_INPUT * @arg @ref LL_LPGPIO_MODE_OUTPUT */ -__STATIC_INLINE uint32_t LL_LPGPIO_GetPinMode(GPIO_TypeDef *LPGPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_LPGPIO_GetPinMode(const GPIO_TypeDef *LPGPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(LPGPIOx->MODER, (LPGPIO_MODER_MOD0 << (POSITION_VAL(Pin)))) >> (POSITION_VAL(Pin))); @@ -245,7 +245,7 @@ __STATIC_INLINE uint32_t LL_LPGPIO_GetPinMode(GPIO_TypeDef *LPGPIOx, uint32_t Pi * @param LPGPIOx LPGPIO Port * @retval Input data register value of port */ -__STATIC_INLINE uint32_t LL_LPGPIO_ReadInputPort(GPIO_TypeDef *LPGPIOx) +__STATIC_INLINE uint32_t LL_LPGPIO_ReadInputPort(const GPIO_TypeDef *LPGPIOx) { return (uint32_t)(READ_REG(LPGPIOx->IDR)); } @@ -274,7 +274,7 @@ __STATIC_INLINE uint32_t LL_LPGPIO_ReadInputPort(GPIO_TypeDef *LPGPIOx) * @arg @ref LL_LPGPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPGPIO_IsInputPinSet(GPIO_TypeDef *LPGPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_LPGPIO_IsInputPinSet(const GPIO_TypeDef *LPGPIOx, uint32_t PinMask) { return ((READ_BIT(LPGPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -284,6 +284,7 @@ __STATIC_INLINE uint32_t LL_LPGPIO_IsInputPinSet(GPIO_TypeDef *LPGPIOx, uint32_t * @rmtoll ODR ODy LL_LPGPIO_WriteOutputPort * @param LPGPIOx LPGPIO Port * @param PortValue Level value for each pin of the port + Value between 0 and 0xFFFF * @retval None */ __STATIC_INLINE void LL_LPGPIO_WriteOutputPort(GPIO_TypeDef *LPGPIOx, uint32_t PortValue) @@ -297,7 +298,7 @@ __STATIC_INLINE void LL_LPGPIO_WriteOutputPort(GPIO_TypeDef *LPGPIOx, uint32_t P * @param LPGPIOx LPGPIO Port * @retval Output data register value of port */ -__STATIC_INLINE uint32_t LL_LPGPIO_ReadOutputPort(GPIO_TypeDef *LPGPIOx) +__STATIC_INLINE uint32_t LL_LPGPIO_ReadOutputPort(const GPIO_TypeDef *LPGPIOx) { return (uint32_t)(READ_REG(LPGPIOx->ODR)); } @@ -326,7 +327,7 @@ __STATIC_INLINE uint32_t LL_LPGPIO_ReadOutputPort(GPIO_TypeDef *LPGPIOx) * @arg @ref LL_LPGPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPGPIO_IsOutputPinSet(GPIO_TypeDef *LPGPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_LPGPIO_IsOutputPinSet(const GPIO_TypeDef *LPGPIOx, uint32_t PinMask) { return ((READ_BIT(LPGPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -431,7 +432,7 @@ __STATIC_INLINE void LL_LPGPIO_TogglePin(GPIO_TypeDef *LPGPIOx, uint32_t PinMask * @{ */ -ErrorStatus LL_LPGPIO_DeInit(GPIO_TypeDef *LPGPIOx); +ErrorStatus LL_LPGPIO_DeInit(const GPIO_TypeDef *LPGPIOx); ErrorStatus LL_LPGPIO_Init(GPIO_TypeDef *LPGPIOx, const LL_LPGPIO_InitTypeDef *const LPGPIO_InitStruct); void LL_LPGPIO_StructInit(LL_LPGPIO_InitTypeDef *LPGPIO_InitStruct); diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lptim.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lptim.c index eb2f4663863..dca6a544f89 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lptim.c @@ -90,7 +90,7 @@ * - SUCCESS: LPTIMx registers are de-initialized * - ERROR: invalid LPTIMx instance */ -ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx) +ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx) { ErrorStatus result = SUCCESS; @@ -149,7 +149,7 @@ void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct) * - SUCCESS: LPTIMx instance has been initialized * - ERROR: LPTIMx instance hasn't been initialized */ -ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct) +ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct) { ErrorStatus result = SUCCESS; /* Check the parameters */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lptim.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lptim.h index 81946fb4485..338c4ad0676 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lptim.h @@ -73,11 +73,34 @@ static const uint8_t LL_LPTIM_SHIFT_TAB_CCxE[] = LPTIM_CCMR1_CC2E_Pos /* CC2E */ }; +static const uint8_t LL_LPTIM_OFFSET_TAB_ICx[8][4] = +{ + {2, 7, 9, 13}, + {3, 5, 6, 8}, + {2, 3, 4, 5}, + {2, 2, 3, 3}, + {2, 2, 2, 2}, + {2, 2, 2, 2}, + {2, 2, 2, 2}, + {2, 2, 2, 2} + +}; + /** * @} */ /* Private constants ---------------------------------------------------------*/ +/** Legacy definitions for compatibility purpose +@cond 0 + */ +#define LL_LPTIM_SetCompareCH1 LL_LPTIM_OC_SetCompareCH1 +#define LL_LPTIM_SetCompareCH2 LL_LPTIM_OC_SetCompareCH2 +#define LL_LPTIM_GetCompareCH1 LL_LPTIM_OC_GetCompareCH1 +#define LL_LPTIM_GetCompareCH2 LL_LPTIM_OC_GetCompareCH2 +/** +@endcond + */ /* Private macros ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) @@ -225,6 +248,7 @@ typedef struct /** * @} */ + /** @defgroup LPTIM_LL_EC_LPTIM_IC_PRESCALER Input Capture Prescaler * @{ */ @@ -291,11 +315,11 @@ typedef struct #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!__REG__) + +/** + * @brief LPTimer Input Capture Get Offset(in counter step unit) + * @note The real capture value corresponding to the input capture trigger can be calculated using + * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset + * The Offset value is depending on the glitch filter value for the channel + * and the value of the prescaler for the kernel clock. + * Please check Errata Sheet V1_8 for more details under "variable latency + * on input capture channel" section. + * @param __PSC__ This parameter can be one of the following values: + * @arg @ref LL_LPTIM_PRESCALER_DIV1 + * @arg @ref LL_LPTIM_PRESCALER_DIV2 + * @arg @ref LL_LPTIM_PRESCALER_DIV4 + * @arg @ref LL_LPTIM_PRESCALER_DIV8 + * @arg @ref LL_LPTIM_PRESCALER_DIV16 + * @arg @ref LL_LPTIM_PRESCALER_DIV32 + * @arg @ref LL_LPTIM_PRESCALER_DIV64 + * @arg @ref LL_LPTIM_PRESCALER_DIV128 + * @param __FLT__ This parameter can be one of the following values: + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8 + * @retval offset value + */ +#define LL_LPTIM_IC_GET_OFFSET(__PSC__, __FLT__) LL_LPTIM_OFFSET_TAB_ICx\ + [((__PSC__) & LPTIM_CFGR_PRESC_Msk) >> LPTIM_CFGR_PRESC_Pos]\ + [((__FLT__) & LPTIM_CCMR1_IC1F_Msk) >> LPTIM_CCMR1_IC1F_Pos] /** * @} */ @@ -474,14 +526,27 @@ typedef struct * @{ */ +/** Legacy definitions for compatibility purpose +@cond 0 + */ +#define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM +#define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1 +#define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2 +#define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O +#define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O +#define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM +/** +@endcond + */ + #if defined(USE_FULL_LL_DRIVER) /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions * @{ */ -ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx); +ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx); void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct); -ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct); +ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct); /** * @} */ @@ -521,7 +586,7 @@ __STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL)); } @@ -574,7 +639,7 @@ __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL)); } @@ -617,7 +682,7 @@ __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t Upda * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD */ -__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD)); } @@ -632,7 +697,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx) * @note autoreload value be strictly greater than the compare value. * @rmtoll ARR ARR LL_LPTIM_SetAutoReload * @param LPTIMx Low-Power Timer instance - * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF + * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF * @retval None */ __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload) @@ -644,9 +709,9 @@ __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t Auto * @brief Get actual auto reload value * @rmtoll ARR ARR LL_LPTIM_GetAutoReload * @param LPTIMx Low-Power Timer instance - * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR)); } @@ -670,7 +735,7 @@ __STATIC_INLINE void LL_LPTIM_SetRepetition(LPTIM_TypeDef *LPTIMx, uint32_t Repe * @param LPTIMx Low-Power Timer instance * @retval Repetition Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->RCR, LPTIM_RCR_REP)); } @@ -715,7 +780,7 @@ __STATIC_INLINE void LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef *LPTIMx, uint32_t * @arg @ref LL_LPTIM_CHANNEL_CH2 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_CC_IsEnabledChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef *LPTIMx, uint32_t Channel) { return ((READ_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]) == \ (0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel])) ? 1UL : 0UL); @@ -728,23 +793,23 @@ __STATIC_INLINE uint32_t LL_LPTIM_CC_IsEnabledChannel(LPTIM_TypeDef *LPTIMx, uin * same register can only be performed when the previous write operation * is completed. Any successive write before the CMP1OK flag is set, will * lead to unpredictable results. - * @rmtoll CCR1 CCR1 LL_LPTIM_SetCompareCH1 + * @rmtoll CCR1 CCR1 LL_LPTIM_OC_SetCompareCH1 * @param LPTIMx Low-Power Timer instance * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF * @retval None */ -__STATIC_INLINE void LL_LPTIM_SetCompareCH1(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue) +__STATIC_INLINE void LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue) { MODIFY_REG(LPTIMx->CCR1, LPTIM_CCR1_CCR1, CompareValue); } /** * @brief Get actual compare value - * @rmtoll CCR1 CCR1 LL_LPTIM_GetCompareCH1 + * @rmtoll CCR1 CCR1 LL_LPTIM_OC_GetCompareCH1 * @param LPTIMx Low-Power Timer instance * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCompareCH1(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1)); } @@ -755,23 +820,23 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetCompareCH1(LPTIM_TypeDef *LPTIMx) * same register can only be performed when the previous write operation * is completed. Any successive write before the CMP2OK flag is set, will * lead to unpredictable results. - * @rmtoll CCR2 CCR2 LL_LPTIM_SetCompareCH2 + * @rmtoll CCR2 CCR2 LL_LPTIM_OC_SetCompareCH2 * @param LPTIMx Low-Power Timer instance * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF * @retval None */ -__STATIC_INLINE void LL_LPTIM_SetCompareCH2(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue) +__STATIC_INLINE void LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue) { MODIFY_REG(LPTIMx->CCR2, LPTIM_CCR2_CCR2, CompareValue); } /** * @brief Get actual compare value - * @rmtoll CCR2 CCR2 LL_LPTIM_GetCompareCH2 + * @rmtoll CCR2 CCR2 LL_LPTIM_OC_GetCompareCH2 * @param LPTIMx Low-Power Timer instance * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCompareCH2(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2)); } @@ -786,7 +851,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetCompareCH2(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval Counter value */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT)); } @@ -814,7 +879,7 @@ __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t Cou * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE)); } @@ -841,7 +906,7 @@ __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Wavefo * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE */ -__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE)); } @@ -884,7 +949,7 @@ __STATIC_INLINE void LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Cha * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE */ -__STATIC_INLINE uint32_t LL_LPTIM_OC_GetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel) { if (LPTIMx == LPTIM4) { @@ -936,7 +1001,7 @@ __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Presc * @arg @ref LL_LPTIM_PRESCALER_DIV64 * @arg @ref LL_LPTIM_PRESCALER_DIV128 */ -__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC)); } @@ -983,13 +1048,13 @@ __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src) * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_GPIO * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSI * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSE + * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_GPIO + * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_COMP1 + * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_COMP2 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_GPIO * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_HSI * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_MSIS_1024 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_MSIS_4 - * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_GPIO - * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_COMP1 - * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_COMP2 * @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_GPIO * @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_COMP1 * @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_COMP2 @@ -1033,7 +1098,7 @@ __STATIC_INLINE void LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Cha * @arg @ref LL_LPTIM_ICPOLARITY_FALLING * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_LPTIM_IC_GetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel) { return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel])) >> \ LL_LPTIM_SHIFT_TAB_CCxP[Channel]); @@ -1075,7 +1140,7 @@ __STATIC_INLINE void LL_LPTIM_IC_SetFilter(LPTIM_TypeDef *LPTIMx, uint32_t Chann * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8 */ -__STATIC_INLINE uint32_t LL_LPTIM_IC_GetFilter(LPTIM_TypeDef *LPTIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef *LPTIMx, uint32_t Channel) { return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel])) >> \ LL_LPTIM_SHIFT_TAB_ICxF[Channel]); @@ -1116,7 +1181,7 @@ __STATIC_INLINE void LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Ch * @arg @ref LL_LPTIM_ICPSC_DIV4 * @arg @ref LL_LPTIM_ICPSC_DIV8 */ -__STATIC_INLINE uint32_t LL_LPTIM_IC_GetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef *LPTIMx, uint32_t Channel) { return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel])) >> \ LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]); @@ -1152,7 +1217,7 @@ __STATIC_INLINE void LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef *LPTIMx, uint32_t * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE */ -__STATIC_INLINE uint32_t LL_LPTIM_CC_GetChannelMode(LPTIM_TypeDef *LPTIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef *LPTIMx, uint32_t Channel) { return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1SEL << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel])) >> \ LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]); @@ -1161,10 +1226,13 @@ __STATIC_INLINE uint32_t LL_LPTIM_CC_GetChannelMode(LPTIM_TypeDef *LPTIMx, uint /** * @brief Get captured value for input channel 1. * @rmtoll CCR1 CCR1 LL_LPTIM_IC_GetCaptureCH1 + * @note The real capture value corresponding to the input capture trigger can be calculated using + * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset + * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET * @param LPTIMx Low-Power Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH1(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1)); } @@ -1172,10 +1240,13 @@ __STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH1(LPTIM_TypeDef *LPTIMx) /** * @brief Get captured value for input channel 2. * @rmtoll CCR2 CCR2 LL_LPTIM_IC_GetCaptureCH2 + * @note The real capture value corresponding to the input capture trigger can be calculated using + * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset + * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET * @param LPTIMx Low-Power Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH2(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2)); } @@ -1225,7 +1296,7 @@ __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL)); } @@ -1300,7 +1371,7 @@ __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Sour * @arg @ref LL_LPTIM_TRIG_SOURCE_GPDMA_CH0_TCF * @arg @ref LL_LPTIM_TRIG_SOURCE_GPDMA_CH4_TCF */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL)); } @@ -1315,7 +1386,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx) * @arg @ref LL_LPTIM_TRIG_FILTER_4 * @arg @ref LL_LPTIM_TRIG_FILTER_8 */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT)); } @@ -1329,7 +1400,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx) * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN)); } @@ -1365,7 +1436,7 @@ __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t Clo * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL)); } @@ -1407,7 +1478,7 @@ __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockF * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); } @@ -1422,7 +1493,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx) * @arg @ref LL_LPTIM_CLK_FILTER_4 * @arg @ref LL_LPTIM_CLK_FILTER_8 */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT)); } @@ -1460,7 +1531,7 @@ __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t Enc * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); } @@ -1499,7 +1570,7 @@ __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL)); } @@ -1514,11 +1585,11 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx) /** * @brief Clear the compare match flag for channel 1 (CC1CF) - * @rmtoll ICR CC1CF LL_LPTIM_ClearFLAG_CC1 + * @rmtoll ICR CC1CF LL_LPTIM_ClearFlag_CC1 * @param LPTIMx Low-Power Timer instance * @retval None */ -__STATIC_INLINE void LL_LPTIM_ClearFLAG_CC1(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE void LL_LPTIM_ClearFlag_CC1(LPTIM_TypeDef *LPTIMx) { SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1CF); } @@ -1529,18 +1600,18 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_CC1(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1IF) == LPTIM_ISR_CC1IF) ? 1UL : 0UL)); } /** * @brief Clear the compare match flag for channel 2 (CC2CF) - * @rmtoll ICR CC2CF LL_LPTIM_ClearFLAG_CC2 + * @rmtoll ICR CC2CF LL_LPTIM_ClearFlag_CC2 * @param LPTIMx Low-Power Timer instance * @retval None */ -__STATIC_INLINE void LL_LPTIM_ClearFLAG_CC2(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE void LL_LPTIM_ClearFlag_CC2(LPTIM_TypeDef *LPTIMx) { SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2CF); } @@ -1551,18 +1622,18 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_CC2(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2IF) == LPTIM_ISR_CC2IF) ? 1UL : 0UL)); } /** * @brief Clear the Capture/Compare 1 over-capture flag for channel 1 (CC1OCF) - * @rmtoll ICR CC1OCF LL_LPTIM_ClearFLAG_CC1O + * @rmtoll ICR CC1OCF LL_LPTIM_ClearFlag_CC1O * @param LPTIMx Low-Power Timer instance * @retval None */ -__STATIC_INLINE void LL_LPTIM_ClearFLAG_CC1O(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE void LL_LPTIM_ClearFlag_CC1O(LPTIM_TypeDef *LPTIMx) { SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1OCF); } @@ -1573,18 +1644,18 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_CC1O(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1O(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1OF) == LPTIM_ISR_CC1OF) ? 1UL : 0UL)); } /** * @brief Clear the Capture/Compare 2 over-capture flag for channel 2 (CC2OCF) - * @rmtoll ICR CC2OCF LL_LPTIM_ClearFLAG_CC2O + * @rmtoll ICR CC2OCF LL_LPTIM_ClearFlag_CC2O * @param LPTIMx Low-Power Timer instance * @retval None */ -__STATIC_INLINE void LL_LPTIM_ClearFLAG_CC2O(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE void LL_LPTIM_ClearFlag_CC2O(LPTIM_TypeDef *LPTIMx) { SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2OCF); } @@ -1595,17 +1666,17 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_CC2O(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2O(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2OF) == LPTIM_ISR_CC2OF) ? 1UL : 0UL)); } /** * @brief Clear the autoreload match flag (ARRMCF) - * @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM + * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM * @param LPTIMx Low-Power Timer instance * @retval None */ -__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx) { SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF); } @@ -1616,7 +1687,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL)); } @@ -1638,7 +1709,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL)); } @@ -1661,7 +1732,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP1OK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP1OK) == LPTIM_ISR_CMP1OK) ? 1UL : 0UL)); } @@ -1684,7 +1755,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP2OK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP2OK) == LPTIM_ISR_CMP2OK) ? 1UL : 0UL)); } @@ -1707,7 +1778,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DIEROK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef *LPTIMx) { return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DIEROK) == (LPTIM_ISR_DIEROK)) ? 1UL : 0UL); } @@ -1730,7 +1801,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL)); } @@ -1753,7 +1824,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL)); } @@ -1776,7 +1847,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL)); } @@ -1799,7 +1870,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef *LPTIMx) { return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_REPOK) == (LPTIM_ISR_REPOK)) ? 1UL : 0UL); } @@ -1821,7 +1892,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef *LPTIMx) { return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UE) == (LPTIM_ISR_UE)) ? 1UL : 0UL); } @@ -1861,7 +1932,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE) == LPTIM_DIER_CC1IE) ? 1UL : 0UL)); } @@ -1894,7 +1965,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE) == LPTIM_DIER_CC2IE) ? 1UL : 0UL)); } @@ -1911,7 +1982,7 @@ __STATIC_INLINE void LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef *LPTIMx) } /** - * @brief Disable capture/compare 1 over-capture interrup (CC1OIE). + * @brief Disable capture/compare 1 over-capture interrupt (CC1OIE). * @rmtoll DIER CC1OIE LL_LPTIM_DisableIT_CC1O * @param LPTIMx Low-Power Timer instance * @retval None @@ -1922,12 +1993,12 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef *LPTIMx) } /** - * @brief Indicates whether the capture/compare 1 over-capture interrup (CC1OIE) is enabled. + * @brief Indicates whether the capture/compare 1 over-capture interrupt (CC1OIE) is enabled. * @rmtoll DIER CC1OIE LL_LPTIM_IsEnabledIT_CC1O * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1O(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE) == LPTIM_DIER_CC1OIE) ? 1UL : 0UL)); } @@ -1944,7 +2015,7 @@ __STATIC_INLINE void LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef *LPTIMx) } /** - * @brief Disable capture/compare 1 over-capture interrup (CC2OIE). + * @brief Disable capture/compare 1 over-capture interrupt (CC2OIE). * @rmtoll DIER CC2OIE LL_LPTIM_DisableIT_CC2O * @param LPTIMx Low-Power Timer instance * @retval None @@ -1955,12 +2026,12 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef *LPTIMx) } /** - * @brief Indicates whether the capture/compare 2 over-capture interrup (CC2OIE) is enabled. + * @brief Indicates whether the capture/compare 2 over-capture interrupt (CC2OIE) is enabled. * @rmtoll DIER CC2OIE LL_LPTIM_IsEnabledIT_CC2O * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2O(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE) == LPTIM_DIER_CC2OIE) ? 1UL : 0UL)); } @@ -1993,7 +2064,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE) == LPTIM_DIER_ARRMIE) ? 1UL : 0UL)); } @@ -2026,7 +2097,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE) == LPTIM_DIER_EXTTRIGIE) ? 1UL : 0UL)); } @@ -2059,7 +2130,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP1OK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE) == LPTIM_DIER_CMP1OKIE) ? 1UL : 0UL)); } @@ -2092,7 +2163,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP2OK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE) == LPTIM_DIER_CMP2OKIE) ? 1UL : 0UL)); } @@ -2125,7 +2196,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE) == LPTIM_DIER_ARROKIE) ? 1UL : 0UL)); } @@ -2158,7 +2229,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE) == LPTIM_DIER_UPIE) ? 1UL : 0UL)); } @@ -2191,7 +2262,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx) { return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE) == LPTIM_DIER_DOWNIE) ? 1UL : 0UL); } @@ -2224,7 +2295,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef *LPTIMx) { return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE) == (LPTIM_DIER_REPOKIE)) ? 1UL : 0UL); } @@ -2257,7 +2328,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UE(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance *@ retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef *LPTIMx) { return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE) == (LPTIM_DIER_UEIE)) ? 1UL : 0UL); } @@ -2297,7 +2368,7 @@ __STATIC_INLINE void LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef *LPTIMx) { return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE) == (LPTIM_DIER_UEDE)) ? 1UL : 0UL); } @@ -2330,7 +2401,7 @@ __STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC1(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef *LPTIMx) { return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE) == (LPTIM_DIER_CC1DE)) ? 1UL : 0UL); } @@ -2363,7 +2434,7 @@ __STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC2(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef *LPTIMx) { return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE) == (LPTIM_DIER_CC2DE)) ? 1UL : 0UL); } diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lpuart.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lpuart.c index 6d4e0b284a8..db8a4dcd8b7 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lpuart.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lpuart.c @@ -44,6 +44,9 @@ * @{ */ +/* Definition of default baudrate value used for LPUART initialisation */ +#define LPUART_DEFAULT_BAUDRATE (9600U) + /** * @} */ @@ -126,7 +129,7 @@ * - SUCCESS: LPUART registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx) +ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx) { ErrorStatus status = SUCCESS; @@ -164,7 +167,7 @@ ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx) * - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content * - ERROR: Problem occurred during LPUART Registers initialization */ -ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct) +ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct) { ErrorStatus status = ERROR; uint32_t periphclk; @@ -253,7 +256,7 @@ void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct) { /* Set LPUART_InitStruct fields to default values */ LPUART_InitStruct->PrescalerValue = LL_LPUART_PRESCALER_DIV1; - LPUART_InitStruct->BaudRate = 9600U; + LPUART_InitStruct->BaudRate = LPUART_DEFAULT_BAUDRATE; LPUART_InitStruct->DataWidth = LL_LPUART_DATAWIDTH_8B; LPUART_InitStruct->StopBits = LL_LPUART_STOPBITS_1; LPUART_InitStruct->Parity = LL_LPUART_PARITY_NONE ; diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lpuart.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lpuart.h index a1df60e834d..77ba8787139 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lpuart.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_lpuart.h @@ -158,7 +158,6 @@ typedef struct #define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */ #define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ #define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ -#define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */ #define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ #define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ #define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ @@ -539,7 +538,7 @@ __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); } @@ -572,7 +571,7 @@ __STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); } @@ -607,7 +606,7 @@ __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 */ -__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); } @@ -642,7 +641,7 @@ __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 */ -__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); } @@ -706,7 +705,7 @@ __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); } @@ -784,7 +783,7 @@ __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint * @arg @ref LL_LPUART_DIRECTION_TX * @arg @ref LL_LPUART_DIRECTION_TX_RX */ -__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE)); } @@ -818,7 +817,7 @@ __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity * @arg @ref LL_LPUART_PARITY_EVEN * @arg @ref LL_LPUART_PARITY_ODD */ -__STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); } @@ -845,7 +844,7 @@ __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t * @arg @ref LL_LPUART_WAKEUP_IDLELINE * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK */ -__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE)); } @@ -874,7 +873,7 @@ __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t Dat * @arg @ref LL_LPUART_DATAWIDTH_8B * @arg @ref LL_LPUART_DATAWIDTH_9B */ -__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M)); } @@ -907,7 +906,7 @@ __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); } @@ -954,7 +953,7 @@ __STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t Pre * @arg @ref LL_LPUART_PRESCALER_DIV128 * @arg @ref LL_LPUART_PRESCALER_DIV256 */ -__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER)); } @@ -981,7 +980,7 @@ __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_ * @arg @ref LL_LPUART_STOPBITS_1 * @arg @ref LL_LPUART_STOPBITS_2 */ -__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP)); } @@ -1039,7 +1038,7 @@ __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t Swap * @arg @ref LL_LPUART_TXRX_STANDARD * @arg @ref LL_LPUART_TXRX_SWAPPED */ -__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP)); } @@ -1066,7 +1065,7 @@ __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t Pi * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED */ -__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV)); } @@ -1093,7 +1092,7 @@ __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t Pi * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED */ -__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV)); } @@ -1123,7 +1122,7 @@ __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE */ -__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV)); } @@ -1154,7 +1153,7 @@ __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint3 * @arg @ref LL_LPUART_BITORDER_LSBFIRST * @arg @ref LL_LPUART_BITORDER_MSBFIRST */ -__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST)); } @@ -1198,7 +1197,7 @@ __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_ * @param LPUARTx LPUART Instance * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255) */ -__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); } @@ -1211,7 +1210,7 @@ __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx) * @arg @ref LL_LPUART_ADDRESS_DETECT_4B * @arg @ref LL_LPUART_ADDRESS_DETECT_7B */ -__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7)); } @@ -1288,7 +1287,7 @@ __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t Ha * @arg @ref LL_LPUART_HWCONTROL_CTS * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS */ -__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); } @@ -1321,7 +1320,7 @@ __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); } @@ -1386,7 +1385,8 @@ __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t Peri * @arg @ref LL_LPUART_PRESCALER_DIV256 * @retval Baud Rate */ -__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue) +__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk, + uint32_t PrescalerValue) { uint32_t lpuartdiv; uint32_t brrresult; @@ -1442,7 +1442,7 @@ __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); } @@ -1473,7 +1473,7 @@ __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint * @param LPUARTx LPUART Instance * @retval Time value expressed on 5 bits ([4:0] bits) : c */ -__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); } @@ -1496,7 +1496,7 @@ __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32 * @param LPUARTx LPUART Instance * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31 */ -__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); } @@ -1529,7 +1529,7 @@ __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); } @@ -1556,7 +1556,7 @@ __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint3 * @arg @ref LL_LPUART_DE_POLARITY_HIGH * @arg @ref LL_LPUART_DE_POLARITY_LOW */ -__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP)); } @@ -1575,7 +1575,7 @@ __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); } @@ -1586,7 +1586,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); } @@ -1597,7 +1597,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); } @@ -1608,7 +1608,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); } @@ -1619,13 +1619,12 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE +#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not @@ -1633,7 +1632,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); } @@ -1644,13 +1643,12 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUART * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF +#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not @@ -1658,7 +1656,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); } @@ -1669,7 +1667,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); } @@ -1680,7 +1678,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); } @@ -1691,7 +1689,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); } @@ -1702,7 +1700,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); } @@ -1713,7 +1711,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); } @@ -1724,7 +1722,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); } @@ -1735,7 +1733,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); } @@ -1746,7 +1744,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); } @@ -1757,7 +1755,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); } @@ -1768,7 +1766,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); } @@ -1779,7 +1777,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); } @@ -1790,7 +1788,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); } @@ -1850,17 +1848,6 @@ __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx) WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF); } -/** - * @brief Clear TX FIFO Empty Flag - * @rmtoll ICR TXFECF LL_LPUART_ClearFlag_TXFE - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_ClearFlag_TXFE(USART_TypeDef *LPUARTx) -{ - WRITE_REG(LPUARTx->ICR, USART_ICR_TXFECF); -} - /** * @brief Clear Transmission Complete Flag * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC @@ -1913,8 +1900,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE +#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt @@ -1938,8 +1924,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF +#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Enable TX Empty and TX FIFO Not Full Interrupt @@ -2055,8 +2040,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE +#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt @@ -2080,8 +2064,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF +#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Disable TX Empty and TX FIFO Not Full Interrupt @@ -2192,13 +2175,12 @@ __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE +#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled. @@ -2206,7 +2188,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); } @@ -2217,13 +2199,12 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF +#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled @@ -2231,7 +2212,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); } @@ -2242,7 +2223,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); } @@ -2253,7 +2234,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); } @@ -2264,7 +2245,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); } @@ -2275,7 +2256,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); } @@ -2286,7 +2267,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); } @@ -2297,7 +2278,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); } @@ -2308,7 +2289,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); } @@ -2319,7 +2300,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); } @@ -2360,7 +2341,7 @@ __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); } @@ -2393,7 +2374,7 @@ __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); } @@ -2426,7 +2407,7 @@ __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); } @@ -2441,7 +2422,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUAR * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction) +__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction) { uint32_t data_reg_addr; @@ -2473,7 +2454,7 @@ __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32 * @param LPUARTx LPUART Instance * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx) { return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU); } @@ -2484,7 +2465,7 @@ __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF */ -__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx) { return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR)); } @@ -2592,7 +2573,7 @@ __STATIC_INLINE void LL_LPUART_Disable_SelectedTrigger(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabled_SelectedTrigger(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabled_SelectedTrigger(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGEN) == (USART_AUTOCR_TRIGEN)) ? 1UL : 0UL); } @@ -2625,7 +2606,7 @@ __STATIC_INLINE void LL_LPUART_Disable_AutonomousSendIdleFrame(USART_TypeDef *LP * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabled_AutonomousSendIdleFrame(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabled_AutonomousSendIdleFrame(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_IDLEDIS) == (USART_AUTOCR_IDLEDIS)) ? 0UL : 1UL); } @@ -2648,7 +2629,7 @@ __STATIC_INLINE void LL_LPUART_SetNbTxData(USART_TypeDef *LPUARTx, uint32_t Nbda * @param LPUARTx LPUART Instance * @retval Returned value can be a value between 0 and 0xFFFF */ -__STATIC_INLINE uint32_t LL_LPUART_GetNbTxData(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetNbTxData(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TDN)); } @@ -2675,7 +2656,7 @@ __STATIC_INLINE void LL_LPUART_SetTriggerPolarity(USART_TypeDef *LPUARTx, uint32 * @arg @ref LL_LPUART_TRIG_POLARITY_RISING * @arg @ref LL_LPUART_TRIG_POLARITY_FALLING */ -__STATIC_INLINE uint32_t LL_LPUART_GetTriggerPolarity(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetTriggerPolarity(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGPOL)); } @@ -2722,7 +2703,7 @@ __STATIC_INLINE void LL_LPUART_SetSelectedTrigger(USART_TypeDef *LPUARTx, uint32 * @arg @ref LL_LPUART_RTC_ALRA_TRG * @arg @ref LL_LPUART_RTC_WUT_TRG */ -__STATIC_INLINE uint32_t LL_LPUART_GetSelectedTrigger(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetSelectedTrigger(const USART_TypeDef *LPUARTx) { return (uint32_t)((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGSEL) >> USART_AUTOCR_TRIGSEL_Pos)); } @@ -2735,8 +2716,8 @@ __STATIC_INLINE uint32_t LL_LPUART_GetSelectedTrigger(USART_TypeDef *LPUARTx) /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx); -ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct); +ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx); +ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct); void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct); /** * @} @@ -2762,3 +2743,4 @@ void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct); #endif #endif /* STM32U5xx_LL_LPUART_H */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_opamp.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_opamp.c index bd2c2c81a83..ad047d6b6ee 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_opamp.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_opamp.c @@ -65,7 +65,7 @@ /* compatibility with other STM32 families. */ #define IS_LL_OPAMP_INPUT_NONINVERTING(__OPAMPX__, __INPUT_NONINVERTING__) \ ( ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO0) \ - || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINV_DAC1_CH1) \ + || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINV_DAC1_CH1) \ ) /* Note: Comparator non-inverting inputs parameters are the same on all */ @@ -74,8 +74,8 @@ /* compatibility with other STM32 families. */ #define IS_LL_OPAMP_INPUT_INVERTING(__OPAMPX__, __INPUT_INVERTING__) \ ( ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO0) \ - || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO1) \ - || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_CONNECT_NO) \ + || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO1) \ + || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_CONNECT_NO) \ ) /** @@ -129,7 +129,7 @@ ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef *OPAMPx) * - SUCCESS: OPAMP registers are initialized * - ERROR: OPAMP registers are not initialized */ -ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct) +ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, const LL_OPAMP_InitTypeDef *OPAMP_InitStruct) { /* Check the parameters */ assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx)); diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_opamp.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_opamp.h index dd389780154..df1c41a5e53 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_opamp.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_opamp.h @@ -90,7 +90,6 @@ extern "C" { * @} */ - /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup OPAMP_LL_ES_INIT OPAMP Exported Init structure @@ -195,7 +194,7 @@ typedef struct * @{ */ #define LL_OPAMP_INPUT_NONINVERT_IO0 0x00000000U /*!< OPAMP non inverting input connected to GPIO pin (pin PA0 for OPAMP1, pin PA6 for OPAMP2) */ -#define LL_OPAMP_INPUT_NONINV_DAC1_CH1 (OPAMP_CSR_VP_SEL) /*!< OPAMP non inverting input connected to DAC1 channel output(channel1 for OPAMP1, channel2 for OPAMP2) */ +#define LL_OPAMP_INPUT_NONINV_DAC1_CH1 (OPAMP_CSR_VP_SEL) /*!< OPAMP non inverting input connected to DAC1 channel output(channel1 for OPAMP1, channel2 for OPAMP2) */ /** * @} */ @@ -298,6 +297,45 @@ typedef struct * @} */ +/** @defgroup OPAMP_LL_EM_HELPER_MACRO OPAMP helper macro + * @{ + */ + +/** + * @brief Helper macro to select the OPAMP common instance + * to which is belonging the selected OPAMP instance. + * @note OPAMP common register instance can be used to + * set parameters common to several OPAMP instances. + * Refer to functions having argument "OPAMPxy_COMMON" as parameter. + * @param __OPAMPx__ OPAMP instance + * @retval OPAMP common instance + */ +#define __LL_OPAMP_COMMON_INSTANCE(__OPAMPx__) (OPAMP12_COMMON) + +/** + * @brief Helper macro to check if all OPAMP instances sharing the same + * OPAMP common instance are disabled. + * @note This check is required by functions with setting conditioned to + * OPAMP state: + * All OPAMP instances of the OPAMP common group must be disabled. + * Refer to functions having argument "OPAMPxy_COMMON" as parameter. + * @retval 0: All OPAMP instances sharing the same OPAMP common instance + * are disabled. + * 1: At least one OPAMP instance sharing the same OPAMP common instance + * is enabled + */ +#if defined(OPAMP1) && defined(OPAMP2) +#define __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE() \ + (LL_OPAMP_IsEnabled(OPAMP1) | \ + LL_OPAMP_IsEnabled(OPAMP2) ) +#else +#define __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE() \ + (LL_OPAMP_IsEnabled(OPAMP1)) +#endif /* defined(OPAMP1) && defined(OPAMP2) */ +/** + * @} + */ + /* Exported functions --------------------------------------------------------*/ /** @defgroup OPAMP_LL_Exported_Functions OPAMP Exported Functions * @{ @@ -325,7 +363,7 @@ typedef struct * @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_HIGH * @retval None */ -__STATIC_INLINE void LL_OPAMP_SetCommonPowerRange(OPAMP_Common_TypeDef *OPAMPxy_COMMON, uint32_t PowerRange) +__STATIC_INLINE void LL_OPAMP_SetCommonPowerRange(const OPAMP_Common_TypeDef *OPAMPxy_COMMON, uint32_t PowerRange) { /* Prevent unused parameter warning */ (void)(*OPAMPxy_COMMON); @@ -343,7 +381,7 @@ __STATIC_INLINE void LL_OPAMP_SetCommonPowerRange(OPAMP_Common_TypeDef *OPAMPxy_ * @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_LOW * @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_HIGH */ -__STATIC_INLINE uint32_t LL_OPAMP_GetCommonPowerRange(OPAMP_Common_TypeDef *OPAMPxy_COMMON) +__STATIC_INLINE uint32_t LL_OPAMP_GetCommonPowerRange(const OPAMP_Common_TypeDef *OPAMPxy_COMMON) { /* Prevent unused parameter warning */ (void)(*OPAMPxy_COMMON); @@ -386,7 +424,7 @@ __STATIC_INLINE void LL_OPAMP_SetPowerMode(OPAMP_TypeDef *OPAMPx, uint32_t Power * @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_NORMALSPEED * @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_HIGHSPEED */ -__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(const OPAMP_TypeDef *OPAMPx) { uint32_t power_mode = (READ_BIT(OPAMPx->CSR, OPAMP_POWERMODE_CSR_BIT_MASK)); @@ -432,7 +470,7 @@ __STATIC_INLINE void LL_OPAMP_SetMode(OPAMP_TypeDef *OPAMPx, uint32_t Mode) * @arg @ref LL_OPAMP_MODE_FUNCTIONAL * @arg @ref LL_OPAMP_MODE_CALIBRATION */ -__STATIC_INLINE uint32_t LL_OPAMP_GetMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetMode(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALON)); } @@ -468,7 +506,7 @@ __STATIC_INLINE void LL_OPAMP_SetFunctionalMode(OPAMP_TypeDef *OPAMPx, uint32_t * @arg @ref LL_OPAMP_MODE_FOLLOWER * @arg @ref LL_OPAMP_MODE_PGA */ -__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMODE)); } @@ -503,7 +541,7 @@ __STATIC_INLINE void LL_OPAMP_SetPGAGain(OPAMP_TypeDef *OPAMPx, uint32_t PGAGain * @arg @ref LL_OPAMP_PGA_GAIN_8 * @arg @ref LL_OPAMP_PGA_GAIN_16 */ -__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGA_GAIN)); } @@ -538,7 +576,7 @@ __STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32 * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0 * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1 */ -__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VP_SEL)); } @@ -571,7 +609,7 @@ __STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t * @arg @ref LL_OPAMP_INPUT_INVERT_IO1 * @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO */ -__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VM_SEL)); } @@ -625,7 +663,7 @@ __STATIC_INLINE void LL_OPAMP_SetTrimmingMode(OPAMP_TypeDef *OPAMPx, uint32_t Tr * @arg @ref LL_OPAMP_TRIMMING_FACTORY * @arg @ref LL_OPAMP_TRIMMING_USER */ -__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_USERTRIM)); } @@ -660,7 +698,7 @@ __STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uin * @arg @ref LL_OPAMP_TRIMMING_NMOS * @arg @ref LL_OPAMP_TRIMMING_PMOS */ -__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(const OPAMP_TypeDef *OPAMPx) { uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL)); @@ -677,7 +715,7 @@ __STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx) * @param OPAMPx OPAMP instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(const OPAMP_TypeDef *OPAMPx) { return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALOUT) == OPAMP_CSR_CALOUT) ? 1UL : 0UL); } @@ -705,7 +743,7 @@ __STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx) __STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef *OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair, uint32_t TrimmingValue) { - uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK)); + __IO uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK)); /* Set bits with position in register depending on parameter */ /* "TransistorsDiffPair". */ @@ -737,10 +775,10 @@ __STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef *OPAMPx, uint32_t P * @arg @ref LL_OPAMP_TRIMMING_PMOS * @retval 0x0...0x1F */ -__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef *OPAMPx, uint32_t PowerMode, +__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(const OPAMP_TypeDef *OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair) { - const uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK)); + const __IO uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK)); /* Retrieve bits with position in register depending on parameter */ /* "TransistorsDiffPair". */ @@ -791,7 +829,7 @@ __STATIC_INLINE void LL_OPAMP_Disable(OPAMP_TypeDef *OPAMPx) * @param OPAMPx OPAMP instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(const OPAMP_TypeDef *OPAMPx) { return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAEN) == (OPAMP_CSR_OPAEN)) ? 1UL : 0UL); } @@ -806,7 +844,7 @@ __STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx) */ ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef *OPAMPx); -ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct); +ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, const LL_OPAMP_InitTypeDef *OPAMP_InitStruct); void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct); /** diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_pka.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_pka.c index d760c697b12..149cdf47ca1 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_pka.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_pka.c @@ -87,7 +87,7 @@ * - SUCCESS: PKA registers are de-initialized * - ERROR: PKA registers are not de-initialized */ -ErrorStatus LL_PKA_DeInit(PKA_TypeDef *PKAx) +ErrorStatus LL_PKA_DeInit(const PKA_TypeDef *PKAx) { ErrorStatus status = SUCCESS; @@ -161,5 +161,3 @@ void LL_PKA_StructInit(LL_PKA_InitTypeDef *PKA_InitStruct) */ #endif /* USE_FULL_LL_DRIVER */ - - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_pka.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_pka.h index a6fe9b64e58..597d09af171 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_pka.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_pka.h @@ -97,7 +97,7 @@ typedef struct */ /** @defgroup PKA_LL_EC_MODE Operation Mode - * @brief List of opearation mode. + * @brief List of operation mode. * @{ */ #define LL_PKA_MODE_MODULAR_EXP ((uint32_t)0x00000000U) /*!< modular exponentiation */ @@ -233,7 +233,7 @@ __STATIC_INLINE void LL_PKA_Disable(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsEnabled(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsEnabled(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->CR, PKA_CR_EN) == (PKA_CR_EN)) ? 1UL : 0UL); } @@ -298,7 +298,7 @@ __STATIC_INLINE void LL_PKA_SetMode(PKA_TypeDef *PKAx, uint32_t Mode) * @arg @ref LL_PKA_MODE_ECC_MUL * @arg @ref LL_PKA_MODE_MODULAR_EXP_FAST */ -__STATIC_INLINE uint32_t LL_PKA_GetMode(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_GetMode(const PKA_TypeDef *PKAx) { return (uint32_t)(READ_BIT(PKAx->CR, PKA_CR_MODE) >> PKA_CR_MODE_Pos); } @@ -416,7 +416,7 @@ __STATIC_INLINE void LL_PKA_DisableIT_OPERR(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_ADDRERR(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_ADDRERR(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->CR, PKA_CR_ADDRERRIE) == (PKA_CR_ADDRERRIE)) ? 1UL : 0UL); } @@ -427,7 +427,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_ADDRERR(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_RAMERR(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_RAMERR(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->CR, PKA_CR_RAMERRIE) == (PKA_CR_RAMERRIE)) ? 1UL : 0UL); } @@ -438,7 +438,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_RAMERR(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_OPERR(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_OPERR(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->CR, PKA_CR_OPERRIE) == (PKA_CR_OPERRIE)) ? 1UL : 0UL); } @@ -449,7 +449,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_OPERR(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_PROCEND(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_PROCEND(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->CR, PKA_CR_PROCENDIE) == (PKA_CR_PROCENDIE)) ? 1UL : 0UL); } @@ -468,7 +468,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_PROCEND(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_ADDRERR(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_ADDRERR(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->SR, PKA_SR_ADDRERRF) == (PKA_SR_ADDRERRF)) ? 1UL : 0UL); } @@ -479,7 +479,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_ADDRERR(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_RAMERR(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_RAMERR(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->SR, PKA_SR_RAMERRF) == (PKA_SR_RAMERRF)) ? 1UL : 0UL); } @@ -490,7 +490,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_RAMERR(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_OPERR(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_OPERR(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->SR, PKA_SR_OPERRF) == (PKA_SR_OPERRF)) ? 1UL : 0UL); } @@ -501,7 +501,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_OPERR(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_PROCEND(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_PROCEND(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->SR, PKA_SR_PROCENDF) == (PKA_SR_PROCENDF)) ? 1UL : 0UL); } @@ -512,7 +512,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_PROCEND(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_BUSY(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_BUSY(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->SR, PKA_SR_BUSY) == (PKA_SR_BUSY)) ? 1UL : 0UL); } @@ -571,7 +571,7 @@ __STATIC_INLINE void LL_PKA_ClearFlag_PROCEND(PKA_TypeDef *PKAx) * @{ */ -ErrorStatus LL_PKA_DeInit(PKA_TypeDef *PKAx); +ErrorStatus LL_PKA_DeInit(const PKA_TypeDef *PKAx); ErrorStatus LL_PKA_Init(PKA_TypeDef *PKAx, LL_PKA_InitTypeDef *PKA_InitStruct); void LL_PKA_StructInit(LL_PKA_InitTypeDef *PKA_InitStruct); @@ -599,4 +599,3 @@ void LL_PKA_StructInit(LL_PKA_InitTypeDef *PKA_InitStruct); #endif #endif /* STM32U5xx_LL_PKA_H */ - diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_pwr.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_pwr.h index 6bac5703194..aec6e4aa568 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_pwr.h @@ -70,29 +70,32 @@ extern "C" { * @brief Flags defines which can be used with LL_PWR_ReadReg function * @{ */ -#define LL_PWR_FLAG_VOSRDY PWR_VOSR_VOSRDY /*!< Voltage scaling ready flag */ -#define LL_PWR_FLAG_BOOSTRDY PWR_VOSR_BOOSTRDY /*!< EPOD booster ready flag */ -#define LL_PWR_FLAG_STOPF PWR_SR_STOPF /*!< Stop flag */ -#define LL_PWR_FLAG_SBF PWR_SR_SBF /*!< Standby flag */ -#define LL_PWR_FLAG_VDDA2RDY PWR_SVMSR_VDDA2RDY /*!< VDDA ready flag (versus 1.8 V threshold) */ -#define LL_PWR_FLAG_VDDA1RDY PWR_SVMSR_VDDA1RDY /*!< VDDA ready flag (versus 1.6 V threshold) */ -#define LL_PWR_FLAG_VDDIO2RDY PWR_SVMSR_VDDIO2RDY /*!< VDDIO2 ready flag */ -#define LL_PWR_FLAG_VDDUSBRDY PWR_SVMSR_VDDUSBRDY /*!< VDDUSB ready flag */ -#define LL_PWR_FLAG_ACTVOSRDY PWR_SVMSR_ACTVOSRDY /*!< Currently applied VOS ready flag */ -#define LL_PWR_FLAG_PVDO PWR_SR2_PVDO /*!< VDD voltage detector output flag */ -#define LL_PWR_FLAG_REGS PWR_SVMSR_REGS /*!< Regulator selection flag */ -#define LL_PWR_FLAG_TEMPH PWR_BDSR_TEMPH /*!< Temperature level flag (versus high threshold) */ -#define LL_PWR_FLAG_TEMPL PWR_BDSR_TEMPL /*!< Temperature level flag (versus low threshold) */ -#define LL_PWR_FLAG_VBATH PWR_BDSR_VBATH /*!< Backup domain voltage level flag (versus high threshold) */ - -#define LL_PWR_WAKEUP_FLAG1 PWR_WUSR_WUF1 /*!< Wakeup flag 1 */ -#define LL_PWR_WAKEUP_FLAG2 PWR_WUSR_WUF2 /*!< Wakeup flag 2 */ -#define LL_PWR_WAKEUP_FLAG3 PWR_WUSR_WUF3 /*!< Wakeup flag 3 */ -#define LL_PWR_WAKEUP_FLAG4 PWR_WUSR_WUF4 /*!< Wakeup flag 4 */ -#define LL_PWR_WAKEUP_FLAG5 PWR_WUSR_WUF5 /*!< Wakeup flag 5 */ -#define LL_PWR_WAKEUP_FLAG6 PWR_WUSR_WUF6 /*!< Wakeup flag 6 */ -#define LL_PWR_WAKEUP_FLAG7 PWR_WUSR_WUF7 /*!< Wakeup flag 7 */ -#define LL_PWR_WAKEUP_FLAG8 PWR_WUSR_WUF8 /*!< Wakeup flag 8 */ +#define LL_PWR_FLAG_VOSRDY PWR_VOSR_VOSRDY /*!< Voltage scaling ready flag */ +#define LL_PWR_FLAG_BOOSTRDY PWR_VOSR_BOOSTRDY /*!< VOS EPOD booster ready flag */ +#if defined (PWR_VOSR_USBBOOSTRDY) +#define LL_PWR_FLAG_USBBOOSTRDY PWR_VOSR_USBBOOSTRDY /*!< USB EPOD booster ready flag */ +#endif /* defined (PWR_VOSR_USBBOOSTRDY) */ +#define LL_PWR_FLAG_STOPF PWR_SR_STOPF /*!< Stop flag */ +#define LL_PWR_FLAG_SBF PWR_SR_SBF /*!< Standby flag */ +#define LL_PWR_FLAG_VDDA2RDY PWR_SVMSR_VDDA2RDY /*!< VDDA ready flag (versus 1.8 V threshold) */ +#define LL_PWR_FLAG_VDDA1RDY PWR_SVMSR_VDDA1RDY /*!< VDDA ready flag (versus 1.6 V threshold) */ +#define LL_PWR_FLAG_VDDIO2RDY PWR_SVMSR_VDDIO2RDY /*!< VDDIO2 ready flag */ +#define LL_PWR_FLAG_VDDUSBRDY PWR_SVMSR_VDDUSBRDY /*!< VDDUSB ready flag */ +#define LL_PWR_FLAG_ACTVOSRDY PWR_SVMSR_ACTVOSRDY /*!< Currently applied VOS ready flag */ +#define LL_PWR_FLAG_PVDO PWR_SR2_PVDO /*!< VDD voltage detector output flag */ +#define LL_PWR_FLAG_REGS PWR_SVMSR_REGS /*!< Regulator selection flag */ +#define LL_PWR_FLAG_TEMPH PWR_BDSR_TEMPH /*!< Temperature level flag (versus high threshold) */ +#define LL_PWR_FLAG_TEMPL PWR_BDSR_TEMPL /*!< Temperature level flag (versus low threshold) */ +#define LL_PWR_FLAG_VBATH PWR_BDSR_VBATH /*!< Backup domain voltage level flag (versus high threshold) */ + +#define LL_PWR_WAKEUP_FLAG1 PWR_WUSR_WUF1 /*!< Wakeup flag 1 */ +#define LL_PWR_WAKEUP_FLAG2 PWR_WUSR_WUF2 /*!< Wakeup flag 2 */ +#define LL_PWR_WAKEUP_FLAG3 PWR_WUSR_WUF3 /*!< Wakeup flag 3 */ +#define LL_PWR_WAKEUP_FLAG4 PWR_WUSR_WUF4 /*!< Wakeup flag 4 */ +#define LL_PWR_WAKEUP_FLAG5 PWR_WUSR_WUF5 /*!< Wakeup flag 5 */ +#define LL_PWR_WAKEUP_FLAG6 PWR_WUSR_WUF6 /*!< Wakeup flag 6 */ +#define LL_PWR_WAKEUP_FLAG7 PWR_WUSR_WUF7 /*!< Wakeup flag 7 */ +#define LL_PWR_WAKEUP_FLAG8 PWR_WUSR_WUF8 /*!< Wakeup flag 8 */ /** * @} */ @@ -126,12 +129,30 @@ extern "C" { /** @defgroup PWR_LL_EC_SRAM1_STOP_CONTENTS_RETENTION PWR SRAM1 Content Retention in Stop Mode * @{ */ -#define LL_PWR_SRAM1_STOP_NO_RETENTION 0U /*!< SRAM1 no retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM1_STOP_PAGE1_RETENTION (PWR_CR2_SRAM1PDS1) /*!< SRAM1 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM1_STOP_PAGE2_RETENTION (PWR_CR2_SRAM1PDS2) /*!< SRAM1 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM1_STOP_PAGE3_RETENTION (PWR_CR2_SRAM1PDS3) /*!< SRAM1 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM1_STOP_1_3_RETENTION (PWR_CR2_SRAM1PDS1 | PWR_CR2_SRAM1PDS2 | \ - PWR_CR2_SRAM1PDS3) /*!< SRAM1 pages (1 to 3) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM1_STOP_NO_RETENTION 0U /*!< SRAM1 no retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM1_STOP_PAGE1_RETENTION (PWR_CR2_SRAM1PDS1) /*!< SRAM1 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM1_STOP_PAGE2_RETENTION (PWR_CR2_SRAM1PDS2) /*!< SRAM1 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM1_STOP_PAGE3_RETENTION (PWR_CR2_SRAM1PDS3) /*!< SRAM1 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#if defined (PWR_CR4_SRAM1PDS4) +#define LL_PWR_SRAM1_STOP_PAGE4_RETENTION (PWR_CR4_SRAM1PDS4) /*!< SRAM1 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM1_STOP_PAGE5_RETENTION (PWR_CR4_SRAM1PDS5) /*!< SRAM1 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM1_STOP_PAGE6_RETENTION (PWR_CR4_SRAM1PDS6) /*!< SRAM1 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM1_STOP_PAGE7_RETENTION (PWR_CR4_SRAM1PDS7) /*!< SRAM1 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM1_STOP_PAGE8_RETENTION (PWR_CR4_SRAM1PDS8) /*!< SRAM1 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM1_STOP_PAGE9_RETENTION (PWR_CR4_SRAM1PDS9) /*!< SRAM1 page 9 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM1_STOP_PAGE10_RETENTION (PWR_CR4_SRAM1PDS10) /*!< SRAM1 page 10 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM1_STOP_PAGE11_RETENTION (PWR_CR4_SRAM1PDS11) /*!< SRAM1 page 11 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM1_STOP_PAGE12_RETENTION (PWR_CR4_SRAM1PDS12) /*!< SRAM1 page 12 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR4_SRAM1PDS4) */ +#define LL_PWR_SRAM1_STOP_1_3_RETENTION (PWR_CR2_SRAM1PDS1 | PWR_CR2_SRAM1PDS2 | \ + PWR_CR2_SRAM1PDS3) /*!< SRAM1 pages (1 to 3) retention in Stop mode (Stop 0, 1, 2, 3) */ +#if defined (PWR_CR4_SRAM1PDS4) +#define LL_PWR_SRAM1_STOP_4_12_RETENTION (PWR_CR4_SRAM1PDS4 | PWR_CR4_SRAM1PDS5 | \ + PWR_CR4_SRAM1PDS6 | PWR_CR4_SRAM1PDS7 | \ + PWR_CR4_SRAM1PDS8 | PWR_CR4_SRAM1PDS9 | \ + PWR_CR4_SRAM1PDS10 | PWR_CR4_SRAM1PDS11 | \ + PWR_CR4_SRAM1PDS12) /*!< SRAM1 pages (4 to 12) retention in Stop mode (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR4_SRAM1PDS4) */ /** * @} */ @@ -147,24 +168,37 @@ extern "C" { * @} */ +#if defined (PWR_CR2_SRAM3PDS1) /** @defgroup PWR_LL_EC_SRAM3_STOP_CONTENTS_RETENTION PWR SRAM3 Content Retention in Stop Mode * @{ */ -#define LL_PWR_SRAM3_STOP_NO_RETENTION 0U /*!< SRAM3 no retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM3_STOP_PAGE1_RETENTION (PWR_CR2_SRAM3PDS1) /*!< SRAM3 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM3_STOP_PAGE2_RETENTION (PWR_CR2_SRAM3PDS2) /*!< SRAM3 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM3_STOP_PAGE3_RETENTION (PWR_CR2_SRAM3PDS3) /*!< SRAM3 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM3_STOP_PAGE4_RETENTION (PWR_CR2_SRAM3PDS4) /*!< SRAM3 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM3_STOP_PAGE5_RETENTION (PWR_CR2_SRAM3PDS5) /*!< SRAM3 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM3_STOP_PAGE6_RETENTION (PWR_CR2_SRAM3PDS6) /*!< SRAM3 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM3_STOP_PAGE7_RETENTION (PWR_CR2_SRAM3PDS7) /*!< SRAM3 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM3_STOP_PAGE8_RETENTION (PWR_CR2_SRAM3PDS8) /*!< SRAM3 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_NO_RETENTION 0U /*!< SRAM3 no retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE1_RETENTION (PWR_CR2_SRAM3PDS1) /*!< SRAM3 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE2_RETENTION (PWR_CR2_SRAM3PDS2) /*!< SRAM3 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE3_RETENTION (PWR_CR2_SRAM3PDS3) /*!< SRAM3 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE4_RETENTION (PWR_CR2_SRAM3PDS4) /*!< SRAM3 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE5_RETENTION (PWR_CR2_SRAM3PDS5) /*!< SRAM3 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE6_RETENTION (PWR_CR2_SRAM3PDS6) /*!< SRAM3 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE7_RETENTION (PWR_CR2_SRAM3PDS7) /*!< SRAM3 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE8_RETENTION (PWR_CR2_SRAM3PDS8) /*!< SRAM3 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#if defined (PWR_CR4_SRAM3PDS9) +#define LL_PWR_SRAM3_STOP_PAGE9_RETENTION (PWR_CR4_SRAM3PDS9) /*!< SRAM3 page 9 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE10_RETENTION (PWR_CR4_SRAM3PDS10) /*!< SRAM3 page 10 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE11_RETENTION (PWR_CR4_SRAM3PDS11) /*!< SRAM3 page 11 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE12_RETENTION (PWR_CR4_SRAM3PDS12) /*!< SRAM3 page 12 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM3_STOP_PAGE13_RETENTION (PWR_CR4_SRAM3PDS13) /*!< SRAM3 page 13 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR4_SRAM3PDS9) */ #define LL_PWR_SRAM3_STOP_1_8_RETENTION (PWR_CR2_SRAM3PDS1 | PWR_CR2_SRAM3PDS2 | PWR_CR2_SRAM3PDS3 | \ PWR_CR2_SRAM3PDS4 | PWR_CR2_SRAM3PDS5 | PWR_CR2_SRAM3PDS6 | \ - PWR_CR2_SRAM3PDS7 | PWR_CR2_SRAM3PDS8) /*!< SRAM3 pages (1 to 8) retention in Stop modes (Stop 0, 1, 2, 3) */ + PWR_CR2_SRAM3PDS7 | PWR_CR2_SRAM3PDS8) /*!< SRAM3 pages (1 to 8) retention in Stop modes (Stop 0, 1, 2, 3) */ +#if defined (PWR_CR4_SRAM3PDS9) +#define LL_PWR_SRAM3_STOP_9_13_RETENTION (PWR_CR4_SRAM3PDS9 | PWR_CR4_SRAM3PDS10 | PWR_CR4_SRAM3PDS11 | \ + PWR_CR4_SRAM3PDS12 | PWR_CR4_SRAM3PDS13) /*!< SRAM3 pages (9 to 13) retention in Stop modes (Stop 0, 1, 2, 3) */ +#endif /* defined (PWR_CR4_SRAM3PDS9) */ /** * @} */ +#endif /* PWR_CR2_SRAM3PDS1 */ /** @defgroup PWR_LL_EC_SRAM4_STOP_CONTENTS_RETENTION PWR SRAM4 Content Retention in Stop Mode * @{ @@ -175,6 +209,56 @@ extern "C" { * @} */ +#if defined (PWR_CR4_SRAM5PDS1) +/** @defgroup PWR_LL_EC_SRAM5_STOP_CONTENTS_RETENTION PWR SRAM5 Content Retention in Stop Mode + * @{ + */ +#define LL_PWR_SRAM5_STOP_NO_RETENTION 0U /*!< SRAM5 no retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE1_RETENTION (PWR_CR4_SRAM5PDS1) /*!< SRAM5 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE2_RETENTION (PWR_CR4_SRAM5PDS2) /*!< SRAM5 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE3_RETENTION (PWR_CR4_SRAM5PDS3) /*!< SRAM5 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE4_RETENTION (PWR_CR4_SRAM5PDS4) /*!< SRAM5 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE5_RETENTION (PWR_CR4_SRAM5PDS5) /*!< SRAM5 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE6_RETENTION (PWR_CR4_SRAM5PDS6) /*!< SRAM5 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE7_RETENTION (PWR_CR4_SRAM5PDS7) /*!< SRAM5 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE8_RETENTION (PWR_CR4_SRAM5PDS8) /*!< SRAM5 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE9_RETENTION (PWR_CR4_SRAM5PDS9) /*!< SRAM5 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE10_RETENTION (PWR_CR4_SRAM5PDS10) /*!< SRAM5 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE11_RETENTION (PWR_CR4_SRAM5PDS11) /*!< SRAM5 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE12_RETENTION (PWR_CR4_SRAM5PDS12) /*!< SRAM5 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_PAGE13_RETENTION (PWR_CR4_SRAM5PDS13) /*!< SRAM5 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM5_STOP_FULL_RETENTION (PWR_CR4_SRAM5PDS1 | PWR_CR4_SRAM5PDS2 | PWR_CR4_SRAM5PDS3 | \ + PWR_CR4_SRAM5PDS4 | PWR_CR4_SRAM5PDS5 | PWR_CR4_SRAM5PDS6 | \ + PWR_CR4_SRAM5PDS7 | PWR_CR4_SRAM5PDS8 | PWR_CR4_SRAM5PDS9 | \ + PWR_CR4_SRAM5PDS10 | PWR_CR4_SRAM5PDS11 | PWR_CR4_SRAM5PDS12 | \ + PWR_CR4_SRAM5PDS13) /*!< SRAM5 pages (1 to 13) retention in Stop modes (Stop 0, 1, 2, 3) */ +/** + * @} + */ +#endif /* defined (PWR_CR4_SRAM5PDS1) */ + +#if defined (PWR_CR5_SRAM6PDS1) +/** @defgroup PWR_LL_EC_SRAM6_STOP_CONTENTS_RETENTION PWR SRAM6 Content Retention in Stop Mode + * @{ + */ +#define LL_PWR_SRAM6_STOP_NO_RETENTION 0U /*!< SRAM6 no retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM6_STOP_PAGE1_RETENTION (PWR_CR5_SRAM6PDS1) /*!< SRAM6 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM6_STOP_PAGE2_RETENTION (PWR_CR5_SRAM6PDS2) /*!< SRAM6 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM6_STOP_PAGE3_RETENTION (PWR_CR5_SRAM6PDS3) /*!< SRAM6 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM6_STOP_PAGE4_RETENTION (PWR_CR5_SRAM6PDS4) /*!< SRAM6 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM6_STOP_PAGE5_RETENTION (PWR_CR5_SRAM6PDS5) /*!< SRAM6 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM6_STOP_PAGE6_RETENTION (PWR_CR5_SRAM6PDS6) /*!< SRAM6 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM6_STOP_PAGE7_RETENTION (PWR_CR5_SRAM6PDS7) /*!< SRAM6 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM6_STOP_PAGE8_RETENTION (PWR_CR5_SRAM6PDS8) /*!< SRAM6 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ +#define LL_PWR_SRAM6_STOP_FULL_RETENTION (PWR_CR5_SRAM6PDS1 | PWR_CR5_SRAM6PDS2 | PWR_CR5_SRAM6PDS3 | \ + PWR_CR5_SRAM6PDS4 | PWR_CR5_SRAM6PDS5 | PWR_CR5_SRAM6PDS6 | \ + PWR_CR5_SRAM6PDS7 | PWR_CR5_SRAM6PDS8) + /*!< SRAM6 pages (1 to 8) retention in Stop modes (Stop 0, 1, 2, 3) */ +/** + * @} + */ +#endif /* defined (PWR_CR5_SRAM6PDS1) */ + /** @defgroup PWR_LL_EC_ICACHERAM_STOP_CONTENTS_RETENTION PWR ICACHE Content Retention in Stop Mode * @{ */ @@ -193,6 +277,18 @@ extern "C" { * @} */ +#if defined (PWR_CR2_DC2RAMPDS) +/** @defgroup PWR_LL_EC_DCACHE2RAM_STOP_CONTENTS_RETENTION PWR DCACHE2 Content Retention in Stop Mode + * @{ + */ +#define LL_PWR_DCACHE2RAM_STOP_NO_RETENTION 0U /*!< DCACHE2 SRAM no retention in Stop mode (Stop 0, 1, 2) */ +#define LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION PWR_CR2_DC2RAMPDS /*!< DCACHE2 SRAM retention in Stop mode (Stop 0, 1, 2) */ +/** + * @} + */ +#endif /* defined (PWR_CR2_DC2RAMPDS) */ + +#if defined (PWR_CR2_DMA2DRAMPDS) /** @defgroup PWR_LL_EC_DMA2DRAM_STOP_CONTENTS_RETENTION PWR DMA2DRAM Content Retention in Stop Mode * @{ */ @@ -201,6 +297,7 @@ extern "C" { /** * @} */ +#endif /* PWR_CR2_DMA2DRAMPDS */ /** @defgroup PWR_LL_EC_PERIPHRAM_STOP_CONTENTS_RETENTION PWR PERIPHRAM Content Retention in Stop Mode * @{ @@ -220,6 +317,39 @@ extern "C" { * @} */ +#if defined (PWR_CR2_GPRAMPDS) +/** @defgroup PWR_LL_EC_GPRAM_STOP_CONTENTS_RETENTION PWR GPRAM Content Retention in Stop Mode + * @{ + */ +#define LL_PWR_GRAPHICPERIPHRAM_STOP_NO_RETENTION 0U /*!< Graphic peripherals (LTDC, GFXMMU) SRAM no retention in Stop mode (Stop 0, 1, 2) */ +#define LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION PWR_CR2_GPRAMPDS /*!< Graphic peripherals (LTDC, GFXMMU) SRAM retention in Stop mode (Stop 0, 1, 2) */ +/** + * @} + */ +#endif /* defined (PWR_CR2_GPRAMPDS) */ + +#if defined (PWR_CR2_DSIRAMPDS) +/** @defgroup PWR_LL_EC_DSIRAM_STOP_CONTENTS_RETENTION PWR DSI RAM Content Retention in Stop Mode + * @{ + */ +#define LL_PWR_DSIRAM_STOP_NO_RETENTION 0U /*!< DSI SRAM no retention in Stop mode (Stop 0, 1, 2) */ +#define LL_PWR_DSIRAM_STOP_FULL_RETENTION PWR_CR2_DSIRAMPDS /*!< DSI SRAM retention in Stop mode (Stop 0, 1, 2) */ +/** + * @} + */ +#endif /* defined (PWR_CR2_JPEGRAMPDS) */ + +#if defined (PWR_CR2_JPEGRAMPDS) +/** @defgroup PWR_LL_EC_JPEGRAM_STOP_CONTENTS_RETENTION PWR JPEG RAM Content Retention in Stop Mode + * @{ + */ +#define LL_PWR_JPEGRAM_STOP_NO_RETENTION 0U /*!< JPEG SRAM no retention in Stop mode (Stop 0, 1, 2) */ +#define LL_PWR_JPEGRAM_STOP_FULL_RETENTION PWR_CR2_JPEGRAMPDS /*!< JPEG SRAM retention in Stop mode (Stop 0, 1, 2) */ +/** + * @} + */ +#endif /* defined (PWR_CR2_JPEGRAMPDS) */ + /** @defgroup PWR_LL_EC_SRAM1_RUN_CONTENTS_RETENTION PWR SRAM1 Content Retention in Run Mode * @{ */ @@ -238,6 +368,7 @@ extern "C" { * @} */ +#if defined (PWR_CR1_SRAM3PD) /** @defgroup PWR_LL_EC_SRAM3_RUN_CONTENTS_RETENTION PWR SRAM3 Content Retention in Run Mode * @{ */ @@ -246,6 +377,7 @@ extern "C" { /** * @} */ +#endif /* PWR_CR1_SRAM3PD */ /** @defgroup PWR_LL_EC_SRAM4_RUN_CONTENTS_RETENTION PWR SRAM4 Content Retention in Run Mode * @{ @@ -256,6 +388,28 @@ extern "C" { * @} */ +#if defined (PWR_CR1_SRAM5PD) +/** @defgroup PWR_LL_EC_SRAM5_RUN_CONTENTS_RETENTION PWR SRAM5 Content Retention in Run Mode + * @{ + */ +#define LL_PWR_SRAM5_RUN_NO_RETENTION 0U /*!< SRAM5 no retention in Run mode */ +#define LL_PWR_SRAM5_RUN_FULL_RETENTION PWR_CR1_SRAM5PD /*!< SRAM5 retention in Run mode */ +/** + * @} + */ +#endif /* defined (PWR_CR1_SRAM5PD) */ + +#if defined (PWR_CR1_SRAM6PD) +/** @defgroup PWR_LL_EC_SRAM6_RUN_CONTENTS_RETENTION PWR SRAM6 Content Retention in Run Mode + * @{ + */ +#define LL_PWR_SRAM6_RUN_NO_RETENTION 0U /*!< SRAM6 no retention in Run mode */ +#define LL_PWR_SRAM6_RUN_FULL_RETENTION PWR_CR1_SRAM6PD /*!< SRAM6 retention in Run mode */ +/** + * @} + */ +#endif /* defined (PWR_CR1_SRAM6PD) */ + /** @defgroup PWR_LL_EC_SRD_MODE PWR Smart Run Domain Mode * @{ */ @@ -344,10 +498,17 @@ extern "C" { #define LL_PWR_GPIO_PORTC (&(PWR->PUCRC)) /*!< GPIO port C */ #define LL_PWR_GPIO_PORTD (&(PWR->PUCRD)) /*!< GPIO port D */ #define LL_PWR_GPIO_PORTE (&(PWR->PUCRE)) /*!< GPIO port E */ +#ifdef PWR_PUCRF_PU0 #define LL_PWR_GPIO_PORTF (&(PWR->PUCRF)) /*!< GPIO port F */ +#endif /* PWR_PUCRF_PU0 */ #define LL_PWR_GPIO_PORTG (&(PWR->PUCRG)) /*!< GPIO port G */ #define LL_PWR_GPIO_PORTH (&(PWR->PUCRH)) /*!< GPIO port H */ +#ifdef PWR_PUCRI_PU0 #define LL_PWR_GPIO_PORTI (&(PWR->PUCRI)) /*!< GPIO port I */ +#endif /* PWR_PUCRI_PU0 */ +#if defined (PWR_PUCRJ_PU0) +#define LL_PWR_GPIO_PORTJ (&(PWR->PUCRJ)) /*!< GPIO port J */ +#endif /* defined (PWR_PUCRJ_PU0) */ /** * @} */ @@ -597,6 +758,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetSRAM2RunRetention(void) return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM2_RUN_FULL_RETENTION))) & LL_PWR_SRAM2_RUN_FULL_RETENTION); } +#if defined (PWR_CR1_SRAM3PD) /** * @brief Set the SRAM3 retention in Run mode. * @rmtoll CR1 SRAM3PD LL_PWR_SetSRAM3RunRetention\n @@ -621,6 +783,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetSRAM3RunRetention(void) { return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM3_RUN_FULL_RETENTION))) & LL_PWR_SRAM3_RUN_FULL_RETENTION); } +#endif /* PWR_CR1_SRAM3PD */ /** * @brief Set the SRAM4 retention in Run mode. @@ -647,6 +810,92 @@ __STATIC_INLINE uint32_t LL_PWR_GetSRAM4RunRetention(void) return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM4_RUN_FULL_RETENTION))) & LL_PWR_SRAM4_RUN_FULL_RETENTION); } +#if defined (PWR_CR1_SRAM5PD) +/** + * @brief Set the SRAM5 retention in Run mode. + * @rmtoll CR1 SRAM5PD LL_PWR_SetSRAM5RunRetention\n + * @param SRAM5Retention : This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM5_RUN_NO_RETENTION + * @arg @ref LL_PWR_SRAM5_RUN_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM5RunRetention(uint32_t SRAM5Retention) +{ + MODIFY_REG(PWR->CR1, LL_PWR_SRAM5_RUN_FULL_RETENTION, ((~SRAM5Retention) & LL_PWR_SRAM5_RUN_FULL_RETENTION)); +} + +/** + * @brief Get the SRAM5 retention in Run mode. + * @rmtoll CR1 SRAM5PD LL_PWR_GetSRAM5RunRetention\n + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM5_RUN_NO_RETENTION + * @arg @ref LL_PWR_SRAM5_RUN_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM5RunRetention(void) +{ + return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM5_RUN_FULL_RETENTION))) & LL_PWR_SRAM5_RUN_FULL_RETENTION); +} +#endif /* defined (PWR_CR1_SRAM5PD) */ + +#if defined (PWR_CR1_SRAM6PD) +/** + * @brief Set the SRAM6 retention in Run mode. + * @rmtoll CR1 SRAM6PD LL_PWR_SetSRAM6RunRetention\n + * @param SRAM6Retention : This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM6_RUN_NO_RETENTION + * @arg @ref LL_PWR_SRAM6_RUN_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM6RunRetention(uint32_t SRAM6Retention) +{ + MODIFY_REG(PWR->CR1, LL_PWR_SRAM6_RUN_FULL_RETENTION, ((~SRAM6Retention) & LL_PWR_SRAM6_RUN_FULL_RETENTION)); +} + +/** + * @brief Get the SRAM6 retention in Run mode. + * @rmtoll CR1 SRAM6PD LL_PWR_GetSRAM6RunRetention\n + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM6_RUN_NO_RETENTION + * @arg @ref LL_PWR_SRAM6_RUN_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM6RunRetention(void) +{ + return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM6_RUN_FULL_RETENTION))) & LL_PWR_SRAM6_RUN_FULL_RETENTION); +} +#endif /* defined (PWR_CR1_SRAM6PD) */ + +#if defined (PWR_CR1_FORCE_USBPWR) +/** + * @brief Enable OTG_HS PHY power during low power modes (Stop2, Stop 3 and Standby). + * @rmtoll CR1 FORCE_USBPWR LL_PWR_EnableOTGHSPHYLowPowerRetention + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableOTGHSPHYLowPowerRetention(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR); +} + +/** + * @brief Disable OTG_HS PHY power during low power modes (Stop2, Stop 3 and Standby). + * @rmtoll CR1 FORCE_USBPWR LL_PWR_DisableOTGHSPHYLowPowerRetention + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableOTGHSPHYLowPowerRetention(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR); +} + +/** + * @brief Check if OTG_HS PHY power during low power modes (Stop2, Stop 3 and Standby) is enabled. + * @rmtoll CR1 FORCE_USBPWR LL_PWR_IsEnabledOTGHSPHYLowPowerRetention + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledOTGHSPHYLowPowerRetention(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR) == (PWR_CR1_FORCE_USBPWR)) ? 1UL : 0UL); +} +#endif /* defined (PWR_CR1_FORCE_USBPWR) */ + /** * @brief Set the SRAM1 page(s) (From page 1 to page 3) retention in Stop mode. * @rmtoll CR2 SRAM1PDS1 LL_PWR_SetSRAM1StopRetention_1_3\n @@ -666,6 +915,39 @@ __STATIC_INLINE void LL_PWR_SetSRAM1StopRetention_1_3(uint32_t SRAM1PageRetentio MODIFY_REG(PWR->CR2, LL_PWR_SRAM1_STOP_1_3_RETENTION, ((~SRAM1PageRetention) & LL_PWR_SRAM1_STOP_1_3_RETENTION)); } +#if defined (PWR_CR4_SRAM1PDS4) +/** + * @brief Set the SRAM1 page(s) (From page 4 to page 12) retention in Stop mode. + * @rmtoll CR2 SRAM1PDS4 LL_PWR_SetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS5 LL_PWR_SetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS6 LL_PWR_SetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS7 LL_PWR_SetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS8 LL_PWR_SetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS9 LL_PWR_SetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS10 LL_PWR_SetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS11 LL_PWR_SetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS12 LL_PWR_SetSRAM1StopRetention_4_12 + * @param SRAM1PageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_4_12_RETENTION + * Or can be a combination of the following values: + * @arg @ref LL_PWR_SRAM1_STOP_PAGE4_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE5_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE6_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE7_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE8_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE9_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE10_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE11_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE12_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM1StopRetention_4_12(uint32_t SRAM1PageRetention) +{ + MODIFY_REG(PWR->CR4, LL_PWR_SRAM1_STOP_4_12_RETENTION, ((~SRAM1PageRetention) & LL_PWR_SRAM1_STOP_4_12_RETENTION)); +} +#endif /* defined (PWR_CR4_SRAM1PDS4) */ + /** * @brief Get the SRAM1 page(s) (From page 1 to page 3) retention in Stop mode. * @rmtoll CR2 SRAM1PDS1 LL_PWR_GetSRAM1StopRetention_1_3\n @@ -684,6 +966,38 @@ __STATIC_INLINE uint32_t LL_PWR_GetSRAM1StopRetention_1_3(void) return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM1_STOP_1_3_RETENTION))) & LL_PWR_SRAM1_STOP_1_3_RETENTION); } +#if defined (PWR_CR4_SRAM1PDS4) +/** + * @brief Get the SRAM1 page(s) (From page 4 to page 12) retention in Stop mode. + * @rmtoll CR2 SRAM1PDS4 LL_PWR_GetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS5 LL_PWR_GetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS6 LL_PWR_GetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS7 LL_PWR_GetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS8 LL_PWR_GetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS9 LL_PWR_GetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS10 LL_PWR_GetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS11 LL_PWR_GetSRAM1StopRetention_4_12\n + * @rmtoll CR2 SRAM1PDS12 LL_PWR_GetSRAM1StopRetention_4_12 + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_4_12_RETENTION + * Or a combination of the following values: + * @arg @ref LL_PWR_SRAM1_STOP_PAGE4_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE5_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE6_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE7_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE8_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE9_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE10_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE11_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_PAGE12_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM1StopRetention_4_12(void) +{ + return ((~(READ_BIT(PWR->CR4, LL_PWR_SRAM1_STOP_4_12_RETENTION))) & LL_PWR_SRAM1_STOP_4_12_RETENTION); +} +#endif /* defined (PWR_CR4_SRAM1PDS4) */ + /** * @brief Set the SRAM2 page(s) retention in Stop mode. * @rmtoll CR2 SRAM2PDS1 LL_PWR_SetSRAM2StopRetention\n @@ -715,6 +1029,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetSRAM2StopRetention(void) return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM2_STOP_FULL_RETENTION))) & LL_PWR_SRAM2_STOP_FULL_RETENTION); } +#if defined (PWR_CR2_SRAM3PDS1) /** * @brief Set the SRAM3 page(s) (From page 1 to page 8) retention in Stop mode. * @rmtoll CR2 SRAM3PDS1 LL_PWR_SetSRAM3StopRetention_1_8\n @@ -744,6 +1059,31 @@ __STATIC_INLINE void LL_PWR_SetSRAM3StopRetention_1_8(uint32_t SRAM3PageRetentio MODIFY_REG(PWR->CR2, LL_PWR_SRAM3_STOP_1_8_RETENTION, ((~SRAM3PageRetention) & LL_PWR_SRAM3_STOP_1_8_RETENTION)); } +#if defined (PWR_CR4_SRAM3PDS9) +/** + * @brief Set the SRAM3 page(s) (From page 9 to page 13) retention in Stop mode. + * @rmtoll CR2 SRAM3PDS9 LL_PWR_SetSRAM3StopRetention_9_13\n + * @rmtoll CR2 SRAM3PDS10 LL_PWR_SetSRAM3StopRetention_9_13\n + * @rmtoll CR2 SRAM3PDS11 LL_PWR_SetSRAM3StopRetention_9_13\n + * @rmtoll CR2 SRAM3PDS12 LL_PWR_SetSRAM3StopRetention_9_13\n + * @rmtoll CR2 SRAM3PDS13 LL_PWR_SetSRAM3StopRetention_9_13 + * @param SRAM3PageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM3_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_9_13_RETENTION + * Or can be a combination of the following values: + * @arg @ref LL_PWR_SRAM3_STOP_PAGE9_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE10_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE11_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE12_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE13_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM3StopRetention_9_13(uint32_t SRAM3PageRetention) +{ + MODIFY_REG(PWR->CR4, LL_PWR_SRAM3_STOP_9_13_RETENTION, ((~SRAM3PageRetention) & LL_PWR_SRAM3_STOP_9_13_RETENTION)); +} +#endif /* defined (PWR_CR4_SRAM3PDS9) */ + /** * @brief Get the SRAM3 page(s) (From page 1 to page 8) retention in Stop mode. * @rmtoll CR2 SRAM3PDS1 LL_PWR_GetSRAM3StopRetention_1_8\n @@ -772,6 +1112,31 @@ __STATIC_INLINE uint32_t LL_PWR_GetSRAM3StopRetention_1_8(void) return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM3_STOP_1_8_RETENTION))) & LL_PWR_SRAM3_STOP_1_8_RETENTION); } +#if defined (PWR_CR4_SRAM3PDS9) +/** + * @brief Get the SRAM3 page(s) (From page 9 to page 13) retention in Stop mode. + * @rmtoll CR2 SRAM3PDS9 LL_PWR_SetSRAM3StopRetention_9_13\n + * @rmtoll CR2 SRAM3PDS10 LL_PWR_SetSRAM3StopRetention_9_13\n + * @rmtoll CR2 SRAM3PDS11 LL_PWR_SetSRAM3StopRetention_9_13\n + * @rmtoll CR2 SRAM3PDS12 LL_PWR_SetSRAM3StopRetention_9_13\n + * @rmtoll CR2 SRAM3PDS13 LL_PWR_SetSRAM3StopRetention_9_13 + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM3_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_9_13_RETENTION + * Or can be a combination of the following values: + * @arg @ref LL_PWR_SRAM3_STOP_PAGE9_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE10_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE11_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE12_RETENTION + * @arg @ref LL_PWR_SRAM3_STOP_PAGE13_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM3StopRetention_9_13(void) +{ + return ((~(READ_BIT(PWR->CR4, LL_PWR_SRAM3_STOP_9_13_RETENTION))) & LL_PWR_SRAM3_STOP_9_13_RETENTION); +} +#endif /* defined (PWR_CR4_SRAM3PDS9) */ +#endif /* PWR_CR2_SRAM3PDS1 */ + /** * @brief Set the SRAM4 page retention in Stop mode. * @rmtoll CR2 SRAM4PDS LL_PWR_SetSRAM4StopRetention\n @@ -797,6 +1162,144 @@ __STATIC_INLINE uint32_t LL_PWR_GetSRAM4StopRetention(void) return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM4_STOP_FULL_RETENTION))) & LL_PWR_SRAM4_STOP_FULL_RETENTION); } +#if defined (PWR_CR4_SRAM5PDS1) +/** + * @brief Set the SRAM5 page(s) retention in Stop mode. + * @rmtoll CR4 SRAM5PDS1 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS2 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS3 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS4 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS5 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS6 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS7 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS8 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS9 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS10 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS11 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS12 LL_PWR_SetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS13 LL_PWR_SetSRAM5StopRetention + * @param SRAM5PageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM5_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_FULL_RETENTION + * Or can be a combination of the following values: + * @arg @ref LL_PWR_SRAM5_STOP_PAGE1_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE2_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE3_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE4_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE5_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE6_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE7_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE8_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE9_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE10_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE11_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE12_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE13_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM5StopRetention(uint32_t SRAM5PageRetention) +{ + MODIFY_REG(PWR->CR4, LL_PWR_SRAM5_STOP_FULL_RETENTION, ((~SRAM5PageRetention) & LL_PWR_SRAM5_STOP_FULL_RETENTION)); +} + +/** + * @brief Get the SRAM5 page(s) retention in Stop mode. + * @rmtoll CR4 SRAM5PDS1 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS2 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS3 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS4 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS5 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS6 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS7 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS8 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS9 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS10 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS11 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS12 LL_PWR_GetSRAM5StopRetention\n + * @rmtoll CR4 SRAM5PDS13 LL_PWR_GetSRAM5StopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM5_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_FULL_RETENTION + * Or can be a combination of the following values: + * @arg @ref LL_PWR_SRAM5_STOP_PAGE1_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE2_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE3_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE4_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE5_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE6_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE7_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE8_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE9_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE10_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE11_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE12_RETENTION + * @arg @ref LL_PWR_SRAM5_STOP_PAGE13_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM5StopRetention(void) +{ + return ((~(READ_BIT(PWR->CR4, LL_PWR_SRAM5_STOP_FULL_RETENTION))) & LL_PWR_SRAM5_STOP_FULL_RETENTION); +} +#endif /* defined (PWR_CR4_SRAM5PDS1) */ + +#if defined (PWR_CR5_SRAM6PDS1) +/** + * @brief Set the SRAM6 page(s) retention in Stop mode. + * @rmtoll CR5 SRAM6PDS1 LL_PWR_SetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS2 LL_PWR_SetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS3 LL_PWR_SetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS4 LL_PWR_SetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS5 LL_PWR_SetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS6 LL_PWR_SetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS7 LL_PWR_SetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS8 LL_PWR_SetSRAM6StopRetention + * @param SRAM5PageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM6_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_FULL_RETENTION + * Or can be a combination of the following values: + * @arg @ref LL_PWR_SRAM6_STOP_PAGE1_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE2_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE3_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE4_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE5_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE6_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE7_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE8_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM6StopRetention(uint32_t SRAM6PageRetention) +{ + MODIFY_REG(PWR->CR5, LL_PWR_SRAM6_STOP_FULL_RETENTION, ((~SRAM6PageRetention) & LL_PWR_SRAM6_STOP_FULL_RETENTION)); +} + +/** + * @brief Get the SRAM6 page(s) retention in Stop mode. + * @rmtoll CR5 SRAM6PDS1 LL_PWR_GetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS2 LL_PWR_GetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS3 LL_PWR_GetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS4 LL_PWR_GetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS5 LL_PWR_GetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS6 LL_PWR_GetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS7 LL_PWR_GetSRAM6StopRetention\n + * @rmtoll CR5 SRAM6PDS8 LL_PWR_GetSRAM6StopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM6_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_FULL_RETENTION + * Or can be a combination of the following values: + * @arg @ref LL_PWR_SRAM6_STOP_PAGE1_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE2_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE3_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE4_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE5_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE6_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE7_RETENTION + * @arg @ref LL_PWR_SRAM6_STOP_PAGE8_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM6StopRetention(void) +{ + return ((~(READ_BIT(PWR->CR5, LL_PWR_SRAM6_STOP_FULL_RETENTION))) & LL_PWR_SRAM6_STOP_FULL_RETENTION); +} +#endif /* defined (PWR_CR5_SRAM6PDS1) */ + /** * @brief Set the ICACHE SRAM page retention in Stop mode. * @rmtoll CR2 ICRAMPDS LL_PWR_SetICacheRAMStopRetention\n @@ -849,6 +1352,35 @@ __STATIC_INLINE uint32_t LL_PWR_GetDCache1RAMStopRetention(void) return ((~(READ_BIT(PWR->CR2, LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION))) & LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION); } +#if defined (PWR_CR2_DC2RAMPDS) +/** + * @brief Set the DCACHE2 SRAM page retention in Stop mode. + * @rmtoll CR2 DC2RAMPDS LL_PWR_SetDCache2RAMStopRetention\n + * @param DCache2PageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_DCACHE2RAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetDCache2RAMStopRetention(uint32_t DCache2PageRetention) +{ + MODIFY_REG(PWR->CR2, LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION, + ((~DCache2PageRetention) & LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION)); +} + +/** + * @brief Get the DCACHE2 SRAM page retention in Stop mode. + * @rmtoll CR2 DC2RAMPDS LL_PWR_GetDCache2RAMStopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_DCACHE2RAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetDCache2RAMStopRetention(void) +{ + return ((~(READ_BIT(PWR->CR2, LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION))) & LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION); +} +#endif /* defined (PWR_CR2_DC2RAMPDS) */ + +#if defined (PWR_CR2_DMA2DRAMPDS) /** * @brief Set the DMA2D SRAM page retention in Stop mode. * @rmtoll CR2 DMA2DRAMPDS LL_PWR_SetDMA2DRAMStopRetention\n @@ -874,6 +1406,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetDMA2DRAMStopRetention(void) { return ((~(READ_BIT(PWR->CR2, LL_PWR_DMA2DRAM_STOP_FULL_RETENTION))) & LL_PWR_DMA2DRAM_STOP_FULL_RETENTION); } +#endif /* PWR_CR2_DMA2DRAMPDS */ /** * @brief Set the FMAC, FDCAN and USB SRAMs pages retention in Stop mode. @@ -926,6 +1459,90 @@ __STATIC_INLINE uint32_t LL_PWR_GetPKARAMStopRetention(void) return ((~(READ_BIT(PWR->CR2, LL_PWR_PKARAM_STOP_FULL_RETENTION))) & LL_PWR_PKARAM_STOP_FULL_RETENTION); } +#if defined (PWR_CR2_GPRAMPDS) +/** + * @brief Set the Graphic peripherals (LTDC, GFXMMU) SRAM page retention in Stop mode. + * @rmtoll CR2 GPRAMPDS LL_PWR_SetGraphicPeriphRAMStopRetention + * @param GraphicPeriphRAMPageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_GRAPHICPERIPHRAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetGraphicPeriphRAMStopRetention(uint32_t GraphicPeriphRAMPageRetention) +{ + MODIFY_REG(PWR->CR2, LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION, + ((~GraphicPeriphRAMPageRetention) & LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION)); +} + +/** + * @brief Get the Graphic peripherals (LTDC, GFXMMU) SRAM page retention in Stop mode. + * @rmtoll CR2 GPRAMPDS LL_PWR_GetGraphicPeriphRAMStopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_GRAPHICPERIPHRAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetGraphicPeriphRAMStopRetention(void) +{ + return ((~(READ_BIT(PWR->CR2, LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION))) & + LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION); +} +#endif /* defined (PWR_CR2_GPRAMPDS) */ + +#if defined (PWR_CR2_DSIRAMPDS) +/** + * @brief Set the DSI SRAM page retention in Stop mode. + * @rmtoll CR2 DSIRAMPDS LL_PWR_SetDSIRAMStopRetention + * @param DSIRAMPageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_DSIRAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_DSIRAM_STOP_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetDSIRAMStopRetention(uint32_t DSIRAMPageRetention) +{ + MODIFY_REG(PWR->CR2, LL_PWR_DSIRAM_STOP_FULL_RETENTION, ((~DSIRAMPageRetention) & LL_PWR_DSIRAM_STOP_FULL_RETENTION)); +} + +/** + * @brief Get the DSI SRAM page retention in Stop mode. + * @rmtoll CR2 DSIRAMPDS LL_PWR_GetDSIRAMStopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_DSIRAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_DSIRAM_STOP_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetDSIRAMStopRetention(void) +{ + return ((~(READ_BIT(PWR->CR2, LL_PWR_DSIRAM_STOP_FULL_RETENTION))) & LL_PWR_DSIRAM_STOP_FULL_RETENTION); +} +#endif /* defined (PWR_CR2_DSIRAMPDS) */ + +#if defined (PWR_CR2_JPEGRAMPDS) +/** + * @brief Set the JPEG SRAM page retention in Stop mode. + * @rmtoll CR2 JPEGRAMPDS LL_PWR_SetJPEGRAMStopRetention + * @param DSIRAMPageRetention : This parameter can be one of the following values: + * @arg @ref LL_PWR_JPEGRAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_JPEGRAM_STOP_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetJPEGRAMStopRetention(uint32_t JPEGRAMPageRetention) +{ + MODIFY_REG(PWR->CR2, LL_PWR_JPEGRAM_STOP_FULL_RETENTION, + ((~JPEGRAMPageRetention) & LL_PWR_JPEGRAM_STOP_FULL_RETENTION)); +} + +/** + * @brief Get the JPEG SRAM page retention in Stop mode. + * @rmtoll CR2 JPEGRAMPDS LL_PWR_GetJPEGRAMStopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_JPEGRAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_JPEGRAM_STOP_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetJPEGRAMStopRetention(void) +{ + return ((~(READ_BIT(PWR->CR2, LL_PWR_JPEGRAM_STOP_FULL_RETENTION))) & LL_PWR_JPEGRAM_STOP_FULL_RETENTION); +} +#endif /* defined (PWR_CR2_JPEGRAMPDS) */ + /** * @brief Enable the flash memory fast wakeup from Stop mode (Stop 0, 1). * @rmtoll CR2 FLASHFWU LL_PWR_EnableFlashFastWakeUp @@ -949,7 +1566,7 @@ __STATIC_INLINE void LL_PWR_DisableFlashFastWakeUp(void) /** * @brief Check if the flash memory fast wakeup from Stop mode (Stop 0, 1) * is enabled. - * @rmtoll CR2 FLASHFWU LL_PWR_IsEnabledFlashSRAM_StopModes + * @rmtoll CR2 FLASHFWU LL_PWR_IsEnabledFlashFastWakeUp * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashFastWakeUp(void) @@ -1127,6 +1744,102 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledEPODBooster(void) return ((READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) == (PWR_VOSR_BOOSTEN)) ? 1UL : 0UL); } +#if defined (PWR_VOSR_USBPWREN) +/** + * @brief Enable the USB power supply. + * @rmtoll VOSR USBPWREN LL_PWR_EnableUSBPowerSupply + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUSBPowerSupply(void) +{ + SET_BIT(PWR->VOSR, PWR_VOSR_USBPWREN); +} + +/** + * @brief Disable the USB power supply. + * @rmtoll VOSR USBPWREN LL_PWR_DisableUSBPowerSupply + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUSBPowerSupply(void) +{ + CLEAR_BIT(PWR->VOSR, PWR_VOSR_USBPWREN); +} + +/** + * @brief Check if the USB power supply is enabled. + * @rmtoll VOSR USBPWREN LL_PWR_IsEnabledUSBPowerSupply + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBPowerSupply(void) +{ + return ((READ_BIT(PWR->VOSR, PWR_VOSR_USBPWREN) == (PWR_VOSR_USBPWREN)) ? 1UL : 0UL); +} +#endif /* defined (PWR_VOSR_USBPWREN) */ + +#if defined (PWR_VOSR_USBBOOSTEN) +/** + * @brief Enable the USB EPOD (Embedded Power Distribution) booster. + * @rmtoll VOSR USBBOOSTEN LL_PWR_EnableUSBEPODBooster + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUSBEPODBooster(void) +{ + SET_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTEN); +} + +/** + * @brief Disable the USB EPOD (Embedded Power Distribution) booster. + * @rmtoll VOSR USBBOOSTEN LL_PWR_DisableUSBEPODBooster + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUSBEPODBooster(void) +{ + CLEAR_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTEN); +} + +/** + * @brief Check if the USB EPOD (Embedded Power Distribution) booster is enabled. + * @rmtoll VOSR USBBOOSTEN LL_PWR_IsEnabledUSBEPODBooster + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBEPODBooster(void) +{ + return ((READ_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTEN) == (PWR_VOSR_USBBOOSTEN)) ? 1UL : 0UL); +} +#endif /* defined (PWR_VOSR_USBBOOSTEN) */ + +#if defined (PWR_VOSR_VDD11USBDIS) +/** + * @brief Enable the VDD11USB. + * @rmtoll VOSR VDD11USBDIS LL_PWR_EnableVDD11USB + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableVDD11USB(void) +{ + CLEAR_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS); +} + +/** + * @brief Disable the VDD11USB. + * @rmtoll VOSR VDD11USBDIS LL_PWR_DisableVDD11USB + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableVDD11USB(void) +{ + SET_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS); +} + +/** + * @brief Check if the VDD11USB is enabled. + * @rmtoll VOSR VDD11USBDIS LL_PWR_IsEnabledVDD11USB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledVDD11USB(void) +{ + return ((READ_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS) == (0U)) ? 1UL : 0UL); +} +#endif /* defined (PWR_VOSR_VDD11USBDIS) */ + /** * @brief Set the Power voltage detector level. * @rmtoll SVMCR PVDLS LL_PWR_SetPVDLevel @@ -1444,7 +2157,7 @@ __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) /** * @brief Check if the wake up pin_x is enabled. - * @rmtoll WUCR1 WUPENx LL_PWR_IsEnableWakeUpPin + * @rmtoll WUCR1 WUPENx LL_PWR_IsEnabledWakeUpPin * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 @@ -1767,6 +2480,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) return ((READ_BIT(PWR->DBPR, PWR_DBPR_DBP) == (PWR_DBPR_DBP)) ? 1UL : 0UL); } +#ifdef UCPD1 /** * @brief Enable the USB Type-C and Power Delivery memorization in Standby mode. * @note This function must be called just before entering Standby mode. @@ -1844,6 +2558,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void) { return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS) == (PWR_UCPDR_UCPD_DBDIS)) ? 0UL : 1UL); } +#endif /* UCPD1 */ /** * @brief Enable the pull-up and pull-down configuration. @@ -1888,6 +2603,8 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDConfig(void) * @arg @ref LL_PWR_GPIO_PORTG * @arg @ref LL_PWR_GPIO_PORTH * @arg @ref LL_PWR_GPIO_PORTI + * @arg @ref LL_PWR_GPIO_PORTJ (*) + * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices. * @param GPIOPin This parameter can be a combination of the following values: * @arg @ref LL_PWR_GPIO_PIN_0 * @arg @ref LL_PWR_GPIO_PIN_1 @@ -1925,6 +2642,8 @@ __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIOPort, uint32_t GPIOPin * @arg @ref LL_PWR_GPIO_PORTG * @arg @ref LL_PWR_GPIO_PORTH * @arg @ref LL_PWR_GPIO_PORTI + * @arg @ref LL_PWR_GPIO_PORTJ (*) + * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices. * @param GPIOPin This parameter can be a combination of the following values: * @arg @ref LL_PWR_GPIO_PIN_0 * @arg @ref LL_PWR_GPIO_PIN_1 @@ -1962,6 +2681,8 @@ __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIOPort, uint32_t GPIOPi * @arg @ref LL_PWR_GPIO_PORTG * @arg @ref LL_PWR_GPIO_PORTH * @arg @ref LL_PWR_GPIO_PORTI + * @arg @ref LL_PWR_GPIO_PORTJ (*) + * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices. * @param GPIOPin This parameter can be one of the following values: * @arg @ref LL_PWR_GPIO_PIN_0 * @arg @ref LL_PWR_GPIO_PIN_1 @@ -1999,6 +2720,8 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIOPort, uint32_t * @arg @ref LL_PWR_GPIO_PORTG * @arg @ref LL_PWR_GPIO_PORTH * @arg @ref LL_PWR_GPIO_PORTI + * @arg @ref LL_PWR_GPIO_PORTJ (*) + * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices. * @param GPIOPin This parameter can be a combination of the following values: * @arg @ref LL_PWR_GPIO_PIN_0 * @arg @ref LL_PWR_GPIO_PIN_1 @@ -2036,6 +2759,8 @@ __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIOPort, uint32_t GPIOP * @arg @ref LL_PWR_GPIO_PORTG * @arg @ref LL_PWR_GPIO_PORTH * @arg @ref LL_PWR_GPIO_PORTI + * @arg @ref LL_PWR_GPIO_PORTJ (*) + * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices. * @param GPIOPin This parameter can be a combination of the following values: * @arg @ref LL_PWR_GPIO_PIN_0 * @arg @ref LL_PWR_GPIO_PIN_1 @@ -2073,6 +2798,8 @@ __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIOPort, uint32_t GPIO * @arg @ref LL_PWR_GPIO_PORTG * @arg @ref LL_PWR_GPIO_PORTH * @arg @ref LL_PWR_GPIO_PORTI + * @arg @ref LL_PWR_GPIO_PORTJ (*) + * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices. * @param GPIOPin This parameter can be one of the following values: * @arg @ref LL_PWR_GPIO_PIN_0 * @arg @ref LL_PWR_GPIO_PIN_1 @@ -2129,6 +2856,19 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BOOST(void) return ((READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == (PWR_VOSR_BOOSTRDY)) ? 1UL : 0UL); } +#if defined (PWR_VOSR_USBBOOSTRDY) +/** + * @brief Indicate whether the USB EPOD (Embedded Power Distribution) booster is + * ready OR not. + * @rmtoll VOSR USBBOOSTRDY LL_PWR_IsActiveFlag_USBBOOST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USBBOOST(void) +{ + return ((READ_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTRDY) == (PWR_VOSR_USBBOOSTRDY)) ? 1UL : 0UL); +} +#endif /* defined (PWR_VOSR_USBBOOSTRDY) */ + /** * @brief Indicate whether the regulator voltage output is above voltage * scaling range or not. diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rcc.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rcc.c index 6089e8e7242..be36f317b32 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rcc.c @@ -41,19 +41,38 @@ /** @addtogroup RCC_LL_Private_Macros * @{ */ +#if defined(USART6) #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)\ + || ((__VALUE__) == LL_RCC_USART6_CLKSOURCE)) +#elif defined(USART2) +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) +#else +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) +#endif /* defined(USART6) */ #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE)) #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE)) +#if defined(I2C5) & defined(I2C6) +#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE)\ + || ((__VALUE__) == LL_RCC_I2C5_CLKSOURCE)\ + || ((__VALUE__) == LL_RCC_I2C6_CLKSOURCE)) +#else #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE)) +#endif /* defined(I2C5) & defined(I2C6) */ #define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_SPI2_CLKSOURCE) \ @@ -62,9 +81,12 @@ #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_LPTIM34_CLKSOURCE)) - +#if defined(SAI2) #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE)) +#else +#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE)) +#endif /* SAI2 */ #define IS_LL_RCC_SDMMC_KERNELCLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC_KERNELCLKSOURCE)) @@ -84,10 +106,22 @@ #define IS_LL_RCC_OCTOSPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_OCTOSPI_CLKSOURCE)) +#if defined(HSPI1) +#define IS_LL_RCC_HSPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_HSPI_CLKSOURCE)) +#endif /* defined(HSPI1) */ + #define IS_LL_RCC_SAES_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAES_CLKSOURCE)) #define IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE)) +#if defined(DSI) +#define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE)) +#endif /* defined(DSI) */ + +#if defined(LTDC) +#define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE)) +#endif /* defined(LTDC) */ + /** * @} */ @@ -109,6 +143,9 @@ static uint32_t RCC_PLL2_GetFreqDomain_48M(void); static uint32_t RCC_PLL2_GetFreqDomain_ADC(void); static uint32_t RCC_PLL3_GetFreqDomain_SAI(void); static uint32_t RCC_PLL3_GetFreqDomain_48M(void); +#if defined(HSPI1) || defined(LTDC) +static uint32_t RCC_PLL3_GetFreqDomain_HSPI_LTDC(void); +#endif /* HSPI1 || LTDC */ /** * @} */ @@ -270,8 +307,11 @@ void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) * @arg @ref LL_RCC_USART1_CLKSOURCE * @arg @ref LL_RCC_USART2_CLKSOURCE * @arg @ref LL_RCC_USART3_CLKSOURCE + * @arg @ref LL_RCC_USART6_CLKSOURCE (*) * @retval USART clock frequency (in Hz) * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready + * + * (*) : USART6 is available only for STM32U59xxx and STM32U5Axxx devices. */ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) { @@ -312,6 +352,7 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) break; } } +#if defined (USART2) else if (USARTxSource == LL_RCC_USART2_CLKSOURCE) { /* USART2CLK clock frequency */ @@ -344,6 +385,7 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) break; } } +#endif /* USART2 */ else if (USARTxSource == LL_RCC_USART3_CLKSOURCE) { /* USART3CLK clock frequency */ @@ -376,6 +418,40 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) break; } } +#if defined (USART6) + else if (USARTxSource == LL_RCC_USART6_CLKSOURCE) + { + /* USART6CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART6_CLKSOURCE_SYSCLK: /* USART6 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART6_CLKSOURCE_HSI: /* USART6 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + usart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART6_CLKSOURCE_LSE: /* USART6 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART6_CLKSOURCE_PCLK1: /* USART6 Clock is PCLK1 */ + usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + + default: + /* unreachable code */ + break; + } + } +#endif /* USART6 */ else { /* nothing to do */ @@ -734,6 +810,72 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) break; } } +#if defined(I2C5) + else if (I2CxSource == LL_RCC_I2C5_CLKSOURCE) + { + /* I2C5 CLK clock frequency */ + switch (LL_RCC_GetI2CClockSource(I2CxSource)) + { + case LL_RCC_I2C5_CLKSOURCE_SYSCLK: /* I2C5 Clock is System Clock */ + i2c_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_I2C5_CLKSOURCE_HSI: /* I2C5 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + i2c_frequency = HSI_VALUE; + } + break; + + case LL_RCC_I2C5_CLKSOURCE_MSIK: /* I2C5 Clock is MSIK Osc.*/ + i2c_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ? + LL_RCC_MSIK_GetRange() : + LL_RCC_MSIK_GetRangeAfterStandby())); + break; + case LL_RCC_I2C5_CLKSOURCE_PCLK1: /* I2C5 Clock is PCLK1 */ + i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + + default: + /* unreachable code */ + break; + } + } +#endif /* I2C5 */ +#if defined(I2C6) + else if (I2CxSource == LL_RCC_I2C6_CLKSOURCE) + { + /* I2C6 CLK clock frequency */ + switch (LL_RCC_GetI2CClockSource(I2CxSource)) + { + case LL_RCC_I2C6_CLKSOURCE_SYSCLK: /* I2C6 Clock is System Clock */ + i2c_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_I2C6_CLKSOURCE_HSI: /* I2C6 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + i2c_frequency = HSI_VALUE; + } + break; + + case LL_RCC_I2C6_CLKSOURCE_MSIK: /* I2C6 Clock is MSIK Osc.*/ + i2c_frequency = __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ? + LL_RCC_MSIK_GetRange() : + LL_RCC_MSIK_GetRangeAfterStandby())); + break; + case LL_RCC_I2C6_CLKSOURCE_PCLK1: /* I2C6 Clock is PCLK1 */ + i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + + default: + /* unreachable code */ + break; + } + } +#endif /* I2C6 */ else { /* nothing to do */ @@ -778,7 +920,7 @@ uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource) break; case LL_RCC_LPUART1_CLKSOURCE_PCLK3: /* LPUART1 Clock is PCLK3 */ - lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + lpuart_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; default: @@ -813,7 +955,14 @@ uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */ if (LL_RCC_LSI_IsReady() == 1U) { - lptim_frequency = LSI_VALUE; + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV) == RCC_BDCR_LSIPREDIV) + { + lptim_frequency = LSI_VALUE / 128U; + } + else + { + lptim_frequency = LSI_VALUE; + } } break; @@ -851,7 +1000,14 @@ uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) case LL_RCC_LPTIM2_CLKSOURCE_LSI: /* LPTIM2 Clock is LSI Osc. */ if (LL_RCC_LSI_IsReady() == 1U) { - lptim_frequency = LSI_VALUE; + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV) == RCC_BDCR_LSIPREDIV) + { + lptim_frequency = LSI_VALUE / 128U; + } + else + { + lptim_frequency = LSI_VALUE; + } } break; @@ -886,7 +1042,14 @@ uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) case LL_RCC_LPTIM34_CLKSOURCE_LSI: /* LPTIM34 Clock is LSI Osc. */ if (LL_RCC_LSI_IsReady() == 1U) { - lptim_frequency = LSI_VALUE; + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV) == RCC_BDCR_LSIPREDIV) + { + lptim_frequency = LSI_VALUE / 128U; + } + else + { + lptim_frequency = LSI_VALUE; + } } break; @@ -947,21 +1110,30 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) case LL_RCC_SAI1_CLKSOURCE_PLL2: /* PLL2 clock used as SAI1 clock source */ if (LL_RCC_PLL2_IsReady() == 1U) { - sai_frequency = RCC_PLL2_GetFreqDomain_SAI(); + if (LL_RCC_PLL2_IsEnabledDomain_SAI() != 0U) + { + sai_frequency = RCC_PLL2_GetFreqDomain_SAI(); + } } break; case LL_RCC_SAI1_CLKSOURCE_PLL3: /* PLL3 clock used as SAI1 clock source */ if (LL_RCC_PLL3_IsReady() == 1U) { - sai_frequency = RCC_PLL3_GetFreqDomain_SAI(); + if (LL_RCC_PLL3_IsEnabledDomain_SAI() != 0U) + { + sai_frequency = RCC_PLL3_GetFreqDomain_SAI(); + } } break; case LL_RCC_SAI1_CLKSOURCE_PLL1: /* PLL1 clock used as SAI1 clock source */ if (LL_RCC_PLL1_IsReady() == 1U) { - sai_frequency = RCC_PLL1_GetFreqDomain_SAI(); + if (LL_RCC_PLL1_IsEnabledDomain_SAI() != 0U) + { + sai_frequency = RCC_PLL1_GetFreqDomain_SAI(); + } } break; @@ -974,6 +1146,7 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) break; } } +#if defined(SAI2) else if (SAIxSource == LL_RCC_SAI2_CLKSOURCE) { /* SAI2CLK clock frequency */ @@ -982,21 +1155,30 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) case LL_RCC_SAI2_CLKSOURCE_PLL2: /* PLL2 clock used as SAI2 clock source */ if (LL_RCC_PLL2_IsReady() == 1U) { - sai_frequency = RCC_PLL2_GetFreqDomain_SAI(); + if (LL_RCC_PLL2_IsEnabledDomain_SAI() != 0U) + { + sai_frequency = RCC_PLL2_GetFreqDomain_SAI(); + } } break; case LL_RCC_SAI2_CLKSOURCE_PLL3: /* PLL3 clock used as SAI2 clock source */ if (LL_RCC_PLL3_IsReady() == 1U) { - sai_frequency = RCC_PLL3_GetFreqDomain_SAI(); + if (LL_RCC_PLL3_IsEnabledDomain_SAI() != 0U) + { + sai_frequency = RCC_PLL3_GetFreqDomain_SAI(); + } } break; case LL_RCC_SAI2_CLKSOURCE_PLL1: /* PLL1 clock used as SAI2 clock source */ if (LL_RCC_PLL1_IsReady() == 1U) { - sai_frequency = RCC_PLL1_GetFreqDomain_SAI(); + if (LL_RCC_PLL1_IsEnabledDomain_SAI() != 0U) + { + sai_frequency = RCC_PLL1_GetFreqDomain_SAI(); + } } break; @@ -1009,6 +1191,7 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) break; } } +#endif /* SAI2 */ else { /* nothing to do */ @@ -1041,7 +1224,10 @@ uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource) case LL_RCC_SDMMC12_KERNELCLKSOURCE_PLL1: /* PLL1 "P" output (PLL1CLK) clock used as SDMMC1/2 clock source */ if (LL_RCC_PLL1_IsReady() == 1U) { - sdmmc_frequency = RCC_PLL1_GetFreqDomain_SAI(); + if (LL_RCC_PLL1_IsEnabledDomain_SAI() != 0U) + { + sdmmc_frequency = RCC_PLL1_GetFreqDomain_SAI(); + } } break; @@ -1073,14 +1259,20 @@ uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource) case LL_RCC_SDMMC12_CLKSOURCE_PLL2: /* PLL2 clock used as SDMMC12 clock source */ if (LL_RCC_PLL2_IsReady() == 1U) { - sdmmc_frequency = RCC_PLL2_GetFreqDomain_48M(); + if (LL_RCC_PLL2_IsEnabledDomain_48M() != 0U) + { + sdmmc_frequency = RCC_PLL2_GetFreqDomain_48M(); + } } break; case LL_RCC_SDMMC12_CLKSOURCE_PLL1: /* PLL1 clock used as SDMMC12 clock source */ if (LL_RCC_PLL1_IsReady() == 1U) { - sdmmc_frequency = RCC_PLL1_GetFreqDomain_48M(); + if (LL_RCC_PLL1_IsEnabledDomain_48M() != 0U) + { + sdmmc_frequency = RCC_PLL1_GetFreqDomain_48M(); + } } break; @@ -1176,14 +1368,20 @@ uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) case LL_RCC_USB_CLKSOURCE_PLL2: /* PLL2 clock used as USB clock source */ if (LL_RCC_PLL2_IsReady() == 1U) { - usb_frequency = RCC_PLL2_GetFreqDomain_48M(); + if (LL_RCC_PLL2_IsEnabledDomain_48M() != 0U) + { + usb_frequency = RCC_PLL2_GetFreqDomain_48M(); + } } break; case LL_RCC_USB_CLKSOURCE_PLL1: /* PLL1 clock used as USB clock source */ if (LL_RCC_PLL1_IsReady() == 1U) { - usb_frequency = RCC_PLL1_GetFreqDomain_48M(); + if (LL_RCC_PLL1_IsEnabledDomain_48M() != 0U) + { + usb_frequency = RCC_PLL1_GetFreqDomain_48M(); + } } break; @@ -1240,7 +1438,10 @@ uint32_t LL_RCC_GetADCDACClockFreq(uint32_t ADCxSource) case LL_RCC_ADCDAC_CLKSOURCE_PLL2: /* PLL2 clock used as ADCDAC clock source */ if (LL_RCC_PLL2_IsReady() == 1U) { - adcdac_frequency = RCC_PLL2_GetFreqDomain_ADC(); + if (LL_RCC_PLL2_IsEnabledDomain_ADC() != 0U) + { + adcdac_frequency = RCC_PLL2_GetFreqDomain_ADC(); + } } break; @@ -1298,11 +1499,23 @@ uint32_t LL_RCC_GetADF1ClockFreq(uint32_t ADF1Source) break; case LL_RCC_ADF1_CLKSOURCE_PLL1: /* ADF1 Clock is PLL1 */ - ADF1_frequency = RCC_PLL1_GetFreqDomain_SAI(); + if (LL_RCC_PLL1_IsReady() != 0U) + { + if (LL_RCC_PLL1_IsEnabledDomain_SAI() != 0U) + { + ADF1_frequency = RCC_PLL1_GetFreqDomain_SAI(); + } + } break; case LL_RCC_ADF1_CLKSOURCE_PLL3: /* ADF1 Clock is PLL3 */ - ADF1_frequency = RCC_PLL3_GetFreqDomain_48M(); + if (LL_RCC_PLL3_IsReady() != 0U) + { + if (LL_RCC_PLL3_IsEnabledDomain_48M() != 0U) + { + ADF1_frequency = RCC_PLL3_GetFreqDomain_48M(); + } + } break; case LL_RCC_ADF1_CLKSOURCE_PIN: /* External input clock used as ADF1 clock source */ @@ -1346,11 +1559,23 @@ uint32_t LL_RCC_GetMDF1ClockFreq(uint32_t MDF1Source) break; case LL_RCC_MDF1_CLKSOURCE_PLL1: /* MDF1 Clock is PLL1 */ - MDF1_frequency = RCC_PLL1_GetFreqDomain_SAI(); + if (LL_RCC_PLL1_IsReady() != 0U) + { + if (LL_RCC_PLL1_IsEnabledDomain_SAI() != 0U) + { + MDF1_frequency = RCC_PLL1_GetFreqDomain_SAI(); + } + } break; case LL_RCC_MDF1_CLKSOURCE_PLL3: /* MDF1 Clock is PLL3 */ - MDF1_frequency = RCC_PLL3_GetFreqDomain_48M(); + if (LL_RCC_PLL3_IsReady() != 0U) + { + if (LL_RCC_PLL3_IsEnabledDomain_48M() != 0U) + { + MDF1_frequency = RCC_PLL3_GetFreqDomain_48M(); + } + } break; case LL_RCC_MDF1_CLKSOURCE_PIN: /* External input clock used as MDF1 clock source */ @@ -1439,13 +1664,19 @@ uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource) case LL_RCC_OCTOSPI_CLKSOURCE_PLL1: /* PLL1 clock used as OCTOSPI source */ if (LL_RCC_PLL1_IsReady() == 1U) { - octospi_frequency = RCC_PLL1_GetFreqDomain_48M(); + if (LL_RCC_PLL1_IsEnabledDomain_48M() != 0U) + { + octospi_frequency = RCC_PLL1_GetFreqDomain_48M(); + } } break; case LL_RCC_OCTOSPI_CLKSOURCE_PLL2: /* PLL2 clock used as OCTOSPI source */ if (LL_RCC_PLL2_IsReady() == 1U) { - octospi_frequency = RCC_PLL2_GetFreqDomain_48M(); + if (LL_RCC_PLL2_IsEnabledDomain_48M() != 0U) + { + octospi_frequency = RCC_PLL2_GetFreqDomain_48M(); + } } break; @@ -1524,14 +1755,20 @@ uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource) case LL_RCC_FDCAN_CLKSOURCE_PLL1: /* PLL2 clock used as FDCAN kernel clock */ if (LL_RCC_PLL1_IsReady() == 1U) { - fdcan_frequency = RCC_PLL1_GetFreqDomain_48M(); + if (LL_RCC_PLL1_IsEnabledDomain_48M() != 0U) + { + fdcan_frequency = RCC_PLL1_GetFreqDomain_48M(); + } } break; case LL_RCC_FDCAN_CLKSOURCE_PLL2: /* PLL2 clock used as FDCAN kernel clock */ if (LL_RCC_PLL2_IsReady() == 1U) { - fdcan_frequency = RCC_PLL2_GetFreqDomain_SAI(); + if (LL_RCC_PLL2_IsEnabledDomain_SAI() != 0U) + { + fdcan_frequency = RCC_PLL2_GetFreqDomain_SAI(); + } } break; @@ -1542,7 +1779,145 @@ uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource) return fdcan_frequency; } +#if defined(DSI) +/** + * @brief Return DSI clock frequency + * @param DSIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE + * @retval DSI clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used + */ +uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource) +{ + uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + switch (LL_RCC_GetDSIClockSource(DSIxSource)) + { + case LL_RCC_LTDC_CLKSOURCE_PLL3: + if (LL_RCC_PLL3_IsReady() != 0U) + { + if (LL_RCC_PLL3_IsEnabledDomain_SAI() != 0U) + { + dsi_frequency = RCC_PLL3_GetFreqDomain_SAI(); + } + } + break; + + case LL_RCC_DSI_CLKSOURCE_PHY: + dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + break; + + default: + /* Nothing to do */ + break; + } + + return dsi_frequency; +} +#endif /* defined(DSI) */ + +#if defined(HSPI1) +/** + * @brief Return HSPI clock frequency + * @param HSPIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_HSPI_CLKSOURCE + * @retval HSPI clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ + +uint32_t LL_RCC_GetHSPIClockFreq(uint32_t HSPIxSource) +{ + uint32_t hspi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + switch (LL_RCC_GetHSPIClockSource(HSPIxSource)) + { + case LL_RCC_HSPI_CLKSOURCE_SYSCLK: + hspi_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_HSPI_CLKSOURCE_PLL1: + if (LL_RCC_PLL1_IsReady() != 0U) + { + if (LL_RCC_PLL1_IsEnabledDomain_48M() != 0U) + { + hspi_frequency = RCC_PLL1_GetFreqDomain_48M(); + } + } + break; + + case LL_RCC_HSPI_CLKSOURCE_PLL2: + if (LL_RCC_PLL2_IsReady() != 0U) + { + if (LL_RCC_PLL2_IsEnabledDomain_48M() != 0U) + { + hspi_frequency = RCC_PLL2_GetFreqDomain_48M(); + } + } + break; + + case LL_RCC_HSPI_CLKSOURCE_PLL3: + if (LL_RCC_PLL3_IsReady() != 0U) + { + if (LL_RCC_PLL3_IsEnabledDomain_HSPI_LTDC() != 0U) + { + hspi_frequency = RCC_PLL3_GetFreqDomain_HSPI_LTDC(); + } + } + break; + + default: + /* Nothing to do */ + break; + } + + return hspi_frequency; +} +#endif /* defined(HSPI1) */ +#if defined(LTDC) +/** + * @brief Return LTDC clock frequency + * @param LTDCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE + * @retval HSPI clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ + +uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource) +{ + uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + switch (LL_RCC_GetHSPIClockSource(LTDCxSource)) + { + case LL_RCC_LTDC_CLKSOURCE_PLL2: + if (LL_RCC_PLL2_IsReady() != 0U) + { + if (LL_RCC_PLL2_IsEnabledDomain_ADC() != 0U) + { + ltdc_frequency = RCC_PLL2_GetFreqDomain_ADC(); + } + } + break; + + case LL_RCC_LTDC_CLKSOURCE_PLL3: + if (LL_RCC_PLL3_IsReady() != 0U) + { + if (LL_RCC_PLL3_IsEnabledDomain_HSPI_LTDC() != 0U) + { + ltdc_frequency = RCC_PLL3_GetFreqDomain_HSPI_LTDC(); + } + } + break; + + default: + /* Nothing to do */ + break; + } + + return ltdc_frequency; +} +#endif /* defined(LTDC) */ /** * @} */ @@ -2016,7 +2391,49 @@ static uint32_t RCC_PLL3_GetFreqDomain_48M(void) return __LL_RCC_CALC_PLL3CLK_48M_FREQ(PLL3inputfreq, LL_RCC_PLL3_GetDivider(), LL_RCC_PLL3_GetN(), LL_RCC_PLL3_GetQ()); } +#if defined(HSPI1) || defined(LTDC) +/** + * @brief Return PLL3 clock frequency used for HSPI_LTDC domain + * @retval PLL3 clock frequency (in Hz) + */ +static uint32_t RCC_PLL3_GetFreqDomain_HSPI_LTDC(void) +{ + uint32_t pll3inputfreq; + uint32_t pll3source; + + /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLL2M) * PLL3N */ + + pll3source = LL_RCC_PLL3_GetSource(); + + switch (pll3source) + { + case LL_RCC_PLL3SOURCE_MSIS: /* MSI used as PLL2 clock source */ + pll3inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ? + LL_RCC_MSIS_GetRange() : + LL_RCC_MSIS_GetRangeAfterStandby())); + break; + + case LL_RCC_PLL3SOURCE_HSI: /* HSI used as PLL2 clock source */ + pll3inputfreq = HSI_VALUE; + break; + + case LL_RCC_PLL3SOURCE_HSE: /* HSE used as PLL2 clock source */ + pll3inputfreq = HSE_VALUE; + break; + + default: + pll3inputfreq = __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ? + LL_RCC_MSIS_GetRange() : + LL_RCC_MSIS_GetRangeAfterStandby())); + break; + } + return __LL_RCC_CALC_PLL3CLK_HSPI_LTDC_FREQ(pll3inputfreq, LL_RCC_PLL3_GetDivider(), + LL_RCC_PLL3_GetN(), LL_RCC_PLL3_GetR()); +} +#endif /* HSPI1 || LTDC */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rcc.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rcc.h index 40b6e23ad72..ed5334c8635 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rcc.h @@ -46,6 +46,7 @@ extern "C" { /* Defines used to perform offsets*/ /* Offset used to access to RCC_CCIPR1 and RCC_CCIPR2 registers */ #define RCC_OFFSET_CCIPR1 0U +#define RCC_OFFSET_CCIPR2 0x04U #define RCC_OFFSET_CCIPR3 0x08U /* Defines used for security configuration extension */ @@ -223,7 +224,7 @@ typedef struct /** @defgroup RCC_LL_EC_MSIKSRANGE MSIK range after Standby mode * @{ */ -#define LL_RCC_MSIKSRANGE_4 RCC_CSR_MSISSRANGE_2 /*!< MSIK = 4 MHz */ +#define LL_RCC_MSIKSRANGE_4 RCC_CSR_MSIKSRANGE_2 /*!< MSIK = 4 MHz */ #define LL_RCC_MSIKSRANGE_5 (RCC_CSR_MSIKSRANGE_2 | RCC_CSR_MSIKSRANGE_0) /*!< MSIK = 2 MHz */ #define LL_RCC_MSIKSRANGE_6 (RCC_CSR_MSIKSRANGE_2 | RCC_CSR_MSIKSRANGE_1) /*!< MSIK = 1.5 MHz */ #define LL_RCC_MSIKSRANGE_7 (RCC_CSR_MSIKSRANGE_2 | RCC_CSR_MSIKSRANGE_1 | RCC_CSR_MSIKSRANGE_0) /*!< MSIK = 1 MHz */ @@ -297,7 +298,6 @@ typedef struct * @} */ - /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status * @{ */ @@ -309,7 +309,6 @@ typedef struct * @} */ - /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler * @{ */ @@ -327,7 +326,6 @@ typedef struct * @} */ - /** @defgroup RCC_LL_EC_SYSTICK_CLKSOURCE SYSTICK clock source selection * @{ */ @@ -350,7 +348,6 @@ typedef struct * @} */ - /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) * @{ */ @@ -376,6 +373,19 @@ typedef struct * @} */ +#if defined(RCC_CFGR2_PPRE_DPHY) +/** @defgroup RCC_LL_EC_DPHY_DIV DSI PHY clock prescaler (DCLK) + * @{ + */ +#define LL_RCC_DPHY_DIV_1 0x00000000U /*!< DCLK not divided */ +#define LL_RCC_DPHY_DIV_2 RCC_CFGR2_PPRE_DPHY_2 /*!< DCLK divided by 2 */ +#define LL_RCC_DPHY_DIV_4 (RCC_CFGR2_PPRE_DPHY_2 | RCC_CFGR2_PPRE_DPHY_0) /*!< DCLK divided by 4 */ +#define LL_RCC_DPHY_DIV_8 (RCC_CFGR2_PPRE_DPHY_2 | RCC_CFGR2_PPRE_DPHY_1) /*!< DCLK divided by 8 */ +#define LL_RCC_DPHY_DIV_16 (RCC_CFGR2_PPRE_DPHY_2 | RCC_CFGR2_PPRE_DPHY_1 | RCC_CFGR2_PPRE_DPHY_0) /*!< DCLK divided by 16 */ +/** + * @} + */ +#endif /* RCC_CFGR2_PPRE_DPHY */ /** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection * @{ @@ -386,6 +396,15 @@ typedef struct * @} */ +/** @defgroup RCC_LL_EC_STOP_WAKEUPKERCLOCK Wakeup from Stop kernel clock automatic enable selection + * @{ + */ +#define LL_RCC_STOP_WAKEUPKERCLOCK_MSIK 0x00000000U /*!< MSIK oscillator automatically enabled when exiting Stop mode */ +#define LL_RCC_STOP_WAKEUPKERCLOCK_HSI RCC_CFGR1_STOPKERWUCK /*!< HSI oscillator automatically enabled when exiting Stop mode */ +/** + * @} + */ + /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection * @{ */ @@ -440,18 +459,28 @@ typedef struct /** @defgroup RCC_LL_EC_USART_CLKSOURCE Peripheral USARTx clock source selection * @{ */ -#define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR1_USART1SEL << 16U) /*!< PCLK2 clock used as USART1 clock source */ -#define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR1_USART1SEL << 16U) | RCC_CCIPR1_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */ -#define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR1_USART1SEL << 16U) | RCC_CCIPR1_USART1SEL_1) /*!< HSI clock used as USART1 clock source */ -#define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR1_USART1SEL << 16U) | RCC_CCIPR1_USART1SEL) /*!< LSE clock used as USART1 clock source */ -#define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR1_USART2SEL << 16U) /*!< PCLK1 clock used as USART2 clock source */ -#define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR1_USART2SEL << 16U) | RCC_CCIPR1_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */ -#define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR1_USART2SEL << 16U) | RCC_CCIPR1_USART2SEL_1) /*!< HSI clock used as USART2 clock source */ -#define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR1_USART2SEL << 16U) | RCC_CCIPR1_USART2SEL) /*!< LSE clock used as USART2 clock source */ -#define LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR1_USART3SEL << 16U) /*!< PCLK3 clock used as USART3 clock source */ -#define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR1_USART3SEL << 16U) | RCC_CCIPR1_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */ -#define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR1_USART3SEL << 16U) | RCC_CCIPR1_USART3SEL_1) /*!< HSI clock used as USART3 clock source */ -#define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR1_USART3SEL << 16U) | RCC_CCIPR1_USART3SEL) /*!< LSE clock used as USART3 clock source */ +#define LL_RCC_USART1_CLKSOURCE_PCLK2 ((RCC_OFFSET_CCIPR1 << 24U)| (RCC_CCIPR1_USART1SEL_Pos << 16U)) /*!< PCLK2 clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART1SEL_Pos << 16U) | (RCC_CCIPR1_USART1SEL_0 >> RCC_CCIPR1_USART1SEL_Pos)) /*!< SYSCLK clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART1SEL_Pos << 16U) | (RCC_CCIPR1_USART1SEL_1 >> RCC_CCIPR1_USART1SEL_Pos)) /*!< HSI clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART1SEL_Pos << 16U) | (RCC_CCIPR1_USART1SEL >> RCC_CCIPR1_USART1SEL_Pos)) /*!< LSE clock used as USART1 clock source */ +#if defined(USART2) +#define LL_RCC_USART2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U)) /*!< PCLK1 clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U) | (RCC_CCIPR1_USART2SEL_0 >> RCC_CCIPR1_USART2SEL_Pos)) /*!< SYSCLK clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U) | (RCC_CCIPR1_USART2SEL_1 >> RCC_CCIPR1_USART2SEL_Pos)) /*!< HSI clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U) | (RCC_CCIPR1_USART2SEL >> RCC_CCIPR1_USART2SEL_Pos)) /*!< LSE clock used as USART2 clock source */ +#endif /* USART2 */ +#define LL_RCC_USART3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U)) /*!< PCLK3 clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U) | (RCC_CCIPR1_USART3SEL_0 >> RCC_CCIPR1_USART3SEL_Pos)) /*!< SYSCLK clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U) | (RCC_CCIPR1_USART3SEL_1 >> RCC_CCIPR1_USART3SEL_Pos)) /*!< HSI clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U) | (RCC_CCIPR1_USART3SEL >> RCC_CCIPR1_USART3SEL_Pos)) /*!< LSE clock used as USART3 clock source */ +#if defined (RCC_CCIPR2_USART6SEL) +#define LL_RCC_USART6_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U)) /*!< PCLK1 clock used as USART6 clock source */ +#define LL_RCC_USART6_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | (RCC_CCIPR2_USART6SEL_0 >> RCC_CCIPR2_USART6SEL_Pos)) /*!< SYSCLK clock used as USART6 clock source */ +#define LL_RCC_USART6_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | (RCC_CCIPR2_USART6SEL_1 >> RCC_CCIPR2_USART6SEL_Pos)) /*!< HSI clock used as USART6 clock source */ +#define LL_RCC_USART6_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | (RCC_CCIPR2_USART6SEL >> RCC_CCIPR2_USART6SEL_Pos)) /*!< LSE clock used as USART6 clock source */ +/* Legacy define */ +#define LL_RCC_USART6_CLKSOURCE_PCLK2 LL_RCC_USART6_CLKSOURCE_PCLK1 +#endif /* RCC_CCIPR2_USART6SEL */ /** * @} */ @@ -493,27 +522,45 @@ typedef struct (RCC_CCIPR1_I2C1SEL_1 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */ #define LL_RCC_I2C1_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \ (RCC_CCIPR1_I2C1SEL >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< MSIK clock used as I2C1 clock source */ -#define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */ #define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \ (RCC_CCIPR1_I2C2SEL_0 >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */ #define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \ (RCC_CCIPR1_I2C2SEL_1 >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */ #define LL_RCC_I2C2_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \ (RCC_CCIPR1_I2C2SEL >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< MSIK clock used as I2C2 clock source */ -#define LL_RCC_I2C3_CLKSOURCE_PCLK3 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U)) /*!< PCLK3 clock used as I2C3 clock source */ +#define LL_RCC_I2C3_CLKSOURCE_PCLK3 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U)) /*!< PCLK3 clock used as I2C3 clock source */ #define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \ (RCC_CCIPR3_I2C3SEL_0 >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */ #define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \ (RCC_CCIPR3_I2C3SEL_1 >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */ #define LL_RCC_I2C3_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \ (RCC_CCIPR3_I2C3SEL >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< MSIK clock used as I2C3 clock source */ -#define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */ +#define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */ #define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \ (RCC_CCIPR1_I2C4SEL_0 >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */ #define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \ (RCC_CCIPR1_I2C4SEL_1 >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */ #define LL_RCC_I2C4_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \ (RCC_CCIPR1_I2C4SEL >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< MSIK clock used as I2C4 clock source */ +#if defined (RCC_CCIPR2_I2C5SEL) +#define LL_RCC_I2C5_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C5 clock source */ +#define LL_RCC_I2C5_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \ + (RCC_CCIPR2_I2C5SEL_0 >> RCC_CCIPR2_I2C5SEL_Pos)) /*!< SYSCLK clock used as I2C5 clock source */ +#define LL_RCC_I2C5_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \ + (RCC_CCIPR2_I2C5SEL_1 >> RCC_CCIPR2_I2C5SEL_Pos)) /*!< HSI clock used as I2C5 clock source */ +#define LL_RCC_I2C5_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \ + (RCC_CCIPR2_I2C5SEL >> RCC_CCIPR2_I2C5SEL_Pos)) /*!< MSIK clock used as I2C5 clock source */ +#endif /* RCC_CCIPR2_I2C5SEL */ +#if defined (RCC_CCIPR2_I2C6SEL) +#define LL_RCC_I2C6_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C6 clock source */ +#define LL_RCC_I2C6_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \ + (RCC_CCIPR2_I2C6SEL_0 >> RCC_CCIPR2_I2C6SEL_Pos)) /*!< SYSCLK clock used as I2C6 clock source */ +#define LL_RCC_I2C6_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \ + (RCC_CCIPR2_I2C6SEL_1 >> RCC_CCIPR2_I2C6SEL_Pos)) /*!< HSI clock used as I2C6 clock source */ +#define LL_RCC_I2C6_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \ + (RCC_CCIPR2_I2C6SEL >> RCC_CCIPR2_I2C6SEL_Pos)) /*!< MSIK clock used as I2C6 clock source */ +#endif /* RCC_CCIPR2_I2C6SEL */ /** * @} */ @@ -593,12 +640,14 @@ typedef struct #define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */ #define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | \ RCC_CCIPR2_SAI1SEL_0)) /*!< External input clock used as SAI1 clock source */ +#if defined(SAI2) #define LL_RCC_SAI2_CLKSOURCE_PLL2 (RCC_CCIPR2_SAI2SEL << 16U) /*!< PLL2 clock used as SAI2 clock source */ #define LL_RCC_SAI2_CLKSOURCE_PLL3 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_0) /*!< PLL3 clock used as SAI2 clock source */ #define LL_RCC_SAI2_CLKSOURCE_PLL1 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_1) /*!< PLL1clock used as SAI2 clock source */ #define LL_RCC_SAI2_CLKSOURCE_HSI ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_2) /*!< HSI clock used as SAI2 clock source */ #define LL_RCC_SAI2_CLKSOURCE_PIN ((RCC_CCIPR2_SAI2SEL << 16U) | (RCC_CCIPR2_SAI2SEL_1 | \ RCC_CCIPR2_SAI2SEL_0)) /*!< External input clock used as SAI2 clock source */ +#endif /* SAI2 */ /** * @} */ @@ -616,9 +665,9 @@ typedef struct * @{ */ #define LL_RCC_SDMMC12_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as SDMMC1/2 clock source */ -#define LL_RCC_SDMMC12_CLKSOURCE_PLL2 RCC_CCIPR1_CLK48MSEL_0 /*!< PLL2 "Q" clock used as SDMMC1/2 clock source */ -#define LL_RCC_SDMMC12_CLKSOURCE_PLL1 RCC_CCIPR1_CLK48MSEL_1 /*!< PLL1 "Q" clock used as SDMMC1/2 clock source */ -#define LL_RCC_SDMMC12_CLKSOURCE_MSIK RCC_CCIPR1_CLK48MSEL /*!< MSIK clock used as SDMMC1/2 clock source */ +#define LL_RCC_SDMMC12_CLKSOURCE_PLL2 RCC_CCIPR1_ICLKSEL_0 /*!< PLL2 "Q" clock used as SDMMC1/2 clock source */ +#define LL_RCC_SDMMC12_CLKSOURCE_PLL1 RCC_CCIPR1_ICLKSEL_1 /*!< PLL1 "Q" clock used as SDMMC1/2 clock source */ +#define LL_RCC_SDMMC12_CLKSOURCE_MSIK RCC_CCIPR1_ICLKSEL /*!< MSIK clock used as SDMMC1/2 clock source */ /** * @} */ @@ -637,9 +686,9 @@ typedef struct * @{ */ #define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB clock source */ -#define LL_RCC_USB_CLKSOURCE_PLL2 RCC_CCIPR1_CLK48MSEL_0 /*!< PLL2 "Q" clock used as USB clock source */ -#define LL_RCC_USB_CLKSOURCE_PLL1 RCC_CCIPR1_CLK48MSEL_1 /*!< PLL1 "Q" clock used as USB clock source */ -#define LL_RCC_USB_CLKSOURCE_MSIK RCC_CCIPR1_CLK48MSEL /*!< MSIK clock used as USB clock source */ +#define LL_RCC_USB_CLKSOURCE_PLL2 RCC_CCIPR1_ICLKSEL_0 /*!< PLL2 "Q" clock used as USB clock source */ +#define LL_RCC_USB_CLKSOURCE_PLL1 RCC_CCIPR1_ICLKSEL_1 /*!< PLL1 "Q" clock used as USB clock source */ +#define LL_RCC_USB_CLKSOURCE_MSIK RCC_CCIPR1_ICLKSEL /*!< MSIK clock used as USB clock source */ /** * @} */ @@ -701,6 +750,19 @@ typedef struct * @} */ +#if defined (HSPI1) +/** @defgroup RCC_LL_EC_HSPI1_CLKSOURCE Peripheral HSPI1 kernel clock source selection + * @{ + */ +#define LL_RCC_HSPI_CLKSOURCE_SYSCLK (0x00000000U) +#define LL_RCC_HSPI_CLKSOURCE_PLL1 RCC_CCIPR2_HSPISEL_0 +#define LL_RCC_HSPI_CLKSOURCE_PLL2 RCC_CCIPR2_HSPISEL_1 +#define LL_RCC_HSPI_CLKSOURCE_PLL3 RCC_CCIPR2_HSPISEL +/** + * @} + */ +#endif /* HSPI1 */ + /** @defgroup RCC_LL_EC_TIM_INPUT_CAPTURE_CLOCKSource TIM Input capture clock source selection * @{ */ @@ -728,9 +790,18 @@ typedef struct /** @defgroup RCC_LL_EC_USART Peripheral USARTx get clock source * @{ */ -#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR1_USART1SEL /*!< USART1 Clock source selection */ -#define LL_RCC_USART2_CLKSOURCE RCC_CCIPR1_USART2SEL /*!< USART2 Clock source selection */ -#define LL_RCC_USART3_CLKSOURCE RCC_CCIPR1_USART3SEL /*!< USART3 Clock source selection */ +#define LL_RCC_USART1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_USART1SEL_Pos << 16U) | \ + (RCC_CCIPR1_USART1SEL >> RCC_CCIPR1_USART1SEL_Pos)) /*!< USART1 Clock source selection */ +#if defined(USART2) +#define LL_RCC_USART2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_USART2SEL_Pos << 16U) | \ + (RCC_CCIPR1_USART2SEL >> RCC_CCIPR1_USART2SEL_Pos)) /*!< USART2 Clock source selection */ +#endif /* USART2 */ +#define LL_RCC_USART3_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_USART3SEL_Pos << 16U) | \ + (RCC_CCIPR1_USART3SEL >> RCC_CCIPR1_USART3SEL_Pos)) /*!< USART3 Clock source selection */ +#if defined (RCC_CCIPR2_USART6SEL) +#define LL_RCC_USART6_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | \ + (RCC_CCIPR2_USART6SEL >> RCC_CCIPR2_USART6SEL_Pos)) /*!< USART6 Clock source selection */ +#endif /* RCC_CCIPR2_USART6SEL */ /** * @} */ @@ -765,6 +836,41 @@ typedef struct * @} */ +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE_PHY (RCC_CCIPR2_DSIHOSTSEL) +#define LL_RCC_DSI_CLKSOURCE_PLL3 (0x00000000U) +/** + * @} + */ +#endif /* DSI */ + +#if defined(LTDC) +/** @defgroup RCC_LL_EC_LTDC_CLKSOURCE Peripheral LTDC clock source selection + * @{ + */ +#define LL_RCC_LTDC_CLKSOURCE_PLL2 (RCC_CCIPR2_LTDCSEL) +#define LL_RCC_LTDC_CLKSOURCE_PLL3 (0x00000000U) +/** + * @} + */ +#endif /* LTDC */ + +#if defined (RCC_CCIPR2_USBPHYCSEL) +/** @defgroup RCC_LL_EC_USBPHY_CLKSOURCE Peripheral USBPHY clock source selection + * @{ + */ +#define LL_RCC_USBPHYCLKSOURCE_HSE (0x00000000U) /*!< HSE clock selected as USBPHYC clock */ +#define LL_RCC_USBPHYCLKSOURCE_HSE_DIV2 RCC_CCIPR2_USBPHYCSEL_1 /*!< HSE clock divided by 2 selected as USBPHYC clock */ +#define LL_RCC_USBPHYCLKSOURCE_PLL1 RCC_CCIPR2_USBPHYCSEL_0 /*!< PLL1 divider P selected as USBPHYC clock */ +#define LL_RCC_USBPHYCLKSOURCE_PLL1_DIV2 (RCC_CCIPR2_USBPHYCSEL_1 | RCC_CCIPR2_USBPHYCSEL_0) /*!< PLL1 divider P divided by 2 selected as USBPHYC clock */ +/** + * @} + */ +#endif /* RCC_CCIPR2_USBPHYCSEL */ + /** @defgroup RCC_LL_EC_I2C Peripheral I2Cx get clock source * @{ */ @@ -776,6 +882,14 @@ typedef struct (RCC_CCIPR3_I2C3SEL >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */ #define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \ (RCC_CCIPR1_I2C4SEL >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */ +#if defined (RCC_CCIPR2_I2C5SEL) +#define LL_RCC_I2C5_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \ + (RCC_CCIPR2_I2C5SEL >> RCC_CCIPR2_I2C5SEL_Pos)) /*!< I2C1 Clock source selection */ +#endif /* RCC_CCIPR2_I2C5SEL */ +#if defined (RCC_CCIPR2_I2C6SEL) +#define LL_RCC_I2C6_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \ + (RCC_CCIPR2_I2C6SEL >> RCC_CCIPR2_I2C6SEL_Pos)) /*!< I2C1 Clock source selection */ +#endif /* RCC_CCIPR2_I2C6SEL */ /** * @} */ @@ -797,7 +911,9 @@ typedef struct * @{ */ #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL /*!< SAI1 Clock source selection */ +#if defined (SAI2) #define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR2_SAI2SEL /*!< SAI2 Clock source selection */ +#endif /* SAI2 */ /** * @} */ @@ -813,7 +929,7 @@ typedef struct /** @defgroup RCC_LL_EC_SDMMC1/2 Peripheral SDMMC get clock source * @{ */ -#define LL_RCC_SDMMC_CLKSOURCE RCC_CCIPR1_CLK48MSEL /*!< SDMMC1/2 Clock source selection */ +#define LL_RCC_SDMMC_CLKSOURCE RCC_CCIPR1_ICLKSEL /*!< SDMMC1/2 Clock source selection */ /** * @} */ @@ -829,7 +945,7 @@ typedef struct /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source * @{ */ -#define LL_RCC_USB_CLKSOURCE RCC_CCIPR1_CLK48MSEL /*!< USB Clock source selection */ +#define LL_RCC_USB_CLKSOURCE RCC_CCIPR1_ICLKSEL /*!< USB Clock source selection */ /** * @} */ @@ -881,6 +997,15 @@ typedef struct /** * @} */ +#if defined (HSPI1) +/** @defgroup RCC_LL_EC_HSPI Peripheral HSPI get clock source + * @{ + */ +#define LL_RCC_HSPI_CLKSOURCE RCC_CCIPR2_HSPISEL /*!< HSPI Clock source selection */ +/** + * @} + */ +#endif /* HSPI */ /** @defgroup RCC_LL_EC_SAES Peripheral SAES get clock source * @{ @@ -890,6 +1015,36 @@ typedef struct * @} */ +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE RCC_CCIPR2_DSIHOSTSEL +/** + * @} + */ +#endif /* DSI */ + +#if defined(LTDC) +/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source + * @{ + */ +#define LL_RCC_LTDC_CLKSOURCE RCC_CCIPR2_LTDCSEL +/** + * @} + */ +#endif /* LTDC */ + +#if defined (RCC_CCIPR2_USBPHYCSEL) +/** @defgroup RCC_LL_EC_USBPHY Peripheral USBPHY get clock source + * @{ + */ +#define LL_RCC_USBPHY_CLKSOURCE RCC_CCIPR2_USBPHYCSEL +/** + * @} + */ +#endif /* RCC_CCIPR2_USBPHYCSEL */ + /** @defgroup RCC_LL_EC_PLL1SOURCE PLL1 entry clock source * @{ */ @@ -897,6 +1052,12 @@ typedef struct #define LL_RCC_PLL1SOURCE_MSIS RCC_PLL1CFGR_PLL1SRC_0 /*!< MSIS clock selected as main PLL1 entry clock source */ #define LL_RCC_PLL1SOURCE_HSI RCC_PLL1CFGR_PLL1SRC_1 /*!< HSI clock selected as main PLL1 entry clock source */ #define LL_RCC_PLL1SOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) /*!< HSE clock selected as main PLL1 entry clock source */ + +#define LL_RCC_PLLSOURCE_NONE LL_RCC_PLL1SOURCE_NONE /*!< alias define for compatibility with legacy code */ +#define LL_RCC_PLLSOURCE_MSIS LL_RCC_PLL1SOURCE_MSIS /*!< alias define for compatibility with legacy code */ +#define LL_RCC_PLLSOURCE_HSI LL_RCC_PLL1SOURCE_HSI /*!< alias define for compatibility with legacy code */ +#define LL_RCC_PLLSOURCE_HSE LL_RCC_PLL1SOURCE_HSE /*!< alias define for compatibility with legacy code */ + /** * @} */ @@ -904,8 +1065,8 @@ typedef struct /** @defgroup RCC_LL_EC_PLLINPUTRANGE All PLLs input ranges * @{ */ -#define LL_RCC_PLLINPUTRANGE_4_8 0x00000002U /*!< VCO input range: 4 to 8 MHz */ -#define LL_RCC_PLLINPUTRANGE_8_16 0x00000003U /*!< VCO input range: 8 to 16 MHz */ +#define LL_RCC_PLLINPUTRANGE_4_8 0x00000000U /*!< VCO input range: 4 to 8 MHz */ +#define LL_RCC_PLLINPUTRANGE_8_16 RCC_PLL1CFGR_PLL1RGE /*!< VCO input range: 8 to 16 MHz */ /** * @} */ @@ -968,12 +1129,17 @@ typedef struct #define LL_RCC_PLL2_NSEC 0U /*!< main PLL2 clock configuration secure/non-secure access */ #define LL_RCC_PLL3_SEC RCC_SECCFGR_PLL3SEC /*!< PLL3 clock configuration security */ #define LL_RCC_PLL3_NSEC 0U /*!< main PLL3 clock configuration secure/non-secure access */ -#define LL_RCC_CLK48M_SEC RCC_SECCFGR_CLK48MSEC /*!< 48MHz clock source selection security */ -#define LL_RCC_CLK48M_NSEC 0U /*!< 48MHz clock source selection secure/non-secure access */ +#define LL_RCC_ICLK_SEC RCC_SECCFGR_ICLKSEC /*!< ICLK clock source selection security */ +#define LL_RCC_ICLK_NSEC 0U /*!< ICLK clock source selection secure/non-secure access */ #define LL_RCC_HSI48_SEC RCC_SECCFGR_HSI48SEC /*!< HSI48 clock configuration security */ #define LL_RCC_HSI48_NSEC 0U /*!< HSI48 clock configuration secure/non-secure access */ #define LL_RCC_RESET_FLAGS_SEC RCC_SECCFGR_RMVFSEC /*!< Remove reset flag security */ #define LL_RCC_RESET_FLAGS_NSEC 0U + +#define LL_RCC_PLL_SEC LL_RCC_PLL1_NSEC /*!< alias define for compatibility with legacy code */ +#define LL_RCC_PLL_NSEC LL_RCC_PLL1_NSEC /*!< alias define for compatibility with legacy code */ +#define LL_RCC_CLK48M_SEC LL_RCC_ICLK_SEC /*!< alias define for compatibility with legacy code */ +#define LL_RCC_CLK48M_NSEC LL_RCC_ICLK_NSEC /*!< alias define for compatibility with legacy code */ /** * @} */ @@ -1020,12 +1186,12 @@ typedef struct * @param __INPUTFREQ__ PLL1 Input frequency (based on MSI/HSE/HSI) * @param __PLL1M__ parameter can be a value between 1 and 16 * @param __PLL1N__ parameter can be a value between 4 and 512 - * @param __PLL1R__ parameter can be a value between 1 and 128 + * @param __PLL1R__ parameter can be a value between 1 and 128 (Only division by 1 and even division are allowed) * @retval PLL1 clock frequency (in Hz) */ - #define __LL_RCC_CALC_PLL1CLK_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1R__) ((((__INPUTFREQ__) /(__PLL1M__)) * \ (__PLL1N__)) / (__PLL1R__)) +#define __LL_RCC_CALC_PLLCLK_FREQ __LL_RCC_CALC_PLL1CLK_FREQ /*!< alias for compatibility with legacy code */ /** * @brief Helper macro to calculate the PLL1CLK frequency used on SAI domain @@ -1034,11 +1200,12 @@ typedef struct * @param __INPUTFREQ__ PLL1 Input frequency (based on MSI/HSE/HSI) * @param __PLL1M__ parameter can be a value between 1 and 16 * @param __PLL1N__ parameter can be a value between 4 and 512 - * @param __PLL1P__ parameter can be a value between 2 and 128 + * @param __PLL1P__ parameter can be a value between 1 and 128 * @retval PLL1 clock frequency (in Hz) */ #define __LL_RCC_CALC_PLL1CLK_SAI_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1P__) ((((__INPUTFREQ__) \ /(__PLL1M__)) * (__PLL1N__)) / (__PLL1P__)) +#define __LL_RCC_CALC_PLLCLK_SAI_FREQ __LL_RCC_CALC_PLL1CLK_SAI_FREQ /*!< alias for compatibility with legacy code */ /** * @brief Helper macro to calculate the PLL1CLK frequency used on 48M domain @@ -1050,9 +1217,9 @@ typedef struct * @param __PLL1Q__ parameter can be a value between 1 and 128 * @retval PLL clock frequency (in Hz) */ - #define __LL_RCC_CALC_PLL1CLK_48M_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1Q__) ((((__INPUTFREQ__) \ /(__PLL1M__)) * (__PLL1N__)) / (__PLL1Q__)) +#define __LL_RCC_CALC_PLLCLK_48M_FREQ __LL_RCC_CALC_PLL1CLK_48M_FREQ /*!< alias for compatibility with legacy code */ /** * @brief Helper macro to calculate the PLL2 frequency used for SAI domain @@ -1061,7 +1228,7 @@ typedef struct * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) * @param __PLL2M__ parameter can be a value between 1 and 16 * @param __PLL2N__ parameter can be a value between 4 and 512 - * @param __PLL2P__ parameter can be a value between 2 and 128 + * @param __PLL2P__ parameter can be a value between 1 and 128 * @retval PLL2 clock frequency (in Hz) */ #define __LL_RCC_CALC_PLL2CLK_SAI_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2P__) ((((__INPUTFREQ__) \ @@ -1100,7 +1267,7 @@ typedef struct * @param __INPUTFREQ__ PLL3 Input frequency (based on MSI/HSE/HSI) * @param __PLL3M__ parameter can be a value between 1 and 16 * @param __PLL3N__ parameter can be a value between 4 and 512 - * @param __PLL3P__ parameter can be a value between 2 and 128 + * @param __PLL3P__ parameter can be a value between 1 and 128 * @retval PLL3 clock frequency (in Hz) */ #define __LL_RCC_CALC_PLL3CLK_SAI_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3P__)((((__INPUTFREQ__) \ @@ -1119,6 +1286,23 @@ typedef struct #define __LL_RCC_CALC_PLL3CLK_48M_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3Q__) ((((__INPUTFREQ__) \ /(__PLL3M__)) * (__PLL3N__)) / (__PLL3Q__)) +#if defined(HSPI1) || defined(LTDC) +/** + * @brief Helper macro to calculate the PLL3 frequency used on HSPI domain + * @note ex: @ref __LL_RCC_CALC_PLL3CLK_HSPI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetDivider (), + * @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetQ ()); + * @param __INPUTFREQ__ PLL3 Input frequency (based on MSI/HSE/HSI) + * @param __PLL3M__ parameter can be a value between 1 and 16 + * @param __PLL3N__ parameter can be a value between 4 and 512 + * @param __PLL3R__ parameter can be a value between 1 and 128 + * @retval PLL3 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLL3CLK_HSPI_LTDC_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3R__) ((((__INPUTFREQ__) \ + /(__PLL3M__)) * (__PLL3N__)) / (__PLL3R__)) +/* Legacy define */ +#define __LL_RCC_CALC_PLL3CLK_HSPI_FREQ __LL_RCC_CALC_PLL3CLK_HSPI_LTDC_FREQ +#endif /* HSPI1 || LTDC */ + /** * @brief Helper macro to calculate the HCLK frequency * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK) @@ -1347,7 +1531,7 @@ __STATIC_INLINE void LL_RCC_HSE_SetClockMode(uint32_t HSEMode) } /** - * @brief Get Externel HSE clock mode + * @brief Get External HSE clock mode * @rmtoll CR HSEEXT LL_RCC_HSE_GetClockMode * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_HSE_ANALOG_MODE @@ -1671,6 +1855,39 @@ __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == RCC_BDCR_LSECSSD) ? 1UL : 0UL); } +/** + * @brief Enable LSE clock glitch filter. + * @note The glitches on LSE can be filtred by setting the LSEGFON. + * @note LSEGFON must be written when the LSE is disabled (LSEON = 0 and LSERDY = 0). + * @rmtoll BDCR LSEGFON LL_RCC_LSE_EnableGlitchFilter + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableGlitchFilter(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEGFON); +} + +/** + * @brief Disable LSE clock glitch filter. + * @note LSEGFON must be written when the LSE is disabled (LSEON = 0 and LSERDY = 0). + * @rmtoll BDCR LSEGFON LL_RCC_LSE_DisableGlitchFilter + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableGlitchFilter(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEGFON); +} + +/** + * @brief Check if LSE clock glitch filter is enabled + * @rmtoll BDCR LSEGFON LL_RCC_LSE_IsGlitchFilterEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsGlitchFilterEnabled(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSEGFON) == RCC_BDCR_LSEGFON) ? 1UL : 0UL); +} + /** * @} */ @@ -1830,6 +2047,7 @@ __STATIC_INLINE void LL_RCC_MSIS_Enable(void) { SET_BIT(RCC->CR, RCC_CR_MSISON); } +#define LL_RCC_MSI_Enable LL_RCC_MSIS_Enable /*!< alias define for compatibility with legacy code */ /** * @brief Disable MSIS oscillator @@ -1840,6 +2058,7 @@ __STATIC_INLINE void LL_RCC_MSIS_Disable(void) { CLEAR_BIT(RCC->CR, RCC_CR_MSISON); } +#define LL_RCC_MSI_Disable LL_RCC_MSIS_Disable /*!< alias define for compatibility with legacy code */ /** * @brief Check if MSIS oscillator Ready @@ -1850,6 +2069,7 @@ __STATIC_INLINE uint32_t LL_RCC_MSIS_IsReady(void) { return ((READ_BIT(RCC->CR, RCC_CR_MSISRDY) == RCC_CR_MSISRDY) ? 1UL : 0UL); } +#define LL_RCC_MSI_IsReady LL_RCC_MSIS_IsReady /*!< alias define for compatibility with legacy code */ /** * @brief Enable MSI PLL-mode (Hardware auto calibration with LSE) @@ -1877,6 +2097,16 @@ __STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void) CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN); } +/** + * @brief Check if MSI-PLL mode has been enabled or not + * @rmtoll CR MSIPLLEN LL_RCC_IsEnabledPLLMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledPLLMode(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_MSIPLLEN) == RCC_CR_MSIPLLEN) ? 1UL : 0UL); +} + /** * @brief Set clock source in PLL mode * @rmtoll CR MSIPLLSEL LL_RCC_SetMSIPLLMode @@ -2039,6 +2269,7 @@ __STATIC_INLINE void LL_RCC_MSIS_SetRange(uint32_t Range) { MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE, Range); } +#define LL_RCC_MSI_SetRange LL_RCC_MSIS_SetRange /*!< alias define for compatibility with legacy code */ /** * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode. @@ -2065,22 +2296,24 @@ __STATIC_INLINE uint32_t LL_RCC_MSIS_GetRange(void) { return (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE)); } +#define LL_RCC_MSI_GetRange LL_RCC_MSIS_GetRange /*!< alias define for compatibility with legacy code */ /** * @brief Configure MSIS range used after standby * @rmtoll CSR MSISSRANGE LL_RCC_MSIS_SetRangeAfterStandby * @param Range This parameter can be one of the following values: - * @arg @ref LL_RCC_MSISRANGE_4 - * @arg @ref LL_RCC_MSISRANGE_5 - * @arg @ref LL_RCC_MSISRANGE_6 - * @arg @ref LL_RCC_MSISRANGE_7 - * @arg @ref LL_RCC_MSISRANGE_8 + * @arg @ref LL_RCC_MSISSRANGE_4 + * @arg @ref LL_RCC_MSISSRANGE_5 + * @arg @ref LL_RCC_MSISSRANGE_6 + * @arg @ref LL_RCC_MSISSRANGE_7 + * @arg @ref LL_RCC_MSISSRANGE_8 * @retval None */ __STATIC_INLINE void LL_RCC_MSIS_SetRangeAfterStandby(uint32_t Range) { MODIFY_REG(RCC->CSR, RCC_CSR_MSISSRANGE, Range); } +#define LL_RCC_MSI_SetRangeAfterStandby LL_RCC_MSIS_SetRangeAfterStandby /*!< alias define for compatibility with legacy code */ /** * @brief Get MSIS range used after standby @@ -2096,6 +2329,7 @@ __STATIC_INLINE uint32_t LL_RCC_MSIS_GetRangeAfterStandby(void) { return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISSRANGE)); } +#define LL_RCC_MSI_GetRangeAfterStandby LL_RCC_MSIS_GetRangeAfterStandby /*!< alias define for compatibility with legacy code */ /** * @brief Set MSI OSCILLATORx Calibration trimming @@ -2410,6 +2644,24 @@ __STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler) MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, Prescaler); } +#if defined(RCC_CFGR2_PPRE_DPHY) +/** + * @brief Set DPHY clock prescaler + * @rmtoll CFGR2 PPRE_DPHY LL_RCC_SetDPHYPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_DPHY_DIV_1 + * @arg @ref LL_RCC_DPHY_DIV_2 + * @arg @ref LL_RCC_DPHY_DIV_4 + * @arg @ref LL_RCC_DPHY_DIV_8 + * @arg @ref LL_RCC_DPHY_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDPHYPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE_DPHY, Prescaler); +} +#endif /* RCC_CFGR2_PPRE_DPHY */ + /** * @brief Get AHB prescaler * @rmtoll CFGR2 HPRE LL_RCC_GetAHBPrescaler @@ -2487,6 +2739,23 @@ __STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void) return (uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_PPRE3)); } +#if defined(RCC_CFGR2_PPRE_DPHY) +/** + * @brief Get DPHY clock prescaler + * @rmtoll CFGR2 PPRE_DPHY LL_RCC_GetDPHYPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DPHY_DIV_1 + * @arg @ref LL_RCC_DPHY_DIV_2 + * @arg @ref LL_RCC_DPHY_DIV_4 + * @arg @ref LL_RCC_DPHY_DIV_8 + * @arg @ref LL_RCC_DPHY_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetDPHYPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE_DPHY)); +} +#endif /* RCC_CFGR2_PPRE_DPHY */ + /** * @brief Set Clock After Wake-Up From Stop mode * @rmtoll CFGR1 STOPWUCK LL_RCC_SetClkAfterWakeFromStop @@ -2511,6 +2780,32 @@ __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void) { return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_STOPWUCK)); } + +/** + * @brief Set Kernel Clock After Wake-Up From Stop mode + * @rmtoll CFGR1 STOPKERWUCK LL_RCC_SetKerClkAfterWakeFromStop + * @param Clock This parameter can be one of the following values: + * @arg @ref LL_RCC_STOP_WAKEUPKERCLOCK_MSIK + * @arg @ref LL_RCC_STOP_WAKEUPKERCLOCK_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetKerClkAfterWakeFromStop(uint32_t Clock) +{ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK, Clock); +} + +/** + * @brief Get Kernel Clock After Wake-Up From Stop mode + * @rmtoll CFGR1 STOPKERWUCK LL_RCC_GetKerClkAfterWakeFromStop + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_STOP_WAKEUPKERCLOCK_MSIK + * @arg @ref LL_RCC_STOP_WAKEUPKERCLOCK_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetKerClkAfterWakeFromStop(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK)); +} + /** * @} */ @@ -2558,25 +2853,35 @@ __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescale * @brief Configure USARTx clock source * @rmtoll CCIPR1 USART1SEL LL_RCC_SetUSARTClockSource\n * CCIPR1 USART2SEL LL_RCC_SetUSARTClockSource\n - * CCIPR1 USART3SEL LL_RCC_SetUSARTClockSource + * CCIPR1 USART3SEL LL_RCC_SetUSARTClockSource\n + * CCIPR2 USART6SEL LL_RCC_SetUSARTClockSource * @param USARTxSource This parameter can be one of the following values: * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE - * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI - * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*) + * + * (*) Availability depends on devices. + * @retval None */ __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) { - MODIFY_REG(RCC->CCIPR1, USARTxSource >> 16U, (USARTxSource & 0x0000FFFFU)); + __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (USARTxSource >> 24U)); + MODIFY_REG(*reg, 3UL << ((USARTxSource & 0x001F0000U) >> 16U), ((USARTxSource & 0x000000FFU) << \ + ((USARTxSource & 0x001F0000U) >> 16U))); } /** @@ -2729,11 +3034,14 @@ __STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource) * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1 - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2 - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3 - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN - * @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1 (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2 (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3 (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI (*) + * + * (*) Availability depends on devices. + * * @retval None */ __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) @@ -2756,7 +3064,7 @@ __STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource) /** * @brief Configure SDMMC1/2 clock source - * @rmtoll CCIPR1 CLK48MSEL LL_RCC_SetSDMMCClockSource + * @rmtoll CCIPR1 ICLKSEL LL_RCC_SetSDMMCClockSource * @param SDMMCxSource This parameter can be one of the following values: * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_HSI48 * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL1 @@ -2766,7 +3074,7 @@ __STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource) */ __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource) { - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, SDMMCxSource); + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ICLKSEL, SDMMCxSource); } /** @@ -2783,9 +3091,26 @@ __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_RNGSEL, RNGxSource); } +#if defined(RCC_CCIPR2_USBPHYCSEL) +/** + * @brief Configure USBPHY clock source + * @rmtoll CCIPR2 USBPHYCSEL LL_RCC_SetUSBPHYClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_USBPHYCLKSOURCE_HSE + * @arg @ref LL_RCC_USBPHYCLKSOURCE_HSE_DIV2 + * @arg @ref LL_RCC_USBPHYCLKSOURCE_PLL1 + * @arg @ref LL_RCC_USBPHYCLKSOURCE_PLL1_DIV2 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBPHYClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBPHYCSEL, Source); +} +#endif /* RCC_CCIPR2_USBPHYCSEL */ + /** * @brief Configure USB clock source - * @rmtoll CCIPR1 CLK48MSEL LL_RCC_SetUSBClockSource + * @rmtoll CCIPR1 ICLKSEL LL_RCC_SetUSBClockSource * @param USBxSource This parameter can be one of the following values: * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1 @@ -2795,7 +3120,7 @@ __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) */ __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) { - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, USBxSource); + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ICLKSEL, USBxSource); } /** @@ -2875,6 +3200,22 @@ __STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t Source) MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OCTOSPISEL, Source); } +#if defined (HSPI1) +/** + * @brief Configure HSPI kernel clock source + * @rmtoll CCIPR2 HSPISEL LL_RCC_SetHSPIClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_HSPI_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL1 + * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL2 + * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL3 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetHSPIClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_HSPISEL, Source); +} +#endif /* HSPI1 */ /** * @brief Configure SAES clock source * @rmtoll CCIPR2 SAESSEL LL_RCC_SetSAESClockSource @@ -2888,32 +3229,71 @@ __STATIC_INLINE void LL_RCC_SetSAESClockSource(uint32_t Source) MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAESSEL, Source); } +#if defined(DSI) +/** + * @brief Configure DSIx clock source + * @rmtoll CCIPR2 DSISEL LL_RCC_SetDSIClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL3 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSIHOSTSEL, Source); +} +#endif /* DSI */ + +#if defined(LTDC) +/** + * @brief Configure LTDCx clock source + * @rmtoll CCIPR2 LTDCSEL LL_RCC_SetLTDCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL2 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL3 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LTDCSEL, Source); +} +#endif /* LTDC */ /** * @brief Get USARTx clock source * @rmtoll CCIPR1 USART1SEL LL_RCC_GetUSARTClockSource\n * CCIPR1 USART2SEL LL_RCC_GetUSARTClockSource\n - * CCIPR1 USART3SEL LL_RCC_GetUSARTClockSource + * CCIPR1 USART3SEL LL_RCC_GetUSARTClockSource\n + * CCIPR2 USART6SEL LL_RCC_GetUSARTClockSource * @param USARTx This parameter can be one of the following values: * @arg @ref LL_RCC_USART1_CLKSOURCE - * @arg @ref LL_RCC_USART2_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE (*) * @arg @ref LL_RCC_USART3_CLKSOURCE + * @arg @ref LL_RCC_USART6_CLKSOURCE (*) * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE - * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI - * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*) + * + * (*) Availability depends on devices. */ __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) { - return (uint32_t)(READ_BIT(RCC->CCIPR1, USARTx) | (USARTx << 16U)); + __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (USARTx >> 24U)); + return (uint32_t)((READ_BIT(*reg, 3UL << ((USARTx & 0x001F0000U) >> 16U)) >> \ + ((USARTx & 0x001F0000U) >> 16U)) | (USARTx & 0xFFFF0000U)); } /** @@ -3104,18 +3484,20 @@ __STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx) * CCIPR2 SAI2SEL LL_RCC_GetSAIClockSource * @param SAIx This parameter can be one of the following values: * @arg @ref LL_RCC_SAI1_CLKSOURCE - * @arg @ref LL_RCC_SAI2_CLKSOURCE + * @arg @ref LL_RCC_SAI2_CLKSOURCE (*) * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1 - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2 - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3 - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN - * @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1 (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2 (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3 (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI (*) + * + * (*) Availability depends on devices. */ __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) { @@ -3138,7 +3520,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx) /** * @brief Get SDMMC1/2 clock source - * @rmtoll CCIPR1 CLK48MSEL LL_RCC_GetSDMMC12ClockSource + * @rmtoll CCIPR1 ICLKSEL LL_RCC_GetSDMMCClockSource * @param SDMMCx This parameter can be one of the following values: * @arg @ref LL_RCC_SDMMC_CLKSOURCE * @retval Returned value can be one of the following values: @@ -3167,9 +3549,27 @@ __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) return (uint32_t)(READ_BIT(RCC->CCIPR2, RNGx)); } +#if defined(RCC_CCIPR2_USBPHYCSEL) +/** + * @brief Get USBPHYx clock source + * @rmtoll CCIPR2 USBPHYCSEL LL_RCC_GetUSBPHYClockSource + * @param USBPHYx This parameter can be one of the following values: + * @arg @ref LL_RCC_USBPHY_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USBPHYCLKSOURCE_HSE + * @arg @ref LL_RCC_USBPHYCLKSOURCE_HSE_DIV2 + * @arg @ref LL_RCC_USBPHYCLKSOURCE_PLL1 + * @arg @ref LL_RCC_USBPHYCLKSOURCE_PLL1_DIV2 + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBPHYClockSource(uint32_t USBPHYx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, USBPHYx)); +} +#endif /* RCC_CCIPR2_USBPHYCSEL */ + /** * @brief Get USBx clock source - * @rmtoll CCIPR1 CLK48MSEL LL_RCC_GetUSBClockSource + * @rmtoll CCIPR1 ICLKSEL LL_RCC_GetUSBClockSource * @param USBx This parameter can be one of the following values: * @arg @ref LL_RCC_USB_CLKSOURCE * @retval Returned value can be one of the following values: @@ -3263,6 +3663,24 @@ __STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx) { return (uint32_t)(READ_BIT(RCC->CCIPR2, OCTOSPIx)); } + +#if defined (HSPI1) +/** + * @brief Get HSPI clock source + * @rmtoll CCIPR2 HSPISEL LL_RCC_GetHSPIClockSource + * @param HSPIx This parameter can be one of the following values: + * @arg @ref LL_RCC_HSPI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_HSPI_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL1 + * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL2 + * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL3 + */ +__STATIC_INLINE uint32_t LL_RCC_GetHSPIClockSource(uint32_t HSPIx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, HSPIx)); +} +#endif /* HSPI1 */ /** * @} */ @@ -3281,6 +3699,38 @@ __STATIC_INLINE uint32_t LL_RCC_GetSAESClockSource(uint32_t SAESx) return (uint32_t)(READ_BIT(RCC->CCIPR2, SAESx)); } +#if defined(DSI) +/** + * @brief Get DSI clock source + * @rmtoll CCIPR2 DSISEL LL_RCC_GetDSIClockSource + * @param DSIx This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL3 + */ +__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, DSIx)); +} +#endif /* DSI */ + +#if defined(LTDC) +/** + * @brief Get LTDC clock source + * @rmtoll CCIPR2 LTDCSEL LL_RCC_GetLTDCClockSource + * @param LTDCx This parameter can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL2 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL3 + */ +__STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t LTDCx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, LTDCx)); +} +#endif /* LTDC */ + /** @defgroup RCC_LL_EF_RTC RTC * @{ */ @@ -3385,6 +3835,7 @@ __STATIC_INLINE void LL_RCC_PLL1_Enable(void) { SET_BIT(RCC->CR, RCC_CR_PLL1ON); } +#define LL_RCC_PLL_Enable LL_RCC_PLL1_Enable /*!< alias for compatibility with legacy code */ /** * @brief Disable PLL1 @@ -3396,6 +3847,7 @@ __STATIC_INLINE void LL_RCC_PLL1_Disable(void) { CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON); } +#define LL_RCC_PLL_Disable LL_RCC_PLL1_Disable /*!< alias for compatibility with legacy code */ /** * @brief Check if PLL1 Ready @@ -3406,6 +3858,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void) { return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == RCC_CR_PLL1RDY) ? 1UL : 0UL); } +#define LL_RCC_PLL_IsReady LL_RCC_PLL1_IsReady /*!< alias for compatibility with legacy code */ /** * @brief Configure PLL1 used for SYSCLK Domain @@ -3421,7 +3874,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void) * @arg @ref LL_RCC_PLL1SOURCE_HSI * @arg @ref LL_RCC_PLL1SOURCE_HSE * @param PLLM parameter can be a value between 1 and 16 - * @param PLLR parameter can be a value between 1 and 128 + * @param PLLR parameter can be a value between 1 and 128 (Only division by 1 and even division are allowed) * @param PLLN parameter can be a value between 4 and 512 * @retval None */ @@ -3433,6 +3886,7 @@ __STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM RCC_PLL1DIVR_PLL1N_Pos) | ((PLLR - 1UL) << \ RCC_PLL1DIVR_PLL1R_Pos)); } +#define LL_RCC_PLL_ConfigDomain_SYS LL_RCC_PLL1_ConfigDomain_SYS /*!< alias for compatibility with legacy code */ /** * @brief Configure PLL1 used for SAI domain clock @@ -3449,7 +3903,7 @@ __STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM * @arg @ref LL_RCC_PLL1SOURCE_HSE * @param PLLM parameter can be a value between 1 and 16 * @param PLLN parameter can be a value between 4 and 512 - * @param PLLP parameter can be a value between 2 and 128 + * @param PLLP parameter can be a value between 1 and 128 * @retval None */ __STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) @@ -3460,6 +3914,7 @@ __STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM RCC_PLL1DIVR_PLL1N_Pos) | ((PLLP - 1UL) << \ RCC_PLL1DIVR_PLL1P_Pos)); } +#define LL_RCC_PLL_ConfigDomain_SAI LL_RCC_PLL1_ConfigDomain_SAI /*!< alias for compatibility with legacy code */ /** * @brief Configure PLL1 used for 48Mhz domain clock @@ -3487,6 +3942,7 @@ __STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM RCC_PLL1DIVR_PLL1N_Pos) | ((PLLQ - 1UL) << \ RCC_PLL1DIVR_PLL1Q_Pos)); } +#define LL_RCC_PLL_ConfigDomain_48M LL_RCC_PLL1_ConfigDomain_48M /*!< alias for compatibility with legacy code */ /** * @brief Configure PLL clock source @@ -3502,6 +3958,7 @@ __STATIC_INLINE void LL_RCC_PLL1_SetMainSource(uint32_t PLL1Source) { MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, PLL1Source); } +#define LL_RCC_PLL_SetMainSource LL_RCC_PLL1_SetMainSource /*!< alias for compatibility with legacy code */ /** * @brief Get the oscillator used as PLL1 clock source. @@ -3516,6 +3973,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL1_GetMainSource(void) { return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC)); } +#define LL_RCC_PLL_GetMainSource LL_RCC_PLL1_GetMainSource /*!< alias for compatibility with legacy code */ /** * @brief Set Main PLL1 multiplication factor for VCO @@ -3526,6 +3984,7 @@ __STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t PLL1N) { MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N, (PLL1N - 1UL) << RCC_PLL1DIVR_PLL1N_Pos); } +#define LL_RCC_PLL_SetN LL_RCC_PLL1_SetN /*!< alias for compatibility with legacy code */ /** * @brief Get Main PLL1 multiplication factor for VCO @@ -3536,30 +3995,31 @@ __STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void) { return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1UL); } - +#define LL_RCC_PLL_GetN LL_RCC_PLL1_GetN /*!< alias for compatibility with legacy code */ /** * @brief Set Main PLL1 division factor for PLL1P * @note Used for SAI1 and SAI2 clock * @rmtoll PLL1CFGR PLL1P LL_RCC_PLL1_SetP - * @param PLL1P parameter can be a value between 2 and 128 + * @param PLL1P parameter can be a value between 1 and 128 */ __STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t PLL1P) { MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P, (PLL1P - 1UL) << RCC_PLL1DIVR_PLL1P_Pos); } +#define LL_RCC_PLL_SetP LL_RCC_PLL1_SetP /*!< alias for compatibility with legacy code */ /** * @brief Get Main PLL1 division factor for PLL1P * @note Used for SAI1 and SAI2 clock * @rmtoll PLL1CFGR PLL1P LL_RCC_PLL1_GetP - * @retval Between 2 and 128 + * @retval Between 1 and 128 */ __STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void) { return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1UL); } - +#define LL_RCC_PLL_GetP LL_RCC_PLL1_GetP /*!< alias for compatibility with legacy code */ /** * @brief Set Main PLL division factor for PLLQ @@ -3571,6 +4031,7 @@ __STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t PLL1Q) { MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q, (PLL1Q - 1UL) << RCC_PLL1DIVR_PLL1Q_Pos); } +#define LL_RCC_PLL_SetQ LL_RCC_PLL1_SetQ /*!< alias for compatibility with legacy code */ /** * @brief Get Main PLL division factor for PLLQ @@ -3582,17 +4043,19 @@ __STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void) { return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1UL); } +#define LL_RCC_PLL_GetQ LL_RCC_PLL1_GetQ /*!< alias for compatibility with legacy code */ /** * @brief Set Main PLL division factor for PLL1R * @note Used for PLL1CLK selected for USB, SDMMC (48 MHz clock) * @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_SetR - * @param PLL1R parameter can be a value between 1 and 128 + * @param PLL1R parameter can be a value between 1 and 128 (Only division by 1 and even division are allowed) */ __STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t PLL1R) { MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R, (PLL1R - 1UL) << RCC_PLL1DIVR_PLL1R_Pos); } +#define LL_RCC_PLL_SetR LL_RCC_PLL1_SetR /*!< alias for compatibility with legacy code */ /** * @brief Get Main PLL1 division factor for PLL1R @@ -3604,6 +4067,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void) { return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1UL); } +#define LL_RCC_PLL_GetR LL_RCC_PLL1_GetR /*!< alias for compatibility with legacy code */ /** * @brief Set Division factor for the main PLL and other PLL @@ -3614,6 +4078,7 @@ __STATIC_INLINE void LL_RCC_PLL1_SetDivider(uint32_t PLL1M) { MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, (PLL1M - 1UL) << RCC_PLL1CFGR_PLL1M_Pos); } +#define LL_RCC_PLL_SetDivider LL_RCC_PLL1_SetDivider /*!< alias for compatibility with legacy code */ /** * @brief Get Division factor for the main PLL and other PLL @@ -3624,6 +4089,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL1_GetDivider(void) { return (uint32_t)((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1UL); } +#define LL_RCC_PLL_GetDivider LL_RCC_PLL1_GetDivider /*!< alias for compatibility with legacy code */ /** * @brief Enable PLL1 output mapped on SAI domain clock @@ -3634,6 +4100,7 @@ __STATIC_INLINE void LL_RCC_PLL1_EnableDomain_SAI(void) { SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN); } +#define LL_RCC_PLL_EnableDomain_SAI LL_RCC_PLL1_EnableDomain_SAI /*!< alias for compatibility with legacy code */ /** * @brief Disable PLL1 output mapped on SAI domain clock @@ -3648,6 +4115,18 @@ __STATIC_INLINE void LL_RCC_PLL1_DisableDomain_SAI(void) { CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN); } +#define LL_RCC_PLL_DisableDomain_SAI LL_RCC_PLL1_DisableDomain_SAI /*!< alias for compatibility with legacy code */ + +/** + * @brief Check if PLL1 output mapped on SAI domain clock is enabled + * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_IsEnabledDomain_SAI + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_SAI(void) +{ + return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN) == (RCC_PLL1CFGR_PLL1PEN)) ? 1UL : 0UL); +} +#define LL_RCC_PLL_IsEnabledDomain_SAI LL_RCC_PLL1_IsEnabledDomain_SAI /*!< alias for compatibility with legacy code */ /** * @brief Enable PLL output mapped on 48MHz domain clock @@ -3672,6 +4151,18 @@ __STATIC_INLINE void LL_RCC_PLL1_DisableDomain_48M(void) { CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN); } +#define LL_RCC_PLL_DisableDomain_48M LL_RCC_PLL1_DisableDomain_48M /*!< alias for compatibility with legacy code */ + +/** + * @brief Check if PLL1 output mapped on 48M domain clock is enabled + * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_IsEnabledDomain_48M + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_48M(void) +{ + return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN) == (RCC_PLL1CFGR_PLL1QEN)) ? 1UL : 0UL); +} +#define LL_RCC_PLL_IsEnabledDomain_48M LL_RCC_PLL1_IsEnabledDomain_48M /*!< alias for compatibility with legacy code */ /** * @brief Enable PLL1 output mapped on SYSCLK domain @@ -3682,6 +4173,7 @@ __STATIC_INLINE void LL_RCC_PLL1_EnableDomain_SYS(void) { SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN); } +#define LL_RCC_PLL_EnableDomain_SYS LL_RCC_PLL1_EnableDomain_SYS /*!< alias for compatibility with legacy code */ /** * @brief Disable PLL1 output mapped on SYSCLK domain @@ -3696,6 +4188,18 @@ __STATIC_INLINE void LL_RCC_PLL1_DisableDomain_SYS(void) { CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN); } +#define LL_RCC_PLL_DisableDomain_SYS LL_RCC_PLL1_DisableDomain_SYS /*!< alias for compatibility with legacy code */ + +/** + * @brief Check if PLL1 output mapped on SYS domain clock is enabled + * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_IsEnabledDomain_SYS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_SYS(void) +{ + return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN) == (RCC_PLL1CFGR_PLL1REN)) ? 1UL : 0UL); +} +#define LL_RCC_PLL_IsEnabledDomain_SYS LL_RCC_PLL1_IsEnabledDomain_SYS /*!< alias for compatibility with legacy code */ /** * @brief Enable PLL1 FRACN @@ -3706,6 +4210,7 @@ __STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void) { SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN); } +#define LL_RCC_PLLFRACN_Enable LL_RCC_PLL1FRACN_Enable /*!< alias for compatibility with legacy code */ /** * @brief Check if PLL1 FRACN is enabled @@ -3716,6 +4221,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void) { return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) == RCC_PLL1CFGR_PLL1FRACEN) ? 1UL : 0UL); } +#define LL_RCC_PLLFRACN_IsEnabled LL_RCC_PLL1FRACN_IsEnabled /*!< alias for compatibility with legacy code */ /** * @brief Disable PLL1 FRACN @@ -3726,6 +4232,7 @@ __STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void) { CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN); } +#define LL_RCC_PLLFRACN_Disable LL_RCC_PLL1FRACN_Disable /*!< alias for compatibility with legacy code */ /** * @brief Set PLL1 FRACN Coefficient @@ -3736,6 +4243,7 @@ __STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN) { MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN, FRACN << RCC_PLL1FRACR_PLL1FRACN_Pos); } +#define LL_RCC_PLL_SetFRACN LL_RCC_PLL1_SetFRACN /*!< alias for compatibility with legacy code */ /** * @brief Get PLL1 FRACN Coefficient @@ -3746,6 +4254,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void) { return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN) >> RCC_PLL1FRACR_PLL1FRACN_Pos); } +#define LL_RCC_PLL_GetFRACN LL_RCC_PLL1_GetFRACN /*!< alias for compatibility with legacy code */ /** * @brief Set PLL1 VCO Input Range @@ -3758,8 +4267,9 @@ __STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void) */ __STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange) { - MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, InputRange << RCC_PLL1CFGR_PLL1RGE_Pos); + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, InputRange); } +#define LL_RCC_PLL_SetVCOInputRange LL_RCC_PLL1_SetVCOInputRange /*!< alias for compatibility with legacy code */ /** * @brief Set PLL1 EPOD Prescaler booster input clock @@ -3879,7 +4389,7 @@ __STATIC_INLINE void LL_RCC_PLL2_ConfigDomain_48M(uint32_t Source, uint32_t PLLM * @arg @ref LL_RCC_PLL2SOURCE_HSE * @param PLLM parameter can be a value between 1 and 16 * @param PLLN parameter can be a value between 4 and 512 - * @param PLLP parameter can be a value between 2 and 128 + * @param PLLP parameter can be a value between 1 and 128 * @retval None */ __STATIC_INLINE void LL_RCC_PLL2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) @@ -3972,7 +4482,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void) * @brief Set Main PLL2 division factor for PLL2P * @note Used for SAI1 and SAI2 clock * @rmtoll PLL2CFGR PLL2P LL_RCC_PLL2_SetP - * @param PLL2P parameter can be a value between 2 and 128 + * @param PLL2P parameter can be a value between 1 and 128 */ __STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t PLL2P) { @@ -3983,7 +4493,7 @@ __STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t PLL2P) * @brief Get Main PLL2 division factor for PLL2P * @note Used for SAI1 and SAI2 clock * @rmtoll PLL2CFGR PLL2P LL_RCC_PLL2_GetP - * @retval Between 2 and 128 + * @retval Between 1 and 128 */ __STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void) { @@ -4077,6 +4587,16 @@ __STATIC_INLINE void LL_RCC_PLL2_DisableDomain_SAI(void) CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN); } +/** + * @brief Check if PLL2 output mapped on SAI domain clock is enabled + * @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2_IsEnabledDomain_SAI + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledDomain_SAI(void) +{ + return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN) == (RCC_PLL2CFGR_PLL2PEN)) ? 1UL : 0UL); +} + /** * @brief Enable PLL2 output mapped on 48MHz domain clock * @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2_EnableDomain_48M @@ -4089,7 +4609,7 @@ __STATIC_INLINE void LL_RCC_PLL2_EnableDomain_48M(void) /** * @brief Disable PLL2 output mapped on 48MHz domain clock - * @note In order to save power, when of the PLLSAI1 is + * @note In order to save power, when of the PLL2 48M is * not used, should be 0 * @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2_DisableDomain_48M * @retval None @@ -4099,6 +4619,16 @@ __STATIC_INLINE void LL_RCC_PLL2_DisableDomain_48M(void) CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN); } +/** + * @brief Check if PLL2 output mapped on 48M domain clock is enabled + * @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2_IsEnabledDomain_48M + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledDomain_48M(void) +{ + return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN) == (RCC_PLL2CFGR_PLL2QEN)) ? 1UL : 0UL); +} + /** * @brief Enable PLL2 output mapped on ADC domain clock * @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2_EnableDomain_ADC @@ -4111,8 +4641,8 @@ __STATIC_INLINE void LL_RCC_PLL2_EnableDomain_ADC(void) /** * @brief Disable PLL2 output mapped on ADC domain clock - * @note In order to save power, when of the PLLSAI1 is - * not used, Main PLLSAI1 should be 0 + * @note In order to save power, when of the PLL2 ADC is + * not used, Main PLL2ADC should be 0 * @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2_DisableDomain_ADC * @retval None */ @@ -4121,6 +4651,16 @@ __STATIC_INLINE void LL_RCC_PLL2_DisableDomain_ADC(void) CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN); } +/** + * @brief Check if PLL2 output mapped on ADC domain clock is enabled + * @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2_IsEnabledDomain_ADC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledDomain_ADC(void) +{ + return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN) == (RCC_PLL2CFGR_PLL2REN)) ? 1UL : 0UL); +} + /** * @brief Enable PLL2 FRACN * @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable @@ -4182,7 +4722,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void) */ __STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange) { - MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2RGE, InputRange << RCC_PLL2CFGR_PLL2RGE_Pos); + MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2RGE, InputRange); } /** @@ -4238,7 +4778,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void) * @arg @ref LL_RCC_PLL3SOURCE_HSE * @param PLLM parameter can be a value between 1 and 16 * @param PLLN parameter can be a value between 4 and 512 - * @param PLLP parameter can be a value between 2 and 128 + * @param PLLP parameter can be a value between 1 and 128 * @retval None */ __STATIC_INLINE void LL_RCC_PLL3_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) @@ -4279,6 +4819,37 @@ __STATIC_INLINE void LL_RCC_PLL3_ConfigDomain_48M(uint32_t Source, uint32_t PLLM } +#if defined(LTDC) || defined(HSPI1) + +/** + * @brief Configure PLL3 used for HSPI_LTDC domain clock + * @note PLL3 Source, PLLM, PLLN and PLLR can be written only when PLL3 is disabled. + * @note This can be selected for HSPI and LTDC + * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_ConfigDomain_HSPI_LTDC\n + * PLL3CFGR PLL3M LL_RCC_PLL3_ConfigDomain_HSPI_LTDC\n + * PLL3CFGR PLL3N LL_RCC_PLL3_ConfigDomain_HSPI_LTDC\n + * PLL3CFGR PLL3R LL_RCC_PLL3_ConfigDomain_HSPI_LTDC + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL3SOURCE_NONE + * @arg @ref LL_RCC_PLL3SOURCE_MSIS + * @arg @ref LL_RCC_PLL3SOURCE_HSI + * @arg @ref LL_RCC_PLL3SOURCE_HSE + * @param PLLM parameter can be a value between 1 and 16 + * @param PLLN parameter can be a value between 4 and 512 + * @param PLLR parameter can be a value between 1 and 128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_ConfigDomain_HSPI_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC | RCC_PLL3CFGR_PLL3M, Source | \ + ((PLLM - 1UL) << RCC_PLL3CFGR_PLL3M_Pos)); + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N | RCC_PLL3DIVR_PLL3R, ((PLLN - 1UL) << \ + RCC_PLL3DIVR_PLL3N_Pos) | ((PLLR - 1UL) << \ + RCC_PLL3DIVR_PLL3R_Pos)); +} + +#endif /* LTDC || HSPI1 */ + /** * @brief Configure PLL3 clock source * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_SetSource @@ -4333,7 +4904,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void) * @brief Set Main PLL3 division factor for PLL3P * @note Used for SAI1 and SAI2 clock * @rmtoll PLL3CFGR PLL3P LL_RCC_PLL3_SetP - * @param PLL3P parameter can be a value between 2 and 128 + * @param PLL3P parameter can be a value between 1 and 128 */ __STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t PLL3P) { @@ -4344,7 +4915,7 @@ __STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t PLL3P) * @brief Get Main PLL3 division factor for PLL3P * @note Used for SAI1 and SAI2 clock * @rmtoll PLL3CFGR PLL3P LL_RCC_PLL3_GetP - * @retval Between 2 and 128 + * @retval Between 1 and 128 */ __STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void) { @@ -4438,6 +5009,16 @@ __STATIC_INLINE void LL_RCC_PLL3_DisableDomain_SAI(void) CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN); } +/** + * @brief Check if PLL3 output mapped on SAI domain clock is enabled + * @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3_IsEnabledDomain_SAI + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledDomain_SAI(void) +{ + return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN) == (RCC_PLL3CFGR_PLL3PEN)) ? 1UL : 0UL); +} + /** * @brief Enable PLL2 output mapped on 48MHz domain clock * @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3_EnableDomain_48M @@ -4460,6 +5041,53 @@ __STATIC_INLINE void LL_RCC_PLL3_DisableDomain_48M(void) CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN); } +/** + * @brief Check if PLL3 output mapped on 48M domain clock is enabled + * @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3_IsEnabledDomain_48M + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledDomain_48M(void) +{ + return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN) == (RCC_PLL3CFGR_PLL3QEN)) ? 1UL : 0UL); +} + +#if defined(LTDC) || defined(HSPI1) + +/** + * @brief Enable PLL3 output mapped on HSPI_LTDC domain clock + * @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3_EnableDomain_HSPI_LTDC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_EnableDomain_HSPI_LTDC(void) +{ + SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN); +} + +/** + * @brief Disable PLL3 output mapped on HSPI_LTDC domain clock + * @note In order to save power, when of the PLL3 is + * not used, should be 0 + * @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3_DisableDomain_HSPI_LTDC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_DisableDomain_HSPI_LTDC(void) +{ + CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN); +} + +/** + * @brief Check if PLL3 output mapped on HSPI_LTDC domain clock is enabled + * @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3_IsEnabledDomain_HSPI_LTDC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledDomain_HSPI_LTDC(void) +{ + return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN) == (RCC_PLL3CFGR_PLL3REN)) ? 1UL : 0UL); +} + +#endif /* LTDC || HSPI1 */ + + /** * @brief Enable PLL3 FRACN * @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable @@ -4521,7 +5149,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void) */ __STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange) { - MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3RGE, InputRange << RCC_PLL3CFGR_PLL3RGE_Pos); + MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3RGE, InputRange); } /** @@ -4532,8 +5160,75 @@ __STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange) * @{ */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable Secure Privileged mode + * @rmtoll PRIVCFGR SPRIV LL_RCC_EnableSecPrivilegedMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableSecPrivilegedMode(void) +{ + SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); +} + +/** + * @brief Disable Secure Privileged mode + * @rmtoll PRIVCFGR SPRIV LL_RCC_DisableSecPrivilegedMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableSecPrivilegedMode(void) +{ + CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); +} + +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Check if Secure Privileged mode has been enabled or not + * @rmtoll PRIVCFGR SPRIV LL_RCC_IsEnabledSecPrivilegedMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledSecPrivilegedMode(void) +{ + return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV) == RCC_PRIVCFGR_SPRIV) ? 1UL : 0UL); +} + +/** + * @brief Enable Non Secure Privileged mode + * @rmtoll PRIVCFGR NSPRIV LL_RCC_EnableNSecPrivilegedMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableNSecPrivilegedMode(void) +{ + SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); +} + +/** + * @brief Disable Non Secure Privileged mode + * @rmtoll PRIVCFGR NSPRIV LL_RCC_DisableNSecPrivilegedMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableNSecPrivilegedMode(void) +{ + CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); +} + +/** + * @brief Check if Non Secure Privileged mode has been enabled or not + * @rmtoll PRIVCFGR NSPRIV LL_RCC_IsEnabledNSecPrivilegedMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledNSecPrivilegedMode(void) +{ + return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV) == RCC_PRIVCFGR_NSPRIV) ? 1UL : 0UL); +} + + /** * @brief Enable privileged mode + * @note User should use LL_RCC_EnableSecPrivilegedMode() to enable Secure privilege + * User should use LL_RCC_EnableNSecPrivilegedMode() to enable Non-secure privilege + * This API is kept for legacy purpose only * @rmtoll PRIVCFGR SPRIV LL_RCC_EnablePrivilegedMode * @rmtoll PRIVCFGR NSPRIV LL_RCC_EnablePrivilegedMode * @retval None @@ -4549,6 +5244,9 @@ __STATIC_INLINE void LL_RCC_EnablePrivilegedMode(void) /** * @brief Disable Privileged mode + * @note User should use LL_RCC_DisableSecPrivilegedMode() to disable Secure privilege + * User should use LL_RCC_DisableNSecPrivilegedMode() to disable Non-secure privilege + * This API is kept for legacy purpose only * @rmtoll CR PRIV LL_RCC_DisablePrivilegedMode * @retval None */ @@ -4563,6 +5261,9 @@ __STATIC_INLINE void LL_RCC_DisablePrivilegedMode(void) /** * @brief Check if Privileged mode has been enabled or not + * @note User should use LL_RCC_IsEnabledSecPrivilegedMode() to check Secure privilege setting + * User should use LL_RCC_IsEnabledNSecPrivilegedMode() to check Non-secure privilege setting + * This API is kept for legacy purpose only * @rmtoll CR PRIV LL_RCC_IsEnabledPrivilegedMode * @retval State of bit (1 or 0). */ @@ -4808,7 +5509,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) /** * @brief Check if Clock security system interrupt occurred or not - * @rmtoll CIFR MSIKRDYF LL_RCC_IsActiveFlag_MSIKRDYF + * @rmtoll CIFR MSIKRDYF LL_RCC_IsActiveFlag_MSIKRDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIKRDY(void) @@ -4819,7 +5520,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIKRDY(void) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** * @brief Check if Clock security system interrupt occurred or not - * @rmtoll CIFR SHSIRDYF LL_RCC_IsActiveFlag_SHSIRDYF + * @rmtoll CIFR SHSIRDYF LL_RCC_IsActiveFlag_SHSIRDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHSIRDY(void) @@ -5372,6 +6073,15 @@ uint32_t LL_RCC_GetDAC1ClockFreq(uint32_t DAC1Source); uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource); uint32_t LL_RCC_GetSAESClockFreq(uint32_t SAESxSource); uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource); +#if defined(DSI) +uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); +#endif /* DSI */ +#if defined(HSPI1) +uint32_t LL_RCC_GetHSPIClockFreq(uint32_t HSPIxSource); +#endif /* HSPI1 */ +#if defined(LTDC) +uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource); +#endif /* defined(LTDC) */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rng.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rng.c index 8a2938fbd71..0a2091b53ae 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rng.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rng.c @@ -79,16 +79,26 @@ * - SUCCESS: RNG registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx) +ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx) { + ErrorStatus status = SUCCESS; + /* Check the parameters */ assert_param(IS_RNG_ALL_INSTANCE(RNGx)); - /* Enable RNG reset state */ - LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG); - - /* Release RNG from reset state */ - LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG); - return (SUCCESS); + if (RNGx == RNG) + { + /* Enable RNG reset state */ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG); + + /* Release RNG from reset state */ + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG); + } + else + { + status = ERROR; + } + + return status; } /** diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rng.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rng.h index 0812b0bab98..8bce535b0d8 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rng.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rng.h @@ -38,6 +38,7 @@ extern "C" { */ /* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ @@ -216,7 +217,7 @@ __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL); } @@ -249,7 +250,7 @@ __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL); } @@ -282,7 +283,7 @@ __STATIC_INLINE void LL_RNG_DisableCondReset(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL); } @@ -304,7 +305,7 @@ __STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL); } @@ -337,7 +338,7 @@ __STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL); } @@ -360,7 +361,7 @@ __STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1) * @param RNGx RNG Instance * @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F */ -__STATIC_INLINE uint32_t LL_RNG_GetConfig1(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_GetConfig1(const RNG_TypeDef *RNGx) { return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos); } @@ -383,7 +384,7 @@ __STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2) * @param RNGx RNG Instance * @retval Returned Value expressed on 3 bits : Value between 0 and 0x7 */ -__STATIC_INLINE uint32_t LL_RNG_GetConfig2(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_GetConfig2(const RNG_TypeDef *RNGx) { return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos); } @@ -406,7 +407,7 @@ __STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3) * @param RNGx RNG Instance * @retval Returned Value expressed on 4 bits : Value between 0 and 0xF */ -__STATIC_INLINE uint32_t LL_RNG_GetConfig3(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_GetConfig3(const RNG_TypeDef *RNGx) { return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos); } @@ -461,7 +462,7 @@ __STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider) * @arg @ref LL_RNG_CLKDIV_BY_16384 * @arg @ref LL_RNG_CLKDIV_BY_32768 */ -__STATIC_INLINE uint32_t LL_RNG_GetClockDivider(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_GetClockDivider(const RNG_TypeDef *RNGx) { return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV); } @@ -479,7 +480,7 @@ __STATIC_INLINE uint32_t LL_RNG_GetClockDivider(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL); } @@ -490,7 +491,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL); } @@ -501,7 +502,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL); } @@ -512,7 +513,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL); } @@ -523,7 +524,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL); } @@ -589,7 +590,7 @@ __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL); } @@ -608,7 +609,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval Generated 32-bit random value */ -__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx) { return (uint32_t)(READ_REG(RNGx->DR)); } @@ -645,7 +646,7 @@ __STATIC_INLINE void LL_RNG_DisableArdis(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabledArdis(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabledArdis(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_ARDIS) != (RNG_CR_ARDIS)) ? 1UL : 0UL); } @@ -672,7 +673,7 @@ __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG) * @param RNGx RNG Instance * @retval Return 32-bit RNG Health Test configuration */ -__STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(const RNG_TypeDef *RNGx) { return (uint32_t)READ_REG(RNGx->HTCR); } @@ -686,7 +687,7 @@ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx) */ ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct); void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); -ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx); +ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); /** * @} @@ -712,3 +713,4 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx); #endif #endif /* __STM32U5xx_LL_RNG_H */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rtc.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rtc.c index 86112bb45fb..65aa6751c53 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rtc.c @@ -158,17 +158,17 @@ ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) /* Set Initialization mode */ if (LL_RTC_EnterInitMode(RTCx) != ERROR) { - WRITE_REG(RTCx->TR, 0x00000000U); + WRITE_REG(RTCx->TR, 0U); WRITE_REG(RTCx->DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); - WRITE_REG(RTCx->CR, 0x00000000U); + WRITE_REG(RTCx->CR, 0U); WRITE_REG(RTCx->WUTR, RTC_WUTR_WUT); WRITE_REG(RTCx->PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT)); - WRITE_REG(RTCx->ALRMAR, 0x00000000U); - WRITE_REG(RTCx->ALRMBR, 0x00000000U); - WRITE_REG(RTCx->SHIFTR, 0x00000000U); - WRITE_REG(RTCx->CALR, 0x00000000U); - WRITE_REG(RTCx->ALRMASSR, 0x00000000U); - WRITE_REG(RTCx->ALRMBSSR, 0x00000000U); + WRITE_REG(RTCx->ALRMAR, 0U); + WRITE_REG(RTCx->ALRMBR, 0U); + WRITE_REG(RTCx->SHIFTR, 0U); + WRITE_REG(RTCx->CALR, 0U); + WRITE_REG(RTCx->ALRMASSR, 0U); + WRITE_REG(RTCx->ALRMBSSR, 0U); /* Exit Initialization mode */ LL_RTC_DisableInitMode(RTCx); @@ -182,21 +182,21 @@ ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) /* DeInitialization of the TAMP */ /* Reset TAMP CR1 and CR2 registers */ - WRITE_REG(TAMP->CR1, 0x00000000U); - WRITE_REG(TAMP->CR2, 0x00000000U); + WRITE_REG(TAMP->CR1, 0U); + WRITE_REG(TAMP->CR2, 0U); #if defined (RTC_OTHER_SUPPORT) - WRITE_REG(TAMP->CR3, 0x00000000U); - WRITE_REG(TAMP->SECCFGR, 0x00000000U); - WRITE_REG(TAMP->PRIVCFGR, 0x00000000U); + WRITE_REG(TAMP->CR3, 0U); + WRITE_REG(TAMP->SECCFGR, 0U); + WRITE_REG(TAMP->PRIVCFGR, 0U); #endif /* RTC_OTHER_SUPPORT */ - WRITE_REG(TAMP->FLTCR, 0x00000000U); + WRITE_REG(TAMP->FLTCR, 0U); #if defined (RTC_ACTIVE_TAMPER_SUPPORT) WRITE_REG(TAMP->ATCR1, 0x00070000U); - WRITE_REG(TAMP->ATCR2, 0x00000000U); + WRITE_REG(TAMP->ATCR2, 0U); #endif /* RTC_ACTIVE_TAMPER_SUPPORT */ - WRITE_REG(TAMP->IER, 0x00000000U); + WRITE_REG(TAMP->IER, 0U); WRITE_REG(TAMP->SCR, 0xFFFFFFFFU); - WRITE_REG(TAMP->ERCFGR, 0x00000000U); + WRITE_REG(TAMP->ERCFGR, 0U); return status; } @@ -304,7 +304,7 @@ ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_Time } else { - RTC_TimeStruct->TimeFormat = 0x00U; + RTC_TimeStruct->TimeFormat = 0U; assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours))); } assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes))); @@ -398,8 +398,8 @@ ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_Date assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day))); } - assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month)); - assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay)); + assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month)); + assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay)); /* Disable the write protection for RTC registers */ LL_RTC_DisableWriteProtection(RTCx); diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rtc.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rtc.h index 32c93961727..ff0d6165ab7 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_rtc.h @@ -214,8 +214,8 @@ typedef struct /** @defgroup RTC_LL_EC_FORMAT FORMAT * @{ */ -#define LL_RTC_FORMAT_BIN 0x00000000U /*!< Binary data format */ -#define LL_RTC_FORMAT_BCD 0x00000001U /*!< BCD data format */ +#define LL_RTC_FORMAT_BIN 0U /*!< Binary data format */ +#define LL_RTC_FORMAT_BCD 1U /*!< BCD data format */ /** * @} */ @@ -223,8 +223,8 @@ typedef struct /** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay * @{ */ -#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm A Date is selected */ -#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /*!< Alarm A WeekDay is selected */ +#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0U /*!< Alarm A Date is selected */ +#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /*!< Alarm A WeekDay is selected */ /** * @} */ @@ -232,8 +232,8 @@ typedef struct /** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay * @{ */ -#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm B Date is selected */ -#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL /*!< Alarm B WeekDay is selected */ +#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0U /*!< Alarm B Date is selected */ +#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL /*!< Alarm B WeekDay is selected */ /** * @} */ @@ -315,7 +315,7 @@ typedef struct /** @defgroup RTC_LL_EC_HOURFORMAT HOUR FORMAT * @{ */ -#define LL_RTC_HOURFORMAT_24HOUR 0x00000000U /*!< 24 hour/day format */ +#define LL_RTC_HOURFORMAT_24HOUR 0U /*!< 24 hour/day format */ #define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT /*!< AM/PM hour format */ /** * @} @@ -324,7 +324,7 @@ typedef struct /** @defgroup RTC_LL_EC_ALARMOUT ALARM OUTPUT * @{ */ -#define LL_RTC_ALARMOUT_DISABLE 0x00000000U /*!< Output disabled */ +#define LL_RTC_ALARMOUT_DISABLE 0U /*!< Output disabled */ #define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0 /*!< Alarm A output enabled */ #define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1 /*!< Alarm B output enabled */ #define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL /*!< Wakeup output enabled */ @@ -335,7 +335,7 @@ typedef struct /** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE * @{ */ -#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U /*!< RTC_ALARM is open-drain output */ +#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0U /*!< RTC_ALARM is open-drain output */ #define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is push-pull output */ /** * @} @@ -344,7 +344,7 @@ typedef struct /** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN * @{ */ -#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/ +#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/ #define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */ /** * @} @@ -353,7 +353,7 @@ typedef struct /** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT * @{ */ -#define LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_TIME_FORMAT_AM_OR_24 0U /*!< AM or 24-hour format */ #define LL_RTC_TIME_FORMAT_PM RTC_TR_PM /*!< PM */ /** * @} @@ -362,7 +362,7 @@ typedef struct /** @defgroup RTC_LL_EC_SHIFT_SECOND SHIFT SECOND * @{ */ -#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */ +#define LL_RTC_SHIFT_SECOND_DELAY 0U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */ #define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */ /** * @} @@ -371,7 +371,7 @@ typedef struct /** @defgroup RTC_LL_EC_ALMA_MASK ALARMA MASK * @{ */ -#define LL_RTC_ALMA_MASK_NONE 0x00000000U /*!< No masks applied on Alarm A*/ +#define LL_RTC_ALMA_MASK_NONE 0U /*!< No masks applied on Alarm A*/ #define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4 /*!< Date/day do not care in Alarm A comparison */ #define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3 /*!< Hours do not care in Alarm A comparison */ #define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2 /*!< Minutes do not care in Alarm A comparison */ @@ -384,7 +384,7 @@ typedef struct /** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT ALARMA TIME FORMAT * @{ */ -#define LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_ALMA_TIME_FORMAT_AM 0U /*!< AM or 24-hour format */ #define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM /*!< PM */ /** * @} @@ -402,7 +402,7 @@ typedef struct /** @defgroup RTC_LL_EC_ALMB_MASK ALARMB MASK * @{ */ -#define LL_RTC_ALMB_MASK_NONE 0x00000000U /*!< No masks applied on Alarm B*/ +#define LL_RTC_ALMB_MASK_NONE 0U /*!< No masks applied on Alarm B*/ #define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4 /*!< Date/day do not care in Alarm B comparison */ #define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours do not care in Alarm B comparison */ #define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes do not care in Alarm B comparison */ @@ -415,7 +415,7 @@ typedef struct /** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT ALARMB TIME FORMAT * @{ */ -#define LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_ALMB_TIME_FORMAT_AM 0U /*!< AM or 24-hour format */ #define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM /*!< PM */ /** * @} @@ -432,7 +432,7 @@ typedef struct /** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE * @{ */ -#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */ +#define LL_RTC_TIMESTAMP_EDGE_RISING 0U /*!< RTC_TS input rising edge generates a time-stamp event */ #define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */ /** * @} @@ -441,7 +441,7 @@ typedef struct /** @defgroup RTC_LL_EC_TS_TIME_FORMAT TIMESTAMP TIME FORMAT * @{ */ -#define LL_RTC_TS_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_TS_TIME_FORMAT_AM 0U /*!< AM or 24-hour format */ #define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM /*!< PM */ /** * @} @@ -490,7 +490,7 @@ typedef struct /** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION * @{ */ -#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ +#define LL_RTC_TAMPER_DURATION_1RTCCLK 0U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ #define LL_RTC_TAMPER_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ #define LL_RTC_TAMPER_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ #define LL_RTC_TAMPER_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ @@ -501,7 +501,7 @@ typedef struct /** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER * @{ */ -#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ +#define LL_RTC_TAMPER_FILTER_DISABLE 0U /*!< Tamper filter is disabled */ #define LL_RTC_TAMPER_FILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */ #define LL_RTC_TAMPER_FILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */ #define LL_RTC_TAMPER_FILTER_8SAMPLE TAMP_FLTCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level. */ @@ -512,14 +512,14 @@ typedef struct /** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER * @{ */ -#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ #define LL_RTC_TAMPER_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ -#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ -#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ -#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */ -#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */ -#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */ -#define LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ /** * @} */ @@ -550,7 +550,7 @@ typedef struct #define LL_RTC_TAMPER_ITAMP6 TAMP_CR1_ITAMP6E /*!< Internal tamper 6: JTAG/SWD access when RDP > 0 */ #define LL_RTC_TAMPER_ITAMP7 TAMP_CR1_ITAMP7E /*!< Internal tamper 7: ADC4 analog watchdog monitoring 1 */ #define LL_RTC_TAMPER_ITAMP8 TAMP_CR1_ITAMP8E /*!< Internal tamper 8: Monotonic counter overflow */ -#define LL_RTC_TAMPER_ITAMP9 TAMP_CR1_ITAMP9E /*!< Internal tamper 9: Cryptograpic IPs fault*/ +#define LL_RTC_TAMPER_ITAMP9 TAMP_CR1_ITAMP9E /*!< Internal tamper 9: Cryptographic IPs fault*/ #define LL_RTC_TAMPER_ITAMP11 TAMP_CR1_ITAMP11E /*!< Internal tamper 11: IWDG reset when tamper flag is set */ #define LL_RTC_TAMPER_ITAMP12 TAMP_CR1_ITAMP12E /*!< Internal tamper 12: ADC4 analog watchdog monitoring 2*/ #define LL_RTC_TAMPER_ITAMP13 TAMP_CR1_ITAMP13E /*!< Internal tamper 13: ADC4 analog watchdog monitoring 3 */ @@ -577,14 +577,16 @@ typedef struct /** @defgroup RTC_LL_EC_ACTIVE_ASYNC_PRESCALER ACTIVE TAMPER ASYNCHRONOUS PRESCALER CLOCK * @{ */ -#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK 0u /*!< RTCCLK */ -#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0 /*!< RTCCLK/2 */ -#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1 /*!< RTCCLK/4 */ -#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/8 */ -#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2 /*!< RTCCLK/16 */ -#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/32 */ -#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1) /*!< RTCCLK/64 */ -#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/128 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK 0U /*!< RTCCLK */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0 /*!< RTCCLK/2 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1 /*!< RTCCLK/4 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/8 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2 /*!< RTCCLK/16 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/32 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1) /*!< RTCCLK/64 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/128 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2048 (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/2048 */ + /** * @} */ @@ -593,77 +595,77 @@ typedef struct /** @defgroup RTC_LL_EC_ACTIVE_OUTPUT_SELECTION ACTIVE TAMPER OUTPUT SELECTION * @{ */ -#define LL_RTC_TAMPER_ATAMP1IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL1_Pos) -#define LL_RTC_TAMPER_ATAMP1IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL1_Pos) -#define LL_RTC_TAMPER_ATAMP1IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL1_Pos) -#define LL_RTC_TAMPER_ATAMP1IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL1_Pos) -#define LL_RTC_TAMPER_ATAMP1IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL1_Pos) -#define LL_RTC_TAMPER_ATAMP1IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL1_Pos) -#define LL_RTC_TAMPER_ATAMP1IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL1_Pos) -#define LL_RTC_TAMPER_ATAMP1IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL1_Pos) - -#define LL_RTC_TAMPER_ATAMP2IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL2_Pos) -#define LL_RTC_TAMPER_ATAMP2IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL2_Pos) -#define LL_RTC_TAMPER_ATAMP2IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL2_Pos) -#define LL_RTC_TAMPER_ATAMP2IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL2_Pos) -#define LL_RTC_TAMPER_ATAMP2IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL2_Pos) -#define LL_RTC_TAMPER_ATAMP2IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL2_Pos) -#define LL_RTC_TAMPER_ATAMP2IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL2_Pos) -#define LL_RTC_TAMPER_ATAMP2IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL2_Pos) - -#define LL_RTC_TAMPER_ATAMP3IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL3_Pos) -#define LL_RTC_TAMPER_ATAMP3IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL3_Pos) -#define LL_RTC_TAMPER_ATAMP3IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL3_Pos) -#define LL_RTC_TAMPER_ATAMP3IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL3_Pos) -#define LL_RTC_TAMPER_ATAMP3IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL3_Pos) -#define LL_RTC_TAMPER_ATAMP3IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL3_Pos) -#define LL_RTC_TAMPER_ATAMP3IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL3_Pos) -#define LL_RTC_TAMPER_ATAMP3IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL3_Pos) - -#define LL_RTC_TAMPER_ATAMP4IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL4_Pos) -#define LL_RTC_TAMPER_ATAMP4IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL4_Pos) -#define LL_RTC_TAMPER_ATAMP4IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL4_Pos) -#define LL_RTC_TAMPER_ATAMP4IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL4_Pos) -#define LL_RTC_TAMPER_ATAMP4IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL4_Pos) -#define LL_RTC_TAMPER_ATAMP4IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL4_Pos) -#define LL_RTC_TAMPER_ATAMP4IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL4_Pos) -#define LL_RTC_TAMPER_ATAMP4IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL4_Pos) - -#define LL_RTC_TAMPER_ATAMP5IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL5_Pos) -#define LL_RTC_TAMPER_ATAMP5IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL5_Pos) -#define LL_RTC_TAMPER_ATAMP5IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL5_Pos) -#define LL_RTC_TAMPER_ATAMP5IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL5_Pos) -#define LL_RTC_TAMPER_ATAMP5IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL5_Pos) -#define LL_RTC_TAMPER_ATAMP5IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL5_Pos) -#define LL_RTC_TAMPER_ATAMP5IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL5_Pos) -#define LL_RTC_TAMPER_ATAMP5IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL5_Pos) - -#define LL_RTC_TAMPER_ATAMP6IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL6_Pos) -#define LL_RTC_TAMPER_ATAMP6IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL6_Pos) -#define LL_RTC_TAMPER_ATAMP6IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL6_Pos) -#define LL_RTC_TAMPER_ATAMP6IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL6_Pos) -#define LL_RTC_TAMPER_ATAMP6IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL6_Pos) -#define LL_RTC_TAMPER_ATAMP6IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL6_Pos) -#define LL_RTC_TAMPER_ATAMP6IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL6_Pos) -#define LL_RTC_TAMPER_ATAMP6IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL6_Pos) - -#define LL_RTC_TAMPER_ATAMP7IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL7_Pos) -#define LL_RTC_TAMPER_ATAMP7IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL7_Pos) -#define LL_RTC_TAMPER_ATAMP7IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL7_Pos) -#define LL_RTC_TAMPER_ATAMP7IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL7_Pos) -#define LL_RTC_TAMPER_ATAMP7IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL7_Pos) -#define LL_RTC_TAMPER_ATAMP7IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL7_Pos) -#define LL_RTC_TAMPER_ATAMP7IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL7_Pos) -#define LL_RTC_TAMPER_ATAMP7IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL7_Pos) - -#define LL_RTC_TAMPER_ATAMP8IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL8_Pos) -#define LL_RTC_TAMPER_ATAMP8IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL8_Pos) -#define LL_RTC_TAMPER_ATAMP8IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL8_Pos) -#define LL_RTC_TAMPER_ATAMP8IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL8_Pos) -#define LL_RTC_TAMPER_ATAMP8IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL8_Pos) -#define LL_RTC_TAMPER_ATAMP8IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL8_Pos) -#define LL_RTC_TAMPER_ATAMP8IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL8_Pos) -#define LL_RTC_TAMPER_ATAMP8IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL8_Pos) +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP1OUT (0U << TAMP_ATCR2_ATOSEL1_Pos) +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP2OUT (1U << TAMP_ATCR2_ATOSEL1_Pos) +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL1_Pos) +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP4OUT (3U << TAMP_ATCR2_ATOSEL1_Pos) +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP5OUT (4U << TAMP_ATCR2_ATOSEL1_Pos) +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP6OUT (5U << TAMP_ATCR2_ATOSEL1_Pos) +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP7OUT (6U << TAMP_ATCR2_ATOSEL1_Pos) +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP8OUT (7U << TAMP_ATCR2_ATOSEL1_Pos) + +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP1OUT (0U << TAMP_ATCR2_ATOSEL2_Pos) +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP2OUT (1U << TAMP_ATCR2_ATOSEL2_Pos) +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL2_Pos) +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP4OUT (3U << TAMP_ATCR2_ATOSEL2_Pos) +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP5OUT (4U << TAMP_ATCR2_ATOSEL2_Pos) +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP6OUT (5U << TAMP_ATCR2_ATOSEL2_Pos) +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP7OUT (6U << TAMP_ATCR2_ATOSEL2_Pos) +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP8OUT (7U << TAMP_ATCR2_ATOSEL2_Pos) + +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP1OUT (0U << TAMP_ATCR2_ATOSEL3_Pos) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP2OUT (1U << TAMP_ATCR2_ATOSEL3_Pos) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL3_Pos) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP4OUT (3U << TAMP_ATCR2_ATOSEL3_Pos) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP5OUT (4U << TAMP_ATCR2_ATOSEL3_Pos) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP6OUT (5U << TAMP_ATCR2_ATOSEL3_Pos) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP7OUT (6U << TAMP_ATCR2_ATOSEL3_Pos) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP8OUT (7U << TAMP_ATCR2_ATOSEL3_Pos) + +#define LL_RTC_TAMPER_ATAMP4IN_ATAMP1OUT (0U << TAMP_ATCR2_ATOSEL4_Pos) +#define LL_RTC_TAMPER_ATAMP4IN_ATAMP2OUT (1U << TAMP_ATCR2_ATOSEL4_Pos) +#define LL_RTC_TAMPER_ATAMP4IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL4_Pos) +#define LL_RTC_TAMPER_ATAMP4IN_ATAMP4OUT (3U << TAMP_ATCR2_ATOSEL4_Pos) +#define LL_RTC_TAMPER_ATAMP4IN_ATAMP5OUT (4U << TAMP_ATCR2_ATOSEL4_Pos) +#define LL_RTC_TAMPER_ATAMP4IN_ATAMP6OUT (5U << TAMP_ATCR2_ATOSEL4_Pos) +#define LL_RTC_TAMPER_ATAMP4IN_ATAMP7OUT (6U << TAMP_ATCR2_ATOSEL4_Pos) +#define LL_RTC_TAMPER_ATAMP4IN_ATAMP8OUT (7U << TAMP_ATCR2_ATOSEL4_Pos) + +#define LL_RTC_TAMPER_ATAMP5IN_ATAMP1OUT (0U << TAMP_ATCR2_ATOSEL5_Pos) +#define LL_RTC_TAMPER_ATAMP5IN_ATAMP2OUT (1U << TAMP_ATCR2_ATOSEL5_Pos) +#define LL_RTC_TAMPER_ATAMP5IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL5_Pos) +#define LL_RTC_TAMPER_ATAMP5IN_ATAMP4OUT (3U << TAMP_ATCR2_ATOSEL5_Pos) +#define LL_RTC_TAMPER_ATAMP5IN_ATAMP5OUT (4U << TAMP_ATCR2_ATOSEL5_Pos) +#define LL_RTC_TAMPER_ATAMP5IN_ATAMP6OUT (5U << TAMP_ATCR2_ATOSEL5_Pos) +#define LL_RTC_TAMPER_ATAMP5IN_ATAMP7OUT (6U << TAMP_ATCR2_ATOSEL5_Pos) +#define LL_RTC_TAMPER_ATAMP5IN_ATAMP8OUT (7U << TAMP_ATCR2_ATOSEL5_Pos) + +#define LL_RTC_TAMPER_ATAMP6IN_ATAMP1OUT (0U << TAMP_ATCR2_ATOSEL6_Pos) +#define LL_RTC_TAMPER_ATAMP6IN_ATAMP2OUT (1U << TAMP_ATCR2_ATOSEL6_Pos) +#define LL_RTC_TAMPER_ATAMP6IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL6_Pos) +#define LL_RTC_TAMPER_ATAMP6IN_ATAMP4OUT (3U << TAMP_ATCR2_ATOSEL6_Pos) +#define LL_RTC_TAMPER_ATAMP6IN_ATAMP5OUT (4U << TAMP_ATCR2_ATOSEL6_Pos) +#define LL_RTC_TAMPER_ATAMP6IN_ATAMP6OUT (5U << TAMP_ATCR2_ATOSEL6_Pos) +#define LL_RTC_TAMPER_ATAMP6IN_ATAMP7OUT (6U << TAMP_ATCR2_ATOSEL6_Pos) +#define LL_RTC_TAMPER_ATAMP6IN_ATAMP8OUT (7U << TAMP_ATCR2_ATOSEL6_Pos) + +#define LL_RTC_TAMPER_ATAMP7IN_ATAMP1OUT (0U << TAMP_ATCR2_ATOSEL7_Pos) +#define LL_RTC_TAMPER_ATAMP7IN_ATAMP2OUT (1U << TAMP_ATCR2_ATOSEL7_Pos) +#define LL_RTC_TAMPER_ATAMP7IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL7_Pos) +#define LL_RTC_TAMPER_ATAMP7IN_ATAMP4OUT (3U << TAMP_ATCR2_ATOSEL7_Pos) +#define LL_RTC_TAMPER_ATAMP7IN_ATAMP5OUT (4U << TAMP_ATCR2_ATOSEL7_Pos) +#define LL_RTC_TAMPER_ATAMP7IN_ATAMP6OUT (5U << TAMP_ATCR2_ATOSEL7_Pos) +#define LL_RTC_TAMPER_ATAMP7IN_ATAMP7OUT (6U << TAMP_ATCR2_ATOSEL7_Pos) +#define LL_RTC_TAMPER_ATAMP7IN_ATAMP8OUT (7U << TAMP_ATCR2_ATOSEL7_Pos) + +#define LL_RTC_TAMPER_ATAMP8IN_ATAMP1OUT (0U << TAMP_ATCR2_ATOSEL8_Pos) +#define LL_RTC_TAMPER_ATAMP8IN_ATAMP2OUT (1U << TAMP_ATCR2_ATOSEL8_Pos) +#define LL_RTC_TAMPER_ATAMP8IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL8_Pos) +#define LL_RTC_TAMPER_ATAMP8IN_ATAMP4OUT (3U << TAMP_ATCR2_ATOSEL8_Pos) +#define LL_RTC_TAMPER_ATAMP8IN_ATAMP5OUT (4U << TAMP_ATCR2_ATOSEL8_Pos) +#define LL_RTC_TAMPER_ATAMP8IN_ATAMP6OUT (5U << TAMP_ATCR2_ATOSEL8_Pos) +#define LL_RTC_TAMPER_ATAMP8IN_ATAMP7OUT (6U << TAMP_ATCR2_ATOSEL8_Pos) +#define LL_RTC_TAMPER_ATAMP8IN_ATAMP8OUT (7U << TAMP_ATCR2_ATOSEL8_Pos) /** * @} */ @@ -711,7 +713,7 @@ typedef struct /** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV * @{ */ -#define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U /*!< RTC/16 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_16 0U /*!< RTC/16 clock is selected */ #define LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0 /*!< RTC/8 clock is selected */ #define LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1 /*!< RTC/4 clock is selected */ #define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */ @@ -724,7 +726,7 @@ typedef struct /** @defgroup RTC_LL_EC_CALIB_OUTPUT Calibration output * @{ */ -#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U /*!< Calibration output disabled */ +#define LL_RTC_CALIB_OUTPUT_NONE 0U /*!< Calibration output disabled */ #define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */ #define LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE /*!< Calibration output is 512 Hz */ /** @@ -734,7 +736,7 @@ typedef struct /** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion * @{ */ -#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U /*!< No RTCCLK pulses are added */ +#define LL_RTC_CALIB_INSERTPULSE_NONE 0U /*!< No RTCCLK pulses are added */ #define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */ /** * @} @@ -743,7 +745,7 @@ typedef struct /** @defgroup RTC_LL_EC_CALIB_PERIOD Calibration period * @{ */ -#define LL_RTC_CALIB_PERIOD_32SEC 0x00000000U /*!< Use a 32-second calibration cycle period */ +#define LL_RTC_CALIB_PERIOD_32SEC 0U /*!< Use a 32-second calibration cycle period */ #define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< Use a 16-second calibration cycle period */ #define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< Use a 8-second calibration cycle period */ /** @@ -753,7 +755,7 @@ typedef struct /** @defgroup RTC_LL_EC_CALIB_LOWPOWER Calibration low power * @{ */ -#define LL_RTC_CALIB_LOWPOWER_NONE 0x00000000U /*!< High conso mode */ +#define LL_RTC_CALIB_LOWPOWER_NONE 0U /*!< High conso mode */ #define LL_RTC_CALIB_LOWPOWER_SET RTC_CALR_LPCAL /*!< low power mode */ /** * @} @@ -762,7 +764,7 @@ typedef struct /** @defgroup RTC_LL_EC_BINARY_MODE Binary mode (Sub Second Register) * @{ */ -#define LL_RTC_BINARY_NONE 0x00000000U /*!< Free running BCD calendar mode (Binary mode disabled). */ +#define LL_RTC_BINARY_NONE 0U /*!< Free running BCD calendar mode (Binary mode disabled). */ #define LL_RTC_BINARY_ONLY RTC_ICSR_BIN_0 /*!< Free running Binary mode (BCD mode disabled) */ #define LL_RTC_BINARY_MIX RTC_ICSR_BIN_1 /*!< Free running BCD calendar and Binary mode enable */ /** @@ -772,7 +774,7 @@ typedef struct /** @defgroup RTC_LL_EC_BINARY_MIX_BCDU Calendar second incrementation in Binary mix mode * @{ */ -#define LL_RTC_BINARY_MIX_BCDU_0 0x00000000u /*!< 1s calendar increment is generated each time SS[7:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_0 0U /*!< 1s calendar increment is generated each time SS[7:0] = 0 */ #define LL_RTC_BINARY_MIX_BCDU_1 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[8:0] = 0 */ #define LL_RTC_BINARY_MIX_BCDU_2 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[9:0] = 0 */ #define LL_RTC_BINARY_MIX_BCDU_3 (0x3UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[10:0] = 0 */ @@ -1034,7 +1036,7 @@ __STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat * @arg @ref LL_RTC_HOURFORMAT_24HOUR * @arg @ref LL_RTC_HOURFORMAT_AMPM */ -__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT)); } @@ -1066,7 +1068,7 @@ __STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOu * @arg @ref LL_RTC_ALARMOUT_ALMB * @arg @ref LL_RTC_ALARMOUT_WAKEUP */ -__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL)); } @@ -1093,7 +1095,7 @@ __STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Outpu * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL */ -__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_TYPE)); } @@ -1153,7 +1155,7 @@ __STATIC_INLINE void LL_RTC_SetBinaryMode(RTC_TypeDef *RTCx, uint32_t BinaryMode * @arg @ref LL_RTC_BINARY_MIX * @retval None */ -__STATIC_INLINE uint32_t LL_RTC_GetBinaryMode(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetBinaryMode(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ICSR, RTC_ICSR_BIN)); } @@ -1195,7 +1197,7 @@ __STATIC_INLINE void LL_RTC_SetBinMixBCDU(RTC_TypeDef *RTCx, uint32_t BinMixBcdU * @arg @ref LL_RTC_BINARY_MIX_BCDU_7 * @retval None */ -__STATIC_INLINE uint32_t LL_RTC_GetBinMixBCDU(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetBinMixBCDU(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ICSR, RTC_ICSR_BCDU)); } @@ -1223,7 +1225,7 @@ __STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polari * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW */ -__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL)); } @@ -1257,7 +1259,7 @@ __STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1U : 0U); } @@ -1318,7 +1320,7 @@ __STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchP * @param RTCx RTC Instance * @retval Value between Min_Data = 0 and Max_Data = 0x7F */ -__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos); } @@ -1329,7 +1331,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF */ -__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S)); } @@ -1387,7 +1389,7 @@ __STATIC_INLINE void LL_RTC_DisableTamperOutput(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)) ? 1U : 0U); } @@ -1420,7 +1422,7 @@ __STATIC_INLINE void LL_RTC_DisableAlarmPullUp(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)) ? 1U : 0U); } @@ -1456,7 +1458,7 @@ __STATIC_INLINE void LL_RTC_DisableOutput2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1U : 0U); } @@ -1497,7 +1499,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 * @arg @ref LL_RTC_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM)); } @@ -1532,7 +1534,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos); } @@ -1567,7 +1569,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); } @@ -1602,7 +1604,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos); } @@ -1657,7 +1659,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS). */ -__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_Get(const RTC_TypeDef *RTCx) { uint32_t temp; @@ -1698,7 +1700,7 @@ __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1U : 0U); } @@ -1741,7 +1743,7 @@ __STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx) * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS)); } @@ -1798,7 +1800,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x99 */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos); } @@ -1837,7 +1839,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos); } @@ -1891,7 +1893,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) * @arg @ref LL_RTC_MONTH_NOVEMBER * @arg @ref LL_RTC_MONTH_DECEMBER */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos); } @@ -1921,7 +1923,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos); } @@ -1990,7 +1992,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin * @param RTCx RTC Instance * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY). */ -__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_Get(const RTC_TypeDef *RTCx) { uint32_t temp; @@ -2070,7 +2072,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) * @arg @ref LL_RTC_ALMA_MASK_SECONDS * @arg @ref LL_RTC_ALMA_MASK_ALL */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)); } @@ -2120,7 +2122,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos); } @@ -2157,7 +2159,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos); } @@ -2184,7 +2186,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeF * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM)); } @@ -2212,7 +2214,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos); } @@ -2240,7 +2242,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos); } @@ -2268,7 +2270,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos); } @@ -2317,7 +2319,7 @@ __STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12 * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds. */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(const RTC_TypeDef *RTCx) { return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << \ RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx)); @@ -2345,7 +2347,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF * else Value between Min_Data=0x0 and Max_Data=0x3F */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos); } @@ -2374,7 +2376,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetBinAutoClr(RTC_TypeDef *RTCx, uint32_t Binar * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetBinAutoClr(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetBinAutoClr(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SSCLR)); } @@ -2399,7 +2401,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS)); } @@ -2472,7 +2474,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) * @arg @ref LL_RTC_ALMB_MASK_SECONDS * @arg @ref LL_RTC_ALMB_MASK_ALL */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)); } @@ -2522,7 +2524,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos); } @@ -2559,7 +2561,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos); } @@ -2586,7 +2588,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeF * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM)); } @@ -2614,7 +2616,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos); } @@ -2642,7 +2644,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos); } @@ -2670,7 +2672,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos); } @@ -2719,7 +2721,7 @@ __STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12 * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds. */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(const RTC_TypeDef *RTCx) { return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << \ RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx)); @@ -2747,7 +2749,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF * else Value between Min_Data=0x0 and Max_Data=0x3F */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos); } @@ -2776,7 +2778,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetBinAutoClr(RTC_TypeDef *RTCx, uint32_t Binar * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_NO * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_YES */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetBinAutoClr(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetBinAutoClr(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SSCLR)); } @@ -2801,7 +2803,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS)); } @@ -2887,7 +2889,7 @@ __STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge) * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE)); } @@ -2900,7 +2902,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_TS_TIME_FORMAT_AM * @arg @ref LL_RTC_TS_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM)); } @@ -2913,7 +2915,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos); } @@ -2926,7 +2928,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos); } @@ -2939,7 +2941,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU)); } @@ -2957,7 +2959,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds. */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU)); @@ -2976,7 +2978,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos); } @@ -3001,7 +3003,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_MONTH_NOVEMBER * @arg @ref LL_RTC_MONTH_DECEMBER */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos); } @@ -3014,7 +3016,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU)); } @@ -3031,7 +3033,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Combination of Weekday, Day and Month */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU)); } @@ -3043,7 +3045,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS)); } @@ -3089,7 +3091,7 @@ __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper) +__STATIC_INLINE void LL_RTC_TAMPER_Enable(const RTC_TypeDef *RTCx, uint32_t Tamper) { UNUSED(RTCx); SET_BIT(TAMP->CR1, Tamper); @@ -3105,7 +3107,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper) * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper) +__STATIC_INLINE void LL_RTC_TAMPER_Disable(const RTC_TypeDef *RTCx, uint32_t Tamper) { UNUSED(RTCx); CLEAR_BIT(TAMP->CR1, Tamper); @@ -3122,7 +3124,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper) * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask) +__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(const RTC_TypeDef *RTCx, uint32_t Mask) { UNUSED(RTCx); SET_BIT(TAMP->CR2, Mask); @@ -3138,7 +3140,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask) * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask) +__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(const RTC_TypeDef *RTCx, uint32_t Mask) { UNUSED(RTCx); CLEAR_BIT(TAMP->CR2, Mask); @@ -3154,7 +3156,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask) * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper) +__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(const RTC_TypeDef *RTCx, uint32_t Tamper) { UNUSED(RTCx); CLEAR_BIT(TAMP->CR2, Tamper); @@ -3170,7 +3172,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Ta * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper) +__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(const RTC_TypeDef *RTCx, uint32_t Tamper) { UNUSED(RTCx); SET_BIT(TAMP->CR2, Tamper); @@ -3182,7 +3184,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t T * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS); @@ -3194,7 +3196,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS); @@ -3211,7 +3213,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration) +__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(const RTC_TypeDef *RTCx, uint32_t Duration) { UNUSED(RTCx); MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH, Duration); @@ -3227,7 +3229,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Dura * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH)); @@ -3244,7 +3246,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount) +__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(const RTC_TypeDef *RTCx, uint32_t FilterCount) { UNUSED(RTCx); MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT, FilterCount); @@ -3260,7 +3262,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t Fi * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT)); @@ -3281,7 +3283,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq) +__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(const RTC_TypeDef *RTCx, uint32_t SamplingFreq) { UNUSED(RTCx); MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ, SamplingFreq); @@ -3301,7 +3303,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t S * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ)); @@ -3317,7 +3319,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) +__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(const RTC_TypeDef *RTCx, uint32_t Tamper) { UNUSED(RTCx); SET_BIT(TAMP->CR2, Tamper); @@ -3333,7 +3335,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) +__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(const RTC_TypeDef *RTCx, uint32_t Tamper) { UNUSED(RTCx); CLEAR_BIT(TAMP->CR2, Tamper); @@ -3357,7 +3359,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_ * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Enable(RTC_TypeDef *RTCx, uint32_t InternalTamper) +__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Enable(const RTC_TypeDef *RTCx, uint32_t InternalTamper) { UNUSED(RTCx); SET_BIT(TAMP->CR1, InternalTamper); @@ -3376,7 +3378,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Enable(RTC_TypeDef *RTCx, uint32_t Inte * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Disable(RTC_TypeDef *RTCx, uint32_t InternalTamper) +__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Disable(const RTC_TypeDef *RTCx, uint32_t InternalTamper) { UNUSED(RTCx); CLEAR_BIT(TAMP->CR1, InternalTamper); @@ -3532,7 +3534,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetSharedOuputSelection(void) /** * @brief Write active tamper seed. * @rmtoll TAMP_ATSEEDR SEED LL_RTC_TAMPER_ATAMP_WriteSeed\n - * @param Seed + * @param Seed Pseudo-random generator seed value * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_ATAMP_WriteSeed(uint32_t Seed) @@ -3598,7 +3600,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1U : 0U); } @@ -3635,7 +3637,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupCl * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL)); } @@ -3659,7 +3661,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Val * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT)); } @@ -3681,11 +3683,38 @@ __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_BKP_DR1 * @arg @ref LL_RTC_BKP_DR2 * @arg @ref LL_RTC_BKP_DR3 - * @arg @ref LL_RTC_BKP_DR4 ... + * @arg @ref LL_RTC_BKP_DR4 + * @arg @ref LL_RTC_BKP_DR5 + * @arg @ref LL_RTC_BKP_DR6 + * @arg @ref LL_RTC_BKP_DR7 + * @arg @ref LL_RTC_BKP_DR8 + * @arg @ref LL_RTC_BKP_DR9 + * @arg @ref LL_RTC_BKP_DR10 + * @arg @ref LL_RTC_BKP_DR11 + * @arg @ref LL_RTC_BKP_DR12 + * @arg @ref LL_RTC_BKP_DR13 + * @arg @ref LL_RTC_BKP_DR14 + * @arg @ref LL_RTC_BKP_DR15 + * @arg @ref LL_RTC_BKP_DR16 + * @arg @ref LL_RTC_BKP_DR17 + * @arg @ref LL_RTC_BKP_DR18 + * @arg @ref LL_RTC_BKP_DR19 + * @arg @ref LL_RTC_BKP_DR20 + * @arg @ref LL_RTC_BKP_DR21 + * @arg @ref LL_RTC_BKP_DR22 + * @arg @ref LL_RTC_BKP_DR23 + * @arg @ref LL_RTC_BKP_DR24 + * @arg @ref LL_RTC_BKP_DR25 + * @arg @ref LL_RTC_BKP_DR26 + * @arg @ref LL_RTC_BKP_DR27 + * @arg @ref LL_RTC_BKP_DR28 + * @arg @ref LL_RTC_BKP_DR29 + * @arg @ref LL_RTC_BKP_DR30 + * @arg @ref LL_RTC_BKP_DR31 * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_RTC_BKP_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data) +__STATIC_INLINE void LL_RTC_BKP_SetRegister(const RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data) { __IO uint32_t tmp; @@ -3707,10 +3736,37 @@ __STATIC_INLINE void LL_RTC_BKP_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRe * @arg @ref LL_RTC_BKP_DR1 * @arg @ref LL_RTC_BKP_DR2 * @arg @ref LL_RTC_BKP_DR3 - * @arg @ref LL_RTC_BKP_DR4 ... + * @arg @ref LL_RTC_BKP_DR4 + * @arg @ref LL_RTC_BKP_DR5 + * @arg @ref LL_RTC_BKP_DR6 + * @arg @ref LL_RTC_BKP_DR7 + * @arg @ref LL_RTC_BKP_DR8 + * @arg @ref LL_RTC_BKP_DR9 + * @arg @ref LL_RTC_BKP_DR10 + * @arg @ref LL_RTC_BKP_DR11 + * @arg @ref LL_RTC_BKP_DR12 + * @arg @ref LL_RTC_BKP_DR13 + * @arg @ref LL_RTC_BKP_DR14 + * @arg @ref LL_RTC_BKP_DR15 + * @arg @ref LL_RTC_BKP_DR16 + * @arg @ref LL_RTC_BKP_DR17 + * @arg @ref LL_RTC_BKP_DR18 + * @arg @ref LL_RTC_BKP_DR19 + * @arg @ref LL_RTC_BKP_DR20 + * @arg @ref LL_RTC_BKP_DR21 + * @arg @ref LL_RTC_BKP_DR22 + * @arg @ref LL_RTC_BKP_DR23 + * @arg @ref LL_RTC_BKP_DR24 + * @arg @ref LL_RTC_BKP_DR25 + * @arg @ref LL_RTC_BKP_DR26 + * @arg @ref LL_RTC_BKP_DR27 + * @arg @ref LL_RTC_BKP_DR28 + * @arg @ref LL_RTC_BKP_DR29 + * @arg @ref LL_RTC_BKP_DR30 + * @arg @ref LL_RTC_BKP_DR31 * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister) +__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(const RTC_TypeDef *RTCx, uint32_t BackupRegister) { uint32_t tmp; @@ -3758,7 +3814,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Freque * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL)); } @@ -3785,7 +3841,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1U : 0U); } @@ -3818,7 +3874,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period) * @arg @ref LL_RTC_CALIB_PERIOD_16SEC * @arg @ref LL_RTC_CALIB_PERIOD_8SEC */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16)); } @@ -3843,7 +3899,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM)); } @@ -3880,7 +3936,7 @@ __STATIC_INLINE void LL_RTC_CAL_LowPower_Disable(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_CAL_LowPower_IsEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_LowPower_IsEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CALR, RTC_CALR_LPCAL) == (RTC_CALR_LPCAL)) ? 1U : 0U); } @@ -3899,7 +3955,7 @@ __STATIC_INLINE uint32_t LL_RTC_CAL_LowPower_IsEnabled(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_ITSF) == (RTC_SR_ITSF)) ? 1U : 0U); } @@ -3910,7 +3966,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)) ? 1U : 0U); } @@ -3921,7 +3977,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)) ? 1U : 0U); } @@ -3932,7 +3988,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_TSF) == (RTC_SR_TSF)) ? 1U : 0U); } @@ -3943,7 +3999,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_WUTF) == (RTC_SR_WUTF)) ? 1U : 0U); } @@ -3954,7 +4010,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)) ? 1U : 0U); } @@ -3965,7 +4021,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1U : 0U); } @@ -3976,7 +4032,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRU(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRU(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_SSRUF) == (RTC_SR_SSRUF)) ? 1U : 0U); } @@ -4000,7 +4056,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx) { - SET_BIT(RTCx->SCR, RTC_SCR_CTSOVF); + WRITE_REG(RTCx->SCR, RTC_SCR_CTSOVF); } /** @@ -4011,7 +4067,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx) { - SET_BIT(RTCx->SCR, RTC_SCR_CTSF); + WRITE_REG(RTCx->SCR, RTC_SCR_CTSF); } /** @@ -4022,7 +4078,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx) { - SET_BIT(RTCx->SCR, RTC_SCR_CWUTF); + WRITE_REG(RTCx->SCR, RTC_SCR_CWUTF); } /** @@ -4033,7 +4089,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx) { - SET_BIT(RTCx->SCR, RTC_SCR_CALRBF); + WRITE_REG(RTCx->SCR, RTC_SCR_CALRBF); } /** @@ -4064,7 +4120,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_SSRU(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)) ? 1U : 0U); } @@ -4075,7 +4131,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)) ? 1U : 0U); } @@ -4097,7 +4153,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)) ? 1U : 0U); } @@ -4108,7 +4164,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)) ? 1U : 0U); } @@ -4119,7 +4175,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)) ? 1U : 0U); } @@ -4130,7 +4186,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)) ? 1U : 0U); } @@ -4141,7 +4197,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRUM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRUM(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_SSRUMF) == (RTC_MISR_SSRUMF)) ? 1U : 0U); } @@ -4152,7 +4208,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRUM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)) ? 1U : 0U); } @@ -4163,7 +4219,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)) ? 1U : 0U); } @@ -4174,7 +4230,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)) ? 1U : 0U); } @@ -4185,7 +4241,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)) ? 1U : 0U); } @@ -4196,7 +4252,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)) ? 1U : 0U); } @@ -4207,7 +4263,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)) ? 1U : 0U); @@ -4219,7 +4275,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)) ? 1U : 0U); @@ -4231,7 +4287,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1U : 0U); @@ -4242,7 +4298,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP4F) == (TAMP_SR_TAMP4F)) ? 1U : 0U); @@ -4253,7 +4309,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP5F) == (TAMP_SR_TAMP5F)) ? 1U : 0U); @@ -4264,7 +4320,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP6F) == (TAMP_SR_TAMP6F)) ? 1U : 0U); @@ -4275,7 +4331,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP7F) == (TAMP_SR_TAMP7F)) ? 1U : 0U); @@ -4286,7 +4342,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP8F) == (TAMP_SR_TAMP8F)) ? 1U : 0U); @@ -4298,7 +4354,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP1F) == (TAMP_SR_ITAMP1F)) ? 1U : 0U); @@ -4310,7 +4366,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP2F) == (TAMP_SR_ITAMP2F)) ? 1U : 0U); @@ -4322,7 +4378,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP3F) == (TAMP_SR_ITAMP3F)) ? 1U : 0U); @@ -4335,7 +4391,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP5F) == (TAMP_SR_ITAMP5F)) ? 1U : 0U); @@ -4347,19 +4403,31 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP6F) == (TAMP_SR_ITAMP6F)) ? 1U : 0U); } +/** + * @brief Get internal tamper 7 detection flag. + * @rmtoll TAMP_SR ITAMP7F LL_RTC_IsActiveFlag_ITAMP7 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP7(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP7F) == (TAMP_SR_ITAMP7F)) ? 1U : 0U); +} + /** * @brief Get internal tamper 8 detection flag. * @rmtoll TAMP_SR ITAMP8F LL_RTC_IsActiveFlag_ITAMP8 * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP8F) == (TAMP_SR_ITAMP8F)) ? 1U : 0U); @@ -4371,7 +4439,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP9(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP9(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP9F) == (TAMP_SR_ITAMP9F)) ? 1U : 0U); @@ -4383,7 +4451,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP9(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP11(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP11(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP11F) == (TAMP_SR_ITAMP11F)) ? 1U : 0U); @@ -4395,7 +4463,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP11(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP12(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP12(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP12F) == (TAMP_SR_ITAMP12F)) ? 1U : 0U); @@ -4406,7 +4474,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP12(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP13(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP13(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP13F) == (TAMP_SR_ITAMP13F)) ? 1U : 0U); @@ -4418,7 +4486,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP13(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)) ? 1U : 0U); @@ -4430,7 +4498,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)) ? 1U : 0U); @@ -4442,7 +4510,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1U : 0U); @@ -4453,7 +4521,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4M(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP4MF) == (TAMP_MISR_TAMP4MF)) ? 1U : 0U); @@ -4464,7 +4532,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5M(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP5MF) == (TAMP_MISR_TAMP5MF)) ? 1U : 0U); @@ -4475,7 +4543,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6M(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP6MF) == (TAMP_MISR_TAMP6MF)) ? 1U : 0U); @@ -4486,7 +4554,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7M(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP7MF) == (TAMP_MISR_TAMP7MF)) ? 1U : 0U); @@ -4497,7 +4565,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8M(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP8MF) == (TAMP_MISR_TAMP8MF)) ? 1U : 0U); @@ -4509,7 +4577,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1M(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP1MF) == (TAMP_MISR_ITAMP1MF)) ? 1U : 0U); @@ -4521,7 +4589,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2M(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP2MF) == (TAMP_MISR_ITAMP2MF)) ? 1U : 0U); @@ -4533,7 +4601,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP3MF) == (TAMP_MISR_ITAMP3MF)) ? 1U : 0U); @@ -4545,7 +4613,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP5MF) == (TAMP_MISR_ITAMP5MF)) ? 1U : 0U); @@ -4557,7 +4625,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8M(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP8MF) == (TAMP_MISR_ITAMP8MF)) ? 1U : 0U); @@ -4569,10 +4637,10 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(const RTC_TypeDef *RTCx) { UNUSED(RTCx); - SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP1F); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP1F); } /** @@ -4581,10 +4649,10 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(const RTC_TypeDef *RTCx) { UNUSED(RTCx); - SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP2F); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP2F); } /** @@ -4593,10 +4661,10 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(const RTC_TypeDef *RTCx) { UNUSED(RTCx); - SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP3F); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP3F); } /** * @brief Clear tamper 4 detection flag. @@ -4604,10 +4672,10 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMP4(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP4(const RTC_TypeDef *RTCx) { UNUSED(RTCx); - SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP4F); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP4F); } /** * @brief Clear tamper 5 detection flag. @@ -4615,10 +4683,10 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP4(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP5(const RTC_TypeDef *RTCx) { UNUSED(RTCx); - SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP5F); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP5F); } /** * @brief Clear tamper 6 detection flag. @@ -4626,10 +4694,10 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMP6(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP6(const RTC_TypeDef *RTCx) { UNUSED(RTCx); - SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP6F); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP6F); } /** * @brief Clear tamper 7 detection flag. @@ -4637,10 +4705,10 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP6(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMP7(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP7(const RTC_TypeDef *RTCx) { UNUSED(RTCx); - SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP7F); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP7F); } /** * @brief Clear tamper 8 detection flag. @@ -4648,10 +4716,10 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP7(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP8(const RTC_TypeDef *RTCx) { UNUSED(RTCx); - SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP8F); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP8F); } /** @@ -4660,10 +4728,10 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP8(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP1(const RTC_TypeDef *RTCx) { UNUSED(RTCx); - SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP1F); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP1F); } /** @@ -4672,10 +4740,10 @@ __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP2(const RTC_TypeDef *RTCx) { UNUSED(RTCx); - SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP2F); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP2F); } /** @@ -4684,10 +4752,10 @@ __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP3(const RTC_TypeDef *RTCx) { UNUSED(RTCx); - SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP3F); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP3F); } /** @@ -4696,10 +4764,10 @@ __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP5(const RTC_TypeDef *RTCx) { UNUSED(RTCx); - SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP5F); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP5F); } /** @@ -4708,10 +4776,10 @@ __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP8(const RTC_TypeDef *RTCx) { UNUSED(RTCx); - SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP8F); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP8F); } /** @@ -4774,7 +4842,7 @@ __STATIC_INLINE void LL_RTC_SetRtcSecure(RTC_TypeDef *RTCx, uint32_t rtcSecure) * @arg @ref LL_RTC_UNSECURE_FEATURE_ALRA * @arg @ref LL_RTC_UNSECURE_FEATURE_ALRB */ -__STATIC_INLINE uint32_t LL_RTC_GetRtcSecure(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetRtcSecure(const RTC_TypeDef *RTCx) { return READ_BIT(RTCx->SECCFGR, RTC_SECCFGR_SEC | RTC_SECCFGR_INITSEC | RTC_SECCFGR_CALSEC | RTC_SECCFGR_TSSEC | \ RTC_SECCFGR_WUTSEC | RTC_SECCFGR_ALRASEC | RTC_SECCFGR_ALRBSEC); @@ -4790,7 +4858,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetRtcSecure(RTC_TypeDef *RTCx) * @arg @ref LL_TAMP_SECURE_FULL_NO * @retval None */ -__STATIC_INLINE void LL_RTC_SetTampSecure(RTC_TypeDef *RTCx, uint32_t tampSecure) +__STATIC_INLINE void LL_RTC_SetTampSecure(const RTC_TypeDef *RTCx, uint32_t tampSecure) { UNUSED(RTCx); MODIFY_REG(TAMP->SECCFGR, TAMP_SECCFGR_TAMPSEC, tampSecure); @@ -4805,7 +4873,7 @@ __STATIC_INLINE void LL_RTC_SetTampSecure(RTC_TypeDef *RTCx, uint32_t tampSecure * @arg @ref LL_TAMP_SECURE_FULL_YES * @arg @ref LL_TAMP_SECURE_FULL_NO */ -__STATIC_INLINE uint32_t LL_RTC_GetTampSecure(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetTampSecure(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return READ_BIT(TAMP->SECCFGR, TAMP_SECCFGR_TAMPSEC); @@ -4868,7 +4936,7 @@ __STATIC_INLINE void LL_RTC_SetRtcPrivilege(RTC_TypeDef *RTCx, uint32_t rtcPrivi * @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRA * @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRB */ -__STATIC_INLINE uint32_t LL_RTC_GetRtcPrivilege(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetRtcPrivilege(const RTC_TypeDef *RTCx) { return READ_BIT(RTCx->PRIVCFGR, RTC_PRIVCFGR_PRIV | RTC_PRIVCFGR_INITPRIV | RTC_PRIVCFGR_CALPRIV | \ RTC_PRIVCFGR_TSPRIV | RTC_PRIVCFGR_WUTPRIV | RTC_PRIVCFGR_ALRAPRIV | RTC_PRIVCFGR_ALRBPRIV); @@ -4883,7 +4951,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetRtcPrivilege(RTC_TypeDef *RTCx) * @arg @ref LL_TAMP_PRIVILEGE_FULL_NO * @retval None */ -__STATIC_INLINE void LL_RTC_SetTampPrivilege(RTC_TypeDef *RTCx, uint32_t tampPrivilege) +__STATIC_INLINE void LL_RTC_SetTampPrivilege(const RTC_TypeDef *RTCx, uint32_t tampPrivilege) { UNUSED(RTCx); MODIFY_REG(TAMP->PRIVCFGR, TAMP_PRIVCFGR_TAMPPRIV, tampPrivilege); @@ -4897,7 +4965,7 @@ __STATIC_INLINE void LL_RTC_SetTampPrivilege(RTC_TypeDef *RTCx, uint32_t tampPri * @arg @ref LL_TAMP_PRIVILEGE_FULL_YES * @arg @ref LL_TAMP_PRIVILEGE_FULL_NO */ -__STATIC_INLINE uint32_t LL_RTC_GetTampPrivilege(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetTampPrivilege(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return READ_BIT(TAMP->PRIVCFGR, TAMP_PRIVCFGR_TAMPPRIV); @@ -4916,7 +4984,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetTampPrivilege(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_ALL * @retval None */ -__STATIC_INLINE void LL_RTC_SetBackupRegisterPrivilege(RTC_TypeDef *RTCx, uint32_t bckupRegisterPrivilege) +__STATIC_INLINE void LL_RTC_SetBackupRegisterPrivilege(const RTC_TypeDef *RTCx, uint32_t bckupRegisterPrivilege) { UNUSED(RTCx); MODIFY_REG(TAMP->PRIVCFGR, (TAMP_PRIVCFGR_BKPWPRIV | TAMP_PRIVCFGR_BKPRWPRIV), bckupRegisterPrivilege); @@ -4933,7 +5001,7 @@ __STATIC_INLINE void LL_RTC_SetBackupRegisterPrivilege(RTC_TypeDef *RTCx, uint32 * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_2 * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_ALL */ -__STATIC_INLINE uint32_t LL_RTC_GetBackupRegisterPrivilege(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetBackupRegisterPrivilege(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return READ_BIT(TAMP->PRIVCFGR, (TAMP_PRIVCFGR_BKPWPRIV | TAMP_PRIVCFGR_BKPRWPRIV)); @@ -4964,16 +5032,70 @@ __STATIC_INLINE uint32_t LL_RTC_GetBackupRegisterPrivilege(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_BKP_DR1 * @arg @ref LL_RTC_BKP_DR2 * @arg @ref LL_RTC_BKP_DR3 - * @arg @ref LL_RTC_BKP_DR4 ... + * @arg @ref LL_RTC_BKP_DR4 + * @arg @ref LL_RTC_BKP_DR5 + * @arg @ref LL_RTC_BKP_DR6 + * @arg @ref LL_RTC_BKP_DR7 + * @arg @ref LL_RTC_BKP_DR8 + * @arg @ref LL_RTC_BKP_DR9 + * @arg @ref LL_RTC_BKP_DR10 + * @arg @ref LL_RTC_BKP_DR11 + * @arg @ref LL_RTC_BKP_DR12 + * @arg @ref LL_RTC_BKP_DR13 + * @arg @ref LL_RTC_BKP_DR14 + * @arg @ref LL_RTC_BKP_DR15 + * @arg @ref LL_RTC_BKP_DR16 + * @arg @ref LL_RTC_BKP_DR17 + * @arg @ref LL_RTC_BKP_DR18 + * @arg @ref LL_RTC_BKP_DR19 + * @arg @ref LL_RTC_BKP_DR20 + * @arg @ref LL_RTC_BKP_DR21 + * @arg @ref LL_RTC_BKP_DR22 + * @arg @ref LL_RTC_BKP_DR23 + * @arg @ref LL_RTC_BKP_DR24 + * @arg @ref LL_RTC_BKP_DR25 + * @arg @ref LL_RTC_BKP_DR26 + * @arg @ref LL_RTC_BKP_DR27 + * @arg @ref LL_RTC_BKP_DR28 + * @arg @ref LL_RTC_BKP_DR29 + * @arg @ref LL_RTC_BKP_DR30 + * @arg @ref LL_RTC_BKP_DR31 * @param startZone3 This parameter can be one of the following values: * @arg @ref LL_RTC_BKP_DR0 * @arg @ref LL_RTC_BKP_DR1 * @arg @ref LL_RTC_BKP_DR2 * @arg @ref LL_RTC_BKP_DR3 - * @arg @ref LL_RTC_BKP_DR4 ... - * @retval None - */ -__STATIC_INLINE void LL_RTC_SetBackupRegProtection(RTC_TypeDef *RTCx, uint32_t startZone2, uint32_t startZone3) + * @arg @ref LL_RTC_BKP_DR4 + * @arg @ref LL_RTC_BKP_DR5 + * @arg @ref LL_RTC_BKP_DR6 + * @arg @ref LL_RTC_BKP_DR7 + * @arg @ref LL_RTC_BKP_DR8 + * @arg @ref LL_RTC_BKP_DR9 + * @arg @ref LL_RTC_BKP_DR10 + * @arg @ref LL_RTC_BKP_DR11 + * @arg @ref LL_RTC_BKP_DR12 + * @arg @ref LL_RTC_BKP_DR13 + * @arg @ref LL_RTC_BKP_DR14 + * @arg @ref LL_RTC_BKP_DR15 + * @arg @ref LL_RTC_BKP_DR16 + * @arg @ref LL_RTC_BKP_DR17 + * @arg @ref LL_RTC_BKP_DR18 + * @arg @ref LL_RTC_BKP_DR19 + * @arg @ref LL_RTC_BKP_DR20 + * @arg @ref LL_RTC_BKP_DR21 + * @arg @ref LL_RTC_BKP_DR22 + * @arg @ref LL_RTC_BKP_DR23 + * @arg @ref LL_RTC_BKP_DR24 + * @arg @ref LL_RTC_BKP_DR25 + * @arg @ref LL_RTC_BKP_DR26 + * @arg @ref LL_RTC_BKP_DR27 + * @arg @ref LL_RTC_BKP_DR28 + * @arg @ref LL_RTC_BKP_DR29 + * @arg @ref LL_RTC_BKP_DR30 + * @arg @ref LL_RTC_BKP_DR31 + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetBackupRegProtection(const RTC_TypeDef *RTCx, uint32_t startZone2, uint32_t startZone3) { UNUSED(RTCx); MODIFY_REG(TAMP->SECCFGR, (TAMP_SECCFGR_BKPRWSEC_Msk | TAMP_SECCFGR_BKPWSEC_Msk), (startZone2 << \ @@ -4989,7 +5111,7 @@ __STATIC_INLINE void LL_RTC_SetBackupRegProtection(RTC_TypeDef *RTCx, uint32_t s * @param RTCx RTC Instance * @retval Start zone 2 */ -__STATIC_INLINE uint32_t LL_RTC_GetBackupRegProtectionStartZone2(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetBackupRegProtectionStartZone2(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return READ_BIT(TAMP->SECCFGR, TAMP_SECCFGR_BKPRWSEC_Msk) >> TAMP_SECCFGR_BKPRWSEC_Pos; @@ -5004,7 +5126,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetBackupRegProtectionStartZone2(RTC_TypeDef *RT * @param RTCx RTC Instance * @retval Start zone 2 */ -__STATIC_INLINE uint32_t LL_RTC_GetBackupRegProtectionStartZone3(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetBackupRegProtectionStartZone3(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return READ_BIT(TAMP->SECCFGR, TAMP_SECCFGR_BKPWSEC_Msk) >> TAMP_SECCFGR_BKPWSEC_Pos; @@ -5143,7 +5265,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_SSRU(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1U : 0U); } @@ -5154,7 +5276,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1U : 0U); } @@ -5165,7 +5287,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1U : 0U); } @@ -5176,7 +5298,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1U : 0U); } @@ -5187,7 +5309,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_SSRU(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_SSRU(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_SSRUIE) == (RTC_CR_SSRUIE)) ? 1U : 0U); } @@ -5198,7 +5320,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_SSRU(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_TAMP1IE); @@ -5210,7 +5332,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP1IE); @@ -5222,7 +5344,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_TAMP2IE); @@ -5234,7 +5356,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP2IE); @@ -5246,7 +5368,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_TAMP3IE); @@ -5257,7 +5379,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP3IE); @@ -5268,7 +5390,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP4(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_TAMP4(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_TAMP4IE); @@ -5279,7 +5401,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_TAMP4(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP4(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_TAMP4(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP4IE); @@ -5291,7 +5413,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP4(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_TAMP5(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_TAMP5IE); @@ -5302,7 +5424,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_TAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_TAMP5(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP5IE); @@ -5314,7 +5436,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP6(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_TAMP6(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_TAMP6IE); @@ -5325,7 +5447,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_TAMP6(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP6(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_TAMP6(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP6IE); @@ -5337,7 +5459,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP6(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP7(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_TAMP7(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_TAMP7IE); @@ -5348,7 +5470,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_TAMP7(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP7(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_TAMP7(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP7IE); @@ -5360,7 +5482,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP7(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_TAMP8(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_TAMP8IE); @@ -5371,7 +5493,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_TAMP8(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_TAMP8(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP8IE); @@ -5383,7 +5505,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP8(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_ITAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP1(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_ITAMP1IE); @@ -5395,7 +5517,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_ITAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_ITAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP1(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP1IE); @@ -5407,7 +5529,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ITAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_ITAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP2(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_ITAMP2IE); @@ -5419,7 +5541,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_ITAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_ITAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP2(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP2IE); @@ -5431,7 +5553,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ITAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_ITAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP3(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_ITAMP3IE); @@ -5442,7 +5564,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_ITAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_ITAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP3(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP3IE); @@ -5454,7 +5576,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ITAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_ITAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP5(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_ITAMP5IE); @@ -5465,7 +5587,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_ITAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_ITAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP5(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP5IE); @@ -5477,7 +5599,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ITAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_ITAMP6(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP6(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_ITAMP6IE); @@ -5488,7 +5610,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_ITAMP6(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_ITAMP6(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP6(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP6IE); @@ -5500,7 +5622,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ITAMP6(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_ITAMP7(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP7(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_ITAMP7IE); @@ -5511,7 +5633,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_ITAMP7(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_ITAMP7(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP7(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP7IE); @@ -5523,7 +5645,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ITAMP7(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_ITAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP8(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_ITAMP8IE); @@ -5534,7 +5656,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_ITAMP8(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_ITAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP8(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP8IE); @@ -5546,7 +5668,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ITAMP8(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_ITAMP9(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP9(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_ITAMP9IE); @@ -5557,7 +5679,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_ITAMP9(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_ITAMP9(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP9(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP9IE); @@ -5569,7 +5691,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ITAMP9(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_ITAMP11(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP11(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_ITAMP11IE); @@ -5580,18 +5702,18 @@ __STATIC_INLINE void LL_RTC_EnableIT_ITAMP11(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_ITAMP11(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP11(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP11IE); } /** * @brief Enable internal tamper 12 interrupt. - * @rmtoll TAMP_IER ITAMP12IE LL_RTC_EnableIT_ITAM12 + * @rmtoll TAMP_IER ITAMP12IE LL_RTC_EnableIT_ITAMP12 * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_ITAMP12(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP12(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_ITAMP12IE); @@ -5602,7 +5724,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_ITAMP12(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_ITAMP12(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP12(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP12IE); @@ -5613,7 +5735,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ITAMP12(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_ITAMP13(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP13(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_ITAMP13IE); @@ -5624,7 +5746,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_ITAMP13(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_ITAMP13(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP13(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP13IE); @@ -5636,7 +5758,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ITAMP13(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)) ? 1U : 0U); @@ -5648,7 +5770,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)) ? 1U : 0U); @@ -5660,7 +5782,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1U : 0U); @@ -5671,7 +5793,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP4(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP4(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP4IE) == (TAMP_IER_TAMP4IE)) ? 1U : 0U); @@ -5682,7 +5804,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP4(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP5(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP5IE) == (TAMP_IER_TAMP5IE)) ? 1U : 0U); @@ -5693,7 +5815,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP6(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP6(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP6IE) == (TAMP_IER_TAMP6IE)) ? 1U : 0U); @@ -5704,7 +5826,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP6(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP7(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP7(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP7IE) == (TAMP_IER_TAMP7IE)) ? 1U : 0U); @@ -5715,7 +5837,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP7(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP8(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP8IE) == (TAMP_IER_TAMP8IE)) ? 1U : 0U); @@ -5727,7 +5849,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP8(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP1(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP1IE) == (TAMP_IER_ITAMP1IE)) ? 1U : 0U); @@ -5739,7 +5861,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP2(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP2IE) == (TAMP_IER_ITAMP2IE)) ? 1U : 0U); @@ -5751,7 +5873,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP3IE) == (TAMP_IER_ITAMP3IE)) ? 1U : 0U); @@ -5763,7 +5885,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP5IE) == (TAMP_IER_ITAMP5IE)) ? 1U : 0U); @@ -5775,7 +5897,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP6(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP6(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP6IE) == (TAMP_IER_ITAMP6IE)) ? 1U : 0U); @@ -5787,7 +5909,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP6(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP7(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP7(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP7IE) == (TAMP_IER_ITAMP7IE)) ? 1U : 0U); @@ -5799,7 +5921,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP7(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP8(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP8IE) == (TAMP_IER_ITAMP8IE)) ? 1U : 0U); @@ -5811,7 +5933,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP8(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP9(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP9(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP9IE) == (TAMP_IER_ITAMP9IE)) ? 1U : 0U); @@ -5823,7 +5945,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP9(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP11(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP11(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP11IE) == (TAMP_IER_ITAMP11IE)) ? 1U : 0U); @@ -5835,7 +5957,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP11(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP12(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP12(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP12IE) == (TAMP_IER_ITAMP12IE)) ? 1U : 0U); @@ -5847,7 +5969,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP12(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP13(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP13(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP13IE) == (TAMP_IER_ITAMP13IE)) ? 1U : 0U); @@ -5859,10 +5981,10 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP13(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None. */ -__STATIC_INLINE void LL_RTC_IncrementMonotonicCounter(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_IncrementMonotonicCounter(const RTC_TypeDef *RTCx) { UNUSED(RTCx); - WRITE_REG(TAMP->COUNTR, 0u); + WRITE_REG(TAMP->COUNTR, 0U); } /** @@ -5871,7 +5993,7 @@ __STATIC_INLINE void LL_RTC_IncrementMonotonicCounter(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Monotonic counter value. */ -__STATIC_INLINE uint32_t LL_RTC_GetMonotonicCounter(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetMonotonicCounter(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return READ_REG(TAMP->COUNTR); diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_sdmmc.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_sdmmc.c index c5af48e3ac2..1f9bc9d9739 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_sdmmc.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_sdmmc.c @@ -147,6 +147,7 @@ By the same approach, you could implement a command and check the response. @endverbatim + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -1058,6 +1059,31 @@ uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA) return errorstate; } +/** + * @brief Send the Sleep command to MMC card (not SD card). + * @param SDMMCx Pointer to SDMMC register base + * @param Argument Argument of the command (RCA and Sleep/Awake) + * @retval HAL status + */ +uint32_t SDMMC_CmdSleepMmc(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD5 SDMMC_CMD_MMC_SLEEP_AWAKE */ + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_MMC_SLEEP_AWAKE; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_MMC_SLEEP_AWAKE, SDMMC_CMDTIMEOUT); + + return errorstate; +} + /** * @brief Send the Status command and check the response. * @param SDMMCx: Pointer to SDMMC register base @@ -1143,7 +1169,7 @@ uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument) /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */ /* CMD Response: R1 */ - sdmmc_cmdinit.Argument = Argument; /* SDMMC_SDR25_SWITCH_PATTERN;*/ + sdmmc_cmdinit.Argument = Argument; /* SDMMC_SDR25_SWITCH_PATTERN*/ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; @@ -1541,7 +1567,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { - /* Card is SD V2.0 compliant */ + /* Card is not SD V2.0 compliant */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); return SDMMC_ERROR_CMD_RSP_TIMEOUT; @@ -1549,7 +1575,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) { - /* Card is SD V2.0 compliant */ + /* Card is not SD V2.0 compliant */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); return SDMMC_ERROR_CMD_CRC_FAIL; @@ -1683,7 +1709,8 @@ uint32_t SDMMC_DMALinkedList_RemoveNode(SDMMC_DMALinkedListTypeDef *pLinkedList, { uint32_t count = 0U; uint32_t linked_list_offset; - SDMMC_DMALinkNodeTypeDef *prev_node, * curr_node ; + SDMMC_DMALinkNodeTypeDef *prev_node = NULL; + SDMMC_DMALinkNodeTypeDef *curr_node ; /* First Node */ if (pLinkedList->NodesCounter == 0U) diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_sdmmc.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_sdmmc.h index f850cddfcf8..dbcdd37d22d 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_sdmmc.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_sdmmc.h @@ -240,6 +240,11 @@ typedef struct #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ +/** + * @brief Following commands are MMC Specific commands. + */ +#define SDMMC_CMD_MMC_SLEEP_AWAKE ((uint8_t)5U) /*!< Toggle the device between Sleep state and Standby state. */ + /** * @brief Following commands are SD Card Specific security commands. * SDMMC_CMD_APP_CMD should be sent before sending these commands. @@ -296,6 +301,7 @@ typedef struct #define SDMMC_SDR104_SWITCH_PATTERN ((uint32_t)0x80FF1F03U) #define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U) #define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U) +#define SDMMC_SDR12_SWITCH_PATTERN ((uint32_t)0x80FFFF00U) #define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU) @@ -307,8 +313,9 @@ typedef struct #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) +#ifndef SDMMC_DATATIMEOUT #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) - +#endif /* SDMMC_DATATIMEOUT */ #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U) #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U) @@ -372,12 +379,15 @@ typedef struct #define SDMMC_SPEED_MODE_DEFAULT ((uint32_t)0x00000001U) #define SDMMC_SPEED_MODE_HIGH ((uint32_t)0x00000002U) #define SDMMC_SPEED_MODE_ULTRA ((uint32_t)0x00000003U) +#define SDMMC_SPEED_MODE_ULTRA_SDR104 SDMMC_SPEED_MODE_ULTRA #define SDMMC_SPEED_MODE_DDR ((uint32_t)0x00000004U) +#define SDMMC_SPEED_MODE_ULTRA_SDR50 ((uint32_t)0x00000005U) -#define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \ - ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \ - ((MODE) == SDMMC_SPEED_MODE_HIGH) || \ - ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \ +#define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \ + ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \ + ((MODE) == SDMMC_SPEED_MODE_HIGH) || \ + ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \ + ((MODE) == SDMMC_SPEED_MODE_ULTRA_SDR50) || \ ((MODE) == SDMMC_SPEED_MODE_DDR)) /** @@ -1078,6 +1088,7 @@ uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA); uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA); +uint32_t SDMMC_CmdSleepMmc(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_spi.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_spi.c index f2aba96a9f6..e1eca0db6d7 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_spi.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_spi.c @@ -20,10 +20,6 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32u5xx_ll_spi.h" #include "stm32u5xx_ll_bus.h" -#include "stm32u5xx_ll_rcc.h" -#ifdef GENERATOR_I2S_PRESENT -#include "stm32u5xx_ll_rcc.h" -#endif /* GENERATOR_I2S_PRESENT*/ #ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else @@ -240,7 +236,7 @@ * - SUCCESS: SPI registers are de-initialized * - ERROR: SPI registers are not de-initialized */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx) { ErrorStatus status = ERROR; @@ -343,6 +339,7 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) ErrorStatus status = ERROR; uint32_t tmp_nss; uint32_t tmp_mode; + uint32_t tmp_nss_polarity; /* Check the SPI Instance SPIx*/ assert_param(IS_SPI_ALL_INSTANCE(SPIx)); @@ -372,10 +369,13 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) tmp_nss = SPI_InitStruct->NSS; tmp_mode = SPI_InitStruct->Mode; + tmp_nss_polarity = LL_SPI_GetNSSPolarity(SPIx); /* Checks to setup Internal SS signal level and avoid a MODF Error */ - if ((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_LOW) && (tmp_nss == LL_SPI_NSS_SOFT) && - (tmp_mode == LL_SPI_MODE_MASTER)) + if ((tmp_nss == LL_SPI_NSS_SOFT) && (((tmp_nss_polarity == LL_SPI_NSS_POLARITY_LOW) && \ + (tmp_mode == LL_SPI_MODE_MASTER)) || \ + ((tmp_nss_polarity == LL_SPI_NSS_POLARITY_HIGH) && \ + (tmp_mode == LL_SPI_MODE_SLAVE)))) { LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH); } diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_spi.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_spi.h index a02c5da8573..3879bba83e1 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_spi.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_spi.h @@ -40,15 +40,24 @@ extern "C" { /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ +/** Legacy definitions for compatibility purpose +@cond 0 + */ +#define LL_SPI_UNDERRUN_BEHAV_LAST_RECEIVED LL_SPI_UDR_CONFIG_LAST_RECEIVED +/** +@endcond + */ /* Private macros ------------------------------------------------------------*/ /** @defgroup SPI_LL_Private_Macros SPI Private Macros * @{ */ -#define IS_LL_SPI_GRP1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) ||\ - ((__INSTANCE__) == SPI2) - -#define IS_LL_SPI_GRP2_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPI3) +#if defined(IS_SPI_GRP2_INSTANCE) +#define IS_LL_SPI_GRP1_INSTANCE(__INSTANCE__) IS_SPI_GRP1_INSTANCE(__INSTANCE__) +#define IS_LL_SPI_GRP2_INSTANCE(__INSTANCE__) IS_SPI_GRP2_INSTANCE(__INSTANCE__) +#else +#define IS_LL_SPI_GRP1_INSTANCE(__INSTANCE__) IS_SPI_GRP1_INSTANCE(__INSTANCE__) +#endif /* SPI_TRIG_GRP2 */ /** * @} */ @@ -271,7 +280,7 @@ typedef struct * @{ */ #define LL_SPI_UDR_CONFIG_REGISTER_PATTERN (0x00000000UL) -#define LL_SPI_UNDERRUN_BEHAV_LAST_RECEIVED (SPI_CFG1_UDRCFG) +#define LL_SPI_UDR_CONFIG_LAST_RECEIVED (SPI_CFG1_UDRCFG) /** * @} */ @@ -495,7 +504,9 @@ typedef struct * @{ */ #define LL_SPI_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for SPI1 and SPI2 */ +#if defined(SPI3) #define LL_SPI_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for SPI3 */ +#endif /* SPI3 */ /*!< HW Trigger signal is GPDMA_CH0_TRG */ #define LL_SPI_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x00000000U)) @@ -522,6 +533,7 @@ typedef struct /*!< HW Trigger signal is RTC_WUT_TRG */ #define LL_SPI_GRP1_RTC_WUT_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos)) +#if defined(LL_SPI_TRIG_GRP2) /*!< HW Trigger signal is LPDMA_CH0_TRG */ #define LL_SPI_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x00000000U)) /*!< HW Trigger signal is LPDMA_CH1_TRG */ @@ -546,7 +558,7 @@ typedef struct #define LL_SPI_GRP2_RTC_ALRA_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_WUT_TRG */ #define LL_SPI_GRP2_RTC_WUT_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos)) - +#endif /* LL_SPI_TRIG_GRP2 */ /** * @} */ @@ -638,7 +650,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); } @@ -673,7 +685,7 @@ __STATIC_INLINE void LL_SPI_DisableIOSwap(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL); } @@ -708,7 +720,7 @@ __STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL); } @@ -736,7 +748,7 @@ __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) * @arg @ref LL_SPI_MODE_MASTER * @arg @ref LL_SPI_MODE_SLAVE */ -__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER)); } @@ -791,7 +803,7 @@ __STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *SPIx, uint32_t Mast * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE */ -__STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI)); } @@ -846,7 +858,7 @@ __STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *SPIx, uint32_t Mas * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE */ -__STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI)); } @@ -871,7 +883,7 @@ __STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count) * @param SPIx SPI Instance * @retval 0..0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferSize(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferSize(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE)); } @@ -895,7 +907,7 @@ __STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL); } @@ -922,7 +934,7 @@ __STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCR * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN */ -__STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI)); } @@ -949,7 +961,7 @@ __STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t RXCR * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN */ -__STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI)); } @@ -977,7 +989,7 @@ __STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *SPIx, uint32_t SSLev * @arg @ref LL_SPI_SS_LEVEL_HIGH * @arg @ref LL_SPI_SS_LEVEL_LOW */ -__STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI)); } @@ -1010,7 +1022,7 @@ __STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL); } @@ -1043,7 +1055,7 @@ __STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL); } @@ -1076,7 +1088,7 @@ __STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL); } @@ -1088,7 +1100,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @param UDRConfig This parameter can be one of the following values: * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN - * @arg @ref LL_SPI_UNDERRUN_BEHAV_LAST_RECEIVED + * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED * @retval None */ __STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRConfig) @@ -1102,9 +1114,9 @@ __STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRC * @param SPIx SPI Instance * @retval Returned value can be one of the following values: * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN - * @arg @ref LL_SPI_UNDERRUN_BEHAV_LAST_RECEIVED + * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED */ -__STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG)); } @@ -1133,7 +1145,7 @@ __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) * @arg @ref LL_SPI_PROTOCOL_MOTOROLA * @arg @ref LL_SPI_PROTOCOL_TI */ -__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP)); } @@ -1162,7 +1174,7 @@ __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase * @arg @ref LL_SPI_PHASE_1EDGE * @arg @ref LL_SPI_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA)); } @@ -1191,7 +1203,7 @@ __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo * @arg @ref LL_SPI_POLARITY_LOW * @arg @ref LL_SPI_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL)); } @@ -1220,7 +1232,7 @@ __STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *SPIx, uint32_t NSSPolari * @arg @ref LL_SPI_NSS_POLARITY_LOW * @arg @ref LL_SPI_NSS_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP)); } @@ -1263,7 +1275,7 @@ __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Bau * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 */ -__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS))); } @@ -1292,7 +1304,7 @@ __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitO * @arg @ref LL_SPI_LSB_FIRST * @arg @ref LL_SPI_MSB_FIRST */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST)); } @@ -1330,7 +1342,7 @@ __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t Tra * @arg @ref LL_SPI_HALF_DUPLEX_RX * @arg @ref LL_SPI_HALF_DUPLEX_TX */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx) { uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR); uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM); @@ -1361,7 +1373,7 @@ __STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t H * @arg @ref LL_SPI_HALF_DUPLEX_RX * @arg @ref LL_SPI_HALF_DUPLEX_TX */ -__STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) | SPI_CFG2_COMM); } @@ -1443,7 +1455,7 @@ __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) * @arg @ref LL_SPI_DATAWIDTH_31BIT * @arg @ref LL_SPI_DATAWIDTH_32BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE)); } @@ -1499,7 +1511,7 @@ __STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Thresho * @arg @ref LL_SPI_FIFO_TH_15DATA * @arg @ref LL_SPI_FIFO_TH_16DATA */ -__STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV)); } @@ -1533,7 +1545,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL); } @@ -1615,7 +1627,7 @@ __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) * @arg @ref LL_SPI_CRC_31BIT * @arg @ref LL_SPI_CRC_32BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE)); } @@ -1648,7 +1660,7 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) * @arg @ref LL_SPI_NSS_HARD_INPUT * @arg @ref LL_SPI_NSS_HARD_OUTPUT */ -__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE)); } @@ -1685,7 +1697,7 @@ __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL); } @@ -1704,7 +1716,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL); } @@ -1715,7 +1727,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL); } @@ -1726,7 +1738,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL); } @@ -1737,7 +1749,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL); } @@ -1748,7 +1760,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL); } @@ -1759,7 +1771,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL); } @@ -1770,7 +1782,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL); } @@ -1781,7 +1793,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); } @@ -1792,7 +1804,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); } @@ -1803,7 +1815,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL); } @@ -1814,7 +1826,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL); } @@ -1825,7 +1837,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL); } @@ -1836,7 +1848,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL); } @@ -1847,7 +1859,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval 0..0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos); } @@ -1862,7 +1874,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(SPI_TypeDef *SPIx) * @arg @ref LL_SPI_RX_FIFO_2PACKET * @arg @ref LL_SPI_RX_FIFO_3PACKET */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL)); } @@ -2189,7 +2201,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL); } @@ -2200,7 +2212,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL); } @@ -2211,7 +2223,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL); } @@ -2222,7 +2234,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL); } @@ -2233,7 +2245,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL); } @@ -2244,7 +2256,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL); } @@ -2255,7 +2267,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL); } @@ -2266,7 +2278,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL); } @@ -2277,7 +2289,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL); } @@ -2288,7 +2300,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL); } @@ -2329,7 +2341,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL); } @@ -2362,11 +2374,31 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL); } +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll TXDR TXDR LL_SPI_DMA_GetTxRegAddr + * @param SPIx SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(const SPI_TypeDef *SPIx) +{ + return (uint32_t) &(SPIx->TXDR); +} +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll RXDR RXDR LL_SPI_DMA_GetRxRegAddr + * @param SPIx SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(const SPI_TypeDef *SPIx) +{ + return (uint32_t) &(SPIx->RXDR); +} /** * @} */ @@ -2381,7 +2413,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval 0..0xFF */ -__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) +__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */ { return (*((__IO uint8_t *)&SPIx->RXDR)); } @@ -2392,9 +2424,14 @@ __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval 0..0xFFFF */ -__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) +__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */ { - return (uint16_t)(READ_REG(SPIx->RXDR)); +#if defined (__GNUC__) + __IO uint16_t *spirxdr = (__IO uint16_t *)(&(SPIx->RXDR)); + return (*spirxdr); +#else + return (*((__IO uint16_t *)&SPIx->RXDR)); +#endif /* __GNUC__ */ } /** @@ -2403,7 +2440,7 @@ __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval 0..0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */ { return (*((__IO uint32_t *)&SPIx->RXDR)); } @@ -2433,7 +2470,7 @@ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR); *spitxdr = TxData; #else - SPIx->TXDR = TxData; + *((__IO uint16_t *)&SPIx->TXDR) = TxData; #endif /* __GNUC__ */ } @@ -2467,7 +2504,7 @@ __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly * @param SPIx SPI Instance * @retval 0..0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->CRCPOLY)); } @@ -2490,7 +2527,7 @@ __STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *SPIx, uint32_t Pattern) * @param SPIx SPI Instance * @retval 0..0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->UDRDR)); } @@ -2501,7 +2538,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval 0..0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->RXCRC)); } @@ -2512,7 +2549,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval 0..0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->TXCRC)); } @@ -2553,7 +2590,7 @@ __STATIC_INLINE void LL_SPI_Disable_SelectedTrigger(SPI_TypeDef *SPIx) * @param SPIx SPI Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabled_SelectedTrigger(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabled_SelectedTrigger(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN) == (SPI_AUTOCR_TRIGEN)) ? 1UL : 0UL); } @@ -2580,7 +2617,7 @@ __STATIC_INLINE void LL_SPI_SetTriggerPolarity(SPI_TypeDef *SPIx, uint32_t Polar * @arg @ref LL_SPI_TRIG_POLARITY_RISING * @arg @ref LL_SPI_TRIG_POLARITY_FALLING */ -__STATIC_INLINE uint32_t LL_SPI_GetTriggerPolarity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTriggerPolarity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGPOL)); } @@ -2651,8 +2688,9 @@ __STATIC_INLINE void LL_SPI_SetSelectedTrigger(SPI_TypeDef *SPIx, uint32_t Trigg * @arg @ref LL_SPI_GRP2_RTC_ALRA_TRG * @arg @ref LL_SPI_GRP2_RTC_WUT_TRG */ -__STATIC_INLINE uint32_t LL_SPI_GetSelectedTrigger(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetSelectedTrigger(const SPI_TypeDef *SPIx) { +#if defined(LL_SPI_TRIG_GRP2) if (IS_LL_SPI_GRP2_INSTANCE(SPIx)) { return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP2)); @@ -2661,6 +2699,9 @@ __STATIC_INLINE uint32_t LL_SPI_GetSelectedTrigger(SPI_TypeDef *SPIx) { return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP1)); } +#else + return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP1)); +#endif /* LL_SPI_TRIG_GRP2 */ } /** @@ -2672,7 +2713,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetSelectedTrigger(SPI_TypeDef *SPIx) * @{ */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx); ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); @@ -2683,6 +2724,9 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); /** * @} */ +/** + * @} + */ #endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) */ @@ -2691,9 +2735,6 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); * @} */ -/** - * @} - */ #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_system.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_system.h index 724c597ca82..6639ad2dbfd 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_system.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_system.h @@ -94,6 +94,19 @@ extern "C" { * @} */ +#if defined(SYSCFG_CCCSR_CS3) +/** @defgroup SYSTEM_LL_EC_CS3 SYSCFG VddHSPI compensation cell Code selection + * @{ + */ +#define LL_SYSCFG_VDDHSPI_CELL_CODE 0U /*VDD HSPI I/Os code from the cell + (available in the SYSCFG_CCVR)*/ +#define LL_SYSCFG_VDDHSPI_REGISTER_CODE SYSCFG_CCCSR_CS3 /*VDD HSPI I/Os code from the SYSCFG compensation + cell code register (SYSCFG_CCCR)*/ +/** + * @} + */ +#endif /* SYSCFG_CCCSR_CS3 */ + /** @defgroup SYSTEM_LL_EC_ERASE_MEMORIES_STATUS SYSCFG MEMORIES ERASE STATUS * @{ */ @@ -111,13 +124,13 @@ extern "C" { * @{ */ -/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS +/** @defgroup SYSTEM_LL_EC_FASTMODEPLUS SYSCFG FASTMODEPLUS * @{ */ -#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ -#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ -#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ -#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +#define LL_SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define LL_SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#define LL_SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define LL_SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ /** * @} */ @@ -186,7 +199,8 @@ extern "C" { */ #define LL_DBGMCU_APB1_GRP2_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP /*!< The I2C4 SMBus timeout is frozen*/ #define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/ -#define LL_DBGMCU_APB1_GRP2_FDCAN_STOP DBGMCU_APB1FZR2_DBG_FDCAN_STOP /*!< The counter clock of FDCAN is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP2_I2C5_STOP DBGMCU_APB1FZR2_DBG_I2C5_STOP /*!< The I2C5 SMBus timeout is frozen*/ +#define LL_DBGMCU_APB1_GRP2_I2C6_STOP DBGMCU_APB1FZR2_DBG_I2C6_STOP /*!< The I2C6 SMBus timeout is frozen*/ /** * @} */ @@ -215,6 +229,39 @@ extern "C" { * @} */ +/** @defgroup SYSTEM_LL_EC_AHB1_GRP1_STOP_IP DBGMCU AHB1 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP DBGMCU_AHB1FZR_DBG_GPDMA0_STOP /*!< The counter clock of GPDMA0 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_STOP /*!< The counter clock of GPDMA1 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP DBGMCU_AHB1FZR_DBG_GPDMA2_STOP /*!< The counter clock of GPDMA2 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP DBGMCU_AHB1FZR_DBG_GPDMA3_STOP /*!< The counter clock of GPDMA3 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP DBGMCU_AHB1FZR_DBG_GPDMA4_STOP /*!< The counter clock of GPDMA4 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP DBGMCU_AHB1FZR_DBG_GPDMA5_STOP /*!< The counter clock of GPDMA5 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP DBGMCU_AHB1FZR_DBG_GPDMA6_STOP /*!< The counter clock of GPDMA6 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP DBGMCU_AHB1FZR_DBG_GPDMA7_STOP /*!< The counter clock of GPDMA7 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP DBGMCU_AHB1FZR_DBG_GPDMA8_STOP /*!< The counter clock of GPDMA8 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP DBGMCU_AHB1FZR_DBG_GPDMA9_STOP /*!< The counter clock of GPDMA9 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP DBGMCU_AHB1FZR_DBG_GPDMA10_STOP /*!< The counter clock of GPDMA10 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP DBGMCU_AHB1FZR_DBG_GPDMA11_STOP /*!< The counter clock of GPDMA11 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP DBGMCU_AHB1FZR_DBG_GPDMA12_STOP /*!< The counter clock of GPDMA12 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP DBGMCU_AHB1FZR_DBG_GPDMA13_STOP /*!< The counter clock of GPDMA13 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP DBGMCU_AHB1FZR_DBG_GPDMA14_STOP /*!< The counter clock of GPDMA14 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP DBGMCU_AHB1FZR_DBG_GPDMA15_STOP /*!< The counter clock of GPDMA15 is stopped when the core is halted*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_AHB3_GRP1_STOP_IP DBGMCU AHB3 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_AHB3_GRP1_LPDMA0_STOP DBGMCU_AHB3FZR_DBG_LPDMA0_STOP /*!< The counter clock of LPDMA0 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB3_GRP1_LPDMA1_STOP DBGMCU_AHB3FZR_DBG_LPDMA1_STOP /*!< The counter clock of LPDMA1 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB3_GRP1_LPDMA2_STOP DBGMCU_AHB3FZR_DBG_LPDMA2_STOP /*!< The counter clock of LPDMA2 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB3_GRP1_LPDMA3_STOP DBGMCU_AHB3FZR_DBG_LPDMA3_STOP /*!< The counter clock of LPDMA3 is stopped when the core is halted*/ +/** + * @} + */ #if defined(VREFBUF) /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE @@ -267,6 +314,30 @@ extern "C" { * @{ */ +/** + * @brief Enable I/O analog switches supplied by VDD. + * @rmtoll SYSCFG_CFGR1 ANASWVDD LL_SYSCFG_EnableAnalogSwitchVdd + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableAnalogSwitchVdd(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); +} + +/** + * @brief Disable I/O analog switches supplied by VDD. + * @note I/O analog switches are supplied by VDDA or booster + * when booster in on. + * Dedicated voltage booster (supplied by VDD) is the recommended + * configuration with low VDDA voltage operation. + * @rmtoll SYSCFG_CFGR1 ANASWVDD LL_SYSCFG_DisableAnalogSwitchVdd + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableAnalogSwitchVdd(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); +} + /** * @brief Enable I/O analog switch voltage booster. * @note When voltage booster is enabled, I/O analog switches are supplied @@ -306,14 +377,13 @@ __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void) } /** - * @brief Enable the I2C fast mode plus driving capability. - * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n - * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus + * @brief Enable the fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR1 PBx_FMP LL_SYSCFG_EnableFastModePlus * @param ConfigFastModePlus This parameter can be a combination of the following values: - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 + * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB8 + * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB9 * @retval None */ __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) @@ -322,14 +392,13 @@ __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) } /** - * @brief Disable the I2C fast mode plus driving capability. - * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n - * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus + * @brief Disable the fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR1 PBx_FMP LL_SYSCFG_DisableFastModePlus * @param ConfigFastModePlus This parameter can be a combination of the following values: - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 + * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB8 + * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB9 * @retval None */ __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) @@ -549,8 +618,8 @@ __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) */ __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) { - return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL - | SYSCFG_CFGR2_ECCL)); + return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | \ + SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL)); } @@ -649,12 +718,34 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationValue(void) return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV2)); } +#if defined(SYSCFG_CCVR_PCV3) +/** + * @brief Get the compensation cell value of the HSPI IO PMOS transistor supplied by VDD + * @rmtoll CCVR PCV3 LL_SYSCFG_GetPMOSVddHSPICompensationValue + * @retval Returned value is the PMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddHSPICompensationValue(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV3)); +} + +/** + * @brief Get the compensation cell value of the HSPI IO NMOS transistor supplied by VDD + * @rmtoll CCVR NCV3 LL_SYSCFG_GetNMOSVddHSPICompensationValue + * @retval Returned value is the NMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddHSPICompensationValue(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV3)); +} +#endif /* SYSCFG_CCVR_PCV3 */ + /** * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDD * @rmtoll CCCR PCC1 LL_SYSCFG_SetPMOSVddCompensationCode * @param PMOSCode PMOS compensation code * This code is applied to the PMOS compensation cell when the CS1 bit of the - * SYSCFG_CMPCR is set + * SYSCFG_CCCSR is set * @retval None */ __STATIC_INLINE void LL_SYSCFG_SetPMOSVddCompensationCode(uint32_t PMOSCode) @@ -677,7 +768,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationCode(void) * @rmtoll CCCR PCC2 LL_SYSCFG_SetPMOSVddIO2CompensationCode * @param PMOSCode PMOS compensation code * This code is applied to the PMOS compensation cell when the CS2 bit of the - * SYSCFG_CMPCR is set + * SYSCFG_CCCSR is set * @retval None */ __STATIC_INLINE void LL_SYSCFG_SetPMOSVddIO2CompensationCode(uint32_t PMOSCode) @@ -696,6 +787,31 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationCode(void) return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC2)); } +#if defined(SYSCFG_CCCR_PCC3) +/** + * @brief Set the compensation cell code of the HSPI IO PMOS transistor supplied by VDD + * @rmtoll CCCR PCC3 LL_SYSCFG_SetPMOSVddHSPICompensationCode + * @param PMOSCode PMOS compensation code + * This code is applied to the PMOS compensation cell when the CS3 bit of the + * SYSCFG_CCCSR is set + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetPMOSVddHSPICompensationCode(uint32_t PMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC3, PMOSCode << SYSCFG_CCCR_PCC3_Pos); +} + +/** + * @brief Get the compensation cell code of the HSPI IO PMOS transistor supplied by VDD + * @rmtoll CCCR PCC3 LL_SYSCFG_GetPMOSVddHSPICompensationCode + * @retval Returned value is the PMOS compensation + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddHSPICompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC3)); +} +#endif /* SYSCFG_CCCR_PCC3 */ + /** * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDD * @rmtoll CCCR PCC2 LL_SYSCFG_SetNMOSVddCompensationCode @@ -725,6 +841,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationCode(void) * @param NMOSCode NMOS compensation code * This code is applied to the NMOS compensation cell when the CS2 bit of the * SYSCFG_CMPCR is set + * Value between 0 and 15 * @retval None */ __STATIC_INLINE void LL_SYSCFG_SetNMOSVddIO2CompensationCode(uint32_t NMOSCode) @@ -743,6 +860,32 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationCode(void) return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC2)); } +#if defined(SYSCFG_CCCR_NCC3) +/** + * @brief Set the compensation cell code of the HSPI IO NMOS transistor supplied by VDD + * @rmtoll CCCR NCC3 LL_SYSCFG_SetNMOSVddHSPICompensationCode + * @param NMOSCode NMOS compensation code + * This code is applied to the NMOS compensation cell when the CS3 bit of the + * SYSCFG_CCCSR is set + * Value between 0 and 15 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetNMOSVddHSPICompensationCode(uint32_t NMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC3, NMOSCode << SYSCFG_CCCR_NCC3_Pos); +} + +/** + * @brief Get the compensation cell code of the HSPI IO NMOS transistor supplied by VDD + * @rmtoll CCCR NCC3 LL_SYSCFG_GetNMOSVddHSPICompensationCode + * @retval Returned value is the NMOS compensation cell code + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddHSPICompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC3)); +} +#endif /* SYSCFG_CCCR_NCC3 */ + /** * @brief Enable the Compensation Cell of GPIO supplied by VDD * @rmtoll CCCSR EN1 LL_SYSCFG_EnableVddCompensationCell @@ -767,9 +910,21 @@ __STATIC_INLINE void LL_SYSCFG_EnableVddIO2CompensationCell(void) SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2); } +#if defined(SYSCFG_CCCSR_EN3) +/** + * @brief Enable the Compensation Cell of HSPI IO supplied by VDD + * @rmtoll CCCSR EN3 LL_SYSCFG_EnableVddHSPICompensationCell + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableVddHSPICompensationCell(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3); +} +#endif /* SYSCFG_CCCSR_EN3 */ + /** * @brief Disable the Compensation Cell of GPIO supplied by VDD - * @rmtoll CCCSR EN1 LL_SYSCFG_EnableVddCompensationCell + * @rmtoll CCCSR EN1 LL_SYSCFG_DisableVddCompensationCell * @note The Vdd compensation cell can be used only when the device supply * voltage ranges from 1.71 to 3.6 V * @retval None @@ -781,7 +936,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableVddCompensationCell(void) /** * @brief Disable the Compensation Cell of GPIO supplied by VDDIO2 - * @rmtoll CCCSR EN2 LL_SYSCFG_EnableVddIOCompensationCell + * @rmtoll CCCSR EN2 LL_SYSCFG_DisableVddIO2CompensationCell * @note The Vdd I/O compensation cell can be used only when the device supply * voltage ranges from 1.08 to 3.6 V * @retval None @@ -791,6 +946,18 @@ __STATIC_INLINE void LL_SYSCFG_DisableVddIO2CompensationCell(void) CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2); } +#if defined(SYSCFG_CCCSR_EN3) +/** + * @brief Disable the Compensation Cell of HSPI IO supplied by VDD + * @rmtoll CCCSR EN3 LL_SYSCFG_DisableVddHSPICompensationCell + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableVddHSPICompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3); +} +#endif /* SYSCFG_CCCSR_EN3 */ + /** * @brief Check if the Compensation Cell of GPIO supplied by VDD is enable * @rmtoll CCCSR EN1 LL_SYSCFG_IsEnabled_VddCompensationCell @@ -811,6 +978,18 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddIO2CompensationCell(void) return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2) == SYSCFG_CCCSR_EN2) ? 1UL : 0UL); } +#if defined(SYSCFG_CCCSR_EN3) +/** + * @brief Check if the Compensation Cell of HSPI IO supplied by VDD is enable + * @rmtoll CCCSR EN3 LL_SYSCFG_IsEnabled_VddHSPICompensationCell + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddHSPICompensationCell(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3) == SYSCFG_CCCSR_EN3) ? 1UL : 0UL); +} +#endif /* SYSCFG_CCCSR_EN3 */ + /** * @brief Get Compensation Cell ready Flag of GPIO supplied by VDD * @rmtoll CCCSR RDY1 LL_SYSCFG_IsActiveFlag_VddCMPCR @@ -823,7 +1002,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddCMPCR(void) /** * @brief Get Compensation Cell ready Flag of GPIO supplied by VDDIO2 - * @rmtoll CCCSR RDY1 LL_SYSCFG_IsActiveFlag_VddIO2CMPCR + * @rmtoll CCCSR RDY2 LL_SYSCFG_IsActiveFlag_VddIO2CMPCR * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddIO2CMPCR(void) @@ -831,6 +1010,17 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddIO2CMPCR(void) return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY2) == (SYSCFG_CCCSR_RDY2)) ? 1UL : 0UL); } +#if defined(SYSCFG_CCCSR_RDY3) +/** + * @brief Get Compensation Cell ready Flag of HSPI IO supplied by VDD + * @rmtoll CCCSR RDY3 LL_SYSCFG_IsActiveFlag_VddHSPICMPCR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddHSPICMPCR(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY3) == (SYSCFG_CCCSR_RDY3)) ? 1UL : 0UL); +} +#endif /* SYSCFG_CCCSR_RDY3 */ /** * @brief Set the compensation cell code selection of GPIO supplied by VDD @@ -860,6 +1050,22 @@ __STATIC_INLINE void LL_SYSCFG_SetVddIO2CellCompensationCode(uint32_t CompCode) SET_BIT(SYSCFG->CCCSR, CompCode); } +#if defined(SYSCFG_CCCSR_CS3) +/** + * @brief Set the compensation cell code selection of HSPI IO supplied by VDD + * @rmtoll CCCSR CS3 LL_SYSCFG_SetVddHSPICellCompensationCode + * @param CompCode: Selects the code to be applied for the VddIO compensation cell + * This parameter can be one of the following values: + * @arg LL_SYSCFG_VDDHSPI_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR) + * @arg LL_SYSCFG_VDDHSPI_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR) + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetVddHSPICellCompensationCode(uint32_t CompCode) +{ + SET_BIT(SYSCFG->CCCSR, CompCode); +} +#endif /* SYSCFG_CCCSR_CS3 */ + /** * @brief Get the compensation cell code selection of GPIO supplied by VDD * @rmtoll CCCSR CS1 LL_SYSCFG_GetVddCellCompensationCode @@ -874,7 +1080,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetVddCellCompensationCode(void) /** * @brief Get the compensation cell code selection of GPIO supplied by VDDIO2 - * @rmtoll CCCSR CS2 LL_SYSCFG_GetVddIOCellCompensationCode + * @rmtoll CCCSR CS2 LL_SYSCFG_GetVddIO2CellCompensationCode * @retval Returned value can be one of the following values: * @arg LL_SYSCFG_VDDIO2_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) * @arg LL_SYSCFG_VDDIO2_REGISTER_CODE: Selected Code is from the SYSCFG compensation @@ -885,6 +1091,20 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetVddIO2CellCompensationCode(void) return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS2)); } +#if defined(SYSCFG_CCCSR_CS3) +/** + * @brief Get the compensation cell code selection of HSPI IO supplied by VDD + * @rmtoll CCCSR CS3 LL_SYSCFG_GetVddHSPICellCompensationCode + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_VDDHSPI_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) + * @arg LL_SYSCFG_VDDHSPI_REGISTER_CODE: Selected Code is from the SYSCFG compensation + cell code register (SYSCFG_CCCR) + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetVddHSPICellCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS3)); +} +#endif /* SYSCFG_CCCSR_CS3 */ /** * @} */ @@ -1046,8 +1266,10 @@ __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP - * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_I2C5_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP2_I2C6_STOP (*) * @retval None + * @note (*) Availability depends on devices. */ __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) { @@ -1068,7 +1290,6 @@ __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP - * @retval None */ __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) @@ -1082,7 +1303,6 @@ __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP - * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP * @retval None */ __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) @@ -1154,6 +1374,90 @@ __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs) CLEAR_BIT(DBGMCU->APB3FZR, Periphs); } +/** + * @brief Freeze AHB1 peripherals + * @rmtoll DBGMCU_AHB1FZ DBG_GPDMAx_STOP LL_DBGMCU_AHB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_AHB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->AHB1FZR, Periphs); +} + +/** + * @brief Unfreeze AHB1 peripherals + * @rmtoll DBGMCU_AHB1FZ DBG_GPDMAx_STOP LL_DBGMCU_AHB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->AHB1FZR, Periphs); +} + +/** + * @brief Freeze AHB3 peripherals + * @rmtoll DBGMCU_AHB3FZ DBG_LPDMAx_STOP LL_DBGMCU_AHB3_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA0_STOP + * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA1_STOP + * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA2_STOP + * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA3_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_AHB3_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->AHB3FZR, Periphs); +} + +/** + * @brief Unfreeze AHB3 peripherals + * @rmtoll DBGMCU_AHB3FZ DBG_LPDMAx_STOP LL_DBGMCU_AHB3_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA0_STOP + * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA1_STOP + * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA2_STOP + * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA3_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_AHB3_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->AHB3FZR, Periphs); +} + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_tim.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_tim.c index 677bef6b297..b5c273904da 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_tim.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_tim.c @@ -208,16 +208,16 @@ /** @defgroup TIM_LL_Private_Functions TIM Private Functions * @{ */ -static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); /** * @} */ @@ -238,7 +238,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: invalid TIMx instance */ -ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx) { ErrorStatus result = SUCCESS; @@ -333,7 +333,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct) { uint32_t tmpcr1; @@ -414,7 +414,7 @@ void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) * - SUCCESS: TIMx output channel is initialized * - ERROR: TIMx output channel is not initialized */ -ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) { ErrorStatus result = ERROR; @@ -475,7 +475,7 @@ void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) * - SUCCESS: TIMx output channel is initialized * - ERROR: TIMx output channel is not initialized */ -ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) { ErrorStatus result = ERROR; @@ -529,7 +529,7 @@ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; @@ -622,7 +622,7 @@ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorI * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) { uint32_t tmpcr2; uint32_t tmpccmr1; @@ -736,7 +736,7 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) * - SUCCESS: Break and Dead Time is initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) { uint32_t tmpbdtr = 0; @@ -761,13 +761,10 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); - if (IS_TIM_ADVANCED_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); - assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); - } + assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); + assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); if (IS_TIM_BKIN2_INSTANCE(TIMx)) { @@ -808,7 +805,7 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; @@ -887,7 +884,7 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; @@ -966,7 +963,7 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr2; uint32_t tmpccer; @@ -1045,7 +1042,7 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr2; uint32_t tmpccer; @@ -1124,7 +1121,7 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr3; uint32_t tmpccer; @@ -1185,7 +1182,7 @@ static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr3; uint32_t tmpccer; @@ -1245,7 +1242,7 @@ static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); @@ -1278,7 +1275,7 @@ static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(TIMx)); @@ -1311,7 +1308,7 @@ static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(TIMx)); @@ -1344,7 +1341,7 @@ static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(TIMx)); diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_tim.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_tim.h index 8b10417bc07..724fd9e2183 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_tim.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_tim.h @@ -946,7 +946,7 @@ typedef struct #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */ #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */ #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */ -#define LL_TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops and is reset) as soon as the trigger becomes low.Both startand stop of +#define LL_TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops and is reset) as soon as the trigger becomes low.Both startand stop of the counter are controlled. */ /** * @} @@ -968,16 +968,16 @@ typedef struct #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ -#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ -#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ -#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ -#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ #define LL_TIM_TS_ITR4 TIM_SMCR_TS_3 /*!< Internal Trigger 4 (ITR4) is used as trigger input */ #define LL_TIM_TS_ITR5 (TIM_SMCR_TS_3 | TIM_SMCR_TS_0) /*!< Internal Trigger 5 (ITR5) is used as trigger input */ #define LL_TIM_TS_ITR6 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1) /*!< Internal Trigger 6 (ITR6) is used as trigger input */ #define LL_TIM_TS_ITR7 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Internal Trigger 7 (ITR7) is used as trigger input */ #define LL_TIM_TS_ITR8 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2) /*!< Internal Trigger 8 (ITR8) is used as trigger input */ #define LL_TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */ +#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ +#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ +#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ +#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ /** * @} */ @@ -1031,15 +1031,22 @@ typedef struct #define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ #define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ #define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ -#define LL_TIM_TIM1_ETRSOURCE_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIK */ +#define LL_TIM_TIM1_ETRSOURCE_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIK */ #define LL_TIM_TIM1_ETRSOURCE_HSI TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */ -#define LL_TIM_TIM1_ETRSOURCE_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIS */ +#define LL_TIM_TIM1_ETRSOURCE_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIS */ +#if defined(ADC2) +#define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ADC2 analog watchdog 2 */ +#define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 3 */ +#endif /* ADC2*/ #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC1 analog watchdog 1 */ #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 2 */ #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC1 analog watchdog 3 */ #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 1 */ #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC4 analog watchdog 2 */ #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 3 */ +#if defined(ADC2) +#define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ADC2 analog watchdog 1 */ +#endif /* ADC2*/ /** * @} */ @@ -1052,11 +1059,22 @@ typedef struct #define LL_TIM_TIM2_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ #define LL_TIM_TIM2_ETRSOURCE_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIK */ #define LL_TIM_TIM2_ETRSOURCE_HSI TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */ -#define LL_TIM_TIM2_ETRSOURCE_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIS */ +#define LL_TIM_TIM2_ETRSOURCE_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIS */ +#if defined(DCMI) && defined(LTDC) +#define LL_TIM_TIM2_ETRSOURCE_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI VSYNC */ +#define LL_TIM_TIM2_ETRSOURCE_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC_VSYNC */ +#endif /* DCMI && LTDC */ #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */ #define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */ #define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to TIM5 ETR */ #define LL_TIM_TIM2_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */ +#if defined(DSI) +#define LL_TIM_TIM2_ETRSOURCE_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to DSI_TE */ +#endif /* DSI */ +#if defined(DCMI) && defined(LTDC) +#define LL_TIM_TIM2_ETRSOURCE_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI HSYNC */ +#define LL_TIM_TIM2_ETRSOURCE_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC HSYNC */ +#endif /* DCMI && LTDC */ /** * @} */ @@ -1069,12 +1087,23 @@ typedef struct #define LL_TIM_TIM3_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ #define LL_TIM_TIM3_ETRSOURCE_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIK */ #define LL_TIM_TIM3_ETRSOURCE_HSI TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */ -#define LL_TIM_TIM3_ETRSOURCE_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIS */ +#define LL_TIM_TIM3_ETRSOURCE_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIS */ +#if defined(DCMI) && defined(LTDC) +#define LL_TIM_TIM3_ETRSOURCE_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI VSYNC */ +#define LL_TIM_TIM3_ETRSOURCE_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC_VSYNC */ +#endif /* DCMI && LTDC */ #define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */ #define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */ +#if defined(DSI) +#define LL_TIM_TIM3_ETRSOURCE_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DSI_TE */ +#endif /* DSI */ #define LL_TIM_TIM3_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 1 */ #define LL_TIM_TIM3_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC1 analog watchdog 2 */ #define LL_TIM_TIM3_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 3 */ +#if defined(DCMI) && defined(LTDC) +#define LL_TIM_TIM3_ETRSOURCE_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI HSYNC */ +#define LL_TIM_TIM3_ETRSOURCE_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC HSYNC */ +#endif /* DCMI && LTDC */ /** * @} */ @@ -1088,8 +1117,24 @@ typedef struct #define LL_TIM_TIM4_ETRSOURCE_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIK */ #define LL_TIM_TIM4_ETRSOURCE_HSI TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */ #define LL_TIM_TIM4_ETRSOURCE_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIS */ +#if defined(DCMI) && defined(LTDC) +#define LL_TIM_TIM4_ETRSOURCE_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI VSYNC */ +#define LL_TIM_TIM4_ETRSOURCE_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC_VSYNC */ +#endif /* DCMI && LTDC */ #define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */ #define LL_TIM_TIM4_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */ +#if defined(DSI) +#define LL_TIM_TIM4_ETRSOURCE_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to DSI_TE */ +#endif /* DSI */ +#if defined(ADC2) +#define LL_TIM_TIM4_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC2 AWD1 */ +#define LL_TIM_TIM4_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ETR input is connected to ADC2 AWD2 */ +#define LL_TIM_TIM4_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC2 AWD3 */ +#endif /* ADC2 */ +#if defined(DCMI) && defined(LTDC) +#define LL_TIM_TIM4_ETRSOURCE_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI HSYNC */ +#define LL_TIM_TIM4_ETRSOURCE_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC HSYNC */ +#endif /* DCMI && LTDC */ /** * @} */ @@ -1103,8 +1148,19 @@ typedef struct #define LL_TIM_TIM5_ETRSOURCE_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIK */ #define LL_TIM_TIM5_ETRSOURCE_HSI TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */ #define LL_TIM_TIM5_ETRSOURCE_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIS */ +#if defined(DCMI) && defined(LTDC) +#define LL_TIM_TIM5_ETRSOURCE_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI VSYNC */ +#define LL_TIM_TIM5_ETRSOURCE_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC_VSYNC */ +#endif /* DCMI && LTDC */ #define LL_TIM_TIM5_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */ #define LL_TIM_TIM5_ETRSOURCE_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM3 ETR */ +#if defined(DSI) +#define LL_TIM_TIM5_ETRSOURCE_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DSI_TE */ +#endif /* DSI */ +#if defined(DCMI) && defined(LTDC) +#define LL_TIM_TIM5_ETRSOURCE_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI HSYNC */ +#define LL_TIM_TIM5_ETRSOURCE_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC HSYNC */ +#endif /* DCMI && LTDC */ /** * @} */ @@ -1117,13 +1173,20 @@ typedef struct #define LL_TIM_TIM8_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ #define LL_TIM_TIM8_ETRSOURCE_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIK */ #define LL_TIM_TIM8_ETRSOURCE_HSI TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */ -#define LL_TIM_TIM8_ETRSOURCE_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIS */ +#define LL_TIM_TIM8_ETRSOURCE_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIS */ +#if defined (ADC2) +#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to ADC2 AWD2 */ +#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC2 AWD3 */ +#endif /* ADC2 */ #define LL_TIM_TIM8_ETRSOURCE_ADC1_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC1 analog watchdog 1 */ #define LL_TIM_TIM8_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 2 */ #define LL_TIM_TIM8_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC1 analog watchdog 3 */ #define LL_TIM_TIM8_ETRSOURCE_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 1 */ #define LL_TIM_TIM8_ETRSOURCE_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC4 analog watchdog 2 */ #define LL_TIM_TIM8_ETRSOURCE_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 3 */ +#if defined (ADC2) +#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to ADC2 AWD1 */ +#endif /* ADC2 */ /** * @} */ @@ -1319,7 +1382,7 @@ typedef struct #define LL_TIM_DMABURST_LENGTH_23TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 23 registers starting from the DMA burst base address */ #define LL_TIM_DMABURST_LENGTH_24TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 24 registers starting from the DMA burst base address */ #define LL_TIM_DMABURST_LENGTH_25TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3) /*!< Transfer is done to 25 registers starting from the DMA burst base address */ -#define LL_TIM_DMABURST_LENGTH_26TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 26 registers starting from the DMA burst base address */ +#define LL_TIM_DMABURST_LENGTH_26TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 26 registers starting from the DMA burst base address */ /** * @} */ @@ -1327,13 +1390,13 @@ typedef struct /** @defgroup TIM_LL_EC_DMABURST_SOURCE DMA Burst Source * @{ */ -#define LL_TIM_DMA_UPDATE 0x00000000U /*!< Transfer source is update event */ -#define LL_TIM_DMA_CC1 TIM_DCR_DBSS_0 /*!< Transfer source is CC1 event */ -#define LL_TIM_DMA_CC2 TIM_DCR_DBSS_1 /*!< Transfer source is CC2 event */ -#define LL_TIM_DMA_CC3 (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) /*!< Transfer source is CC3 event */ -#define LL_TIM_DMA_CC4 TIM_DCR_DBSS_2 /*!< Transfer source is CC4 event */ -#define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0) /*!< Transfer source is COM event */ -#define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1) /*!< Transfer source is trigger event */ +#define LL_TIM_DMA_UPDATE TIM_DCR_DBSS_0 /*!< Transfer source is update event */ +#define LL_TIM_DMA_CC1 TIM_DCR_DBSS_1 /*!< Transfer source is CC1 event */ +#define LL_TIM_DMA_CC2 (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) /*!< Transfer source is CC2 event */ +#define LL_TIM_DMA_CC3 TIM_DCR_DBSS_2 /*!< Transfer source is CC3 event */ +#define LL_TIM_DMA_CC4 (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0) /*!< Transfer source is CC4 event */ +#define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1) /*!< Transfer source is COM event */ +#define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) /*!< Transfer source is trigger event */ /** * @} */ @@ -1575,6 +1638,7 @@ typedef struct /** @endcond */ + /** * @} */ @@ -1607,10 +1671,6 @@ typedef struct * @} */ -/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros - * @{ - */ - /** * @brief HELPER macro retrieving the UIFCPY flag from the counter value. * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); @@ -1655,7 +1715,7 @@ typedef struct * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) */ #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ - (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U) + (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U) /** * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. @@ -1749,11 +1809,6 @@ typedef struct ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) -/** - * @} - */ - - /** * @} */ @@ -1794,7 +1849,7 @@ __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); } @@ -1827,7 +1882,7 @@ __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval Inverted state of bit (0 or 1). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); } @@ -1861,7 +1916,7 @@ __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSo * @arg @ref LL_TIM_UPDATESOURCE_REGULAR * @arg @ref LL_TIM_UPDATESOURCE_COUNTER */ -__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); } @@ -1888,7 +1943,7 @@ __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulse * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE */ -__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); } @@ -1932,7 +1987,7 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN */ -__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) { uint32_t counter_mode; @@ -1974,7 +2029,7 @@ __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); } @@ -2011,7 +2066,7 @@ __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDi * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 */ -__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); } @@ -2040,7 +2095,7 @@ __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) * @param TIMx Timer instance * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) */ -__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CNT)); } @@ -2053,7 +2108,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) * @arg @ref LL_TIM_COUNTERDIRECTION_UP * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN */ -__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); } @@ -2080,7 +2135,7 @@ __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) * @param TIMx Timer instance * @retval Prescaler value between Min_Data=0 and Max_Data=65535 */ -__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->PSC)); } @@ -2112,7 +2167,7 @@ __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload * @param TIMx Timer instance * @retval Auto-reload value */ -__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->ARR)); } @@ -2140,7 +2195,7 @@ __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t Rep * @param TIMx Timer instance * @retval Repetition counter value */ -__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->RCR)); } @@ -2174,7 +2229,7 @@ __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) * @param Counter Counter value * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter) +__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter) { return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); } @@ -2213,7 +2268,7 @@ __STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL); } @@ -2292,7 +2347,7 @@ __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAR * @arg @ref LL_TIM_CCDMAREQUEST_CC * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE */ -__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); } @@ -2404,7 +2459,7 @@ __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channe * @arg @ref LL_TIM_CHANNEL_CH6 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) { return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); } @@ -2537,7 +2592,7 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only) * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2607,7 +2662,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_OCPOLARITY_HIGH * @arg @ref LL_TIM_OCPOLARITY_LOW */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); @@ -2680,7 +2735,7 @@ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_OCIDLESTATE_LOW * @arg @ref LL_TIM_OCIDLESTATE_HIGH */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); @@ -2757,7 +2812,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) * @arg @ref LL_TIM_CHANNEL_CH6 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2833,7 +2888,7 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe * @arg @ref LL_TIM_CHANNEL_CH6 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2918,7 +2973,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) * @arg @ref LL_TIM_CHANNEL_CH6 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -3056,7 +3111,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t Compare * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR1)); } @@ -3073,7 +3128,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR2)); } @@ -3090,7 +3145,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR3)); } @@ -3107,7 +3162,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR4)); } @@ -3121,7 +3176,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); } @@ -3135,7 +3190,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR6)); } @@ -3200,7 +3255,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_ * @arg @ref LL_TIM_PWPRSC_X64 * @arg @ref LL_TIM_PWPRSC_X128 */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC)); } @@ -3229,7 +3284,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWi * @param TIMx Timer instance * @retval Returned value can be between Min_Data=0 and Max_Data=255: */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW)); } @@ -3329,7 +3384,7 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI * @arg @ref LL_TIM_ACTIVEINPUT_TRC */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -3380,7 +3435,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_ICPSC_DIV4 * @arg @ref LL_TIM_ICPSC_DIV8 */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -3455,7 +3510,7 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -3512,7 +3567,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_IC_POLARITY_FALLING * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> @@ -3553,7 +3608,7 @@ __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); } @@ -3570,7 +3625,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR1)); } @@ -3587,7 +3642,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR2)); } @@ -3604,7 +3659,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR3)); } @@ -3621,7 +3676,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR4)); } @@ -3668,7 +3723,7 @@ __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); } @@ -3811,16 +3866,16 @@ __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) * @arg @ref LL_TIM_TS_ITR1 * @arg @ref LL_TIM_TS_ITR2 * @arg @ref LL_TIM_TS_ITR3 - * @arg @ref LL_TIM_TS_TI1F_ED - * @arg @ref LL_TIM_TS_TI1FP1 - * @arg @ref LL_TIM_TS_TI2FP2 - * @arg @ref LL_TIM_TS_ETRF * @arg @ref LL_TIM_TS_ITR4 * @arg @ref LL_TIM_TS_ITR5 * @arg @ref LL_TIM_TS_ITR6 * @arg @ref LL_TIM_TS_ITR7 * @arg @ref LL_TIM_TS_ITR8 * @arg @ref LL_TIM_TS_ITR11 + * @arg @ref LL_TIM_TS_TI1F_ED + * @arg @ref LL_TIM_TS_TI1FP1 + * @arg @ref LL_TIM_TS_TI2FP2 + * @arg @ref LL_TIM_TS_ETRF * @retval None */ __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) @@ -3862,7 +3917,7 @@ __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); } @@ -3924,12 +3979,15 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * @arg @ref LL_TIM_TIM1_ETRSOURCE_MSIK * @arg @ref LL_TIM_TIM1_ETRSOURCE_HSI * @arg @ref LL_TIM_TIM1_ETRSOURCE_MSIS + * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD2 (*) + * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD3 (*) * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 + * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD1 (*) * * TIM2: any combination of ETR_RMP where * @@ -3939,10 +3997,15 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * @arg @ref LL_TIM_TIM2_ETRSOURCE_MSIK * @arg @ref LL_TIM_TIM2_ETRSOURCE_HSI * @arg @ref LL_TIM_TIM2_ETRSOURCE_MSIS + * @arg @ref LL_TIM_TIM2_ETRSOURCE_DCMI_VSYNC (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_LTDC_VSYNC (*) * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR * @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE + * @arg @ref LL_TIM_TIM2_ETRSOURCE_DSI_TE (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_DCMI_HSYNC (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_LTDC_HSYNC (*) * * TIM3: any combination of ETR_RMP where * @@ -3952,11 +4015,16 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * @arg @ref LL_TIM_TIM3_ETRSOURCE_MSIK * @arg @ref LL_TIM_TIM3_ETRSOURCE_HSI * @arg @ref LL_TIM_TIM3_ETRSOURCE_MSIS + * @arg @ref LL_TIM_TIM3_ETRSOURCE_DCMI_VSYNC (*) + * @arg @ref LL_TIM_TIM3_ETRSOURCE_LTDC_VSYNC (*) * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR + * @arg @ref LL_TIM_TIM3_ETRSOURCE_DSI_TE (*) * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC1_AWD1 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC1_AWD2 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC1_AWD3 + * @arg @ref LL_TIM_TIM3_ETRSOURCE_DCMI_HSYNC (*) + * @arg @ref LL_TIM_TIM3_ETRSOURCE_LTDC_HSYNC (*) * * TIM4: any combination of ETR_RMP where * @@ -3966,8 +4034,16 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * @arg @ref LL_TIM_TIM4_ETRSOURCE_MSIK * @arg @ref LL_TIM_TIM4_ETRSOURCE_HSI * @arg @ref LL_TIM_TIM4_ETRSOURCE_MSIS + * @arg @ref LL_TIM_TIM4_ETRSOURCE_DCMI_VSYNC (*) + * @arg @ref LL_TIM_TIM4_ETRSOURCE_LTDC_VSYNC (*) * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR + * @arg @ref LL_TIM_TIM4_ETRSOURCE_DSI_TE (*) + * @arg @ref LL_TIM_TIM4_ETRSOURCE_ADC2_AWD1 (*) + * @arg @ref LL_TIM_TIM4_ETRSOURCE_ADC2_AWD2 (*) + * @arg @ref LL_TIM_TIM4_ETRSOURCE_ADC2_AWD3 (*) + * @arg @ref LL_TIM_TIM4_ETRSOURCE_DCMI_HSYNC (*) + * @arg @ref LL_TIM_TIM4_ETRSOURCE_LTDC_HSYNC (*) * * TIM5: any combination of ETR_RMP where * @@ -3977,8 +4053,13 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * @arg @ref LL_TIM_TIM5_ETRSOURCE_MSIK * @arg @ref LL_TIM_TIM5_ETRSOURCE_HSI * @arg @ref LL_TIM_TIM5_ETRSOURCE_MSIS + * @arg @ref LL_TIM_TIM5_ETRSOURCE_DCMI_VSYNC (*) + * @arg @ref LL_TIM_TIM5_ETRSOURCE_LTDC_VSYNC (*) * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR + * @arg @ref LL_TIM_TIM5_ETRSOURCE_DSI_TE (*) + * @arg @ref LL_TIM_TIM5_ETRSOURCE_DCMI_HSYNC (*) + * @arg @ref LL_TIM_TIM5_ETRSOURCE_LTDC_HSYNC (*) * * TIM8: any combination of ETR_RMP where * @@ -3989,12 +4070,17 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * @arg @ref LL_TIM_TIM8_ETRSOURCE_MSIK * @arg @ref LL_TIM_TIM8_ETRSOURCE_HSI * @arg @ref LL_TIM_TIM8_ETRSOURCE_MSIS + * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (*) + * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (*) * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC1_AWD1 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC1_AWD2 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC1_AWD3 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC4_AWD1 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC4_AWD2 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC4_AWD3 + * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (*) + * + * (*) Value not defined in all devices. \n * @retval None */ __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource) @@ -4036,7 +4122,7 @@ __STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL); } @@ -4067,7 +4153,7 @@ __STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t Prel * @arg @ref LL_TIM_SMSPS_TIMUPDATE * @arg @ref LL_TIM_SMSPS_INDEX */ -__STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS)); } @@ -4335,7 +4421,7 @@ __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); } @@ -4378,7 +4464,7 @@ __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); } @@ -4504,7 +4590,7 @@ __STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); } @@ -4538,7 +4624,7 @@ __STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadT * @param TIMx Timer instance * @retval Returned value can be between Min_Data=0 and Max_Data=255: */ -__STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF)); } @@ -4577,7 +4663,7 @@ __STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL); } @@ -4615,9 +4701,9 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(TIM_TypeDef *TIMx) * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 * @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2 * @arg @ref LL_TIM_DMABURST_BASEADDR_ECR * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL @@ -4710,7 +4796,7 @@ __STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U); } @@ -4743,7 +4829,7 @@ __STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexD * @arg @ref LL_TIM_INDEX_UP * @arg @ref LL_TIM_INDEX_DOWN */ -__STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR)); } @@ -4752,7 +4838,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(TIM_TypeDef *TIMx) * @brief Set index blanking * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides an index input. - * @rmtoll ECR IBLK LL_TIM_SetIndexBlanking + * @rmtoll ECR IBLK LL_TIM_SetIndexblanking * @param TIMx Timer instance * @param Indexblanking This parameter can be one of the following values: * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS @@ -4776,7 +4862,7 @@ __STATIC_INLINE void LL_TIM_SetIndexblanking(TIM_TypeDef *TIMx, uint32_t Indexbl * @arg @ref LL_TIM_INDEX_BLANK_TI3 * @arg @ref LL_TIM_INDEX_BLANK_TI4 */ -__STATIC_INLINE uint32_t LL_TIM_GetIndexblanking(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetIndexblanking(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IBLK)); } @@ -4816,7 +4902,7 @@ __STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL); } @@ -4855,7 +4941,7 @@ __STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t Ind * @arg @ref LL_TIM_INDEX_POSITION_DOWN * @arg @ref LL_TIM_INDEX_POSITION_UP */ -__STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS)); } @@ -5005,7 +5091,7 @@ __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) * @note Only TIM16 and TIM17 support HSE/32 remap * @note The Cut1.x contains a limitation when using HSE/32 as input capture for TIM16 * @note Bug ID 56: On TIM16, the HSE/32 input capture requires the set of HSE32EN bit of TIM17 Option Register - * @rmtoll OR HSE32EN LL_TIM_EnableHSE32 + * @rmtoll OR1 HSE32EN LL_TIM_EnableHSE32 * @param TIMx Timer instance * @retval None */ @@ -5017,7 +5103,7 @@ __STATIC_INLINE void LL_TIM_EnableHSE32(TIM_TypeDef *TIMx) /** * @brief Disable request for HSE/32 clock used for TISEL remap. * @note Only TIM16 and TIM17 support HSE/32 remap - * @rmtoll OR HSE32EN LL_TIM_DisableHSE32 + * @rmtoll OR1 HSE32EN LL_TIM_DisableHSE32 * @param TIMx Timer instance * @retval None */ @@ -5029,11 +5115,11 @@ __STATIC_INLINE void LL_TIM_DisableHSE32(TIM_TypeDef *TIMx) /** * @brief Indicate whether request for HSE/32 clock is enabled. * @note Only TIM16 and TIM17 support HSE/32 remap - * @rmtoll OR HSE32EN LL_TIM_IsEnabledHSE32 + * @rmtoll OR1 HSE32EN LL_TIM_IsEnabledHSE32 * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledHSE32(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledHSE32(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->OR1, TIM_OR1_HSE32EN) == (TIM_OR1_HSE32EN)) ? 1UL : 0UL); } @@ -5088,7 +5174,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); } @@ -5110,7 +5196,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); } @@ -5132,7 +5218,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); } @@ -5154,7 +5240,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); } @@ -5176,7 +5262,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); } @@ -5198,7 +5284,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); } @@ -5220,7 +5306,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); } @@ -5242,7 +5328,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); } @@ -5264,7 +5350,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); } @@ -5286,7 +5372,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); } @@ -5308,7 +5394,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); } @@ -5331,7 +5417,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); } @@ -5354,7 +5440,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); } @@ -5377,7 +5463,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); } @@ -5400,7 +5486,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); } @@ -5422,7 +5508,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); } @@ -5448,7 +5534,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL); } @@ -5474,7 +5560,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL); } @@ -5500,7 +5586,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL); } @@ -5526,7 +5612,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL); } @@ -5565,7 +5651,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); } @@ -5598,7 +5684,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); } @@ -5631,7 +5717,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); } @@ -5664,7 +5750,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); } @@ -5697,7 +5783,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); } @@ -5730,7 +5816,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); } @@ -5763,7 +5849,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); } @@ -5796,7 +5882,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); } @@ -5835,7 +5921,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL); } @@ -5874,7 +5960,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL); } @@ -5913,7 +5999,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL); } @@ -5952,7 +6038,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL); } @@ -5992,7 +6078,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); } @@ -6025,7 +6111,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); } @@ -6058,7 +6144,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); } @@ -6091,7 +6177,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); } @@ -6124,7 +6210,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); } @@ -6157,7 +6243,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); } @@ -6190,7 +6276,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); } @@ -6310,19 +6396,19 @@ __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) * @{ */ -ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx); void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); -ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); -ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); -ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); -ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); -ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_ucpd.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_ucpd.h index bb1a8b67370..5ff7ced25ab 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_ucpd.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_ucpd.h @@ -1801,13 +1801,13 @@ __STATIC_INLINE uint32_t LL_UCPD_ReadRxOrderSet(UCPD_TypeDef const *const UCPDx) /** * @brief Read the Rx paysize - * @rmtoll TX_PAYSZ TXPAYSZ LL_UCPD_ReadRxPaySize + * @rmtoll RX_PAYSZ RXPAYSZ LL_UCPD_ReadRxPaySize * @param UCPDx UCPD Instance * @retval RXPaysize. */ __STATIC_INLINE uint32_t LL_UCPD_ReadRxPaySize(UCPD_TypeDef const *const UCPDx) { - return READ_BIT(UCPDx->TX_PAYSZ, UCPD_RX_PAYSZ_RXPAYSZ); + return READ_BIT(UCPDx->RX_PAYSZ, UCPD_RX_PAYSZ_RXPAYSZ); } /** diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_usart.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_usart.c index da03d03c21b..8f0e93ecd1b 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_usart.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_usart.c @@ -31,7 +31,7 @@ * @{ */ -#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5) +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5) /** @addtogroup USART_LL * @{ @@ -40,6 +40,17 @@ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ +/** @addtogroup USART_LL_Private_Constants + * @{ + */ + +/* Definition of default baudrate value used for USART initialisation */ +#define USART_DEFAULT_BAUDRATE (9600U) + +/** + * @} + */ + /* Private macros ------------------------------------------------------------*/ /** @addtogroup USART_LL_Private_Macros * @{ @@ -125,7 +136,7 @@ * - SUCCESS: USART registers are de-initialized * - ERROR: USART registers are not de-initialized */ -ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx) { ErrorStatus status = SUCCESS; @@ -140,6 +151,7 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) /* Release reset of USART clock */ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1); } +#if defined(USART2) else if (USARTx == USART2) { /* Force reset of USART clock */ @@ -148,6 +160,7 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) /* Release reset of USART clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2); } +#endif /* USART2 */ else if (USARTx == USART3) { /* Force reset of USART clock */ @@ -172,6 +185,16 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) /* Release reset of UART clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5); } +#if defined(USART6) + else if (USARTx == USART6) + { + /* Force reset of USART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART6); + + /* Release reset of USART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART6); + } +#endif /* USART6 */ else { status = ERROR; @@ -194,7 +217,7 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) * - SUCCESS: USART registers are initialized according to USART_InitStruct content * - ERROR: Problem occurred during USART Registers initialization */ -ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct) +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct) { ErrorStatus status = ERROR; uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; @@ -248,10 +271,12 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini { periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE); } +#if defined(USART2) else if (USARTx == USART2) { periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE); } +#endif /* USART2 */ else if (USARTx == USART3) { periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE); @@ -264,6 +289,12 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini { periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART5_CLKSOURCE); } +#if defined(USART6) + else if (USARTx == USART6) + { + periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART6_CLKSOURCE); + } +#endif /* USART6 */ else { /* Nothing to do, as error code is already assigned to ERROR value */ @@ -310,7 +341,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) { /* Set USART_InitStruct fields to default values */ USART_InitStruct->PrescalerValue = LL_USART_PRESCALER_DIV1; - USART_InitStruct->BaudRate = 9600U; + USART_InitStruct->BaudRate = USART_DEFAULT_BAUDRATE; USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B; USART_InitStruct->StopBits = LL_USART_STOPBITS_1; USART_InitStruct->Parity = LL_USART_PARITY_NONE ; @@ -333,7 +364,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) * to USART_ClockInitStruct content * - ERROR: Problem occurred during USART Registers initialization */ -ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct) +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct) { ErrorStatus status = SUCCESS; @@ -411,3 +442,5 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) */ #endif /* USE_FULL_LL_DRIVER */ + + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_usart.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_usart.h index 054b2a92091..90aa03bc12f 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_usart.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_usart.h @@ -31,7 +31,7 @@ extern "C" { * @{ */ -#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5) +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5) /** @defgroup USART_LL USART * @{ @@ -63,6 +63,12 @@ static const uint32_t USART_PRESCALER_TAB[] = */ /* Private constants ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Constants USART Private Constants + * @{ + */ +/** + * @} + */ /* Private macros ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup USART_LL_Private_Macros USART Private Macros @@ -666,7 +672,7 @@ __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); } @@ -705,7 +711,7 @@ __STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); } @@ -744,7 +750,7 @@ __STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 */ -__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); } @@ -783,7 +789,7 @@ __STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 */ -__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); } @@ -854,7 +860,7 @@ __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); } @@ -932,7 +938,7 @@ __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32 * @arg @ref LL_USART_DIRECTION_TX * @arg @ref LL_USART_DIRECTION_TX_RX */ -__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); } @@ -966,7 +972,7 @@ __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) * @arg @ref LL_USART_PARITY_EVEN * @arg @ref LL_USART_PARITY_ODD */ -__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); } @@ -993,7 +999,7 @@ __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Me * @arg @ref LL_USART_WAKEUP_IDLELINE * @arg @ref LL_USART_WAKEUP_ADDRESSMARK */ -__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); } @@ -1024,7 +1030,7 @@ __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataW * @arg @ref LL_USART_DATAWIDTH_8B * @arg @ref LL_USART_DATAWIDTH_9B */ -__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); } @@ -1057,7 +1063,7 @@ __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); } @@ -1084,7 +1090,7 @@ __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t Ov * @arg @ref LL_USART_OVERSAMPLING_16 * @arg @ref LL_USART_OVERSAMPLING_8 */ -__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); } @@ -1116,7 +1122,7 @@ __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint3 * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT */ -__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); } @@ -1147,7 +1153,7 @@ __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t Cloc * @arg @ref LL_USART_PHASE_1EDGE * @arg @ref LL_USART_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); } @@ -1178,7 +1184,7 @@ __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t C * @arg @ref LL_USART_POLARITY_LOW * @arg @ref LL_USART_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); } @@ -1257,7 +1263,7 @@ __STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t Presc * @arg @ref LL_USART_PRESCALER_DIV128 * @arg @ref LL_USART_PRESCALER_DIV256 */ -__STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetPrescaler(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER)); } @@ -1296,7 +1302,7 @@ __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); } @@ -1327,7 +1333,7 @@ __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t * @arg @ref LL_USART_STOPBITS_1_5 * @arg @ref LL_USART_STOPBITS_2 */ -__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); } @@ -1388,7 +1394,7 @@ __STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapCo * @arg @ref LL_USART_TXRX_STANDARD * @arg @ref LL_USART_TXRX_SWAPPED */ -__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); } @@ -1415,7 +1421,7 @@ __STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinI * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED */ -__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); } @@ -1442,7 +1448,7 @@ __STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinI * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED */ -__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); } @@ -1471,7 +1477,7 @@ __STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE */ -__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); } @@ -1502,7 +1508,7 @@ __STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_ * @arg @ref LL_USART_BITORDER_LSBFIRST * @arg @ref LL_USART_BITORDER_MSBFIRST */ -__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); } @@ -1541,7 +1547,7 @@ __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); } @@ -1576,7 +1582,7 @@ __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME */ -__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); } @@ -1609,7 +1615,7 @@ __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); } @@ -1653,7 +1659,7 @@ __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t * @param USARTx USART Instance * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) */ -__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); } @@ -1666,7 +1672,7 @@ __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx) * @arg @ref LL_USART_ADDRESS_DETECT_4B * @arg @ref LL_USART_ADDRESS_DETECT_7B */ -__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); } @@ -1755,7 +1761,7 @@ __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t Hard * @arg @ref LL_USART_HWCONTROL_CTS * @arg @ref LL_USART_HWCONTROL_RTS_CTS */ -__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); } @@ -1788,7 +1794,7 @@ __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); } @@ -1821,7 +1827,7 @@ __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); } @@ -1909,7 +1915,7 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph * @arg @ref LL_USART_OVERSAMPLING_8 * @retval Baud Rate */ -__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling) { uint32_t usartdiv; @@ -1958,7 +1964,7 @@ __STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeo * @param USARTx USART Instance * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF */ -__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO)); } @@ -1981,7 +1987,7 @@ __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t Blo * @param USARTx USART Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); } @@ -2028,7 +2034,7 @@ __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL); } @@ -2059,7 +2065,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t P * @arg @ref LL_USART_IRDA_POWER_NORMAL * @arg @ref LL_USART_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); } @@ -2076,7 +2082,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) { - MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue); + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); } /** @@ -2088,7 +2094,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t P * @param USARTx USART Instance * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) */ -__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); } @@ -2135,7 +2141,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL); } @@ -2174,7 +2180,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL); } @@ -2206,7 +2212,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, * @param USARTx USART Instance * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7) */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); } @@ -2223,7 +2229,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USAR */ __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) { - MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue); + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); } /** @@ -2235,7 +2241,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint3 * @param USARTx USART Instance * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); } @@ -2252,7 +2258,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) { - MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); + MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); } /** @@ -2264,7 +2270,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint3 * @param USARTx USART Instance * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); } @@ -2311,7 +2317,7 @@ __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); } @@ -2357,7 +2363,7 @@ __STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL); } @@ -2399,7 +2405,7 @@ __STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL); } @@ -2438,7 +2444,7 @@ __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint3 * @arg @ref LL_USART_LINBREAK_DETECT_10B * @arg @ref LL_USART_LINBREAK_DETECT_11B */ -__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); } @@ -2477,7 +2483,7 @@ __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL); } @@ -2512,7 +2518,7 @@ __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32 * @param USARTx USART Instance * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 */ -__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); } @@ -2539,7 +2545,7 @@ __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t * @param USARTx USART Instance * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 */ -__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); } @@ -2578,7 +2584,7 @@ __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); } @@ -2609,7 +2615,7 @@ __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_ * @arg @ref LL_USART_DE_POLARITY_HIGH * @arg @ref LL_USART_DE_POLARITY_LOW */ -__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP)); } @@ -2912,7 +2918,7 @@ __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); } @@ -2923,7 +2929,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); } @@ -2934,7 +2940,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); } @@ -2945,7 +2951,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); } @@ -2956,13 +2962,12 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE +#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not @@ -2972,7 +2977,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); } @@ -2983,13 +2988,12 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF +#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not @@ -2999,7 +3003,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); } @@ -3012,7 +3016,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL); } @@ -3025,7 +3029,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); } @@ -3038,7 +3042,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); } @@ -3049,7 +3053,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL); } @@ -3062,7 +3066,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL); } @@ -3075,7 +3079,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL); } @@ -3088,7 +3092,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL); } @@ -3101,7 +3105,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL); } @@ -3112,7 +3116,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); } @@ -3123,7 +3127,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); } @@ -3134,7 +3138,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); } @@ -3145,7 +3149,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); } @@ -3156,7 +3160,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); } @@ -3167,7 +3171,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); } @@ -3180,7 +3184,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); } @@ -3193,7 +3197,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); } @@ -3204,7 +3208,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); } @@ -3217,7 +3221,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); } @@ -3230,7 +3234,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); } @@ -3418,8 +3422,7 @@ __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE +#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt @@ -3445,8 +3448,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF +#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Enable TX Empty and TX FIFO Not Full Interrupt @@ -3622,8 +3624,7 @@ __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE +#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt @@ -3649,8 +3650,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF +#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Disable TX Empty and TX FIFO Not Full Interrupt @@ -3823,13 +3823,12 @@ __STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE +#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled. @@ -3839,7 +3838,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); } @@ -3850,13 +3849,12 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF +#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled @@ -3866,7 +3864,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); } @@ -3877,7 +3875,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); } @@ -3888,7 +3886,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); } @@ -3899,7 +3897,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL); } @@ -3912,7 +3910,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL); } @@ -3925,7 +3923,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); } @@ -3938,7 +3936,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); } @@ -3951,7 +3949,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL); } @@ -3962,7 +3960,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); } @@ -3975,7 +3973,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); } @@ -3988,7 +3986,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); } @@ -4001,7 +3999,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); } @@ -4014,7 +4012,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); } @@ -4055,7 +4053,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); } @@ -4088,7 +4086,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); } @@ -4121,7 +4119,7 @@ __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); } @@ -4136,7 +4134,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction) +__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction) { uint32_t data_reg_addr; @@ -4168,7 +4166,7 @@ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t * @param USARTx USART Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) +__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) { return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU); } @@ -4179,7 +4177,7 @@ __STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval Value between Min_Data=0x00 and Max_Data=0x1FF */ -__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx) +__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) { return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); } @@ -4315,7 +4313,7 @@ __STATIC_INLINE void LL_USART_Disable_SelectedTrigger(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabled_SelectedTrigger(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabled_SelectedTrigger(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGEN) == (USART_AUTOCR_TRIGEN)) ? 1UL : 0UL); } @@ -4348,7 +4346,7 @@ __STATIC_INLINE void LL_USART_Disable_AutonomousSendIdleFrame(USART_TypeDef *USA * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabled_AutonomousSendIdleFrame(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabled_AutonomousSendIdleFrame(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->AUTOCR, USART_AUTOCR_IDLEDIS) == (USART_AUTOCR_IDLEDIS)) ? 0UL : 1UL); } @@ -4371,7 +4369,7 @@ __STATIC_INLINE void LL_USART_SetNbTxData(USART_TypeDef *USARTx, uint32_t Nbdata * @param USARTx USART Instance * @retval Returned value can be a value between 0 and 0xFFFF */ -__STATIC_INLINE uint32_t LL_USART_GetNbTxData(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetNbTxData(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TDN)); } @@ -4398,7 +4396,7 @@ __STATIC_INLINE void LL_USART_SetTriggerPolarity(USART_TypeDef *USARTx, uint32_t * @arg @ref LL_USART_TRIG_POLARITY_RISING * @arg @ref LL_USART_TRIG_POLARITY_FALLING */ -__STATIC_INLINE uint32_t LL_USART_GetTriggerPolarity(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTriggerPolarity(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGPOL)); } @@ -4445,7 +4443,7 @@ __STATIC_INLINE void LL_USART_SetSelectedTrigger(USART_TypeDef *USARTx, uint32_t * @arg @ref LL_USART_RTC_ALRA_TRG * @arg @ref LL_USART_RTC_WUT_TRG */ -__STATIC_INLINE uint32_t LL_USART_GetSelectedTrigger(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetSelectedTrigger(const USART_TypeDef *USARTx) { return (uint32_t)((READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGSEL) >> USART_AUTOCR_TRIGSEL_Pos)); } @@ -4458,10 +4456,10 @@ __STATIC_INLINE uint32_t LL_USART_GetSelectedTrigger(USART_TypeDef *USARTx) /** @defgroup USART_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx); -ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct); +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx); +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct); void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); -ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct); void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); /** * @} @@ -4487,3 +4485,4 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitS #endif #endif /* STM32U5xx_LL_USART_H */ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_usb.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_usb.c index 5c341eb2a92..154174e96df 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_usb.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_usb.c @@ -27,7 +27,7 @@ ##### How to use this driver ##### ============================================================================== [..] - (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure. + (#) Fill parameters of Init structure in USB_CfgTypeDef structure. (#) Call USB_CoreInit() API to initialize the USB Core peripheral. @@ -46,7 +46,7 @@ */ #if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -83,15 +83,11 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { HAL_StatusTypeDef ret; - #if defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) { /* Init The UTMI Interface */ - USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); - - /* Select vbus source */ - USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS); } /* Reset after a PHY select */ @@ -301,6 +297,11 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf USBx->DIEPTXF[i] = 0U; } +#if defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) + /* Disable USB PHY pulldown resistors */ + USBx->GCCFG &= ~USB_OTG_GCCFG_PULLDOWNEN; +#endif /* defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) */ + /* VBUS Sensing setup */ if (cfg.vbus_sensing_enable == 0U) { @@ -333,9 +334,6 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf /* Restart the Phy Clock */ USBx_PCGCCTL = 0U; - /* Device mode configuration */ - USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; - #if defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) { @@ -451,7 +449,7 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf } /** - * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO + * @brief USB_FlushTxFifo Flush a Tx FIFO * @param USBx Selected device * @param num FIFO number * This parameter can be a value from 1 to 15 @@ -460,13 +458,28 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf */ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { - uint32_t count = 0U; + __IO uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > 200000U) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + /* Flush TX Fifo */ + count = 0U; USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); do { - if (++count > 200000U) + count++; + + if (count > 200000U) { return HAL_TIMEOUT; } @@ -476,19 +489,34 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) } /** - * @brief USB_FlushRxFifo : Flush Rx FIFO + * @brief USB_FlushRxFifo Flush Rx FIFO * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { - uint32_t count = 0; + __IO uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > 200000U) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + /* Flush RX Fifo */ + count = 0U; USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; do { - if (++count > 200000U) + count++; + + if (count > 200000U) { return HAL_TIMEOUT; } @@ -744,8 +772,21 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef */ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & - (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + + if (epnum == 0U) + { + if (ep->xfer_len > ep->maxpacket) + { + ep->xfer_len = ep->maxpacket; + } + + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & + (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); @@ -815,16 +856,34 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - if (ep->xfer_len == 0U) + if (epnum == 0U) { - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); + if (ep->xfer_len > 0U) + { + ep->xfer_len = ep->maxpacket; + } + + /* Store transfer size, for EP0 this is equal to endpoint max packet size */ + ep->xfer_size = ep->maxpacket; + + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); } else { - pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); - USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); - USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt); + if (ep->xfer_len == 0U) + { + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + ep->xfer_size = ep->maxpacket * pktcnt; + + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; + } } if (dma == 1U) @@ -853,103 +912,64 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef return HAL_OK; } + /** - * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0 - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @param dma USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval HAL status - */ -HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) + * @brief USB_EPStoptXfer Stop transfer on an EP + * @param USBx usb device instance + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { + __IO uint32_t count = 0U; + HAL_StatusTypeDef ret = HAL_OK; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; /* IN endpoint */ if (ep->is_in == 1U) { - /* Zero Length Packet? */ - if (ep->xfer_len == 0U) - { - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - } - else + /* EP enable, IN data in FIFO */ + if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) { - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - - if (ep->xfer_len > ep->maxpacket) - { - ep->xfer_len = ep->maxpacket; - } - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - } + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK); + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS); - if (dma == 1U) - { - if ((uint32_t)ep->dma_addr != 0U) + do { - USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); - } - - /* EP enable, IN data in FIFO */ - USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); - } - else - { - /* EP enable, IN data in FIFO */ - USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + count++; - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0U) - { - USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); - } + if (count > 10000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); } } else /* OUT endpoint */ { - /* Program the transfer size and packet count as follows: - * pktcnt = N - * xfersize = N * maxpacket - */ - USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); - USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - - if (ep->xfer_len > 0U) + if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) { - ep->xfer_len = ep->maxpacket; - } + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); - - if (dma == 1U) - { - if ((uint32_t)ep->xfer_buff != 0U) + do { - USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); - } - } + count++; - /* EP enable */ - USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + if (count > 10000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); + } } - return HAL_OK; + return ret; } + /** * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated * with the EP/channel @@ -1137,7 +1157,7 @@ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) * This parameter can be a value from 0 to 255 * @retval HAL status */ -HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address) +HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1152,7 +1172,7 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t addres * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1169,7 +1189,7 @@ HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1184,9 +1204,9 @@ HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_ReadInterrupts: return the global USB interrupt status * @param USBx Selected device - * @retval HAL status + * @retval USB Global Interrupt status */ -uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx) { uint32_t tmpreg; @@ -1196,10 +1216,27 @@ uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx) return tmpreg; } +/** + * @brief USB_ReadChInterrupts: return USB channel interrupt status + * @param USBx Selected device + * @param chnum Channel number + * @retval USB Channel Interrupt status + */ +uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_HC(chnum)->HCINT; + tmpreg &= USBx_HC(chnum)->HCINTMSK; + + return tmpreg; +} + /** * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status * @param USBx Selected device - * @retval HAL status + * @retval USB Device OUT EP interrupt status */ uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) { @@ -1215,7 +1252,7 @@ uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status * @param USBx Selected device - * @retval HAL status + * @retval USB Device IN EP interrupt status */ uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx) { @@ -1276,7 +1313,7 @@ uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) */ void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) { - USBx->GINTSTS |= interrupt; + USBx->GINTSTS &= interrupt; } /** @@ -1297,7 +1334,7 @@ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1354,12 +1391,14 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uin */ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { - uint32_t count = 0U; + __IO uint32_t count = 0U; /* Wait for AHB master IDLE state. */ do { - if (++count > 200000U) + count++; + + if (count > 200000U) { return HAL_TIMEOUT; } @@ -1371,7 +1410,9 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) do { - if (++count > 200000U) + count++; + + if (count > 200000U) { return HAL_TIMEOUT; } @@ -1390,9 +1431,15 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { + HAL_StatusTypeDef ret = HAL_OK; uint32_t USBx_BASE = (uint32_t)USBx; uint32_t i; +#if defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) + /* Enable USB PHY pulldown resistors */ + USBx->GCCFG |= USB_OTG_GCCFG_PULLDOWNEN; +#endif /* defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) */ + /* Restart the Phy Clock */ USBx_PCGCCTL = 0U; @@ -1406,6 +1453,10 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c #if defined (STM32U575xx) || defined (STM32U585xx) /* Disable Battery chargin detector */ USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); +#else + /* Disable Battery chargin detector */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); + USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); #endif /* defined (STM32U575xx) || defined (STM32U585xx) */ if ((USBx->CID & (0x1U << 14)) != 0U) @@ -1428,13 +1479,20 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c } /* Make sure the FIFOs are flushed. */ - (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */ - (void)USB_FlushRxFifo(USBx); + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } /* Clear all pending HC Interrupts */ for (i = 0U; i < cfg.Host_channels; i++) { - USBx_HC(i)->HCINT = 0xFFFFFFFFU; + USBx_HC(i)->HCINT = CLEAR_INTERRUPT_MASK; USBx_HC(i)->HCINTMSK = 0U; } @@ -1442,7 +1500,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USBx->GINTMSK = 0U; /* Clear any pending interrupts */ - USBx->GINTSTS = 0xFFFFFFFFU; + USBx->GINTSTS = CLEAR_INTERRUPT_MASK; if ((USBx->CID & (0x1U << 14)) != 0U) { @@ -1470,7 +1528,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); - return HAL_OK; + return ret; } /** @@ -1492,15 +1550,15 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) if (freq == HCFG_48_MHZ) { - USBx_HOST->HFIR = 48000U; + USBx_HOST->HFIR = HFIR_48_MHZ; } else if (freq == HCFG_6_MHZ) { - USBx_HOST->HFIR = 6000U; + USBx_HOST->HFIR = HFIR_6_MHZ; } else { - /* ... */ + return HAL_ERROR; } return HAL_OK; @@ -1626,7 +1684,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint32_t HostCoreSpeed; /* Clear old interrupt conditions for this host channel. */ - USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU; + USBx_HC((uint32_t)ch_num)->HCINT = CLEAR_INTERRUPT_MASK; /* Enable channel interrupts required for this transfer. */ switch (ep_type) @@ -1687,6 +1745,12 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, break; } + /* Clear Hub Start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = 0U; + + /* Enable host channel Halt interrupt */ + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM; + /* Enable the top level host channel interrupt. */ USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); @@ -1718,11 +1782,12 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | - ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed; + ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | + USB_OTG_HCCHAR_MC_0 | HCcharEpDir | HCcharLowSpeed; - if (ep_type == EP_TYPE_INTR) + if ((ep_type == EP_TYPE_INTR) || (ep_type == EP_TYPE_ISOC)) { - USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; + USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; } return ret; @@ -1746,7 +1811,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe uint8_t is_oddframe; uint16_t len_words; uint16_t num_packets; - uint16_t max_hc_pkt_count = 256U; + uint16_t max_hc_pkt_count = HC_MAX_PKT_CNT; if (((USBx->CID & (0x1U << 14)) != 0U) && (hc->speed == USBH_HS_SPEED)) { @@ -1766,33 +1831,91 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe } - /* Compute the expected number of packets associated to the transfer */ - if (hc->xfer_len > 0U) + if (hc->do_ssplit == 1U) { - num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); + /* Set number of packet to 1 for Split transaction */ + num_packets = 1U; - if (num_packets > max_hc_pkt_count) + if (hc->ep_is_in != 0U) { - num_packets = max_hc_pkt_count; hc->XferSize = (uint32_t)num_packets * hc->max_packet; } - } - else - { - num_packets = 1U; - } + else + { + if (hc->ep_type == EP_TYPE_ISOC) + { + if (hc->xfer_len > ISO_SPLT_MPS) + { + /* Isochrone Max Packet Size for Split mode */ + hc->XferSize = hc->max_packet; + hc->xfer_len = hc->XferSize; - /* - * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of - * max_packet size. - */ - if (hc->ep_is_in != 0U) - { - hc->XferSize = (uint32_t)num_packets * hc->max_packet; + if ((hc->iso_splt_xactPos == HCSPLT_BEGIN) || (hc->iso_splt_xactPos == HCSPLT_MIDDLE)) + { + hc->iso_splt_xactPos = HCSPLT_MIDDLE; + } + else + { + hc->iso_splt_xactPos = HCSPLT_BEGIN; + } + } + else + { + hc->XferSize = hc->xfer_len; + + if ((hc->iso_splt_xactPos != HCSPLT_BEGIN) && (hc->iso_splt_xactPos != HCSPLT_MIDDLE)) + { + hc->iso_splt_xactPos = HCSPLT_FULL; + } + else + { + hc->iso_splt_xactPos = HCSPLT_END; + } + } + } + else + { + if ((dma == 1U) && (hc->xfer_len > hc->max_packet)) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + hc->XferSize = hc->xfer_len; + } + } + } } else { - hc->XferSize = hc->xfer_len; + /* Compute the expected number of packets associated to the transfer */ + if (hc->xfer_len > 0U) + { + num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); + + if (num_packets > max_hc_pkt_count) + { + num_packets = max_hc_pkt_count; + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + } + else + { + num_packets = 1U; + } + + /* + * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of + * max_packet size. + */ + if (hc->ep_is_in != 0U) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + hc->XferSize = hc->xfer_len; + } } /* Initialize the HCTSIZn register */ @@ -1810,6 +1933,65 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; + if (hc->do_ssplit == 1U) + { + /* Set Hub start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = ((uint32_t)hc->hub_addr << USB_OTG_HCSPLT_HUBADDR_Pos) | + (uint32_t)hc->hub_port_nbr | USB_OTG_HCSPLT_SPLITEN; + + /* unmask ack & nyet for IN/OUT transactions */ + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_NYET); + + if ((hc->do_csplit == 1U) && (hc->ep_is_in == 0U)) + { + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET; + } + + if (((hc->ep_type == EP_TYPE_ISOC) || (hc->ep_type == EP_TYPE_INTR)) && + (hc->do_csplit == 1U) && (hc->ep_is_in == 1U)) + { + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; + } + + /* Position management for iso out transaction on split mode */ + if ((hc->ep_type == EP_TYPE_ISOC) && (hc->ep_is_in == 0U)) + { + /* Set data payload position */ + switch (hc->iso_splt_xactPos) + { + case HCSPLT_BEGIN: + /* First data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_1; + break; + + case HCSPLT_MIDDLE: + /* Middle data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_Pos; + break; + + case HCSPLT_END: + /* End data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_0; + break; + + case HCSPLT_FULL: + /* Entire data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS; + break; + + default: + break; + } + } + } + else + { + /* Clear Hub Start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = 0U; + } + /* Set host channel enable */ tmpreg = USBx_HC(ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; @@ -1831,7 +2013,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe return HAL_OK; } - if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U)) + if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U) && (hc->do_csplit == 0U)) { switch (hc->ep_type) { @@ -1895,12 +2077,17 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t hcnum = (uint32_t)hc_num; - uint32_t count = 0U; + __IO uint32_t count = 0U; uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; + uint32_t SplitEna = (USBx_HC(hcnum)->HCSPLT & USB_OTG_HCSPLT_SPLITEN) >> 31; - if (((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && - (ChannelEna == 0U)) + /* In buffer DMA, Channel disable must not be programmed for non-split periodic channels. + At the end of the next uframe/frame (in the worst case), the core generates a channel halted + and disables the channel automatically. */ + + if ((((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && (SplitEna == 0U)) && + ((ChannelEna == 0U) || (((HcEpType == HCCHAR_ISOC) || (HcEpType == HCCHAR_INTR))))) { return HAL_OK; } @@ -1916,10 +2103,11 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; do { - if (++count > 1000U) + count++; + + if (count > 1000U) { break; } @@ -1930,6 +2118,10 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; } } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } } else { @@ -1939,10 +2131,11 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; do { - if (++count > 1000U) + count++; + + if (count > 1000U) { break; } @@ -1990,18 +2183,26 @@ HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) */ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) { + HAL_StatusTypeDef ret = HAL_OK; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t count = 0U; + __IO uint32_t count = 0U; uint32_t value; uint32_t i; (void)USB_DisableGlobalInt(USBx); - /* Flush FIFO */ - (void)USB_FlushTxFifo(USBx, 0x10U); - (void)USB_FlushRxFifo(USBx); - - /* Flush out any leftover queued requests. */ + /* Flush USB FIFO */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } + + /* Flush out any leftover queued requests. */ for (i = 0U; i <= 15U; i++) { value = USBx_HC(i)->HCCHAR; @@ -2022,7 +2223,9 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) do { - if (++count > 1000U) + count++; + + if (count > 1000U) { break; } @@ -2030,12 +2233,12 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) } /* Clear any pending Host interrupts */ - USBx_HOST->HAINT = 0xFFFFFFFFU; - USBx->GINTSTS = 0xFFFFFFFFU; + USBx_HOST->HAINT = CLEAR_INTERRUPT_MASK; + USBx->GINTSTS = CLEAR_INTERRUPT_MASK; (void)USB_EnableGlobalInt(USBx); - return HAL_OK; + return ret; } /** @@ -2072,15 +2275,1356 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) } #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) +static HAL_StatusTypeDef USB_CoreReset(USB_DRD_TypeDef *USBx); +#if (USE_USB_DOUBLE_BUFFER == 1U) +static HAL_StatusTypeDef USB_HC_BULK_DB_StartXfer(USB_DRD_TypeDef *USBx, + USB_DRD_HCTypeDef *hc, + uint32_t ch_reg, + uint32_t *len); + +static HAL_StatusTypeDef USB_HC_ISO_DB_StartXfer(USB_DRD_TypeDef *USBx, + USB_DRD_HCTypeDef *hc, + uint32_t len); +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ /** - * @} + * @brief Reset the USB Core (needed after USB clock settings change) + * @param USBx Selected device + * @retval HAL status */ +static HAL_StatusTypeDef USB_CoreReset(USB_DRD_TypeDef *USBx) +{ + /* Disable Host Mode */ + USBx->CNTR &= ~USB_CNTR_HOST; + + /* Force Reset IP */ + USBx->CNTR |= USB_CNTR_USBRST; + + return HAL_OK; +} /** - * @} + * @brief Initializes the USB Core + * @param USBx USB Instance + * @param cfg pointer to a USB_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +HAL_StatusTypeDef USB_CoreInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret; + UNUSED(cfg); + + if (USBx == NULL) + { + return HAL_ERROR; + } + + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + + /* Clear pending interrupts */ + USBx->ISTR = 0U; + + return ret; +} + +/** + * @brief USB_EnableGlobalInt + * Enables the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_EnableGlobalInt(USB_DRD_TypeDef *USBx) +{ + uint32_t winterruptmask; + + /* Clear pending interrupts */ + USBx->ISTR = 0U; + + /* Set winterruptmask variable */ + winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | + USB_CNTR_SUSPM | USB_CNTR_ERRM | + USB_CNTR_SOFM | USB_CNTR_ESOFM | + USB_CNTR_RESETM | USB_CNTR_L1REQM; + + /* Set interrupt mask */ + USBx->CNTR = winterruptmask; + + return HAL_OK; +} + +/** + * @brief USB_DisableGlobalInt + * Disable the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DisableGlobalInt(USB_DRD_TypeDef *USBx) +{ + uint32_t winterruptmask; + + /* Set winterruptmask variable */ + winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | + USB_CNTR_SUSPM | USB_CNTR_ERRM | + USB_CNTR_SOFM | USB_CNTR_ESOFM | + USB_CNTR_RESETM | USB_CNTR_L1REQM; + + /* Clear interrupt mask */ + USBx->CNTR &= ~winterruptmask; + + return HAL_OK; +} + +/** + * @brief USB_SetCurrentMode Set functional mode + * @param USBx Selected device + * @param mode current core mode + * This parameter can be one of the these values: + * @arg USB_DEVICE_MODE Peripheral mode + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetCurrentMode(USB_DRD_TypeDef *USBx, USB_DRD_ModeTypeDef mode) +{ + if (mode == USB_DEVICE_MODE) + { + USBx->CNTR &= ~USB_CNTR_HOST; + } + else if (mode == USB_HOST_MODE) + { + USBx->CNTR |= USB_CNTR_HOST; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief USB_DevInit Initializes the USB controller registers + * for device mode + * @param USBx Selected device + * @param cfg pointer to a USB_DRD_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(cfg); + + /* Force Reset */ + USBx->CNTR = USB_CNTR_USBRST; + + /* Release Reset */ + USBx->CNTR &= ~USB_CNTR_USBRST; + + /* Set the Device Mode */ + ret = USB_SetCurrentMode(USBx, USB_DEVICE_MODE); + + /* Clear pending interrupts */ + USBx->ISTR = 0U; + + return ret; +} + +#if defined (HAL_PCD_MODULE_ENABLED) +/** + * @brief Activate and configure an endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t wEpRegVal; + + wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK; + + /* initialize Endpoint */ + switch (ep->type) + { + case EP_TYPE_CTRL: + wEpRegVal |= USB_EP_CONTROL; + break; + + case EP_TYPE_BULK: + wEpRegVal |= USB_EP_BULK; + break; + + case EP_TYPE_INTR: + wEpRegVal |= USB_EP_INTERRUPT; + break; + + case EP_TYPE_ISOC: + wEpRegVal |= USB_EP_ISOCHRONOUS; + break; + + default: + ret = HAL_ERROR; + break; + } + + PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_VTRX | USB_EP_VTTX)); + + PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num); + + if (ep->doublebuffer == 0U) + { + if (ep->is_in != 0U) + { + /*Set the endpoint Transmit buffer address */ + PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress); + PCD_CLEAR_TX_DTOG(USBx, ep->num); + + if (ep->type != EP_TYPE_ISOC) + { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + } + else + { + /* Configure TX Endpoint to disabled state */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + } + } + else + { + /* Set the endpoint Receive buffer address */ + PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress); + + /* Set the endpoint Receive buffer counter */ + PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket); + PCD_CLEAR_RX_DTOG(USBx, ep->num); + + if (ep->num == 0U) + { + /* Configure VALID status for EP0 */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } + else + { + /* Configure NAK status for OUT Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK); + } + } + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + /* Double Buffer */ + else + { + if (ep->type == EP_TYPE_BULK) + { + /* Set bulk endpoint as double buffered */ + PCD_SET_BULK_EP_DBUF(USBx, ep->num); + } + else + { + /* Set the ISOC endpoint in double buffer mode */ + PCD_CLEAR_EP_KIND(USBx, ep->num); + } + + /* Set buffer address for double buffered mode */ + PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1); + + if (ep->is_in == 0U) + { + /* Clear the data toggle bits for the endpoint IN/OUT */ + PCD_CLEAR_RX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); + + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + } + else + { + /* Clear the data toggle bits for the endpoint IN/OUT */ + PCD_CLEAR_RX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); + + if (ep->type != EP_TYPE_ISOC) + { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + } + else + { + /* Configure TX Endpoint to disabled state */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + } + + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); + } + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + return ret; +} + +/** + * @brief De-activate and de-initialize an endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeactivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) +{ + if (ep->doublebuffer == 0U) + { + if (ep->is_in != 0U) + { + PCD_CLEAR_TX_DTOG(USBx, ep->num); + + /* Configure DISABLE status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + } + + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + + /* Configure DISABLE status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); + } + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + /* Double Buffer */ + else + { + if (ep->is_in == 0U) + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); + + /* Reset value of the data toggle bits for the endpoint out*/ + PCD_TX_DTOG(USBx, ep->num); + + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + } + else + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); + PCD_RX_DTOG(USBx, ep->num); + + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); + } + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + return HAL_OK; +} + +/** + * @brief USB_EPStartXfer setup and starts a transfer over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) +{ + uint32_t len; +#if (USE_USB_DOUBLE_BUFFER == 1U) + uint16_t pmabuffer; + uint16_t wEPVal; +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /*Multi packet transfer*/ + if (ep->xfer_len > ep->maxpacket) + { + len = ep->maxpacket; + } + else + { + len = ep->xfer_len; + } + + /* configure and validate Tx endpoint */ + if (ep->doublebuffer == 0U) + { + USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len); + PCD_SET_EP_TX_CNT(USBx, ep->num, len); + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + else + { + /* double buffer bulk management */ + if (ep->type == EP_TYPE_BULK) + { + if (ep->xfer_len_db > ep->maxpacket) + { + /* enable double buffer */ + PCD_SET_BULK_EP_DBUF(USBx, ep->num); + + /* each Time to write in PMA xfer_len_db will */ + ep->xfer_len_db -= len; + + /* Fill the two first buffer in the Buffer0 & Buffer1 */ + if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) + { + /* Set the Double buffer counter for pmabuffer1 */ + PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr1; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + ep->xfer_buff += len; + + if (ep->xfer_len_db > ep->maxpacket) + { + ep->xfer_len_db -= len; + } + else + { + len = ep->xfer_len_db; + ep->xfer_len_db = 0U; + } + + /* Set the Double buffer counter for pmabuffer0 */ + PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr0; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } + else + { + /* Set the Double buffer counter for pmabuffer0 */ + PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr0; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + ep->xfer_buff += len; + + if (ep->xfer_len_db > ep->maxpacket) + { + ep->xfer_len_db -= len; + } + else + { + len = ep->xfer_len_db; + ep->xfer_len_db = 0U; + } + + /* Set the Double buffer counter for pmabuffer1 */ + PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr1; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } + } + /* auto Switch to single buffer mode when transfer xfer_len_db; + + /* disable double buffer mode for Bulk endpoint */ + PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num); + + /* Set Tx count with nbre of byte to be transmitted */ + PCD_SET_EP_TX_CNT(USBx, ep->num, len); + pmabuffer = ep->pmaaddr0; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } + } + else /* manage isochronous double buffer IN mode */ + { + /* each Time to write in PMA xfer_len_db will */ + ep->xfer_len_db -= len; + + /* Fill the data buffer */ + if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) + { + /* Set the Double buffer counter for pmabuffer1 */ + PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr1; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } + else + { + /* Set the Double buffer counter for pmabuffer0 */ + PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr0; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } + } + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); + } + else /* OUT endpoint */ + { + if (ep->doublebuffer == 0U) + { + /* Multi packet transfer */ + if (ep->xfer_len > ep->maxpacket) + { + len = ep->maxpacket; + ep->xfer_len -= len; + } + else + { + len = ep->xfer_len; + ep->xfer_len = 0U; + } + /* configure and validate Rx endpoint */ + PCD_SET_EP_RX_CNT(USBx, ep->num, len); + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + else + { + /* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */ + /* Set the Double buffer counter */ + if (ep->type == EP_TYPE_BULK) + { + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); + + /* Coming from ISR */ + if (ep->xfer_count != 0U) + { + /* update last value to check if there is blocking state */ + wEPVal = (uint16_t)PCD_GET_ENDPOINT(USBx, ep->num); + + /*Blocking State */ + if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || + (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) + { + PCD_FREE_USER_BUFFER(USBx, ep->num, 0U); + } + } + } + /* iso out double */ + else if (ep->type == EP_TYPE_ISOC) + { + /* Multi packet transfer */ + if (ep->xfer_len > ep->maxpacket) + { + len = ep->maxpacket; + ep->xfer_len -= len; + } + else + { + len = ep->xfer_len; + ep->xfer_len = 0U; + } + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); + } + else + { + return HAL_ERROR; + } + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } + + return HAL_OK; +} + + +/** + * @brief USB_EPSetStall set a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPSetStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) +{ + if (ep->is_in != 0U) + { + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL); + } + else + { + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL); + } + + return HAL_OK; +} + +/** + * @brief USB_EPClearStall Clear a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) +{ + if (ep->doublebuffer == 0U) + { + if (ep->is_in != 0U) + { + PCD_CLEAR_TX_DTOG(USBx, ep->num); + + if (ep->type != EP_TYPE_ISOC) + { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + } + } + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + + /* Configure VALID status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } + } + + return HAL_OK; +} + +/** + * @brief USB_EPStoptXfer Stop transfer on an EP + * @param USBx usb device instance + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStopXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) +{ + /* IN endpoint */ + if (ep->is_in == 1U) + { + if (ep->doublebuffer == 0U) + { + if (ep->type != EP_TYPE_ISOC) + { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + } + else + { + /* Configure TX Endpoint to disabled state */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + } + } + } + else /* OUT endpoint */ + { + if (ep->doublebuffer == 0U) + { + if (ep->type != EP_TYPE_ISOC) + { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK); + } + else + { + /* Configure RX Endpoint to disabled state */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); + } + } + } + + return HAL_OK; +} +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ + +/** + * @brief USB_StopDevice Stop the usb device mode + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_StopDevice(USB_DRD_TypeDef *USBx) +{ + /* disable all interrupts and force USB reset */ + USBx->CNTR = USB_CNTR_USBRST; + + /* clear interrupt status register */ + USBx->ISTR = 0U; + + /* switch-off device */ + USBx->CNTR = (USB_CNTR_USBRST | USB_CNTR_PDWN); + + return HAL_OK; +} + +/** + * @brief USB_SetDevAddress Stop the usb device mode + * @param USBx Selected device + * @param address new device address to be assigned + * This parameter can be a value from 0 to 255 + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetDevAddress(USB_DRD_TypeDef *USBx, uint8_t address) +{ + if (address == 0U) + { + /* set device address and enable function */ + USBx->DADDR = USB_DADDR_EF; + } + + return HAL_OK; +} + +/** + * @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevConnect(USB_DRD_TypeDef *USBx) +{ + /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */ + USBx->BCDR |= USB_BCDR_DPPU; + + return HAL_OK; +} + +/** + * @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevDisconnect(USB_DRD_TypeDef *USBx) +{ + /* Disable DP Pull-Up bit to disconnect the Internal PU resistor on USB DP line */ + USBx->BCDR &= ~(USB_BCDR_DPPU); + + return HAL_OK; +} + +/** + * @brief USB_ReadInterrupts return the global USB interrupt status + * @param USBx Selected device + * @retval USB Global Interrupt status + */ +uint32_t USB_ReadInterrupts(USB_DRD_TypeDef *USBx) +{ + uint32_t tmpreg; + + tmpreg = USBx->ISTR; + return tmpreg; +} + +/** + * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_DRD_TypeDef *USBx) +{ + USBx->CNTR |= USB_CNTR_L2RES; + + return HAL_OK; +} + +/** + * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_DRD_TypeDef *USBx) +{ + USBx->CNTR &= ~USB_CNTR_L2RES; + + return HAL_OK; +} + +/** + * @brief Copy a buffer from user memory area to packet memory area (PMA) + * @param USBx USB peripheral instance register address. + * @param pbUsrBuf pointer to user memory area. + * @param wPMABufAddr address into PMA. + * @param wNBytes no. of bytes to be copied. + * @retval None + */ +void USB_WritePMA(USB_DRD_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + UNUSED(USBx); + uint32_t WrVal; + uint32_t count; + __IO uint32_t *pdwVal; + uint32_t NbWords = ((uint32_t)wNBytes + 3U) >> 2U; + /* Due to the PMA access 32bit only so the last non word data should be processed alone */ + uint16_t remaining_bytes = wNBytes % 4U; + uint8_t *pBuf = pbUsrBuf; + + /* Check if there is a remaining byte */ + if (remaining_bytes != 0U) + { + NbWords--; + } + + /* Get the PMA Buffer pointer */ + pdwVal = (__IO uint32_t *)(USB_DRD_PMAADDR + (uint32_t)wPMABufAddr); + + /* Write the Calculated Word into the PMA related Buffer */ + for (count = NbWords; count != 0U; count--) + { + *pdwVal = __UNALIGNED_UINT32_READ(pBuf); + pdwVal++; + /* Increment pBuf 4 Time as Word Increment */ + pBuf++; + pBuf++; + pBuf++; + pBuf++; + } + + /* When Number of data is not word aligned, write the remaining Byte */ + if (remaining_bytes != 0U) + { + WrVal = 0U; + + do + { + WrVal |= (uint32_t)(*(uint8_t *)pBuf) << (8U * count); + count++; + pBuf++; + remaining_bytes--; + } while (remaining_bytes != 0U); + + *pdwVal = WrVal; + } +} + +/** + * @brief Copy data from packet memory area (PMA) to user memory buffer + * @param USBx USB peripheral instance register address. + * @param pbUsrBuf pointer to user memory area. + * @param wPMABufAddr address into PMA. + * @param wNBytes no. of bytes to be copied. + * @retval None + */ +void USB_ReadPMA(USB_DRD_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + UNUSED(USBx); + uint32_t count; + uint32_t RdVal; + __IO uint32_t *pdwVal; + uint32_t NbWords = ((uint32_t)wNBytes + 3U) >> 2U; + /*Due to the PMA access 32bit only so the last non word data should be processed alone */ + uint16_t remaining_bytes = wNBytes % 4U; + uint8_t *pBuf = pbUsrBuf; + + /* Get the PMA Buffer pointer */ + pdwVal = (__IO uint32_t *)(USB_DRD_PMAADDR + (uint32_t)wPMABufAddr); + + /* if nbre of byte is not word aligned decrement the nbre of word*/ + if (remaining_bytes != 0U) + { + NbWords--; + } + + /*Read the Calculated Word From the PMA related Buffer*/ + for (count = NbWords; count != 0U; count--) + { + __UNALIGNED_UINT32_WRITE(pBuf, *pdwVal); + + pdwVal++; + pBuf++; + pBuf++; + pBuf++; + pBuf++; + } + + /*When Number of data is not word aligned, read the remaining byte*/ + if (remaining_bytes != 0U) + { + RdVal = *(__IO uint32_t *)pdwVal; + + do + { + *(uint8_t *)pBuf = (uint8_t)(RdVal >> (8U * (uint8_t)(count))); + count++; + pBuf++; + remaining_bytes--; + } while (remaining_bytes != 0U); + } +} + + +/*------------------------------------------------------------------------*/ +/* HOST API */ +/*------------------------------------------------------------------------*/ + +/** + * @brief USB_HostInit Initializes the USB DRD controller registers + * for Host mode + * @param USBx Selected device + * @param cfg pointer to a USB_DRD_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_HostInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg) +{ + UNUSED(cfg); + + /* Clear All Pending Interrupt */ + USBx->ISTR = 0U; + + /* Disable all interrupts */ + USBx->CNTR &= ~(USB_CNTR_CTRM | USB_CNTR_PMAOVRM | USB_CNTR_ERRM | + USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_DCON | + USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_L1REQM); + + /* Clear All Pending Interrupt */ + USBx->ISTR = 0U; + + /* Enable Global interrupt */ + USBx->CNTR |= (USB_CNTR_CTRM | USB_CNTR_PMAOVRM | USB_CNTR_ERRM | + USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_DCON | + USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_L1REQM); + + /* Remove Reset */ + USBx->CNTR &= ~USB_CNTR_USBRST; + + return HAL_OK; +} + + +/** + * @brief USB_DRD_ResetPort : Reset Host Port + * @param USBx Selected device + * @retval HAL status + * @note (1)The application must wait at least 10 ms + * before clearing the reset bit. + */ +HAL_StatusTypeDef USB_ResetPort(USB_DRD_TypeDef *USBx) +{ + /* Force USB Reset */ + USBx->CNTR |= USB_CNTR_USBRST; + HAL_Delay(100); + /* Release USB Reset */ + USBx->CNTR &= ~USB_CNTR_USBRST; + HAL_Delay(30); + + return HAL_OK; +} + +/** + * @brief Return Host Core speed + * @param USBx Selected device + * @retval speed Host speed + * This parameter can be one of these values + * @arg USB_DRD_SPEED_FS Full speed mode + * @arg USB_DRD_SPEED_LS Low speed mode + */ +uint32_t USB_GetHostSpeed(USB_DRD_TypeDef *USBx) +{ + if ((USBx->ISTR & USB_ISTR_LS_DCONN) != 0U) + { + return USB_DRD_SPEED_LS; + } + else + { + return USB_DRD_SPEED_FS; + } +} + +/** + * @brief Return Host Current Frame number + * @param USBx Selected device + * @retval current frame number + */ +uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef *USBx) +{ + return USBx->FNR & 0x7FFU; +} + +/** + * @brief Set the channel Kind (Single/double buffer mode) + * @param USBx Selected device + * @param phy_ch_num Selected device + * @param db_state double state can be USB_DRD_XXX_DBUFF_ENBALE/USB_DRD_XXX_DBUFF_DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, + uint8_t phy_ch_num, uint8_t db_state) +{ + uint32_t tmp; + + if ((db_state == USB_DRD_BULK_DBUFF_ENBALE) || (db_state == USB_DRD_ISOC_DBUFF_DISABLE)) + { + tmp = (USB_DRD_GET_CHEP(USBx, phy_ch_num) | USB_CH_KIND) & USB_CHEP_DB_MSK; + } + else + { + tmp = USB_DRD_GET_CHEP(USBx, phy_ch_num) & (~USB_CH_KIND) & USB_CHEP_DB_MSK; + } + + /* Set the device speed in case using HUB FS with device LS */ + USB_DRD_SET_CHEP(USBx, phy_ch_num, tmp); + + return HAL_OK; +} + +/** + * @brief Initialize a host channel + * @param USBx Selected device + * @param phy_ch_num Channel number + * This parameter can be a value from 1 to 15 + * @param epnum Endpoint number + * This parameter can be a value from 1 to 15 + * @param dev_address Current device address + * This parameter can be a value from 0 to 255 + * @param speed Current device speed + * This parameter can be one of these values: + * @arg USB_DRD_SPEED_FULL Full speed mode + * @arg USB_DRD_SPEED_LOW Low speed mode + * @param ep_type Endpoint Type + * This parameter can be one of these values: + * @arg EP_TYPE_CTRL Control type + * @arg EP_TYPE_ISOC Isochronous type + * @arg EP_TYPE_BULK Bulk type + * @arg EP_TYPE_INTR Interrupt type + * @param mps Max Packet Size + * This parameter can be a value from 0 to 32K + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t wChRegVal; + uint32_t HostCoreSpeed; + + UNUSED(mps); + + wChRegVal = USB_DRD_GET_CHEP(USBx, phy_ch_num) & USB_CH_T_MASK; + + /* initialize host Channel */ + switch (ep_type) + { + case EP_TYPE_CTRL: + wChRegVal |= USB_EP_CONTROL; + break; + + case EP_TYPE_BULK: + wChRegVal |= USB_EP_BULK; + break; + + case EP_TYPE_INTR: + wChRegVal |= USB_EP_INTERRUPT; + break; + + case EP_TYPE_ISOC: + wChRegVal |= USB_EP_ISOCHRONOUS; + break; + + default: + ret = HAL_ERROR; + break; + } + + wChRegVal &= ~USB_CHEP_DEVADDR; + wChRegVal |= (((uint32_t)dev_address << USB_CHEP_DEVADDR_Pos) | + ((uint32_t)epnum & 0x0FU)); + + /* Get Host core Speed */ + HostCoreSpeed = USB_GetHostSpeed(USBx); + + /* Set the device speed in case using HUB FS with device LS */ + if ((speed == USB_DRD_SPEED_LS) && (HostCoreSpeed == USB_DRD_SPEED_FS)) + { + wChRegVal |= USB_CHEP_LSEP; + } + + /* Set the dev_address & ep type */ + USB_DRD_SET_CHEP(USBx, phy_ch_num, (wChRegVal | USB_CH_VTRX | USB_CH_VTTX)); + + return ret; +} + +/** + * @brief Start a transfer over a host channel + * @param USBx Selected device + * @param hc pointer to host channel structure + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) +{ + uint32_t len; + uint32_t phy_ch_num = (uint32_t)hc->phy_ch_num; +#if (USE_USB_DOUBLE_BUFFER == 1U) + uint32_t ch_reg = USB_DRD_GET_CHEP(USBx, phy_ch_num); +#endif /* USE_USB_DOUBLE_BUFFER */ + + if (hc->ch_dir == CH_IN_DIR) /* In Channel */ + { + /* Multi packet transfer */ + if (hc->xfer_len > hc->max_packet) + { + len = hc->max_packet; + } + else + { + len = hc->xfer_len; + } + + if (hc->doublebuffer == 0U) + { + /* Set RX buffer count */ + USB_DRD_SET_CHEP_RX_CNT(USBx, phy_ch_num, len); + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + else if (hc->ep_type == EP_TYPE_BULK) + { + /* Double buffer activated */ + if ((hc->xfer_len > hc->max_packet)) + { + (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_ENBALE); + + /*Set the Double buffer counter*/ + USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 0U, len); + USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 0U, len); + } + else /* switch to single buffer mode */ + { + (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_DISABLE); + + /* Set RX buffer count */ + USB_DRD_SET_CHEP_RX_CNT(USBx, phy_ch_num, len); + } + } + else /* isochronous */ + { + /* Set the Double buffer counter */ + USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 0U, len); + USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 0U, len); + } +#endif /* USE_USB_DOUBLE_BUFFER */ + + /*Enable host channel */ + USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch_num, USB_CHEP_RX_STRX); + } + else /* Out Channel */ + { + /* Multi packet transfer*/ + if (hc->xfer_len > hc->max_packet) + { + len = hc->max_packet; + } + else + { + len = hc->xfer_len; + } + + /* configure and validate Tx endpoint */ + if (hc->doublebuffer == 0U) + { + USB_WritePMA(USBx, hc->xfer_buff, hc->pmaadress, (uint16_t)len); + USB_DRD_SET_CHEP_TX_CNT(USBx, phy_ch_num, (uint16_t)len); + + /*SET PID SETUP */ + if ((hc->data_pid) == HC_PID_SETUP) + { + USB_DRD_CHEP_TX_SETUP(USBx, phy_ch_num); + } + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + else if (hc->ep_type == EP_TYPE_BULK) + { + (void)USB_HC_BULK_DB_StartXfer(USBx, hc, ch_reg, &len); + } + else + { + (void)USB_HC_ISO_DB_StartXfer(USBx, hc, len); + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + /* Enable host channel */ + USB_DRD_SET_CHEP_TX_STATUS(USBx, hc->phy_ch_num, USB_CH_TX_VALID); + } + + return HAL_OK; +} + +#if (USE_USB_DOUBLE_BUFFER == 1U) +/** + * @brief Start Transfer of Channel isochronous out double buffer + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @param len Transfer Length + * @retval HAL state + */ +static HAL_StatusTypeDef USB_HC_ISO_DB_StartXfer(USB_DRD_TypeDef *USBx, + USB_DRD_HCTypeDef *hc, + uint32_t len) +{ + uint32_t phy_ch_num = (uint32_t)hc->phy_ch_num; + + /* check the DTOG_TX to determine in which buffer we should write */ + if ((USB_DRD_GET_CHEP(USBx, phy_ch_num) & USB_CH_DTOG_TX) != 0U) + { + USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 1U, len); + USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr0, (uint16_t)len); + } + else + { + /* DTOGTX=0 */ + /* Set the Double buffer counter for pmabuffer0 */ + USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 1U, len); + USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr1, (uint16_t)len); + } + + return HAL_OK; +} + +/** + * @brief Start Transfer of Channel bulk out double buffer + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @param ch_reg snapshot of the CHEPR register + * @param len Transfer Length + * @retval HAL state + */ +static HAL_StatusTypeDef USB_HC_BULK_DB_StartXfer(USB_DRD_TypeDef *USBx, + USB_DRD_HCTypeDef *hc, + uint32_t ch_reg, + uint32_t *len) +{ + uint32_t phy_ch_num = (uint32_t)hc->phy_ch_num; + + /* -Double Buffer Mangement- */ + if (hc->xfer_len_db > hc->max_packet) + { + /* enable double buffer mode */ + (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_ENBALE); + *len = hc->max_packet; + hc->xfer_len_db -= *len; + + /* Prepare two buffer before enabling host */ + if ((ch_reg & USB_CH_DTOG_TX) == 0U) + { + /* Write Buffer0 */ + USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 1U, (uint16_t)*len); + USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr0, (uint16_t)*len); + } + else + { + /* Write Buffer1 */ + USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 1U, (uint16_t)*len); + USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr1, (uint16_t)*len); + } + + hc->xfer_buff += *len; + + /* Multi packet transfer */ + if (hc->xfer_len_db > hc->max_packet) + { + hc->xfer_len_db -= *len; + } + else + { + *len = hc->xfer_len_db; + hc->xfer_len_db = 0U; + } + + if ((ch_reg & USB_CH_DTOG_TX) == 0U) + { + /* Write Buffer1 */ + USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 1U, (uint16_t)*len); + USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr1, (uint16_t)*len); + } + else + { + /* Write Buffer0 */ + USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 1U, (uint16_t)*len); + USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr0, (uint16_t)*len); + } + } + else + { + /* Disable bulk double buffer mode */ + (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_DISABLE); + USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr0, (uint16_t)*len); + USB_DRD_SET_CHEP_TX_CNT(USBx, phy_ch_num, (uint16_t)*len); + } + + return HAL_OK; +} +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + +/** + * @brief Halt a host channel in + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch) +{ + /* Set disable to Channel */ + USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch, USB_CH_RX_DIS); + + return HAL_OK; +} + + +/** + * @brief Halt a host channel out + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch) +{ + /* Set disable to Channel */ + USB_DRD_SET_CHEP_TX_STATUS(USBx, phy_ch, USB_CH_TX_DIS); + + return HAL_OK; +} + +/** + * @brief Stop Host Core + * @param USBx Selected device + * @retval HAL state + */ +HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx) +{ + USBx->ISTR &= ~(USB_ISTR_DIR | USB_ISTR_L1REQ | + USB_ISTR_ESOF | USB_ISTR_SOF | + USB_ISTR_RESET | USB_ISTR_DCON | + USB_ISTR_SUSP | USB_ISTR_WKUP | + USB_ISTR_ERR | USB_ISTR_PMAOVR | + USB_ISTR_CTR); + + /* Set PowerDown */ + USBx->CNTR |= USB_CNTR_PDWN; + + /* Force a Reset */ + USBx->CNTR |= USB_CNTR_USBRST; + + return HAL_OK; +} +#endif /* defined (USB_DRD_FS) */ +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ /** diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_usb.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_usb.h index 82f50cc124a..51f5942a1a6 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_usb.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_usb.h @@ -22,12 +22,12 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /* __cplusplus */ /* Includes ------------------------------------------------------------------*/ #include "stm32u5xx_hal_def.h" -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) /** @addtogroup STM32U5xx_HAL_Driver * @{ */ @@ -41,14 +41,13 @@ extern "C" { /** * @brief USB Mode definition */ -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) typedef enum { - USB_DEVICE_MODE = 0, - USB_HOST_MODE = 1, - USB_DRD_MODE = 2 -} USB_OTG_ModeTypeDef; + USB_DEVICE_MODE = 0, + USB_HOST_MODE = 1, + USB_DRD_MODE = 2 +} USB_ModeTypeDef; /** * @brief URB States definition @@ -61,7 +60,7 @@ typedef enum URB_NYET, URB_ERROR, URB_STALL -} USB_OTG_URBStateTypeDef; +} USB_URBStateTypeDef; /** * @brief Host channel States definition @@ -71,13 +70,15 @@ typedef enum HC_IDLE = 0, HC_XFRC, HC_HALTED, + HC_ACK, HC_NAK, HC_NYET, HC_STALL, HC_XACTERR, HC_BBLERR, HC_DATATGLERR -} USB_OTG_HCStateTypeDef; +} USB_HCStateTypeDef; + /** * @brief USB Instance Initialization Structure definition @@ -92,12 +93,13 @@ typedef struct This parameter Depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + uint32_t dma_enable; /*!< USB DMA state. + If DMA is not supported this parameter shall be set by default to zero */ + uint32_t speed; /*!< USB Core speed. This parameter can be any value of @ref PCD_Speed/HCD_Speed (HCD_SPEED_xxx, HCD_SPEED_xxx) */ - uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */ - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ uint32_t phy_itface; /*!< Select the used PHY interface. @@ -105,7 +107,7 @@ typedef struct uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ + uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */ uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ @@ -113,11 +115,17 @@ typedef struct uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) + uint32_t bulk_doublebuffer_enable; /*!< Enable or disable the double buffer mode on bulk EP */ -} USB_OTG_CfgTypeDef; + uint32_t iso_singlebuffer_enable; /*!< Enable or disable the Single buffer mode on Isochronous EP */ +#endif /* defined (USB_DRD_FS) */ +} USB_CfgTypeDef; typedef struct { @@ -130,51 +138,93 @@ typedef struct uint8_t is_stall; /*!< Endpoint stall condition This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + uint8_t is_iso_incomplete; /*!< Endpoint isoc condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + uint8_t type; /*!< Endpoint type This parameter can be any value of @ref USB_LL_EP_Type */ uint8_t data_pid_start; /*!< Initial data PID This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - uint8_t even_odd_frame; /*!< IFrame parity - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ +#if defined (USB_DRD_FS) + uint16_t pmaadress; /*!< PMA Address + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - uint16_t tx_fifo_num; /*!< Transmission FIFO number - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + uint16_t pmaaddr0; /*!< PMA Address0 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint16_t pmaaddr1; /*!< PMA Address1 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint8_t doublebuffer; /*!< Double buffer enable + This parameter can be 0 or 1 */ +#endif /* defined (USB_DRD_FS) */ uint32_t maxpacket; /*!< Endpoint Max packet size This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ - uint32_t xfer_len; /*!< Current transfer length */ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ -} USB_OTG_EPTypeDef; + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + uint8_t even_odd_frame; /*!< IFrame parity + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint16_t tx_fifo_num; /*!< Transmission FIFO number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ + + uint32_t xfer_size; /*!< requested transfer size */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#if defined (USB_DRD_FS) + uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */ + + uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */ +#endif /* defined (USB_DRD_FS) */ +} USB_EPTypeDef; typedef struct { uint8_t dev_addr; /*!< USB device address. This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ - - uint8_t ch_num; /*!< Host channel number. +#if defined (USB_DRD_FS) + uint8_t phy_ch_num; /*!< Host channel number. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint8_t ep_num; /*!< Endpoint number. + uint8_t ch_dir; /*!< channel direction + This parameter store the physical channel direction IN/OUT/BIDIR */ +#else + uint8_t ch_num; /*!< Host channel number. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ uint8_t ep_is_in; /*!< Endpoint direction This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ +#endif /* defined (USB_DRD_FS) */ + uint8_t ep_num; /*!< Endpoint number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ uint8_t speed; /*!< USB Host Channel speed. This parameter can be any value of @ref HCD_Device_Speed: (HCD_DEVICE_SPEED_xxx) */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ + uint8_t do_ssplit; /*!< Enable start split transaction in HS mode. */ + uint8_t do_csplit; /*!< Enable complete split transaction in HS mode. */ + uint8_t ep_ss_schedule; /*!< Enable periodic endpoint start split schedule . */ + uint32_t iso_splt_xactPos; /*!< iso split transfer transaction position. */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */ + uint8_t hub_port_nbr; /*!< USB HUB port number */ + uint8_t hub_addr; /*!< USB HUB address */ uint8_t ep_type; /*!< Endpoint Type. This parameter can be any value of @ref USB_LL_EP_Type */ @@ -187,9 +237,14 @@ typedef struct uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ - uint32_t XferSize; /*!< OTG Channel transfer size. */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + uint32_t XferSize; /*!< OTG Channel transfer size. */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ uint32_t xfer_len; /*!< Current transfer length. */ +#if defined (USB_DRD_FS) + uint32_t xfer_len_db; /*!< Current transfer length used in double buffer mode. */ +#endif /* defined (USB_DRD_FS) */ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ @@ -198,19 +253,50 @@ typedef struct uint8_t toggle_out; /*!< OUT transfer current toggle flag This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ + uint32_t NyetErrCnt; /*!< Complete Split NYET Host channel error count. */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ uint32_t ErrCnt; /*!< Host channel error count. */ - USB_OTG_URBStateTypeDef urb_state; /*!< URB state. - This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ +#if defined (USB_DRD_FS) + uint16_t pmaadress; /*!< PMA Address + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - USB_OTG_HCStateTypeDef state; /*!< Host Channel state. - This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ -} USB_OTG_HCTypeDef; -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + uint16_t pmaaddr0; /*!< PMA Address0 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint16_t pmaaddr1; /*!< PMA Address1 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint8_t doublebuffer; /*!< Double buffer enable + This parameter can be 0 or 1 */ +#endif /* defined (USB_DRD_FS) */ + + USB_URBStateTypeDef urb_state; /*!< URB state. + This parameter can be any value of @ref USB_URBStateTypeDef */ + USB_HCStateTypeDef state; /*!< Host Channel state. + This parameter can be any value of @ref USB_HCStateTypeDef */ +} USB_HCTypeDef; + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +typedef USB_ModeTypeDef USB_OTG_ModeTypeDef; +typedef USB_CfgTypeDef USB_OTG_CfgTypeDef; +typedef USB_EPTypeDef USB_OTG_EPTypeDef; +typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef; +typedef USB_HCStateTypeDef USB_OTG_HCStateTypeDef; +typedef USB_HCTypeDef USB_OTG_HCTypeDef; +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) +typedef USB_ModeTypeDef USB_DRD_ModeTypeDef; +typedef USB_CfgTypeDef USB_DRD_CfgTypeDef; +typedef USB_EPTypeDef USB_DRD_EPTypeDef; +typedef USB_URBStateTypeDef USB_DRD_URBStateTypeDef; +typedef USB_HCStateTypeDef USB_DRD_HCStateTypeDef; +typedef USB_HCTypeDef USB_DRD_HCTypeDef; +#endif /* defined (USB_DRD_FS) */ /* Exported constants --------------------------------------------------------*/ @@ -238,18 +324,6 @@ typedef struct * @} */ -/** @defgroup USB_LL Device Speed - * @{ - */ -#define USBD_HS_SPEED 0U -#define USBD_HSINFS_SPEED 1U -#define USBH_HS_SPEED 0U -#define USBD_FS_SPEED 2U -#define USBH_FSLS_SPEED 1U -/** - * @} - */ - /** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed * @{ */ @@ -263,7 +337,6 @@ typedef struct /** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY * @{ */ -#define USB_OTG_ULPI_PHY 1U #define USB_OTG_EMBEDDED_PHY 2U #define USB_OTG_HS_EMBEDDED_PHY 3U /** @@ -314,14 +387,26 @@ typedef struct /** * @} */ - +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ -#define EP_MPS_64 0U -#define EP_MPS_32 1U -#define EP_MPS_16 2U -#define EP_MPS_8 3U +#define EP_MPS_64 0U +#define EP_MPS_32 1U +#define EP_MPS_16 2U +#define EP_MPS_8 3U +/** + * @} + */ + +/** @defgroup USB_LL_EP_Type USB Low Layer EP Type + * @{ + */ +#define EP_TYPE_CTRL 0U +#define EP_TYPE_ISOC 1U +#define EP_TYPE_BULK 2U +#define EP_TYPE_INTR 3U +#define EP_TYPE_MSK 3U /** * @} */ @@ -336,18 +421,30 @@ typedef struct * @} */ -/** @defgroup USB_LL_EP_Type USB Low Layer EP Type +/** @defgroup USB_LL_CH_PID_Type USB Low Layer Channel PID Type * @{ */ -#define EP_TYPE_CTRL 0U -#define EP_TYPE_ISOC 1U -#define EP_TYPE_BULK 2U -#define EP_TYPE_INTR 3U -#define EP_TYPE_MSK 3U +#define HC_PID_DATA0 0U +#define HC_PID_DATA2 1U +#define HC_PID_DATA1 2U +#define HC_PID_SETUP 3U /** * @} */ +/** @defgroup USB_LL Device Speed + * @{ + */ +#define USBD_HS_SPEED 0U +#define USBD_HSINFS_SPEED 1U +#define USBH_HS_SPEED 0U +#define USBD_FS_SPEED 2U +#define USBH_FSLS_SPEED 1U +/** + * @} + */ + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines * @{ */ @@ -370,6 +467,16 @@ typedef struct * @} */ +/** @defgroup USB_LL_HFIR_Defines USB Low Layer frame interval Defines + * @{ + */ +#define HFIR_6_MHZ 6000U +#define HFIR_60_MHZ 60000U +#define HFIR_48_MHZ 48000U +/** + * @} + */ + /** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines * @{ */ @@ -385,16 +492,27 @@ typedef struct #define HCCHAR_BULK 2U #define HCCHAR_INTR 3U -#define HC_PID_DATA0 0U -#define HC_PID_DATA2 1U -#define HC_PID_DATA1 2U -#define HC_PID_SETUP 3U - #define GRXSTS_PKTSTS_IN 2U #define GRXSTS_PKTSTS_IN_XFER_COMP 3U #define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U #define GRXSTS_PKTSTS_CH_HALTED 7U +#define CLEAR_INTERRUPT_MASK 0xFFFFFFFFU + +#define HC_MAX_PKT_CNT 256U +#define ISO_SPLT_MPS 188U + +#define HCSPLT_BEGIN 1U +#define HCSPLT_MIDDLE 2U +#define HCSPLT_END 3U +#define HCSPLT_FULL 4U + +#define TEST_J 1U +#define TEST_K 2U +#define TEST_SE0_NAK 3U +#define TEST_PACKET 4U +#define TEST_FORCE_EN 5U + #define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) #define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) @@ -412,9 +530,540 @@ typedef struct + USB_OTG_HOST_CHANNEL_BASE\ + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #define EP_ADDR_MSK 0xFU +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) +#define EP_ADDR_MSK 0x7U + +#ifndef USE_USB_DOUBLE_BUFFER +#define USE_USB_DOUBLE_BUFFER 1U +#endif /* USE_USB_DOUBLE_BUFFER */ + +#define USB_EMBEDDED_PHY 2U + +/*!< USB Speed */ +#define USB_DRD_SPEED_FS 1U +#define USB_DRD_SPEED_LS 2U +#define USB_DRD_SPEED_LSFS 3U + +/*!< Channel Direction */ +#define CH_IN_DIR 1U +#define CH_OUT_DIR 0U + +/*!< Number of used channels in the Application */ +#ifndef USB_DRD_USED_CHANNELS +#define USB_DRD_USED_CHANNELS 8U +#endif /* USB_DRD_USED_CHANNELS */ + +/** + * used for USB_HC_DoubleBuffer API + */ +#define USB_DRD_BULK_DBUFF_ENBALE 1U +#define USB_DRD_BULK_DBUFF_DISABLE 2U +#define USB_DRD_ISOC_DBUFF_ENBALE 3U +#define USB_DRD_ISOC_DBUFF_DISABLE 4U + +/* First available address in PMA */ +#define PMA_START_ADDR (0x10U + (8U *(USB_DRD_USED_CHANNELS - 2U))) +#define PMA_END_ADDR USB_DRD_PMA_SIZE + +/* Exported macro ------------------------------------------------------------*/ +/** + * @} + */ +/******************** Bit definition for USB_COUNTn_RX register *************/ +#define USB_CNTRX_NBLK_MSK (0x1FU << 26) +#define USB_CNTRX_BLSIZE (0x1U << 31) + + +/*Set Channel/Endpoint to the USB Register */ +#define USB_DRD_SET_CHEP(USBx, bEpChNum, wRegValue) (*(__IO uint32_t *)\ + (&(USBx)->CHEP0R + (bEpChNum)) = (uint32_t)(wRegValue)) + +/*Get Channel/Endpoint from the USB Register */ +#define USB_DRD_GET_CHEP(USBx, bEpChNum) (*(__IO uint32_t *)(&(USBx)->CHEP0R + (bEpChNum))) + + +/** + * @brief free buffer used from the application realizing it to the line + * toggles bit SW_BUF in the double buffered endpoint register + * @param USBx USB device. + * @param bEpChNum, bDir + * @retval None + */ +#define USB_DRD_FREE_USER_BUFFER(USBx, bEpChNum, bDir) \ + do { \ + if ((bDir) == 0U) \ + { \ + /* OUT double buffered endpoint */ \ + USB_DRD_TX_DTOG((USBx), (bEpChNum)); \ + } \ + else if ((bDir) == 1U) \ + { \ + /* IN double buffered endpoint */ \ + USB_DRD_RX_DTOG((USBx), (bEpChNum)); \ + } \ + } while(0) + + +/** + * @brief Set the Setup bit in the corresponding channel, when a Setup + transaction is needed. + * @param USBx USB device. + * @param bEpChNum + * @retval None + */ +#define USB_DRD_CHEP_TX_SETUP(USBx, bEpChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) ; \ + \ + /* Set Setup bit */ \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_SETUP)); \ + } while(0) + + +/** + * @brief Clears bit ERR_RX in the Channel register + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_CLEAR_CHEP_RX_ERR(USBx, bChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bChNum)); \ + _wRegVal = (_wRegVal & USB_CHEP_REG_MASK & (~USB_CHEP_ERRRX) & (~USB_CHEP_VTRX)) | \ + (USB_CHEP_VTTX | USB_CHEP_ERRTX); \ + \ + USB_DRD_SET_CHEP((USBx), (bChNum), _wRegVal); \ + } while(0) /* USB_DRD_CLEAR_CHEP_RX_ERR */ + + +/** + * @brief Clears bit ERR_TX in the Channel register + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_CLEAR_CHEP_TX_ERR(USBx, bChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bChNum)); \ + _wRegVal = (_wRegVal & USB_CHEP_REG_MASK & (~USB_CHEP_ERRTX) & (~USB_CHEP_VTTX)) | \ + (USB_CHEP_VTRX|USB_CHEP_ERRRX); \ + \ + USB_DRD_SET_CHEP((USBx), (bChNum), _wRegVal); \ + } while(0) /* USB_DRD_CLEAR_CHEP_TX_ERR */ + + +/** + * @brief sets the status for tx transfer (bits STAT_TX[1:0]). + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define USB_DRD_SET_CHEP_TX_STATUS(USBx, bEpChNum, wState) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_TX_DTOGMASK; \ + /* toggle first bit ? */ \ + if ((USB_CHEP_TX_DTOG1 & (wState)) != 0U) \ + { \ + _wRegVal ^= USB_CHEP_TX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_CHEP_TX_DTOG2 & (wState)) != 0U) \ + { \ + _wRegVal ^= USB_CHEP_TX_DTOG2; \ + } \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX| USB_CHEP_VTTX)); \ + } while(0) /* USB_DRD_SET_CHEP_TX_STATUS */ + + +/** + * @brief sets the status for rx transfer (bits STAT_TX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define USB_DRD_SET_CHEP_RX_STATUS(USBx, bEpChNum, wState) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_RX_DTOGMASK; \ + /* toggle first bit ? */ \ + if ((USB_CHEP_RX_DTOG1 & (wState)) != 0U) \ + { \ + _wRegVal ^= USB_CHEP_RX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_CHEP_RX_DTOG2 & (wState)) != 0U) \ + { \ + _wRegVal ^= USB_CHEP_RX_DTOG2; \ + } \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \ + } while(0) /* USB_DRD_SET_CHEP_RX_STATUS */ + + +/** + * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] + * /STAT_RX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval status + */ +#define USB_DRD_GET_CHEP_TX_STATUS(USBx, bEpChNum) \ + ((uint16_t)USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_DRD_CHEP_TX_STTX) + +#define USB_DRD_GET_CHEP_RX_STATUS(USBx, bEpChNum) \ + ((uint16_t)USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_DRD_CHEP_RX_STRX) + + +/** + * @brief set EP_KIND bit. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_SET_CHEP_KIND(USBx, bEpChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \ + \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_KIND)); \ + } while(0) /* USB_DRD_SET_CHEP_KIND */ + + +/** + * @brief clear EP_KIND bit. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_CLEAR_CHEP_KIND(USBx, bEpChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_EP_KIND_MASK; \ + \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \ + } while(0) /* USB_DRD_CLEAR_CHEP_KIND */ + + +/** + * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_CLEAR_RX_CHEP_CTR(USBx, bEpChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & (0xFFFF7FFFU & USB_CHEP_REG_MASK); \ + \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTTX)); \ + } while(0) /* USB_CLEAR_RX_CHEP_CTR */ + +#define USB_DRD_CLEAR_TX_CHEP_CTR(USBx, bEpChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & (0xFFFFFF7FU & USB_CHEP_REG_MASK); \ + \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX)); \ + } while(0) /* USB_CLEAR_TX_CHEP_CTR */ + + +/** + * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_RX_DTOG(USBx, bEpChNum) \ + do { \ + uint32_t _wEPVal; \ + \ + _wEPVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \ + \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wEPVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_RX)); \ + } while(0) /* USB_DRD_RX_DTOG */ + +#define USB_DRD_TX_DTOG(USBx, bEpChNum) \ + do { \ + uint32_t _wEPVal; \ + \ + _wEPVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \ + \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wEPVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_TX)); \ + } while(0) /* USB_TX_DTOG */ + + +/** + * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_CLEAR_RX_DTOG(USBx, bEpChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)); \ + \ + if ((_wRegVal & USB_CHEP_DTOG_RX) != 0U) \ + { \ + USB_DRD_RX_DTOG((USBx), (bEpChNum)); \ + } \ + } while(0) /* USB_DRD_CLEAR_RX_DTOG */ + +#define USB_DRD_CLEAR_TX_DTOG(USBx, bEpChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)); \ + \ + if ((_wRegVal & USB_CHEP_DTOG_TX) != 0U) \ + { \ + USB_DRD_TX_DTOG((USBx), (bEpChNum)); \ + } \ + } while(0) /* USB_DRD_CLEAR_TX_DTOG */ + + +/** + * @brief Sets address in an endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @param bAddr Address. + * @retval None + */ +#define USB_DRD_SET_CHEP_ADDRESS(USBx, bEpChNum, bAddr) \ + do { \ + uint32_t _wRegVal; \ + \ + /*Read the USB->CHEPx into _wRegVal, Reset(DTOGRX/STRX/DTOGTX/STTX) and set the EpAddress*/ \ + _wRegVal = (USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK) | (bAddr); \ + \ + /*Set _wRegVal in USB->CHEPx and set Transmit/Receive Valid Transfer (x=bEpChNum)*/ \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \ + } while(0) /* USB_DRD_SET_CHEP_ADDRESS */ + + +/* PMA API Buffer Descriptor Management ------------------------------------------------------------*/ +/* Buffer Descriptor Table TXBD0/RXBD0 --- > TXBD7/RXBD7 8 possible descriptor +* The buffer descriptor is located inside the packet buffer memory (USB_PMA_BUFF) +* TXBD [Reserve |Countx| Address_Tx] +* RXBD [BLSIEZ|NUM_Block |CounRx| Address_Rx] */ + +/* Set TX Buffer Descriptor Address Field */ +#define USB_DRD_SET_CHEP_TX_ADDRESS(USBx, bEpChNum, wAddr) \ + do { \ + /* Reset old Address */ \ + (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD &= USB_PMA_TXBD_ADDMSK; \ + \ + /* Bit0 & Bit1 should be =0 PMA must be Word aligned */ \ + (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD |= (uint32_t)(((uint32_t)(wAddr) >> 2U) << 2U); \ + } while(0) /* USB_DRD_SET_CHEP_TX_ADDRESS */ + +/* Set RX Buffer Descriptor Address Field */ +#define USB_DRD_SET_CHEP_RX_ADDRESS(USBx, bEpChNum, wAddr) \ + do { \ + /* Reset old Address */ \ + (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD &= USB_PMA_RXBD_ADDMSK; \ + \ + /* Bit0 & Bit1 should be =0 PMA must be Word aligned */ \ + (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD |= (uint32_t)(((uint32_t)(wAddr) >> 2U) << 2U); \ + } while(0) /* USB_SET_CHEP_RX_ADDRESS */ + + +/** + * @brief Sets counter of rx buffer with no. of blocks. + * @param pdwReg Register pointer + * @param wCount Counter. + * @param wNBlocks no. of Blocks. + * @retval None + */ +#define USB_DRD_CALC_BLK32(pdwReg, wCount, wNBlocks) \ + do { \ + /* Divide PacketSize by 32 to calculate the Nb of Block32 */ \ + (wNBlocks) =((uint32_t)(wCount) >> 5U); \ + if (((uint32_t)(wCount) % 32U) == 0U) \ + { \ + (wNBlocks)--; \ + } \ + \ + (pdwReg)|= (uint32_t)((((wNBlocks) << 26U)) | USB_CNTRX_BLSIZE); \ + } while(0) /* USB_DRD_CALC_BLK32 */ + +#define USB_DRD_CALC_BLK2(pdwReg, wCount, wNBlocks) \ + do { \ + /* Divide PacketSize by 32 to calculate the Nb of Block32 */ \ + (wNBlocks) = (uint32_t)((uint32_t)(wCount) >> 1U); \ + if (((wCount) & 0x1U) != 0U) \ + { \ + (wNBlocks)++; \ + } \ + (pdwReg) |= (uint32_t)((wNBlocks) << 26U); \ + } while(0) /* USB_DRD_CALC_BLK2 */ + +#define USB_DRD_SET_CHEP_CNT_RX_REG(pdwReg, wCount) \ + do { \ + uint32_t wNBlocks; \ + \ + (pdwReg) &= ~(USB_CNTRX_BLSIZE | USB_CNTRX_NBLK_MSK); \ + \ + if ((wCount) > 62U) \ + { \ + USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ + } \ + else \ + { \ + if ((wCount) == 0U) \ + { \ + (pdwReg) |= USB_CNTRX_BLSIZE; \ + } \ + else \ + { \ + USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ + } \ + } \ + } while(0) /* USB_DRD_SET_CHEP_CNT_RX_REG */ + + +/** + * @brief sets counter for the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @param wCount Counter value. + * @retval None + */ +#define USB_DRD_SET_CHEP_TX_CNT(USBx,bEpChNum, wCount) \ + do { \ + /* Reset old TX_Count value */ \ + (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD &= USB_PMA_TXBD_COUNTMSK; \ + \ + /* Set the wCount in the dedicated EP_TXBuffer */ \ + (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD |= (uint32_t)((uint32_t)(wCount) << 16U); \ + } while(0) + +#define USB_DRD_SET_CHEP_RX_DBUF0_CNT(USBx, bEpChNum, wCount) \ + USB_DRD_SET_CHEP_CNT_RX_REG(((USB_DRD_PMA_BUFF + (bEpChNum))->TXBD), (wCount)) + +#define USB_DRD_SET_CHEP_RX_CNT(USBx, bEpChNum, wCount) \ + USB_DRD_SET_CHEP_CNT_RX_REG(((USB_DRD_PMA_BUFF + (bEpChNum))->RXBD), (wCount)) + +/** + * @brief gets counter of the tx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval Counter value + */ +#define USB_DRD_GET_CHEP_TX_CNT(USBx, bEpChNum) (((USB_DRD_PMA_BUFF + (bEpChNum))->TXBD & 0x03FF0000U) >> 16U) +#define USB_DRD_GET_CHEP_RX_CNT(USBx, bEpChNum) (((USB_DRD_PMA_BUFF + (bEpChNum))->RXBD & 0x03FF0000U) >> 16U) + +#define USB_DRD_GET_EP_TX_CNT USB_GET_CHEP_TX_CNT +#define USB_DRD_GET_CH_TX_CNT USB_GET_CHEP_TX_CNT + +#define USB_DRD_GET_EP_RX_CNT USB_DRD_GET_CHEP_RX_CNT +#define USB_DRD_GET_CH_RX_CNT USB_DRD_GET_CHEP_RX_CNT +/** + * @brief Sets buffer 0/1 address in a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @param wBuf0Addr buffer 0 address. + * @retval Counter value + */ +#define USB_DRD_SET_CHEP_DBUF0_ADDR(USBx, bEpChNum, wBuf0Addr) \ + USB_DRD_SET_CHEP_TX_ADDRESS((USBx), (bEpChNum), (wBuf0Addr)) + +#define USB_DRD_SET_CHEP_DBUF1_ADDR(USBx, bEpChNum, wBuf1Addr) \ + USB_DRD_SET_CHEP_RX_ADDRESS((USBx), (bEpChNum), (wBuf1Addr)) + + +/** + * @brief Sets addresses in a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @param wBuf0Addr: buffer 0 address. + * @param wBuf1Addr = buffer 1 address. + * @retval None + */ +#define USB_DRD_SET_CHEP_DBUF_ADDR(USBx, bEpChNum, wBuf0Addr, wBuf1Addr) \ + do { \ + USB_DRD_SET_CHEP_DBUF0_ADDR((USBx), (bEpChNum), (wBuf0Addr)); \ + USB_DRD_SET_CHEP_DBUF1_ADDR((USBx), (bEpChNum), (wBuf1Addr)); \ + } while(0) /* USB_DRD_SET_CHEP_DBUF_ADDR */ + + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @param bDir endpoint dir EP_DBUF_OUT = OUT + * EP_DBUF_IN = IN + * @param wCount: Counter value + * @retval None + */ +#define USB_DRD_SET_CHEP_DBUF0_CNT(USBx, bEpChNum, bDir, wCount) \ + do { \ + if ((bDir) == 0U) \ + { \ + /* OUT endpoint */ \ + USB_DRD_SET_CHEP_RX_DBUF0_CNT((USBx), (bEpChNum), (wCount)); \ + } \ + else \ + { \ + if ((bDir) == 1U) \ + { \ + /* IN endpoint */ \ + USB_DRD_SET_CHEP_TX_CNT((USBx), (bEpChNum), (wCount)); \ + } \ + } \ + } while(0) /* USB_DRD_SET_CHEP_DBUF0_CNT */ + +#define USB_DRD_SET_CHEP_DBUF1_CNT(USBx, bEpChNum, bDir, wCount) \ + do { \ + if ((bDir) == 0U) \ + { \ + /* OUT endpoint */ \ + USB_DRD_SET_CHEP_RX_CNT((USBx), (bEpChNum), (wCount)); \ + } \ + else \ + { \ + if ((bDir) == 1U) \ + { \ + /* IN endpoint */ \ + (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD &= USB_PMA_TXBD_COUNTMSK; \ + (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD |= (uint32_t)((uint32_t)(wCount) << 16U); \ + } \ + } \ + } while(0) /* USB_DRD_SET_CHEP_DBUF1_CNT */ + +#define USB_DRD_SET_CHEP_DBUF_CNT(USBx, bEpChNum, bDir, wCount) \ + do { \ + USB_DRD_SET_CHEP_DBUF0_CNT((USBx), (bEpChNum), (bDir), (wCount)); \ + USB_DRD_SET_CHEP_DBUF1_CNT((USBx), (bEpChNum), (bDir), (wCount)); \ + } while(0) /* USB_DRD_SET_EPCH_DBUF_CNT */ + +/** + * @brief Gets buffer 0/1 rx/tx counter for double buffering. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_GET_CHEP_DBUF0_CNT(USBx, bEpChNum) (USB_DRD_GET_CHEP_TX_CNT((USBx), (bEpChNum))) +#define USB_DRD_GET_CHEP_DBUF1_CNT(USBx, bEpChNum) (USB_DRD_GET_CHEP_RX_CNT((USBx), (bEpChNum))) +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -453,13 +1102,13 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); -HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma); void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address); HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx); @@ -469,6 +1118,7 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uin uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx); uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx); uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum); uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx); uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx); @@ -495,6 +1145,50 @@ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) +HAL_StatusTypeDef USB_CoreInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); +HAL_StatusTypeDef USB_DevInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); +HAL_StatusTypeDef USB_EnableGlobalInt(USB_DRD_TypeDef *USBx); +HAL_StatusTypeDef USB_DisableGlobalInt(USB_DRD_TypeDef *USBx); +HAL_StatusTypeDef USB_SetCurrentMode(USB_DRD_TypeDef *USBx, USB_DRD_ModeTypeDef mode); + +#if defined (HAL_PCD_MODULE_ENABLED) +HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPSetStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStopXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ + +HAL_StatusTypeDef USB_SetDevAddress(USB_DRD_TypeDef *USBx, uint8_t address); +HAL_StatusTypeDef USB_DevConnect(USB_DRD_TypeDef *USBx); +HAL_StatusTypeDef USB_DevDisconnect(USB_DRD_TypeDef *USBx); +HAL_StatusTypeDef USB_StopDevice(USB_DRD_TypeDef *USBx); +uint32_t USB_ReadInterrupts(USB_DRD_TypeDef *USBx); + +HAL_StatusTypeDef USB_ResetPort(USB_DRD_TypeDef *USBx); +HAL_StatusTypeDef USB_HostInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); +HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch); +HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch); +HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc); + +uint32_t USB_GetHostSpeed(USB_DRD_TypeDef *USBx); +uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef *USBx); +HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx); +HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t db_state); +HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t epnum, + uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps); + +HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_DRD_TypeDef *USBx); +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_DRD_TypeDef *USBx); + +void USB_WritePMA(USB_DRD_TypeDef *USBx, uint8_t *pbUsrBuf, + uint16_t wPMABufAddr, uint16_t wNBytes); + +void USB_ReadPMA(USB_DRD_TypeDef *USBx, uint8_t *pbUsrBuf, + uint16_t wPMABufAddr, uint16_t wNBytes); +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -510,11 +1204,11 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); /** * @} */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #ifdef __cplusplus } -#endif +#endif /* __cplusplus */ #endif /* STM32U5xx_LL_USB_H */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_utils.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_utils.c index 7702a5a9b0a..5c23514e448 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_utils.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_utils.c @@ -66,9 +66,9 @@ #define UTILS_SCALE2_LATENCY1_FREQ (50000000U) /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ #define UTILS_SCALE2_LATENCY2_FREQ (75000000U) /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ #define UTILS_SCALE2_LATENCY3_FREQ (100000000U) /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */ -#define UTILS_SCALE3_LATENCY0_FREQ (12.5000000) /*!< HCLK frequency to set FLASH latency 0 in power scale 3 */ +#define UTILS_SCALE3_LATENCY0_FREQ (12500000U) /*!< HCLK frequency to set FLASH latency 0 in power scale 3 */ #define UTILS_SCALE3_LATENCY1_FREQ (25000000U) /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */ -#define UTILS_SCALE3_LATENCY2_FREQ (37.5000000) /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */ +#define UTILS_SCALE3_LATENCY2_FREQ (37500000U) /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */ #define UTILS_SCALE3_LATENCY3_FREQ (50000000U) /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */ #define UTILS_SCALE4_LATENCY0_FREQ (8000000U) /*!< HCLK frequency to set FLASH latency 0 in power scale 4 */ #define UTILS_SCALE4_LATENCY1_FREQ (16000000U) /*!< HCLK frequency to set FLASH latency 1 in power scale 4 */ @@ -345,7 +345,7 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency) } else if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE3) { - if ((float_t)HCLK_Frequency <= UTILS_SCALE3_LATENCY0_FREQ) + if (HCLK_Frequency <= UTILS_SCALE3_LATENCY0_FREQ) { /* 0 < HCLK <= 12.5 => 0WS (1 CPU cycles) : Do nothing, keep latency to default LL_FLASH_LATENCY_0 */ } @@ -354,7 +354,7 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency) /* 12.5 < HCLK <= 25 => 1WS (2 CPU cycles) */ latency = LL_FLASH_LATENCY_1; } - else if ((float_t)HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ) + else if (HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ) { /* 25 < HCLK <= 37.5 => 2WS (3 CPU cycles) */ latency = LL_FLASH_LATENCY_2; @@ -394,10 +394,10 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency) } } - if(status == SUCCESS) + if (status == SUCCESS) { LL_FLASH_SetLatency(latency); - + /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ timeout = 2; @@ -407,8 +407,8 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency) getlatency = LL_FLASH_GetLatency(); timeout--; } while ((getlatency != latency) && (timeout > 0U)); - - if(getlatency != latency) + + if (getlatency != latency) { status = ERROR; } @@ -435,7 +435,7 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency) * - ERROR: Max frequency configuration not done */ ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) { ErrorStatus status = SUCCESS; uint32_t pllfreq; @@ -546,7 +546,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS * - ERROR: Max frequency configuration not done */ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) { ErrorStatus status; uint32_t pllfreq; @@ -605,8 +605,8 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS * - ERROR: Max frequency configuration not done */ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, - LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) { ErrorStatus status; uint32_t pllfreq; diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_utils.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_utils.h index f763b599115..4e9d902c814 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_utils.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_utils.h @@ -97,19 +97,19 @@ typedef struct This parameter can be a value of @ref RCC_LL_EC_PLL1MBOOST_DIV This feature can be modified afterwards using unitary function - @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + @ref LL_RCC_PLL1_ConfigDomain_SYS(). */ uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 8 and Max_Data = 86 This feature can be modified afterwards using unitary function - @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + @ref LL_RCC_PLL1_ConfigDomain_SYS(). */ uint32_t PLLR; /*!< Division for the main system clock. - This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV + This parameter must be a number between Min_Data = 1 and Max_Data = 128 This feature can be modified afterwards using unitary function - @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + @ref LL_RCC_PLL1_ConfigDomain_SYS(). */ } LL_UTILS_PLLInitTypeDef; /** @@ -164,19 +164,29 @@ typedef struct /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE * @{ */ -#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA132 0x00000003U /*!< UFBGA132 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP144 0x00000004U /*!< LQFP144 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP48 0x00000005U /*!< LQFP48 package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000007U /*!< UFBGA169 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP64_SMPS 0x00000008U /*!< LQFP64 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_WLSCP90_SMPS 0x00000009U /*!< WLSCP90 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x0000000AU /*!< LQFP100 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA132_SMPS 0x0000000BU /*!< UFBGA132 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x0000000CU /*!< LQFP144 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_LQFP48_SMPS 0x0000000DU /*!< LQFP48 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA169_SMPS 0x0000000FU /*!< UFBGA169 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA132 0x00000003U /*!< UFBGA132 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144 0x00000004U /*!< LQFP144 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP48 0x00000005U /*!< LQFP48 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000007U /*!< UFBGA169 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP64_SMPS 0x00000008U /*!< LQFP64 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_WLSCP90_SMPS 0x00000009U /*!< WLSCP90 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x0000000AU /*!< LQFP100 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA132_SMPS 0x0000000BU /*!< UFBGA132 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x0000000CU /*!< LQFP144 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_LQFP48_SMPS 0x0000000DU /*!< LQFP48 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA169_SMPS 0x0000000FU /*!< UFBGA169 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP144 0x00000010U /*!< WLCSP144 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA144 0x00000011U /*!< UFBGA144 package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP144_SMPS 0x00000018U /*!< WLCSP144 with internal SMPS package t */ +#define LL_UTILS_PACKAGETYPE_UFBGA144_SMPS 0x00000019U /*!< UFBGA144 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP208_SMPS 0x0000001BU /*!< WLCSP208 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA216_SMPS 0x0000001CU /*!< TFBGA216 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA100_SMPS 0x0000001DU /*!< UFBGA100 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP56_SMPS 0x0000001EU /*!< WLCSP56 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP150_SMPS 0x0000001FU /*!< WLCSP150 or WLCSP150 DSI with internal package type */ + /** * @} */ @@ -250,6 +260,12 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void) * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_SMPS * @arg @ref LL_UTILS_PACKAGETYPE_LQFP48_SMPS * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP144 + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144 + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP144_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP208_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA216_SMPS */ __STATIC_INLINE uint32_t LL_GetPackageType(void) { @@ -304,12 +320,12 @@ void LL_mDelay(uint32_t Delay); void LL_SetSystemCoreClock(uint32_t HCLKFrequency); ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, - LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_wwdg.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_wwdg.h index 90885fce4e0..ff6c8d0e3a1 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/STM32U5xx_HAL_Driver/stm32u5xx_ll_wwdg.h @@ -135,7 +135,7 @@ __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL); } @@ -162,7 +162,7 @@ __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter) * @param WWDGx WWDG Instance * @retval 7 bit Watchdog Counter value */ -__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetCounter(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CR, WWDG_CR_T)); } @@ -203,7 +203,7 @@ __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescale * @arg @ref LL_WWDG_PRESCALER_64 * @arg @ref LL_WWDG_PRESCALER_128 */ -__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB)); } @@ -235,7 +235,7 @@ __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window) * @param WWDGx WWDG Instance * @retval 7 bit Watchdog Window value */ -__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetWindow(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CFR, WWDG_CFR_W)); } @@ -256,7 +256,7 @@ __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL); } @@ -298,7 +298,7 @@ __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL); } diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/stm32u5xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/stm32u5xx_hal_conf.h index ffaf9f09d29..1b8fb574d82 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/stm32u5xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/stm32u5xx_hal_conf.h @@ -45,11 +45,14 @@ extern "C" { #define HAL_DCMI_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED #define HAL_DMA2D_MODULE_ENABLED +#define HAL_DSI_MODULE_ENABLED #define HAL_EXTI_MODULE_ENABLED #define HAL_FDCAN_MODULE_ENABLED #define HAL_FLASH_MODULE_ENABLED #define HAL_FMAC_MODULE_ENABLED +#define HAL_GFXMMU_MODULE_ENABLED #define HAL_GPIO_MODULE_ENABLED +#define HAL_GPU2D_MODULE_ENABLED #define HAL_GTZC_MODULE_ENABLED #define HAL_HASH_MODULE_ENABLED #define HAL_HCD_MODULE_ENABLED @@ -58,6 +61,7 @@ extern "C" { #define HAL_IRDA_MODULE_ENABLED #define HAL_IWDG_MODULE_ENABLED #define HAL_LPTIM_MODULE_ENABLED +#define HAL_LTDC_MODULE_ENABLED #define HAL_MDF_MODULE_ENABLED #define HAL_MMC_MODULE_ENABLED #define HAL_NAND_MODULE_ENABLED @@ -84,6 +88,7 @@ extern "C" { #define HAL_UART_MODULE_ENABLED #define HAL_USART_MODULE_ENABLED #define HAL_WWDG_MODULE_ENABLED +#define HAL_XSPI_MODULE_ENABLED /* ########################## Oscillator Values adaptation ####################*/ /** @@ -197,9 +202,12 @@ vary depending on the variations in voltage and temperature.*/ #define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ #define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ #define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ #define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ #define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ #define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */ +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */ +#define USE_HAL_GPU2D_REGISTER_CALLBACKS 0U /* GPU2D register callback disabled */ #define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ #define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ #define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ @@ -212,6 +220,7 @@ vary depending on the variations in voltage and temperature.*/ #define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ #define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ #define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ +#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U /* OCTOSPI register callback disabled */ #define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */ #define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ #define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */ @@ -230,6 +239,7 @@ vary depending on the variations in voltage and temperature.*/ #define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ #define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ #define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ +#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U /* XSPI register callback disabled */ /* ################## SPI peripheral configuration ########################## */ @@ -277,6 +287,10 @@ vary depending on the variations in voltage and temperature.*/ #include "stm32u5xx_hal_dma2d.h" #endif /* HAL_DMA2D_MODULE_ENABLED */ +#ifdef HAL_DSI_MODULE_ENABLED +#include "stm32u5xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + #ifdef HAL_CORTEX_MODULE_ENABLED #include "stm32u5xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ @@ -309,6 +323,10 @@ vary depending on the variations in voltage and temperature.*/ #include "stm32u5xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ +#ifdef HAL_GFXMMU_MODULE_ENABLED +#include "stm32u5xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + #ifdef HAL_HASH_MODULE_ENABLED #include "stm32u5xx_hal_hash.h" #endif /* HAL_HASH_MODULE_ENABLED */ @@ -341,6 +359,10 @@ vary depending on the variations in voltage and temperature.*/ #include "stm32u5xx_hal_lptim.h" #endif /* HAL_LPTIM_MODULE_ENABLED */ +#ifdef HAL_LTDC_MODULE_ENABLED +#include "stm32u5xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + #ifdef HAL_OPAMP_MODULE_ENABLED #include "stm32u5xx_hal_opamp.h" #endif /* HAL_OPAMP_MODULE_ENABLED */ @@ -449,6 +471,14 @@ vary depending on the variations in voltage and temperature.*/ #include "stm32u5xx_hal_mdf.h" #endif /* HAL_MDF_MODULE_ENABLED */ +#ifdef HAL_GPU2D_MODULE_ENABLED +#include "stm32u5xx_hal_gpu2d.h" +#endif /* HAL_GPU2D_MODULE_ENABLED */ + +#ifdef HAL_XSPI_MODULE_ENABLED +#include "stm32u5xx_hal_xspi.h" +#endif /* HAL_XSPI_MODULE_ENABLED */ + /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT #include "stm32_assert.h" // MBED patch diff --git a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/system_stm32u5xx.c b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/system_stm32u5xx.c index 01e7f2847f6..727a6e2c605 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/system_stm32u5xx.c +++ b/targets/TARGET_STM/TARGET_STM32U5/STM32Cube_FW/system_stm32u5xx.c @@ -166,8 +166,8 @@ const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; - const uint32_t MSIRangeTable[16] = {48000000U,24000000U,16000000U,12000000U, 4000000U, 2000000U, 1500000U,\ - 1000000U, 3072000U, 1536000U,1024000U, 768000U, 400000U, 200000U, 150000U, 100000U}; + const uint32_t MSIRangeTable[16] = {48000000U,24000000U,16000000U,12000000U, 4000000U, 2000000U, 1330000U,\ + 1000000U, 3072000U, 1536000U,1024000U, 768000U, 400000U, 200000U, 133000U, 100000U}; /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/TOOLCHAIN_ARM/startup_stm32u575xx.S b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/TOOLCHAIN_ARM/startup_stm32u575xx.S index 2e8cf244925..70733b5c881 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/TOOLCHAIN_ARM/startup_stm32u575xx.S +++ b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/TOOLCHAIN_ARM/startup_stm32u575xx.S @@ -11,14 +11,14 @@ ;* After Reset the Cortex-M33 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************* +;* @attention ;* -;*

© Copyright (c) 2021 STMicroelectronics. -;* All rights reserved.

+;* Copyright (c) 2021 STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ;* ;******************************************************************************* ;* <<< Use Configuration Wizard in Context Menu >>> @@ -52,7 +52,7 @@ __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection Interrupt + DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection Interrupt DCD RTC_IRQHandler ; RTC non-secure interrupt DCD RTC_S_IRQHandler ; RTC secure interrupt DCD TAMP_IRQHandler ; Tamper non-secure interrupt @@ -176,6 +176,7 @@ __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; DCD MDF1_FLT5_IRQHandler ; MDF1 Filter 5 global interrupt DCD CORDIC_IRQHandler ; CORDIC global interrupt DCD FMAC_IRQHandler ; FMAC global interrupt + DCD LSECSSD_IRQHandler ; LSECSSD global interrupt __Vectors_End @@ -254,7 +255,7 @@ SysTick_Handler\ Default_Handler PROC EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_AVD_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT RTC_S_IRQHandler [WEAK] EXPORT TAMP_IRQHandler [WEAK] @@ -373,10 +374,11 @@ Default_Handler PROC EXPORT MDF1_FLT5_IRQHandler [WEAK] EXPORT CORDIC_IRQHandler [WEAK] EXPORT FMAC_IRQHandler [WEAK] + EXPORT LSECSSD_IRQHandler [WEAK] WWDG_IRQHandler -PVD_AVD_IRQHandler +PVD_PVM_IRQHandler RTC_IRQHandler RTC_S_IRQHandler TAMP_IRQHandler @@ -495,6 +497,7 @@ MDF1_FLT4_IRQHandler MDF1_FLT5_IRQHandler CORDIC_IRQHandler FMAC_IRQHandler +LSECSSD_IRQHandler B . @@ -507,5 +510,3 @@ FMAC_IRQHandler ;******************************************************************************* END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/TOOLCHAIN_GCC_ARM/startup_stm32u575xx.S b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/TOOLCHAIN_GCC_ARM/startup_stm32u575xx.S index 4001182ef23..eb584bb079d 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/TOOLCHAIN_GCC_ARM/startup_stm32u575xx.S +++ b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/TOOLCHAIN_GCC_ARM/startup_stm32u575xx.S @@ -12,18 +12,17 @@ * calls main()). * After Reset the Cortex-M33 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** + ******************************************************************************* * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * - ****************************************************************************** + ******************************************************************************* */ .syntax unified @@ -61,6 +60,8 @@ defined in linker script */ .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 @@ -90,8 +91,6 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit bl _start bx lr @@ -143,7 +142,7 @@ g_pfnVectors: .word PendSV_Handler .word SysTick_Handler .word WWDG_IRQHandler - .word PVD_AVD_IRQHandler + .word PVD_PVM_IRQHandler .word RTC_IRQHandler .word RTC_S_IRQHandler .word TAMP_IRQHandler @@ -267,6 +266,7 @@ g_pfnVectors: .word MDF1_FLT5_IRQHandler .word CORDIC_IRQHandler .word FMAC_IRQHandler + .word LSECSSD_IRQHandler /******************************************************************************* @@ -310,8 +310,8 @@ g_pfnVectors: .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler - .weak PVD_AVD_IRQHandler - .thumb_set PVD_AVD_IRQHandler,Default_Handler + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler .weak RTC_IRQHandler .thumb_set RTC_IRQHandler,Default_Handler @@ -534,13 +534,13 @@ g_pfnVectors: .weak OCTOSPI1_IRQHandler .thumb_set OCTOSPI1_IRQHandler,Default_Handler - + .weak PWR_S3WU_IRQHandler .thumb_set PWR_S3WU_IRQHandler,Default_Handler .weak SDMMC1_IRQHandler .thumb_set SDMMC1_IRQHandler,Default_Handler - + .weak SDMMC2_IRQHandler .thumb_set SDMMC2_IRQHandler,Default_Handler @@ -621,50 +621,53 @@ g_pfnVectors: .weak ICACHE_IRQHandler .thumb_set ICACHE_IRQHandler,Default_Handler - + .weak LPTIM4_IRQHandler .thumb_set LPTIM4_IRQHandler,Default_Handler - + .weak DCACHE1_IRQHandler .thumb_set DCACHE1_IRQHandler,Default_Handler - + .weak ADF1_IRQHandler .thumb_set ADF1_IRQHandler,Default_Handler - + .weak ADC4_IRQHandler .thumb_set ADC4_IRQHandler,Default_Handler - + .weak LPDMA1_Channel0_IRQHandler .thumb_set LPDMA1_Channel0_IRQHandler,Default_Handler - + .weak LPDMA1_Channel1_IRQHandler .thumb_set LPDMA1_Channel1_IRQHandler,Default_Handler - + .weak LPDMA1_Channel2_IRQHandler .thumb_set LPDMA1_Channel2_IRQHandler,Default_Handler - + .weak LPDMA1_Channel3_IRQHandler .thumb_set LPDMA1_Channel3_IRQHandler,Default_Handler - + .weak DMA2D_IRQHandler .thumb_set DMA2D_IRQHandler,Default_Handler - + .weak DCMI_PSSI_IRQHandler .thumb_set DCMI_PSSI_IRQHandler,Default_Handler - + .weak OCTOSPI2_IRQHandler .thumb_set OCTOSPI2_IRQHandler,Default_Handler - + .weak MDF1_FLT4_IRQHandler .thumb_set MDF1_FLT4_IRQHandler,Default_Handler - + .weak MDF1_FLT5_IRQHandler .thumb_set MDF1_FLT5_IRQHandler,Default_Handler - + .weak CORDIC_IRQHandler .thumb_set CORDIC_IRQHandler,Default_Handler - + .weak FMAC_IRQHandler .thumb_set FMAC_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + .weak LSECSSD_IRQHandler + .thumb_set LSECSSD_IRQHandler,Default_Handler + + diff --git a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/TOOLCHAIN_IAR/startup_stm32u575xx.S b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/TOOLCHAIN_IAR/startup_stm32u575xx.S index 57a87aadd4f..ea45c6c7554 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/TOOLCHAIN_IAR/startup_stm32u575xx.S +++ b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/TOOLCHAIN_IAR/startup_stm32u575xx.S @@ -11,15 +11,15 @@ ;* calls main()). ;* After Reset the Cortex-M33 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** +;******************************************************************************* +;* @attention ;* -;*

© Copyright (c) 2021 STMicroelectronics. -;* All rights reserved.

+;* Copyright (c) 2021 STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ;* ;******************************************************************************* ; @@ -75,7 +75,7 @@ __vector_table ; External Interrupts DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection Interrupt + DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection Interrupt DCD RTC_IRQHandler ; RTC non-secure interrupt DCD RTC_S_IRQHandler ; RTC secure interrupt DCD TAMP_IRQHandler ; Tamper non-secure interrupt @@ -199,6 +199,7 @@ __vector_table DCD MDF1_FLT5_IRQHandler ; MDF1 Filter 5 global interrupt DCD CORDIC_IRQHandler ; CORDIC global interrupt DCD FMAC_IRQHandler ; FMAC global interrupt + DCD LSECSSD_IRQHandler ; LSECSSD global interrupt __Vectors_End @@ -273,10 +274,10 @@ SysTick_Handler WWDG_IRQHandler B WWDG_IRQHandler - PUBWEAK PVD_AVD_IRQHandler + PUBWEAK PVD_PVM_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -PVD_AVD_IRQHandler - B PVD_AVD_IRQHandler +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler PUBWEAK RTC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) @@ -868,5 +869,10 @@ CORDIC_IRQHandler FMAC_IRQHandler B FMAC_IRQHandler + PUBWEAK LSECSSD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LSECSSD_IRQHandler + B LSECSSD_IRQHandler + END -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/TOOLCHAIN_IAR/stm32u575xg.icf b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/TOOLCHAIN_IAR/stm32u575xg.icf index afba70d1f13..61a3ced5cfd 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/TOOLCHAIN_IAR/stm32u575xg.icf +++ b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/TOOLCHAIN_IAR/stm32u575xg.icf @@ -18,8 +18,8 @@ /* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ -define symbol VECTORS = 141; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ -define symbol HEAP_SIZE = 0x11000; +define symbol VECTORS = 142; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0x1000; /* Common - Do not change */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/cmsis_nvic.h index 12612167fe2..1276bee0afb 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/cmsis_nvic.h @@ -22,7 +22,7 @@ #endif #if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x100000 // 1 MB +#define MBED_ROM_SIZE 0x0 // 0 B #endif #if !defined(MBED_RAM_START) @@ -30,10 +30,10 @@ #endif #if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0xC0000 // 768 KB +#define MBED_RAM_SIZE 0x0 // 0 B #endif -#define NVIC_NUM_VECTORS 141 +#define NVIC_NUM_VECTORS 142 #define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START #endif diff --git a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/TOOLCHAIN_ARM/startup_stm32u575xx.S b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/TOOLCHAIN_ARM/startup_stm32u575xx.S index 2e8cf244925..70733b5c881 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/TOOLCHAIN_ARM/startup_stm32u575xx.S +++ b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/TOOLCHAIN_ARM/startup_stm32u575xx.S @@ -11,14 +11,14 @@ ;* After Reset the Cortex-M33 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************* +;* @attention ;* -;*

© Copyright (c) 2021 STMicroelectronics. -;* All rights reserved.

+;* Copyright (c) 2021 STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ;* ;******************************************************************************* ;* <<< Use Configuration Wizard in Context Menu >>> @@ -52,7 +52,7 @@ __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection Interrupt + DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection Interrupt DCD RTC_IRQHandler ; RTC non-secure interrupt DCD RTC_S_IRQHandler ; RTC secure interrupt DCD TAMP_IRQHandler ; Tamper non-secure interrupt @@ -176,6 +176,7 @@ __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; DCD MDF1_FLT5_IRQHandler ; MDF1 Filter 5 global interrupt DCD CORDIC_IRQHandler ; CORDIC global interrupt DCD FMAC_IRQHandler ; FMAC global interrupt + DCD LSECSSD_IRQHandler ; LSECSSD global interrupt __Vectors_End @@ -254,7 +255,7 @@ SysTick_Handler\ Default_Handler PROC EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_AVD_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT RTC_S_IRQHandler [WEAK] EXPORT TAMP_IRQHandler [WEAK] @@ -373,10 +374,11 @@ Default_Handler PROC EXPORT MDF1_FLT5_IRQHandler [WEAK] EXPORT CORDIC_IRQHandler [WEAK] EXPORT FMAC_IRQHandler [WEAK] + EXPORT LSECSSD_IRQHandler [WEAK] WWDG_IRQHandler -PVD_AVD_IRQHandler +PVD_PVM_IRQHandler RTC_IRQHandler RTC_S_IRQHandler TAMP_IRQHandler @@ -495,6 +497,7 @@ MDF1_FLT4_IRQHandler MDF1_FLT5_IRQHandler CORDIC_IRQHandler FMAC_IRQHandler +LSECSSD_IRQHandler B . @@ -507,5 +510,3 @@ FMAC_IRQHandler ;******************************************************************************* END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/TOOLCHAIN_GCC_ARM/startup_stm32u575xx.S b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/TOOLCHAIN_GCC_ARM/startup_stm32u575xx.S index 4001182ef23..eb584bb079d 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/TOOLCHAIN_GCC_ARM/startup_stm32u575xx.S +++ b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/TOOLCHAIN_GCC_ARM/startup_stm32u575xx.S @@ -12,18 +12,17 @@ * calls main()). * After Reset the Cortex-M33 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** + ******************************************************************************* * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * - ****************************************************************************** + ******************************************************************************* */ .syntax unified @@ -61,6 +60,8 @@ defined in linker script */ .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 @@ -90,8 +91,6 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit bl _start bx lr @@ -143,7 +142,7 @@ g_pfnVectors: .word PendSV_Handler .word SysTick_Handler .word WWDG_IRQHandler - .word PVD_AVD_IRQHandler + .word PVD_PVM_IRQHandler .word RTC_IRQHandler .word RTC_S_IRQHandler .word TAMP_IRQHandler @@ -267,6 +266,7 @@ g_pfnVectors: .word MDF1_FLT5_IRQHandler .word CORDIC_IRQHandler .word FMAC_IRQHandler + .word LSECSSD_IRQHandler /******************************************************************************* @@ -310,8 +310,8 @@ g_pfnVectors: .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler - .weak PVD_AVD_IRQHandler - .thumb_set PVD_AVD_IRQHandler,Default_Handler + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler .weak RTC_IRQHandler .thumb_set RTC_IRQHandler,Default_Handler @@ -534,13 +534,13 @@ g_pfnVectors: .weak OCTOSPI1_IRQHandler .thumb_set OCTOSPI1_IRQHandler,Default_Handler - + .weak PWR_S3WU_IRQHandler .thumb_set PWR_S3WU_IRQHandler,Default_Handler .weak SDMMC1_IRQHandler .thumb_set SDMMC1_IRQHandler,Default_Handler - + .weak SDMMC2_IRQHandler .thumb_set SDMMC2_IRQHandler,Default_Handler @@ -621,50 +621,53 @@ g_pfnVectors: .weak ICACHE_IRQHandler .thumb_set ICACHE_IRQHandler,Default_Handler - + .weak LPTIM4_IRQHandler .thumb_set LPTIM4_IRQHandler,Default_Handler - + .weak DCACHE1_IRQHandler .thumb_set DCACHE1_IRQHandler,Default_Handler - + .weak ADF1_IRQHandler .thumb_set ADF1_IRQHandler,Default_Handler - + .weak ADC4_IRQHandler .thumb_set ADC4_IRQHandler,Default_Handler - + .weak LPDMA1_Channel0_IRQHandler .thumb_set LPDMA1_Channel0_IRQHandler,Default_Handler - + .weak LPDMA1_Channel1_IRQHandler .thumb_set LPDMA1_Channel1_IRQHandler,Default_Handler - + .weak LPDMA1_Channel2_IRQHandler .thumb_set LPDMA1_Channel2_IRQHandler,Default_Handler - + .weak LPDMA1_Channel3_IRQHandler .thumb_set LPDMA1_Channel3_IRQHandler,Default_Handler - + .weak DMA2D_IRQHandler .thumb_set DMA2D_IRQHandler,Default_Handler - + .weak DCMI_PSSI_IRQHandler .thumb_set DCMI_PSSI_IRQHandler,Default_Handler - + .weak OCTOSPI2_IRQHandler .thumb_set OCTOSPI2_IRQHandler,Default_Handler - + .weak MDF1_FLT4_IRQHandler .thumb_set MDF1_FLT4_IRQHandler,Default_Handler - + .weak MDF1_FLT5_IRQHandler .thumb_set MDF1_FLT5_IRQHandler,Default_Handler - + .weak CORDIC_IRQHandler .thumb_set CORDIC_IRQHandler,Default_Handler - + .weak FMAC_IRQHandler .thumb_set FMAC_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + .weak LSECSSD_IRQHandler + .thumb_set LSECSSD_IRQHandler,Default_Handler + + diff --git a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/TOOLCHAIN_IAR/startup_stm32u575xx.S b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/TOOLCHAIN_IAR/startup_stm32u575xx.S index 57a87aadd4f..ea45c6c7554 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/TOOLCHAIN_IAR/startup_stm32u575xx.S +++ b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/TOOLCHAIN_IAR/startup_stm32u575xx.S @@ -11,15 +11,15 @@ ;* calls main()). ;* After Reset the Cortex-M33 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** +;******************************************************************************* +;* @attention ;* -;*

© Copyright (c) 2021 STMicroelectronics. -;* All rights reserved.

+;* Copyright (c) 2021 STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ;* ;******************************************************************************* ; @@ -75,7 +75,7 @@ __vector_table ; External Interrupts DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection Interrupt + DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection Interrupt DCD RTC_IRQHandler ; RTC non-secure interrupt DCD RTC_S_IRQHandler ; RTC secure interrupt DCD TAMP_IRQHandler ; Tamper non-secure interrupt @@ -199,6 +199,7 @@ __vector_table DCD MDF1_FLT5_IRQHandler ; MDF1 Filter 5 global interrupt DCD CORDIC_IRQHandler ; CORDIC global interrupt DCD FMAC_IRQHandler ; FMAC global interrupt + DCD LSECSSD_IRQHandler ; LSECSSD global interrupt __Vectors_End @@ -273,10 +274,10 @@ SysTick_Handler WWDG_IRQHandler B WWDG_IRQHandler - PUBWEAK PVD_AVD_IRQHandler + PUBWEAK PVD_PVM_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -PVD_AVD_IRQHandler - B PVD_AVD_IRQHandler +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler PUBWEAK RTC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) @@ -868,5 +869,10 @@ CORDIC_IRQHandler FMAC_IRQHandler B FMAC_IRQHandler + PUBWEAK LSECSSD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LSECSSD_IRQHandler + B LSECSSD_IRQHandler + END -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/TOOLCHAIN_IAR/stm32u575xi.icf b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/TOOLCHAIN_IAR/stm32u575xi.icf index afba70d1f13..b6e8206523f 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/TOOLCHAIN_IAR/stm32u575xi.icf +++ b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/TOOLCHAIN_IAR/stm32u575xi.icf @@ -18,8 +18,8 @@ /* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ -define symbol VECTORS = 141; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ -define symbol HEAP_SIZE = 0x11000; +define symbol VECTORS = 142; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0x10000; /* Common - Do not change */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/cmsis_nvic.h index dc1aaaf24d2..47849e542c5 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/cmsis_nvic.h @@ -22,7 +22,7 @@ #endif #if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x200000 // 2 MB +#define MBED_ROM_SIZE 0x200000 // 2.0 MB #endif #if !defined(MBED_RAM_START) @@ -30,10 +30,10 @@ #endif #if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0xC0000 // 768 KB +#define MBED_RAM_SIZE 0xc0000 // 768 KB #endif -#define NVIC_NUM_VECTORS 141 +#define NVIC_NUM_VECTORS 142 #define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START #endif diff --git a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/TOOLCHAIN_ARM/startup_stm32u585xx.S b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/TOOLCHAIN_ARM/startup_stm32u585xx.S index cf3862c55df..0618a5410cd 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/TOOLCHAIN_ARM/startup_stm32u585xx.S +++ b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/TOOLCHAIN_ARM/startup_stm32u585xx.S @@ -11,14 +11,14 @@ ;* After Reset the Cortex-M33 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************* +;* @attention ;* -;*

© Copyright (c) 2021 STMicroelectronics. -;* All rights reserved.

+;* Copyright (c) 2021 STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ;* ;******************************************************************************* ;* <<< Use Configuration Wizard in Context Menu >>> @@ -52,7 +52,7 @@ __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection Interrupt + DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection Interrupt DCD RTC_IRQHandler ; RTC non-secure interrupt DCD RTC_S_IRQHandler ; RTC secure interrupt DCD TAMP_IRQHandler ; Tamper non-secure interrupt @@ -131,7 +131,7 @@ __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; DCD PWR_S3WU_IRQHandler ; PWR wake up from Stop3 interrupt DCD SDMMC1_IRQHandler ; SDMMC1 global interrupt DCD SDMMC2_IRQHandler ; SDMMC2 global interrupt - DCD GPDMA1_Channel8_IRQHandler ; GPDMA Channel 8 global interrupt + DCD GPDMA1_Channel8_IRQHandler ; GPDMA1 Channel 8 global interrupt DCD GPDMA1_Channel9_IRQHandler ; GPDMA1 Channel 9 global interrupt DCD GPDMA1_Channel10_IRQHandler ; GPDMA1 Channel 10 global interrupt DCD GPDMA1_Channel11_IRQHandler ; GPDMA1 Channel 11 global interrupt @@ -176,6 +176,7 @@ __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; DCD MDF1_FLT5_IRQHandler ; MDF1 Filter 5 global interrupt DCD CORDIC_IRQHandler ; CORDIC global interrupt DCD FMAC_IRQHandler ; FMAC global interrupt + DCD LSECSSD_IRQHandler ; LSECSSD global interrupt __Vectors_End @@ -254,7 +255,7 @@ SysTick_Handler\ Default_Handler PROC EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_AVD_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] EXPORT RTC_IRQHandler [WEAK] EXPORT RTC_S_IRQHandler [WEAK] EXPORT TAMP_IRQHandler [WEAK] @@ -378,9 +379,10 @@ Default_Handler PROC EXPORT MDF1_FLT5_IRQHandler [WEAK] EXPORT CORDIC_IRQHandler [WEAK] EXPORT FMAC_IRQHandler [WEAK] + EXPORT LSECSSD_IRQHandler [WEAK] WWDG_IRQHandler -PVD_AVD_IRQHandler +PVD_PVM_IRQHandler RTC_IRQHandler RTC_S_IRQHandler TAMP_IRQHandler @@ -504,6 +506,7 @@ MDF1_FLT4_IRQHandler MDF1_FLT5_IRQHandler CORDIC_IRQHandler FMAC_IRQHandler +LSECSSD_IRQHandler B . @@ -516,5 +519,3 @@ FMAC_IRQHandler ;******************************************************************************* END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/TOOLCHAIN_GCC_ARM/startup_stm32u585xx.S b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/TOOLCHAIN_GCC_ARM/startup_stm32u585xx.S index 756db9a4406..abfe8279ab4 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/TOOLCHAIN_GCC_ARM/startup_stm32u585xx.S +++ b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/TOOLCHAIN_GCC_ARM/startup_stm32u585xx.S @@ -12,18 +12,17 @@ * calls main()). * After Reset the Cortex-M33 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** + ******************************************************************************* * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * - ****************************************************************************** + ******************************************************************************* */ .syntax unified @@ -61,6 +60,8 @@ defined in linker script */ .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 @@ -90,8 +91,6 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss -/* Call the clock system initialization function.*/ - bl SystemInit bl _start bx lr @@ -143,7 +142,7 @@ g_pfnVectors: .word PendSV_Handler .word SysTick_Handler .word WWDG_IRQHandler - .word PVD_AVD_IRQHandler + .word PVD_PVM_IRQHandler .word RTC_IRQHandler .word RTC_S_IRQHandler .word TAMP_IRQHandler @@ -267,6 +266,7 @@ g_pfnVectors: .word MDF1_FLT5_IRQHandler .word CORDIC_IRQHandler .word FMAC_IRQHandler + .word LSECSSD_IRQHandler /******************************************************************************* @@ -310,8 +310,8 @@ g_pfnVectors: .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler - .weak PVD_AVD_IRQHandler - .thumb_set PVD_AVD_IRQHandler,Default_Handler + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler .weak RTC_IRQHandler .thumb_set RTC_IRQHandler,Default_Handler @@ -537,13 +537,13 @@ g_pfnVectors: .weak OCTOSPI1_IRQHandler .thumb_set OCTOSPI1_IRQHandler,Default_Handler - + .weak PWR_S3WU_IRQHandler .thumb_set PWR_S3WU_IRQHandler,Default_Handler .weak SDMMC1_IRQHandler .thumb_set SDMMC1_IRQHandler,Default_Handler - + .weak SDMMC2_IRQHandler .thumb_set SDMMC2_IRQHandler,Default_Handler @@ -633,53 +633,55 @@ g_pfnVectors: .weak OTFDEC1_IRQHandler .thumb_set OTFDEC1_IRQHandler,Default_Handler - + .weak OTFDEC2_IRQHandler .thumb_set OTFDEC2_IRQHandler,Default_Handler - + .weak LPTIM4_IRQHandler .thumb_set LPTIM4_IRQHandler,Default_Handler - + .weak DCACHE1_IRQHandler .thumb_set DCACHE1_IRQHandler,Default_Handler - + .weak ADF1_IRQHandler .thumb_set ADF1_IRQHandler,Default_Handler - + .weak ADC4_IRQHandler .thumb_set ADC4_IRQHandler,Default_Handler - + .weak LPDMA1_Channel0_IRQHandler .thumb_set LPDMA1_Channel0_IRQHandler,Default_Handler - + .weak LPDMA1_Channel1_IRQHandler .thumb_set LPDMA1_Channel1_IRQHandler,Default_Handler - + .weak LPDMA1_Channel2_IRQHandler .thumb_set LPDMA1_Channel2_IRQHandler,Default_Handler - + .weak LPDMA1_Channel3_IRQHandler .thumb_set LPDMA1_Channel3_IRQHandler,Default_Handler - + .weak DMA2D_IRQHandler .thumb_set DMA2D_IRQHandler,Default_Handler - + .weak DCMI_PSSI_IRQHandler .thumb_set DCMI_PSSI_IRQHandler,Default_Handler - + .weak OCTOSPI2_IRQHandler .thumb_set OCTOSPI2_IRQHandler,Default_Handler - + .weak MDF1_FLT4_IRQHandler .thumb_set MDF1_FLT4_IRQHandler,Default_Handler - + .weak MDF1_FLT5_IRQHandler .thumb_set MDF1_FLT5_IRQHandler,Default_Handler - + .weak CORDIC_IRQHandler .thumb_set CORDIC_IRQHandler,Default_Handler - + .weak FMAC_IRQHandler .thumb_set FMAC_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + .weak LSECSSD_IRQHandler + .thumb_set LSECSSD_IRQHandler,Default_Handler + diff --git a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/TOOLCHAIN_IAR/startup_stm32u585xx.S b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/TOOLCHAIN_IAR/startup_stm32u585xx.S index 7e74ada68d5..865cb5f0e03 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/TOOLCHAIN_IAR/startup_stm32u585xx.S +++ b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/TOOLCHAIN_IAR/startup_stm32u585xx.S @@ -11,15 +11,15 @@ ;* calls main()). ;* After Reset the Cortex-M33 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** +;******************************************************************************* +;* @attention ;* -;*

© Copyright (c) 2021 STMicroelectronics. -;* All rights reserved.

+;* Copyright (c) 2021 STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ;* ;******************************************************************************* ; @@ -75,7 +75,7 @@ __vector_table ; External Interrupts DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection Interrupt + DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection Interrupt DCD RTC_IRQHandler ; RTC non-secure interrupt DCD RTC_S_IRQHandler ; RTC secure interrupt DCD TAMP_IRQHandler ; Tamper non-secure interrupt @@ -199,6 +199,7 @@ __vector_table DCD MDF1_FLT5_IRQHandler ; MDF1 Filter 5 global interrupt DCD CORDIC_IRQHandler ; CORDIC global interrupt DCD FMAC_IRQHandler ; FMAC global interrupt + DCD LSECSSD_IRQHandler ; LSECSSD global interrupt __Vectors_End @@ -273,10 +274,10 @@ SysTick_Handler WWDG_IRQHandler B WWDG_IRQHandler - PUBWEAK PVD_AVD_IRQHandler + PUBWEAK PVD_PVM_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -PVD_AVD_IRQHandler - B PVD_AVD_IRQHandler +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler PUBWEAK RTC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) @@ -893,5 +894,9 @@ CORDIC_IRQHandler FMAC_IRQHandler B FMAC_IRQHandler + PUBWEAK LSECSSD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LSECSSD_IRQHandler + B LSECSSD_IRQHandler + END -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/TOOLCHAIN_IAR/stm32u585xi.icf b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/TOOLCHAIN_IAR/stm32u585xi.icf index afba70d1f13..b6e8206523f 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/TOOLCHAIN_IAR/stm32u585xi.icf +++ b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/TOOLCHAIN_IAR/stm32u585xi.icf @@ -18,8 +18,8 @@ /* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ -define symbol VECTORS = 141; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ -define symbol HEAP_SIZE = 0x11000; +define symbol VECTORS = 142; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0x10000; /* Common - Do not change */ diff --git a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/cmsis_nvic.h index dc1aaaf24d2..47849e542c5 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/cmsis_nvic.h @@ -22,7 +22,7 @@ #endif #if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x200000 // 2 MB +#define MBED_ROM_SIZE 0x200000 // 2.0 MB #endif #if !defined(MBED_RAM_START) @@ -30,10 +30,10 @@ #endif #if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0xC0000 // 768 KB +#define MBED_RAM_SIZE 0xc0000 // 768 KB #endif -#define NVIC_NUM_VECTORS 141 +#define NVIC_NUM_VECTORS 142 #define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START #endif diff --git a/targets/TARGET_STM/stm_spi_api.c b/targets/TARGET_STM/stm_spi_api.c index 61bec6352f1..70f10557fd2 100644 --- a/targets/TARGET_STM/stm_spi_api.c +++ b/targets/TARGET_STM/stm_spi_api.c @@ -70,8 +70,12 @@ #define TIMEOUT_1_BYTE 10 #if defined(SPI_FLAG_FRLVL) // STM32F0 STM32F3 STM32F7 STM32L4 +#if defined(STM32U5) +extern HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi); +#else extern HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi); #endif +#endif #if defined(SPI_DATASIZE_17BIT) || defined(SPI_DATASIZE_18BIT) || defined(SPI_DATASIZE_19BIT) || defined(SPI_DATASIZE_20BIT) || \ defined(SPI_DATASIZE_21BIT) || defined(SPI_DATASIZE_22BIT) || defined(SPI_DATASIZE_23BIT) || defined(SPI_DATASIZE_24BIT) || \