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stm32h7.c hardcodes PLL_BASE to 5 MHz causing timing errors #147

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calithameridi opened this issue Feb 7, 2024 · 3 comments · Fixed by #148 · May be fixed by calithameridi/danger-klipper#1
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stm32h7.c hardcodes PLL_BASE to 5 MHz causing timing errors #147

calithameridi opened this issue Feb 7, 2024 · 3 comments · Fixed by #148 · May be fixed by calithameridi/danger-klipper#1

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@calithameridi
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calithameridi commented Feb 7, 2024 •
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Clock configuration on stm32h7 hardcodes a PLL_BASE of 5 MHz due to an implicit assumption that HSE is a 25 MHz crystal oscillator, which works for BTT Octopus Pro and Kraken boards. Unfortunately this breaks timing on boards without 25 MHz (e.g. Corevus-G v0.4 with a 12 MHz on HSE) — for example, all moves execute at 20% greater velocity, and more critically a clock frequency above 2^(32) / (10 s) = 429 MHz causes integer overflow errors.

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@calithameridi calithameridi changed the title stm32h7.c hardcodes stm32h7.c hardcodes PLL_BASE to 5 MHz causing timing errors Feb 7, 2024
@calithameridi
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I find that bodging the value of pll_base to 4 MHz allows me to successfully build an image with 400 MHz clock. Obviously this is not a permanent fix although it may suffice in providing pre-built firmware images to Corevus beta-testers

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This was referenced Feb 7, 2024
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@Fisheiyy
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Fisheiyy commented Feb 8, 2024

This would also be good to PR into mainline klipper and fix it for EVERYONE, not just DK

@calithameridi
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This would also be good to PR into mainline klipper and fix it for EVERYONE, not just DK

yeah but they don't have a convenient way of reporting issues

@calithameridi calithameridi mentioned this issue Jun 25, 2024
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Update stm32h7.c calithameridi/danger-klipper
Update stm32h7.c calithameridi/danger-klipper
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@Fisheiyy @calithameridi