diff --git a/include/libopencm3/usb/dwc/otg_common.h b/include/libopencm3/usb/dwc/otg_common.h index e196eaf534..288b754447 100644 --- a/include/libopencm3/usb/dwc/otg_common.h +++ b/include/libopencm3/usb/dwc/otg_common.h @@ -27,63 +27,63 @@ #define LIBOPENCM3_USB_DWC_OTG_COMMON_H /* Core Global Control and Status Registers */ -#define OTG_GOTGCTL 0x000 -#define OTG_GOTGINT 0x004 -#define OTG_GAHBCFG 0x008 -#define OTG_GUSBCFG 0x00C -#define OTG_GRSTCTL 0x010 -#define OTG_GINTSTS 0x014 -#define OTG_GINTMSK 0x018 -#define OTG_GRXSTSR 0x01C -#define OTG_GRXSTSP 0x020 -#define OTG_GRXFSIZ 0x024 -#define OTG_GNPTXFSIZ 0x028 -#define OTG_GNPTXSTS 0x02C -#define OTG_GCCFG 0x038 -#define OTG_CID 0x03C -#define OTG_HPTXFSIZ 0x100 -#define OTG_DIEPTXF(x) (0x104 + 4*((x)-1)) +#define OTG_GOTGCTL 0x000U +#define OTG_GOTGINT 0x004U +#define OTG_GAHBCFG 0x008U +#define OTG_GUSBCFG 0x00CU +#define OTG_GRSTCTL 0x010U +#define OTG_GINTSTS 0x014U +#define OTG_GINTMSK 0x018U +#define OTG_GRXSTSR 0x01CU +#define OTG_GRXSTSP 0x020U +#define OTG_GRXFSIZ 0x024U +#define OTG_GNPTXFSIZ 0x028U +#define OTG_GNPTXSTS 0x02CU +#define OTG_GCCFG 0x038U +#define OTG_CID 0x03CU +#define OTG_HPTXFSIZ 0x100U +#define OTG_DIEPTXF(x) (0x104U + 4*((x)-1)) /* Host-mode Control and Status Registers */ -#define OTG_HCFG 0x400 -#define OTG_HFIR 0x404 -#define OTG_HFNUM 0x408 -#define OTG_HPTXSTS 0x410 -#define OTG_HAINT 0x414 -#define OTG_HAINTMSK 0x418 -#define OTG_HPRT 0x440 -#define OTG_HCCHAR(x) (0x500 + 0x20*(x)) -#define OTG_HCINT(x) (0x508 + 0x20*(x)) -#define OTG_HCINTMSK(x) (0x50C + 0x20*(x)) -#define OTG_HCTSIZ(x) (0x510 + 0x20*(x)) +#define OTG_HCFG 0x400U +#define OTG_HFIR 0x404U +#define OTG_HFNUM 0x408U +#define OTG_HPTXSTS 0x410U +#define OTG_HAINT 0x414U +#define OTG_HAINTMSK 0x418U +#define OTG_HPRT 0x440U +#define OTG_HCCHAR(x) (0x500U + 0x20*(x)) +#define OTG_HCINT(x) (0x508U + 0x20*(x)) +#define OTG_HCINTMSK(x) (0x50CU + 0x20*(x)) +#define OTG_HCTSIZ(x) (0x510U + 0x20*(x)) /* Device-mode Control and Status Registers */ -#define OTG_DCFG 0x800 -#define OTG_DCTL 0x804 -#define OTG_DSTS 0x808 -#define OTG_DIEPMSK 0x810 -#define OTG_DOEPMSK 0x814 -#define OTG_DAINT 0x818 -#define OTG_DAINTMSK 0x81C -#define OTG_DVBUSDIS 0x828 -#define OTG_DVBUSPULSE 0x82C -#define OTG_DIEPEMPMSK 0x834 - -#define OTG_DIEPCTL0 0x900 -#define OTG_DIEPCTL(x) (0x900 + 0x20*(x)) -#define OTG_DOEPCTL0 0xB00 -#define OTG_DOEPCTL(x) (0xB00 + 0x20*(x)) -#define OTG_DIEPINT(x) (0x908 + 0x20*(x)) -#define OTG_DOEPINT(x) (0xB08 + 0x20*(x)) -#define OTG_DIEPTSIZ0 0x910 -#define OTG_DIEPTSIZ(x) (0x910 + 0x20*(x)) -#define OTG_DOEPTSIZ0 0xB10 -#define OTG_DOEPTSIZ(x) (0xB10 + 0x20*(x)) -#define OTG_DTXFSTS(x) (0x918 + 0x20*(x)) +#define OTG_DCFG 0x800U +#define OTG_DCTL 0x804U +#define OTG_DSTS 0x808U +#define OTG_DIEPMSK 0x810U +#define OTG_DOEPMSK 0x814U +#define OTG_DAINT 0x818U +#define OTG_DAINTMSK 0x81CU +#define OTG_DVBUSDIS 0x828U +#define OTG_DVBUSPULSE 0x82CU +#define OTG_DIEPEMPMSK 0x834U + +#define OTG_DIEPCTL0 0x900U +#define OTG_DIEPCTL(x) (0x900U + 0x20*(x)) +#define OTG_DOEPCTL0 0xB00U +#define OTG_DOEPCTL(x) (0xB00U + 0x20*(x)) +#define OTG_DIEPINT(x) (0x908U + 0x20*(x)) +#define OTG_DOEPINT(x) (0xB08U + 0x20*(x)) +#define OTG_DIEPTSIZ0 0x910U +#define OTG_DIEPTSIZ(x) (0x910U + 0x20*(x)) +#define OTG_DOEPTSIZ0 0xB10U +#define OTG_DOEPTSIZ(x) (0xB10U + 0x20*(x)) +#define OTG_DTXFSTS(x) (0x918U + 0x20*(x)) /* Power and clock gating control and status register */ -#define OTG_PCGCCTL 0xE00 +#define OTG_PCGCCTL 0xE00U /* Data FIFO */ #if defined(STM32H7) @@ -115,19 +115,19 @@ #define OTG_GOTGINT_SEDET (1U << 2U) /* OTG AHB configuration register (OTG_GAHBCFG) */ -#define OTG_GAHBCFG_GINT 0x0001 -#define OTG_GAHBCFG_TXFELVL 0x0080 -#define OTG_GAHBCFG_PTXFELVL 0x0100 +#define OTG_GAHBCFG_GINT (1U << 0U) +#define OTG_GAHBCFG_TXFELVL (1U << 7U) +#define OTG_GAHBCFG_PTXFELVL (1U << 8U) /* OTG USB configuration register (OTG_GUSBCFG) */ -#define OTG_GUSBCFG_TOCAL 0x00000003 -#define OTG_GUSBCFG_SRPCAP 0x00000100 -#define OTG_GUSBCFG_HNPCAP 0x00000200 +#define OTG_GUSBCFG_TOCAL 0x00000003U +#define OTG_GUSBCFG_SRPCAP (1U << 8U) +#define OTG_GUSBCFG_HNPCAP (1U << 9U) #define OTG_GUSBCFG_TRDT_MASK (0xfU << 10U) -#define OTG_GUSBCFG_NPTXRWEN 0x00004000 -#define OTG_GUSBCFG_FHMOD 0x20000000 -#define OTG_GUSBCFG_FDMOD 0x40000000 -#define OTG_GUSBCFG_CTXPKT 0x80000000 +#define OTG_GUSBCFG_NPTXRWEN (1U << 15U) +#define OTG_GUSBCFG_FHMOD (1U << 29U) +#define OTG_GUSBCFG_FDMOD (1U << 30U) +#define OTG_GUSBCFG_CTXPKT (1U << 31U) #define OTG_GUSBCFG_PHYSEL (1U << 6U) /* OTG reset register (OTG_GRSTCTL) */ @@ -176,32 +176,32 @@ #define OTG_GINTSTS_CMOD (1U << 0U) /* OTG interrupt mask register (OTG_GINTMSK) */ -#define OTG_GINTMSK_MMISM 0x00000002 -#define OTG_GINTMSK_OTGINT 0x00000004 -#define OTG_GINTMSK_SOFM 0x00000008 -#define OTG_GINTMSK_RXFLVLM 0x00000010 -#define OTG_GINTMSK_NPTXFEM 0x00000020 -#define OTG_GINTMSK_GINAKEFFM 0x00000040 -#define OTG_GINTMSK_GONAKEFFM 0x00000080 -#define OTG_GINTMSK_ESUSPM 0x00000400 -#define OTG_GINTMSK_USBSUSPM 0x00000800 -#define OTG_GINTMSK_USBRST 0x00001000 -#define OTG_GINTMSK_ENUMDNEM 0x00002000 -#define OTG_GINTMSK_ISOODRPM 0x00004000 -#define OTG_GINTMSK_EOPFM 0x00008000 -#define OTG_GINTMSK_EPMISM 0x00020000 -#define OTG_GINTMSK_IEPINT 0x00040000 -#define OTG_GINTMSK_OEPINT 0x00080000 -#define OTG_GINTMSK_IISOIXFRM 0x00100000 -#define OTG_GINTMSK_IISOOXFRM 0x00200000 -#define OTG_GINTMSK_IPXFRM 0x00200000 -#define OTG_GINTMSK_PRTIM 0x01000000 -#define OTG_GINTMSK_HCIM 0x02000000 -#define OTG_GINTMSK_PTXFEM 0x04000000 -#define OTG_GINTMSK_CIDSCHGM 0x10000000 -#define OTG_GINTMSK_DISCINT 0x20000000 -#define OTG_GINTMSK_SRQIM 0x40000000 -#define OTG_GINTMSK_WUIM 0x80000000 +#define OTG_GINTMSK_MMISM (1U << 1U) +#define OTG_GINTMSK_OTGINT (1U << 2U) +#define OTG_GINTMSK_SOFM (1U << 3U) +#define OTG_GINTMSK_RXFLVLM (1U << 4U) +#define OTG_GINTMSK_NPTXFEM (1U << 5U) +#define OTG_GINTMSK_GINAKEFFM (1U << 6U) +#define OTG_GINTMSK_GONAKEFFM (1U << 7U) +#define OTG_GINTMSK_ESUSPM (1U << 10U) +#define OTG_GINTMSK_USBSUSPM (1U << 11U) +#define OTG_GINTMSK_USBRST (1U << 12U) +#define OTG_GINTMSK_ENUMDNEM (1U << 13U) +#define OTG_GINTMSK_ISOODRPM (1U << 14U) +#define OTG_GINTMSK_EOPFM (1U << 15U) +#define OTG_GINTMSK_EPMISM (1U << 17U) +#define OTG_GINTMSK_IEPINT (1U << 18U) +#define OTG_GINTMSK_OEPINT (1U << 19U) +#define OTG_GINTMSK_IISOIXFRM (1U << 20U) +#define OTG_GINTMSK_IISOOXFRM (1U << 21U) +#define OTG_GINTMSK_IPXFRM (1U << 21U) +#define OTG_GINTMSK_PRTIM (1U << 24U) +#define OTG_GINTMSK_HCIM (1U << 25U) +#define OTG_GINTMSK_PTXFEM (1U << 26U) +#define OTG_GINTMSK_CIDSCHGM (1U << 28U) +#define OTG_GINTMSK_DISCINT (1U << 29U) +#define OTG_GINTMSK_SRQIM (1U << 30U) +#define OTG_GINTMSK_WUIM (1U << 31U) /* OTG Receive Status Pop Register (OTG_GRXSTSP) */ /* Bits 31:25 - Reserved */ @@ -242,7 +242,7 @@ /* Bits 15:0 - Reserved */ /* OTG FS Product ID register (OTG_CID) */ -#define OTG_CID_HAS_VBDEN 0x00002000 +#define OTG_CID_HAS_VBDEN 0x00002000U /* Device-mode CSRs */ /* OTG device control register (OTG_DCTL) */ @@ -258,10 +258,10 @@ #define OTG_DCTL_RWUSIG (1U << 0U) /* OTG device configuration register (OTG_DCFG) */ -#define OTG_DCFG_DSPD 0x0003 -#define OTG_DCFG_NZLSOHSK 0x0004 -#define OTG_DCFG_DAD 0x07F0 -#define OTG_DCFG_PFIVL 0x1800 +#define OTG_DCFG_DSPD 0x00000003U +#define OTG_DCFG_NZLSOHSK 0x00000004U +#define OTG_DCFG_DAD 0x000007F0U +#define OTG_DCFG_PFIVL 0x00001800U /* OTG device status register (OTG_DSTS) */ #define OTG_DSTS_SUSPSTS (1U << 0U) @@ -292,7 +292,7 @@ #define OTG_DOEPMSK_EPDM (1U << 1U) #define OTG_DOEPMSK_XFRCM (1U << 0U) -/* OTG Device Control IN Endpoint 0 Control Register (OTG_DIEPCTL0) */ +/* OTG Device IN Endpoint 0 Control Register (OTG_DIEPCTL0) */ #define OTG_DIEPCTL0_EPENA (1U << 31U) #define OTG_DIEPCTL0_EPDIS (1U << 30U) /* Bits 29:28 - Reserved */ @@ -307,17 +307,18 @@ /* Bit 16 - Reserved */ #define OTG_DIEPCTL0_USBAEP (1U << 15U) /* Bits 14:2 - Reserved */ -#if defined STM32H7 -#define OTG_DIEPCTL0_MPSIZ_MASK (0x000007ffU) -#else #define OTG_DIEPCTL0_MPSIZ_MASK (0x3U << 0U) #define OTG_DIEPCTL0_MPSIZ_64 (0x0U << 0U) #define OTG_DIEPCTL0_MPSIZ_32 (0x1U << 0U) #define OTG_DIEPCTL0_MPSIZ_16 (0x2U << 0U) #define OTG_DIEPCTL0_MPSIZ_8 (0x3U << 0U) -#endif -/* OTG Device Control OUT Endpoint 0 Control Register (OTG_DOEPCTL0) */ +/* OTG Device IN Endpoint X Control Register (OTG_DOEPCTLX) */ +#define OTG_DIEPCTLX_EPTYP_SHIFT 18U +#define OTG_DIEPCTLX_TXFNUM_SHIFT 22U +#define OTG_DIEPCTLX_MPSIZ_MASK (0x000007ffU) + +/* OTG Device OUT Endpoint 0 Control Register (OTG_DOEPCTL0) */ #define OTG_DOEPCTL0_EPENA (1U << 31U) #define OTG_DOEPCTL0_EPDIS (1U << 30U) /* Bits 29:28 - Reserved */ @@ -327,16 +328,19 @@ /* Bits 25:22 - Reserved */ #define OTG_DOEPCTL0_STALL (1U << 21U) #define OTG_DOEPCTL0_SNPM (1U << 20U) -#define OTG_DOEPCTL0_EPTYP_MASK (0x3U << 18U) +#define OTG_DOEPCTL0_EPTYP_MASK (0x3U << 18U) #define OTG_DOEPCTL0_NAKSTS (1U << 17U) /* Bit 16 - Reserved */ #define OTG_DOEPCTL0_USBAEP (1U << 15U) /* Bits 14:2 - Reserved */ -#define OTG_DOEPCTL0_MPSIZ_MASK (0x3U << 0U) -#define OTG_DOEPCTL0_MPSIZ_64 (0x0U << 0U) -#define OTG_DOEPCTL0_MPSIZ_32 (0x1U << 0U) -#define OTG_DOEPCTL0_MPSIZ_16 (0x2U << 0U) -#define OTG_DOEPCTL0_MPSIZ_8 (0x3U << 0U) +#define OTG_DOEPCTL0_MPSIZ_MASK (0x3U << 0U) +#define OTG_DOEPCTL0_MPSIZ_64 (0x0U << 0U) +#define OTG_DOEPCTL0_MPSIZ_32 (0x1U << 0U) +#define OTG_DOEPCTL0_MPSIZ_16 (0x2U << 0U) +#define OTG_DOEPCTL0_MPSIZ_8 (0x3U << 0U) + +/* OTG Device OUT Endpoint X Control Register (OTG_DOEPCTLX) */ +#define OTG_DOEPCTLX_MPSIZ_MASK (0x000007ffU) /* OTG Device IN Endpoint Interrupt Register (OTG_DIEPINTx) */ /* Bits 31:8 - Reserved */ @@ -368,19 +372,21 @@ /* Bits 28:20 - Reserved */ #define OTG_DIEPSIZ0_PKTCNT (1U << 19U) /* Bits 18:7 - Reserved */ -#define OTG_DIEPSIZ0_XFRSIZ_MASK (0x7fU << 0U) +#define OTG_DIEPSIZ0_XFRSIZ_MASK (0x0000007fU) +/* OTG Device OUT Endpoint X Transfer Size Register (OTG_DOEPTSIZX) */ +#define OTG_DIEPSIZX_XFRSIZ_MASK (0x0007ffffU) /* Host-mode CSRs */ /* OTG Host non-periodic transmit FIFO size register (OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_DIEPTXF0) */ -#define OTG_HNPTXFSIZ_PTXFD_MASK (0xffff0000) -#define OTG_HNPTXFSIZ_PTXSA_MASK (0x0000ffff) +#define OTG_HNPTXFSIZ_PTXFD_MASK (0xffff0000U) +#define OTG_HNPTXFSIZ_PTXSA_MASK (0x0000ffffU) /* OTG Host periodic transmit FIFO size register (OTG_HPTXFSIZ) */ -#define OTG_HPTXFSIZ_PTXFD_MASK (0xffff0000) -#define OTG_HPTXFSIZ_PTXSA_MASK (0x0000ffff) +#define OTG_HPTXFSIZ_PTXFD_MASK (0xffff0000U) +#define OTG_HPTXFSIZ_PTXSA_MASK (0x0000ffffU) /* OTG Host Configuration Register (OTG_HCFG) */ /* Bits 31:3 - Reserved */ @@ -391,14 +397,14 @@ /* OTG Host Frame Interval Register (OTG_HFIR) */ /* Bits 31:16 - Reserved */ -#define OTG_HFIR_FRIVL_MASK (0x0000ffff) +#define OTG_HFIR_FRIVL_MASK (0x0000ffffU) /* OTG Host frame number/frame time remaining register (OTG_HFNUM) */ -#define OTG_HFNUM_FTREM_MASK (0xffff0000) -#define OTG_HFNUM_FRNUM_MASK (0x0000ffff) +#define OTG_HFNUM_FTREM_MASK (0xffff0000U) +#define OTG_HFNUM_FRNUM_MASK (0x0000ffffU) /* OTG Host periodic transmit FIFO/queue status register (OTG_HPTXSTS) */ -#define OTG_HPTXSTS_PTXQTOP_MASK (0xff000000) +#define OTG_HPTXSTS_PTXQTOP_MASK (0xff000000U) #define OTG_HPTXSTS_PTXQTOP_ODDFRM (1U << 31U) #define OTG_HPTXSTS_PTXQTOP_EVENFRM (0U << 31U) #define OTG_HPTXSTS_PTXQTOP_CHANNEL_NUMBER_MASK (0xfU << 27U) @@ -407,16 +413,16 @@ #define OTG_HPTXSTS_PTXQTOP_TYPE_ZEROLENGTH (0x01U << 25U) #define OTG_HPTXSTS_PTXQTOP_TYPE_DISABLECMD (0x11U << 25U) #define OTG_HPTXSTS_PTXQTOP_TERMINATE (1U << 24U) -#define OTG_HPTXSTS_PTXQSAV_MASK (0x00ff0000) -#define OTG_HPTXSTS_PTXFSAVL_MASK (0x0000ffff) +#define OTG_HPTXSTS_PTXQSAV_MASK (0x00ff0000U) +#define OTG_HPTXSTS_PTXFSAVL_MASK (0x0000ffffU) /* OTG Host all channels interrupt mask register (OTG_HAINT) */ /* Bits 31:16 - Reserved */ -#define OTG_HAINTMSK_HAINT_MASK (0x0000ffff) +#define OTG_HAINTMSK_HAINT_MASK (0x0000ffffU) /* OTG Host all channels interrupt mask register (OTG_HAINTMSK) */ /* Bits 31:16 - Reserved */ -#define OTG_HAINTMSK_HAINTM_MASK (0x0000ffff) +#define OTG_HAINTMSK_HAINTM_MASK (0x0000ffffU) /* OTG Host port control and status register (OTG_HPRT) */ /* Bits 31:19 - Reserved */ @@ -464,7 +470,7 @@ #define OTG_HCCHAR_EPDIR_IN (1U << 15U) #define OTG_HCCHAR_EPDIR_MASK (1U << 15U) #define OTG_HCCHAR_EPNUM_MASK (0xfU << 11U) -#define OTG_HCCHAR_MPSIZ_MASK (0x7ffU << 0U) +#define OTG_HCCHAR_MPSIZ_MASK (0x000007ffU) /* OTG Host channel-x interrupt register (OTG_HCINTx) */ /* Bits 31:11 - Reserved */ @@ -507,7 +513,7 @@ #define OTG_HCTSIZ_DPID_MDATA (0x3U << 29U) #define OTG_HCTSIZ_DPID_MASK (0x3U << 29U) #define OTG_HCTSIZ_PKTCNT_MASK (0x3ffU << 19U) -#define OTG_HCTSIZ_XFRSIZ_MASK (0x7ffffU << 0U) +#define OTG_HCTSIZ_XFRSIZ_MASK (0x0007ffffU) diff --git a/lib/usb/usb_dwc_common.c b/lib/usb/usb_dwc_common.c index b62ba273d2..6978b16521 100644 --- a/lib/usb/usb_dwc_common.c +++ b/lib/usb/usb_dwc_common.c @@ -50,7 +50,7 @@ void dwc_ep_setup(usbd_device *const usbd_dev, const uint8_t addr, const uint8_t #if defined(STM32H7) /* Do not initially arm the IN endpoint - we've got nothing to send the host at first */ REBASE(OTG_DIEPTSIZ(0)) = 0; - REBASE(OTG_DIEPCTL(0)) = (max_size & OTG_DIEPCTL0_MPSIZ_MASK) | OTG_DIEPCTL0_SNAK | OTG_DIEPCTL0_USBAEP; + REBASE(OTG_DIEPCTL(0)) = (max_size & OTG_DIEPCTLX_MPSIZ_MASK) | OTG_DIEPCTL0_SNAK | OTG_DIEPCTL0_USBAEP; #else if (max_size >= 64) { REBASE(OTG_DIEPCTL0) = OTG_DIEPCTL0_MPSIZ_64;