From bfde640475a3009a78863441c90e06c8f91ee701 Mon Sep 17 00:00:00 2001 From: dragonmux Date: Fri, 26 Apr 2024 10:50:15 +0100 Subject: [PATCH] stm32/h7: Fixed an issue with the naming of the D2CCIP2R selector constant for some of the USARTs --- include/libopencm3/stm32/h7/rcc.h | 2 +- lib/stm32/h7/rcc.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/libopencm3/stm32/h7/rcc.h b/include/libopencm3/stm32/h7/rcc.h index d390a43770..abdb12625f 100644 --- a/include/libopencm3/stm32/h7/rcc.h +++ b/include/libopencm3/stm32/h7/rcc.h @@ -414,7 +414,7 @@ LGPL License Terms @ref lgpl_license #define RCC_D2CCIP2R_I2C123SEL_SHIFT 12U #define RCC_D2CCIP2R_RNGSEL_MASK 0x3U #define RCC_D2CCIP2R_RNGSEL_SHIFT 8U -#define RCC_D2CCIP2R_USART16SEL_SHIFT 3U +#define RCC_D2CCIP2R_USART16910SEL_SHIFT 3U #define RCC_D2CCIP2R_USART234578SEL_SHIFT 0U #define RCC_D2CCIP2R_USARTSEL_MASK 7U diff --git a/lib/stm32/h7/rcc.c b/lib/stm32/h7/rcc.c index 5c5ef27628..163d14a5f0 100644 --- a/lib/stm32/h7/rcc.c +++ b/lib/stm32/h7/rcc.c @@ -272,7 +272,7 @@ uint32_t rcc_get_usart_clk_freq(uint32_t usart) uint32_t clksel, pclk; if (usart == USART1_BASE || usart == USART6_BASE) { pclk = rcc_clock_tree.per.pclk2_mhz * HZ_PER_MHZ;; - clksel = (RCC_D2CCIP2R >> RCC_D2CCIP2R_USART16SEL_SHIFT) & RCC_D2CCIP2R_USARTSEL_MASK; + clksel = (RCC_D2CCIP2R >> RCC_D2CCIP2R_USART16910SEL_SHIFT) & RCC_D2CCIP2R_USARTSEL_MASK; } else { pclk = rcc_clock_tree.per.pclk1_mhz * HZ_PER_MHZ; clksel = (RCC_D2CCIP2R >> RCC_D2CCIP2R_USART234578SEL_SHIFT) & RCC_D2CCIP2R_USARTSEL_MASK; @@ -404,8 +404,8 @@ void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel) { case UART9_BASE: case USART10_BASE: reg = &RCC_D2CCIP2R; - mask = RCC_D2CCIP2R_USARTSEL_MASK << RCC_D2CCIP2R_USART16SEL_SHIFT; - val = sel << RCC_D2CCIP2R_USART16SEL_SHIFT; + mask = RCC_D2CCIP2R_USARTSEL_MASK << RCC_D2CCIP2R_USART16910SEL_SHIFT; + val = sel << RCC_D2CCIP2R_USART16910SEL_SHIFT; break; case USART2_BASE: case USART3_BASE: