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Hi everyone,
it is quite amazing what you have created here with this project, and that you share all this with other developers.
In the last days I have been reading here on this site and also on the project web site about the features of the native HW 2.3 and the latest FW version - trying to find out, if the BMP could help me with some of my projects. Especially the RTT is a very interesting part. However, I would have planned to use it mainly for dumping out profiling and binary log data instead of the printf-style logging.
Now it looks like - at least from the source code - that for RTT only the channel 0 is supported, for terminal input and output. Adding additional RTT channels would probably also require adding additional devices on the USB interface to the host, to get these data out.
The flash on the GD F103 seems already quite filled, so I had wondered if there are any plans to move to a larger MCU in future designs?
I haven't found how long the current HW V2.3 is now available, so this question for a new HW may be silly.
Another question, that had popped-up: has it been considered to use the SPI of the platform-MCU for the JTAG/SWD signals and protocols instead of bit-banging, to speed-up the access to the target-MCU? Or are there any limitations or pitfalls that make this too tricky?
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Hi everyone,
it is quite amazing what you have created here with this project, and that you share all this with other developers.
In the last days I have been reading here on this site and also on the project web site about the features of the native HW 2.3 and the latest FW version - trying to find out, if the BMP could help me with some of my projects. Especially the RTT is a very interesting part. However, I would have planned to use it mainly for dumping out profiling and binary log data instead of the printf-style logging.
Now it looks like - at least from the source code - that for RTT only the channel 0 is supported, for terminal input and output. Adding additional RTT channels would probably also require adding additional devices on the USB interface to the host, to get these data out.
The flash on the GD F103 seems already quite filled, so I had wondered if there are any plans to move to a larger MCU in future designs?
I haven't found how long the current HW V2.3 is now available, so this question for a new HW may be silly.
Another question, that had popped-up: has it been considered to use the SPI of the platform-MCU for the JTAG/SWD signals and protocols instead of bit-banging, to speed-up the access to the target-MCU? Or are there any limitations or pitfalls that make this too tricky?
Best regards,
Philipp
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