From aa71bdcd306563bd3f4c37f84d978637f1a00e67 Mon Sep 17 00:00:00 2001 From: ALTracer Date: Sat, 23 Sep 2023 21:03:13 +0300 Subject: [PATCH] stm32mp15: Rename macros for SRAM base addresses (CM4 side) --- src/target/stm32mp15.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/target/stm32mp15.c b/src/target/stm32mp15.c index 99955cc6465..ae11884486c 100644 --- a/src/target/stm32mp15.c +++ b/src/target/stm32mp15.c @@ -33,10 +33,10 @@ #include "cortexm.h" /* Memory map constants for STM32MP15x */ -#define STM32MP15_RETRAM_BASE 0x00000000U -#define STM32MP15_RETRAM_SIZE 0x00001000U /* RETRAM, 64 KiB */ -#define STM32MP15_AHBSRAM_BASE 0x10000000U -#define STM32MP15_AHBSRAM_SIZE 0x00060000U /* AHB SRAM 1+2+3+4, 128+128+64+64 KiB */ +#define STM32MP15_CM4_RETRAM_BASE 0x00000000U +#define STM32MP15_RETRAM_SIZE 0x00001000U /* RETRAM, 64 KiB */ +#define STM32MP15_CM4_AHBSRAM_BASE 0x10000000U +#define STM32MP15_AHBSRAM_SIZE 0x00060000U /* AHB SRAM 1+2+3+4, 128+128+64+64 KiB */ /* Access from processor address space. * Access via the debug APB is at 0xe0081000 over AP1. */ @@ -105,8 +105,8 @@ bool stm32mp15_cm4_probe(target_s *target) target->target_storage = priv; /* Figure 4. Memory map from ยง2.5.2 in RM0436 rev 6, pg158 */ - target_add_ram(target, STM32MP15_RETRAM_BASE, STM32MP15_RETRAM_SIZE); - target_add_ram(target, STM32MP15_AHBSRAM_BASE, STM32MP15_AHBSRAM_SIZE); + target_add_ram(target, STM32MP15_CM4_RETRAM_BASE, STM32MP15_RETRAM_SIZE); + target_add_ram(target, STM32MP15_CM4_AHBSRAM_BASE, STM32MP15_AHBSRAM_SIZE); return true; }