diff --git a/src/target/riscv_debug.c b/src/target/riscv_debug.c
index 13b4eb9e4a7..44ec9e42c8b 100644
--- a/src/target/riscv_debug.c
+++ b/src/target/riscv_debug.c
@@ -380,6 +380,7 @@ static bool riscv_hart_init(riscv_hart_s *const hart)
 
 	/* If the hart implements mvendorid, this gives us the JEP-106, otherwise use the DTM designer code */
 	target->designer_code = hart->vendorid ? hart->vendorid : hart->dbg_module->dmi_bus->designer_code;
+	target->cpuid = hart->archid;
 
 	riscv_hart_discover_triggers(hart);
 
diff --git a/src/target/stm32f1.c b/src/target/stm32f1.c
index 1b70914eb67..48c34e98ed6 100644
--- a/src/target/stm32f1.c
+++ b/src/target/stm32f1.c
@@ -184,6 +184,10 @@ bool gd32f1_probe(target_s *target)
 /* Identify RISC-V GD32VF1 chips */
 bool gd32vf1_probe(target_s *const target)
 {
+	/* Make sure the architecture ID matches */
+	if (target->cpuid != 0x80000022U)
+		return false;
+	/* Then read out the device ID */
 	const uint16_t device_id = target_mem_read32(target, DBGMCU_IDCODE) & 0xfffU;
 	switch (device_id) {
 	case 0x410U: /* GD32VF103 */