Display.vf

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 14.7
//  \   \         Application : sch2hdl
//  /   /         Filename : Display.vf
// /___/   /\     Timestamp : 11/17/2019 17:57:40
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: sch2hdl -sympath C:/Users/z/Documents/Projects/pipeline-cpu/ipcore_dir -intstyle ise -family kintex7 -verilog C:/Users/z/Documents/Projects/pipeline-cpu/Display.vf -w C:/Users/z/Documents/Projects/pipeline-cpu/Display.sch
//Design Name: Display
//Device: kintex7
//Purpose:
//    This verilog netlist is translated from an ECS schematic.It can be 
//    synthesized and simulated, but it should not be modified. 
//
`timescale 1ns / 1ps

module Display(clk, 
               flash, 
               Hexs, 
               LES, 
               point, 
               rst, 
               Start, 
               Text, 
               SEGCLK, 
               SEGCLR, 
               SEGEN, 
               SEGOUT);

    input clk;
    input flash;
    input [31:0] Hexs;
    input [7:0] LES;
    input [7:0] point;
    input rst;
    input Start;
    input Text;
   output SEGCLK;
   output SEGCLR;
   output SEGEN;
   output SEGOUT;
   
   wire [63:0] XLXN_17;
   wire [63:0] XLXN_18;
   wire [63:0] XLXN_19;
   
   HexTo8SEG  XLXI_1 (.flash(flash), 
                     .Hexs(Hexs[31:0]), 
                     .LES(LES[7:0]), 
                     .point(point[7:0]), 
                     .SEG_TXT(XLXN_19[63:0]));
   MUX2T1_64  XLXI_4 (.I0(XLXN_18[63:0]), 
                     .I1(XLXN_19[63:0]), 
                     .sel(Text), 
                     .o(XLXN_17[63:0]));
   SSeg_map  XLXI_5 (.Disp_num({Hexs[31:0], Hexs[31:0]}), 
                    .SSeg_map(XLXN_18[63:0]));
   P2S  XLXI_6 (.clk(clk), 
               .P_Data(XLXN_17[63:0]), 
               .rst(rst), 
               .Serial(Start), 
               .EN(SEGEN), 
               .sout(SEGOUT), 
               .s_clk(SEGCLK), 
               .s_clrn(SEGCLR));
endmodule