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Once we design the network structure within the FPGA, can we adjust the order and number of network layers in Jupyter Notebook as we want? Or do we need to change the network hardware in the FPGA when we change the network structure in Jupyter Notebook? I hope I could explain my question. Thank you for your answer.
The text was updated successfully, but these errors were encountered:
You would need to change both the python front end and the FPGA IP cores. Regarding the python front end you need to change the network description of both the jupyter notebook and the conv_fpga.py. Regarding the backend you need to synthesise your own FPGA bitstreams
Once we design the network structure within the FPGA, can we adjust the order and number of network layers in Jupyter Notebook as we want? Or do we need to change the network hardware in the FPGA when we change the network structure in Jupyter Notebook? I hope I could explain my question. Thank you for your answer.
The text was updated successfully, but these errors were encountered: