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hw-microdiff.kicad_pro
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hw-microdiff.kicad_pro
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"missing_courtyard": "ignore",
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"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
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"shorting_items": "error",
"silk_over_copper": "ignore",
"silk_overlap": "ignore",
"skew_out_of_range": "error",
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"too_many_vias": "error",
"track_dangling": "warning",
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"tracks_crossing": "error",
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"min_clearance": 0.0,
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"min_hole_clearance": 0.25,
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"min_microvia_diameter": 0.19999999999999998,
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"min_silk_clearance": 0.0,
"min_through_hole_diameter": 0.3,
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"boards": [],
"cvpcb": {
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"rule_severities": {
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"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
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"global_label_dangling": "warning",
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"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
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"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unannotated": "error",
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"diff_pair_width": 0.2,
"line_style": 0,
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"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
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"pcbnew": {
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"vrml": "hw-microdiff.wrl"
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"drawing": {
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"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
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"junction_size_choice": 3,
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"spice_external_command": "spice \"%I\"",
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"sheets": [
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],
"text_variables": {}
}