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vivado_16052.backup.jou
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vivado_16052.backup.jou
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#-----------------------------------------------------------
# Vivado v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Wed Dec 14 21:54:32 2022
# Process ID: 16052
# Current directory: C:/Xilinx/projects/Bidirectional_Transmitter
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent16504 C:\Xilinx\projects\Bidirectional_Transmitter\Bidirectional_Transmitter.xpr
# Log file: C:/Xilinx/projects/Bidirectional_Transmitter/vivado.log
# Journal file: C:/Xilinx/projects/Bidirectional_Transmitter\vivado.jou
#-----------------------------------------------------------
start_gui
open_project C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.xpr
update_compile_order -fileset sources_1
open_bd_design {C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd}
close [ open C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/new/gpio_parse.v w ]
add_files C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/new/gpio_parse.v
update_compile_order -fileset sources_1
startgroup
set_property -dict [list CONFIG.C_GPIO_WIDTH {10}] [get_bd_cells axi_gpio_0]
endgroup
create_bd_cell -type module -reference gpio_parse gpio_parse_0
delete_bd_objs [get_bd_nets axi_gpio_0_gpio_io_o]
connect_bd_net [get_bd_pins UART_Transmitter_0/tx_axgpio] [get_bd_pins gpio_parse_0/tx_gpio]
connect_bd_net [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins gpio_parse_0/gpio_in]
save_bd_design
update_compile_order -fileset sources_1
regenerate_bd_layout
startgroup
make_bd_pins_external [get_bd_pins gpio_parse_0/din_gpio]
endgroup
set_property name din_gpio [get_bd_ports din_gpio_0]
save_bd_design
regenerate_bd_layout
validate_bd_design
save_bd_design
reset_run synth_1
reset_run Bidirectional_Transmitter_axi_gpio_0_0_synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
wait_on_run impl_1
reset_run synth_1
reset_run Bidirectional_Transmitter_axi_gpio_0_0_synth_1
reset_run Bidirectional_Transmitter_gpio_parse_0_0_synth_1
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.3 xadc_wiz_0
endgroup
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config { Clk_master {/processing_system7_0/FCLK_CLK0 (50 MHz)} Clk_slave {Auto} Clk_xbar {/processing_system7_0/FCLK_CLK0 (50 MHz)} Master {/processing_system7_0/M_AXI_GP0} Slave {/xadc_wiz_0/s_axi_lite} intc_ip {/ps7_0_axi_periph} master_apm {0}} [get_bd_intf_pins xadc_wiz_0/s_axi_lite]
validate_bd_design
regenerate_bd_layout
startgroup
set_property -dict [list CONFIG.XADC_STARUP_SELECTION {channel_sequencer} CONFIG.ADC_CONVERSION_RATE {962} CONFIG.OT_ALARM {false} CONFIG.USER_TEMP_ALARM {false} CONFIG.VCCINT_ALARM {false} CONFIG.VCCAUX_ALARM {false} CONFIG.ENABLE_VCCPINT_ALARM {false} CONFIG.ENABLE_VCCPAUX_ALARM {false} CONFIG.ENABLE_VCCDDRO_ALARM {false} CONFIG.SEQUENCER_MODE {Continuous} CONFIG.EXTERNAL_MUX_CHANNEL {VP_VN} CONFIG.SINGLE_CHANNEL_SELECTION {TEMPERATURE} CONFIG.CHANNEL_ENABLE_VP_VN {true}] [get_bd_cells xadc_wiz_0]
endgroup
startgroup
set_property -dict [list CONFIG.CHANNEL_ENABLE_VAUXP0_VAUXN0 {true} CONFIG.CHANNEL_ENABLE_VAUXP1_VAUXN1 {true} CONFIG.CHANNEL_ENABLE_VAUXP5_VAUXN5 {true} CONFIG.CHANNEL_ENABLE_VAUXP6_VAUXN6 {true} CONFIG.CHANNEL_ENABLE_VAUXP8_VAUXN8 {true} CONFIG.CHANNEL_ENABLE_VAUXP9_VAUXN9 {true} CONFIG.CHANNEL_ENABLE_VAUXP12_VAUXN12 {true} CONFIG.CHANNEL_ENABLE_VAUXP13_VAUXN13 {true} CONFIG.CHANNEL_ENABLE_VAUXP15_VAUXN15 {true}] [get_bd_cells xadc_wiz_0]
endgroup
startgroup
make_bd_intf_pins_external [get_bd_intf_pins xadc_wiz_0/Vp_Vn]
endgroup
set_property name Vp_Vn [get_bd_intf_ports Vp_Vn_0]
startgroup
make_bd_intf_pins_external [get_bd_intf_pins xadc_wiz_0/Vaux0]
endgroup
set_property name Vaux0 [get_bd_intf_ports Vaux0_0]
startgroup
make_bd_intf_pins_external [get_bd_intf_pins xadc_wiz_0/Vaux1]
endgroup
startgroup
make_bd_intf_pins_external [get_bd_intf_pins xadc_wiz_0/Vaux5]
endgroup
startgroup
make_bd_intf_pins_external [get_bd_intf_pins xadc_wiz_0/Vaux6]
endgroup
startgroup
make_bd_intf_pins_external [get_bd_intf_pins xadc_wiz_0/Vaux8]
endgroup
startgroup
make_bd_intf_pins_external [get_bd_intf_pins xadc_wiz_0/Vaux9]
endgroup
startgroup
make_bd_intf_pins_external [get_bd_intf_pins xadc_wiz_0/Vaux12]
endgroup
startgroup
make_bd_intf_pins_external [get_bd_intf_pins xadc_wiz_0/Vaux13]
endgroup
startgroup
make_bd_intf_pins_external [get_bd_intf_pins xadc_wiz_0/Vaux15]
endgroup
set_property name Vaux1 [get_bd_intf_ports Vaux1_0]
set_property name Vaux5 [get_bd_intf_ports Vaux5_0]
set_property name Vaux6 [get_bd_intf_ports Vaux6_0]
set_property name Vaux8 [get_bd_intf_ports Vaux8_0]
set_property name Vaux9 [get_bd_intf_ports Vaux9_0]
set_property name Vaux12 [get_bd_intf_ports Vaux12_0]
set_property name Vaux13 [get_bd_intf_ports Vaux13_0]
set_property name Vaux15 [get_bd_intf_ports Vaux15_0]
save_bd_design
regenerate_bd_layout
regenerate_bd_layout
validate_bd_design
regenerate_bd_layout
save_bd_design
launch_runs impl_1 -to_step write_bitstream -jobs 7
wait_on_run impl_1
launch_sdk -workspace C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk -hwspec C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk/Bidirectional_Transmitter_wrapper.hdf
export_ip_user_files -of_objects [get_files C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v] -no_script -reset -force -quiet
remove_files C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v
file delete -force C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v
update_compile_order -fileset sources_1
make_wrapper -files [get_files C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd] -top
add_files -norecurse C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v
update_compile_order -fileset sources_1
generate_target all [get_files C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd]
export_ip_user_files -of_objects [get_files C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd]
launch_runs -jobs 7 Bidirectional_Transmitter_gpio_parse_0_0_synth_1
export_simulation -of_objects [get_files C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd] -directory C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.ip_user_files/sim_scripts -ip_user_files_dir C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.ip_user_files -ipstatic_source_dir C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.cache/compile_simlib/modelsim} {questa=C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.cache/compile_simlib/questa} {riviera=C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.cache/compile_simlib/riviera} {activehdl=C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
set_property source_mgmt_mode None [current_project]
set_property top Bidirectional_Transmitter_wrapper [current_fileset]
# Re-enabling previously disabled source management mode.
set_property source_mgmt_mode All [current_project]
update_compile_order -fileset sources_1
reset_run synth_1
reset_run Bidirectional_Transmitter_gpio_parse_0_0_synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
wait_on_run impl_1
reset_run synth_1
reset_run Bidirectional_Transmitter_gpio_parse_0_0_synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
wait_on_run impl_1
reset_run synth_1
reset_run Bidirectional_Transmitter_gpio_parse_0_0_synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
wait_on_run impl_1
update_module_reference Bidirectional_Transmitter_gpio_parse_0_0
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
wait_on_run impl_1
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
wait_on_run impl_1
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
wait_on_run impl_1
file copy -force C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/Bidirectional_Transmitter_wrapper.sysdef C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk/Bidirectional_Transmitter_wrapper.hdf
startgroup
set_property -dict [list CONFIG.NUM_MI {3}] [get_bd_cells ps7_0_axi_periph]
endgroup
connect_bd_net [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0]
connect_bd_net [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins rst_ps7_0_50M/peripheral_aresetn]
regenerate_bd_layout
save_bd_design
validate_bd_design
save_bd_design
reset_run synth_1
reset_run Bidirectional_Transmitter_xbar_0_synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
wait_on_run impl_1
file copy -force C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/Bidirectional_Transmitter_wrapper.sysdef C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk/Bidirectional_Transmitter_wrapper.hdf
update_module_reference Bidirectional_Transmitter_gpio_parse_0_0
generate_target all [get_files C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd]
catch { config_ip_cache -export [get_ips -all Bidirectional_Transmitter_auto_pc_0] }
export_ip_user_files -of_objects [get_files C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd]
launch_runs -jobs 7 Bidirectional_Transmitter_gpio_parse_0_0_synth_1
export_simulation -of_objects [get_files C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd] -directory C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.ip_user_files/sim_scripts -ip_user_files_dir C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.ip_user_files -ipstatic_source_dir C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.ip_user_files/ipstatic -lib_map_path [list {modelsim=C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.cache/compile_simlib/modelsim} {questa=C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.cache/compile_simlib/questa} {riviera=C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.cache/compile_simlib/riviera} {activehdl=C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
wait_on_run impl_1
file copy -force C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/Bidirectional_Transmitter_wrapper.sysdef C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk/Bidirectional_Transmitter_wrapper.hdf
update_module_reference Bidirectional_Transmitter_UART_Reciever_0_0
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
wait_on_run impl_1
file copy -force C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/Bidirectional_Transmitter_wrapper.sysdef C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk/Bidirectional_Transmitter_wrapper.hdf
update_module_reference Bidirectional_Transmitter_UART_Reciever_0_0
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
wait_on_run impl_1
file copy -force C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/Bidirectional_Transmitter_wrapper.sysdef C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk/Bidirectional_Transmitter_wrapper.hdf
update_module_reference Bidirectional_Transmitter_UART_Reciever_0_0