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vivado_11072.backup.log
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vivado_11072.backup.log
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#-----------------------------------------------------------
# Vivado v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Sat Dec 17 14:27:34 2022
# Process ID: 11072
# Current directory: C:/Xilinx/projects/Bidirectional_Transmitter
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent8060 C:\Xilinx\projects\Bidirectional_Transmitter\Bidirectional_Transmitter.xpr
# Log file: C:/Xilinx/projects/Bidirectional_Transmitter/vivado.log
# Journal file: C:/Xilinx/projects/Bidirectional_Transmitter\vivado.jou
#-----------------------------------------------------------
start_gui
open_project C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.2/data/ip'.
open_project: Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 897.664 ; gain = 199.457
open_bd_design {C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd}
Adding cell -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_0
Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_50M
Adding cell -- xilinx.com:module_ref:UART_Transmitter:1.0 - UART_Transmitter_0
Adding cell -- xilinx.com:ip:xadc_wiz:3.3 - xadc_wiz_0
Adding cell -- xilinx.com:module_ref:gpio_parse:1.0 - gpio_parse_0
Adding cell -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
Adding cell -- xilinx.com:module_ref:UART_Reciever:1.0 - UART_Reciever_0
Adding cell -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Successfully read diagram <Bidirectional_Transmitter> from BD file <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
open_bd_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 1019.773 ; gain = 120.945
update_compile_order -fileset sources_1
delete_bd_objs [get_bd_nets din_0_1] [get_bd_ports din]
delete_bd_objs [get_bd_nets gpio_parse_0_din_gpio] [get_bd_ports din_gpio]
connect_bd_net [get_bd_pins gpio_parse_0/din_gpio] [get_bd_pins UART_Reciever_0/din]
regenerate_bd_layout
validate_bd_design
WARNING: [BD 41-927] Following properties on pin /UART_Transmitter_0/int_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
WARNING: [BD 41-927] Following properties on pin /xadc_wiz_0/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
WARNING: [BD 41-927] Following properties on pin /UART_Reciever_0/int_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
export_ip_user_files -of_objects [get_files C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v] -no_script -reset -force -quiet
remove_files C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v
file delete -force C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v
update_compile_order -fileset sources_1
save_bd_design
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/ui/bd_b6017575.ui>
regenerate_bd_layout
validate_bd_design -force
WARNING: [BD 41-927] Following properties on pin /UART_Transmitter_0/int_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
WARNING: [BD 41-927] Following properties on pin /xadc_wiz_0/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
WARNING: [BD 41-927] Following properties on pin /UART_Reciever_0/int_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
save_bd_design
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
reset_run synth_1
reset_run Bidirectional_Transmitter_processing_system7_0_0_synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
[Sat Dec 17 14:30:24 2022] Launched Bidirectional_Transmitter_processing_system7_0_0_synth_1, synth_1...
Run output will be captured here:
Bidirectional_Transmitter_processing_system7_0_0_synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/Bidirectional_Transmitter_processing_system7_0_0_synth_1/runme.log
synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/synth_1/runme.log
[Sat Dec 17 14:30:24 2022] Launched impl_1...
Run output will be captured here: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/runme.log
open_run impl_1
INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.2
INFO: [Device 21-403] Loading part xc7z007sclg400-1
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.074 . Memory (MB): peak = 1898.242 ; gain = 0.000
Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.074 . Memory (MB): peak = 1898.242 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
open_run: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1967.508 ; gain = 882.191
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
make_wrapper -files [get_files C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd] -top
INFO: [BD 41-1662] The design 'Bidirectional_Transmitter.bd' is already validated. Therefore parameter propagation will not be re-run.
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/ui/bd_b6017575.ui>
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/sim/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v
add_files -norecurse C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v
update_compile_order -fileset sources_1
set_property top Bidirectional_Transmitter_wrapper [current_fileset]
update_compile_order -fileset sources_1
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
INFO: [BD 41-1662] The design 'Bidirectional_Transmitter.bd' is already validated. Therefore parameter propagation will not be re-run.
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/ui/bd_b6017575.ui>
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/sim/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_50M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Transmitter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Reciever_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block gpio_parse_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xadc_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/xbar .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconcat_0 .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/ip/Bidirectional_Transmitter_auto_pc_0/Bidirectional_Transmitter_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/s00_couplers/auto_pc .
Exporting to file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter.hwh
Generated Block Design Tcl file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter_bd.tcl
Generated Hardware Definition File C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.hwdef
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Bidirectional_Transmitter_processing_system7_0_0, cache-ID = 70db3ee901be59e2; cache size = 6.915 MB.
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Bidirectional_Transmitter_auto_pc_0, cache-ID = ecea0249ad5cfe19; cache size = 6.915 MB.
[Sat Dec 17 14:35:57 2022] Launched Bidirectional_Transmitter_UART_Reciever_0_0_synth_1, synth_1...
Run output will be captured here:
Bidirectional_Transmitter_UART_Reciever_0_0_synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/Bidirectional_Transmitter_UART_Reciever_0_0_synth_1/runme.log
synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/synth_1/runme.log
[Sat Dec 17 14:35:58 2022] Launched impl_1...
Run output will be captured here: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:16 ; elapsed = 00:00:37 . Memory (MB): peak = 2219.469 ; gain = 107.164
file copy -force C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/Bidirectional_Transmitter_wrapper.sysdef C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk/Bidirectional_Transmitter_wrapper.hdf
launch_sdk -workspace C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk -hwspec C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk/Bidirectional_Transmitter_wrapper.hdf
INFO: [Vivado 12-393] Launching SDK...
INFO: [Vivado 12-417] Running xsdk -workspace C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk -hwspec C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk/Bidirectional_Transmitter_wrapper.hdf
INFO: [Vivado 12-3157] SDK launch initiated. Please check console for any further messages.
update_module_reference Bidirectional_Transmitter_UART_Transmitter_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'int_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'int_clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
Upgrading 'C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd'
INFO: [IP_Flow 19-1972] Upgraded Bidirectional_Transmitter_UART_Transmitter_0_0 from UART_Transmitter_v1_0 1.0 to UART_Transmitter_v1_0 1.0
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/ui/bd_b6017575.ui>
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
WARNING: [BD 41-927] Following properties on pin /xadc_wiz_0/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
WARNING: [BD 41-927] Following properties on pin /UART_Reciever_0/int_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/sim/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_50M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Transmitter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Reciever_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block gpio_parse_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xadc_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/xbar .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconcat_0 .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/ip/Bidirectional_Transmitter_auto_pc_0/Bidirectional_Transmitter_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/s00_couplers/auto_pc .
Exporting to file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter.hwh
Generated Block Design Tcl file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter_bd.tcl
Generated Hardware Definition File C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.hwdef
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Bidirectional_Transmitter_auto_pc_0, cache-ID = ecea0249ad5cfe19; cache size = 6.915 MB.
[Sat Dec 17 14:43:52 2022] Launched Bidirectional_Transmitter_UART_Transmitter_0_0_synth_1, synth_1...
Run output will be captured here:
Bidirectional_Transmitter_UART_Transmitter_0_0_synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/Bidirectional_Transmitter_UART_Transmitter_0_0_synth_1/runme.log
synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/synth_1/runme.log
[Sat Dec 17 14:43:53 2022] Launched impl_1...
Run output will be captured here: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:03 ; elapsed = 00:00:10 . Memory (MB): peak = 2258.695 ; gain = 36.477
file copy -force C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/Bidirectional_Transmitter_wrapper.sysdef C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk/Bidirectional_Transmitter_wrapper.hdf
update_module_reference Bidirectional_Transmitter_UART_Reciever_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'int_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'int_clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
Upgrading 'C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd'
INFO: [IP_Flow 19-1972] Upgraded Bidirectional_Transmitter_UART_Reciever_0_0 from UART_Reciever_v1_0 1.0 to UART_Reciever_v1_0 1.0
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
update_module_reference Bidirectional_Transmitter_UART_Transmitter_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'int_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'int_clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
Upgrading 'C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd'
INFO: [IP_Flow 19-1972] Upgraded Bidirectional_Transmitter_UART_Transmitter_0_0 from UART_Transmitter_v1_0 1.0 to UART_Transmitter_v1_0 1.0
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
update_module_reference Bidirectional_Transmitter_UART_Reciever_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'int_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'int_clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
Upgrading 'C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd'
INFO: [IP_Flow 19-1972] Upgraded Bidirectional_Transmitter_UART_Reciever_0_0 from UART_Reciever_v1_0 1.0 to UART_Reciever_v1_0 1.0
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
WARNING: [BD 41-927] Following properties on pin /xadc_wiz_0/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/sim/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_50M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Transmitter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Reciever_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block gpio_parse_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xadc_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/xbar .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconcat_0 .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/ip/Bidirectional_Transmitter_auto_pc_0/Bidirectional_Transmitter_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/s00_couplers/auto_pc .
Exporting to file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter.hwh
Generated Block Design Tcl file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter_bd.tcl
Generated Hardware Definition File C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.hwdef
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Bidirectional_Transmitter_auto_pc_0, cache-ID = ecea0249ad5cfe19; cache size = 6.915 MB.
[Sat Dec 17 15:17:18 2022] Launched Bidirectional_Transmitter_UART_Transmitter_0_0_synth_1, Bidirectional_Transmitter_UART_Reciever_0_0_synth_1, synth_1...
Run output will be captured here:
Bidirectional_Transmitter_UART_Transmitter_0_0_synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/Bidirectional_Transmitter_UART_Transmitter_0_0_synth_1/runme.log
Bidirectional_Transmitter_UART_Reciever_0_0_synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/Bidirectional_Transmitter_UART_Reciever_0_0_synth_1/runme.log
synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/synth_1/runme.log
[Sat Dec 17 15:17:19 2022] Launched impl_1...
Run output will be captured here: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:03 ; elapsed = 00:00:14 . Memory (MB): peak = 2360.164 ; gain = 29.926
file copy -force C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/Bidirectional_Transmitter_wrapper.sysdef C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk/Bidirectional_Transmitter_wrapper.hdf
update_module_reference Bidirectional_Transmitter_UART_Transmitter_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'int_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'int_clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
Upgrading 'C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd'
INFO: [IP_Flow 19-1972] Upgraded Bidirectional_Transmitter_UART_Transmitter_0_0 from UART_Transmitter_v1_0 1.0 to UART_Transmitter_v1_0 1.0
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
update_module_reference Bidirectional_Transmitter_UART_Reciever_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'int_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'int_clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
Upgrading 'C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd'
INFO: [IP_Flow 19-1972] Upgraded Bidirectional_Transmitter_UART_Reciever_0_0 from UART_Reciever_v1_0 1.0 to UART_Reciever_v1_0 1.0
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 7
WARNING: [BD 41-927] Following properties on pin /xadc_wiz_0/s_axi_aclk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
CLK_DOMAIN=Bidirectional_Transmitter_processing_system7_0_0_FCLK_CLK0
Wrote : <C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/Bidirectional_Transmitter.bd>
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/sim/Bidirectional_Transmitter.v
VHDL Output written to : C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hdl/Bidirectional_Transmitter_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_50M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Transmitter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block UART_Reciever_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block gpio_parse_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xadc_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/xbar .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconcat_0 .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/ip/Bidirectional_Transmitter_auto_pc_0/Bidirectional_Transmitter_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/s00_couplers/auto_pc .
Exporting to file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter.hwh
Generated Block Design Tcl file C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/hw_handoff/Bidirectional_Transmitter_bd.tcl
Generated Hardware Definition File C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.srcs/sources_1/bd/Bidirectional_Transmitter/synth/Bidirectional_Transmitter.hwdef
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP Bidirectional_Transmitter_auto_pc_0, cache-ID = ecea0249ad5cfe19; cache size = 6.915 MB.
[Sat Dec 17 15:28:24 2022] Launched Bidirectional_Transmitter_UART_Transmitter_0_0_synth_1, Bidirectional_Transmitter_UART_Reciever_0_0_synth_1, synth_1...
Run output will be captured here:
Bidirectional_Transmitter_UART_Transmitter_0_0_synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/Bidirectional_Transmitter_UART_Transmitter_0_0_synth_1/runme.log
Bidirectional_Transmitter_UART_Reciever_0_0_synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/Bidirectional_Transmitter_UART_Reciever_0_0_synth_1/runme.log
synth_1: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/synth_1/runme.log
[Sat Dec 17 15:28:25 2022] Launched impl_1...
Run output will be captured here: C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 2400.152 ; gain = 35.285
file copy -force C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.runs/impl_1/Bidirectional_Transmitter_wrapper.sysdef C:/Xilinx/projects/Bidirectional_Transmitter/Bidirectional_Transmitter.sdk/Bidirectional_Transmitter_wrapper.hdf
exit
INFO: [Common 17-206] Exiting Vivado at Sat Dec 17 16:31:02 2022...