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Day 25 - Post-placement STA analysis of your Design (RISC-V Myth CPU Core)

25.1 OpenLANE Installation (latest stable version)

For ease of installation, OpenLane uses Docker images, that include all the required applications, binaries and the flow scripts.
The OpenLane Installation Documentation page explains in detail the step to setup OpenLANE. A short summary of the necessary steps is given below:

Install the required dependencies:

sudo apt-get update
sudo apt-get upgrade
sudo apt install -y build-essential python3 python3-venv make git

Docker Installation

Run the following command to uninstall all conflicting packages:

for pkg in docker.io docker-doc docker-compose docker-compose-v2 podman-docker containerd runc; do sudo apt-get remove $pkg; done

Set up Docker's apt repository

# Add Docker's official GPG key:
sudo apt-get update
sudo apt-get install ca-certificates curl
sudo install -m 0755 -d /etc/apt/keyrings
sudo curl -fsSL https://download.docker.com/linux/ubuntu/gpg -o /etc/apt/keyrings/docker.asc
sudo chmod a+r /etc/apt/keyrings/docker.asc

# Add the repository to Apt sources:
echo \
  "deb [arch=$(dpkg --print-architecture) signed-by=/etc/apt/keyrings/docker.asc] https://download.docker.com/linux/ubuntu \
  $(. /etc/os-release && echo "$VERSION_CODENAME") stable" | \
  sudo tee /etc/apt/sources.list.d/docker.list > /dev/null
sudo apt-get update

Install the Docker packages:

sudo apt-get install docker-ce docker-ce-cli containerd.io docker-buildx-plugin docker-compose-plugin

Verify that the Docker Engine installation is successful by running:

sudo docker run hello-world

To make Docker available without root:

sudo groupadd docker
sudo usermod -aG docker $USER
sudo reboot # REBOOT!

# After reboot
docker run hello-world

Download OpenLane from GitHub:
```
git clone --depth 1 https://github.com/The-OpenROAD-Project/OpenLane.git
cd OpenLane/
make
make test
```
- These steps will download and build OpenLane and sky130 PDK.
- Finally, it will run a ~5 minute test that verifies that the flow and the PDK were properly installed. Successful test will output the following line:
```
Basic test passed
```

25.2 Basic Usage

25.2.1 Invoking the OpenLane Docker session:

cd to the OpenLane folder

# Start the Docker session:
make mount

# Leave the Docker
exit

25.2.2 Adding Your Designs

To add a new design, the following command creates a configuration file for your design:
```
# JSON Configuration File
./flow.tcl -design <design_name> -init_design_config -add_to_designs

# Tcl Configuration File
./flow.tcl -design <design_name> -init_design_config -add_to_designs -config_file config.tcl
```
This will create the following directory structure:
```
designs/<design_name>
├── config.json (or config.tcl)
```
- NOTE: The <design_name> must match the top-level module name of your design exactly. Otherwise, OpenLane will throw an error (at least by the run_synthesis stage).
It is recommended to place the verilog files of the design in a src directory inside the folder of the design as following:
```
designs/<design_name>
├── config.tcl
├── src
│   ├── design.v
```

25.2.3 Running the flow for the design:

To run the automated flow:
```
./flow.tcl -design <design_name>
```

To run the flow interactively (Interactive Mode):

./flow.tcl -interactive

A tcl shell will be opened where the openlane package is to be sourced

package require openlane 0.9

Now, the following main commands run the various major steps of the Physical design flow:

0. Any valid Tcl code
1. prep -design <design> [-tag TAG] [-config CONFIG] [-init_design_config] [-overwrite]
2. run_synthesis
3.run_floorplan
4.run_placement
5.run_cts
6.run_routing
7.a write_powered_verilog 
7.b set_netlist $::env(routing_logs)/$::env(DESIGN_NAME).powered.v
8. run_magic
9. run_magic_spice_export
10. run_magic_drc
11. run_lvs
12. run_antenna_check

25.2.4 Some FYI Notes:

Command-Line Arguments that can be passed to flow.tcl

Argument	Description
`-tag <name>` (Optional)	Specifies a “name” for a specific run. If the tag is not specified, a timestamp is generated for identification of that run.
`-overwrite` (Optional)	Flag to overwrite an existing run with the same tag
`-synth_explore`	If enabled, synthesis exploration will be run (only synthesis exploration), which will try out the available synthesis strategies against the input design.
`-verbose <level>` (Optional)	0: Outputs only high-level messages 1: Also ouputs some of the inner workings of the flow scripts >=2: Forwards outputs from all tools

Design configuration files: config.json (or config.tcl)
Each OpenLane-compatible design must come with a configuration file written in either JSON or Tcl.
Flow Configuration variables
PDK Configuration variables
Tcl commands available in OpenLane
- When running the flow in interactive mode, use the -verbose <level> flag with the prep -design <design_name> command to set the verbose output level (2 and greater outputs everything including tool outputs). Example: prep -design riscv_core -tag run1 -overwrite -verbose 2

25.3 Synthesis Results

Some synthesis settings modified:

set ::env(SYNTH_STRATEGY) "DELAY 0"
set ::env(SYNTH_BUFFERING) 1
set ::env(SYNTH_SIZING) 1
set ::env(SYNTH_SPLITNETS) 0
set ::env(SYNTH_MAX_FANOUT) 6

In addition, the Openlane/scripts/yosys/synth.tcl file was modified, with the sequence of yosys/ abc synthesis commands being modified in accordance with this comment from Yosys issue #4266.

Synthesis cell usage statistics:

=== riscv_core ===

   Number of wires:               8458
   Number of wire bits:          11999
   Number of public wires:         176
   Number of public wire bits:    3717
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              11997
     sky130_fd_sc_hd__a2111o_2      10
     sky130_fd_sc_hd__a2111oi_2      2
     sky130_fd_sc_hd__a211o_2      132
     sky130_fd_sc_hd__a211oi_2      38
     sky130_fd_sc_hd__a21bo_2        3
     sky130_fd_sc_hd__a21boi_2       6
     sky130_fd_sc_hd__a21o_2        41
     sky130_fd_sc_hd__a21oi_2      894
     sky130_fd_sc_hd__a221o_2      442
     sky130_fd_sc_hd__a221oi_2       3
     sky130_fd_sc_hd__a22o_2       318
     sky130_fd_sc_hd__a22oi_2        5
     sky130_fd_sc_hd__a2bb2o_2       4
     sky130_fd_sc_hd__a311o_2       54
     sky130_fd_sc_hd__a311oi_2       2
     sky130_fd_sc_hd__a31o_2        72
     sky130_fd_sc_hd__a31oi_2       41
     sky130_fd_sc_hd__a32o_2       216
     sky130_fd_sc_hd__a32oi_2        2
     sky130_fd_sc_hd__a41o_2         6
     sky130_fd_sc_hd__a41oi_2        1
     sky130_fd_sc_hd__and2_2        40
     sky130_fd_sc_hd__and2b_2       24
     sky130_fd_sc_hd__and3_2       104
     sky130_fd_sc_hd__and3b_2        7
     sky130_fd_sc_hd__and4_2        32
     sky130_fd_sc_hd__and4b_2       23
     sky130_fd_sc_hd__and4bb_2      28
     sky130_fd_sc_hd__buf_1       2242
     sky130_fd_sc_hd__buf_2        940
     sky130_fd_sc_hd__conb_1       775
     sky130_fd_sc_hd__dfxtp_2     1907
     sky130_fd_sc_hd__inv_2         80
     sky130_fd_sc_hd__mux2_2        78
     sky130_fd_sc_hd__nand2_2      105
     sky130_fd_sc_hd__nand3_2       17
     sky130_fd_sc_hd__nand3b_2       2
     sky130_fd_sc_hd__nand4_2        1
     sky130_fd_sc_hd__nand4b_2       1
     sky130_fd_sc_hd__nor2_2       118
     sky130_fd_sc_hd__nor3_2         1
     sky130_fd_sc_hd__nor3b_2        5
     sky130_fd_sc_hd__nor4_2        12
     sky130_fd_sc_hd__nor4b_2        5
     sky130_fd_sc_hd__o2111ai_2      3
     sky130_fd_sc_hd__o211a_2       77
     sky130_fd_sc_hd__o211ai_2      31
     sky130_fd_sc_hd__o21a_2       944
     sky130_fd_sc_hd__o21ai_2       74
     sky130_fd_sc_hd__o21ba_2      516
     sky130_fd_sc_hd__o21bai_2      32
     sky130_fd_sc_hd__o221a_2       31
     sky130_fd_sc_hd__o221ai_2       4
     sky130_fd_sc_hd__o22a_2         5
     sky130_fd_sc_hd__o22ai_2        2
     sky130_fd_sc_hd__o2bb2a_2      10
     sky130_fd_sc_hd__o2bb2ai_2      4
     sky130_fd_sc_hd__o311a_2       19
     sky130_fd_sc_hd__o311ai_2       1
     sky130_fd_sc_hd__o31a_2       935
     sky130_fd_sc_hd__o31ai_2        1
     sky130_fd_sc_hd__o32a_2        12
     sky130_fd_sc_hd__o41a_2        45
     sky130_fd_sc_hd__or2_2         75
     sky130_fd_sc_hd__or2b_2        37
     sky130_fd_sc_hd__or3_2         63
     sky130_fd_sc_hd__or3b_2        18
     sky130_fd_sc_hd__or4_2        133
     sky130_fd_sc_hd__or4b_2        22
     sky130_fd_sc_hd__or4bb_2        4
     sky130_fd_sc_hd__xnor2_2       27
     sky130_fd_sc_hd__xor2_2        33

Chip area for module '\riscv_core': 115293.075200

25.4 Placement (Pre-CTS)

Placement optimizations:

Reading design constraints file at '/openlane/designs/riscv_core/src/riscv_base_post_cts.sdc'…
[INFO]: Setting output delay to: 4.0
[INFO]: Setting input delay to: 4.0
[INFO]: Setting load to: 0.01765
[INFO]: Setting clock uncertainty to: 0.25
[INFO]: Setting clock transition to: 0.15
[INFO]: Setting timing derate to: 5.0 %
[INFO]: Setting RC values...
[INFO RSZ-0027] Inserted 1 input buffers.
[INFO RSZ-0028] Inserted 10 output buffers.
[INFO RSZ-0058] Using max wire length 8182um.
[INFO RSZ-0034] Found 80 slew violations.
[INFO RSZ-0035] Found 14 fanout violations.
[INFO RSZ-0036] Found 11 capacitance violations.
[INFO RSZ-0038] Inserted 303 buffers in 94 nets.
[INFO RSZ-0039] Resized 9488 instances.
[INFO RSZ-0042] Inserted 513 tie sky130_fd_sc_hd__conb_1 instances.
[INFO RSZ-0042] Inserted 262 tie sky130_fd_sc_hd__conb_1 instances.

Design area: 124358 u^2 33% utilization

25.5 STA Comparison: Post-synthesis vs. Post-Placement (Pre-CTS)

Post-Synthesis	Post-Placement (Pre-CTS)

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Day_25.md

Day_25.md

Day 25 - Post-placement STA analysis of your Design (RISC-V Myth CPU Core)

25.1 OpenLANE Installation (latest stable version)

25.2 Basic Usage

25.2.1 Invoking the OpenLane Docker session:

25.2.2 Adding Your Designs

25.2.3 Running the flow for the design:

25.2.4 Some FYI Notes:

25.3 Synthesis Results

25.4 Placement (Pre-CTS)

25.5 STA Comparison: Post-synthesis vs. Post-Placement (Pre-CTS)

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Day_25.md

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Day_25.md

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Day 25 - Post-placement STA analysis of your Design (RISC-V Myth CPU Core)

25.1 OpenLANE Installation (latest stable version)

25.2 Basic Usage

25.2.1 Invoking the OpenLane Docker session:

25.2.2 Adding Your Designs

25.2.3 Running the flow for the design:

25.2.4 Some FYI Notes:

25.3 Synthesis Results

25.4 Placement (Pre-CTS)

25.5 STA Comparison: Post-synthesis vs. Post-Placement (Pre-CTS)