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Fabricating ICs is very expensive and time-consuming, so designers need simulation tools to explore the design space and verify designs before they are fabricated. Simulation is cheap, but silicon revisions (even a single Metal layer change) are prohibitively expensive.
Simulators operate at many levels of abstraction, from process through architecture.
- Process simulators such as SUPREME predict how factors in the process recipe such as time and temperature affect device physical and electrical characteristics.
- Circuit simulators such as SPICE and Spectre use device models and a circuit netlist to predict circuit voltages and currents, which indicate performance and power consumption.
- Logic simulators such as VCS and ModelSim are widely used to verify correct logical operation of designs specified in a hardware description language (HDL).
- Architecture simulators, sometimes offered with a processor’s development toolkit, work at the level of instructions and registers to predict throughput and memory access patterns, which influence design decisions such as pipelining and cache memory organization.
The various levels of abstraction offer trade-offs between degree of detail and the size of the system that can be simulated. VLSI designers are primarily concerned with circuit and logic simulation.
SPICE (Simulation Program with Integrated Circuit Emphasis) was originally developed in the 1970s at University of California, Berkeley. It solves the nonlinear differential equations describing components such as transistors, resistors, capacitors, and voltage sources.
Based on the original SPICE, there are many SPICE versions available - both free (like Ngspice, Xyce, LTSpice, TINA-TI) as well as commercial (HSPICE, PSPICE). All versions of SPICE read an input file and generate an output with results, warnings, and error messages. The input file is often called a SPICE deck and each line is called a card because it was once provided to a mainframe as a deck of punch cards.
A circuit simulator is provided with an input file that contains:
- A netlist consisting of components and nodes detailing the circuit connectivity.
The netlist can be entered by hand or extracted from a circuit schematic or layout in a CAD program. - Component behaviour by means of device models and model parameters.
- The Initial state of the circuit -- initial conditions
- Inputs to the circuit, called stimulus
- Simulation options & analysis commands that explain the type of simulation to be run.
Ref: CMOS VLSI Design - A Circuits and Systems Perspective - Weste & Harris
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Analysis Types supported by SPICE:
| Analysis Type | Details |
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| DC Analysis | Find the DC operating point of the circuit i.e., all voltages and currents |
| AC Small-Signal Analysis | AC analysis is limited to analog nodes and represents the small signal, sinusoidal solution of the analog system described at a particular frequency or set of frequencies. |
| Transient Analysis | Transient analysis is an extension of DC analysis to the time domain. In other words, it solves a DC Analysis for each timestep based on initial conditions. |
| Pole-Zero Analysis | Computes the poles and/or zeros in the small-signal ac transfer function. |
| Small-Signal Distortion Analysis | Computes steady-state harmonic and intermodulation products for small input signal magnitudes. |
| Sensitivity Analysis | Calculate either the DC operating-point sensitivity or the AC small-signal sensitivity of an output variable with respect to all circuit variables, including model parameters. |
| Noise Analysis | Measures the device-generated noise for a given circuit. |
The following images show how a SPICE deck is written to perform DC analysis of an NMOS transistor:
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In Digital VLSI Design, the timing, power, process variation, noise and signal integrity analyses all ultimately rely on SPICE for accurate modelling and characterization of the various Standard Cells and macros used in the design.
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- Without the application of a Gate potential, the transistor is said to be in Cut-off region as there is no conducting path between the Source and Drain terminals.
- On the application a sufficiently high Gate-to-Source voltage, a conductive channel starts to form underneath the Gate composed of minority carriers (electrons in an NMOS) and at a certain voltage called the Threshold voltage, surface inversion occurs when the concentration of minority carriers in the channel becomes equal to the concentration of majority carriers in the bulk.
- When VGS is increased further by several
$\Phi_t (=thermal voltage, \dfrac{k_B T}{q}) $ , the transistor moves into the strong inversion region. Here, the minority carrier concentration in the channel is a strong function of the applied gate potential.
The below images depict the same for an NMOS transistor:
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- The Source-to-Substrate amd Drain-to-Substrate pn junctions must always be reverse biased for the "normal operation" of the MOS transistor, so
$V_{SB}, V_{DB}$ must always be greater than or equal to zero for an NMOS transistor. - If
$V_{SB} = 0$ , then surface inversion is achieved at a Gate-to-Source voltage equal to VT0 - However, when
$V_{SB} > 0$ , the electrons from the channel can move laterally and flow out of the source terminal resulting in a reduced carrier concentration in the channel. - Thus, with when
$V_{SB} > 0$ , a higher Gate-to-Source voltage is required to achieve surface inversion. - In other words, the threshold voltage of an NMOS increases when
$V_{SB} > 0$ .
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Threshold Voltage Equation considering Body Bias:  |
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Let us analyse the condition when we apply a Gate-Source potential,
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Using a simple first-order analysis, let us try to derive an equation for the Drain Current,
The mechanism for the Drain current,
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Let
$V_{GS}$ be held constant at a value greater than$V_{TH}$ . -
The applied
$V_{DS}$ appears as a voltage drop across the length of the channel. -
As we travel along the channel from Source to Drain, the voltage (measured relative to the Source terminal) increases from zero to
$V_{DS}$ . -
Thus the voltage between the gate and points along the channel decreases from
$V_{GS}$ at the Source end to$V_{GD} = V_{GS}-V_{DS}$ at the Drain end. -
At a point x along the channel, the voltage is
$V(x)$ , and the gate-to-channel voltage at that point equals$V_{GS} – V(x)$ .
Under the assumption that this voltage exceeds the threshold voltage all along the channel, the induced channel charge per unit area at point x can be computed.
The current is given as the product of the drift velocity of the carriers,
The electron velocity is related to the electric field through a parameter called the mobility
Drift velocity,
Integrating the equation over the length of the channel L yields the voltage-current relation of the transistor:
The product of process transconductance,
Now, the above equation for Drain Current:
But at low values, the
For the example scenario we were discussing, this translates to:
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- When a
$V_{DS}$ voltage is applied, the channel voltage becomes a function of both$V_{GS}$ and$V_{DS}$ . - Since the induced channel depth depends on the channel voltage relative to the Gate terminal, and specifically on the amount by which this voltage exceeds the threshold voltage,
$V_{TH}$ , we find that the channel is no longer of uniform depth; rather, the channel will take a tapered shape:- being deepest at the Source end, where the depth is proportional to
$[V_{GS}-V_{TH}]$ , and - shallowest at the drain end, where the depth is proportional to
$[V_{GS}-V_{TH}-V_{DS}]$ .
- being deepest at the Source end, where the depth is proportional to
- As the value of the Drain-Source voltage is increased further, the assumption that the channel voltage is larger than the threshold all along the channel ceases to hold.
- In the limiting case, the channel depth at the drain end reduces to zero and the channel is said to be "pinched-off". This happens when
$V_{GD}$ is just equal to the threshold voltage,$V_{TH}$ . - i.e.,
$V_{DS}= V_{GS}-V_{TH} ~~~~~~~~ (=V_{OV})$ , Gate Over-drive voltage
- In the limiting case, the channel depth at the drain end reduces to zero and the channel is said to be "pinched-off". This happens when
- At this point, the induced charge is zero, and the conducting channel disappears or is pinched off starting from the Drain end.
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Increasing
$V_{DS}$ beyond the$V_{DSsat}$ value of ($V_{GS}-V_{TH}$ ) has no effect on the channel shape and charge. -
Thus, the current through the channel remains constant at the value reached for
$V_{DS}= V_{GS}-V_{TH}$ . -
The MOSFET is said to have entered saturation/ pinch-off regsion at:
$V_{DS} = V_{DSsat} = V_{GS}-V_{TH}$
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Subsequently, the Saturation Drain current:
$I_D = I_{Dsat} = {k_n}^\prime \dfrac{W}{L} \left[ (V_{GS}-V_{TH})V_{DSsat} - \dfrac{{V_{DSsat}}^2}{2} \right]$ $\boxed{i.e., I_{Dsat} = \dfrac{1}{2} {k_n}^\prime \dfrac{W}{L} {\left[ {V_{GS}-V_{TH}}^2\right]}}$
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Channel pinch-off does not imply channel blockage
- Current continues to flow through the pinched-off channel.
- The electrons that reach the drain end of the channel are accelerated through the depletion region that exists there and into the drain terminal.
- Any increase in
$V_{DS}$ above$V_{DSsat}$ appears as a voltage drop across the depletion region - Thus, both the current through the channel,
$I_{Dsat}$ and the voltage drop across the channel$i.e., V_{DSsat} = (V_{GS}-V_{TH})$ remain constant in saturation.
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The above Drain current equation seems to indicate that in sarutation,
$I_D$ is independent of$V_{DS}$ -
Thus a change,
$\Delta V_{DS}$ , in the Drain-to-Source voltage causes a zero change in$I_D$ , which implies that the incremental resistance looking into the drain of a saturated MOSFET is infinite. -
This, however, is an idealization based on the premise that once the channel is pinched off at the drain end, further increases in
$V_{DS}$ have no effect on the channel’s shape. -
But, in practice, increasing
$V_{DS}$ beyond$V_{GS}-V_{TH}$ does affect the channel somewhat.- As
$V_{DS}$ is increased, the channel pinch-off point is moved slightly away from the drain, toward the source. - That is, the voltage across the channel remains constant at
$V_{GS}-V_{TH}$ , and - The additional voltage applied to the drain appears as a voltage drop across the narrow depletion region between the end of the channel and the drain region.
- This voltage accelerates the electrons that reach the drain end of the channel and sweeps them across the depletion region into the drain.
- As
-
Note, however, that (with depletion-layer widening) the channel length is reduced from
$L$ to$(L-\Delta L)$ , called Channel Length Modulation (CLM). -
Since
$I_D$ is inversely proportional to the channel length,$I_D$ increases with$V_{DS}$ . -
CLM can be accounted for in the expression for
$I_D$ by including a factor$[1 + \lambda (V_{DS}-V_{DSsat})]$ .
For simplicity, we use:$[1 + \lambda V_{DS}]$ $\boxed{\therefore I_{D} = \dfrac{1}{2} {k_n}^\prime \dfrac{W}{L} \left[ {(V_{GS}-V_{TH}}^2\right] (1 + \lambda V_{DS})}$ -
The CLM parameter,
$\lambda$ is a device parameter having the units of$V^{-1}$ . Its value depends both on the process technology used to fabricate the device and on the channel length,$L$ that the circuit designer selects. -
Output Resistance,
$r_o = \dfrac{1}{\lambda I_D}$
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SPICE File: day1_nfet_idvds_L2_W5.spice
*** Model Description ***
.param temp=27
*** Including sky130 library files ***
.lib "sky130_fd_pr/models/sky130.lib.spice" tt
*** Netlist Description ***
XM1 vdd n1 0 0 sky130_fd_pr__nfet_01v8 w=5 l=2
R1 n1 in 55
Vdd vdd 0 1.8
Vin in 0 1.8
*** Simulation Commands ***
.op
.dc Vdd 0 1.8 0.1 Vin 0 1.8 0.2
.control
run
display
setplot dc1
.endc
.end
Output:  |
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