Day7.md

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Day 7: Digital Logic with TL-Verilog and Makerchip

7.1 TL-Verilog

Transaction-Level Verilog (TL-Verilog) is an extension to SystemVerilog that supports a new design methodology, called transaction-level design. A transaction, in this methodology, is an entity that moves through structures like pipelines, arbiters, and queues. A transaction might be a machine instruction, a flit of a packet, or a memory read/write. Transaction logic, like packet header decode or instruction execution, that operates on the transaction can be placed anywhere along the transaction’s flow. Tools produce the logic to carry signals through their flows to stitch the transaction logic.

7.2 Makerchip Platform

Makerchip is a free online environment provided by Redwood EDA for developing integrated circuits. The online platform can be used to code, compile, simulate and debug Verilog designs from a web browser. In addition to Verilog and synthesizable SystemVerilog, the platform provides support for Transaction-Level Verilog (TL-Verilog).

The Makerchip IDE also provides various tutorials and examples (inside Learn menu in the main window) to help learn the new concepts and constructs in TL-Verilog quickly.

References:

1. https://www.redwoodeda.com/tl-verilog
2. https://www.tl-x.org
3. Top-Down Transaction-Level Design with TL-Verilog
4. Makerchip IDE
5. Makerchip IDE Documentation

In this session, we will learn the concepts and syntax of TL-Verilog by implementing basic combinational and sequential logic using the same in Makerchip.

1. Combinational logic
2. Sequential logic
3. Pipelined logic
4. Validity

7.2.1 Combinational Logic

Implemented basic combinational logic elements and circuits like gates, muxes, vector adder, combinational calculator etc. using TL-Verilog in Makerchip.

1. AND2 Gate

2. Vector Mux

3. Adder

4. Combinational Calculator

7.2.2 Sequential Logic

1. Fibonacci Series

2. Free-running Counter (starts from 1 and increments by 1 every cycle)

3. Sequential Calculator

7.2.3 Pipelined Logic

1. Pythagorus Theorem with 3-stage pipeline

2. Example showing the ease of pipelining/ retiming in TL-Verilog

3. Sequential Calculator with counter

4. 2-Cycle Sequential Calculator

7.2.4 Validity

Using validity makes the design cleaner. Debugging and error checking also becomes easier.

1. 2-Cycle Calculator with Validity
2. Calculator with Single-value Memory

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