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arm64: dts: Add device tree for ArmSoM-w3 #83

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Aug 22, 2023
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1 change: 1 addition & 0 deletions arch/arm64/boot/dts/rockchip/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -190,6 +190,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-v11.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-v11-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-fxblox-rk1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-hinlink-h88k.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-w3.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10-android.dtb
Expand Down
206 changes: 206 additions & 0 deletions arch/arm64/boot/dts/rockchip/rk3588-armsom-w3-camera.dtsi
Original file line number Diff line number Diff line change
@@ -0,0 +1,206 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/

/ {
camera_pwdn_gpio: camera-pwdn-gpio {
status = "okay";
compatible = "regulator-fixed";
regulator-name = "camera_pwdn_gpio";
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cam_pwdn_gpio>;
};

clk_cam_24m: external-camera-clock-24m {
status = "okay";
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "clk_cam_24m";
#clock-cells = <0>;
};
};

&i2c3 {
status = "okay";

imx415: imx415@1a {
status = "okay";
compatible = "sony,imx415";
reg = <0x1a>;
clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
clock-names = "xvclk";
pinctrl-names = "default";
pinctrl-0 = <&mipim0_camera3_clk>;
power-domains = <&power RK3588_PD_VI>;
pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2022-PX1";
rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20";
port {
imx415_out0: endpoint {
remote-endpoint = <&mipidphy0_in_ucam0>;
data-lanes = <1 2 3 4>;
};
};
};

camera_imx219: camera-imx219@10 {
status = "disabled";
compatible = "sony,imx219";
reg = <0x10>;

clocks = <&clk_cam_24m>;
clock-names = "xvclk";

rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "rpi-camera-v2";
rockchip,camera-module-lens-name = "default";

port {
imx219_out0: endpoint {
remote-endpoint = <&mipidphy0_in_ucam1>;
data-lanes = <1 2>;
};
};
};
};

&csi2_dphy0_hw {
status = "okay";
};

&csi2_dphy0 {
status = "okay";

ports {
#address-cells = <1>;
#size-cells = <0>;

port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;

mipidphy0_in_ucam0: endpoint@1 {
reg = <1>;
remote-endpoint = <&imx415_out0>;
data-lanes = <1 2 3 4>;
};

mipidphy0_in_ucam1: endpoint@2 {
reg = <2>;
remote-endpoint = <&imx219_out0>;
data-lanes = <1 2>;
};
};

port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;

csidphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi2_csi2_input>;
};
};
};
};

&mipi2_csi2 {
status = "okay";

ports {
#address-cells = <1>;
#size-cells = <0>;

port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;

mipi2_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy0_out>;
};
};

port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;

mipi2_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi2_in0>;
};
};
};
};

&rkcif {
status = "okay";
};

&rkcif_mipi_lvds2 {
status = "okay";

port {
cif_mipi2_in0: endpoint {
remote-endpoint = <&mipi2_csi2_output>;
};
};
};

&rkcif_mipi_lvds2_sditf {
status = "okay";

port {
mipi_lvds2_sditf: endpoint {
remote-endpoint = <&isp0_vir0>;
};
};
};

&rkcif_mmu {
status = "okay";
};

&rkisp0 {
status = "okay";
};

&isp0_mmu {
status = "okay";
};

&rkisp0_vir0 {
status = "okay";

port {
#address-cells = <1>;
#size-cells = <0>;

isp0_vir0: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_lvds2_sditf>;
};
};
};

&pinctrl {
camera {
cam_pwdn_gpio: cam-pwdn-gpio {
rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
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