From d4acdd676107ca161fbda6126d855b6652ea1a0e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Armandas=20Jaru=C5=A1auskas?= Date: Sat, 5 Oct 2024 14:59:54 +0900 Subject: [PATCH] Update comments to address feedback in #562 --- avr-hal-generic/src/usart_spi.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/avr-hal-generic/src/usart_spi.rs b/avr-hal-generic/src/usart_spi.rs index e6ecbfb45f..91a51e74a5 100644 --- a/avr-hal-generic/src/usart_spi.rs +++ b/avr-hal-generic/src/usart_spi.rs @@ -55,8 +55,7 @@ macro_rules! add_usart_spi { fn raw_setup(&mut self, settings: &$crate::spi::Settings) { use $crate::hal::spi; - // Setup control registers - // We start by setting the UBBRn to 0 + // UBRRn must be zero at the time the transmitter is enabled. self.[].write(|w| unsafe {w.bits(0)}); // We have to translate the character size register into the 2 bits which are the MSB/LSB and the phase @@ -84,13 +83,14 @@ macro_rules! add_usart_spi { } }); - // Enable receiver and transmitter, and also the rec interrupt. + // Enable receiver and transmitter. self.[].write(|w| w .[]().set_bit() .[]().set_bit() ); // Set the clock divider for SPI clock. + // This must be done after the transmitter is enabled. self.[].write(|w| { match settings.clock { $crate::spi::SerialClockRate::OscfOver2 => w.bits(0),