diff --git a/firmwares/zephyr-arduino_giga_r1_m7.bin b/firmwares/zephyr-arduino_giga_r1_m7.bin index 36dd1e83..578f7211 100755 Binary files a/firmwares/zephyr-arduino_giga_r1_m7.bin and b/firmwares/zephyr-arduino_giga_r1_m7.bin differ diff --git a/firmwares/zephyr-arduino_giga_r1_m7.elf b/firmwares/zephyr-arduino_giga_r1_m7.elf index 2905c1b8..acf05c48 100755 Binary files a/firmwares/zephyr-arduino_giga_r1_m7.elf and b/firmwares/zephyr-arduino_giga_r1_m7.elf differ diff --git a/firmwares/zephyr-arduino_nano_33_ble_sense.elf b/firmwares/zephyr-arduino_nano_33_ble_sense.elf index 281f2265..f6ad9aac 100755 Binary files a/firmwares/zephyr-arduino_nano_33_ble_sense.elf and b/firmwares/zephyr-arduino_nano_33_ble_sense.elf differ diff --git a/firmwares/zephyr-arduino_portenta_h7.elf b/firmwares/zephyr-arduino_portenta_h7.elf index 96d1d652..de219f77 100755 Binary files a/firmwares/zephyr-arduino_portenta_h7.elf and b/firmwares/zephyr-arduino_portenta_h7.elf differ diff --git a/firmwares/zephyr-ek_ra8d1.elf b/firmwares/zephyr-ek_ra8d1.elf index 57b5ac27..706d1018 100755 Binary files a/firmwares/zephyr-ek_ra8d1.elf and b/firmwares/zephyr-ek_ra8d1.elf differ diff --git a/firmwares/zephyr-frdm_mcxn947_mcxn947_cpu0.elf b/firmwares/zephyr-frdm_mcxn947_mcxn947_cpu0.elf index 98558328..e7d7f6d9 100755 Binary files a/firmwares/zephyr-frdm_mcxn947_mcxn947_cpu0.elf and b/firmwares/zephyr-frdm_mcxn947_mcxn947_cpu0.elf differ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/syscall_list.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/syscall_list.h index bd8cf6f0..74704a43 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/syscall_list.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/syscall_list.h @@ -10,295 +10,295 @@ #define K_SYSCALL_DEVICE_GET_BY_DT_NODELABEL 4 #define K_SYSCALL_DEVICE_INIT 5 #define K_SYSCALL_DEVICE_IS_READY 6 -#define K_SYSCALL_FLASH_ERASE 7 -#define K_SYSCALL_FLASH_EX_OP 8 -#define K_SYSCALL_FLASH_FILL 9 -#define K_SYSCALL_FLASH_FLATTEN 10 -#define K_SYSCALL_FLASH_GET_PAGE_COUNT 11 -#define K_SYSCALL_FLASH_GET_PAGE_INFO_BY_IDX 12 -#define K_SYSCALL_FLASH_GET_PAGE_INFO_BY_OFFS 13 -#define K_SYSCALL_FLASH_GET_PARAMETERS 14 -#define K_SYSCALL_FLASH_GET_WRITE_BLOCK_SIZE 15 -#define K_SYSCALL_FLASH_READ 16 -#define K_SYSCALL_FLASH_READ_JEDEC_ID 17 -#define K_SYSCALL_FLASH_SFDP_READ 18 -#define K_SYSCALL_FLASH_WRITE 19 -#define K_SYSCALL_GPIO_GET_PENDING_INT 20 -#define K_SYSCALL_GPIO_PIN_CONFIGURE 21 -#define K_SYSCALL_GPIO_PIN_GET_CONFIG 22 -#define K_SYSCALL_GPIO_PIN_INTERRUPT_CONFIGURE 23 -#define K_SYSCALL_GPIO_PORT_CLEAR_BITS_RAW 24 -#define K_SYSCALL_GPIO_PORT_GET_DIRECTION 25 -#define K_SYSCALL_GPIO_PORT_GET_RAW 26 -#define K_SYSCALL_GPIO_PORT_SET_BITS_RAW 27 -#define K_SYSCALL_GPIO_PORT_SET_MASKED_RAW 28 -#define K_SYSCALL_GPIO_PORT_TOGGLE_BITS 29 -#define K_SYSCALL_HWINFO_CLEAR_RESET_CAUSE 30 -#define K_SYSCALL_HWINFO_GET_DEVICE_EUI64 31 -#define K_SYSCALL_HWINFO_GET_DEVICE_ID 32 -#define K_SYSCALL_HWINFO_GET_RESET_CAUSE 33 -#define K_SYSCALL_HWINFO_GET_SUPPORTED_RESET_CAUSE 34 -#define K_SYSCALL_I2C_CONFIGURE 35 -#define K_SYSCALL_I2C_GET_CONFIG 36 -#define K_SYSCALL_I2C_RECOVER_BUS 37 -#define K_SYSCALL_I2C_TARGET_DRIVER_REGISTER 38 -#define K_SYSCALL_I2C_TARGET_DRIVER_UNREGISTER 39 -#define K_SYSCALL_I2C_TRANSFER 40 -#define K_SYSCALL_K_BUSY_WAIT 41 -#define K_SYSCALL_K_CONDVAR_BROADCAST 42 -#define K_SYSCALL_K_CONDVAR_INIT 43 -#define K_SYSCALL_K_CONDVAR_SIGNAL 44 -#define K_SYSCALL_K_CONDVAR_WAIT 45 -#define K_SYSCALL_K_EVENT_CLEAR 46 -#define K_SYSCALL_K_EVENT_INIT 47 -#define K_SYSCALL_K_EVENT_POST 48 -#define K_SYSCALL_K_EVENT_SET 49 -#define K_SYSCALL_K_EVENT_SET_MASKED 50 -#define K_SYSCALL_K_EVENT_WAIT 51 -#define K_SYSCALL_K_EVENT_WAIT_ALL 52 -#define K_SYSCALL_K_FLOAT_DISABLE 53 -#define K_SYSCALL_K_FLOAT_ENABLE 54 -#define K_SYSCALL_K_FUTEX_WAIT 55 -#define K_SYSCALL_K_FUTEX_WAKE 56 -#define K_SYSCALL_K_IS_PREEMPT_THREAD 57 -#define K_SYSCALL_K_MSGQ_ALLOC_INIT 58 -#define K_SYSCALL_K_MSGQ_GET 59 -#define K_SYSCALL_K_MSGQ_GET_ATTRS 60 -#define K_SYSCALL_K_MSGQ_NUM_FREE_GET 61 -#define K_SYSCALL_K_MSGQ_NUM_USED_GET 62 -#define K_SYSCALL_K_MSGQ_PEEK 63 -#define K_SYSCALL_K_MSGQ_PEEK_AT 64 -#define K_SYSCALL_K_MSGQ_PURGE 65 -#define K_SYSCALL_K_MSGQ_PUT 66 -#define K_SYSCALL_K_MUTEX_INIT 67 -#define K_SYSCALL_K_MUTEX_LOCK 68 -#define K_SYSCALL_K_MUTEX_UNLOCK 69 -#define K_SYSCALL_K_OBJECT_ACCESS_GRANT 70 -#define K_SYSCALL_K_OBJECT_ALLOC 71 -#define K_SYSCALL_K_OBJECT_ALLOC_SIZE 72 -#define K_SYSCALL_K_OBJECT_RELEASE 73 -#define K_SYSCALL_K_PIPE_ALLOC_INIT 74 -#define K_SYSCALL_K_PIPE_BUFFER_FLUSH 75 -#define K_SYSCALL_K_PIPE_FLUSH 76 -#define K_SYSCALL_K_PIPE_GET 77 -#define K_SYSCALL_K_PIPE_PUT 78 -#define K_SYSCALL_K_PIPE_READ_AVAIL 79 -#define K_SYSCALL_K_PIPE_WRITE_AVAIL 80 -#define K_SYSCALL_K_POLL 81 -#define K_SYSCALL_K_POLL_SIGNAL_CHECK 82 -#define K_SYSCALL_K_POLL_SIGNAL_INIT 83 -#define K_SYSCALL_K_POLL_SIGNAL_RAISE 84 -#define K_SYSCALL_K_POLL_SIGNAL_RESET 85 -#define K_SYSCALL_K_QUEUE_ALLOC_APPEND 86 -#define K_SYSCALL_K_QUEUE_ALLOC_PREPEND 87 -#define K_SYSCALL_K_QUEUE_CANCEL_WAIT 88 -#define K_SYSCALL_K_QUEUE_GET 89 -#define K_SYSCALL_K_QUEUE_INIT 90 -#define K_SYSCALL_K_QUEUE_IS_EMPTY 91 -#define K_SYSCALL_K_QUEUE_PEEK_HEAD 92 -#define K_SYSCALL_K_QUEUE_PEEK_TAIL 93 -#define K_SYSCALL_K_SCHED_CURRENT_THREAD_QUERY 94 -#define K_SYSCALL_K_SEM_COUNT_GET 95 -#define K_SYSCALL_K_SEM_GIVE 96 -#define K_SYSCALL_K_SEM_INIT 97 -#define K_SYSCALL_K_SEM_RESET 98 -#define K_SYSCALL_K_SEM_TAKE 99 -#define K_SYSCALL_K_SLEEP 100 -#define K_SYSCALL_K_STACK_ALLOC_INIT 101 -#define K_SYSCALL_K_STACK_POP 102 -#define K_SYSCALL_K_STACK_PUSH 103 -#define K_SYSCALL_K_STR_OUT 104 -#define K_SYSCALL_K_THREAD_ABORT 105 -#define K_SYSCALL_K_THREAD_CREATE 106 -#define K_SYSCALL_K_THREAD_CUSTOM_DATA_GET 107 -#define K_SYSCALL_K_THREAD_CUSTOM_DATA_SET 108 -#define K_SYSCALL_K_THREAD_DEADLINE_SET 109 -#define K_SYSCALL_K_THREAD_JOIN 110 -#define K_SYSCALL_K_THREAD_NAME_COPY 111 -#define K_SYSCALL_K_THREAD_NAME_SET 112 -#define K_SYSCALL_K_THREAD_PRIORITY_GET 113 -#define K_SYSCALL_K_THREAD_PRIORITY_SET 114 -#define K_SYSCALL_K_THREAD_RESUME 115 -#define K_SYSCALL_K_THREAD_STACK_ALLOC 116 -#define K_SYSCALL_K_THREAD_STACK_FREE 117 -#define K_SYSCALL_K_THREAD_STACK_SPACE_GET 118 -#define K_SYSCALL_K_THREAD_START 119 -#define K_SYSCALL_K_THREAD_SUSPEND 120 -#define K_SYSCALL_K_THREAD_TIMEOUT_EXPIRES_TICKS 121 -#define K_SYSCALL_K_THREAD_TIMEOUT_REMAINING_TICKS 122 -#define K_SYSCALL_K_TIMER_EXPIRES_TICKS 123 -#define K_SYSCALL_K_TIMER_REMAINING_TICKS 124 -#define K_SYSCALL_K_TIMER_START 125 -#define K_SYSCALL_K_TIMER_STATUS_GET 126 -#define K_SYSCALL_K_TIMER_STATUS_SYNC 127 -#define K_SYSCALL_K_TIMER_STOP 128 -#define K_SYSCALL_K_TIMER_USER_DATA_GET 129 -#define K_SYSCALL_K_TIMER_USER_DATA_SET 130 -#define K_SYSCALL_K_UPTIME_TICKS 131 -#define K_SYSCALL_K_USLEEP 132 -#define K_SYSCALL_K_WAKEUP 133 -#define K_SYSCALL_K_YIELD 134 -#define K_SYSCALL_LLEXT_GET_FN_TABLE 135 -#define K_SYSCALL_LOG_BUFFERED_CNT 136 -#define K_SYSCALL_LOG_FILTER_SET 137 -#define K_SYSCALL_LOG_FRONTEND_FILTER_SET 138 -#define K_SYSCALL_LOG_PANIC 139 -#define K_SYSCALL_LOG_PROCESS 140 -#define K_SYSCALL_PWM_CAPTURE_CYCLES 141 -#define K_SYSCALL_PWM_DISABLE_CAPTURE 142 -#define K_SYSCALL_PWM_ENABLE_CAPTURE 143 -#define K_SYSCALL_PWM_GET_CYCLES_PER_SEC 144 -#define K_SYSCALL_PWM_SET_CYCLES 145 -#define K_SYSCALL_RESET_LINE_ASSERT 146 -#define K_SYSCALL_RESET_LINE_DEASSERT 147 -#define K_SYSCALL_RESET_LINE_TOGGLE 148 -#define K_SYSCALL_RESET_STATUS 149 -#define K_SYSCALL_SPI_RELEASE 150 -#define K_SYSCALL_SPI_TRANSCEIVE 151 -#define K_SYSCALL_SYS_CACHE_DATA_FLUSH_AND_INVD_RANGE 152 -#define K_SYSCALL_SYS_CACHE_DATA_FLUSH_RANGE 153 -#define K_SYSCALL_SYS_CACHE_DATA_INVD_RANGE 154 -#define K_SYSCALL_SYS_CLOCK_HW_CYCLES_PER_SEC_RUNTIME_GET 155 -#define K_SYSCALL_UART_CONFIGURE 156 -#define K_SYSCALL_UART_CONFIG_GET 157 -#define K_SYSCALL_UART_DRV_CMD 158 -#define K_SYSCALL_UART_ERR_CHECK 159 -#define K_SYSCALL_UART_IRQ_ERR_DISABLE 160 -#define K_SYSCALL_UART_IRQ_ERR_ENABLE 161 -#define K_SYSCALL_UART_IRQ_IS_PENDING 162 -#define K_SYSCALL_UART_IRQ_RX_DISABLE 163 -#define K_SYSCALL_UART_IRQ_RX_ENABLE 164 -#define K_SYSCALL_UART_IRQ_TX_DISABLE 165 -#define K_SYSCALL_UART_IRQ_TX_ENABLE 166 -#define K_SYSCALL_UART_IRQ_UPDATE 167 -#define K_SYSCALL_UART_LINE_CTRL_GET 168 -#define K_SYSCALL_UART_LINE_CTRL_SET 169 -#define K_SYSCALL_UART_POLL_IN 170 -#define K_SYSCALL_UART_POLL_IN_U16 171 -#define K_SYSCALL_UART_POLL_OUT 172 -#define K_SYSCALL_UART_POLL_OUT_U16 173 -#define K_SYSCALL_UART_RX_DISABLE 174 -#define K_SYSCALL_UART_RX_ENABLE 175 -#define K_SYSCALL_UART_RX_ENABLE_U16 176 -#define K_SYSCALL_UART_TX 177 -#define K_SYSCALL_UART_TX_ABORT 178 -#define K_SYSCALL_UART_TX_U16 179 -#define K_SYSCALL_ZEPHYR_FPUTC 180 -#define K_SYSCALL_ZEPHYR_FWRITE 181 -#define K_SYSCALL_ZEPHYR_READ_STDIN 182 -#define K_SYSCALL_ZEPHYR_WRITE_STDOUT 183 -#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_0 184 -#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_1 185 -#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_2 186 -#define K_SYSCALL_Z_LOG_MSG_STATIC_CREATE 187 -#define K_SYSCALL_Z_SYS_MUTEX_KERNEL_LOCK 188 -#define K_SYSCALL_Z_SYS_MUTEX_KERNEL_UNLOCK 189 -#define K_SYSCALL_BAD 190 -#define K_SYSCALL_LIMIT 191 +#define K_SYSCALL_DMA_CHAN_FILTER 7 +#define K_SYSCALL_DMA_RELEASE_CHANNEL 8 +#define K_SYSCALL_DMA_REQUEST_CHANNEL 9 +#define K_SYSCALL_DMA_RESUME 10 +#define K_SYSCALL_DMA_START 11 +#define K_SYSCALL_DMA_STOP 12 +#define K_SYSCALL_DMA_SUSPEND 13 +#define K_SYSCALL_FLASH_ERASE 14 +#define K_SYSCALL_FLASH_EX_OP 15 +#define K_SYSCALL_FLASH_FILL 16 +#define K_SYSCALL_FLASH_FLATTEN 17 +#define K_SYSCALL_FLASH_GET_PAGE_COUNT 18 +#define K_SYSCALL_FLASH_GET_PAGE_INFO_BY_IDX 19 +#define K_SYSCALL_FLASH_GET_PAGE_INFO_BY_OFFS 20 +#define K_SYSCALL_FLASH_GET_PARAMETERS 21 +#define K_SYSCALL_FLASH_GET_WRITE_BLOCK_SIZE 22 +#define K_SYSCALL_FLASH_READ 23 +#define K_SYSCALL_FLASH_READ_JEDEC_ID 24 +#define K_SYSCALL_FLASH_SFDP_READ 25 +#define K_SYSCALL_FLASH_WRITE 26 +#define K_SYSCALL_GPIO_GET_PENDING_INT 27 +#define K_SYSCALL_GPIO_PIN_CONFIGURE 28 +#define K_SYSCALL_GPIO_PIN_GET_CONFIG 29 +#define K_SYSCALL_GPIO_PIN_INTERRUPT_CONFIGURE 30 +#define K_SYSCALL_GPIO_PORT_CLEAR_BITS_RAW 31 +#define K_SYSCALL_GPIO_PORT_GET_DIRECTION 32 +#define K_SYSCALL_GPIO_PORT_GET_RAW 33 +#define K_SYSCALL_GPIO_PORT_SET_BITS_RAW 34 +#define K_SYSCALL_GPIO_PORT_SET_MASKED_RAW 35 +#define K_SYSCALL_GPIO_PORT_TOGGLE_BITS 36 +#define K_SYSCALL_HWINFO_CLEAR_RESET_CAUSE 37 +#define K_SYSCALL_HWINFO_GET_DEVICE_EUI64 38 +#define K_SYSCALL_HWINFO_GET_DEVICE_ID 39 +#define K_SYSCALL_HWINFO_GET_RESET_CAUSE 40 +#define K_SYSCALL_HWINFO_GET_SUPPORTED_RESET_CAUSE 41 +#define K_SYSCALL_I2C_CONFIGURE 42 +#define K_SYSCALL_I2C_GET_CONFIG 43 +#define K_SYSCALL_I2C_RECOVER_BUS 44 +#define K_SYSCALL_I2C_TARGET_DRIVER_REGISTER 45 +#define K_SYSCALL_I2C_TARGET_DRIVER_UNREGISTER 46 +#define K_SYSCALL_I2C_TRANSFER 47 +#define K_SYSCALL_K_BUSY_WAIT 48 +#define K_SYSCALL_K_CONDVAR_BROADCAST 49 +#define K_SYSCALL_K_CONDVAR_INIT 50 +#define K_SYSCALL_K_CONDVAR_SIGNAL 51 +#define K_SYSCALL_K_CONDVAR_WAIT 52 +#define K_SYSCALL_K_EVENT_CLEAR 53 +#define K_SYSCALL_K_EVENT_INIT 54 +#define K_SYSCALL_K_EVENT_POST 55 +#define K_SYSCALL_K_EVENT_SET 56 +#define K_SYSCALL_K_EVENT_SET_MASKED 57 +#define K_SYSCALL_K_EVENT_WAIT 58 +#define K_SYSCALL_K_EVENT_WAIT_ALL 59 +#define K_SYSCALL_K_FLOAT_DISABLE 60 +#define K_SYSCALL_K_FLOAT_ENABLE 61 +#define K_SYSCALL_K_FUTEX_WAIT 62 +#define K_SYSCALL_K_FUTEX_WAKE 63 +#define K_SYSCALL_K_IS_PREEMPT_THREAD 64 +#define K_SYSCALL_K_MSGQ_ALLOC_INIT 65 +#define K_SYSCALL_K_MSGQ_GET 66 +#define K_SYSCALL_K_MSGQ_GET_ATTRS 67 +#define K_SYSCALL_K_MSGQ_NUM_FREE_GET 68 +#define K_SYSCALL_K_MSGQ_NUM_USED_GET 69 +#define K_SYSCALL_K_MSGQ_PEEK 70 +#define K_SYSCALL_K_MSGQ_PEEK_AT 71 +#define K_SYSCALL_K_MSGQ_PURGE 72 +#define K_SYSCALL_K_MSGQ_PUT 73 +#define K_SYSCALL_K_MUTEX_INIT 74 +#define K_SYSCALL_K_MUTEX_LOCK 75 +#define K_SYSCALL_K_MUTEX_UNLOCK 76 +#define K_SYSCALL_K_OBJECT_ACCESS_GRANT 77 +#define K_SYSCALL_K_OBJECT_ALLOC 78 +#define K_SYSCALL_K_OBJECT_ALLOC_SIZE 79 +#define K_SYSCALL_K_OBJECT_RELEASE 80 +#define K_SYSCALL_K_PIPE_ALLOC_INIT 81 +#define K_SYSCALL_K_PIPE_BUFFER_FLUSH 82 +#define K_SYSCALL_K_PIPE_FLUSH 83 +#define K_SYSCALL_K_PIPE_GET 84 +#define K_SYSCALL_K_PIPE_PUT 85 +#define K_SYSCALL_K_PIPE_READ_AVAIL 86 +#define K_SYSCALL_K_PIPE_WRITE_AVAIL 87 +#define K_SYSCALL_K_POLL 88 +#define K_SYSCALL_K_POLL_SIGNAL_CHECK 89 +#define K_SYSCALL_K_POLL_SIGNAL_INIT 90 +#define K_SYSCALL_K_POLL_SIGNAL_RAISE 91 +#define K_SYSCALL_K_POLL_SIGNAL_RESET 92 +#define K_SYSCALL_K_QUEUE_ALLOC_APPEND 93 +#define K_SYSCALL_K_QUEUE_ALLOC_PREPEND 94 +#define K_SYSCALL_K_QUEUE_CANCEL_WAIT 95 +#define K_SYSCALL_K_QUEUE_GET 96 +#define K_SYSCALL_K_QUEUE_INIT 97 +#define K_SYSCALL_K_QUEUE_IS_EMPTY 98 +#define K_SYSCALL_K_QUEUE_PEEK_HEAD 99 +#define K_SYSCALL_K_QUEUE_PEEK_TAIL 100 +#define K_SYSCALL_K_SCHED_CURRENT_THREAD_QUERY 101 +#define K_SYSCALL_K_SEM_COUNT_GET 102 +#define K_SYSCALL_K_SEM_GIVE 103 +#define K_SYSCALL_K_SEM_INIT 104 +#define K_SYSCALL_K_SEM_RESET 105 +#define K_SYSCALL_K_SEM_TAKE 106 +#define K_SYSCALL_K_SLEEP 107 +#define K_SYSCALL_K_STACK_ALLOC_INIT 108 +#define K_SYSCALL_K_STACK_POP 109 +#define K_SYSCALL_K_STACK_PUSH 110 +#define K_SYSCALL_K_STR_OUT 111 +#define K_SYSCALL_K_THREAD_ABORT 112 +#define K_SYSCALL_K_THREAD_CREATE 113 +#define K_SYSCALL_K_THREAD_CUSTOM_DATA_GET 114 +#define K_SYSCALL_K_THREAD_CUSTOM_DATA_SET 115 +#define K_SYSCALL_K_THREAD_DEADLINE_SET 116 +#define K_SYSCALL_K_THREAD_JOIN 117 +#define K_SYSCALL_K_THREAD_NAME_COPY 118 +#define K_SYSCALL_K_THREAD_NAME_SET 119 +#define K_SYSCALL_K_THREAD_PRIORITY_GET 120 +#define K_SYSCALL_K_THREAD_PRIORITY_SET 121 +#define K_SYSCALL_K_THREAD_RESUME 122 +#define K_SYSCALL_K_THREAD_STACK_ALLOC 123 +#define K_SYSCALL_K_THREAD_STACK_FREE 124 +#define K_SYSCALL_K_THREAD_STACK_SPACE_GET 125 +#define K_SYSCALL_K_THREAD_START 126 +#define K_SYSCALL_K_THREAD_SUSPEND 127 +#define K_SYSCALL_K_THREAD_TIMEOUT_EXPIRES_TICKS 128 +#define K_SYSCALL_K_THREAD_TIMEOUT_REMAINING_TICKS 129 +#define K_SYSCALL_K_TIMER_EXPIRES_TICKS 130 +#define K_SYSCALL_K_TIMER_REMAINING_TICKS 131 +#define K_SYSCALL_K_TIMER_START 132 +#define K_SYSCALL_K_TIMER_STATUS_GET 133 +#define K_SYSCALL_K_TIMER_STATUS_SYNC 134 +#define K_SYSCALL_K_TIMER_STOP 135 +#define K_SYSCALL_K_TIMER_USER_DATA_GET 136 +#define K_SYSCALL_K_TIMER_USER_DATA_SET 137 +#define K_SYSCALL_K_UPTIME_TICKS 138 +#define K_SYSCALL_K_USLEEP 139 +#define K_SYSCALL_K_WAKEUP 140 +#define K_SYSCALL_K_YIELD 141 +#define K_SYSCALL_LLEXT_GET_FN_TABLE 142 +#define K_SYSCALL_LOG_BUFFERED_CNT 143 +#define K_SYSCALL_LOG_FILTER_SET 144 +#define K_SYSCALL_LOG_FRONTEND_FILTER_SET 145 +#define K_SYSCALL_LOG_PANIC 146 +#define K_SYSCALL_LOG_PROCESS 147 +#define K_SYSCALL_PWM_CAPTURE_CYCLES 148 +#define K_SYSCALL_PWM_DISABLE_CAPTURE 149 +#define K_SYSCALL_PWM_ENABLE_CAPTURE 150 +#define K_SYSCALL_PWM_GET_CYCLES_PER_SEC 151 +#define K_SYSCALL_PWM_SET_CYCLES 152 +#define K_SYSCALL_RESET_LINE_ASSERT 153 +#define K_SYSCALL_RESET_LINE_DEASSERT 154 +#define K_SYSCALL_RESET_LINE_TOGGLE 155 +#define K_SYSCALL_RESET_STATUS 156 +#define K_SYSCALL_SPI_RELEASE 157 +#define K_SYSCALL_SPI_TRANSCEIVE 158 +#define K_SYSCALL_SYS_CACHE_DATA_FLUSH_AND_INVD_RANGE 159 +#define K_SYSCALL_SYS_CACHE_DATA_FLUSH_RANGE 160 +#define K_SYSCALL_SYS_CACHE_DATA_INVD_RANGE 161 +#define K_SYSCALL_SYS_CLOCK_HW_CYCLES_PER_SEC_RUNTIME_GET 162 +#define K_SYSCALL_UART_CONFIGURE 163 +#define K_SYSCALL_UART_CONFIG_GET 164 +#define K_SYSCALL_UART_DRV_CMD 165 +#define K_SYSCALL_UART_ERR_CHECK 166 +#define K_SYSCALL_UART_IRQ_ERR_DISABLE 167 +#define K_SYSCALL_UART_IRQ_ERR_ENABLE 168 +#define K_SYSCALL_UART_IRQ_IS_PENDING 169 +#define K_SYSCALL_UART_IRQ_RX_DISABLE 170 +#define K_SYSCALL_UART_IRQ_RX_ENABLE 171 +#define K_SYSCALL_UART_IRQ_TX_DISABLE 172 +#define K_SYSCALL_UART_IRQ_TX_ENABLE 173 +#define K_SYSCALL_UART_IRQ_UPDATE 174 +#define K_SYSCALL_UART_LINE_CTRL_GET 175 +#define K_SYSCALL_UART_LINE_CTRL_SET 176 +#define K_SYSCALL_UART_POLL_IN 177 +#define K_SYSCALL_UART_POLL_IN_U16 178 +#define K_SYSCALL_UART_POLL_OUT 179 +#define K_SYSCALL_UART_POLL_OUT_U16 180 +#define K_SYSCALL_UART_RX_DISABLE 181 +#define K_SYSCALL_UART_RX_ENABLE 182 +#define K_SYSCALL_UART_RX_ENABLE_U16 183 +#define K_SYSCALL_UART_TX 184 +#define K_SYSCALL_UART_TX_ABORT 185 +#define K_SYSCALL_UART_TX_U16 186 +#define K_SYSCALL_ZEPHYR_FPUTC 187 +#define K_SYSCALL_ZEPHYR_FWRITE 188 +#define K_SYSCALL_ZEPHYR_READ_STDIN 189 +#define K_SYSCALL_ZEPHYR_WRITE_STDOUT 190 +#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_0 191 +#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_1 192 +#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_2 193 +#define K_SYSCALL_Z_LOG_MSG_STATIC_CREATE 194 +#define K_SYSCALL_Z_SYS_MUTEX_KERNEL_LOCK 195 +#define K_SYSCALL_Z_SYS_MUTEX_KERNEL_UNLOCK 196 +#define K_SYSCALL_BAD 197 +#define K_SYSCALL_LIMIT 198 /* Following syscalls are not used in image */ -#define K_SYSCALL_ATOMIC_ADD 192 -#define K_SYSCALL_ATOMIC_AND 193 -#define K_SYSCALL_ATOMIC_CAS 194 -#define K_SYSCALL_ATOMIC_NAND 195 -#define K_SYSCALL_ATOMIC_OR 196 -#define K_SYSCALL_ATOMIC_PTR_CAS 197 -#define K_SYSCALL_ATOMIC_PTR_SET 198 -#define K_SYSCALL_ATOMIC_SET 199 -#define K_SYSCALL_ATOMIC_SUB 200 -#define K_SYSCALL_ATOMIC_XOR 201 -#define K_SYSCALL_AUXDISPLAY_BACKLIGHT_GET 202 -#define K_SYSCALL_AUXDISPLAY_BACKLIGHT_SET 203 -#define K_SYSCALL_AUXDISPLAY_BRIGHTNESS_GET 204 -#define K_SYSCALL_AUXDISPLAY_BRIGHTNESS_SET 205 -#define K_SYSCALL_AUXDISPLAY_CAPABILITIES_GET 206 -#define K_SYSCALL_AUXDISPLAY_CLEAR 207 -#define K_SYSCALL_AUXDISPLAY_CURSOR_POSITION_GET 208 -#define K_SYSCALL_AUXDISPLAY_CURSOR_POSITION_SET 209 -#define K_SYSCALL_AUXDISPLAY_CURSOR_SET_ENABLED 210 -#define K_SYSCALL_AUXDISPLAY_CURSOR_SHIFT_SET 211 -#define K_SYSCALL_AUXDISPLAY_CUSTOM_CHARACTER_SET 212 -#define K_SYSCALL_AUXDISPLAY_CUSTOM_COMMAND 213 -#define K_SYSCALL_AUXDISPLAY_DISPLAY_OFF 214 -#define K_SYSCALL_AUXDISPLAY_DISPLAY_ON 215 -#define K_SYSCALL_AUXDISPLAY_DISPLAY_POSITION_GET 216 -#define K_SYSCALL_AUXDISPLAY_DISPLAY_POSITION_SET 217 -#define K_SYSCALL_AUXDISPLAY_IS_BUSY 218 -#define K_SYSCALL_AUXDISPLAY_POSITION_BLINKING_SET_ENABLED 219 -#define K_SYSCALL_AUXDISPLAY_WRITE 220 -#define K_SYSCALL_BBRAM_CHECK_INVALID 221 -#define K_SYSCALL_BBRAM_CHECK_POWER 222 -#define K_SYSCALL_BBRAM_CHECK_STANDBY_POWER 223 -#define K_SYSCALL_BBRAM_GET_SIZE 224 -#define K_SYSCALL_BBRAM_READ 225 -#define K_SYSCALL_BBRAM_WRITE 226 -#define K_SYSCALL_BC12_SET_RESULT_CB 227 -#define K_SYSCALL_BC12_SET_ROLE 228 -#define K_SYSCALL_CAN_ADD_RX_FILTER_MSGQ 229 -#define K_SYSCALL_CAN_CALC_TIMING 230 -#define K_SYSCALL_CAN_CALC_TIMING_DATA 231 -#define K_SYSCALL_CAN_GET_BITRATE_MAX 232 -#define K_SYSCALL_CAN_GET_BITRATE_MIN 233 -#define K_SYSCALL_CAN_GET_CAPABILITIES 234 -#define K_SYSCALL_CAN_GET_CORE_CLOCK 235 -#define K_SYSCALL_CAN_GET_MAX_FILTERS 236 -#define K_SYSCALL_CAN_GET_MODE 237 -#define K_SYSCALL_CAN_GET_STATE 238 -#define K_SYSCALL_CAN_GET_TIMING_DATA_MAX 239 -#define K_SYSCALL_CAN_GET_TIMING_DATA_MIN 240 -#define K_SYSCALL_CAN_GET_TIMING_MAX 241 -#define K_SYSCALL_CAN_GET_TIMING_MIN 242 -#define K_SYSCALL_CAN_GET_TRANSCEIVER 243 -#define K_SYSCALL_CAN_RECOVER 244 -#define K_SYSCALL_CAN_REMOVE_RX_FILTER 245 -#define K_SYSCALL_CAN_SEND 246 -#define K_SYSCALL_CAN_SET_BITRATE 247 -#define K_SYSCALL_CAN_SET_BITRATE_DATA 248 -#define K_SYSCALL_CAN_SET_MODE 249 -#define K_SYSCALL_CAN_SET_TIMING 250 -#define K_SYSCALL_CAN_SET_TIMING_DATA 251 -#define K_SYSCALL_CAN_START 252 -#define K_SYSCALL_CAN_STATS_GET_ACK_ERRORS 253 -#define K_SYSCALL_CAN_STATS_GET_BIT0_ERRORS 254 -#define K_SYSCALL_CAN_STATS_GET_BIT1_ERRORS 255 -#define K_SYSCALL_CAN_STATS_GET_BIT_ERRORS 256 -#define K_SYSCALL_CAN_STATS_GET_CRC_ERRORS 257 -#define K_SYSCALL_CAN_STATS_GET_FORM_ERRORS 258 -#define K_SYSCALL_CAN_STATS_GET_RX_OVERRUNS 259 -#define K_SYSCALL_CAN_STATS_GET_STUFF_ERRORS 260 -#define K_SYSCALL_CAN_STOP 261 -#define K_SYSCALL_CHARGER_CHARGE_ENABLE 262 -#define K_SYSCALL_CHARGER_GET_PROP 263 -#define K_SYSCALL_CHARGER_SET_PROP 264 -#define K_SYSCALL_COUNTER_CANCEL_CHANNEL_ALARM 265 -#define K_SYSCALL_COUNTER_GET_FREQUENCY 266 -#define K_SYSCALL_COUNTER_GET_GUARD_PERIOD 267 -#define K_SYSCALL_COUNTER_GET_MAX_TOP_VALUE 268 -#define K_SYSCALL_COUNTER_GET_NUM_OF_CHANNELS 269 -#define K_SYSCALL_COUNTER_GET_PENDING_INT 270 -#define K_SYSCALL_COUNTER_GET_TOP_VALUE 271 -#define K_SYSCALL_COUNTER_GET_VALUE 272 -#define K_SYSCALL_COUNTER_GET_VALUE_64 273 -#define K_SYSCALL_COUNTER_IS_COUNTING_UP 274 -#define K_SYSCALL_COUNTER_SET_CHANNEL_ALARM 275 -#define K_SYSCALL_COUNTER_SET_GUARD_PERIOD 276 -#define K_SYSCALL_COUNTER_SET_TOP_VALUE 277 -#define K_SYSCALL_COUNTER_START 278 -#define K_SYSCALL_COUNTER_STOP 279 -#define K_SYSCALL_COUNTER_TICKS_TO_US 280 -#define K_SYSCALL_COUNTER_US_TO_TICKS 281 -#define K_SYSCALL_DAC_CHANNEL_SETUP 282 -#define K_SYSCALL_DAC_WRITE_VALUE 283 -#define K_SYSCALL_DEVMUX_SELECT_GET 284 -#define K_SYSCALL_DEVMUX_SELECT_SET 285 -#define K_SYSCALL_DMA_CHAN_FILTER 286 -#define K_SYSCALL_DMA_RELEASE_CHANNEL 287 -#define K_SYSCALL_DMA_REQUEST_CHANNEL 288 -#define K_SYSCALL_DMA_RESUME 289 -#define K_SYSCALL_DMA_START 290 -#define K_SYSCALL_DMA_STOP 291 -#define K_SYSCALL_DMA_SUSPEND 292 +#define K_SYSCALL_ATOMIC_ADD 199 +#define K_SYSCALL_ATOMIC_AND 200 +#define K_SYSCALL_ATOMIC_CAS 201 +#define K_SYSCALL_ATOMIC_NAND 202 +#define K_SYSCALL_ATOMIC_OR 203 +#define K_SYSCALL_ATOMIC_PTR_CAS 204 +#define K_SYSCALL_ATOMIC_PTR_SET 205 +#define K_SYSCALL_ATOMIC_SET 206 +#define K_SYSCALL_ATOMIC_SUB 207 +#define K_SYSCALL_ATOMIC_XOR 208 +#define K_SYSCALL_AUXDISPLAY_BACKLIGHT_GET 209 +#define K_SYSCALL_AUXDISPLAY_BACKLIGHT_SET 210 +#define K_SYSCALL_AUXDISPLAY_BRIGHTNESS_GET 211 +#define K_SYSCALL_AUXDISPLAY_BRIGHTNESS_SET 212 +#define K_SYSCALL_AUXDISPLAY_CAPABILITIES_GET 213 +#define K_SYSCALL_AUXDISPLAY_CLEAR 214 +#define K_SYSCALL_AUXDISPLAY_CURSOR_POSITION_GET 215 +#define K_SYSCALL_AUXDISPLAY_CURSOR_POSITION_SET 216 +#define K_SYSCALL_AUXDISPLAY_CURSOR_SET_ENABLED 217 +#define K_SYSCALL_AUXDISPLAY_CURSOR_SHIFT_SET 218 +#define K_SYSCALL_AUXDISPLAY_CUSTOM_CHARACTER_SET 219 +#define K_SYSCALL_AUXDISPLAY_CUSTOM_COMMAND 220 +#define K_SYSCALL_AUXDISPLAY_DISPLAY_OFF 221 +#define K_SYSCALL_AUXDISPLAY_DISPLAY_ON 222 +#define K_SYSCALL_AUXDISPLAY_DISPLAY_POSITION_GET 223 +#define K_SYSCALL_AUXDISPLAY_DISPLAY_POSITION_SET 224 +#define K_SYSCALL_AUXDISPLAY_IS_BUSY 225 +#define K_SYSCALL_AUXDISPLAY_POSITION_BLINKING_SET_ENABLED 226 +#define K_SYSCALL_AUXDISPLAY_WRITE 227 +#define K_SYSCALL_BBRAM_CHECK_INVALID 228 +#define K_SYSCALL_BBRAM_CHECK_POWER 229 +#define K_SYSCALL_BBRAM_CHECK_STANDBY_POWER 230 +#define K_SYSCALL_BBRAM_GET_SIZE 231 +#define K_SYSCALL_BBRAM_READ 232 +#define K_SYSCALL_BBRAM_WRITE 233 +#define K_SYSCALL_BC12_SET_RESULT_CB 234 +#define K_SYSCALL_BC12_SET_ROLE 235 +#define K_SYSCALL_CAN_ADD_RX_FILTER_MSGQ 236 +#define K_SYSCALL_CAN_CALC_TIMING 237 +#define K_SYSCALL_CAN_CALC_TIMING_DATA 238 +#define K_SYSCALL_CAN_GET_BITRATE_MAX 239 +#define K_SYSCALL_CAN_GET_BITRATE_MIN 240 +#define K_SYSCALL_CAN_GET_CAPABILITIES 241 +#define K_SYSCALL_CAN_GET_CORE_CLOCK 242 +#define K_SYSCALL_CAN_GET_MAX_FILTERS 243 +#define K_SYSCALL_CAN_GET_MODE 244 +#define K_SYSCALL_CAN_GET_STATE 245 +#define K_SYSCALL_CAN_GET_TIMING_DATA_MAX 246 +#define K_SYSCALL_CAN_GET_TIMING_DATA_MIN 247 +#define K_SYSCALL_CAN_GET_TIMING_MAX 248 +#define K_SYSCALL_CAN_GET_TIMING_MIN 249 +#define K_SYSCALL_CAN_GET_TRANSCEIVER 250 +#define K_SYSCALL_CAN_RECOVER 251 +#define K_SYSCALL_CAN_REMOVE_RX_FILTER 252 +#define K_SYSCALL_CAN_SEND 253 +#define K_SYSCALL_CAN_SET_BITRATE 254 +#define K_SYSCALL_CAN_SET_BITRATE_DATA 255 +#define K_SYSCALL_CAN_SET_MODE 256 +#define K_SYSCALL_CAN_SET_TIMING 257 +#define K_SYSCALL_CAN_SET_TIMING_DATA 258 +#define K_SYSCALL_CAN_START 259 +#define K_SYSCALL_CAN_STATS_GET_ACK_ERRORS 260 +#define K_SYSCALL_CAN_STATS_GET_BIT0_ERRORS 261 +#define K_SYSCALL_CAN_STATS_GET_BIT1_ERRORS 262 +#define K_SYSCALL_CAN_STATS_GET_BIT_ERRORS 263 +#define K_SYSCALL_CAN_STATS_GET_CRC_ERRORS 264 +#define K_SYSCALL_CAN_STATS_GET_FORM_ERRORS 265 +#define K_SYSCALL_CAN_STATS_GET_RX_OVERRUNS 266 +#define K_SYSCALL_CAN_STATS_GET_STUFF_ERRORS 267 +#define K_SYSCALL_CAN_STOP 268 +#define K_SYSCALL_CHARGER_CHARGE_ENABLE 269 +#define K_SYSCALL_CHARGER_GET_PROP 270 +#define K_SYSCALL_CHARGER_SET_PROP 271 +#define K_SYSCALL_COUNTER_CANCEL_CHANNEL_ALARM 272 +#define K_SYSCALL_COUNTER_GET_FREQUENCY 273 +#define K_SYSCALL_COUNTER_GET_GUARD_PERIOD 274 +#define K_SYSCALL_COUNTER_GET_MAX_TOP_VALUE 275 +#define K_SYSCALL_COUNTER_GET_NUM_OF_CHANNELS 276 +#define K_SYSCALL_COUNTER_GET_PENDING_INT 277 +#define K_SYSCALL_COUNTER_GET_TOP_VALUE 278 +#define K_SYSCALL_COUNTER_GET_VALUE 279 +#define K_SYSCALL_COUNTER_GET_VALUE_64 280 +#define K_SYSCALL_COUNTER_IS_COUNTING_UP 281 +#define K_SYSCALL_COUNTER_SET_CHANNEL_ALARM 282 +#define K_SYSCALL_COUNTER_SET_GUARD_PERIOD 283 +#define K_SYSCALL_COUNTER_SET_TOP_VALUE 284 +#define K_SYSCALL_COUNTER_START 285 +#define K_SYSCALL_COUNTER_STOP 286 +#define K_SYSCALL_COUNTER_TICKS_TO_US 287 +#define K_SYSCALL_COUNTER_US_TO_TICKS 288 +#define K_SYSCALL_DAC_CHANNEL_SETUP 289 +#define K_SYSCALL_DAC_WRITE_VALUE 290 +#define K_SYSCALL_DEVMUX_SELECT_GET 291 +#define K_SYSCALL_DEVMUX_SELECT_SET 292 #define K_SYSCALL_EEPROM_GET_SIZE 293 #define K_SYSCALL_EEPROM_READ 294 #define K_SYSCALL_EEPROM_WRITE 295 diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/autoconf.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/autoconf.h index 7b60fb7f..bda1e2c3 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/autoconf.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/autoconf.h @@ -34,6 +34,7 @@ #define CONFIG_FLASH_FILL_BUFFER_SIZE 32 #define CONFIG_GPIO 1 #define CONFIG_CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS 1 +#define CONFIG_MEMC 1 #define CONFIG_KERNEL_ENTRY "__start" #define CONFIG_CACHE 1 #define CONFIG_DCACHE 1 @@ -71,10 +72,15 @@ #define CONFIG_DT_HAS_GPIO_LEDS_ENABLED 1 #define CONFIG_DT_HAS_INFINEON_CYW43XXX_BT_HCI_ENABLED 1 #define CONFIG_DT_HAS_MMIO_SRAM_ENABLED 1 +#define CONFIG_DT_HAS_OVTI_OV7670_ENABLED 1 +#define CONFIG_DT_HAS_PWM_CLOCK_ENABLED 1 #define CONFIG_DT_HAS_SOC_NV_FLASH_ENABLED 1 #define CONFIG_DT_HAS_ST_MBOX_STM32_HSEM_ENABLED 1 #define CONFIG_DT_HAS_ST_STM32_ADC_ENABLED 1 #define CONFIG_DT_HAS_ST_STM32_DAC_ENABLED 1 +#define CONFIG_DT_HAS_ST_STM32_DCMI_ENABLED 1 +#define CONFIG_DT_HAS_ST_STM32_DMA_V1_ENABLED 1 +#define CONFIG_DT_HAS_ST_STM32_DMAMUX_ENABLED 1 #define CONFIG_DT_HAS_ST_STM32_EXTI_ENABLED 1 #define CONFIG_DT_HAS_ST_STM32_FLASH_CONTROLLER_ENABLED 1 #define CONFIG_DT_HAS_ST_STM32_FMC_SDRAM_ENABLED 1 @@ -86,12 +92,14 @@ #define CONFIG_DT_HAS_ST_STM32_NV_FLASH_ENABLED 1 #define CONFIG_DT_HAS_ST_STM32_OTGFS_ENABLED 1 #define CONFIG_DT_HAS_ST_STM32_PINCTRL_ENABLED 1 +#define CONFIG_DT_HAS_ST_STM32_PWM_ENABLED 1 #define CONFIG_DT_HAS_ST_STM32_QSPI_ENABLED 1 #define CONFIG_DT_HAS_ST_STM32_QSPI_NOR_ENABLED 1 #define CONFIG_DT_HAS_ST_STM32_RCC_RCTL_ENABLED 1 #define CONFIG_DT_HAS_ST_STM32_RNG_ENABLED 1 #define CONFIG_DT_HAS_ST_STM32_SPI_ENABLED 1 #define CONFIG_DT_HAS_ST_STM32_SPI_FIFO_ENABLED 1 +#define CONFIG_DT_HAS_ST_STM32_TIMERS_ENABLED 1 #define CONFIG_DT_HAS_ST_STM32_UART_ENABLED 1 #define CONFIG_DT_HAS_ST_STM32_USART_ENABLED 1 #define CONFIG_DT_HAS_ST_STM32H7_FDCAN_ENABLED 1 @@ -101,6 +109,7 @@ #define CONFIG_DT_HAS_ST_STM32H7_RCC_ENABLED 1 #define CONFIG_DT_HAS_ST_STM32H7_SPI_ENABLED 1 #define CONFIG_DT_HAS_USB_NOP_XCEIV_ENABLED 1 +#define CONFIG_DT_HAS_VND_GPIO_ENABLED 1 #define CONFIG_DT_HAS_ZEPHYR_BT_HCI_UART_ENABLED 1 #define CONFIG_DT_HAS_ZEPHYR_CDC_ACM_UART_ENABLED 1 #define CONFIG_DT_HAS_ZEPHYR_MEMORY_REGION_ENABLED 1 @@ -129,9 +138,13 @@ #define CONFIG_USE_STM32_HAL_PCD 1 #define CONFIG_USE_STM32_HAL_PCD_EX 1 #define CONFIG_USE_STM32_HAL_QSPI 1 +#define CONFIG_USE_STM32_HAL_SDRAM 1 +#define CONFIG_USE_STM32_LL_DMA 1 +#define CONFIG_USE_STM32_LL_FMC 1 #define CONFIG_USE_STM32_LL_I2C 1 #define CONFIG_USE_STM32_LL_RCC 1 #define CONFIG_USE_STM32_LL_SPI 1 +#define CONFIG_USE_STM32_LL_TIM 1 #define CONFIG_USE_STM32_LL_USB 1 #define CONFIG_USE_STM32_LL_UTILS 1 #define CONFIG_BOARD "arduino_giga_r1" @@ -262,12 +275,22 @@ #define CONFIG_CLOCK_STM32_HSE_CLOCK 16000000 #define CONFIG_CLOCK_STM32_MCO1_SRC_NOCLOCK 1 #define CONFIG_CLOCK_STM32_MCO2_SRC_NOCLOCK 1 +#define CONFIG_CLOCK_CONTROL_PWM 1 +#define CONFIG_CLOCK_CONTROL_PWM_INIT_PRIORITY 51 #define CONFIG_CONSOLE_INPUT_MAX_LINE_LEN 128 #define CONFIG_CONSOLE_HAS_DRIVER 1 #define CONFIG_CONSOLE_INIT_PRIORITY 60 #define CONFIG_UART_CONSOLE 1 #define CONFIG_UART_CONSOLE_LOG_LEVEL_DEFAULT 1 #define CONFIG_UART_CONSOLE_LOG_LEVEL 3 +#define CONFIG_DMA 1 +#define CONFIG_DMA_INIT_PRIORITY 40 +#define CONFIG_DMA_LOG_LEVEL_DEFAULT 1 +#define CONFIG_DMA_LOG_LEVEL 3 +#define CONFIG_DMA_STM32 1 +#define CONFIG_DMA_STM32_V1 1 +#define CONFIG_DMAMUX_STM32 1 +#define CONFIG_DMAMUX_STM32_INIT_PRIORITY 41 #define CONFIG_FLASH_HAS_DRIVER_ENABLED 1 #define CONFIG_FLASH_HAS_EXPLICIT_ERASE 1 #define CONFIG_FLASH_HAS_PAGE_LAYOUT 1 @@ -280,6 +303,7 @@ #define CONFIG_GPIO_LOG_LEVEL_DEFAULT 1 #define CONFIG_GPIO_LOG_LEVEL 3 #define CONFIG_GPIO_STM32 1 +#define CONFIG_GPIO_TEST 1 #define CONFIG_HWINFO 1 #define CONFIG_HWINFO_LOG_LEVEL_DEFAULT 1 #define CONFIG_HWINFO_LOG_LEVEL 3 @@ -294,6 +318,11 @@ #define CONFIG_INTC_LOG_LEVEL_DEFAULT 1 #define CONFIG_INTC_LOG_LEVEL 3 #define CONFIG_EXTI_STM32 1 +#define CONFIG_MEMC_LOG_LEVEL_DEFAULT 1 +#define CONFIG_MEMC_LOG_LEVEL 3 +#define CONFIG_MEMC_INIT_PRIORITY 0 +#define CONFIG_MEMC_STM32 1 +#define CONFIG_MEMC_STM32_SDRAM 1 #define CONFIG_PINCTRL_LOG_LEVEL_DEFAULT 1 #define CONFIG_PINCTRL_LOG_LEVEL 3 #define CONFIG_PINCTRL_STM32 1 @@ -302,9 +331,11 @@ #define CONFIG_PWM_LOG_LEVEL_DEFAULT 1 #define CONFIG_PWM_LOG_LEVEL 3 #define CONFIG_PWM_INIT_PRIORITY 50 +#define CONFIG_PWM_STM32 1 #define CONFIG_RESET_INIT_PRIORITY 35 #define CONFIG_RESET_STM32 1 #define CONFIG_SERIAL_HAS_DRIVER 1 +#define CONFIG_SERIAL_SUPPORT_ASYNC 1 #define CONFIG_SERIAL_SUPPORT_INTERRUPT 1 #define CONFIG_UART_LOG_LEVEL_DEFAULT 1 #define CONFIG_UART_LOG_LEVEL 3 @@ -508,5 +539,6 @@ #define CONFIG_BUILD_OUTPUT_STRIP_PATHS 1 #define CONFIG_CHECK_INIT_PRIORITIES 1 #define CONFIG_WARN_DEPRECATED 1 +#define CONFIG_EXPERIMENTAL 1 #define CONFIG_ENFORCE_ZEPHYR_STDINT 1 #define CONFIG_LEGACY_GENERATED_INCLUDE_PATH 1 diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/devicetree_generated.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/devicetree_generated.h index 9b4b01ac..230f4f95 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/devicetree_generated.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/devicetree_generated.h @@ -18,250 +18,282 @@ * 7 /clocks/clk-hse * 8 /clocks/pll@0 * 9 /soc/rcc@58024400 - * 10 /soc/adc@58026000 - * 11 /dietemp - * 12 /memory@24000000 - * 13 /memory@30000000 - * 14 /memory@30020000 - * 15 /memory@30040000 - * 16 /memory@38000000 - * 17 /memory@90000000 - * 18 /sdram@c0000000 - * 19 /soc/pin-controller@58020000 - * 20 /soc/pin-controller@58020000/i2c1_scl_pb8 - * 21 /soc/pin-controller@58020000/i2c1_sda_pb9 - * 22 /soc/i2c@40005400 - * 23 /smbus1 - * 24 /soc/pin-controller@58020000/i2c2_scl_ph4 - * 25 /soc/pin-controller@58020000/i2c2_sda_pb11 - * 26 /soc/i2c@40005800 - * 27 /smbus2 - * 28 /soc/i2c@40005c00 - * 29 /smbus3 - * 30 /soc/pin-controller@58020000/i2c4_scl_pb6 - * 31 /soc/pin-controller@58020000/i2c4_sda_ph12 - * 32 /soc/i2c@58001c00 - * 33 /smbus4 - * 34 /vbat - * 35 /vref - * 36 /soc/pin-controller@58020000/adc1_inp10_pc0 - * 37 /soc/pin-controller@58020000/adc1_inp12_pc2 - * 38 /soc/pin-controller@58020000/adc1_inp13_pc3 - * 39 /soc/pin-controller@58020000/adc1_inp16_pa0 - * 40 /soc/pin-controller@58020000/adc1_inp4_pc4 - * 41 /soc/pin-controller@58020000/adc1_inp5_pb1 - * 42 /soc/pin-controller@58020000/adc1_inp8_pc5 - * 43 /soc/pin-controller@58020000/adc1_inp9_pb0 - * 44 /soc/adc@40022000 - * 45 /soc/pin-controller@58020000/usart1_rx_pb7 - * 46 /soc/pin-controller@58020000/usart1_tx_pa9 - * 47 /soc/rcc@58024400/reset-controller - * 48 /soc/serial@40011000 - * 49 /soc/pin-controller@58020000/usart6_rx_pc7 - * 50 /soc/pin-controller@58020000/usart6_tx_pg14 - * 51 /soc/serial@40011400 - * 52 /soc/pin-controller@58020000/spi1_miso_pg9 - * 53 /soc/pin-controller@58020000/spi1_mosi_pd7 - * 54 /soc/pin-controller@58020000/spi1_nss_pa4 - * 55 /soc/pin-controller@58020000/spi1_sck_pb3 - * 56 /soc/spi@40013000 - * 57 /soc/pin-controller@58020000/spi5_miso_pj11 - * 58 /soc/pin-controller@58020000/spi5_mosi_pj10 - * 59 /soc/pin-controller@58020000/spi5_nss_pk1 - * 60 /soc/pin-controller@58020000/spi5_sck_ph6 - * 61 /soc/spi@40015000 - * 62 /soc/pin-controller@58020000/gpio@58020000 - * 63 /soc/pin-controller@58020000/gpio@58020400 - * 64 /soc/pin-controller@58020000/gpio@58020800 - * 65 /soc/pin-controller@58020000/gpio@58020C00 - * 66 /soc/pin-controller@58020000/gpio@58021000 - * 67 /soc/pin-controller@58020000/gpio@58021C00 - * 68 /soc/pin-controller@58020000/gpio@58022000 - * 69 /soc/pin-controller@58020000/gpio@58022400 - * 70 /soc/pin-controller@58020000/gpio@58022800 - * 71 /otghs_fs_phy - * 72 /soc/pin-controller@58020000/usb_otg_fs_dm_pa11 - * 73 /soc/pin-controller@58020000/usb_otg_fs_dp_pa12 - * 74 /soc/usb@40080000 - * 75 /soc/usb@40080000/cdc_acm_uart0 - * 76 /zephyr,user - * 77 /clocks/clk-csi - * 78 /clocks/clk-hsi - * 79 /clocks/clk-hsi48 - * 80 /clocks/clk-lse - * 81 /clocks/clk-lsi - * 82 /clocks/perck - * 83 /clocks/pll@1 - * 84 /clocks/pll@2 - * 85 /cpus - * 86 /cpus/cpu@0 - * 87 /cpus/cpu@0/mpu@e000ed90 - * 88 /gpio_keys - * 89 /gpio_keys/button_0 - * 90 /leds - * 91 /leds/led_0 - * 92 /leds/led_1 - * 93 /leds/led_2 - * 94 /soc/adc@40022100 - * 95 /soc/adc@40022300 - * 96 /soc/bdma@58025400 - * 97 /soc/can@4000a000 - * 98 /soc/pin-controller@58020000/fdcan2_rx_pb5 - * 99 /soc/pin-controller@58020000/fdcan2_tx_pb13 - * 100 /soc/can@4000a400 - * 101 /soc/pin-controller@58020000/dac1_out1_pa4 - * 102 /soc/pin-controller@58020000/dac1_out2_pa5 - * 103 /soc/dac@40007400 - * 104 /soc/dcmi@48020000 - * 105 /soc/display-controller@50001000 - * 106 /soc/dma@40020000 - * 107 /soc/dma@40020400 - * 108 /soc/dmamux@58025800 - * 109 /soc/dsihost@50000000 - * 110 /soc/dmamux@40020800 - * 111 /soc/i2s@40003800 - * 112 /soc/i2s@40003c00 - * 113 /soc/i2s@40013000 - * 114 /soc/interrupt-controller@58000000 - * 115 /soc/mailbox@58026400 - * 116 /soc/memory@38800000 - * 117 /soc/rng@48021800 - * 118 /soc/sdmmc@48022400 - * 119 /soc/sdmmc@52007000 - * 120 /soc/serial@40004400 - * 121 /soc/serial@40004800 - * 122 /soc/pin-controller@58020000/uart4_rx_pi9 - * 123 /soc/pin-controller@58020000/uart4_tx_ph13 - * 124 /soc/serial@40004c00 - * 125 /soc/serial@40005000 - * 126 /soc/serial@40007c00 - * 127 /soc/serial@58000c00 - * 128 /soc/spi@40003800 - * 129 /soc/spi@40003c00 - * 130 /soc/spi@40013400 - * 131 /soc/spi@58001400 - * 132 /soc/timer@e000e010 - * 133 /soc/timers@40002400 - * 134 /soc/usb@40040000 - * 135 /soc/watchdog@50003000 - * 136 /soc/watchdog@58004800 - * 137 /soc/adc@40022000/channel@4 - * 138 /soc/adc@40022000/channel@5 - * 139 /soc/adc@40022000/channel@8 - * 140 /soc/adc@40022000/channel@9 - * 141 /soc/adc@40022000/channel@10 - * 142 /soc/adc@40022000/channel@12 - * 143 /soc/adc@40022000/channel@13 - * 144 /soc/adc@40022000/channel@16 - * 145 /soc/ethernet@40028000 - * 146 /soc/ethernet@40028000/mdio - * 147 /soc/flash-controller@52002000 - * 148 /soc/flash-controller@52002000/flash@8000000 - * 149 /soc/flash-controller@52002000/flash@8000000/partitions - * 150 /soc/flash-controller@52002000/flash@8000000/partitions/partition@0 - * 151 /soc/flash-controller@52002000/flash@8000000/partitions/partition@40000 - * 152 /soc/pin-controller@58020000/fmc_a0_pf0 - * 153 /soc/pin-controller@58020000/fmc_a10_pg0 - * 154 /soc/pin-controller@58020000/fmc_a11_pg1 - * 155 /soc/pin-controller@58020000/fmc_a12_pg2 - * 156 /soc/pin-controller@58020000/fmc_a14_pg4 - * 157 /soc/pin-controller@58020000/fmc_a15_pg5 - * 158 /soc/pin-controller@58020000/fmc_a1_pf1 - * 159 /soc/pin-controller@58020000/fmc_a2_pf2 - * 160 /soc/pin-controller@58020000/fmc_a3_pf3 - * 161 /soc/pin-controller@58020000/fmc_a4_pf4 - * 162 /soc/pin-controller@58020000/fmc_a5_pf5 - * 163 /soc/pin-controller@58020000/fmc_a6_pf12 - * 164 /soc/pin-controller@58020000/fmc_a7_pf13 - * 165 /soc/pin-controller@58020000/fmc_a8_pf14 - * 166 /soc/pin-controller@58020000/fmc_a9_pf15 - * 167 /soc/pin-controller@58020000/fmc_d0_pd14 - * 168 /soc/pin-controller@58020000/fmc_d10_pe13 - * 169 /soc/pin-controller@58020000/fmc_d11_pe14 - * 170 /soc/pin-controller@58020000/fmc_d12_pe15 - * 171 /soc/pin-controller@58020000/fmc_d13_pd8 - * 172 /soc/pin-controller@58020000/fmc_d14_pd9 - * 173 /soc/pin-controller@58020000/fmc_d15_pd10 - * 174 /soc/pin-controller@58020000/fmc_d1_pd15 - * 175 /soc/pin-controller@58020000/fmc_d2_pd0 - * 176 /soc/pin-controller@58020000/fmc_d3_pd1 - * 177 /soc/pin-controller@58020000/fmc_d4_pe7 - * 178 /soc/pin-controller@58020000/fmc_d5_pe8 - * 179 /soc/pin-controller@58020000/fmc_d6_pe9 - * 180 /soc/pin-controller@58020000/fmc_d7_pe10 - * 181 /soc/pin-controller@58020000/fmc_d8_pe11 - * 182 /soc/pin-controller@58020000/fmc_d9_pe12 - * 183 /soc/pin-controller@58020000/fmc_nbl0_pe0 - * 184 /soc/pin-controller@58020000/fmc_nbl1_pe1 - * 185 /soc/pin-controller@58020000/fmc_sdcke0_ph2 - * 186 /soc/pin-controller@58020000/fmc_sdclk_pg8 - * 187 /soc/pin-controller@58020000/fmc_sdncas_pg15 - * 188 /soc/pin-controller@58020000/fmc_sdne0_ph3 - * 189 /soc/pin-controller@58020000/fmc_sdnras_pf11 - * 190 /soc/pin-controller@58020000/fmc_sdnwe_ph5 - * 191 /soc/memory-controller@52004000 - * 192 /soc/memory-controller@52004000/sdram - * 193 /soc/memory-controller@52004000/sdram/bank@0 - * 194 /soc/pin-controller@58020000/gpio@58021400 - * 195 /soc/pin-controller@58020000/quadspi_bk1_io0_pd11 - * 196 /soc/pin-controller@58020000/quadspi_bk1_io1_pd12 - * 197 /soc/pin-controller@58020000/quadspi_bk1_io2_pe2 - * 198 /soc/pin-controller@58020000/quadspi_bk1_io3_pf6 - * 199 /soc/pin-controller@58020000/quadspi_bk1_ncs_pg6 - * 200 /soc/pin-controller@58020000/quadspi_clk_pf10 - * 201 /soc/quadspi@52005000 - * 202 /soc/quadspi@52005000/qspi-nor-flash@90000000 - * 203 /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions - * 204 /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions/partition@0 - * 205 /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions/partition@100000 - * 206 /soc/rtc@58004000 - * 207 /soc/rtc@58004000/backup_regs - * 208 /soc/pin-controller@58020000/gpio@58021800 - * 209 /soc/pin-controller@58020000/uart7_cts_pf9 - * 210 /soc/pin-controller@58020000/uart7_rts_pf8 - * 211 /soc/pin-controller@58020000/uart7_rx_pa8 - * 212 /soc/pin-controller@58020000/uart7_tx_pf7 - * 213 /soc/serial@40007800 - * 214 /soc/serial@40007800/bt_hci_uart - * 215 /soc/serial@40007800/bt_hci_uart/murata-1dx - * 216 /soc/timers@40000000 - * 217 /soc/timers@40000000/counter - * 218 /soc/timers@40000000/pwm - * 219 /soc/timers@40000400 - * 220 /soc/timers@40000400/counter - * 221 /soc/timers@40000400/pwm - * 222 /soc/timers@40000800 - * 223 /soc/timers@40000800/counter - * 224 /soc/timers@40000800/pwm - * 225 /soc/timers@40000c00 - * 226 /soc/timers@40000c00/counter - * 227 /soc/timers@40000c00/pwm - * 228 /soc/timers@40001000 - * 229 /soc/timers@40001000/counter - * 230 /soc/timers@40001400 - * 231 /soc/timers@40001400/counter - * 232 /soc/timers@40001800 - * 233 /soc/timers@40001800/counter - * 234 /soc/timers@40001800/pwm - * 235 /soc/timers@40001c00 - * 236 /soc/timers@40001c00/counter - * 237 /soc/timers@40001c00/pwm - * 238 /soc/timers@40002000 - * 239 /soc/timers@40002000/counter - * 240 /soc/timers@40002000/pwm - * 241 /soc/timers@40010000 - * 242 /soc/timers@40010000/pwm - * 243 /soc/timers@40010400 - * 244 /soc/timers@40010400/pwm - * 245 /soc/timers@40014000 - * 246 /soc/timers@40014000/counter - * 247 /soc/timers@40014000/pwm - * 248 /soc/timers@40014400 - * 249 /soc/timers@40014400/counter - * 250 /soc/timers@40014400/pwm - * 251 /soc/timers@40014800 - * 252 /soc/timers@40014800/counter - * 253 /soc/timers@40014800/pwm + * 10 /soc/pin-controller@58020000 + * 11 /soc/pin-controller@58020000/adc3_inp0_pc2_c + * 12 /soc/pin-controller@58020000/adc3_inp1_pc3_c + * 13 /soc/adc@58026000 + * 14 /dietemp + * 15 /memory@24000000 + * 16 /memory@30000000 + * 17 /memory@30020000 + * 18 /memory@30040000 + * 19 /memory@38000000 + * 20 /memory@90000000 + * 21 /sdram@c0000000 + * 22 /soc/pin-controller@58020000/i2c1_scl_pb8 + * 23 /soc/pin-controller@58020000/i2c1_sda_pb9 + * 24 /soc/i2c@40005400 + * 25 /smbus1 + * 26 /soc/pin-controller@58020000/i2c2_scl_ph4 + * 27 /soc/pin-controller@58020000/i2c2_sda_pb11 + * 28 /soc/i2c@40005800 + * 29 /smbus2 + * 30 /soc/i2c@40005c00 + * 31 /smbus3 + * 32 /soc/pin-controller@58020000/i2c4_scl_pb6 + * 33 /soc/pin-controller@58020000/i2c4_sda_ph12 + * 34 /soc/i2c@58001c00 + * 35 /smbus4 + * 36 /vbat + * 37 /vref + * 38 /gpio@deadbeef + * 39 /soc/pin-controller@58020000/adc1_inp0_pa0_c + * 40 /soc/pin-controller@58020000/adc1_inp10_pc0 + * 41 /soc/pin-controller@58020000/adc1_inp12_pc2 + * 42 /soc/pin-controller@58020000/adc1_inp13_pc3 + * 43 /soc/pin-controller@58020000/adc1_inp16_pa0 + * 44 /soc/pin-controller@58020000/adc1_inp18_pa4 + * 45 /soc/pin-controller@58020000/adc1_inp19_pa5 + * 46 /soc/pin-controller@58020000/adc1_inp1_pa1_c + * 47 /soc/pin-controller@58020000/adc1_inp4_pc4 + * 48 /soc/pin-controller@58020000/adc1_inp5_pb1 + * 49 /soc/pin-controller@58020000/adc1_inp8_pc5 + * 50 /soc/pin-controller@58020000/adc1_inp9_pb0 + * 51 /soc/adc@40022000 + * 52 /soc/pin-controller@58020000/usart1_rx_pb7 + * 53 /soc/pin-controller@58020000/usart1_tx_pa9 + * 54 /soc/rcc@58024400/reset-controller + * 55 /soc/serial@40011000 + * 56 /soc/pin-controller@58020000/usart6_rx_pc7 + * 57 /soc/pin-controller@58020000/usart6_tx_pg14 + * 58 /soc/serial@40011400 + * 59 /soc/pin-controller@58020000/spi1_miso_pg9 + * 60 /soc/pin-controller@58020000/spi1_mosi_pd7 + * 61 /soc/pin-controller@58020000/spi1_nss_pa4 + * 62 /soc/pin-controller@58020000/spi1_sck_pb3 + * 63 /soc/spi@40013000 + * 64 /soc/pin-controller@58020000/spi5_miso_pj11 + * 65 /soc/pin-controller@58020000/spi5_mosi_pj10 + * 66 /soc/pin-controller@58020000/spi5_nss_pk1 + * 67 /soc/pin-controller@58020000/spi5_sck_ph6 + * 68 /soc/spi@40015000 + * 69 /soc/pin-controller@58020000/gpio@58020000 + * 70 /soc/pin-controller@58020000/gpio@58020400 + * 71 /soc/pin-controller@58020000/gpio@58020800 + * 72 /soc/pin-controller@58020000/gpio@58020C00 + * 73 /soc/pin-controller@58020000/gpio@58021000 + * 74 /soc/pin-controller@58020000/gpio@58021800 + * 75 /soc/pin-controller@58020000/gpio@58021C00 + * 76 /soc/pin-controller@58020000/gpio@58022000 + * 77 /soc/pin-controller@58020000/gpio@58022400 + * 78 /soc/pin-controller@58020000/gpio@58022800 + * 79 /soc/timers@40010000 + * 80 /soc/pin-controller@58020000/tim1_ch3_pj9 + * 81 /soc/timers@40010000/pwm + * 82 /otghs_fs_phy + * 83 /soc/pin-controller@58020000/usb_otg_fs_dm_pa11 + * 84 /soc/pin-controller@58020000/usb_otg_fs_dp_pa12 + * 85 /soc/usb@40080000 + * 86 /soc/usb@40080000/cdc_acm_uart0 + * 87 /zephyr,user + * 88 /clocks/clk-csi + * 89 /clocks/clk-hsi + * 90 /clocks/clk-hsi48 + * 91 /clocks/clk-lse + * 92 /clocks/clk-lsi + * 93 /clocks/perck + * 94 /clocks/pll@1 + * 95 /clocks/pll@2 + * 96 /cpus + * 97 /cpus/cpu@0 + * 98 /cpus/cpu@0/mpu@e000ed90 + * 99 /gpio_keys + * 100 /gpio_keys/button_0 + * 101 /leds + * 102 /leds/led_0 + * 103 /leds/led_1 + * 104 /leds/led_2 + * 105 /soc/adc@40022100 + * 106 /soc/adc@40022300 + * 107 /soc/bdma@58025400 + * 108 /soc/can@4000a000 + * 109 /soc/pin-controller@58020000/fdcan2_rx_pb5 + * 110 /soc/pin-controller@58020000/fdcan2_tx_pb13 + * 111 /soc/can@4000a400 + * 112 /soc/pin-controller@58020000/dac1_out1_pa4 + * 113 /soc/pin-controller@58020000/dac1_out2_pa5 + * 114 /soc/dac@40007400 + * 115 /soc/display-controller@50001000 + * 116 /soc/dma@40020400 + * 117 /soc/dmamux@58025800 + * 118 /soc/dsihost@50000000 + * 119 /soc/dmamux@40020800 + * 120 /soc/i2s@40003800 + * 121 /soc/i2s@40003c00 + * 122 /soc/i2s@40013000 + * 123 /soc/interrupt-controller@58000000 + * 124 /soc/mailbox@58026400 + * 125 /soc/memory@38800000 + * 126 /soc/rng@48021800 + * 127 /soc/sdmmc@48022400 + * 128 /soc/sdmmc@52007000 + * 129 /soc/serial@40004400 + * 130 /soc/serial@40004800 + * 131 /soc/pin-controller@58020000/uart4_rx_pi9 + * 132 /soc/pin-controller@58020000/uart4_tx_ph13 + * 133 /soc/serial@40004c00 + * 134 /soc/serial@40005000 + * 135 /soc/serial@40007c00 + * 136 /soc/serial@58000c00 + * 137 /soc/spi@40003800 + * 138 /soc/spi@40003c00 + * 139 /soc/spi@40013400 + * 140 /soc/spi@58001400 + * 141 /soc/timer@e000e010 + * 142 /soc/timers@40002400 + * 143 /soc/usb@40040000 + * 144 /soc/watchdog@50003000 + * 145 /soc/watchdog@58004800 + * 146 /soc/adc@40022000/channel@0 + * 147 /soc/adc@40022000/channel@1 + * 148 /soc/adc@40022000/channel@4 + * 149 /soc/adc@40022000/channel@5 + * 150 /soc/adc@40022000/channel@8 + * 151 /soc/adc@40022000/channel@9 + * 152 /soc/adc@40022000/channel@a + * 153 /soc/adc@40022000/channel@c + * 154 /soc/adc@40022000/channel@d + * 155 /soc/adc@40022000/channel@10 + * 156 /soc/adc@40022000/channel@12 + * 157 /soc/adc@40022000/channel@13 + * 158 /soc/adc@58026000/channel@0 + * 159 /soc/adc@58026000/channel@1 + * 160 /soc/dma@40020000 + * 161 /soc/i2c@58001c00/ov7670@21 + * 162 /soc/pin-controller@58020000/dcmi_d0_ph9 + * 163 /soc/pin-controller@58020000/dcmi_d1_ph10 + * 164 /soc/pin-controller@58020000/dcmi_d2_ph11 + * 165 /soc/pin-controller@58020000/dcmi_d3_pg11 + * 166 /soc/pin-controller@58020000/dcmi_d4_ph14 + * 167 /soc/pin-controller@58020000/dcmi_d5_pi4 + * 168 /soc/pin-controller@58020000/dcmi_d6_pi6 + * 169 /soc/pin-controller@58020000/dcmi_d7_pi7 + * 170 /soc/pin-controller@58020000/dcmi_hsync_ph8 + * 171 /soc/pin-controller@58020000/dcmi_pixclk_pa6 + * 172 /soc/pin-controller@58020000/dcmi_vsync_pi5 + * 173 /soc/dcmi@48020000 + * 174 /soc/dcmi@48020000/port + * 175 /soc/dcmi@48020000/port/endpoint + * 176 /soc/ethernet@40028000 + * 177 /soc/ethernet@40028000/mdio + * 178 /soc/flash-controller@52002000 + * 179 /soc/flash-controller@52002000/flash@8000000 + * 180 /soc/flash-controller@52002000/flash@8000000/partitions + * 181 /soc/flash-controller@52002000/flash@8000000/partitions/partition@0 + * 182 /soc/flash-controller@52002000/flash@8000000/partitions/partition@40000 + * 183 /soc/flash-controller@52002000/flash@8000000/partitions/partition@e0000 + * 184 /soc/i2c@58001c00/ov7670@21/port + * 185 /soc/i2c@58001c00/ov7670@21/port/endpoint + * 186 /soc/pin-controller@58020000/fmc_a0_pf0 + * 187 /soc/pin-controller@58020000/fmc_a10_pg0 + * 188 /soc/pin-controller@58020000/fmc_a11_pg1 + * 189 /soc/pin-controller@58020000/fmc_a12_pg2 + * 190 /soc/pin-controller@58020000/fmc_a14_pg4 + * 191 /soc/pin-controller@58020000/fmc_a15_pg5 + * 192 /soc/pin-controller@58020000/fmc_a1_pf1 + * 193 /soc/pin-controller@58020000/fmc_a2_pf2 + * 194 /soc/pin-controller@58020000/fmc_a3_pf3 + * 195 /soc/pin-controller@58020000/fmc_a4_pf4 + * 196 /soc/pin-controller@58020000/fmc_a5_pf5 + * 197 /soc/pin-controller@58020000/fmc_a6_pf12 + * 198 /soc/pin-controller@58020000/fmc_a7_pf13 + * 199 /soc/pin-controller@58020000/fmc_a8_pf14 + * 200 /soc/pin-controller@58020000/fmc_a9_pf15 + * 201 /soc/pin-controller@58020000/fmc_d0_pd14 + * 202 /soc/pin-controller@58020000/fmc_d10_pe13 + * 203 /soc/pin-controller@58020000/fmc_d11_pe14 + * 204 /soc/pin-controller@58020000/fmc_d12_pe15 + * 205 /soc/pin-controller@58020000/fmc_d13_pd8 + * 206 /soc/pin-controller@58020000/fmc_d14_pd9 + * 207 /soc/pin-controller@58020000/fmc_d15_pd10 + * 208 /soc/pin-controller@58020000/fmc_d1_pd15 + * 209 /soc/pin-controller@58020000/fmc_d2_pd0 + * 210 /soc/pin-controller@58020000/fmc_d3_pd1 + * 211 /soc/pin-controller@58020000/fmc_d4_pe7 + * 212 /soc/pin-controller@58020000/fmc_d5_pe8 + * 213 /soc/pin-controller@58020000/fmc_d6_pe9 + * 214 /soc/pin-controller@58020000/fmc_d7_pe10 + * 215 /soc/pin-controller@58020000/fmc_d8_pe11 + * 216 /soc/pin-controller@58020000/fmc_d9_pe12 + * 217 /soc/pin-controller@58020000/fmc_nbl0_pe0 + * 218 /soc/pin-controller@58020000/fmc_nbl1_pe1 + * 219 /soc/pin-controller@58020000/fmc_sdcke0_ph2 + * 220 /soc/pin-controller@58020000/fmc_sdclk_pg8 + * 221 /soc/pin-controller@58020000/fmc_sdncas_pg15 + * 222 /soc/pin-controller@58020000/fmc_sdne0_ph3 + * 223 /soc/pin-controller@58020000/fmc_sdnras_pf11 + * 224 /soc/pin-controller@58020000/fmc_sdnwe_ph5 + * 225 /soc/memory-controller@52004000 + * 226 /soc/memory-controller@52004000/sdram + * 227 /soc/memory-controller@52004000/sdram/bank@0 + * 228 /soc/pin-controller@58020000/gpio@58021400 + * 229 /soc/pin-controller@58020000/quadspi_bk1_io0_pd11 + * 230 /soc/pin-controller@58020000/quadspi_bk1_io1_pd12 + * 231 /soc/pin-controller@58020000/quadspi_bk1_io2_pe2 + * 232 /soc/pin-controller@58020000/quadspi_bk1_io3_pf6 + * 233 /soc/pin-controller@58020000/quadspi_bk1_ncs_pg6 + * 234 /soc/pin-controller@58020000/quadspi_clk_pf10 + * 235 /soc/quadspi@52005000 + * 236 /soc/quadspi@52005000/qspi-nor-flash@90000000 + * 237 /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions + * 238 /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions/partition@0 + * 239 /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions/partition@100000 + * 240 /soc/rtc@58004000 + * 241 /soc/rtc@58004000/backup_regs + * 242 /soc/pin-controller@58020000/uart7_cts_pf9 + * 243 /soc/pin-controller@58020000/uart7_rts_pf8 + * 244 /soc/pin-controller@58020000/uart7_rx_pa8 + * 245 /soc/pin-controller@58020000/uart7_tx_pf7 + * 246 /soc/serial@40007800 + * 247 /soc/serial@40007800/bt_hci_uart + * 248 /soc/serial@40007800/bt_hci_uart/murata-1dx + * 249 /soc/timers@40000000 + * 250 /soc/timers@40000000/counter + * 251 /soc/timers@40000000/pwm + * 252 /soc/timers@40000400 + * 253 /soc/timers@40000400/counter + * 254 /soc/timers@40000400/pwm + * 255 /soc/timers@40000800 + * 256 /soc/timers@40000800/counter + * 257 /soc/timers@40000800/pwm + * 258 /soc/timers@40000c00 + * 259 /soc/timers@40000c00/counter + * 260 /soc/timers@40000c00/pwm + * 261 /soc/timers@40001000 + * 262 /soc/timers@40001000/counter + * 263 /soc/timers@40001400 + * 264 /soc/timers@40001400/counter + * 265 /soc/timers@40001800 + * 266 /soc/timers@40001800/counter + * 267 /soc/timers@40001800/pwm + * 268 /soc/timers@40001c00 + * 269 /soc/timers@40001c00/counter + * 270 /soc/timers@40001c00/pwm + * 271 /soc/timers@40002000 + * 272 /soc/timers@40002000/counter + * 273 /soc/timers@40002000/pwm + * 274 /soc/timers@40010000/pwm/pwmclock + * 275 /soc/timers@40010400 + * 276 /soc/timers@40010400/pwm + * 277 /soc/timers@40014000 + * 278 /soc/timers@40014000/counter + * 279 /soc/timers@40014000/pwm + * 280 /soc/timers@40014400 + * 281 /soc/timers@40014400/counter + * 282 /soc/timers@40014400/pwm + * 283 /soc/timers@40014800 + * 284 /soc/timers@40014800/counter + * 285 /soc/timers@40014800/pwm * * Definitions derived from these nodes in dependency order are next, * followed by /chosen nodes. @@ -288,16 +320,16 @@ #define DT_N_FOREACH_NODELABEL_VARGS(fn, ...) /* Helper macros for child nodes of this node. */ -#define DT_N_CHILD_NUM 24 -#define DT_N_CHILD_NUM_STATUS_OKAY 17 -#define DT_N_FOREACH_CHILD(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_cpus) fn(DT_N_S_memory_90000000) fn(DT_N_S_clocks) fn(DT_N_S_dietemp) fn(DT_N_S_vbat) fn(DT_N_S_vref) fn(DT_N_S_smbus1) fn(DT_N_S_smbus2) fn(DT_N_S_smbus3) fn(DT_N_S_smbus4) fn(DT_N_S_memory_24000000) fn(DT_N_S_memory_30000000) fn(DT_N_S_memory_30020000) fn(DT_N_S_memory_30040000) fn(DT_N_S_memory_38000000) fn(DT_N_S_otghs_fs_phy) fn(DT_N_S_connector) fn(DT_N_S_leds) fn(DT_N_S_gpio_keys) fn(DT_N_S_sdram_c0000000) fn(DT_N_S_zephyr_user) -#define DT_N_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_90000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_dietemp) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vbat) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vref) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_24000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30040000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_38000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otghs_fs_phy) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sdram_c0000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_zephyr_user) -#define DT_N_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_memory_90000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_dietemp, __VA_ARGS__) fn(DT_N_S_vbat, __VA_ARGS__) fn(DT_N_S_vref, __VA_ARGS__) fn(DT_N_S_smbus1, __VA_ARGS__) fn(DT_N_S_smbus2, __VA_ARGS__) fn(DT_N_S_smbus3, __VA_ARGS__) fn(DT_N_S_smbus4, __VA_ARGS__) fn(DT_N_S_memory_24000000, __VA_ARGS__) fn(DT_N_S_memory_30000000, __VA_ARGS__) fn(DT_N_S_memory_30020000, __VA_ARGS__) fn(DT_N_S_memory_30040000, __VA_ARGS__) fn(DT_N_S_memory_38000000, __VA_ARGS__) fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__) fn(DT_N_S_sdram_c0000000, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__) -#define DT_N_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_90000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_dietemp, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vbat, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vref, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_24000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30040000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_38000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sdram_c0000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_zephyr_user, __VA_ARGS__) -#define DT_N_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_cpus) fn(DT_N_S_memory_90000000) fn(DT_N_S_clocks) fn(DT_N_S_memory_24000000) fn(DT_N_S_memory_30000000) fn(DT_N_S_memory_30020000) fn(DT_N_S_memory_30040000) fn(DT_N_S_memory_38000000) fn(DT_N_S_otghs_fs_phy) fn(DT_N_S_connector) fn(DT_N_S_leds) fn(DT_N_S_gpio_keys) fn(DT_N_S_sdram_c0000000) fn(DT_N_S_zephyr_user) -#define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_90000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_24000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30040000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_38000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otghs_fs_phy) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sdram_c0000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_zephyr_user) -#define DT_N_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_memory_90000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_memory_24000000, __VA_ARGS__) fn(DT_N_S_memory_30000000, __VA_ARGS__) fn(DT_N_S_memory_30020000, __VA_ARGS__) fn(DT_N_S_memory_30040000, __VA_ARGS__) fn(DT_N_S_memory_38000000, __VA_ARGS__) fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__) fn(DT_N_S_sdram_c0000000, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__) -#define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_90000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_24000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30040000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_38000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sdram_c0000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_zephyr_user, __VA_ARGS__) +#define DT_N_CHILD_NUM 25 +#define DT_N_CHILD_NUM_STATUS_OKAY 18 +#define DT_N_FOREACH_CHILD(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_cpus) fn(DT_N_S_memory_90000000) fn(DT_N_S_clocks) fn(DT_N_S_dietemp) fn(DT_N_S_vbat) fn(DT_N_S_vref) fn(DT_N_S_smbus1) fn(DT_N_S_smbus2) fn(DT_N_S_smbus3) fn(DT_N_S_smbus4) fn(DT_N_S_memory_24000000) fn(DT_N_S_memory_30000000) fn(DT_N_S_memory_30020000) fn(DT_N_S_memory_30040000) fn(DT_N_S_memory_38000000) fn(DT_N_S_otghs_fs_phy) fn(DT_N_S_connector) fn(DT_N_S_leds) fn(DT_N_S_gpio_keys) fn(DT_N_S_sdram_c0000000) fn(DT_N_S_gpio_deadbeef) fn(DT_N_S_zephyr_user) +#define DT_N_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_90000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_dietemp) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vbat) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vref) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_24000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30040000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_38000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otghs_fs_phy) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sdram_c0000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_deadbeef) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_zephyr_user) +#define DT_N_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_memory_90000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_dietemp, __VA_ARGS__) fn(DT_N_S_vbat, __VA_ARGS__) fn(DT_N_S_vref, __VA_ARGS__) fn(DT_N_S_smbus1, __VA_ARGS__) fn(DT_N_S_smbus2, __VA_ARGS__) fn(DT_N_S_smbus3, __VA_ARGS__) fn(DT_N_S_smbus4, __VA_ARGS__) fn(DT_N_S_memory_24000000, __VA_ARGS__) fn(DT_N_S_memory_30000000, __VA_ARGS__) fn(DT_N_S_memory_30020000, __VA_ARGS__) fn(DT_N_S_memory_30040000, __VA_ARGS__) fn(DT_N_S_memory_38000000, __VA_ARGS__) fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__) fn(DT_N_S_sdram_c0000000, __VA_ARGS__) fn(DT_N_S_gpio_deadbeef, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__) +#define DT_N_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_90000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_dietemp, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vbat, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vref, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_24000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30040000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_38000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sdram_c0000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_deadbeef, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_zephyr_user, __VA_ARGS__) +#define DT_N_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_cpus) fn(DT_N_S_memory_90000000) fn(DT_N_S_clocks) fn(DT_N_S_memory_24000000) fn(DT_N_S_memory_30000000) fn(DT_N_S_memory_30020000) fn(DT_N_S_memory_30040000) fn(DT_N_S_memory_38000000) fn(DT_N_S_otghs_fs_phy) fn(DT_N_S_connector) fn(DT_N_S_leds) fn(DT_N_S_gpio_keys) fn(DT_N_S_sdram_c0000000) fn(DT_N_S_gpio_deadbeef) fn(DT_N_S_zephyr_user) +#define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_90000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_24000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30040000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_38000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otghs_fs_phy) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sdram_c0000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_deadbeef) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_zephyr_user) +#define DT_N_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_memory_90000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_memory_24000000, __VA_ARGS__) fn(DT_N_S_memory_30000000, __VA_ARGS__) fn(DT_N_S_memory_30020000, __VA_ARGS__) fn(DT_N_S_memory_30040000, __VA_ARGS__) fn(DT_N_S_memory_38000000, __VA_ARGS__) fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__) fn(DT_N_S_sdram_c0000000, __VA_ARGS__) fn(DT_N_S_gpio_deadbeef, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__) +#define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_90000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_24000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30040000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_38000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sdram_c0000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_deadbeef, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_zephyr_user, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_ORD 0 @@ -313,25 +345,26 @@ 3, /* /connector */ \ 4, /* /soc */ \ 6, /* /clocks */ \ - 11, /* /dietemp */ \ - 12, /* /memory@24000000 */ \ - 13, /* /memory@30000000 */ \ - 14, /* /memory@30020000 */ \ - 15, /* /memory@30040000 */ \ - 16, /* /memory@38000000 */ \ - 17, /* /memory@90000000 */ \ - 18, /* /sdram@c0000000 */ \ - 23, /* /smbus1 */ \ - 27, /* /smbus2 */ \ - 29, /* /smbus3 */ \ - 33, /* /smbus4 */ \ - 34, /* /vbat */ \ - 35, /* /vref */ \ - 71, /* /otghs_fs_phy */ \ - 76, /* /zephyr,user */ \ - 85, /* /cpus */ \ - 88, /* /gpio_keys */ \ - 90, /* /leds */ + 14, /* /dietemp */ \ + 15, /* /memory@24000000 */ \ + 16, /* /memory@30000000 */ \ + 17, /* /memory@30020000 */ \ + 18, /* /memory@30040000 */ \ + 19, /* /memory@38000000 */ \ + 20, /* /memory@90000000 */ \ + 21, /* /sdram@c0000000 */ \ + 25, /* /smbus1 */ \ + 29, /* /smbus2 */ \ + 31, /* /smbus3 */ \ + 35, /* /smbus4 */ \ + 36, /* /vbat */ \ + 37, /* /vref */ \ + 38, /* /gpio@deadbeef */ \ + 82, /* /otghs_fs_phy */ \ + 87, /* /zephyr,user */ \ + 96, /* /cpus */ \ + 99, /* /gpio_keys */ \ + 101, /* /leds */ /* Existence and alternate IDs: */ #define DT_N_EXISTS 1 @@ -605,15 +638,15 @@ /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_CHILD_NUM 71 -#define DT_N_S_soc_CHILD_NUM_STATUS_OKAY 20 +#define DT_N_S_soc_CHILD_NUM_STATUS_OKAY 25 #define DT_N_S_soc_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_flash_controller_52002000) fn(DT_N_S_soc_S_rcc_58024400) fn(DT_N_S_soc_S_interrupt_controller_58000000) fn(DT_N_S_soc_S_pin_controller_58020000) fn(DT_N_S_soc_S_watchdog_58004800) fn(DT_N_S_soc_S_watchdog_50003000) fn(DT_N_S_soc_S_serial_40011000) fn(DT_N_S_soc_S_serial_40004400) fn(DT_N_S_soc_S_serial_40004800) fn(DT_N_S_soc_S_serial_40004c00) fn(DT_N_S_soc_S_serial_40005000) fn(DT_N_S_soc_S_serial_40011400) fn(DT_N_S_soc_S_serial_40007800) fn(DT_N_S_soc_S_serial_40007c00) fn(DT_N_S_soc_S_serial_58000c00) fn(DT_N_S_soc_S_rtc_58004000) fn(DT_N_S_soc_S_i2c_40005400) fn(DT_N_S_soc_S_i2c_40005800) fn(DT_N_S_soc_S_i2c_40005c00) fn(DT_N_S_soc_S_i2c_58001c00) fn(DT_N_S_soc_S_spi_40013000) fn(DT_N_S_soc_S_spi_40003800) fn(DT_N_S_soc_S_spi_40003c00) fn(DT_N_S_soc_S_spi_40013400) fn(DT_N_S_soc_S_spi_40015000) fn(DT_N_S_soc_S_spi_58001400) fn(DT_N_S_soc_S_i2s_40013000) fn(DT_N_S_soc_S_i2s_40003800) fn(DT_N_S_soc_S_i2s_40003c00) fn(DT_N_S_soc_S_can_4000a000) fn(DT_N_S_soc_S_can_4000a400) fn(DT_N_S_soc_S_timers_40010000) fn(DT_N_S_soc_S_timers_40000000) fn(DT_N_S_soc_S_timers_40000400) fn(DT_N_S_soc_S_timers_40000800) fn(DT_N_S_soc_S_timers_40000c00) fn(DT_N_S_soc_S_timers_40001000) fn(DT_N_S_soc_S_timers_40001400) fn(DT_N_S_soc_S_timers_40010400) fn(DT_N_S_soc_S_timers_40001800) fn(DT_N_S_soc_S_timers_40001c00) fn(DT_N_S_soc_S_timers_40002000) fn(DT_N_S_soc_S_timers_40014000) fn(DT_N_S_soc_S_timers_40014400) fn(DT_N_S_soc_S_timers_40014800) fn(DT_N_S_soc_S_timers_40002400) fn(DT_N_S_soc_S_adc_40022000) fn(DT_N_S_soc_S_adc_40022100) fn(DT_N_S_soc_S_adc_40022300) fn(DT_N_S_soc_S_adc_58026000) fn(DT_N_S_soc_S_dac_40007400) fn(DT_N_S_soc_S_dma_40020000) fn(DT_N_S_soc_S_dma_40020400) fn(DT_N_S_soc_S_bdma_58025400) fn(DT_N_S_soc_S_dmamux_40020800) fn(DT_N_S_soc_S_dmamux_58025800) fn(DT_N_S_soc_S_rng_48021800) fn(DT_N_S_soc_S_sdmmc_52007000) fn(DT_N_S_soc_S_sdmmc_48022400) fn(DT_N_S_soc_S_ethernet_40028000) fn(DT_N_S_soc_S_memory_controller_52004000) fn(DT_N_S_soc_S_memory_38800000) fn(DT_N_S_soc_S_quadspi_52005000) fn(DT_N_S_soc_S_dcmi_48020000) fn(DT_N_S_soc_S_mailbox_58026400) fn(DT_N_S_soc_S_display_controller_50001000) fn(DT_N_S_soc_S_usb_40040000) fn(DT_N_S_soc_S_usb_40080000) fn(DT_N_S_soc_S_dsihost_50000000) #define DT_N_S_soc_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_52002000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rcc_58024400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_interrupt_controller_58000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_58004800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_50003000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40011000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40004400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40004800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40004c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40005000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40011400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40007800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40007c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_58000c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rtc_58004000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40005400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40005800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40005c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_58001c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40013000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40003800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40003c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40013400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40015000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_58001400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2s_40013000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2s_40003800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2s_40003c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_can_4000a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_can_4000a400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40010000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40010400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40002000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40002400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022100) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022300) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_58026000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dac_40007400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dma_40020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dma_40020400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_bdma_58025400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dmamux_40020800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dmamux_58025800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rng_48021800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sdmmc_52007000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sdmmc_48022400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ethernet_40028000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_controller_52004000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_38800000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_quadspi_52005000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dcmi_48020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_mailbox_58026400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_display_controller_50001000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_usb_40040000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_usb_40080000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dsihost_50000000) #define DT_N_S_soc_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_58024400, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_58000000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_58004800, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_50003000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004c00, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40005000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007c00, __VA_ARGS__) fn(DT_N_S_soc_S_serial_58000c00, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_58004000, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005400, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005800, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005c00, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003800, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003c00, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013400, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40015000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_58001400, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_40003800, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_40003c00, __VA_ARGS__) fn(DT_N_S_soc_S_can_4000a000, __VA_ARGS__) fn(DT_N_S_soc_S_can_4000a400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000c00, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001800, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001c00, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40002000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014800, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40002400, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022100, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022300, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000, __VA_ARGS__) fn(DT_N_S_soc_S_dac_40007400, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40020400, __VA_ARGS__) fn(DT_N_S_soc_S_bdma_58025400, __VA_ARGS__) fn(DT_N_S_soc_S_dmamux_40020800, __VA_ARGS__) fn(DT_N_S_soc_S_dmamux_58025800, __VA_ARGS__) fn(DT_N_S_soc_S_rng_48021800, __VA_ARGS__) fn(DT_N_S_soc_S_sdmmc_52007000, __VA_ARGS__) fn(DT_N_S_soc_S_sdmmc_48022400, __VA_ARGS__) fn(DT_N_S_soc_S_ethernet_40028000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_38800000, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000, __VA_ARGS__) fn(DT_N_S_soc_S_dcmi_48020000, __VA_ARGS__) fn(DT_N_S_soc_S_mailbox_58026400, __VA_ARGS__) fn(DT_N_S_soc_S_display_controller_50001000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40040000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40080000, __VA_ARGS__) fn(DT_N_S_soc_S_dsihost_50000000, __VA_ARGS__) #define DT_N_S_soc_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_52002000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rcc_58024400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_interrupt_controller_58000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_58004800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_50003000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40011000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40004400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40004800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40004c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40005000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40011400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40007800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40007c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_58000c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rtc_58004000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40005400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40005800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40005c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_58001c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40003800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40003c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40013400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40015000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_58001400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2s_40013000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2s_40003800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2s_40003c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_can_4000a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_can_4000a400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40010000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40010400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40002000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40002400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022100, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022300, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_58026000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dac_40007400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dma_40020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dma_40020400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_bdma_58025400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dmamux_40020800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dmamux_58025800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rng_48021800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sdmmc_52007000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sdmmc_48022400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ethernet_40028000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_controller_52004000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_38800000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_quadspi_52005000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dcmi_48020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_mailbox_58026400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_display_controller_50001000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_usb_40040000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_usb_40080000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dsihost_50000000, __VA_ARGS__) -#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_flash_controller_52002000) fn(DT_N_S_soc_S_rcc_58024400) fn(DT_N_S_soc_S_interrupt_controller_58000000) fn(DT_N_S_soc_S_pin_controller_58020000) fn(DT_N_S_soc_S_serial_40011000) fn(DT_N_S_soc_S_serial_40011400) fn(DT_N_S_soc_S_serial_40007800) fn(DT_N_S_soc_S_i2c_58001c00) fn(DT_N_S_soc_S_spi_40013000) fn(DT_N_S_soc_S_spi_40015000) fn(DT_N_S_soc_S_can_4000a400) fn(DT_N_S_soc_S_adc_40022000) fn(DT_N_S_soc_S_dac_40007400) fn(DT_N_S_soc_S_rng_48021800) fn(DT_N_S_soc_S_memory_controller_52004000) fn(DT_N_S_soc_S_quadspi_52005000) fn(DT_N_S_soc_S_mailbox_58026400) fn(DT_N_S_soc_S_usb_40080000) -#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_52002000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rcc_58024400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_interrupt_controller_58000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40011000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40011400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40007800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_58001c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40013000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40015000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_can_4000a400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dac_40007400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rng_48021800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_controller_52004000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_quadspi_52005000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_mailbox_58026400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_usb_40080000) -#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_58024400, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_58000000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40015000, __VA_ARGS__) fn(DT_N_S_soc_S_can_4000a400, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000, __VA_ARGS__) fn(DT_N_S_soc_S_dac_40007400, __VA_ARGS__) fn(DT_N_S_soc_S_rng_48021800, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000, __VA_ARGS__) fn(DT_N_S_soc_S_mailbox_58026400, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40080000, __VA_ARGS__) -#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_52002000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rcc_58024400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_interrupt_controller_58000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40011000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40011400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40007800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_58001c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40015000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_can_4000a400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dac_40007400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rng_48021800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_controller_52004000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_quadspi_52005000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_mailbox_58026400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_usb_40080000, __VA_ARGS__) +#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_flash_controller_52002000) fn(DT_N_S_soc_S_rcc_58024400) fn(DT_N_S_soc_S_interrupt_controller_58000000) fn(DT_N_S_soc_S_pin_controller_58020000) fn(DT_N_S_soc_S_serial_40011000) fn(DT_N_S_soc_S_serial_40011400) fn(DT_N_S_soc_S_serial_40007800) fn(DT_N_S_soc_S_i2c_58001c00) fn(DT_N_S_soc_S_spi_40013000) fn(DT_N_S_soc_S_spi_40015000) fn(DT_N_S_soc_S_can_4000a400) fn(DT_N_S_soc_S_timers_40010000) fn(DT_N_S_soc_S_adc_40022000) fn(DT_N_S_soc_S_adc_58026000) fn(DT_N_S_soc_S_dac_40007400) fn(DT_N_S_soc_S_dma_40020000) fn(DT_N_S_soc_S_dmamux_40020800) fn(DT_N_S_soc_S_rng_48021800) fn(DT_N_S_soc_S_memory_controller_52004000) fn(DT_N_S_soc_S_quadspi_52005000) fn(DT_N_S_soc_S_dcmi_48020000) fn(DT_N_S_soc_S_mailbox_58026400) fn(DT_N_S_soc_S_usb_40080000) +#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_52002000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rcc_58024400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_interrupt_controller_58000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40011000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40011400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40007800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_58001c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40013000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40015000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_can_4000a400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40010000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_58026000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dac_40007400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dma_40020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dmamux_40020800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rng_48021800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_controller_52004000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_quadspi_52005000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dcmi_48020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_mailbox_58026400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_usb_40080000) +#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_58024400, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_58000000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40015000, __VA_ARGS__) fn(DT_N_S_soc_S_can_4000a400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000, __VA_ARGS__) fn(DT_N_S_soc_S_dac_40007400, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_dmamux_40020800, __VA_ARGS__) fn(DT_N_S_soc_S_rng_48021800, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000, __VA_ARGS__) fn(DT_N_S_soc_S_dcmi_48020000, __VA_ARGS__) fn(DT_N_S_soc_S_mailbox_58026400, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40080000, __VA_ARGS__) +#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_52002000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rcc_58024400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_interrupt_controller_58000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40011000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40011400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40007800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_58001c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40015000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_can_4000a400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40010000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_58026000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dac_40007400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dma_40020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dmamux_40020800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rng_48021800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_controller_52004000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_quadspi_52005000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dcmi_48020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_mailbox_58026400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_usb_40080000, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_S_soc_ORD 4 @@ -627,75 +660,75 @@ #define DT_N_S_soc_SUPPORTS_ORDS \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 10, /* /soc/adc@58026000 */ \ - 19, /* /soc/pin-controller@58020000 */ \ - 22, /* /soc/i2c@40005400 */ \ - 26, /* /soc/i2c@40005800 */ \ - 28, /* /soc/i2c@40005c00 */ \ - 32, /* /soc/i2c@58001c00 */ \ - 44, /* /soc/adc@40022000 */ \ - 48, /* /soc/serial@40011000 */ \ - 51, /* /soc/serial@40011400 */ \ - 56, /* /soc/spi@40013000 */ \ - 61, /* /soc/spi@40015000 */ \ - 74, /* /soc/usb@40080000 */ \ - 94, /* /soc/adc@40022100 */ \ - 95, /* /soc/adc@40022300 */ \ - 96, /* /soc/bdma@58025400 */ \ - 97, /* /soc/can@4000a000 */ \ - 100, /* /soc/can@4000a400 */ \ - 103, /* /soc/dac@40007400 */ \ - 104, /* /soc/dcmi@48020000 */ \ - 105, /* /soc/display-controller@50001000 */ \ - 106, /* /soc/dma@40020000 */ \ - 107, /* /soc/dma@40020400 */ \ - 108, /* /soc/dmamux@58025800 */ \ - 109, /* /soc/dsihost@50000000 */ \ - 110, /* /soc/dmamux@40020800 */ \ - 111, /* /soc/i2s@40003800 */ \ - 112, /* /soc/i2s@40003c00 */ \ - 113, /* /soc/i2s@40013000 */ \ - 114, /* /soc/interrupt-controller@58000000 */ \ - 115, /* /soc/mailbox@58026400 */ \ - 116, /* /soc/memory@38800000 */ \ - 117, /* /soc/rng@48021800 */ \ - 118, /* /soc/sdmmc@48022400 */ \ - 119, /* /soc/sdmmc@52007000 */ \ - 120, /* /soc/serial@40004400 */ \ - 121, /* /soc/serial@40004800 */ \ - 124, /* /soc/serial@40004c00 */ \ - 125, /* /soc/serial@40005000 */ \ - 126, /* /soc/serial@40007c00 */ \ - 127, /* /soc/serial@58000c00 */ \ - 128, /* /soc/spi@40003800 */ \ - 129, /* /soc/spi@40003c00 */ \ - 130, /* /soc/spi@40013400 */ \ - 131, /* /soc/spi@58001400 */ \ - 132, /* /soc/timer@e000e010 */ \ - 133, /* /soc/timers@40002400 */ \ - 134, /* /soc/usb@40040000 */ \ - 135, /* /soc/watchdog@50003000 */ \ - 136, /* /soc/watchdog@58004800 */ \ - 145, /* /soc/ethernet@40028000 */ \ - 147, /* /soc/flash-controller@52002000 */ \ - 191, /* /soc/memory-controller@52004000 */ \ - 201, /* /soc/quadspi@52005000 */ \ - 206, /* /soc/rtc@58004000 */ \ - 213, /* /soc/serial@40007800 */ \ - 216, /* /soc/timers@40000000 */ \ - 219, /* /soc/timers@40000400 */ \ - 222, /* /soc/timers@40000800 */ \ - 225, /* /soc/timers@40000c00 */ \ - 228, /* /soc/timers@40001000 */ \ - 230, /* /soc/timers@40001400 */ \ - 232, /* /soc/timers@40001800 */ \ - 235, /* /soc/timers@40001c00 */ \ - 238, /* /soc/timers@40002000 */ \ - 241, /* /soc/timers@40010000 */ \ - 243, /* /soc/timers@40010400 */ \ - 245, /* /soc/timers@40014000 */ \ - 248, /* /soc/timers@40014400 */ \ - 251, /* /soc/timers@40014800 */ + 10, /* /soc/pin-controller@58020000 */ \ + 13, /* /soc/adc@58026000 */ \ + 24, /* /soc/i2c@40005400 */ \ + 28, /* /soc/i2c@40005800 */ \ + 30, /* /soc/i2c@40005c00 */ \ + 34, /* /soc/i2c@58001c00 */ \ + 51, /* /soc/adc@40022000 */ \ + 55, /* /soc/serial@40011000 */ \ + 58, /* /soc/serial@40011400 */ \ + 63, /* /soc/spi@40013000 */ \ + 68, /* /soc/spi@40015000 */ \ + 79, /* /soc/timers@40010000 */ \ + 85, /* /soc/usb@40080000 */ \ + 105, /* /soc/adc@40022100 */ \ + 106, /* /soc/adc@40022300 */ \ + 107, /* /soc/bdma@58025400 */ \ + 108, /* /soc/can@4000a000 */ \ + 111, /* /soc/can@4000a400 */ \ + 114, /* /soc/dac@40007400 */ \ + 115, /* /soc/display-controller@50001000 */ \ + 116, /* /soc/dma@40020400 */ \ + 117, /* /soc/dmamux@58025800 */ \ + 118, /* /soc/dsihost@50000000 */ \ + 119, /* /soc/dmamux@40020800 */ \ + 120, /* /soc/i2s@40003800 */ \ + 121, /* /soc/i2s@40003c00 */ \ + 122, /* /soc/i2s@40013000 */ \ + 123, /* /soc/interrupt-controller@58000000 */ \ + 124, /* /soc/mailbox@58026400 */ \ + 125, /* /soc/memory@38800000 */ \ + 126, /* /soc/rng@48021800 */ \ + 127, /* /soc/sdmmc@48022400 */ \ + 128, /* /soc/sdmmc@52007000 */ \ + 129, /* /soc/serial@40004400 */ \ + 130, /* /soc/serial@40004800 */ \ + 133, /* /soc/serial@40004c00 */ \ + 134, /* /soc/serial@40005000 */ \ + 135, /* /soc/serial@40007c00 */ \ + 136, /* /soc/serial@58000c00 */ \ + 137, /* /soc/spi@40003800 */ \ + 138, /* /soc/spi@40003c00 */ \ + 139, /* /soc/spi@40013400 */ \ + 140, /* /soc/spi@58001400 */ \ + 141, /* /soc/timer@e000e010 */ \ + 142, /* /soc/timers@40002400 */ \ + 143, /* /soc/usb@40040000 */ \ + 144, /* /soc/watchdog@50003000 */ \ + 145, /* /soc/watchdog@58004800 */ \ + 160, /* /soc/dma@40020000 */ \ + 173, /* /soc/dcmi@48020000 */ \ + 176, /* /soc/ethernet@40028000 */ \ + 178, /* /soc/flash-controller@52002000 */ \ + 225, /* /soc/memory-controller@52004000 */ \ + 235, /* /soc/quadspi@52005000 */ \ + 240, /* /soc/rtc@58004000 */ \ + 246, /* /soc/serial@40007800 */ \ + 249, /* /soc/timers@40000000 */ \ + 252, /* /soc/timers@40000400 */ \ + 255, /* /soc/timers@40000800 */ \ + 258, /* /soc/timers@40000c00 */ \ + 261, /* /soc/timers@40001000 */ \ + 263, /* /soc/timers@40001400 */ \ + 265, /* /soc/timers@40001800 */ \ + 268, /* /soc/timers@40001c00 */ \ + 271, /* /soc/timers@40002000 */ \ + 275, /* /soc/timers@40010400 */ \ + 277, /* /soc/timers@40014000 */ \ + 280, /* /soc/timers@40014400 */ \ + 283, /* /soc/timers@40014800 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_EXISTS 1 @@ -809,68 +842,68 @@ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_SUPPORTS_ORDS \ - 10, /* /soc/adc@58026000 */ \ - 22, /* /soc/i2c@40005400 */ \ - 26, /* /soc/i2c@40005800 */ \ - 28, /* /soc/i2c@40005c00 */ \ - 32, /* /soc/i2c@58001c00 */ \ - 44, /* /soc/adc@40022000 */ \ - 48, /* /soc/serial@40011000 */ \ - 51, /* /soc/serial@40011400 */ \ - 56, /* /soc/spi@40013000 */ \ - 61, /* /soc/spi@40015000 */ \ - 74, /* /soc/usb@40080000 */ \ - 94, /* /soc/adc@40022100 */ \ - 95, /* /soc/adc@40022300 */ \ - 96, /* /soc/bdma@58025400 */ \ - 97, /* /soc/can@4000a000 */ \ - 100, /* /soc/can@4000a400 */ \ - 104, /* /soc/dcmi@48020000 */ \ - 105, /* /soc/display-controller@50001000 */ \ - 106, /* /soc/dma@40020000 */ \ - 107, /* /soc/dma@40020400 */ \ - 108, /* /soc/dmamux@58025800 */ \ - 110, /* /soc/dmamux@40020800 */ \ - 111, /* /soc/i2s@40003800 */ \ - 112, /* /soc/i2s@40003c00 */ \ - 113, /* /soc/i2s@40013000 */ \ - 114, /* /soc/interrupt-controller@58000000 */ \ - 115, /* /soc/mailbox@58026400 */ \ - 117, /* /soc/rng@48021800 */ \ - 118, /* /soc/sdmmc@48022400 */ \ - 119, /* /soc/sdmmc@52007000 */ \ - 120, /* /soc/serial@40004400 */ \ - 121, /* /soc/serial@40004800 */ \ - 124, /* /soc/serial@40004c00 */ \ - 125, /* /soc/serial@40005000 */ \ - 126, /* /soc/serial@40007c00 */ \ - 127, /* /soc/serial@58000c00 */ \ - 128, /* /soc/spi@40003800 */ \ - 129, /* /soc/spi@40003c00 */ \ - 130, /* /soc/spi@40013400 */ \ - 131, /* /soc/spi@58001400 */ \ - 133, /* /soc/timers@40002400 */ \ - 134, /* /soc/usb@40040000 */ \ - 135, /* /soc/watchdog@50003000 */ \ - 145, /* /soc/ethernet@40028000 */ \ - 147, /* /soc/flash-controller@52002000 */ \ - 201, /* /soc/quadspi@52005000 */ \ - 206, /* /soc/rtc@58004000 */ \ - 213, /* /soc/serial@40007800 */ \ - 216, /* /soc/timers@40000000 */ \ - 219, /* /soc/timers@40000400 */ \ - 222, /* /soc/timers@40000800 */ \ - 225, /* /soc/timers@40000c00 */ \ - 228, /* /soc/timers@40001000 */ \ - 230, /* /soc/timers@40001400 */ \ - 232, /* /soc/timers@40001800 */ \ - 235, /* /soc/timers@40001c00 */ \ - 238, /* /soc/timers@40002000 */ \ - 241, /* /soc/timers@40010000 */ \ - 243, /* /soc/timers@40010400 */ \ - 245, /* /soc/timers@40014000 */ \ - 248, /* /soc/timers@40014400 */ \ - 251, /* /soc/timers@40014800 */ + 13, /* /soc/adc@58026000 */ \ + 24, /* /soc/i2c@40005400 */ \ + 28, /* /soc/i2c@40005800 */ \ + 30, /* /soc/i2c@40005c00 */ \ + 34, /* /soc/i2c@58001c00 */ \ + 51, /* /soc/adc@40022000 */ \ + 55, /* /soc/serial@40011000 */ \ + 58, /* /soc/serial@40011400 */ \ + 63, /* /soc/spi@40013000 */ \ + 68, /* /soc/spi@40015000 */ \ + 79, /* /soc/timers@40010000 */ \ + 85, /* /soc/usb@40080000 */ \ + 105, /* /soc/adc@40022100 */ \ + 106, /* /soc/adc@40022300 */ \ + 107, /* /soc/bdma@58025400 */ \ + 108, /* /soc/can@4000a000 */ \ + 111, /* /soc/can@4000a400 */ \ + 115, /* /soc/display-controller@50001000 */ \ + 116, /* /soc/dma@40020400 */ \ + 117, /* /soc/dmamux@58025800 */ \ + 119, /* /soc/dmamux@40020800 */ \ + 120, /* /soc/i2s@40003800 */ \ + 121, /* /soc/i2s@40003c00 */ \ + 122, /* /soc/i2s@40013000 */ \ + 123, /* /soc/interrupt-controller@58000000 */ \ + 124, /* /soc/mailbox@58026400 */ \ + 126, /* /soc/rng@48021800 */ \ + 127, /* /soc/sdmmc@48022400 */ \ + 128, /* /soc/sdmmc@52007000 */ \ + 129, /* /soc/serial@40004400 */ \ + 130, /* /soc/serial@40004800 */ \ + 133, /* /soc/serial@40004c00 */ \ + 134, /* /soc/serial@40005000 */ \ + 135, /* /soc/serial@40007c00 */ \ + 136, /* /soc/serial@58000c00 */ \ + 137, /* /soc/spi@40003800 */ \ + 138, /* /soc/spi@40003c00 */ \ + 139, /* /soc/spi@40013400 */ \ + 140, /* /soc/spi@58001400 */ \ + 142, /* /soc/timers@40002400 */ \ + 143, /* /soc/usb@40040000 */ \ + 144, /* /soc/watchdog@50003000 */ \ + 160, /* /soc/dma@40020000 */ \ + 173, /* /soc/dcmi@48020000 */ \ + 176, /* /soc/ethernet@40028000 */ \ + 178, /* /soc/flash-controller@52002000 */ \ + 235, /* /soc/quadspi@52005000 */ \ + 240, /* /soc/rtc@58004000 */ \ + 246, /* /soc/serial@40007800 */ \ + 249, /* /soc/timers@40000000 */ \ + 252, /* /soc/timers@40000400 */ \ + 255, /* /soc/timers@40000800 */ \ + 258, /* /soc/timers@40000c00 */ \ + 261, /* /soc/timers@40001000 */ \ + 263, /* /soc/timers@40001400 */ \ + 265, /* /soc/timers@40001800 */ \ + 268, /* /soc/timers@40001c00 */ \ + 271, /* /soc/timers@40002000 */ \ + 275, /* /soc/timers@40010400 */ \ + 277, /* /soc/timers@40014000 */ \ + 280, /* /soc/timers@40014400 */ \ + 283, /* /soc/timers@40014800 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_EXISTS 1 @@ -973,14 +1006,14 @@ #define DT_N_S_clocks_SUPPORTS_ORDS \ 7, /* /clocks/clk-hse */ \ 8, /* /clocks/pll@0 */ \ - 77, /* /clocks/clk-csi */ \ - 78, /* /clocks/clk-hsi */ \ - 79, /* /clocks/clk-hsi48 */ \ - 80, /* /clocks/clk-lse */ \ - 81, /* /clocks/clk-lsi */ \ - 82, /* /clocks/perck */ \ - 83, /* /clocks/pll@1 */ \ - 84, /* /clocks/pll@2 */ + 88, /* /clocks/clk-csi */ \ + 89, /* /clocks/clk-hsi */ \ + 90, /* /clocks/clk-hsi48 */ \ + 91, /* /clocks/clk-lse */ \ + 92, /* /clocks/clk-lsi */ \ + 93, /* /clocks/perck */ \ + 94, /* /clocks/pll@1 */ \ + 95, /* /clocks/pll@2 */ /* Existence and alternate IDs: */ #define DT_N_S_clocks_EXISTS 1 @@ -1267,83 +1300,83 @@ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_rcc_58024400_SUPPORTS_ORDS \ - 10, /* /soc/adc@58026000 */ \ - 22, /* /soc/i2c@40005400 */ \ - 26, /* /soc/i2c@40005800 */ \ - 28, /* /soc/i2c@40005c00 */ \ - 32, /* /soc/i2c@58001c00 */ \ - 44, /* /soc/adc@40022000 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ \ - 48, /* /soc/serial@40011000 */ \ - 51, /* /soc/serial@40011400 */ \ - 56, /* /soc/spi@40013000 */ \ - 61, /* /soc/spi@40015000 */ \ - 62, /* /soc/pin-controller@58020000/gpio@58020000 */ \ - 63, /* /soc/pin-controller@58020000/gpio@58020400 */ \ - 64, /* /soc/pin-controller@58020000/gpio@58020800 */ \ - 65, /* /soc/pin-controller@58020000/gpio@58020C00 */ \ - 66, /* /soc/pin-controller@58020000/gpio@58021000 */ \ - 67, /* /soc/pin-controller@58020000/gpio@58021C00 */ \ - 68, /* /soc/pin-controller@58020000/gpio@58022000 */ \ - 69, /* /soc/pin-controller@58020000/gpio@58022400 */ \ - 70, /* /soc/pin-controller@58020000/gpio@58022800 */ \ - 74, /* /soc/usb@40080000 */ \ - 94, /* /soc/adc@40022100 */ \ - 95, /* /soc/adc@40022300 */ \ - 96, /* /soc/bdma@58025400 */ \ - 97, /* /soc/can@4000a000 */ \ - 100, /* /soc/can@4000a400 */ \ - 103, /* /soc/dac@40007400 */ \ - 104, /* /soc/dcmi@48020000 */ \ - 105, /* /soc/display-controller@50001000 */ \ - 106, /* /soc/dma@40020000 */ \ - 107, /* /soc/dma@40020400 */ \ - 108, /* /soc/dmamux@58025800 */ \ - 109, /* /soc/dsihost@50000000 */ \ - 110, /* /soc/dmamux@40020800 */ \ - 111, /* /soc/i2s@40003800 */ \ - 112, /* /soc/i2s@40003c00 */ \ - 113, /* /soc/i2s@40013000 */ \ - 115, /* /soc/mailbox@58026400 */ \ - 116, /* /soc/memory@38800000 */ \ - 117, /* /soc/rng@48021800 */ \ - 118, /* /soc/sdmmc@48022400 */ \ - 119, /* /soc/sdmmc@52007000 */ \ - 120, /* /soc/serial@40004400 */ \ - 121, /* /soc/serial@40004800 */ \ - 124, /* /soc/serial@40004c00 */ \ - 125, /* /soc/serial@40005000 */ \ - 126, /* /soc/serial@40007c00 */ \ - 127, /* /soc/serial@58000c00 */ \ - 128, /* /soc/spi@40003800 */ \ - 129, /* /soc/spi@40003c00 */ \ - 130, /* /soc/spi@40013400 */ \ - 131, /* /soc/spi@58001400 */ \ - 133, /* /soc/timers@40002400 */ \ - 134, /* /soc/usb@40040000 */ \ - 135, /* /soc/watchdog@50003000 */ \ - 145, /* /soc/ethernet@40028000 */ \ - 147, /* /soc/flash-controller@52002000 */ \ - 191, /* /soc/memory-controller@52004000 */ \ - 194, /* /soc/pin-controller@58020000/gpio@58021400 */ \ - 201, /* /soc/quadspi@52005000 */ \ - 206, /* /soc/rtc@58004000 */ \ - 208, /* /soc/pin-controller@58020000/gpio@58021800 */ \ - 213, /* /soc/serial@40007800 */ \ - 216, /* /soc/timers@40000000 */ \ - 219, /* /soc/timers@40000400 */ \ - 222, /* /soc/timers@40000800 */ \ - 225, /* /soc/timers@40000c00 */ \ - 228, /* /soc/timers@40001000 */ \ - 230, /* /soc/timers@40001400 */ \ - 232, /* /soc/timers@40001800 */ \ - 235, /* /soc/timers@40001c00 */ \ - 238, /* /soc/timers@40002000 */ \ - 241, /* /soc/timers@40010000 */ \ - 243, /* /soc/timers@40010400 */ \ - 245, /* /soc/timers@40014000 */ \ - 248, /* /soc/timers@40014400 */ \ - 251, /* /soc/timers@40014800 */ + 13, /* /soc/adc@58026000 */ \ + 24, /* /soc/i2c@40005400 */ \ + 28, /* /soc/i2c@40005800 */ \ + 30, /* /soc/i2c@40005c00 */ \ + 34, /* /soc/i2c@58001c00 */ \ + 51, /* /soc/adc@40022000 */ \ + 54, /* /soc/rcc@58024400/reset-controller */ \ + 55, /* /soc/serial@40011000 */ \ + 58, /* /soc/serial@40011400 */ \ + 63, /* /soc/spi@40013000 */ \ + 68, /* /soc/spi@40015000 */ \ + 69, /* /soc/pin-controller@58020000/gpio@58020000 */ \ + 70, /* /soc/pin-controller@58020000/gpio@58020400 */ \ + 71, /* /soc/pin-controller@58020000/gpio@58020800 */ \ + 72, /* /soc/pin-controller@58020000/gpio@58020C00 */ \ + 73, /* /soc/pin-controller@58020000/gpio@58021000 */ \ + 74, /* /soc/pin-controller@58020000/gpio@58021800 */ \ + 75, /* /soc/pin-controller@58020000/gpio@58021C00 */ \ + 76, /* /soc/pin-controller@58020000/gpio@58022000 */ \ + 77, /* /soc/pin-controller@58020000/gpio@58022400 */ \ + 78, /* /soc/pin-controller@58020000/gpio@58022800 */ \ + 79, /* /soc/timers@40010000 */ \ + 85, /* /soc/usb@40080000 */ \ + 105, /* /soc/adc@40022100 */ \ + 106, /* /soc/adc@40022300 */ \ + 107, /* /soc/bdma@58025400 */ \ + 108, /* /soc/can@4000a000 */ \ + 111, /* /soc/can@4000a400 */ \ + 114, /* /soc/dac@40007400 */ \ + 115, /* /soc/display-controller@50001000 */ \ + 116, /* /soc/dma@40020400 */ \ + 117, /* /soc/dmamux@58025800 */ \ + 118, /* /soc/dsihost@50000000 */ \ + 119, /* /soc/dmamux@40020800 */ \ + 120, /* /soc/i2s@40003800 */ \ + 121, /* /soc/i2s@40003c00 */ \ + 122, /* /soc/i2s@40013000 */ \ + 124, /* /soc/mailbox@58026400 */ \ + 125, /* /soc/memory@38800000 */ \ + 126, /* /soc/rng@48021800 */ \ + 127, /* /soc/sdmmc@48022400 */ \ + 128, /* /soc/sdmmc@52007000 */ \ + 129, /* /soc/serial@40004400 */ \ + 130, /* /soc/serial@40004800 */ \ + 133, /* /soc/serial@40004c00 */ \ + 134, /* /soc/serial@40005000 */ \ + 135, /* /soc/serial@40007c00 */ \ + 136, /* /soc/serial@58000c00 */ \ + 137, /* /soc/spi@40003800 */ \ + 138, /* /soc/spi@40003c00 */ \ + 139, /* /soc/spi@40013400 */ \ + 140, /* /soc/spi@58001400 */ \ + 142, /* /soc/timers@40002400 */ \ + 143, /* /soc/usb@40040000 */ \ + 144, /* /soc/watchdog@50003000 */ \ + 160, /* /soc/dma@40020000 */ \ + 173, /* /soc/dcmi@48020000 */ \ + 176, /* /soc/ethernet@40028000 */ \ + 178, /* /soc/flash-controller@52002000 */ \ + 225, /* /soc/memory-controller@52004000 */ \ + 228, /* /soc/pin-controller@58020000/gpio@58021400 */ \ + 235, /* /soc/quadspi@52005000 */ \ + 240, /* /soc/rtc@58004000 */ \ + 246, /* /soc/serial@40007800 */ \ + 249, /* /soc/timers@40000000 */ \ + 252, /* /soc/timers@40000400 */ \ + 255, /* /soc/timers@40000800 */ \ + 258, /* /soc/timers@40000c00 */ \ + 261, /* /soc/timers@40001000 */ \ + 263, /* /soc/timers@40001400 */ \ + 265, /* /soc/timers@40001800 */ \ + 268, /* /soc/timers@40001c00 */ \ + 271, /* /soc/timers@40002000 */ \ + 275, /* /soc/timers@40010400 */ \ + 277, /* /soc/timers@40014000 */ \ + 280, /* /soc/timers@40014400 */ \ + 283, /* /soc/timers@40014800 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_rcc_58024400_EXISTS 1 @@ -1429,6 +1462,424 @@ #define DT_N_S_soc_S_rcc_58024400_P_d3ppre_ENUM_VAL_2_EXISTS 1 #define DT_N_S_soc_S_rcc_58024400_P_d3ppre_EXISTS 1 +/* + * Devicetree node: /soc/pin-controller@58020000 + * + * Node identifier: DT_N_S_soc_S_pin_controller_58020000 + * + * Binding (compatible = st,stm32-pinctrl): + * $ZEPHYR_BASE/dts/bindings/pinctrl/st,stm32-pinctrl.yaml + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_pin_controller_58020000_PATH "/soc/pin-controller@58020000" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_pin_controller_58020000_FULL_NAME "pin-controller@58020000" + +/* Node parent (/soc) identifier: */ +#define DT_N_S_soc_S_pin_controller_58020000_PARENT DT_N_S_soc + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_pin_controller_58020000_CHILD_IDX 5 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_pin_controller_58020000_NODELABEL_NUM 1 +#define DT_N_S_soc_S_pin_controller_58020000_FOREACH_NODELABEL(fn) fn(pinctrl) +#define DT_N_S_soc_S_pin_controller_58020000_FOREACH_NODELABEL_VARGS(fn, ...) fn(pinctrl, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_pin_controller_58020000_CHILD_NUM 112 +#define DT_N_S_soc_S_pin_controller_58020000_CHILD_NUM_STATUS_OKAY 112 +#define DT_N_S_soc_S_pin_controller_58020000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12) +#define DT_N_S_soc_S_pin_controller_58020000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12) +#define DT_N_S_soc_S_pin_controller_58020000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12) +#define DT_N_S_soc_S_pin_controller_58020000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12) +#define DT_N_S_soc_S_pin_controller_58020000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12, __VA_ARGS__) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_pin_controller_58020000_ORD 10 +#define DT_N_S_soc_S_pin_controller_58020000_ORD_STR_SORTABLE 00010 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_pin_controller_58020000_REQUIRES_ORDS \ + 4, /* /soc */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_pin_controller_58020000_SUPPORTS_ORDS \ + 11, /* /soc/pin-controller@58020000/adc3_inp0_pc2_c */ \ + 12, /* /soc/pin-controller@58020000/adc3_inp1_pc3_c */ \ + 22, /* /soc/pin-controller@58020000/i2c1_scl_pb8 */ \ + 23, /* /soc/pin-controller@58020000/i2c1_sda_pb9 */ \ + 26, /* /soc/pin-controller@58020000/i2c2_scl_ph4 */ \ + 27, /* /soc/pin-controller@58020000/i2c2_sda_pb11 */ \ + 32, /* /soc/pin-controller@58020000/i2c4_scl_pb6 */ \ + 33, /* /soc/pin-controller@58020000/i2c4_sda_ph12 */ \ + 39, /* /soc/pin-controller@58020000/adc1_inp0_pa0_c */ \ + 40, /* /soc/pin-controller@58020000/adc1_inp10_pc0 */ \ + 41, /* /soc/pin-controller@58020000/adc1_inp12_pc2 */ \ + 42, /* /soc/pin-controller@58020000/adc1_inp13_pc3 */ \ + 43, /* /soc/pin-controller@58020000/adc1_inp16_pa0 */ \ + 44, /* /soc/pin-controller@58020000/adc1_inp18_pa4 */ \ + 45, /* /soc/pin-controller@58020000/adc1_inp19_pa5 */ \ + 46, /* /soc/pin-controller@58020000/adc1_inp1_pa1_c */ \ + 47, /* /soc/pin-controller@58020000/adc1_inp4_pc4 */ \ + 48, /* /soc/pin-controller@58020000/adc1_inp5_pb1 */ \ + 49, /* /soc/pin-controller@58020000/adc1_inp8_pc5 */ \ + 50, /* /soc/pin-controller@58020000/adc1_inp9_pb0 */ \ + 52, /* /soc/pin-controller@58020000/usart1_rx_pb7 */ \ + 53, /* /soc/pin-controller@58020000/usart1_tx_pa9 */ \ + 56, /* /soc/pin-controller@58020000/usart6_rx_pc7 */ \ + 57, /* /soc/pin-controller@58020000/usart6_tx_pg14 */ \ + 59, /* /soc/pin-controller@58020000/spi1_miso_pg9 */ \ + 60, /* /soc/pin-controller@58020000/spi1_mosi_pd7 */ \ + 61, /* /soc/pin-controller@58020000/spi1_nss_pa4 */ \ + 62, /* /soc/pin-controller@58020000/spi1_sck_pb3 */ \ + 64, /* /soc/pin-controller@58020000/spi5_miso_pj11 */ \ + 65, /* /soc/pin-controller@58020000/spi5_mosi_pj10 */ \ + 66, /* /soc/pin-controller@58020000/spi5_nss_pk1 */ \ + 67, /* /soc/pin-controller@58020000/spi5_sck_ph6 */ \ + 69, /* /soc/pin-controller@58020000/gpio@58020000 */ \ + 70, /* /soc/pin-controller@58020000/gpio@58020400 */ \ + 71, /* /soc/pin-controller@58020000/gpio@58020800 */ \ + 72, /* /soc/pin-controller@58020000/gpio@58020C00 */ \ + 73, /* /soc/pin-controller@58020000/gpio@58021000 */ \ + 74, /* /soc/pin-controller@58020000/gpio@58021800 */ \ + 75, /* /soc/pin-controller@58020000/gpio@58021C00 */ \ + 76, /* /soc/pin-controller@58020000/gpio@58022000 */ \ + 77, /* /soc/pin-controller@58020000/gpio@58022400 */ \ + 78, /* /soc/pin-controller@58020000/gpio@58022800 */ \ + 80, /* /soc/pin-controller@58020000/tim1_ch3_pj9 */ \ + 83, /* /soc/pin-controller@58020000/usb_otg_fs_dm_pa11 */ \ + 84, /* /soc/pin-controller@58020000/usb_otg_fs_dp_pa12 */ \ + 109, /* /soc/pin-controller@58020000/fdcan2_rx_pb5 */ \ + 110, /* /soc/pin-controller@58020000/fdcan2_tx_pb13 */ \ + 112, /* /soc/pin-controller@58020000/dac1_out1_pa4 */ \ + 113, /* /soc/pin-controller@58020000/dac1_out2_pa5 */ \ + 131, /* /soc/pin-controller@58020000/uart4_rx_pi9 */ \ + 132, /* /soc/pin-controller@58020000/uart4_tx_ph13 */ \ + 162, /* /soc/pin-controller@58020000/dcmi_d0_ph9 */ \ + 163, /* /soc/pin-controller@58020000/dcmi_d1_ph10 */ \ + 164, /* /soc/pin-controller@58020000/dcmi_d2_ph11 */ \ + 165, /* /soc/pin-controller@58020000/dcmi_d3_pg11 */ \ + 166, /* /soc/pin-controller@58020000/dcmi_d4_ph14 */ \ + 167, /* /soc/pin-controller@58020000/dcmi_d5_pi4 */ \ + 168, /* /soc/pin-controller@58020000/dcmi_d6_pi6 */ \ + 169, /* /soc/pin-controller@58020000/dcmi_d7_pi7 */ \ + 170, /* /soc/pin-controller@58020000/dcmi_hsync_ph8 */ \ + 171, /* /soc/pin-controller@58020000/dcmi_pixclk_pa6 */ \ + 172, /* /soc/pin-controller@58020000/dcmi_vsync_pi5 */ \ + 186, /* /soc/pin-controller@58020000/fmc_a0_pf0 */ \ + 187, /* /soc/pin-controller@58020000/fmc_a10_pg0 */ \ + 188, /* /soc/pin-controller@58020000/fmc_a11_pg1 */ \ + 189, /* /soc/pin-controller@58020000/fmc_a12_pg2 */ \ + 190, /* /soc/pin-controller@58020000/fmc_a14_pg4 */ \ + 191, /* /soc/pin-controller@58020000/fmc_a15_pg5 */ \ + 192, /* /soc/pin-controller@58020000/fmc_a1_pf1 */ \ + 193, /* /soc/pin-controller@58020000/fmc_a2_pf2 */ \ + 194, /* /soc/pin-controller@58020000/fmc_a3_pf3 */ \ + 195, /* /soc/pin-controller@58020000/fmc_a4_pf4 */ \ + 196, /* /soc/pin-controller@58020000/fmc_a5_pf5 */ \ + 197, /* /soc/pin-controller@58020000/fmc_a6_pf12 */ \ + 198, /* /soc/pin-controller@58020000/fmc_a7_pf13 */ \ + 199, /* /soc/pin-controller@58020000/fmc_a8_pf14 */ \ + 200, /* /soc/pin-controller@58020000/fmc_a9_pf15 */ \ + 201, /* /soc/pin-controller@58020000/fmc_d0_pd14 */ \ + 202, /* /soc/pin-controller@58020000/fmc_d10_pe13 */ \ + 203, /* /soc/pin-controller@58020000/fmc_d11_pe14 */ \ + 204, /* /soc/pin-controller@58020000/fmc_d12_pe15 */ \ + 205, /* /soc/pin-controller@58020000/fmc_d13_pd8 */ \ + 206, /* /soc/pin-controller@58020000/fmc_d14_pd9 */ \ + 207, /* /soc/pin-controller@58020000/fmc_d15_pd10 */ \ + 208, /* /soc/pin-controller@58020000/fmc_d1_pd15 */ \ + 209, /* /soc/pin-controller@58020000/fmc_d2_pd0 */ \ + 210, /* /soc/pin-controller@58020000/fmc_d3_pd1 */ \ + 211, /* /soc/pin-controller@58020000/fmc_d4_pe7 */ \ + 212, /* /soc/pin-controller@58020000/fmc_d5_pe8 */ \ + 213, /* /soc/pin-controller@58020000/fmc_d6_pe9 */ \ + 214, /* /soc/pin-controller@58020000/fmc_d7_pe10 */ \ + 215, /* /soc/pin-controller@58020000/fmc_d8_pe11 */ \ + 216, /* /soc/pin-controller@58020000/fmc_d9_pe12 */ \ + 217, /* /soc/pin-controller@58020000/fmc_nbl0_pe0 */ \ + 218, /* /soc/pin-controller@58020000/fmc_nbl1_pe1 */ \ + 219, /* /soc/pin-controller@58020000/fmc_sdcke0_ph2 */ \ + 220, /* /soc/pin-controller@58020000/fmc_sdclk_pg8 */ \ + 221, /* /soc/pin-controller@58020000/fmc_sdncas_pg15 */ \ + 222, /* /soc/pin-controller@58020000/fmc_sdne0_ph3 */ \ + 223, /* /soc/pin-controller@58020000/fmc_sdnras_pf11 */ \ + 224, /* /soc/pin-controller@58020000/fmc_sdnwe_ph5 */ \ + 228, /* /soc/pin-controller@58020000/gpio@58021400 */ \ + 229, /* /soc/pin-controller@58020000/quadspi_bk1_io0_pd11 */ \ + 230, /* /soc/pin-controller@58020000/quadspi_bk1_io1_pd12 */ \ + 231, /* /soc/pin-controller@58020000/quadspi_bk1_io2_pe2 */ \ + 232, /* /soc/pin-controller@58020000/quadspi_bk1_io3_pf6 */ \ + 233, /* /soc/pin-controller@58020000/quadspi_bk1_ncs_pg6 */ \ + 234, /* /soc/pin-controller@58020000/quadspi_clk_pf10 */ \ + 242, /* /soc/pin-controller@58020000/uart7_cts_pf9 */ \ + 243, /* /soc/pin-controller@58020000/uart7_rts_pf8 */ \ + 244, /* /soc/pin-controller@58020000/uart7_rx_pa8 */ \ + 245, /* /soc/pin-controller@58020000/uart7_tx_pf7 */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_pin_controller_58020000_EXISTS 1 +#define DT_N_INST_0_st_stm32_pinctrl DT_N_S_soc_S_pin_controller_58020000 +#define DT_N_NODELABEL_pinctrl DT_N_S_soc_S_pin_controller_58020000 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_pin_controller_58020000_REG_NUM 1 +#define DT_N_S_soc_S_pin_controller_58020000_REG_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_REG_IDX_0_VAL_ADDRESS 1476526080 /* 0x58020000 */ +#define DT_N_S_soc_S_pin_controller_58020000_REG_IDX_0_VAL_SIZE 9216 /* 0x2400 */ +#define DT_N_S_soc_S_pin_controller_58020000_RANGES_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_pin_controller_58020000_IRQ_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_IRQ_LEVEL 0 +#define DT_N_S_soc_S_pin_controller_58020000_COMPAT_MATCHES_st_stm32_pinctrl 1 +#define DT_N_S_soc_S_pin_controller_58020000_COMPAT_VENDOR_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_COMPAT_VENDOR_IDX_0 "STMicroelectronics" +#define DT_N_S_soc_S_pin_controller_58020000_COMPAT_MODEL_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_COMPAT_MODEL_IDX_0 "stm32-pinctrl" +#define DT_N_S_soc_S_pin_controller_58020000_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_pin_controller_58020000_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_pin_controller_58020000_P_wakeup_source 0 +#define DT_N_S_soc_S_pin_controller_58020000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_pin_controller_58020000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_P_compatible {"st,stm32-pinctrl"} +#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_IDX_0 "st,stm32-pinctrl" +#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pinctrl +#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_IDX_0_STRING_TOKEN st_stm32_pinctrl +#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PINCTRL +#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_P_reg {1476526080 /* 0x58020000 */, 9216 /* 0x2400 */} +#define DT_N_S_soc_S_pin_controller_58020000_P_reg_IDX_0 1476526080 +#define DT_N_S_soc_S_pin_controller_58020000_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_P_reg_IDX_1 9216 +#define DT_N_S_soc_S_pin_controller_58020000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_P_reg_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_pin_controller_58020000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa11 0 +#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa11_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa12 0 +#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa12_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa11_pa12 0 +#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa11_pa12_EXISTS 1 + +/* + * Devicetree node: /soc/pin-controller@58020000/adc3_inp0_pc2_c + * + * Node identifier: DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_PATH "/soc/pin-controller@58020000/adc3_inp0_pc2_c" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_FULL_NAME "adc3_inp0_pc2_c" + +/* Node parent (/soc/pin-controller@58020000) identifier: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_PARENT DT_N_S_soc_S_pin_controller_58020000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_CHILD_IDX 23 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_NODELABEL_NUM 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_FOREACH_NODELABEL(fn) fn(adc3_inp0_pc2_c) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_FOREACH_NODELABEL_VARGS(fn, ...) fn(adc3_inp0_pc2_c, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_CHILD_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_ORD 11 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_ORD_STR_SORTABLE 00011 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_REQUIRES_ORDS \ + 10, /* /soc/pin-controller@58020000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_SUPPORTS_ORDS \ + 13, /* /soc/adc@58026000 */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_EXISTS 1 +#define DT_N_NODELABEL_adc3_inp0_pc2_c DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_REG_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_RANGES_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_IRQ_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_IRQ_LEVEL 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_output_high_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_pinmux 1104 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_pinmux_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate "low-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_STRING_UNQUOTED low-speed +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_STRING_TOKEN low_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_IDX_0 "low-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_ENUM_TOKEN low_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_EXISTS 1 + +/* + * Devicetree node: /soc/pin-controller@58020000/adc3_inp1_pc3_c + * + * Node identifier: DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_PATH "/soc/pin-controller@58020000/adc3_inp1_pc3_c" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_FULL_NAME "adc3_inp1_pc3_c" + +/* Node parent (/soc/pin-controller@58020000) identifier: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_PARENT DT_N_S_soc_S_pin_controller_58020000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_CHILD_IDX 24 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_NODELABEL_NUM 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_FOREACH_NODELABEL(fn) fn(adc3_inp1_pc3_c) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_FOREACH_NODELABEL_VARGS(fn, ...) fn(adc3_inp1_pc3_c, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_CHILD_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_ORD 12 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_ORD_STR_SORTABLE 00012 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_REQUIRES_ORDS \ + 10, /* /soc/pin-controller@58020000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_SUPPORTS_ORDS \ + 13, /* /soc/adc@58026000 */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_EXISTS 1 +#define DT_N_NODELABEL_adc3_inp1_pc3_c DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_REG_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_RANGES_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_IRQ_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_IRQ_LEVEL 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_output_high_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_pinmux 1136 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_pinmux_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate "low-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_STRING_UNQUOTED low-speed +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_STRING_TOKEN low_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_IDX_0 "low-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_ENUM_TOKEN low_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_EXISTS 1 + /* * Devicetree node: /soc/adc@58026000 * @@ -1459,36 +1910,41 @@ #define DT_N_S_soc_S_adc_58026000_FOREACH_NODELABEL_VARGS(fn, ...) fn(adc3, __VA_ARGS__) /* Helper macros for child nodes of this node. */ -#define DT_N_S_soc_S_adc_58026000_CHILD_NUM 0 -#define DT_N_S_soc_S_adc_58026000_CHILD_NUM_STATUS_OKAY 0 -#define DT_N_S_soc_S_adc_58026000_FOREACH_CHILD(fn) -#define DT_N_S_soc_S_adc_58026000_FOREACH_CHILD_SEP(fn, sep) -#define DT_N_S_soc_S_adc_58026000_FOREACH_CHILD_VARGS(fn, ...) -#define DT_N_S_soc_S_adc_58026000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) -#define DT_N_S_soc_S_adc_58026000_FOREACH_CHILD_STATUS_OKAY(fn) -#define DT_N_S_soc_S_adc_58026000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) -#define DT_N_S_soc_S_adc_58026000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) -#define DT_N_S_soc_S_adc_58026000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_adc_58026000_CHILD_NUM 2 +#define DT_N_S_soc_S_adc_58026000_CHILD_NUM_STATUS_OKAY 2 +#define DT_N_S_soc_S_adc_58026000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_adc_58026000_S_channel_0) fn(DT_N_S_soc_S_adc_58026000_S_channel_1) +#define DT_N_S_soc_S_adc_58026000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_adc_58026000_S_channel_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_58026000_S_channel_1) +#define DT_N_S_soc_S_adc_58026000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000_S_channel_1, __VA_ARGS__) +#define DT_N_S_soc_S_adc_58026000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_58026000_S_channel_1, __VA_ARGS__) +#define DT_N_S_soc_S_adc_58026000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_adc_58026000_S_channel_0) fn(DT_N_S_soc_S_adc_58026000_S_channel_1) +#define DT_N_S_soc_S_adc_58026000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_adc_58026000_S_channel_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_58026000_S_channel_1) +#define DT_N_S_soc_S_adc_58026000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000_S_channel_1, __VA_ARGS__) +#define DT_N_S_soc_S_adc_58026000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_58026000_S_channel_1, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_58026000_ORD 10 -#define DT_N_S_soc_S_adc_58026000_ORD_STR_SORTABLE 00010 +#define DT_N_S_soc_S_adc_58026000_ORD 13 +#define DT_N_S_soc_S_adc_58026000_ORD_STR_SORTABLE 00013 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_58026000_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ + 9, /* /soc/rcc@58024400 */ \ + 11, /* /soc/pin-controller@58020000/adc3_inp0_pc2_c */ \ + 12, /* /soc/pin-controller@58020000/adc3_inp1_pc3_c */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_58026000_SUPPORTS_ORDS \ - 11, /* /dietemp */ \ - 34, /* /vbat */ \ - 35, /* /vref */ + 14, /* /dietemp */ \ + 36, /* /vbat */ \ + 37, /* /vref */ \ + 87, /* /zephyr,user */ \ + 158, /* /soc/adc@58026000/channel@0 */ \ + 159, /* /soc/adc@58026000/channel@1 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_adc_58026000_EXISTS 1 -#define DT_N_INST_3_st_stm32_adc DT_N_S_soc_S_adc_58026000 +#define DT_N_INST_1_st_stm32_adc DT_N_S_soc_S_adc_58026000 #define DT_N_NODELABEL_adc3 DT_N_S_soc_S_adc_58026000 /* Macros for properties that are special in the specification: */ @@ -1512,26 +1968,33 @@ #define DT_N_S_soc_S_adc_58026000_COMPAT_VENDOR_IDX_0 "STMicroelectronics" #define DT_N_S_soc_S_adc_58026000_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_adc_58026000_COMPAT_MODEL_IDX_0 "stm32-adc" -#define DT_N_S_soc_S_adc_58026000_STATUS_disabled 1 +#define DT_N_S_soc_S_adc_58026000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ -#define DT_N_S_soc_S_adc_58026000_PINCTRL_NUM 0 +#define DT_N_S_soc_S_adc_58026000_PINCTRL_NUM 1 +#define DT_N_S_soc_S_adc_58026000_PINCTRL_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_PINCTRL_IDX_0_TOKEN default +#define DT_N_S_soc_S_adc_58026000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT +#define DT_N_S_soc_S_adc_58026000_PINCTRL_NAME_default_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_PINCTRL_NAME_default_IDX 0 +#define DT_N_S_soc_S_adc_58026000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c +#define DT_N_S_soc_S_adc_58026000_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c /* Generic property macros: */ #define DT_N_S_soc_S_adc_58026000_P_wakeup_source 0 #define DT_N_S_soc_S_adc_58026000_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_adc_58026000_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_adc_58026000_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_status "disabled" -#define DT_N_S_soc_S_adc_58026000_P_status_STRING_UNQUOTED disabled -#define DT_N_S_soc_S_adc_58026000_P_status_STRING_TOKEN disabled -#define DT_N_S_soc_S_adc_58026000_P_status_STRING_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_adc_58026000_P_status_IDX_0 "disabled" +#define DT_N_S_soc_S_adc_58026000_P_status "okay" +#define DT_N_S_soc_S_adc_58026000_P_status_STRING_UNQUOTED okay +#define DT_N_S_soc_S_adc_58026000_P_status_STRING_TOKEN okay +#define DT_N_S_soc_S_adc_58026000_P_status_STRING_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_adc_58026000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_adc_58026000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_adc_58026000_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_adc_58026000_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_adc_58026000_P_status_ENUM_IDX 1 +#define DT_N_S_soc_S_adc_58026000_P_status_ENUM_VAL_okay_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_status_ENUM_TOKEN okay +#define DT_N_S_soc_S_adc_58026000_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_adc_58026000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_58026000, status, 0) #define DT_N_S_soc_S_adc_58026000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_58026000, status, 0) #define DT_N_S_soc_S_adc_58026000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_58026000, status, 0, __VA_ARGS__) @@ -1576,6 +2039,42 @@ #define DT_N_S_soc_S_adc_58026000_P_clocks_EXISTS 1 #define DT_N_S_soc_S_adc_58026000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_adc_58026000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 0) \ + fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 1) +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 1) +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 1, __VA_ARGS__) +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 1, __VA_ARGS__) +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_LEN 2 +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names {"default"} +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_IDX_0 "default" +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_IDX_0_STRING_TOKEN default +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_58026000, pinctrl_names, 0) +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_58026000, pinctrl_names, 0) +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_58026000, pinctrl_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_58026000, pinctrl_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_LEN 1 +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_st_adc_clock_source 1 +#define DT_N_S_soc_S_adc_58026000_P_st_adc_clock_source_ENUM_IDX 0 +#define DT_N_S_soc_S_adc_58026000_P_st_adc_clock_source_ENUM_VAL_1_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_st_adc_clock_source_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_st_adc_prescaler 4 +#define DT_N_S_soc_S_adc_58026000_P_st_adc_prescaler_ENUM_IDX 2 +#define DT_N_S_soc_S_adc_58026000_P_st_adc_prescaler_ENUM_VAL_4_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_st_adc_prescaler_EXISTS 1 #define DT_N_S_soc_S_adc_58026000_P_vref_mv 3300 #define DT_N_S_soc_S_adc_58026000_P_vref_mv_EXISTS 1 #define DT_N_S_soc_S_adc_58026000_P_resolutions {8446476 /* 0x80e20c */, 7725580 /* 0x75e20c */, 6742540 /* 0x66e20c */, 5497356 /* 0x53e20c */, 4710924 /* 0x47e20c */} @@ -1709,13 +2208,13 @@ #define DT_N_S_dietemp_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_dietemp_ORD 11 -#define DT_N_S_dietemp_ORD_STR_SORTABLE 00011 +#define DT_N_S_dietemp_ORD 14 +#define DT_N_S_dietemp_ORD_STR_SORTABLE 00014 /* Ordinals for what this node depends on directly: */ #define DT_N_S_dietemp_REQUIRES_ORDS \ 0, /* / */ \ - 10, /* /soc/adc@58026000 */ + 13, /* /soc/adc@58026000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_dietemp_SUPPORTS_ORDS /* nothing */ @@ -1843,8 +2342,8 @@ #define DT_N_S_memory_24000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_memory_24000000_ORD 12 -#define DT_N_S_memory_24000000_ORD_STR_SORTABLE 00012 +#define DT_N_S_memory_24000000_ORD 15 +#define DT_N_S_memory_24000000_ORD_STR_SORTABLE 00015 /* Ordinals for what this node depends on directly: */ #define DT_N_S_memory_24000000_REQUIRES_ORDS \ @@ -1941,8 +2440,8 @@ #define DT_N_S_memory_30000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_memory_30000000_ORD 13 -#define DT_N_S_memory_30000000_ORD_STR_SORTABLE 00013 +#define DT_N_S_memory_30000000_ORD 16 +#define DT_N_S_memory_30000000_ORD_STR_SORTABLE 00016 /* Ordinals for what this node depends on directly: */ #define DT_N_S_memory_30000000_REQUIRES_ORDS \ @@ -2066,8 +2565,8 @@ #define DT_N_S_memory_30020000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_memory_30020000_ORD 14 -#define DT_N_S_memory_30020000_ORD_STR_SORTABLE 00014 +#define DT_N_S_memory_30020000_ORD 17 +#define DT_N_S_memory_30020000_ORD_STR_SORTABLE 00017 /* Ordinals for what this node depends on directly: */ #define DT_N_S_memory_30020000_REQUIRES_ORDS \ @@ -2191,8 +2690,8 @@ #define DT_N_S_memory_30040000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_memory_30040000_ORD 15 -#define DT_N_S_memory_30040000_ORD_STR_SORTABLE 00015 +#define DT_N_S_memory_30040000_ORD 18 +#define DT_N_S_memory_30040000_ORD_STR_SORTABLE 00018 /* Ordinals for what this node depends on directly: */ #define DT_N_S_memory_30040000_REQUIRES_ORDS \ @@ -2316,8 +2815,8 @@ #define DT_N_S_memory_38000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_memory_38000000_ORD 16 -#define DT_N_S_memory_38000000_ORD_STR_SORTABLE 00016 +#define DT_N_S_memory_38000000_ORD 19 +#define DT_N_S_memory_38000000_ORD_STR_SORTABLE 00019 /* Ordinals for what this node depends on directly: */ #define DT_N_S_memory_38000000_REQUIRES_ORDS \ @@ -2441,8 +2940,8 @@ #define DT_N_S_memory_90000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_memory_90000000_ORD 17 -#define DT_N_S_memory_90000000_ORD_STR_SORTABLE 00017 +#define DT_N_S_memory_90000000_ORD 20 +#define DT_N_S_memory_90000000_ORD_STR_SORTABLE 00020 /* Ordinals for what this node depends on directly: */ #define DT_N_S_memory_90000000_REQUIRES_ORDS \ @@ -2557,8 +3056,8 @@ #define DT_N_S_sdram_c0000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_sdram_c0000000_ORD 18 -#define DT_N_S_sdram_c0000000_ORD_STR_SORTABLE 00018 +#define DT_N_S_sdram_c0000000_ORD 21 +#define DT_N_S_sdram_c0000000_ORD_STR_SORTABLE 00021 /* Ordinals for what this node depends on directly: */ #define DT_N_S_sdram_c0000000_REQUIRES_ORDS \ @@ -2642,208 +3141,6 @@ #define DT_N_S_sdram_c0000000_P_zephyr_memory_attr 1048576 #define DT_N_S_sdram_c0000000_P_zephyr_memory_attr_EXISTS 1 -/* - * Devicetree node: /soc/pin-controller@58020000 - * - * Node identifier: DT_N_S_soc_S_pin_controller_58020000 - * - * Binding (compatible = st,stm32-pinctrl): - * $ZEPHYR_BASE/dts/bindings/pinctrl/st,stm32-pinctrl.yaml - * - * (Descriptions have moved to the Devicetree Bindings Index - * in the documentation.) - */ - -/* Node's full path: */ -#define DT_N_S_soc_S_pin_controller_58020000_PATH "/soc/pin-controller@58020000" - -/* Node's name with unit-address: */ -#define DT_N_S_soc_S_pin_controller_58020000_FULL_NAME "pin-controller@58020000" - -/* Node parent (/soc) identifier: */ -#define DT_N_S_soc_S_pin_controller_58020000_PARENT DT_N_S_soc - -/* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_CHILD_IDX 5 - -/* Helpers for dealing with node labels: */ -#define DT_N_S_soc_S_pin_controller_58020000_NODELABEL_NUM 1 -#define DT_N_S_soc_S_pin_controller_58020000_FOREACH_NODELABEL(fn) fn(pinctrl) -#define DT_N_S_soc_S_pin_controller_58020000_FOREACH_NODELABEL_VARGS(fn, ...) fn(pinctrl, __VA_ARGS__) - -/* Helper macros for child nodes of this node. */ -#define DT_N_S_soc_S_pin_controller_58020000_CHILD_NUM 94 -#define DT_N_S_soc_S_pin_controller_58020000_CHILD_NUM_STATUS_OKAY 94 -#define DT_N_S_soc_S_pin_controller_58020000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12) -#define DT_N_S_soc_S_pin_controller_58020000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12) -#define DT_N_S_soc_S_pin_controller_58020000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12) -#define DT_N_S_soc_S_pin_controller_58020000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12) -#define DT_N_S_soc_S_pin_controller_58020000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12, __VA_ARGS__) - -/* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_ORD 19 -#define DT_N_S_soc_S_pin_controller_58020000_ORD_STR_SORTABLE 00019 - -/* Ordinals for what this node depends on directly: */ -#define DT_N_S_soc_S_pin_controller_58020000_REQUIRES_ORDS \ - 4, /* /soc */ - -/* Ordinals for what depends directly on this node: */ -#define DT_N_S_soc_S_pin_controller_58020000_SUPPORTS_ORDS \ - 20, /* /soc/pin-controller@58020000/i2c1_scl_pb8 */ \ - 21, /* /soc/pin-controller@58020000/i2c1_sda_pb9 */ \ - 24, /* /soc/pin-controller@58020000/i2c2_scl_ph4 */ \ - 25, /* /soc/pin-controller@58020000/i2c2_sda_pb11 */ \ - 30, /* /soc/pin-controller@58020000/i2c4_scl_pb6 */ \ - 31, /* /soc/pin-controller@58020000/i2c4_sda_ph12 */ \ - 36, /* /soc/pin-controller@58020000/adc1_inp10_pc0 */ \ - 37, /* /soc/pin-controller@58020000/adc1_inp12_pc2 */ \ - 38, /* /soc/pin-controller@58020000/adc1_inp13_pc3 */ \ - 39, /* /soc/pin-controller@58020000/adc1_inp16_pa0 */ \ - 40, /* /soc/pin-controller@58020000/adc1_inp4_pc4 */ \ - 41, /* /soc/pin-controller@58020000/adc1_inp5_pb1 */ \ - 42, /* /soc/pin-controller@58020000/adc1_inp8_pc5 */ \ - 43, /* /soc/pin-controller@58020000/adc1_inp9_pb0 */ \ - 45, /* /soc/pin-controller@58020000/usart1_rx_pb7 */ \ - 46, /* /soc/pin-controller@58020000/usart1_tx_pa9 */ \ - 49, /* /soc/pin-controller@58020000/usart6_rx_pc7 */ \ - 50, /* /soc/pin-controller@58020000/usart6_tx_pg14 */ \ - 52, /* /soc/pin-controller@58020000/spi1_miso_pg9 */ \ - 53, /* /soc/pin-controller@58020000/spi1_mosi_pd7 */ \ - 54, /* /soc/pin-controller@58020000/spi1_nss_pa4 */ \ - 55, /* /soc/pin-controller@58020000/spi1_sck_pb3 */ \ - 57, /* /soc/pin-controller@58020000/spi5_miso_pj11 */ \ - 58, /* /soc/pin-controller@58020000/spi5_mosi_pj10 */ \ - 59, /* /soc/pin-controller@58020000/spi5_nss_pk1 */ \ - 60, /* /soc/pin-controller@58020000/spi5_sck_ph6 */ \ - 62, /* /soc/pin-controller@58020000/gpio@58020000 */ \ - 63, /* /soc/pin-controller@58020000/gpio@58020400 */ \ - 64, /* /soc/pin-controller@58020000/gpio@58020800 */ \ - 65, /* /soc/pin-controller@58020000/gpio@58020C00 */ \ - 66, /* /soc/pin-controller@58020000/gpio@58021000 */ \ - 67, /* /soc/pin-controller@58020000/gpio@58021C00 */ \ - 68, /* /soc/pin-controller@58020000/gpio@58022000 */ \ - 69, /* /soc/pin-controller@58020000/gpio@58022400 */ \ - 70, /* /soc/pin-controller@58020000/gpio@58022800 */ \ - 72, /* /soc/pin-controller@58020000/usb_otg_fs_dm_pa11 */ \ - 73, /* /soc/pin-controller@58020000/usb_otg_fs_dp_pa12 */ \ - 98, /* /soc/pin-controller@58020000/fdcan2_rx_pb5 */ \ - 99, /* /soc/pin-controller@58020000/fdcan2_tx_pb13 */ \ - 101, /* /soc/pin-controller@58020000/dac1_out1_pa4 */ \ - 102, /* /soc/pin-controller@58020000/dac1_out2_pa5 */ \ - 122, /* /soc/pin-controller@58020000/uart4_rx_pi9 */ \ - 123, /* /soc/pin-controller@58020000/uart4_tx_ph13 */ \ - 152, /* /soc/pin-controller@58020000/fmc_a0_pf0 */ \ - 153, /* /soc/pin-controller@58020000/fmc_a10_pg0 */ \ - 154, /* /soc/pin-controller@58020000/fmc_a11_pg1 */ \ - 155, /* /soc/pin-controller@58020000/fmc_a12_pg2 */ \ - 156, /* /soc/pin-controller@58020000/fmc_a14_pg4 */ \ - 157, /* /soc/pin-controller@58020000/fmc_a15_pg5 */ \ - 158, /* /soc/pin-controller@58020000/fmc_a1_pf1 */ \ - 159, /* /soc/pin-controller@58020000/fmc_a2_pf2 */ \ - 160, /* /soc/pin-controller@58020000/fmc_a3_pf3 */ \ - 161, /* /soc/pin-controller@58020000/fmc_a4_pf4 */ \ - 162, /* /soc/pin-controller@58020000/fmc_a5_pf5 */ \ - 163, /* /soc/pin-controller@58020000/fmc_a6_pf12 */ \ - 164, /* /soc/pin-controller@58020000/fmc_a7_pf13 */ \ - 165, /* /soc/pin-controller@58020000/fmc_a8_pf14 */ \ - 166, /* /soc/pin-controller@58020000/fmc_a9_pf15 */ \ - 167, /* /soc/pin-controller@58020000/fmc_d0_pd14 */ \ - 168, /* /soc/pin-controller@58020000/fmc_d10_pe13 */ \ - 169, /* /soc/pin-controller@58020000/fmc_d11_pe14 */ \ - 170, /* /soc/pin-controller@58020000/fmc_d12_pe15 */ \ - 171, /* /soc/pin-controller@58020000/fmc_d13_pd8 */ \ - 172, /* /soc/pin-controller@58020000/fmc_d14_pd9 */ \ - 173, /* /soc/pin-controller@58020000/fmc_d15_pd10 */ \ - 174, /* /soc/pin-controller@58020000/fmc_d1_pd15 */ \ - 175, /* /soc/pin-controller@58020000/fmc_d2_pd0 */ \ - 176, /* /soc/pin-controller@58020000/fmc_d3_pd1 */ \ - 177, /* /soc/pin-controller@58020000/fmc_d4_pe7 */ \ - 178, /* /soc/pin-controller@58020000/fmc_d5_pe8 */ \ - 179, /* /soc/pin-controller@58020000/fmc_d6_pe9 */ \ - 180, /* /soc/pin-controller@58020000/fmc_d7_pe10 */ \ - 181, /* /soc/pin-controller@58020000/fmc_d8_pe11 */ \ - 182, /* /soc/pin-controller@58020000/fmc_d9_pe12 */ \ - 183, /* /soc/pin-controller@58020000/fmc_nbl0_pe0 */ \ - 184, /* /soc/pin-controller@58020000/fmc_nbl1_pe1 */ \ - 185, /* /soc/pin-controller@58020000/fmc_sdcke0_ph2 */ \ - 186, /* /soc/pin-controller@58020000/fmc_sdclk_pg8 */ \ - 187, /* /soc/pin-controller@58020000/fmc_sdncas_pg15 */ \ - 188, /* /soc/pin-controller@58020000/fmc_sdne0_ph3 */ \ - 189, /* /soc/pin-controller@58020000/fmc_sdnras_pf11 */ \ - 190, /* /soc/pin-controller@58020000/fmc_sdnwe_ph5 */ \ - 194, /* /soc/pin-controller@58020000/gpio@58021400 */ \ - 195, /* /soc/pin-controller@58020000/quadspi_bk1_io0_pd11 */ \ - 196, /* /soc/pin-controller@58020000/quadspi_bk1_io1_pd12 */ \ - 197, /* /soc/pin-controller@58020000/quadspi_bk1_io2_pe2 */ \ - 198, /* /soc/pin-controller@58020000/quadspi_bk1_io3_pf6 */ \ - 199, /* /soc/pin-controller@58020000/quadspi_bk1_ncs_pg6 */ \ - 200, /* /soc/pin-controller@58020000/quadspi_clk_pf10 */ \ - 208, /* /soc/pin-controller@58020000/gpio@58021800 */ \ - 209, /* /soc/pin-controller@58020000/uart7_cts_pf9 */ \ - 210, /* /soc/pin-controller@58020000/uart7_rts_pf8 */ \ - 211, /* /soc/pin-controller@58020000/uart7_rx_pa8 */ \ - 212, /* /soc/pin-controller@58020000/uart7_tx_pf7 */ - -/* Existence and alternate IDs: */ -#define DT_N_S_soc_S_pin_controller_58020000_EXISTS 1 -#define DT_N_INST_0_st_stm32_pinctrl DT_N_S_soc_S_pin_controller_58020000 -#define DT_N_NODELABEL_pinctrl DT_N_S_soc_S_pin_controller_58020000 - -/* Macros for properties that are special in the specification: */ -#define DT_N_S_soc_S_pin_controller_58020000_REG_NUM 1 -#define DT_N_S_soc_S_pin_controller_58020000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_REG_IDX_0_VAL_ADDRESS 1476526080 /* 0x58020000 */ -#define DT_N_S_soc_S_pin_controller_58020000_REG_IDX_0_VAL_SIZE 9216 /* 0x2400 */ -#define DT_N_S_soc_S_pin_controller_58020000_RANGES_NUM 0 -#define DT_N_S_soc_S_pin_controller_58020000_FOREACH_RANGE(fn) -#define DT_N_S_soc_S_pin_controller_58020000_IRQ_NUM 0 -#define DT_N_S_soc_S_pin_controller_58020000_IRQ_LEVEL 0 -#define DT_N_S_soc_S_pin_controller_58020000_COMPAT_MATCHES_st_stm32_pinctrl 1 -#define DT_N_S_soc_S_pin_controller_58020000_COMPAT_VENDOR_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_COMPAT_VENDOR_IDX_0 "STMicroelectronics" -#define DT_N_S_soc_S_pin_controller_58020000_COMPAT_MODEL_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_COMPAT_MODEL_IDX_0 "stm32-pinctrl" -#define DT_N_S_soc_S_pin_controller_58020000_STATUS_okay 1 - -/* Pin control (pinctrl-, pinctrl-names) properties: */ -#define DT_N_S_soc_S_pin_controller_58020000_PINCTRL_NUM 0 - -/* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_P_wakeup_source 0 -#define DT_N_S_soc_S_pin_controller_58020000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_pin_controller_58020000_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_P_compatible {"st,stm32-pinctrl"} -#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_IDX_0 "st,stm32-pinctrl" -#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pinctrl -#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_IDX_0_STRING_TOKEN st_stm32_pinctrl -#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PINCTRL -#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_LEN 1 -#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_P_reg {1476526080 /* 0x58020000 */, 9216 /* 0x2400 */} -#define DT_N_S_soc_S_pin_controller_58020000_P_reg_IDX_0 1476526080 -#define DT_N_S_soc_S_pin_controller_58020000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_P_reg_IDX_1 9216 -#define DT_N_S_soc_S_pin_controller_58020000_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_pin_controller_58020000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa11 0 -#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa11_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa12 0 -#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa12_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa11_pa12 0 -#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa11_pa12_EXISTS 1 - /* * Devicetree node: /soc/pin-controller@58020000/i2c1_scl_pb8 * @@ -2863,7 +3160,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_CHILD_IDX 62 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_CHILD_IDX 79 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_NODELABEL_NUM 1 @@ -2883,16 +3180,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_ORD 20 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_ORD_STR_SORTABLE 00020 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_ORD 22 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_ORD_STR_SORTABLE 00022 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_SUPPORTS_ORDS \ - 22, /* /soc/i2c@40005400 */ + 24, /* /soc/i2c@40005400 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_EXISTS 1 @@ -2962,7 +3259,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_CHILD_IDX 65 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_CHILD_IDX 82 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_NODELABEL_NUM 1 @@ -2982,16 +3279,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_ORD 21 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_ORD_STR_SORTABLE 00021 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_ORD 23 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_ORD_STR_SORTABLE 00023 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_SUPPORTS_ORDS \ - 22, /* /soc/i2c@40005400 */ + 24, /* /soc/i2c@40005400 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_EXISTS 1 @@ -3084,20 +3381,20 @@ #define DT_N_S_soc_S_i2c_40005400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_i2c_40005400_ORD 22 -#define DT_N_S_soc_S_i2c_40005400_ORD_STR_SORTABLE 00022 +#define DT_N_S_soc_S_i2c_40005400_ORD 24 +#define DT_N_S_soc_S_i2c_40005400_ORD_STR_SORTABLE 00024 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_i2c_40005400_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 20, /* /soc/pin-controller@58020000/i2c1_scl_pb8 */ \ - 21, /* /soc/pin-controller@58020000/i2c1_sda_pb9 */ + 22, /* /soc/pin-controller@58020000/i2c1_scl_pb8 */ \ + 23, /* /soc/pin-controller@58020000/i2c1_sda_pb9 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_i2c_40005400_SUPPORTS_ORDS \ - 23, /* /smbus1 */ + 25, /* /smbus1 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_i2c_40005400_EXISTS 1 @@ -3315,13 +3612,13 @@ #define DT_N_S_smbus1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_smbus1_ORD 23 -#define DT_N_S_smbus1_ORD_STR_SORTABLE 00023 +#define DT_N_S_smbus1_ORD 25 +#define DT_N_S_smbus1_ORD_STR_SORTABLE 00025 /* Ordinals for what this node depends on directly: */ #define DT_N_S_smbus1_REQUIRES_ORDS \ 0, /* / */ \ - 22, /* /soc/i2c@40005400 */ + 24, /* /soc/i2c@40005400 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_smbus1_SUPPORTS_ORDS /* nothing */ @@ -3412,7 +3709,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_CHILD_IDX 63 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_CHILD_IDX 80 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_NODELABEL_NUM 1 @@ -3432,16 +3729,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_ORD 24 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_ORD_STR_SORTABLE 00024 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_ORD 26 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_ORD_STR_SORTABLE 00026 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_SUPPORTS_ORDS \ - 26, /* /soc/i2c@40005800 */ + 28, /* /soc/i2c@40005800 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_EXISTS 1 @@ -3511,7 +3808,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_CHILD_IDX 66 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_CHILD_IDX 83 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_NODELABEL_NUM 1 @@ -3531,16 +3828,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_ORD 25 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_ORD_STR_SORTABLE 00025 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_ORD 27 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_ORD_STR_SORTABLE 00027 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_SUPPORTS_ORDS \ - 26, /* /soc/i2c@40005800 */ + 28, /* /soc/i2c@40005800 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_EXISTS 1 @@ -3633,20 +3930,20 @@ #define DT_N_S_soc_S_i2c_40005800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_i2c_40005800_ORD 26 -#define DT_N_S_soc_S_i2c_40005800_ORD_STR_SORTABLE 00026 +#define DT_N_S_soc_S_i2c_40005800_ORD 28 +#define DT_N_S_soc_S_i2c_40005800_ORD_STR_SORTABLE 00028 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_i2c_40005800_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 24, /* /soc/pin-controller@58020000/i2c2_scl_ph4 */ \ - 25, /* /soc/pin-controller@58020000/i2c2_sda_pb11 */ + 26, /* /soc/pin-controller@58020000/i2c2_scl_ph4 */ \ + 27, /* /soc/pin-controller@58020000/i2c2_sda_pb11 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_i2c_40005800_SUPPORTS_ORDS \ - 27, /* /smbus2 */ + 29, /* /smbus2 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_i2c_40005800_EXISTS 1 @@ -3864,13 +4161,13 @@ #define DT_N_S_smbus2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_smbus2_ORD 27 -#define DT_N_S_smbus2_ORD_STR_SORTABLE 00027 +#define DT_N_S_smbus2_ORD 29 +#define DT_N_S_smbus2_ORD_STR_SORTABLE 00029 /* Ordinals for what this node depends on directly: */ #define DT_N_S_smbus2_REQUIRES_ORDS \ 0, /* / */ \ - 26, /* /soc/i2c@40005800 */ + 28, /* /soc/i2c@40005800 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_smbus2_SUPPORTS_ORDS /* nothing */ @@ -3984,8 +4281,8 @@ #define DT_N_S_soc_S_i2c_40005c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_i2c_40005c00_ORD 28 -#define DT_N_S_soc_S_i2c_40005c00_ORD_STR_SORTABLE 00028 +#define DT_N_S_soc_S_i2c_40005c00_ORD 30 +#define DT_N_S_soc_S_i2c_40005c00_ORD_STR_SORTABLE 00030 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_i2c_40005c00_REQUIRES_ORDS \ @@ -3995,7 +4292,7 @@ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_i2c_40005c00_SUPPORTS_ORDS \ - 29, /* /smbus3 */ + 31, /* /smbus3 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_i2c_40005c00_EXISTS 1 @@ -4178,13 +4475,13 @@ #define DT_N_S_smbus3_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_smbus3_ORD 29 -#define DT_N_S_smbus3_ORD_STR_SORTABLE 00029 +#define DT_N_S_smbus3_ORD 31 +#define DT_N_S_smbus3_ORD_STR_SORTABLE 00031 /* Ordinals for what this node depends on directly: */ #define DT_N_S_smbus3_REQUIRES_ORDS \ 0, /* / */ \ - 28, /* /soc/i2c@40005c00 */ + 30, /* /soc/i2c@40005c00 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_smbus3_SUPPORTS_ORDS /* nothing */ @@ -4275,7 +4572,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_CHILD_IDX 64 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_CHILD_IDX 81 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_NODELABEL_NUM 1 @@ -4295,16 +4592,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_ORD 30 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_ORD_STR_SORTABLE 00030 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_ORD 32 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_ORD_STR_SORTABLE 00032 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_SUPPORTS_ORDS \ - 32, /* /soc/i2c@58001c00 */ + 34, /* /soc/i2c@58001c00 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_EXISTS 1 @@ -4374,7 +4671,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_CHILD_IDX 67 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_CHILD_IDX 84 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_NODELABEL_NUM 1 @@ -4394,16 +4691,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_ORD 31 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_ORD_STR_SORTABLE 00031 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_ORD 33 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_ORD_STR_SORTABLE 00033 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_SUPPORTS_ORDS \ - 32, /* /soc/i2c@58001c00 */ + 34, /* /soc/i2c@58001c00 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_EXISTS 1 @@ -4484,33 +4781,34 @@ #define DT_N_S_soc_S_i2c_58001c00_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c4, __VA_ARGS__) fn(arduino_i2c, __VA_ARGS__) /* Helper macros for child nodes of this node. */ -#define DT_N_S_soc_S_i2c_58001c00_CHILD_NUM 0 -#define DT_N_S_soc_S_i2c_58001c00_CHILD_NUM_STATUS_OKAY 0 -#define DT_N_S_soc_S_i2c_58001c00_FOREACH_CHILD(fn) -#define DT_N_S_soc_S_i2c_58001c00_FOREACH_CHILD_SEP(fn, sep) -#define DT_N_S_soc_S_i2c_58001c00_FOREACH_CHILD_VARGS(fn, ...) -#define DT_N_S_soc_S_i2c_58001c00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) -#define DT_N_S_soc_S_i2c_58001c00_FOREACH_CHILD_STATUS_OKAY(fn) -#define DT_N_S_soc_S_i2c_58001c00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) -#define DT_N_S_soc_S_i2c_58001c00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) -#define DT_N_S_soc_S_i2c_58001c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_i2c_58001c00_CHILD_NUM 1 +#define DT_N_S_soc_S_i2c_58001c00_CHILD_NUM_STATUS_OKAY 1 +#define DT_N_S_soc_S_i2c_58001c00_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21) +#define DT_N_S_soc_S_i2c_58001c00_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21) +#define DT_N_S_soc_S_i2c_58001c00_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_58001c00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_58001c00_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21) +#define DT_N_S_soc_S_i2c_58001c00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21) +#define DT_N_S_soc_S_i2c_58001c00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_58001c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_i2c_58001c00_ORD 32 -#define DT_N_S_soc_S_i2c_58001c00_ORD_STR_SORTABLE 00032 +#define DT_N_S_soc_S_i2c_58001c00_ORD 34 +#define DT_N_S_soc_S_i2c_58001c00_ORD_STR_SORTABLE 00034 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_i2c_58001c00_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 30, /* /soc/pin-controller@58020000/i2c4_scl_pb6 */ \ - 31, /* /soc/pin-controller@58020000/i2c4_sda_ph12 */ + 32, /* /soc/pin-controller@58020000/i2c4_scl_pb6 */ \ + 33, /* /soc/pin-controller@58020000/i2c4_sda_ph12 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_i2c_58001c00_SUPPORTS_ORDS \ - 33, /* /smbus4 */ \ - 76, /* /zephyr,user */ + 35, /* /smbus4 */ \ + 87, /* /zephyr,user */ \ + 161, /* /soc/i2c@58001c00/ov7670@21 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_i2c_58001c00_EXISTS 1 @@ -4729,13 +5027,13 @@ #define DT_N_S_smbus4_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_smbus4_ORD 33 -#define DT_N_S_smbus4_ORD_STR_SORTABLE 00033 +#define DT_N_S_smbus4_ORD 35 +#define DT_N_S_smbus4_ORD_STR_SORTABLE 00035 /* Ordinals for what this node depends on directly: */ #define DT_N_S_smbus4_REQUIRES_ORDS \ 0, /* / */ \ - 32, /* /soc/i2c@58001c00 */ + 34, /* /soc/i2c@58001c00 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_smbus4_SUPPORTS_ORDS /* nothing */ @@ -4849,13 +5147,13 @@ #define DT_N_S_vbat_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_vbat_ORD 34 -#define DT_N_S_vbat_ORD_STR_SORTABLE 00034 +#define DT_N_S_vbat_ORD 36 +#define DT_N_S_vbat_ORD_STR_SORTABLE 00036 /* Ordinals for what this node depends on directly: */ #define DT_N_S_vbat_REQUIRES_ORDS \ 0, /* / */ \ - 10, /* /soc/adc@58026000 */ + 13, /* /soc/adc@58026000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_vbat_SUPPORTS_ORDS /* nothing */ @@ -4971,13 +5269,13 @@ #define DT_N_S_vref_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_vref_ORD 35 -#define DT_N_S_vref_ORD_STR_SORTABLE 00035 +#define DT_N_S_vref_ORD 37 +#define DT_N_S_vref_ORD_STR_SORTABLE 00037 /* Ordinals for what this node depends on directly: */ #define DT_N_S_vref_REQUIRES_ORDS \ 0, /* / */ \ - 10, /* /soc/adc@58026000 */ + 13, /* /soc/adc@58026000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_vref_SUPPORTS_ORDS /* nothing */ @@ -5053,6 +5351,228 @@ #define DT_N_S_vref_P_vrefint_cal_mv 3300 #define DT_N_S_vref_P_vrefint_cal_mv_EXISTS 1 +/* + * Devicetree node: /gpio@deadbeef + * + * Node identifier: DT_N_S_gpio_deadbeef + * + * Binding (compatible = vnd,gpio): + * $ZEPHYR_BASE/dts/bindings/test/vnd,gpio.yaml + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_gpio_deadbeef_PATH "/gpio@deadbeef" + +/* Node's name with unit-address: */ +#define DT_N_S_gpio_deadbeef_FULL_NAME "gpio@deadbeef" + +/* Node parent (/) identifier: */ +#define DT_N_S_gpio_deadbeef_PARENT DT_N + +/* Node's index in its parent's list of children: */ +#define DT_N_S_gpio_deadbeef_CHILD_IDX 23 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_gpio_deadbeef_NODELABEL_NUM 1 +#define DT_N_S_gpio_deadbeef_FOREACH_NODELABEL(fn) fn(gpioz) +#define DT_N_S_gpio_deadbeef_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpioz, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_gpio_deadbeef_CHILD_NUM 0 +#define DT_N_S_gpio_deadbeef_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_gpio_deadbeef_FOREACH_CHILD(fn) +#define DT_N_S_gpio_deadbeef_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_gpio_deadbeef_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_gpio_deadbeef_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_gpio_deadbeef_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_gpio_deadbeef_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_gpio_deadbeef_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_gpio_deadbeef_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_gpio_deadbeef_ORD 38 +#define DT_N_S_gpio_deadbeef_ORD_STR_SORTABLE 00038 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_gpio_deadbeef_REQUIRES_ORDS \ + 0, /* / */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_gpio_deadbeef_SUPPORTS_ORDS \ + 87, /* /zephyr,user */ + +/* Existence and alternate IDs: */ +#define DT_N_S_gpio_deadbeef_EXISTS 1 +#define DT_N_INST_0_vnd_gpio DT_N_S_gpio_deadbeef +#define DT_N_NODELABEL_gpioz DT_N_S_gpio_deadbeef + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_gpio_deadbeef_REG_NUM 1 +#define DT_N_S_gpio_deadbeef_REG_IDX_0_EXISTS 1 +#define DT_N_S_gpio_deadbeef_REG_IDX_0_VAL_ADDRESS 3735928559 /* 0xdeadbeef */ +#define DT_N_S_gpio_deadbeef_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ +#define DT_N_S_gpio_deadbeef_RANGES_NUM 0 +#define DT_N_S_gpio_deadbeef_FOREACH_RANGE(fn) +#define DT_N_S_gpio_deadbeef_IRQ_NUM 0 +#define DT_N_S_gpio_deadbeef_IRQ_LEVEL 0 +#define DT_N_S_gpio_deadbeef_COMPAT_MATCHES_vnd_gpio 1 +#define DT_N_S_gpio_deadbeef_COMPAT_VENDOR_IDX_0_EXISTS 1 +#define DT_N_S_gpio_deadbeef_COMPAT_VENDOR_IDX_0 "A stand-in for a real vendor which can be used in examples and tests" +#define DT_N_S_gpio_deadbeef_COMPAT_MODEL_IDX_0_EXISTS 1 +#define DT_N_S_gpio_deadbeef_COMPAT_MODEL_IDX_0 "gpio" +#define DT_N_S_gpio_deadbeef_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_gpio_deadbeef_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_gpio_deadbeef_P_gpio_controller 1 +#define DT_N_S_gpio_deadbeef_P_gpio_controller_EXISTS 1 +#define DT_N_S_gpio_deadbeef_P_ngpios 32 +#define DT_N_S_gpio_deadbeef_P_ngpios_EXISTS 1 +#define DT_N_S_gpio_deadbeef_P_wakeup_source 0 +#define DT_N_S_gpio_deadbeef_P_wakeup_source_EXISTS 1 +#define DT_N_S_gpio_deadbeef_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_gpio_deadbeef_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_gpio_deadbeef_P_status "okay" +#define DT_N_S_gpio_deadbeef_P_status_STRING_UNQUOTED okay +#define DT_N_S_gpio_deadbeef_P_status_STRING_TOKEN okay +#define DT_N_S_gpio_deadbeef_P_status_STRING_UPPER_TOKEN OKAY +#define DT_N_S_gpio_deadbeef_P_status_IDX_0 "okay" +#define DT_N_S_gpio_deadbeef_P_status_IDX_0_EXISTS 1 +#define DT_N_S_gpio_deadbeef_P_status_ENUM_IDX 1 +#define DT_N_S_gpio_deadbeef_P_status_ENUM_VAL_okay_EXISTS 1 +#define DT_N_S_gpio_deadbeef_P_status_ENUM_TOKEN okay +#define DT_N_S_gpio_deadbeef_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_gpio_deadbeef_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_gpio_deadbeef, status, 0) +#define DT_N_S_gpio_deadbeef_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_gpio_deadbeef, status, 0) +#define DT_N_S_gpio_deadbeef_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_gpio_deadbeef, status, 0, __VA_ARGS__) +#define DT_N_S_gpio_deadbeef_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_gpio_deadbeef, status, 0, __VA_ARGS__) +#define DT_N_S_gpio_deadbeef_P_status_LEN 1 +#define DT_N_S_gpio_deadbeef_P_status_EXISTS 1 +#define DT_N_S_gpio_deadbeef_P_compatible {"vnd,gpio"} +#define DT_N_S_gpio_deadbeef_P_compatible_IDX_0 "vnd,gpio" +#define DT_N_S_gpio_deadbeef_P_compatible_IDX_0_STRING_UNQUOTED vnd,gpio +#define DT_N_S_gpio_deadbeef_P_compatible_IDX_0_STRING_TOKEN vnd_gpio +#define DT_N_S_gpio_deadbeef_P_compatible_IDX_0_STRING_UPPER_TOKEN VND_GPIO +#define DT_N_S_gpio_deadbeef_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_gpio_deadbeef_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_gpio_deadbeef, compatible, 0) +#define DT_N_S_gpio_deadbeef_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_gpio_deadbeef, compatible, 0) +#define DT_N_S_gpio_deadbeef_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_gpio_deadbeef, compatible, 0, __VA_ARGS__) +#define DT_N_S_gpio_deadbeef_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_gpio_deadbeef, compatible, 0, __VA_ARGS__) +#define DT_N_S_gpio_deadbeef_P_compatible_LEN 1 +#define DT_N_S_gpio_deadbeef_P_compatible_EXISTS 1 +#define DT_N_S_gpio_deadbeef_P_reg {3735928559 /* 0xdeadbeef */, 4096 /* 0x1000 */} +#define DT_N_S_gpio_deadbeef_P_reg_IDX_0 3735928559 +#define DT_N_S_gpio_deadbeef_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_gpio_deadbeef_P_reg_IDX_1 4096 +#define DT_N_S_gpio_deadbeef_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_gpio_deadbeef_P_reg_EXISTS 1 +#define DT_N_S_gpio_deadbeef_P_zephyr_deferred_init 0 +#define DT_N_S_gpio_deadbeef_P_zephyr_deferred_init_EXISTS 1 + +/* + * Devicetree node: /soc/pin-controller@58020000/adc1_inp0_pa0_c + * + * Node identifier: DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_PATH "/soc/pin-controller@58020000/adc1_inp0_pa0_c" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_FULL_NAME "adc1_inp0_pa0_c" + +/* Node parent (/soc/pin-controller@58020000) identifier: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_PARENT DT_N_S_soc_S_pin_controller_58020000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_CHILD_IDX 12 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_NODELABEL_NUM 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_FOREACH_NODELABEL(fn) fn(adc1_inp0_pa0_c) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_FOREACH_NODELABEL_VARGS(fn, ...) fn(adc1_inp0_pa0_c, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_CHILD_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_ORD 39 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_ORD_STR_SORTABLE 00039 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_REQUIRES_ORDS \ + 10, /* /soc/pin-controller@58020000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_SUPPORTS_ORDS \ + 51, /* /soc/adc@40022000 */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_EXISTS 1 +#define DT_N_NODELABEL_adc1_inp0_pa0_c DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_REG_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_RANGES_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_IRQ_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_IRQ_LEVEL 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_output_high_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_pinmux 16 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_pinmux_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate "low-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_STRING_UNQUOTED low-speed +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_STRING_TOKEN low_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_IDX_0 "low-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_ENUM_TOKEN low_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_EXISTS 1 + /* * Devicetree node: /soc/pin-controller@58020000/adc1_inp10_pc0 * @@ -5072,7 +5592,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_CHILD_IDX 14 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_CHILD_IDX 18 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_NODELABEL_NUM 1 @@ -5092,16 +5612,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_ORD 36 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_ORD_STR_SORTABLE 00036 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_ORD 40 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_ORD_STR_SORTABLE 00040 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_SUPPORTS_ORDS \ - 44, /* /soc/adc@40022000 */ + 51, /* /soc/adc@40022000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_EXISTS 1 @@ -5171,7 +5691,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_CHILD_IDX 15 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_CHILD_IDX 19 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_NODELABEL_NUM 1 @@ -5191,16 +5711,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_ORD 37 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_ORD_STR_SORTABLE 00037 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_ORD 41 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_ORD_STR_SORTABLE 00041 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_SUPPORTS_ORDS \ - 44, /* /soc/adc@40022000 */ + 51, /* /soc/adc@40022000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_EXISTS 1 @@ -5270,7 +5790,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_CHILD_IDX 16 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_CHILD_IDX 20 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_NODELABEL_NUM 1 @@ -5290,16 +5810,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_ORD 38 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_ORD_STR_SORTABLE 00038 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_ORD 42 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_ORD_STR_SORTABLE 00042 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_SUPPORTS_ORDS \ - 44, /* /soc/adc@40022000 */ + 51, /* /soc/adc@40022000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_EXISTS 1 @@ -5389,16 +5909,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_ORD 39 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_ORD_STR_SORTABLE 00039 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_ORD 43 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_ORD_STR_SORTABLE 00043 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_SUPPORTS_ORDS \ - 44, /* /soc/adc@40022000 */ + 51, /* /soc/adc@40022000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_EXISTS 1 @@ -5449,6 +5969,303 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_slew_rate_EXISTS 1 +/* + * Devicetree node: /soc/pin-controller@58020000/adc1_inp18_pa4 + * + * Node identifier: DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4 + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_PATH "/soc/pin-controller@58020000/adc1_inp18_pa4" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_FULL_NAME "adc1_inp18_pa4" + +/* Node parent (/soc/pin-controller@58020000) identifier: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_PARENT DT_N_S_soc_S_pin_controller_58020000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_CHILD_IDX 14 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_NODELABEL_NUM 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_FOREACH_NODELABEL(fn) fn(adc1_inp18_pa4) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_FOREACH_NODELABEL_VARGS(fn, ...) fn(adc1_inp18_pa4, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_CHILD_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_ORD 44 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_ORD_STR_SORTABLE 00044 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_REQUIRES_ORDS \ + 10, /* /soc/pin-controller@58020000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_SUPPORTS_ORDS \ + 51, /* /soc/adc@40022000 */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_EXISTS 1 +#define DT_N_NODELABEL_adc1_inp18_pa4 DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_REG_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_RANGES_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_IRQ_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_IRQ_LEVEL 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_output_high_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_pinmux 144 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_pinmux_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate "low-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_STRING_UNQUOTED low-speed +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_STRING_TOKEN low_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_IDX_0 "low-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_ENUM_TOKEN low_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_EXISTS 1 + +/* + * Devicetree node: /soc/pin-controller@58020000/adc1_inp19_pa5 + * + * Node identifier: DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5 + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_PATH "/soc/pin-controller@58020000/adc1_inp19_pa5" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_FULL_NAME "adc1_inp19_pa5" + +/* Node parent (/soc/pin-controller@58020000) identifier: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_PARENT DT_N_S_soc_S_pin_controller_58020000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_CHILD_IDX 15 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_NODELABEL_NUM 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_FOREACH_NODELABEL(fn) fn(adc1_inp19_pa5) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_FOREACH_NODELABEL_VARGS(fn, ...) fn(adc1_inp19_pa5, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_CHILD_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_ORD 45 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_ORD_STR_SORTABLE 00045 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_REQUIRES_ORDS \ + 10, /* /soc/pin-controller@58020000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_SUPPORTS_ORDS \ + 51, /* /soc/adc@40022000 */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_EXISTS 1 +#define DT_N_NODELABEL_adc1_inp19_pa5 DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_REG_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_RANGES_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_IRQ_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_IRQ_LEVEL 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_output_high_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_pinmux 176 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_pinmux_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate "low-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_STRING_UNQUOTED low-speed +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_STRING_TOKEN low_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_IDX_0 "low-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_ENUM_TOKEN low_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_EXISTS 1 + +/* + * Devicetree node: /soc/pin-controller@58020000/adc1_inp1_pa1_c + * + * Node identifier: DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_PATH "/soc/pin-controller@58020000/adc1_inp1_pa1_c" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_FULL_NAME "adc1_inp1_pa1_c" + +/* Node parent (/soc/pin-controller@58020000) identifier: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_PARENT DT_N_S_soc_S_pin_controller_58020000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_CHILD_IDX 13 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_NODELABEL_NUM 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_FOREACH_NODELABEL(fn) fn(adc1_inp1_pa1_c) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_FOREACH_NODELABEL_VARGS(fn, ...) fn(adc1_inp1_pa1_c, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_CHILD_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_ORD 46 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_ORD_STR_SORTABLE 00046 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_REQUIRES_ORDS \ + 10, /* /soc/pin-controller@58020000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_SUPPORTS_ORDS \ + 51, /* /soc/adc@40022000 */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_EXISTS 1 +#define DT_N_NODELABEL_adc1_inp1_pa1_c DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_REG_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_RANGES_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_IRQ_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_IRQ_LEVEL 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_output_high_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_pinmux 48 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_pinmux_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate "low-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_STRING_UNQUOTED low-speed +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_STRING_TOKEN low_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_IDX_0 "low-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_ENUM_TOKEN low_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_EXISTS 1 + /* * Devicetree node: /soc/pin-controller@58020000/adc1_inp4_pc4 * @@ -5468,7 +6285,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_CHILD_IDX 17 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_CHILD_IDX 21 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_NODELABEL_NUM 1 @@ -5488,16 +6305,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_ORD 40 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_ORD_STR_SORTABLE 00040 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_ORD 47 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_ORD_STR_SORTABLE 00047 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_SUPPORTS_ORDS \ - 44, /* /soc/adc@40022000 */ + 51, /* /soc/adc@40022000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_EXISTS 1 @@ -5567,7 +6384,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_CHILD_IDX 13 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_CHILD_IDX 17 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_NODELABEL_NUM 1 @@ -5587,16 +6404,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_ORD 41 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_ORD_STR_SORTABLE 00041 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_ORD 48 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_ORD_STR_SORTABLE 00048 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_SUPPORTS_ORDS \ - 44, /* /soc/adc@40022000 */ + 51, /* /soc/adc@40022000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_EXISTS 1 @@ -5666,7 +6483,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_CHILD_IDX 18 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_CHILD_IDX 22 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_NODELABEL_NUM 1 @@ -5686,16 +6503,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_ORD 42 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_ORD_STR_SORTABLE 00042 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_ORD 49 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_ORD_STR_SORTABLE 00049 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_SUPPORTS_ORDS \ - 44, /* /soc/adc@40022000 */ + 51, /* /soc/adc@40022000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_EXISTS 1 @@ -5765,7 +6582,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_CHILD_IDX 12 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_CHILD_IDX 16 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_NODELABEL_NUM 1 @@ -5785,16 +6602,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_ORD 43 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_ORD_STR_SORTABLE 00043 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_ORD 50 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_ORD_STR_SORTABLE 00050 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_SUPPORTS_ORDS \ - 44, /* /soc/adc@40022000 */ + 51, /* /soc/adc@40022000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_EXISTS 1 @@ -5875,46 +6692,54 @@ #define DT_N_S_soc_S_adc_40022000_FOREACH_NODELABEL_VARGS(fn, ...) fn(adc1, __VA_ARGS__) /* Helper macros for child nodes of this node. */ -#define DT_N_S_soc_S_adc_40022000_CHILD_NUM 8 -#define DT_N_S_soc_S_adc_40022000_CHILD_NUM_STATUS_OKAY 8 -#define DT_N_S_soc_S_adc_40022000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_4) fn(DT_N_S_soc_S_adc_40022000_S_channel_8) fn(DT_N_S_soc_S_adc_40022000_S_channel_9) fn(DT_N_S_soc_S_adc_40022000_S_channel_5) fn(DT_N_S_soc_S_adc_40022000_S_channel_13) fn(DT_N_S_soc_S_adc_40022000_S_channel_12) fn(DT_N_S_soc_S_adc_40022000_S_channel_10) fn(DT_N_S_soc_S_adc_40022000_S_channel_16) -#define DT_N_S_soc_S_adc_40022000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_16) -#define DT_N_S_soc_S_adc_40022000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_4, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_8, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_9, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_5, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_10, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_16, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_16, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_4) fn(DT_N_S_soc_S_adc_40022000_S_channel_8) fn(DT_N_S_soc_S_adc_40022000_S_channel_9) fn(DT_N_S_soc_S_adc_40022000_S_channel_5) fn(DT_N_S_soc_S_adc_40022000_S_channel_13) fn(DT_N_S_soc_S_adc_40022000_S_channel_12) fn(DT_N_S_soc_S_adc_40022000_S_channel_10) fn(DT_N_S_soc_S_adc_40022000_S_channel_16) -#define DT_N_S_soc_S_adc_40022000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_16) -#define DT_N_S_soc_S_adc_40022000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_4, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_8, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_9, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_5, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_10, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_16, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_16, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_CHILD_NUM 12 +#define DT_N_S_soc_S_adc_40022000_CHILD_NUM_STATUS_OKAY 12 +#define DT_N_S_soc_S_adc_40022000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_4) fn(DT_N_S_soc_S_adc_40022000_S_channel_8) fn(DT_N_S_soc_S_adc_40022000_S_channel_9) fn(DT_N_S_soc_S_adc_40022000_S_channel_5) fn(DT_N_S_soc_S_adc_40022000_S_channel_d) fn(DT_N_S_soc_S_adc_40022000_S_channel_c) fn(DT_N_S_soc_S_adc_40022000_S_channel_a) fn(DT_N_S_soc_S_adc_40022000_S_channel_10) fn(DT_N_S_soc_S_adc_40022000_S_channel_12) fn(DT_N_S_soc_S_adc_40022000_S_channel_13) fn(DT_N_S_soc_S_adc_40022000_S_channel_0) fn(DT_N_S_soc_S_adc_40022000_S_channel_1) +#define DT_N_S_soc_S_adc_40022000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_d) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_a) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_1) +#define DT_N_S_soc_S_adc_40022000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_4, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_8, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_9, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_5, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_d, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_c, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_a, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_10, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_0, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_1, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_d, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_a, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_1, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_4) fn(DT_N_S_soc_S_adc_40022000_S_channel_8) fn(DT_N_S_soc_S_adc_40022000_S_channel_9) fn(DT_N_S_soc_S_adc_40022000_S_channel_5) fn(DT_N_S_soc_S_adc_40022000_S_channel_d) fn(DT_N_S_soc_S_adc_40022000_S_channel_c) fn(DT_N_S_soc_S_adc_40022000_S_channel_a) fn(DT_N_S_soc_S_adc_40022000_S_channel_10) fn(DT_N_S_soc_S_adc_40022000_S_channel_12) fn(DT_N_S_soc_S_adc_40022000_S_channel_13) fn(DT_N_S_soc_S_adc_40022000_S_channel_0) fn(DT_N_S_soc_S_adc_40022000_S_channel_1) +#define DT_N_S_soc_S_adc_40022000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_d) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_a) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_1) +#define DT_N_S_soc_S_adc_40022000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_4, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_8, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_9, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_5, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_d, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_c, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_a, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_10, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_0, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_1, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_d, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_a, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40022000_S_channel_1, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022000_ORD 44 -#define DT_N_S_soc_S_adc_40022000_ORD_STR_SORTABLE 00044 +#define DT_N_S_soc_S_adc_40022000_ORD 51 +#define DT_N_S_soc_S_adc_40022000_ORD_STR_SORTABLE 00051 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_40022000_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 36, /* /soc/pin-controller@58020000/adc1_inp10_pc0 */ \ - 37, /* /soc/pin-controller@58020000/adc1_inp12_pc2 */ \ - 38, /* /soc/pin-controller@58020000/adc1_inp13_pc3 */ \ - 39, /* /soc/pin-controller@58020000/adc1_inp16_pa0 */ \ - 40, /* /soc/pin-controller@58020000/adc1_inp4_pc4 */ \ - 41, /* /soc/pin-controller@58020000/adc1_inp5_pb1 */ \ - 42, /* /soc/pin-controller@58020000/adc1_inp8_pc5 */ \ - 43, /* /soc/pin-controller@58020000/adc1_inp9_pb0 */ + 39, /* /soc/pin-controller@58020000/adc1_inp0_pa0_c */ \ + 40, /* /soc/pin-controller@58020000/adc1_inp10_pc0 */ \ + 41, /* /soc/pin-controller@58020000/adc1_inp12_pc2 */ \ + 42, /* /soc/pin-controller@58020000/adc1_inp13_pc3 */ \ + 43, /* /soc/pin-controller@58020000/adc1_inp16_pa0 */ \ + 44, /* /soc/pin-controller@58020000/adc1_inp18_pa4 */ \ + 45, /* /soc/pin-controller@58020000/adc1_inp19_pa5 */ \ + 46, /* /soc/pin-controller@58020000/adc1_inp1_pa1_c */ \ + 47, /* /soc/pin-controller@58020000/adc1_inp4_pc4 */ \ + 48, /* /soc/pin-controller@58020000/adc1_inp5_pb1 */ \ + 49, /* /soc/pin-controller@58020000/adc1_inp8_pc5 */ \ + 50, /* /soc/pin-controller@58020000/adc1_inp9_pb0 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_40022000_SUPPORTS_ORDS \ - 76, /* /zephyr,user */ \ - 137, /* /soc/adc@40022000/channel@4 */ \ - 138, /* /soc/adc@40022000/channel@5 */ \ - 139, /* /soc/adc@40022000/channel@8 */ \ - 140, /* /soc/adc@40022000/channel@9 */ \ - 141, /* /soc/adc@40022000/channel@10 */ \ - 142, /* /soc/adc@40022000/channel@12 */ \ - 143, /* /soc/adc@40022000/channel@13 */ \ - 144, /* /soc/adc@40022000/channel@16 */ + 87, /* /zephyr,user */ \ + 146, /* /soc/adc@40022000/channel@0 */ \ + 147, /* /soc/adc@40022000/channel@1 */ \ + 148, /* /soc/adc@40022000/channel@4 */ \ + 149, /* /soc/adc@40022000/channel@5 */ \ + 150, /* /soc/adc@40022000/channel@8 */ \ + 151, /* /soc/adc@40022000/channel@9 */ \ + 152, /* /soc/adc@40022000/channel@a */ \ + 153, /* /soc/adc@40022000/channel@c */ \ + 154, /* /soc/adc@40022000/channel@d */ \ + 155, /* /soc/adc@40022000/channel@10 */ \ + 156, /* /soc/adc@40022000/channel@12 */ \ + 157, /* /soc/adc@40022000/channel@13 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_adc_40022000_EXISTS 1 @@ -5959,6 +6784,10 @@ #define DT_N_S_soc_S_adc_40022000_PINCTRL_NAME_default_IDX_5_PH DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2 #define DT_N_S_soc_S_adc_40022000_PINCTRL_NAME_default_IDX_6_PH DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0 #define DT_N_S_soc_S_adc_40022000_PINCTRL_NAME_default_IDX_7_PH DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0 +#define DT_N_S_soc_S_adc_40022000_PINCTRL_NAME_default_IDX_8_PH DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4 +#define DT_N_S_soc_S_adc_40022000_PINCTRL_NAME_default_IDX_9_PH DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5 +#define DT_N_S_soc_S_adc_40022000_PINCTRL_NAME_default_IDX_10_PH DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c +#define DT_N_S_soc_S_adc_40022000_PINCTRL_NAME_default_IDX_11_PH DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c /* Generic property macros: */ #define DT_N_S_soc_S_adc_40022000_P_wakeup_source 0 @@ -6043,6 +6872,18 @@ #define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_IDX_7 DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0 #define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_IDX_7_PH DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0 #define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_IDX_7_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_IDX_8 DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4 +#define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_IDX_8_PH DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4 +#define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_IDX_8_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_IDX_9 DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5 +#define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_IDX_9_PH DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5 +#define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_IDX_9_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_IDX_10 DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c +#define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_IDX_10_PH DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c +#define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_IDX_10_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_IDX_11 DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c +#define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_IDX_11_PH DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c +#define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_IDX_11_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 0) \ fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 1) \ fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 2) \ @@ -6050,7 +6891,11 @@ fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 4) \ fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 5) \ fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 6) \ - fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 7) + fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 7) \ + fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 8) \ + fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 9) \ + fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 10) \ + fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 11) #define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 2) DT_DEBRACKET_INTERNAL sep \ @@ -6058,7 +6903,11 @@ fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 4) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 5) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 6) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 7) + fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 7) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 8) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 9) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 10) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 11) #define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 0, __VA_ARGS__) \ fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 1, __VA_ARGS__) \ fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 2, __VA_ARGS__) \ @@ -6066,7 +6915,11 @@ fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 4, __VA_ARGS__) \ fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 5, __VA_ARGS__) \ fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 6, __VA_ARGS__) \ - fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 7, __VA_ARGS__) + fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 7, __VA_ARGS__) \ + fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 8, __VA_ARGS__) \ + fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 9, __VA_ARGS__) \ + fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 10, __VA_ARGS__) \ + fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 11, __VA_ARGS__) #define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ @@ -6074,8 +6927,12 @@ fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 7, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_LEN 8 + fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, pinctrl_0, 11, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_LEN 12 #define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_P_pinctrl_names {"default"} #define DT_N_S_soc_S_adc_40022000_P_pinctrl_names_IDX_0 "default" @@ -6207,7 +7064,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_CHILD_IDX 84 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_CHILD_IDX 102 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_NODELABEL_NUM 1 @@ -6227,16 +7084,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_ORD 45 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_ORD_STR_SORTABLE 00045 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_ORD 52 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_ORD_STR_SORTABLE 00052 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_SUPPORTS_ORDS \ - 48, /* /soc/serial@40011000 */ + 55, /* /soc/serial@40011000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_EXISTS 1 @@ -6306,7 +7163,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_CHILD_IDX 88 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_CHILD_IDX 106 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_NODELABEL_NUM 1 @@ -6326,16 +7183,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_ORD 46 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_ORD_STR_SORTABLE 00046 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_ORD 53 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_ORD_STR_SORTABLE 00053 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_SUPPORTS_ORDS \ - 48, /* /soc/serial@40011000 */ + 55, /* /soc/serial@40011000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_EXISTS 1 @@ -6428,8 +7285,8 @@ #define DT_N_S_soc_S_rcc_58024400_S_reset_controller_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_rcc_58024400_S_reset_controller_ORD 47 -#define DT_N_S_soc_S_rcc_58024400_S_reset_controller_ORD_STR_SORTABLE 00047 +#define DT_N_S_soc_S_rcc_58024400_S_reset_controller_ORD 54 +#define DT_N_S_soc_S_rcc_58024400_S_reset_controller_ORD_STR_SORTABLE 00054 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_rcc_58024400_S_reset_controller_REQUIRES_ORDS \ @@ -6437,32 +7294,32 @@ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_rcc_58024400_S_reset_controller_SUPPORTS_ORDS \ - 48, /* /soc/serial@40011000 */ \ - 51, /* /soc/serial@40011400 */ \ - 109, /* /soc/dsihost@50000000 */ \ - 118, /* /soc/sdmmc@48022400 */ \ - 119, /* /soc/sdmmc@52007000 */ \ - 120, /* /soc/serial@40004400 */ \ - 121, /* /soc/serial@40004800 */ \ - 124, /* /soc/serial@40004c00 */ \ - 125, /* /soc/serial@40005000 */ \ - 126, /* /soc/serial@40007c00 */ \ - 127, /* /soc/serial@58000c00 */ \ - 213, /* /soc/serial@40007800 */ \ - 216, /* /soc/timers@40000000 */ \ - 219, /* /soc/timers@40000400 */ \ - 222, /* /soc/timers@40000800 */ \ - 225, /* /soc/timers@40000c00 */ \ - 228, /* /soc/timers@40001000 */ \ - 230, /* /soc/timers@40001400 */ \ - 232, /* /soc/timers@40001800 */ \ - 235, /* /soc/timers@40001c00 */ \ - 238, /* /soc/timers@40002000 */ \ - 241, /* /soc/timers@40010000 */ \ - 243, /* /soc/timers@40010400 */ \ - 245, /* /soc/timers@40014000 */ \ - 248, /* /soc/timers@40014400 */ \ - 251, /* /soc/timers@40014800 */ + 55, /* /soc/serial@40011000 */ \ + 58, /* /soc/serial@40011400 */ \ + 79, /* /soc/timers@40010000 */ \ + 118, /* /soc/dsihost@50000000 */ \ + 127, /* /soc/sdmmc@48022400 */ \ + 128, /* /soc/sdmmc@52007000 */ \ + 129, /* /soc/serial@40004400 */ \ + 130, /* /soc/serial@40004800 */ \ + 133, /* /soc/serial@40004c00 */ \ + 134, /* /soc/serial@40005000 */ \ + 135, /* /soc/serial@40007c00 */ \ + 136, /* /soc/serial@58000c00 */ \ + 246, /* /soc/serial@40007800 */ \ + 249, /* /soc/timers@40000000 */ \ + 252, /* /soc/timers@40000400 */ \ + 255, /* /soc/timers@40000800 */ \ + 258, /* /soc/timers@40000c00 */ \ + 261, /* /soc/timers@40001000 */ \ + 263, /* /soc/timers@40001400 */ \ + 265, /* /soc/timers@40001800 */ \ + 268, /* /soc/timers@40001c00 */ \ + 271, /* /soc/timers@40002000 */ \ + 275, /* /soc/timers@40010400 */ \ + 277, /* /soc/timers@40014000 */ \ + 280, /* /soc/timers@40014400 */ \ + 283, /* /soc/timers@40014800 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_rcc_58024400_S_reset_controller_EXISTS 1 @@ -6549,21 +7406,21 @@ #define DT_N_S_soc_S_serial_40011000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_serial_40011000_ORD 48 -#define DT_N_S_soc_S_serial_40011000_ORD_STR_SORTABLE 00048 +#define DT_N_S_soc_S_serial_40011000_ORD 55 +#define DT_N_S_soc_S_serial_40011000_ORD_STR_SORTABLE 00055 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_serial_40011000_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 45, /* /soc/pin-controller@58020000/usart1_rx_pb7 */ \ - 46, /* /soc/pin-controller@58020000/usart1_tx_pa9 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ + 52, /* /soc/pin-controller@58020000/usart1_rx_pb7 */ \ + 53, /* /soc/pin-controller@58020000/usart1_tx_pa9 */ \ + 54, /* /soc/rcc@58024400/reset-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_serial_40011000_SUPPORTS_ORDS \ - 76, /* /zephyr,user */ + 87, /* /zephyr,user */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_serial_40011000_EXISTS 1 @@ -6758,7 +7615,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_CHILD_IDX 86 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_CHILD_IDX 104 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_NODELABEL_NUM 1 @@ -6778,16 +7635,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_ORD 49 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_ORD_STR_SORTABLE 00049 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_ORD 56 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_ORD_STR_SORTABLE 00056 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_SUPPORTS_ORDS \ - 51, /* /soc/serial@40011400 */ + 58, /* /soc/serial@40011400 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_EXISTS 1 @@ -6857,7 +7714,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_CHILD_IDX 90 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_CHILD_IDX 108 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_NODELABEL_NUM 1 @@ -6877,16 +7734,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_ORD 50 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_ORD_STR_SORTABLE 00050 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_ORD 57 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_ORD_STR_SORTABLE 00057 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_SUPPORTS_ORDS \ - 51, /* /soc/serial@40011400 */ + 58, /* /soc/serial@40011400 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_EXISTS 1 @@ -6979,21 +7836,21 @@ #define DT_N_S_soc_S_serial_40011400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_serial_40011400_ORD 51 -#define DT_N_S_soc_S_serial_40011400_ORD_STR_SORTABLE 00051 +#define DT_N_S_soc_S_serial_40011400_ORD 58 +#define DT_N_S_soc_S_serial_40011400_ORD_STR_SORTABLE 00058 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_serial_40011400_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ \ - 49, /* /soc/pin-controller@58020000/usart6_rx_pc7 */ \ - 50, /* /soc/pin-controller@58020000/usart6_tx_pg14 */ + 54, /* /soc/rcc@58024400/reset-controller */ \ + 56, /* /soc/pin-controller@58020000/usart6_rx_pc7 */ \ + 57, /* /soc/pin-controller@58020000/usart6_tx_pg14 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_serial_40011400_SUPPORTS_ORDS \ - 76, /* /zephyr,user */ + 87, /* /zephyr,user */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_serial_40011400_EXISTS 1 @@ -7187,7 +8044,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_CHILD_IDX 74 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_CHILD_IDX 91 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_NODELABEL_NUM 1 @@ -7207,16 +8064,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_ORD 52 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_ORD_STR_SORTABLE 00052 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_ORD 59 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_ORD_STR_SORTABLE 00059 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_SUPPORTS_ORDS \ - 56, /* /soc/spi@40013000 */ + 63, /* /soc/spi@40013000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_EXISTS 1 @@ -7286,7 +8143,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_CHILD_IDX 76 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_CHILD_IDX 93 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_NODELABEL_NUM 1 @@ -7306,16 +8163,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_ORD 53 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_ORD_STR_SORTABLE 00053 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_ORD 60 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_ORD_STR_SORTABLE 00060 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_SUPPORTS_ORDS \ - 56, /* /soc/spi@40013000 */ + 63, /* /soc/spi@40013000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_EXISTS 1 @@ -7385,7 +8242,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_CHILD_IDX 78 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_CHILD_IDX 95 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_NODELABEL_NUM 1 @@ -7405,16 +8262,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_ORD 54 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_ORD_STR_SORTABLE 00054 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_ORD 61 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_ORD_STR_SORTABLE 00061 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_SUPPORTS_ORDS \ - 56, /* /soc/spi@40013000 */ + 63, /* /soc/spi@40013000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_EXISTS 1 @@ -7484,7 +8341,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_CHILD_IDX 80 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_CHILD_IDX 97 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_NODELABEL_NUM 1 @@ -7504,16 +8361,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_ORD 55 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_ORD_STR_SORTABLE 00055 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_ORD 62 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_ORD_STR_SORTABLE 00062 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_SUPPORTS_ORDS \ - 56, /* /soc/spi@40013000 */ + 63, /* /soc/spi@40013000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_EXISTS 1 @@ -7606,22 +8463,22 @@ #define DT_N_S_soc_S_spi_40013000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_spi_40013000_ORD 56 -#define DT_N_S_soc_S_spi_40013000_ORD_STR_SORTABLE 00056 +#define DT_N_S_soc_S_spi_40013000_ORD 63 +#define DT_N_S_soc_S_spi_40013000_ORD_STR_SORTABLE 00063 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_spi_40013000_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 52, /* /soc/pin-controller@58020000/spi1_miso_pg9 */ \ - 53, /* /soc/pin-controller@58020000/spi1_mosi_pd7 */ \ - 54, /* /soc/pin-controller@58020000/spi1_nss_pa4 */ \ - 55, /* /soc/pin-controller@58020000/spi1_sck_pb3 */ + 59, /* /soc/pin-controller@58020000/spi1_miso_pg9 */ \ + 60, /* /soc/pin-controller@58020000/spi1_mosi_pd7 */ \ + 61, /* /soc/pin-controller@58020000/spi1_nss_pa4 */ \ + 62, /* /soc/pin-controller@58020000/spi1_sck_pb3 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_spi_40013000_SUPPORTS_ORDS \ - 76, /* /zephyr,user */ + 87, /* /zephyr,user */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_spi_40013000_EXISTS 1 @@ -7830,7 +8687,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_CHILD_IDX 75 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_CHILD_IDX 92 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_NODELABEL_NUM 1 @@ -7850,16 +8707,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_ORD 57 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_ORD_STR_SORTABLE 00057 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_ORD 64 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_ORD_STR_SORTABLE 00064 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_SUPPORTS_ORDS \ - 61, /* /soc/spi@40015000 */ + 68, /* /soc/spi@40015000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_EXISTS 1 @@ -7929,7 +8786,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_CHILD_IDX 77 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_CHILD_IDX 94 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_NODELABEL_NUM 1 @@ -7949,16 +8806,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_ORD 58 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_ORD_STR_SORTABLE 00058 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_ORD 65 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_ORD_STR_SORTABLE 00065 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_SUPPORTS_ORDS \ - 61, /* /soc/spi@40015000 */ + 68, /* /soc/spi@40015000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_EXISTS 1 @@ -8028,7 +8885,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_CHILD_IDX 79 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_CHILD_IDX 96 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_NODELABEL_NUM 1 @@ -8048,16 +8905,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_ORD 59 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_ORD_STR_SORTABLE 00059 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_ORD 66 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_ORD_STR_SORTABLE 00066 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_SUPPORTS_ORDS \ - 61, /* /soc/spi@40015000 */ + 68, /* /soc/spi@40015000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_EXISTS 1 @@ -8127,7 +8984,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_CHILD_IDX 81 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_CHILD_IDX 98 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_NODELABEL_NUM 1 @@ -8147,16 +9004,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_ORD 60 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_ORD_STR_SORTABLE 00060 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_ORD 67 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_ORD_STR_SORTABLE 00067 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_SUPPORTS_ORDS \ - 61, /* /soc/spi@40015000 */ + 68, /* /soc/spi@40015000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_EXISTS 1 @@ -8249,22 +9106,22 @@ #define DT_N_S_soc_S_spi_40015000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_spi_40015000_ORD 61 -#define DT_N_S_soc_S_spi_40015000_ORD_STR_SORTABLE 00061 +#define DT_N_S_soc_S_spi_40015000_ORD 68 +#define DT_N_S_soc_S_spi_40015000_ORD_STR_SORTABLE 00068 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_spi_40015000_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 57, /* /soc/pin-controller@58020000/spi5_miso_pj11 */ \ - 58, /* /soc/pin-controller@58020000/spi5_mosi_pj10 */ \ - 59, /* /soc/pin-controller@58020000/spi5_nss_pk1 */ \ - 60, /* /soc/pin-controller@58020000/spi5_sck_ph6 */ + 64, /* /soc/pin-controller@58020000/spi5_miso_pj11 */ \ + 65, /* /soc/pin-controller@58020000/spi5_mosi_pj10 */ \ + 66, /* /soc/pin-controller@58020000/spi5_nss_pk1 */ \ + 67, /* /soc/pin-controller@58020000/spi5_sck_ph6 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_spi_40015000_SUPPORTS_ORDS \ - 76, /* /zephyr,user */ + 87, /* /zephyr,user */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_spi_40015000_EXISTS 1 @@ -8487,18 +9344,19 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_ORD 62 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_ORD_STR_SORTABLE 00062 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_ORD 69 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_ORD_STR_SORTABLE 00069 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_REQUIRES_ORDS \ 9, /* /soc/rcc@58024400 */ \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_SUPPORTS_ORDS \ - 76, /* /zephyr,user */ \ - 215, /* /soc/serial@40007800/bt_hci_uart/murata-1dx */ + 87, /* /zephyr,user */ \ + 161, /* /soc/i2c@58001c00/ov7670@21 */ \ + 248, /* /soc/serial@40007800/bt_hci_uart/murata-1dx */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_EXISTS 1 @@ -8608,17 +9466,17 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_ORD 63 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_ORD_STR_SORTABLE 00063 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_ORD 70 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_ORD_STR_SORTABLE 00070 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_REQUIRES_ORDS \ 9, /* /soc/rcc@58024400 */ \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_SUPPORTS_ORDS \ - 76, /* /zephyr,user */ + 87, /* /zephyr,user */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_EXISTS 1 @@ -8728,19 +9586,19 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_ORD 64 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_ORD_STR_SORTABLE 00064 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_ORD 71 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_ORD_STR_SORTABLE 00071 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_REQUIRES_ORDS \ 9, /* /soc/rcc@58024400 */ \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_SUPPORTS_ORDS \ - 76, /* /zephyr,user */ \ - 88, /* /gpio_keys */ \ - 89, /* /gpio_keys/button_0 */ + 87, /* /zephyr,user */ \ + 99, /* /gpio_keys */ \ + 100, /* /gpio_keys/button_0 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_EXISTS 1 @@ -8850,17 +9708,18 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_ORD 65 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_ORD_STR_SORTABLE 00065 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_ORD 72 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_ORD_STR_SORTABLE 00072 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_REQUIRES_ORDS \ 9, /* /soc/rcc@58024400 */ \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_SUPPORTS_ORDS \ - 76, /* /zephyr,user */ + 87, /* /zephyr,user */ \ + 161, /* /soc/i2c@58001c00/ov7670@21 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_EXISTS 1 @@ -8970,19 +9829,19 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_ORD 66 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_ORD_STR_SORTABLE 00066 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_ORD 73 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_ORD_STR_SORTABLE 00073 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_REQUIRES_ORDS \ 9, /* /soc/rcc@58024400 */ \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_SUPPORTS_ORDS \ - 76, /* /zephyr,user */ \ - 90, /* /leds */ \ - 93, /* /leds/led_2 */ + 87, /* /zephyr,user */ \ + 101, /* /leds */ \ + 104, /* /leds/led_2 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_EXISTS 1 @@ -9050,6 +9909,127 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_zephyr_deferred_init_EXISTS 1 +/* + * Devicetree node: /soc/pin-controller@58020000/gpio@58021800 + * + * Node identifier: DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800 + * + * Binding (compatible = st,stm32-gpio): + * $ZEPHYR_BASE/dts/bindings/gpio/st,stm32-gpio.yaml + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_PATH "/soc/pin-controller@58020000/gpio@58021800" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FULL_NAME "gpio@58021800" + +/* Node parent (/soc/pin-controller@58020000) identifier: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_PARENT DT_N_S_soc_S_pin_controller_58020000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_CHILD_IDX 6 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_NODELABEL_NUM 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FOREACH_NODELABEL(fn) fn(gpiog) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpiog, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_CHILD_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_ORD 74 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_ORD_STR_SORTABLE 00074 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_REQUIRES_ORDS \ + 9, /* /soc/rcc@58024400 */ \ + 10, /* /soc/pin-controller@58020000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_SUPPORTS_ORDS \ + 87, /* /zephyr,user */ \ + 248, /* /soc/serial@40007800/bt_hci_uart/murata-1dx */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_EXISTS 1 +#define DT_N_INST_6_st_stm32_gpio DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800 +#define DT_N_NODELABEL_gpiog DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_REG_NUM 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_REG_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_REG_IDX_0_VAL_ADDRESS 1476532224 /* 0x58021800 */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_RANGES_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_IRQ_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_IRQ_LEVEL 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_COMPAT_MATCHES_st_stm32_gpio 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_COMPAT_VENDOR_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_COMPAT_VENDOR_IDX_0 "STMicroelectronics" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_COMPAT_MODEL_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_COMPAT_MODEL_IDX_0 "stm32-gpio" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_gpio_controller 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_gpio_controller_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_ngpios 32 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_ngpios_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_wakeup_source 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible {"st,stm32-gpio"} +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_IDX_0 "st,stm32-gpio" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_reg {1476532224 /* 0x58021800 */, 1024 /* 0x400 */} +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_reg_IDX_0 1476532224 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_reg_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_IDX_0_VAL_bus 224 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_IDX_0_VAL_bits 64 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, clocks, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, clocks, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_zephyr_deferred_init_EXISTS 1 + /* * Devicetree node: /soc/pin-controller@58020000/gpio@58021C00 * @@ -9092,18 +10072,18 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_ORD 67 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_ORD_STR_SORTABLE 00067 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_ORD 75 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_ORD_STR_SORTABLE 00075 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_REQUIRES_ORDS \ 9, /* /soc/rcc@58024400 */ \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_SUPPORTS_ORDS \ - 76, /* /zephyr,user */ \ - 215, /* /soc/serial@40007800/bt_hci_uart/murata-1dx */ + 87, /* /zephyr,user */ \ + 248, /* /soc/serial@40007800/bt_hci_uart/murata-1dx */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_EXISTS 1 @@ -9213,19 +10193,19 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_ORD 68 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_ORD_STR_SORTABLE 00068 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_ORD 76 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_ORD_STR_SORTABLE 00076 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_REQUIRES_ORDS \ 9, /* /soc/rcc@58024400 */ \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_SUPPORTS_ORDS \ - 76, /* /zephyr,user */ \ - 90, /* /leds */ \ - 91, /* /leds/led_0 */ + 87, /* /zephyr,user */ \ + 101, /* /leds */ \ + 102, /* /leds/led_0 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_EXISTS 1 @@ -9335,19 +10315,19 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_ORD 69 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_ORD_STR_SORTABLE 00069 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_ORD 77 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_ORD_STR_SORTABLE 00077 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_REQUIRES_ORDS \ 9, /* /soc/rcc@58024400 */ \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_SUPPORTS_ORDS \ - 76, /* /zephyr,user */ \ - 90, /* /leds */ \ - 92, /* /leds/led_1 */ + 87, /* /zephyr,user */ \ + 101, /* /leds */ \ + 103, /* /leds/led_1 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_EXISTS 1 @@ -9457,17 +10437,17 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_ORD 70 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_ORD_STR_SORTABLE 00070 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_ORD 78 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_ORD_STR_SORTABLE 00078 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_REQUIRES_ORDS \ 9, /* /soc/rcc@58024400 */ \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_SUPPORTS_ORDS \ - 76, /* /zephyr,user */ + 87, /* /zephyr,user */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_EXISTS 1 @@ -9535,6 +10515,499 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_zephyr_deferred_init_EXISTS 1 +/* + * Devicetree node: /soc/timers@40010000 + * + * Node identifier: DT_N_S_soc_S_timers_40010000 + * + * Binding (compatible = st,stm32-timers): + * $ZEPHYR_BASE/dts/bindings/timer/st,stm32-timers.yaml + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_timers_40010000_PATH "/soc/timers@40010000" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_timers_40010000_FULL_NAME "timers@40010000" + +/* Node parent (/soc) identifier: */ +#define DT_N_S_soc_S_timers_40010000_PARENT DT_N_S_soc + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_timers_40010000_CHILD_IDX 33 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_timers_40010000_NODELABEL_NUM 1 +#define DT_N_S_soc_S_timers_40010000_FOREACH_NODELABEL(fn) fn(timers1) +#define DT_N_S_soc_S_timers_40010000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers1, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_timers_40010000_CHILD_NUM 1 +#define DT_N_S_soc_S_timers_40010000_CHILD_NUM_STATUS_OKAY 1 +#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm) +#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm) +#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm) +#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm) +#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, __VA_ARGS__) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_timers_40010000_ORD 79 +#define DT_N_S_soc_S_timers_40010000_ORD_STR_SORTABLE 00079 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_timers_40010000_REQUIRES_ORDS \ + 4, /* /soc */ \ + 5, /* /soc/interrupt-controller@e000e100 */ \ + 9, /* /soc/rcc@58024400 */ \ + 54, /* /soc/rcc@58024400/reset-controller */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_timers_40010000_SUPPORTS_ORDS \ + 81, /* /soc/timers@40010000/pwm */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_timers_40010000_EXISTS 1 +#define DT_N_INST_0_st_stm32_timers DT_N_S_soc_S_timers_40010000 +#define DT_N_NODELABEL_timers1 DT_N_S_soc_S_timers_40010000 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_timers_40010000_REG_NUM 1 +#define DT_N_S_soc_S_timers_40010000_REG_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_REG_IDX_0_VAL_ADDRESS 1073807360 /* 0x40010000 */ +#define DT_N_S_soc_S_timers_40010000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_timers_40010000_RANGES_NUM 0 +#define DT_N_S_soc_S_timers_40010000_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_timers_40010000_IRQ_NUM 4 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_VAL_irq 24 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_VAL_irq_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_VAL_priority 0 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_VAL_priority_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_VAL_irq 25 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_VAL_irq_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_VAL_priority 0 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_VAL_priority_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_VAL_irq 26 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_VAL_irq_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_VAL_priority 0 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_VAL_priority_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_VAL_irq 27 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_VAL_irq_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_VAL_priority 0 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_VAL_priority_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 +#define DT_N_S_soc_S_timers_40010000_IRQ_LEVEL 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_brk_VAL_irq DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_VAL_irq +#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_brk_VAL_irq_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_brk_VAL_priority DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_VAL_priority +#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_brk_VAL_priority_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_brk_CONTROLLER DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_CONTROLLER +#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_up_VAL_irq DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_VAL_irq +#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_up_VAL_irq_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_up_VAL_priority DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_VAL_priority +#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_up_VAL_priority_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_up_CONTROLLER DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_CONTROLLER +#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_trgcom_VAL_irq DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_VAL_irq +#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_trgcom_VAL_irq_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_trgcom_VAL_priority DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_VAL_priority +#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_trgcom_VAL_priority_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_trgcom_CONTROLLER DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_CONTROLLER +#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_cc_VAL_irq DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_VAL_irq +#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_cc_VAL_irq_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_cc_VAL_priority DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_VAL_priority +#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_cc_VAL_priority_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_cc_CONTROLLER DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_CONTROLLER +#define DT_N_S_soc_S_timers_40010000_COMPAT_MATCHES_st_stm32_timers 1 +#define DT_N_S_soc_S_timers_40010000_COMPAT_VENDOR_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_COMPAT_VENDOR_IDX_0 "STMicroelectronics" +#define DT_N_S_soc_S_timers_40010000_COMPAT_MODEL_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_COMPAT_MODEL_IDX_0 "stm32-timers" +#define DT_N_S_soc_S_timers_40010000_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_timers_40010000_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_timers_40010000_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40010000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40010000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_status "okay" +#define DT_N_S_soc_S_timers_40010000_P_status_STRING_UNQUOTED okay +#define DT_N_S_soc_S_timers_40010000_P_status_STRING_TOKEN okay +#define DT_N_S_soc_S_timers_40010000_P_status_STRING_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_timers_40010000_P_status_IDX_0 "okay" +#define DT_N_S_soc_S_timers_40010000_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_status_ENUM_IDX 1 +#define DT_N_S_soc_S_timers_40010000_P_status_ENUM_VAL_okay_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_status_ENUM_TOKEN okay +#define DT_N_S_soc_S_timers_40010000_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_timers_40010000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, status, 0) +#define DT_N_S_soc_S_timers_40010000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, status, 0) +#define DT_N_S_soc_S_timers_40010000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_P_status_LEN 1 +#define DT_N_S_soc_S_timers_40010000_P_status_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_compatible {"st,stm32-timers"} +#define DT_N_S_soc_S_timers_40010000_P_compatible_IDX_0 "st,stm32-timers" +#define DT_N_S_soc_S_timers_40010000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers +#define DT_N_S_soc_S_timers_40010000_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers +#define DT_N_S_soc_S_timers_40010000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS +#define DT_N_S_soc_S_timers_40010000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, compatible, 0) +#define DT_N_S_soc_S_timers_40010000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, compatible, 0) +#define DT_N_S_soc_S_timers_40010000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_P_compatible_LEN 1 +#define DT_N_S_soc_S_timers_40010000_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_reg {1073807360 /* 0x40010000 */, 1024 /* 0x400 */} +#define DT_N_S_soc_S_timers_40010000_P_reg_IDX_0 1073807360 +#define DT_N_S_soc_S_timers_40010000_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_timers_40010000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_reg_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_interrupts {24 /* 0x18 */, 0 /* 0x0 */, 25 /* 0x19 */, 0 /* 0x0 */, 26 /* 0x1a */, 0 /* 0x0 */, 27 /* 0x1b */, 0 /* 0x0 */} +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_0 24 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_2 25 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_3 0 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_4 26 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_4_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_5 0 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_5_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_6 27 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_6_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_7 0 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_7_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names {"brk", "up", "trgcom", "cc"} +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_0 "brk" +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_0_STRING_UNQUOTED brk +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_0_STRING_TOKEN brk +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN BRK +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_1 "up" +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_1_STRING_UNQUOTED up +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_1_STRING_TOKEN up +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN UP +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_2 "trgcom" +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_2_STRING_UNQUOTED trgcom +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_2_STRING_TOKEN trgcom +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_2_STRING_UPPER_TOKEN TRGCOM +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_3 "cc" +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_3_STRING_UNQUOTED cc +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_3_STRING_TOKEN cc +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_3_STRING_UPPER_TOKEN CC +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 0) \ + fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 1) \ + fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 2) \ + fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 3) +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 1) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 2) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 3) +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 1, __VA_ARGS__) \ + fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 2, __VA_ARGS__) \ + fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 3, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 3, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_LEN 4 +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_VAL_bus 240 +#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_VAL_bits 1 +#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, clocks, 0) +#define DT_N_S_soc_S_timers_40010000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, clocks, 0) +#define DT_N_S_soc_S_timers_40010000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_P_clocks_LEN 1 +#define DT_N_S_soc_S_timers_40010000_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_timers_40010000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_resets_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller +#define DT_N_S_soc_S_timers_40010000_P_resets_IDX_0_VAL_id 4864 +#define DT_N_S_soc_S_timers_40010000_P_resets_IDX_0_VAL_id_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, resets, 0) +#define DT_N_S_soc_S_timers_40010000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, resets, 0) +#define DT_N_S_soc_S_timers_40010000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_P_resets_LEN 1 +#define DT_N_S_soc_S_timers_40010000_P_resets_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_st_prescaler 0 +#define DT_N_S_soc_S_timers_40010000_P_st_prescaler_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_st_countermode 0 +#define DT_N_S_soc_S_timers_40010000_P_st_countermode_EXISTS 1 + +/* + * Devicetree node: /soc/pin-controller@58020000/tim1_ch3_pj9 + * + * Node identifier: DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9 + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_PATH "/soc/pin-controller@58020000/tim1_ch3_pj9" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_FULL_NAME "tim1_ch3_pj9" + +/* Node parent (/soc/pin-controller@58020000) identifier: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_PARENT DT_N_S_soc_S_pin_controller_58020000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_CHILD_IDX 99 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_NODELABEL_NUM 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_FOREACH_NODELABEL(fn) fn(tim1_ch3_pj9) +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_FOREACH_NODELABEL_VARGS(fn, ...) fn(tim1_ch3_pj9, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_CHILD_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_ORD 80 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_ORD_STR_SORTABLE 00080 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_REQUIRES_ORDS \ + 10, /* /soc/pin-controller@58020000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_SUPPORTS_ORDS \ + 81, /* /soc/timers@40010000/pwm */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_EXISTS 1 +#define DT_N_NODELABEL_tim1_ch3_pj9 DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_REG_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_RANGES_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_IRQ_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_IRQ_LEVEL 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_output_high_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_pinmux 4897 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_pinmux_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate "low-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_STRING_UNQUOTED low-speed +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_STRING_TOKEN low_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_IDX_0 "low-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_ENUM_TOKEN low_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_EXISTS 1 + +/* + * Devicetree node: /soc/timers@40010000/pwm + * + * Node identifier: DT_N_S_soc_S_timers_40010000_S_pwm + * + * Binding (compatible = st,stm32-pwm): + * $ZEPHYR_BASE/dts/bindings/pwm/st,stm32-pwm.yaml + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_timers_40010000_S_pwm_PATH "/soc/timers@40010000/pwm" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_timers_40010000_S_pwm_FULL_NAME "pwm" + +/* Node parent (/soc/timers@40010000) identifier: */ +#define DT_N_S_soc_S_timers_40010000_S_pwm_PARENT DT_N_S_soc_S_timers_40010000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_timers_40010000_S_pwm_CHILD_IDX 0 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_timers_40010000_S_pwm_NODELABEL_NUM 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_NODELABEL(fn) fn(cam_clock_pwm) +#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_NODELABEL_VARGS(fn, ...) fn(cam_clock_pwm, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_timers_40010000_S_pwm_CHILD_NUM 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_CHILD_NUM_STATUS_OKAY 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock) +#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock) +#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock) +#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock) +#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, __VA_ARGS__) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_timers_40010000_S_pwm_ORD 81 +#define DT_N_S_soc_S_timers_40010000_S_pwm_ORD_STR_SORTABLE 00081 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_timers_40010000_S_pwm_REQUIRES_ORDS \ + 79, /* /soc/timers@40010000 */ \ + 80, /* /soc/pin-controller@58020000/tim1_ch3_pj9 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_timers_40010000_S_pwm_SUPPORTS_ORDS \ + 87, /* /zephyr,user */ \ + 274, /* /soc/timers@40010000/pwm/pwmclock */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_timers_40010000_S_pwm_EXISTS 1 +#define DT_N_INST_0_st_stm32_pwm DT_N_S_soc_S_timers_40010000_S_pwm +#define DT_N_NODELABEL_cam_clock_pwm DT_N_S_soc_S_timers_40010000_S_pwm + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_timers_40010000_S_pwm_REG_NUM 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_RANGES_NUM 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_timers_40010000_S_pwm_IRQ_NUM 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_IRQ_LEVEL 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_COMPAT_MATCHES_st_stm32_pwm 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_COMPAT_VENDOR_IDX_0 "STMicroelectronics" +#define DT_N_S_soc_S_timers_40010000_S_pwm_COMPAT_MODEL_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_COMPAT_MODEL_IDX_0 "stm32-pwm" +#define DT_N_S_soc_S_timers_40010000_S_pwm_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_timers_40010000_S_pwm_PINCTRL_NUM 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_PINCTRL_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_PINCTRL_IDX_0_TOKEN default +#define DT_N_S_soc_S_timers_40010000_S_pwm_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT +#define DT_N_S_soc_S_timers_40010000_S_pwm_PINCTRL_NAME_default_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_PINCTRL_NAME_default_IDX 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_PINCTRL_NAME_default_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9 + +/* Generic property macros: */ +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status "okay" +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_STRING_UNQUOTED okay +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_STRING_TOKEN okay +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_STRING_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_IDX_0 "okay" +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_ENUM_IDX 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_ENUM_VAL_okay_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_ENUM_TOKEN okay +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm, status, 0) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm, status, 0) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_LEN 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible {"st,stm32-pwm"} +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_IDX_0 "st,stm32-pwm" +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm, compatible, 0) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm, compatible, 0) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_LEN 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_0, 0) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_0, 0) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_0, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_0, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_LEN 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names {"default"} +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_IDX_0 "default" +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_IDX_0_STRING_UNQUOTED default +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_IDX_0_STRING_TOKEN default +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_names, 0) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_names, 0) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_LEN 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_four_channel_capture_support 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_four_channel_capture_support_EXISTS 1 + /* * Devicetree node: /otghs_fs_phy * @@ -9577,8 +11050,8 @@ #define DT_N_S_otghs_fs_phy_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_otghs_fs_phy_ORD 71 -#define DT_N_S_otghs_fs_phy_ORD_STR_SORTABLE 00071 +#define DT_N_S_otghs_fs_phy_ORD 82 +#define DT_N_S_otghs_fs_phy_ORD_STR_SORTABLE 00082 /* Ordinals for what this node depends on directly: */ #define DT_N_S_otghs_fs_phy_REQUIRES_ORDS \ @@ -9586,8 +11059,8 @@ /* Ordinals for what depends directly on this node: */ #define DT_N_S_otghs_fs_phy_SUPPORTS_ORDS \ - 74, /* /soc/usb@40080000 */ \ - 134, /* /soc/usb@40040000 */ + 85, /* /soc/usb@40080000 */ \ + 143, /* /soc/usb@40040000 */ /* Existence and alternate IDs: */ #define DT_N_S_otghs_fs_phy_EXISTS 1 @@ -9645,7 +11118,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_CHILD_IDX 92 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_CHILD_IDX 110 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_NODELABEL_NUM 1 @@ -9665,16 +11138,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_ORD 72 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_ORD_STR_SORTABLE 00072 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_ORD 83 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_ORD_STR_SORTABLE 00083 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_SUPPORTS_ORDS \ - 74, /* /soc/usb@40080000 */ + 85, /* /soc/usb@40080000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_EXISTS 1 @@ -9744,7 +11217,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_CHILD_IDX 93 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_CHILD_IDX 111 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_NODELABEL_NUM 1 @@ -9764,16 +11237,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_ORD 73 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_ORD_STR_SORTABLE 00073 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_ORD 84 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_ORD_STR_SORTABLE 00084 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_SUPPORTS_ORDS \ - 74, /* /soc/usb@40080000 */ + 85, /* /soc/usb@40080000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_EXISTS 1 @@ -9866,21 +11339,21 @@ #define DT_N_S_soc_S_usb_40080000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_usb_40080000_ORD 74 -#define DT_N_S_soc_S_usb_40080000_ORD_STR_SORTABLE 00074 +#define DT_N_S_soc_S_usb_40080000_ORD 85 +#define DT_N_S_soc_S_usb_40080000_ORD_STR_SORTABLE 00085 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_usb_40080000_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 71, /* /otghs_fs_phy */ \ - 72, /* /soc/pin-controller@58020000/usb_otg_fs_dm_pa11 */ \ - 73, /* /soc/pin-controller@58020000/usb_otg_fs_dp_pa12 */ + 82, /* /otghs_fs_phy */ \ + 83, /* /soc/pin-controller@58020000/usb_otg_fs_dm_pa11 */ \ + 84, /* /soc/pin-controller@58020000/usb_otg_fs_dp_pa12 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_usb_40080000_SUPPORTS_ORDS \ - 75, /* /soc/usb@40080000/cdc_acm_uart0 */ + 86, /* /soc/usb@40080000/cdc_acm_uart0 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_usb_40080000_EXISTS 1 @@ -10183,16 +11656,16 @@ #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_ORD 75 -#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_ORD_STR_SORTABLE 00075 +#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_ORD 86 +#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_ORD_STR_SORTABLE 00086 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_REQUIRES_ORDS \ - 74, /* /soc/usb@40080000 */ + 85, /* /soc/usb@40080000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_SUPPORTS_ORDS \ - 76, /* /zephyr,user */ + 87, /* /zephyr,user */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_EXISTS 1 @@ -10280,7 +11753,7 @@ #define DT_N_S_zephyr_user_PARENT DT_N /* Node's index in its parent's list of children: */ -#define DT_N_S_zephyr_user_CHILD_IDX 23 +#define DT_N_S_zephyr_user_CHILD_IDX 24 /* Helpers for dealing with node labels: */ #define DT_N_S_zephyr_user_NODELABEL_NUM 0 @@ -10300,28 +11773,32 @@ #define DT_N_S_zephyr_user_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_zephyr_user_ORD 76 -#define DT_N_S_zephyr_user_ORD_STR_SORTABLE 00076 +#define DT_N_S_zephyr_user_ORD 87 +#define DT_N_S_zephyr_user_ORD_STR_SORTABLE 00087 /* Ordinals for what this node depends on directly: */ #define DT_N_S_zephyr_user_REQUIRES_ORDS \ 0, /* / */ \ - 32, /* /soc/i2c@58001c00 */ \ - 44, /* /soc/adc@40022000 */ \ - 48, /* /soc/serial@40011000 */ \ - 51, /* /soc/serial@40011400 */ \ - 56, /* /soc/spi@40013000 */ \ - 61, /* /soc/spi@40015000 */ \ - 62, /* /soc/pin-controller@58020000/gpio@58020000 */ \ - 63, /* /soc/pin-controller@58020000/gpio@58020400 */ \ - 64, /* /soc/pin-controller@58020000/gpio@58020800 */ \ - 65, /* /soc/pin-controller@58020000/gpio@58020C00 */ \ - 66, /* /soc/pin-controller@58020000/gpio@58021000 */ \ - 67, /* /soc/pin-controller@58020000/gpio@58021C00 */ \ - 68, /* /soc/pin-controller@58020000/gpio@58022000 */ \ - 69, /* /soc/pin-controller@58020000/gpio@58022400 */ \ - 70, /* /soc/pin-controller@58020000/gpio@58022800 */ \ - 75, /* /soc/usb@40080000/cdc_acm_uart0 */ + 13, /* /soc/adc@58026000 */ \ + 34, /* /soc/i2c@58001c00 */ \ + 38, /* /gpio@deadbeef */ \ + 51, /* /soc/adc@40022000 */ \ + 55, /* /soc/serial@40011000 */ \ + 58, /* /soc/serial@40011400 */ \ + 63, /* /soc/spi@40013000 */ \ + 68, /* /soc/spi@40015000 */ \ + 69, /* /soc/pin-controller@58020000/gpio@58020000 */ \ + 70, /* /soc/pin-controller@58020000/gpio@58020400 */ \ + 71, /* /soc/pin-controller@58020000/gpio@58020800 */ \ + 72, /* /soc/pin-controller@58020000/gpio@58020C00 */ \ + 73, /* /soc/pin-controller@58020000/gpio@58021000 */ \ + 74, /* /soc/pin-controller@58020000/gpio@58021800 */ \ + 75, /* /soc/pin-controller@58020000/gpio@58021C00 */ \ + 76, /* /soc/pin-controller@58020000/gpio@58022000 */ \ + 77, /* /soc/pin-controller@58020000/gpio@58022400 */ \ + 78, /* /soc/pin-controller@58020000/gpio@58022800 */ \ + 81, /* /soc/timers@40010000/pwm */ \ + 86, /* /soc/usb@40080000/cdc_acm_uart0 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_zephyr_user_SUPPORTS_ORDS /* nothing */ @@ -10426,83 +11903,503 @@ #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_13_VAL_flags 0 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_13_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_14_EXISTS 1 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_14_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_14_VAL_pin 12 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_14_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_14_VAL_pin 14 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_14_VAL_pin_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_14_VAL_flags 0 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_14_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_15_EXISTS 1 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_15_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_15_VAL_pin 6 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_15_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_15_VAL_pin 7 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_15_VAL_pin_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_15_VAL_flags 0 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_15_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_16_EXISTS 1 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_16_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_16_VAL_pin 4 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_16_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_16_VAL_pin 13 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_16_VAL_pin_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_16_VAL_flags 0 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_16_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_17_EXISTS 1 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_17_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_17_VAL_pin 5 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_17_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_17_VAL_pin 9 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_17_VAL_pin_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_17_VAL_flags 0 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_17_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_18_EXISTS 1 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_18_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_18_VAL_pin 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_18_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_18_VAL_pin 5 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_18_VAL_pin_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_18_VAL_flags 0 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_18_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_19_EXISTS 1 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_19_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_19_VAL_pin 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_19_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_19_VAL_pin 6 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_19_VAL_pin_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_19_VAL_flags 0 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_19_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_20_EXISTS 1 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_20_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_20_VAL_pin 3 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_20_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_20_VAL_pin 11 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_20_VAL_pin_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_20_VAL_flags 0 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_20_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_21_EXISTS 1 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_21_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_21_VAL_pin 2 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_21_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_21_VAL_pin 4 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_21_VAL_pin_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_21_VAL_flags 0 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_21_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_22_EXISTS 1 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_22_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_22_VAL_pin 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_22_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_22_VAL_pin 12 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_22_VAL_pin_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_22_VAL_flags 0 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_22_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_23_EXISTS 1 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_23_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_23_VAL_pin 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_23_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_23_VAL_pin 13 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_23_VAL_pin_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_23_VAL_flags 0 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_23_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_24_EXISTS 1 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_24_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_24_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_24_VAL_pin 12 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_24_VAL_pin_EXISTS 1 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_24_VAL_flags 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_24_VAL_flags 0 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_24_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_25_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_25_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_25_VAL_pin 13 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_25_VAL_pin 0 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_25_VAL_pin_EXISTS 1 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_25_VAL_flags 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_25_VAL_flags 0 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_25_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_26_EXISTS 1 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_26_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_26_VAL_pin 3 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_26_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_26_VAL_pin 14 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_26_VAL_pin_EXISTS 1 -#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_26_VAL_flags 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_26_VAL_flags 0 #define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_26_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_27_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_27_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_27_VAL_pin 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_27_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_27_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_27_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_28_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_28_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_28_VAL_pin 15 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_28_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_28_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_28_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_29_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_29_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_29_VAL_pin 2 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_29_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_29_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_29_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_30_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_30_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_30_VAL_pin 3 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_30_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_30_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_30_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_31_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_31_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_31_VAL_pin 3 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_31_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_31_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_31_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_32_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_32_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_32_VAL_pin 4 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_32_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_32_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_32_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_33_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_33_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_33_VAL_pin 4 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_33_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_33_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_33_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_34_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_34_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_34_VAL_pin 5 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_34_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_34_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_34_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_35_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_35_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_35_VAL_pin 5 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_35_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_35_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_35_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_36_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_36_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_36_VAL_pin 6 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_36_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_36_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_36_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_37_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_37_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_37_VAL_pin 6 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_37_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_37_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_37_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_38_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_38_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_38_VAL_pin 7 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_38_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_38_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_38_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_39_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_39_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_39_VAL_pin 14 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_39_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_39_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_39_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_40_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_40_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_40_VAL_pin 6 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_40_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_40_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_40_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_41_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_41_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_41_VAL_pin 7 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_41_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_41_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_41_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_42_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_42_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_42_VAL_pin 15 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_42_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_42_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_42_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_43_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_43_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_43_VAL_pin 10 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_43_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_43_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_43_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_44_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_44_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_44_VAL_pin 10 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_44_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_44_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_44_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_45_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_45_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_45_VAL_pin 13 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_45_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_45_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_45_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_46_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_46_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_46_VAL_pin 15 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_46_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_46_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_46_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_47_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_47_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_47_VAL_pin 2 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_47_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_47_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_47_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_48_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_48_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_48_VAL_pin 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_48_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_48_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_48_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_49_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_49_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_49_VAL_pin 4 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_49_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_49_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_49_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_50_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_50_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_50_VAL_pin 11 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_50_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_50_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_50_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_51_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_51_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_51_VAL_pin 5 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_51_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_51_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_51_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_52_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_52_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_52_VAL_pin 2 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_52_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_52_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_52_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_53_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_53_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_53_VAL_pin 7 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_53_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_53_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_53_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_54_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_54_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_54_VAL_pin 5 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_54_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_54_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_54_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_55_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_55_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_55_VAL_pin 8 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_55_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_55_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_55_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_56_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_56_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_56_VAL_pin 6 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_56_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_56_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_56_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_57_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_57_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_57_VAL_pin 9 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_57_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_57_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_57_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_58_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_58_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_58_VAL_pin 7 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_58_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_58_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_58_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_59_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_59_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_59_VAL_pin 6 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_59_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_59_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_59_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_60_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_60_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_60_VAL_pin 4 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_60_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_60_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_60_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_61_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_61_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_61_VAL_pin 14 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_61_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_61_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_61_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_62_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_62_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_62_VAL_pin 11 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_62_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_62_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_62_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_63_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_63_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_63_VAL_pin 11 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_63_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_63_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_63_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_64_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_64_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_64_VAL_pin 10 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_64_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_64_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_64_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_65_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_65_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_65_VAL_pin 9 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_65_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_65_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_65_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_66_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_66_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_66_VAL_pin 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_66_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_66_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_66_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_67_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_67_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_67_VAL_pin 4 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_67_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_67_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_67_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_68_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_68_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_68_VAL_pin 6 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_68_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_68_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_68_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_69_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_69_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_69_VAL_pin 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_69_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_69_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_69_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_70_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_70_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_70_VAL_pin 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_70_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_70_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_70_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_71_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_71_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_71_VAL_pin 2 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_71_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_71_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_71_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_72_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_72_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_72_VAL_pin 3 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_72_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_72_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_72_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_73_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_73_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_73_VAL_pin 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_73_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_73_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_73_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_74_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_74_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_74_VAL_pin 12 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_74_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_74_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_74_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_75_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_75_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_75_VAL_pin 3 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_75_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_75_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_75_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_76_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_76_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_76_VAL_pin 6 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_76_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_76_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_76_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_77_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_77_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_77_VAL_pin 12 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_77_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_77_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_77_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_78_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_78_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_78_VAL_pin 4 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_78_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_78_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_78_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_79_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_79_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_79_VAL_pin 5 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_79_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_79_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_79_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_80_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_80_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_80_VAL_pin 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_80_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_80_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_80_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_81_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_81_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_81_VAL_pin 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_81_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_81_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_81_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_82_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_82_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_82_VAL_pin 3 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_82_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_82_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_82_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_83_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_83_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_83_VAL_pin 2 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_83_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_83_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_83_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_84_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_84_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_84_VAL_pin 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_84_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_84_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_84_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_85_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_85_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_85_VAL_pin 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_85_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_85_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_85_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_86_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_86_PH DT_N_S_gpio_deadbeef +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_86_VAL_pin 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_86_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_86_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_86_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_87_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_87_PH DT_N_S_gpio_deadbeef +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_87_VAL_pin 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_87_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_87_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_87_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_88_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_88_PH DT_N_S_gpio_deadbeef +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_88_VAL_pin 2 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_88_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_88_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_88_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_89_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_89_PH DT_N_S_gpio_deadbeef +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_89_VAL_pin 3 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_89_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_89_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_89_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_90_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_90_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_90_VAL_pin 4 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_90_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_90_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_90_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_91_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_91_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_91_VAL_pin 5 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_91_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_91_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_91_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_92_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_92_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_92_VAL_pin 5 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_92_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_92_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_92_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_93_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_93_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_93_VAL_pin 13 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_93_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_93_VAL_flags 0 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_93_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_94_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_94_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_94_VAL_pin 12 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_94_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_94_VAL_flags 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_94_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_95_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_95_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_95_VAL_pin 13 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_95_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_95_VAL_flags 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_95_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_96_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_96_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_96_VAL_pin 3 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_96_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_96_VAL_flags 1 +#define DT_N_S_zephyr_user_P_digital_pin_gpios_IDX_96_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_digital_pin_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_zephyr_user, digital_pin_gpios, 0) \ fn(DT_N_S_zephyr_user, digital_pin_gpios, 1) \ fn(DT_N_S_zephyr_user, digital_pin_gpios, 2) \ @@ -10529,7 +12426,77 @@ fn(DT_N_S_zephyr_user, digital_pin_gpios, 23) \ fn(DT_N_S_zephyr_user, digital_pin_gpios, 24) \ fn(DT_N_S_zephyr_user, digital_pin_gpios, 25) \ - fn(DT_N_S_zephyr_user, digital_pin_gpios, 26) + fn(DT_N_S_zephyr_user, digital_pin_gpios, 26) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 27) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 28) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 29) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 30) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 31) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 32) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 33) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 34) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 35) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 36) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 37) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 38) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 39) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 40) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 41) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 42) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 43) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 44) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 45) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 46) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 47) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 48) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 49) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 50) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 51) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 52) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 53) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 54) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 55) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 56) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 57) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 58) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 59) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 60) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 61) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 62) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 63) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 64) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 65) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 66) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 67) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 68) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 69) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 70) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 71) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 72) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 73) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 74) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 75) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 76) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 77) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 78) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 79) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 80) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 81) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 82) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 83) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 84) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 85) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 86) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 87) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 88) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 89) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 90) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 91) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 92) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 93) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 94) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 95) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 96) #define DT_N_S_zephyr_user_P_digital_pin_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_zephyr_user, digital_pin_gpios, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, digital_pin_gpios, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, digital_pin_gpios, 2) DT_DEBRACKET_INTERNAL sep \ @@ -10556,7 +12523,77 @@ fn(DT_N_S_zephyr_user, digital_pin_gpios, 23) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, digital_pin_gpios, 24) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, digital_pin_gpios, 25) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_zephyr_user, digital_pin_gpios, 26) + fn(DT_N_S_zephyr_user, digital_pin_gpios, 26) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 27) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 28) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 29) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 30) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 31) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 32) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 33) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 34) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 35) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 36) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 37) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 38) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 39) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 40) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 41) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 42) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 43) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 44) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 45) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 46) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 47) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 48) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 49) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 50) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 51) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 52) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 53) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 54) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 55) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 56) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 57) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 58) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 59) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 60) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 61) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 62) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 63) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 64) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 65) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 66) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 67) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 68) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 69) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 70) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 71) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 72) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 73) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 74) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 75) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 76) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 77) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 78) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 79) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 80) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 81) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 82) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 83) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 84) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 85) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 86) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 87) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 88) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 89) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 90) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 91) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 92) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 93) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 94) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 95) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 96) #define DT_N_S_zephyr_user_P_digital_pin_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_zephyr_user, digital_pin_gpios, 0, __VA_ARGS__) \ fn(DT_N_S_zephyr_user, digital_pin_gpios, 1, __VA_ARGS__) \ fn(DT_N_S_zephyr_user, digital_pin_gpios, 2, __VA_ARGS__) \ @@ -10583,7 +12620,77 @@ fn(DT_N_S_zephyr_user, digital_pin_gpios, 23, __VA_ARGS__) \ fn(DT_N_S_zephyr_user, digital_pin_gpios, 24, __VA_ARGS__) \ fn(DT_N_S_zephyr_user, digital_pin_gpios, 25, __VA_ARGS__) \ - fn(DT_N_S_zephyr_user, digital_pin_gpios, 26, __VA_ARGS__) + fn(DT_N_S_zephyr_user, digital_pin_gpios, 26, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 27, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 28, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 29, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 30, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 31, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 32, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 33, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 34, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 35, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 36, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 37, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 38, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 39, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 40, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 41, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 42, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 43, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 44, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 45, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 46, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 47, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 48, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 49, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 50, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 51, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 52, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 53, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 54, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 55, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 56, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 57, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 58, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 59, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 60, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 61, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 62, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 63, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 64, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 65, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 66, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 67, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 68, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 69, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 70, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 71, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 72, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 73, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 74, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 75, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 76, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 77, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 78, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 79, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 80, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 81, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 82, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 83, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 84, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 85, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 86, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 87, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 88, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 89, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 90, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 91, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 92, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 93, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 94, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 95, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 96, __VA_ARGS__) #define DT_N_S_zephyr_user_P_digital_pin_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_zephyr_user, digital_pin_gpios, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, digital_pin_gpios, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, digital_pin_gpios, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ @@ -10610,8 +12717,78 @@ fn(DT_N_S_zephyr_user, digital_pin_gpios, 23, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, digital_pin_gpios, 24, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, digital_pin_gpios, 25, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_zephyr_user, digital_pin_gpios, 26, __VA_ARGS__) -#define DT_N_S_zephyr_user_P_digital_pin_gpios_LEN 27 + fn(DT_N_S_zephyr_user, digital_pin_gpios, 26, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 27, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 28, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 29, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 30, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 31, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 32, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 33, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 34, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 35, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 36, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 37, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 38, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 39, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 40, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 41, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 42, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 43, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 44, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 45, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 46, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 47, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 48, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 49, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 50, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 51, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 52, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 53, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 54, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 55, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 56, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 57, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 58, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 59, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 60, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 61, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 62, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 63, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 64, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 65, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 66, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 67, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 68, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 69, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 70, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 71, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 72, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 73, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 74, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 75, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 76, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 77, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 78, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 79, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 80, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 81, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 82, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 83, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 84, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 85, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 86, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 87, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 88, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 89, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 90, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 91, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 92, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 93, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 94, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 95, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, digital_pin_gpios, 96, __VA_ARGS__) +#define DT_N_S_zephyr_user_P_digital_pin_gpios_LEN 97 #define DT_N_S_zephyr_user_P_digital_pin_gpios_EXISTS 1 #define DT_N_S_zephyr_user_P_builtin_led_gpios_IDX_0_EXISTS 1 #define DT_N_S_zephyr_user_P_builtin_led_gpios_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000 @@ -10646,53 +12823,59 @@ #define DT_N_S_zephyr_user_P_builtin_led_gpios_LEN 3 #define DT_N_S_zephyr_user_P_builtin_led_gpios_EXISTS 1 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_0_EXISTS 1 -#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400 -#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_0_VAL_pin 7 +#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400 +#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_0_VAL_pin 9 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_0_VAL_pin_EXISTS 1 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_0_VAL_flags 0 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_0_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_1_EXISTS 1 -#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800 -#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_1_VAL_pin 2 +#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400 +#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_1_VAL_pin 7 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_1_VAL_pin_EXISTS 1 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_1_VAL_flags 0 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_1_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_2_EXISTS 1 -#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_2_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400 -#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_2_VAL_pin 10 +#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_2_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800 +#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_2_VAL_pin 2 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_2_VAL_pin_EXISTS 1 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_2_VAL_flags 0 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_2_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_3_EXISTS 1 -#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_3_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00 -#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_3_VAL_pin 13 +#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_3_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400 +#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_3_VAL_pin 10 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_3_VAL_pin_EXISTS 1 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_3_VAL_flags 0 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_3_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_4_EXISTS 1 -#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_4_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400 -#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_4_VAL_pin 0 +#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_4_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00 +#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_4_VAL_pin 13 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_4_VAL_pin_EXISTS 1 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_4_VAL_flags 0 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_4_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_5_EXISTS 1 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_5_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400 -#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_5_VAL_pin 1 +#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_5_VAL_pin 0 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_5_VAL_pin_EXISTS 1 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_5_VAL_flags 0 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_5_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_6_EXISTS 1 -#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_6_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000 -#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_6_VAL_pin 2 +#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_6_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400 +#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_6_VAL_pin 1 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_6_VAL_pin_EXISTS 1 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_6_VAL_flags 0 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_6_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_7_EXISTS 1 -#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_7_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400 -#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_7_VAL_pin 8 +#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_7_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000 +#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_7_VAL_pin 2 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_7_VAL_pin_EXISTS 1 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_7_VAL_flags 0 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_7_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_8_EXISTS 1 +#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_8_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400 +#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_8_VAL_pin 8 +#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_8_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_8_VAL_flags 0 +#define DT_N_S_zephyr_user_P_pwm_pin_gpios_IDX_8_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_zephyr_user, pwm_pin_gpios, 0) \ fn(DT_N_S_zephyr_user, pwm_pin_gpios, 1) \ fn(DT_N_S_zephyr_user, pwm_pin_gpios, 2) \ @@ -10700,7 +12883,8 @@ fn(DT_N_S_zephyr_user, pwm_pin_gpios, 4) \ fn(DT_N_S_zephyr_user, pwm_pin_gpios, 5) \ fn(DT_N_S_zephyr_user, pwm_pin_gpios, 6) \ - fn(DT_N_S_zephyr_user, pwm_pin_gpios, 7) + fn(DT_N_S_zephyr_user, pwm_pin_gpios, 7) \ + fn(DT_N_S_zephyr_user, pwm_pin_gpios, 8) #define DT_N_S_zephyr_user_P_pwm_pin_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_zephyr_user, pwm_pin_gpios, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, pwm_pin_gpios, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, pwm_pin_gpios, 2) DT_DEBRACKET_INTERNAL sep \ @@ -10708,7 +12892,8 @@ fn(DT_N_S_zephyr_user, pwm_pin_gpios, 4) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, pwm_pin_gpios, 5) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, pwm_pin_gpios, 6) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_zephyr_user, pwm_pin_gpios, 7) + fn(DT_N_S_zephyr_user, pwm_pin_gpios, 7) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, pwm_pin_gpios, 8) #define DT_N_S_zephyr_user_P_pwm_pin_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_zephyr_user, pwm_pin_gpios, 0, __VA_ARGS__) \ fn(DT_N_S_zephyr_user, pwm_pin_gpios, 1, __VA_ARGS__) \ fn(DT_N_S_zephyr_user, pwm_pin_gpios, 2, __VA_ARGS__) \ @@ -10716,7 +12901,8 @@ fn(DT_N_S_zephyr_user, pwm_pin_gpios, 4, __VA_ARGS__) \ fn(DT_N_S_zephyr_user, pwm_pin_gpios, 5, __VA_ARGS__) \ fn(DT_N_S_zephyr_user, pwm_pin_gpios, 6, __VA_ARGS__) \ - fn(DT_N_S_zephyr_user, pwm_pin_gpios, 7, __VA_ARGS__) + fn(DT_N_S_zephyr_user, pwm_pin_gpios, 7, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, pwm_pin_gpios, 8, __VA_ARGS__) #define DT_N_S_zephyr_user_P_pwm_pin_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_zephyr_user, pwm_pin_gpios, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, pwm_pin_gpios, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, pwm_pin_gpios, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ @@ -10724,8 +12910,9 @@ fn(DT_N_S_zephyr_user, pwm_pin_gpios, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, pwm_pin_gpios, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, pwm_pin_gpios, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_zephyr_user, pwm_pin_gpios, 7, __VA_ARGS__) -#define DT_N_S_zephyr_user_P_pwm_pin_gpios_LEN 8 + fn(DT_N_S_zephyr_user, pwm_pin_gpios, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, pwm_pin_gpios, 8, __VA_ARGS__) +#define DT_N_S_zephyr_user_P_pwm_pin_gpios_LEN 9 #define DT_N_S_zephyr_user_P_pwm_pin_gpios_EXISTS 1 #define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_0_EXISTS 1 #define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800 @@ -10775,6 +12962,42 @@ #define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_7_VAL_pin_EXISTS 1 #define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_7_VAL_flags 0 #define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_7_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_8_EXISTS 1 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_8_PH DT_N_S_gpio_deadbeef +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_8_VAL_pin 0 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_8_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_8_VAL_flags 0 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_8_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_9_EXISTS 1 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_9_PH DT_N_S_gpio_deadbeef +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_9_VAL_pin 1 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_9_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_9_VAL_flags 0 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_9_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_10_EXISTS 1 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_10_PH DT_N_S_gpio_deadbeef +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_10_VAL_pin 2 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_10_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_10_VAL_flags 0 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_10_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_11_EXISTS 1 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_11_PH DT_N_S_gpio_deadbeef +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_11_VAL_pin 3 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_11_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_11_VAL_flags 0 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_11_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_12_EXISTS 1 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_12_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_12_VAL_pin 4 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_12_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_12_VAL_flags 0 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_12_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_13_EXISTS 1 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_13_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_13_VAL_pin 5 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_13_VAL_pin_EXISTS 1 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_13_VAL_flags 0 +#define DT_N_S_zephyr_user_P_adc_pin_gpios_IDX_13_VAL_flags_EXISTS 1 #define DT_N_S_zephyr_user_P_adc_pin_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_zephyr_user, adc_pin_gpios, 0) \ fn(DT_N_S_zephyr_user, adc_pin_gpios, 1) \ fn(DT_N_S_zephyr_user, adc_pin_gpios, 2) \ @@ -10782,7 +13005,13 @@ fn(DT_N_S_zephyr_user, adc_pin_gpios, 4) \ fn(DT_N_S_zephyr_user, adc_pin_gpios, 5) \ fn(DT_N_S_zephyr_user, adc_pin_gpios, 6) \ - fn(DT_N_S_zephyr_user, adc_pin_gpios, 7) + fn(DT_N_S_zephyr_user, adc_pin_gpios, 7) \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 8) \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 9) \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 10) \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 11) \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 12) \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 13) #define DT_N_S_zephyr_user_P_adc_pin_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_zephyr_user, adc_pin_gpios, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, adc_pin_gpios, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, adc_pin_gpios, 2) DT_DEBRACKET_INTERNAL sep \ @@ -10790,7 +13019,13 @@ fn(DT_N_S_zephyr_user, adc_pin_gpios, 4) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, adc_pin_gpios, 5) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, adc_pin_gpios, 6) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_zephyr_user, adc_pin_gpios, 7) + fn(DT_N_S_zephyr_user, adc_pin_gpios, 7) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 8) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 9) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 10) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 11) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 12) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 13) #define DT_N_S_zephyr_user_P_adc_pin_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_zephyr_user, adc_pin_gpios, 0, __VA_ARGS__) \ fn(DT_N_S_zephyr_user, adc_pin_gpios, 1, __VA_ARGS__) \ fn(DT_N_S_zephyr_user, adc_pin_gpios, 2, __VA_ARGS__) \ @@ -10798,7 +13033,13 @@ fn(DT_N_S_zephyr_user, adc_pin_gpios, 4, __VA_ARGS__) \ fn(DT_N_S_zephyr_user, adc_pin_gpios, 5, __VA_ARGS__) \ fn(DT_N_S_zephyr_user, adc_pin_gpios, 6, __VA_ARGS__) \ - fn(DT_N_S_zephyr_user, adc_pin_gpios, 7, __VA_ARGS__) + fn(DT_N_S_zephyr_user, adc_pin_gpios, 7, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 8, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 9, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 10, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 11, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 12, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 13, __VA_ARGS__) #define DT_N_S_zephyr_user_P_adc_pin_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_zephyr_user, adc_pin_gpios, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, adc_pin_gpios, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, adc_pin_gpios, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ @@ -10806,8 +13047,14 @@ fn(DT_N_S_zephyr_user, adc_pin_gpios, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, adc_pin_gpios, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, adc_pin_gpios, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_zephyr_user, adc_pin_gpios, 7, __VA_ARGS__) -#define DT_N_S_zephyr_user_P_adc_pin_gpios_LEN 8 + fn(DT_N_S_zephyr_user, adc_pin_gpios, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, adc_pin_gpios, 13, __VA_ARGS__) +#define DT_N_S_zephyr_user_P_adc_pin_gpios_LEN 14 #define DT_N_S_zephyr_user_P_adc_pin_gpios_EXISTS 1 #define DT_N_S_zephyr_user_P_serials_IDX_0 DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0 #define DT_N_S_zephyr_user_P_serials_IDX_0_PH DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0 @@ -10868,12 +13115,19 @@ fn(DT_N_S_zephyr_user, spis, 1, __VA_ARGS__) #define DT_N_S_zephyr_user_P_spis_LEN 2 #define DT_N_S_zephyr_user_P_spis_EXISTS 1 -#define DT_N_S_zephyr_user_P_pwms {} -#define DT_N_S_zephyr_user_P_pwms_FOREACH_PROP_ELEM(fn) -#define DT_N_S_zephyr_user_P_pwms_FOREACH_PROP_ELEM_SEP(fn, sep) -#define DT_N_S_zephyr_user_P_pwms_FOREACH_PROP_ELEM_VARGS(fn, ...) -#define DT_N_S_zephyr_user_P_pwms_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) -#define DT_N_S_zephyr_user_P_pwms_LEN 0 +#define DT_N_S_zephyr_user_P_pwms_IDX_0_EXISTS 1 +#define DT_N_S_zephyr_user_P_pwms_IDX_0_PH DT_N_S_soc_S_timers_40010000_S_pwm +#define DT_N_S_zephyr_user_P_pwms_IDX_0_VAL_channel 3 +#define DT_N_S_zephyr_user_P_pwms_IDX_0_VAL_channel_EXISTS 1 +#define DT_N_S_zephyr_user_P_pwms_IDX_0_VAL_period 166 +#define DT_N_S_zephyr_user_P_pwms_IDX_0_VAL_period_EXISTS 1 +#define DT_N_S_zephyr_user_P_pwms_IDX_0_VAL_flags 0 +#define DT_N_S_zephyr_user_P_pwms_IDX_0_VAL_flags_EXISTS 1 +#define DT_N_S_zephyr_user_P_pwms_FOREACH_PROP_ELEM(fn) fn(DT_N_S_zephyr_user, pwms, 0) +#define DT_N_S_zephyr_user_P_pwms_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_zephyr_user, pwms, 0) +#define DT_N_S_zephyr_user_P_pwms_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_zephyr_user, pwms, 0, __VA_ARGS__) +#define DT_N_S_zephyr_user_P_pwms_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_zephyr_user, pwms, 0, __VA_ARGS__) +#define DT_N_S_zephyr_user_P_pwms_LEN 1 #define DT_N_S_zephyr_user_P_pwms_EXISTS 1 #define DT_N_S_zephyr_user_P_io_channels_IDX_0_EXISTS 1 #define DT_N_S_zephyr_user_P_io_channels_IDX_0_PH DT_N_S_soc_S_adc_40022000 @@ -10907,6 +13161,30 @@ #define DT_N_S_zephyr_user_P_io_channels_IDX_7_PH DT_N_S_soc_S_adc_40022000 #define DT_N_S_zephyr_user_P_io_channels_IDX_7_VAL_input 16 #define DT_N_S_zephyr_user_P_io_channels_IDX_7_VAL_input_EXISTS 1 +#define DT_N_S_zephyr_user_P_io_channels_IDX_8_EXISTS 1 +#define DT_N_S_zephyr_user_P_io_channels_IDX_8_PH DT_N_S_soc_S_adc_58026000 +#define DT_N_S_zephyr_user_P_io_channels_IDX_8_VAL_input 0 +#define DT_N_S_zephyr_user_P_io_channels_IDX_8_VAL_input_EXISTS 1 +#define DT_N_S_zephyr_user_P_io_channels_IDX_9_EXISTS 1 +#define DT_N_S_zephyr_user_P_io_channels_IDX_9_PH DT_N_S_soc_S_adc_58026000 +#define DT_N_S_zephyr_user_P_io_channels_IDX_9_VAL_input 1 +#define DT_N_S_zephyr_user_P_io_channels_IDX_9_VAL_input_EXISTS 1 +#define DT_N_S_zephyr_user_P_io_channels_IDX_10_EXISTS 1 +#define DT_N_S_zephyr_user_P_io_channels_IDX_10_PH DT_N_S_soc_S_adc_40022000 +#define DT_N_S_zephyr_user_P_io_channels_IDX_10_VAL_input 1 +#define DT_N_S_zephyr_user_P_io_channels_IDX_10_VAL_input_EXISTS 1 +#define DT_N_S_zephyr_user_P_io_channels_IDX_11_EXISTS 1 +#define DT_N_S_zephyr_user_P_io_channels_IDX_11_PH DT_N_S_soc_S_adc_40022000 +#define DT_N_S_zephyr_user_P_io_channels_IDX_11_VAL_input 0 +#define DT_N_S_zephyr_user_P_io_channels_IDX_11_VAL_input_EXISTS 1 +#define DT_N_S_zephyr_user_P_io_channels_IDX_12_EXISTS 1 +#define DT_N_S_zephyr_user_P_io_channels_IDX_12_PH DT_N_S_soc_S_adc_40022000 +#define DT_N_S_zephyr_user_P_io_channels_IDX_12_VAL_input 18 +#define DT_N_S_zephyr_user_P_io_channels_IDX_12_VAL_input_EXISTS 1 +#define DT_N_S_zephyr_user_P_io_channels_IDX_13_EXISTS 1 +#define DT_N_S_zephyr_user_P_io_channels_IDX_13_PH DT_N_S_soc_S_adc_40022000 +#define DT_N_S_zephyr_user_P_io_channels_IDX_13_VAL_input 19 +#define DT_N_S_zephyr_user_P_io_channels_IDX_13_VAL_input_EXISTS 1 #define DT_N_S_zephyr_user_P_io_channels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_zephyr_user, io_channels, 0) \ fn(DT_N_S_zephyr_user, io_channels, 1) \ fn(DT_N_S_zephyr_user, io_channels, 2) \ @@ -10914,7 +13192,13 @@ fn(DT_N_S_zephyr_user, io_channels, 4) \ fn(DT_N_S_zephyr_user, io_channels, 5) \ fn(DT_N_S_zephyr_user, io_channels, 6) \ - fn(DT_N_S_zephyr_user, io_channels, 7) + fn(DT_N_S_zephyr_user, io_channels, 7) \ + fn(DT_N_S_zephyr_user, io_channels, 8) \ + fn(DT_N_S_zephyr_user, io_channels, 9) \ + fn(DT_N_S_zephyr_user, io_channels, 10) \ + fn(DT_N_S_zephyr_user, io_channels, 11) \ + fn(DT_N_S_zephyr_user, io_channels, 12) \ + fn(DT_N_S_zephyr_user, io_channels, 13) #define DT_N_S_zephyr_user_P_io_channels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_zephyr_user, io_channels, 0) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, io_channels, 1) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, io_channels, 2) DT_DEBRACKET_INTERNAL sep \ @@ -10922,7 +13206,13 @@ fn(DT_N_S_zephyr_user, io_channels, 4) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, io_channels, 5) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, io_channels, 6) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_zephyr_user, io_channels, 7) + fn(DT_N_S_zephyr_user, io_channels, 7) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, io_channels, 8) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, io_channels, 9) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, io_channels, 10) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, io_channels, 11) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, io_channels, 12) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, io_channels, 13) #define DT_N_S_zephyr_user_P_io_channels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_zephyr_user, io_channels, 0, __VA_ARGS__) \ fn(DT_N_S_zephyr_user, io_channels, 1, __VA_ARGS__) \ fn(DT_N_S_zephyr_user, io_channels, 2, __VA_ARGS__) \ @@ -10930,7 +13220,13 @@ fn(DT_N_S_zephyr_user, io_channels, 4, __VA_ARGS__) \ fn(DT_N_S_zephyr_user, io_channels, 5, __VA_ARGS__) \ fn(DT_N_S_zephyr_user, io_channels, 6, __VA_ARGS__) \ - fn(DT_N_S_zephyr_user, io_channels, 7, __VA_ARGS__) + fn(DT_N_S_zephyr_user, io_channels, 7, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, io_channels, 8, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, io_channels, 9, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, io_channels, 10, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, io_channels, 11, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, io_channels, 12, __VA_ARGS__) \ + fn(DT_N_S_zephyr_user, io_channels, 13, __VA_ARGS__) #define DT_N_S_zephyr_user_P_io_channels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_zephyr_user, io_channels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, io_channels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, io_channels, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ @@ -10938,8 +13234,14 @@ fn(DT_N_S_zephyr_user, io_channels, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, io_channels, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ fn(DT_N_S_zephyr_user, io_channels, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_zephyr_user, io_channels, 7, __VA_ARGS__) -#define DT_N_S_zephyr_user_P_io_channels_LEN 8 + fn(DT_N_S_zephyr_user, io_channels, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, io_channels, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, io_channels, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, io_channels, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, io_channels, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, io_channels, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_zephyr_user, io_channels, 13, __VA_ARGS__) +#define DT_N_S_zephyr_user_P_io_channels_LEN 14 #define DT_N_S_zephyr_user_P_io_channels_EXISTS 1 /* @@ -10984,8 +13286,8 @@ #define DT_N_S_clocks_S_clk_csi_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_clocks_S_clk_csi_ORD 77 -#define DT_N_S_clocks_S_clk_csi_ORD_STR_SORTABLE 00077 +#define DT_N_S_clocks_S_clk_csi_ORD 88 +#define DT_N_S_clocks_S_clk_csi_ORD_STR_SORTABLE 00088 /* Ordinals for what this node depends on directly: */ #define DT_N_S_clocks_S_clk_csi_REQUIRES_ORDS \ @@ -11057,8 +13359,8 @@ #define DT_N_S_clocks_S_clk_hsi_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_clocks_S_clk_hsi_ORD 78 -#define DT_N_S_clocks_S_clk_hsi_ORD_STR_SORTABLE 00078 +#define DT_N_S_clocks_S_clk_hsi_ORD 89 +#define DT_N_S_clocks_S_clk_hsi_ORD_STR_SORTABLE 00089 /* Ordinals for what this node depends on directly: */ #define DT_N_S_clocks_S_clk_hsi_REQUIRES_ORDS \ @@ -11134,8 +13436,8 @@ #define DT_N_S_clocks_S_clk_hsi48_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_clocks_S_clk_hsi48_ORD 79 -#define DT_N_S_clocks_S_clk_hsi48_ORD_STR_SORTABLE 00079 +#define DT_N_S_clocks_S_clk_hsi48_ORD 90 +#define DT_N_S_clocks_S_clk_hsi48_ORD_STR_SORTABLE 00090 /* Ordinals for what this node depends on directly: */ #define DT_N_S_clocks_S_clk_hsi48_REQUIRES_ORDS \ @@ -11207,8 +13509,8 @@ #define DT_N_S_clocks_S_clk_lse_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_clocks_S_clk_lse_ORD 80 -#define DT_N_S_clocks_S_clk_lse_ORD_STR_SORTABLE 00080 +#define DT_N_S_clocks_S_clk_lse_ORD 91 +#define DT_N_S_clocks_S_clk_lse_ORD_STR_SORTABLE 00091 /* Ordinals for what this node depends on directly: */ #define DT_N_S_clocks_S_clk_lse_REQUIRES_ORDS \ @@ -11290,8 +13592,8 @@ #define DT_N_S_clocks_S_clk_lsi_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_clocks_S_clk_lsi_ORD 81 -#define DT_N_S_clocks_S_clk_lsi_ORD_STR_SORTABLE 00081 +#define DT_N_S_clocks_S_clk_lsi_ORD 92 +#define DT_N_S_clocks_S_clk_lsi_ORD_STR_SORTABLE 00092 /* Ordinals for what this node depends on directly: */ #define DT_N_S_clocks_S_clk_lsi_REQUIRES_ORDS \ @@ -11363,8 +13665,8 @@ #define DT_N_S_clocks_S_perck_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_clocks_S_perck_ORD 82 -#define DT_N_S_clocks_S_perck_ORD_STR_SORTABLE 00082 +#define DT_N_S_clocks_S_perck_ORD 93 +#define DT_N_S_clocks_S_perck_ORD_STR_SORTABLE 00093 /* Ordinals for what this node depends on directly: */ #define DT_N_S_clocks_S_perck_REQUIRES_ORDS \ @@ -11466,8 +13768,8 @@ #define DT_N_S_clocks_S_pll_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_clocks_S_pll_1_ORD 83 -#define DT_N_S_clocks_S_pll_1_ORD_STR_SORTABLE 00083 +#define DT_N_S_clocks_S_pll_1_ORD 94 +#define DT_N_S_clocks_S_pll_1_ORD_STR_SORTABLE 00094 /* Ordinals for what this node depends on directly: */ #define DT_N_S_clocks_S_pll_1_REQUIRES_ORDS \ @@ -11581,8 +13883,8 @@ #define DT_N_S_clocks_S_pll_2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_clocks_S_pll_2_ORD 84 -#define DT_N_S_clocks_S_pll_2_ORD_STR_SORTABLE 00084 +#define DT_N_S_clocks_S_pll_2_ORD 95 +#define DT_N_S_clocks_S_pll_2_ORD_STR_SORTABLE 00095 /* Ordinals for what this node depends on directly: */ #define DT_N_S_clocks_S_pll_2_REQUIRES_ORDS \ @@ -11690,8 +13992,8 @@ #define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_cpus_ORD 85 -#define DT_N_S_cpus_ORD_STR_SORTABLE 00085 +#define DT_N_S_cpus_ORD 96 +#define DT_N_S_cpus_ORD_STR_SORTABLE 00096 /* Ordinals for what this node depends on directly: */ #define DT_N_S_cpus_REQUIRES_ORDS \ @@ -11699,7 +14001,7 @@ /* Ordinals for what depends directly on this node: */ #define DT_N_S_cpus_SUPPORTS_ORDS \ - 86, /* /cpus/cpu@0 */ + 97, /* /cpus/cpu@0 */ /* Existence and alternate IDs: */ #define DT_N_S_cpus_EXISTS 1 @@ -11759,16 +14061,16 @@ #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_cpus_S_cpu_0_ORD 86 -#define DT_N_S_cpus_S_cpu_0_ORD_STR_SORTABLE 00086 +#define DT_N_S_cpus_S_cpu_0_ORD 97 +#define DT_N_S_cpus_S_cpu_0_ORD_STR_SORTABLE 00097 /* Ordinals for what this node depends on directly: */ #define DT_N_S_cpus_S_cpu_0_REQUIRES_ORDS \ - 85, /* /cpus */ + 96, /* /cpus */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_cpus_S_cpu_0_SUPPORTS_ORDS \ - 87, /* /cpus/cpu@0/mpu@e000ed90 */ + 98, /* /cpus/cpu@0/mpu@e000ed90 */ /* Existence and alternate IDs: */ #define DT_N_S_cpus_S_cpu_0_EXISTS 1 @@ -11859,12 +14161,12 @@ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_ORD 87 -#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_ORD_STR_SORTABLE 00087 +#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_ORD 98 +#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_ORD_STR_SORTABLE 00098 /* Ordinals for what this node depends on directly: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REQUIRES_ORDS \ - 86, /* /cpus/cpu@0 */ + 97, /* /cpus/cpu@0 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_SUPPORTS_ORDS /* nothing */ @@ -11961,17 +14263,17 @@ #define DT_N_S_gpio_keys_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_gpio_keys_S_button_0, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_gpio_keys_ORD 88 -#define DT_N_S_gpio_keys_ORD_STR_SORTABLE 00088 +#define DT_N_S_gpio_keys_ORD 99 +#define DT_N_S_gpio_keys_ORD_STR_SORTABLE 00099 /* Ordinals for what this node depends on directly: */ #define DT_N_S_gpio_keys_REQUIRES_ORDS \ 0, /* / */ \ - 64, /* /soc/pin-controller@58020000/gpio@58020800 */ + 71, /* /soc/pin-controller@58020000/gpio@58020800 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_gpio_keys_SUPPORTS_ORDS \ - 89, /* /gpio_keys/button_0 */ + 100, /* /gpio_keys/button_0 */ /* Existence and alternate IDs: */ #define DT_N_S_gpio_keys_EXISTS 1 @@ -12052,13 +14354,13 @@ #define DT_N_S_gpio_keys_S_button_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_gpio_keys_S_button_0_ORD 89 -#define DT_N_S_gpio_keys_S_button_0_ORD_STR_SORTABLE 00089 +#define DT_N_S_gpio_keys_S_button_0_ORD 100 +#define DT_N_S_gpio_keys_S_button_0_ORD_STR_SORTABLE 00100 /* Ordinals for what this node depends on directly: */ #define DT_N_S_gpio_keys_S_button_0_REQUIRES_ORDS \ - 64, /* /soc/pin-controller@58020000/gpio@58020800 */ \ - 88, /* /gpio_keys */ + 71, /* /soc/pin-controller@58020000/gpio@58020800 */ \ + 99, /* /gpio_keys */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_gpio_keys_S_button_0_SUPPORTS_ORDS /* nothing */ @@ -12137,21 +14439,21 @@ #define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_leds_ORD 90 -#define DT_N_S_leds_ORD_STR_SORTABLE 00090 +#define DT_N_S_leds_ORD 101 +#define DT_N_S_leds_ORD_STR_SORTABLE 00101 /* Ordinals for what this node depends on directly: */ #define DT_N_S_leds_REQUIRES_ORDS \ 0, /* / */ \ - 66, /* /soc/pin-controller@58020000/gpio@58021000 */ \ - 68, /* /soc/pin-controller@58020000/gpio@58022000 */ \ - 69, /* /soc/pin-controller@58020000/gpio@58022400 */ + 73, /* /soc/pin-controller@58020000/gpio@58021000 */ \ + 76, /* /soc/pin-controller@58020000/gpio@58022000 */ \ + 77, /* /soc/pin-controller@58020000/gpio@58022400 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_leds_SUPPORTS_ORDS \ - 91, /* /leds/led_0 */ \ - 92, /* /leds/led_1 */ \ - 93, /* /leds/led_2 */ + 102, /* /leds/led_0 */ \ + 103, /* /leds/led_1 */ \ + 104, /* /leds/led_2 */ /* Existence and alternate IDs: */ #define DT_N_S_leds_EXISTS 1 @@ -12222,13 +14524,13 @@ #define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_leds_S_led_0_ORD 91 -#define DT_N_S_leds_S_led_0_ORD_STR_SORTABLE 00091 +#define DT_N_S_leds_S_led_0_ORD 102 +#define DT_N_S_leds_S_led_0_ORD_STR_SORTABLE 00102 /* Ordinals for what this node depends on directly: */ #define DT_N_S_leds_S_led_0_REQUIRES_ORDS \ - 68, /* /soc/pin-controller@58020000/gpio@58022000 */ \ - 90, /* /leds */ + 76, /* /soc/pin-controller@58020000/gpio@58022000 */ \ + 101, /* /leds */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_leds_S_led_0_SUPPORTS_ORDS /* nothing */ @@ -12302,13 +14604,13 @@ #define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_leds_S_led_1_ORD 92 -#define DT_N_S_leds_S_led_1_ORD_STR_SORTABLE 00092 +#define DT_N_S_leds_S_led_1_ORD 103 +#define DT_N_S_leds_S_led_1_ORD_STR_SORTABLE 00103 /* Ordinals for what this node depends on directly: */ #define DT_N_S_leds_S_led_1_REQUIRES_ORDS \ - 69, /* /soc/pin-controller@58020000/gpio@58022400 */ \ - 90, /* /leds */ + 77, /* /soc/pin-controller@58020000/gpio@58022400 */ \ + 101, /* /leds */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_leds_S_led_1_SUPPORTS_ORDS /* nothing */ @@ -12382,13 +14684,13 @@ #define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_leds_S_led_2_ORD 93 -#define DT_N_S_leds_S_led_2_ORD_STR_SORTABLE 00093 +#define DT_N_S_leds_S_led_2_ORD 104 +#define DT_N_S_leds_S_led_2_ORD_STR_SORTABLE 00104 /* Ordinals for what this node depends on directly: */ #define DT_N_S_leds_S_led_2_REQUIRES_ORDS \ - 66, /* /soc/pin-controller@58020000/gpio@58021000 */ \ - 90, /* /leds */ + 73, /* /soc/pin-controller@58020000/gpio@58021000 */ \ + 101, /* /leds */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_leds_S_led_2_SUPPORTS_ORDS /* nothing */ @@ -12464,8 +14766,8 @@ #define DT_N_S_soc_S_adc_40022100_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022100_ORD 94 -#define DT_N_S_soc_S_adc_40022100_ORD_STR_SORTABLE 00094 +#define DT_N_S_soc_S_adc_40022100_ORD 105 +#define DT_N_S_soc_S_adc_40022100_ORD_STR_SORTABLE 00105 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_40022100_REQUIRES_ORDS \ @@ -12478,7 +14780,7 @@ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_adc_40022100_EXISTS 1 -#define DT_N_INST_1_st_stm32_adc DT_N_S_soc_S_adc_40022100 +#define DT_N_INST_2_st_stm32_adc DT_N_S_soc_S_adc_40022100 #define DT_N_NODELABEL_adc2 DT_N_S_soc_S_adc_40022100 /* Macros for properties that are special in the specification: */ @@ -12699,8 +15001,8 @@ #define DT_N_S_soc_S_adc_40022300_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022300_ORD 95 -#define DT_N_S_soc_S_adc_40022300_ORD_STR_SORTABLE 00095 +#define DT_N_S_soc_S_adc_40022300_ORD 106 +#define DT_N_S_soc_S_adc_40022300_ORD_STR_SORTABLE 00106 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_40022300_REQUIRES_ORDS \ @@ -12713,7 +15015,7 @@ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_adc_40022300_EXISTS 1 -#define DT_N_INST_2_st_stm32_adc DT_N_S_soc_S_adc_40022300 +#define DT_N_INST_3_st_stm32_adc DT_N_S_soc_S_adc_40022300 #define DT_N_NODELABEL_adc1_2 DT_N_S_soc_S_adc_40022300 /* Macros for properties that are special in the specification: */ @@ -12934,8 +15236,8 @@ #define DT_N_S_soc_S_bdma_58025400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_bdma_58025400_ORD 96 -#define DT_N_S_soc_S_bdma_58025400_ORD_STR_SORTABLE 00096 +#define DT_N_S_soc_S_bdma_58025400_ORD 107 +#define DT_N_S_soc_S_bdma_58025400_ORD_STR_SORTABLE 00107 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_bdma_58025400_REQUIRES_ORDS \ @@ -13162,8 +15464,8 @@ #define DT_N_S_soc_S_can_4000a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_can_4000a000_ORD 97 -#define DT_N_S_soc_S_can_4000a000_ORD_STR_SORTABLE 00097 +#define DT_N_S_soc_S_can_4000a000_ORD 108 +#define DT_N_S_soc_S_can_4000a000_ORD_STR_SORTABLE 00108 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_can_4000a000_REQUIRES_ORDS \ @@ -13436,7 +15738,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_CHILD_IDX 21 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_CHILD_IDX 38 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_NODELABEL_NUM 1 @@ -13456,16 +15758,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_ORD 98 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_ORD_STR_SORTABLE 00098 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_ORD 109 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_ORD_STR_SORTABLE 00109 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_SUPPORTS_ORDS \ - 100, /* /soc/can@4000a400 */ + 111, /* /soc/can@4000a400 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_EXISTS 1 @@ -13535,7 +15837,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_CHILD_IDX 22 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_CHILD_IDX 39 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_NODELABEL_NUM 1 @@ -13555,16 +15857,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_ORD 99 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_ORD_STR_SORTABLE 00099 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_ORD 110 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_ORD_STR_SORTABLE 00110 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_SUPPORTS_ORDS \ - 100, /* /soc/can@4000a400 */ + 111, /* /soc/can@4000a400 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_EXISTS 1 @@ -13657,16 +15959,16 @@ #define DT_N_S_soc_S_can_4000a400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_can_4000a400_ORD 100 -#define DT_N_S_soc_S_can_4000a400_ORD_STR_SORTABLE 00100 +#define DT_N_S_soc_S_can_4000a400_ORD 111 +#define DT_N_S_soc_S_can_4000a400_ORD_STR_SORTABLE 00111 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_can_4000a400_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 98, /* /soc/pin-controller@58020000/fdcan2_rx_pb5 */ \ - 99, /* /soc/pin-controller@58020000/fdcan2_tx_pb13 */ + 109, /* /soc/pin-controller@58020000/fdcan2_rx_pb5 */ \ + 110, /* /soc/pin-controller@58020000/fdcan2_tx_pb13 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_can_4000a400_SUPPORTS_ORDS /* nothing */ @@ -13978,7 +16280,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_CHILD_IDX 19 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_CHILD_IDX 25 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_NODELABEL_NUM 1 @@ -13998,16 +16300,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_ORD 101 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_ORD_STR_SORTABLE 00101 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_ORD 112 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_ORD_STR_SORTABLE 00112 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_SUPPORTS_ORDS \ - 103, /* /soc/dac@40007400 */ + 114, /* /soc/dac@40007400 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_EXISTS 1 @@ -14077,7 +16379,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_CHILD_IDX 20 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_CHILD_IDX 26 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_NODELABEL_NUM 1 @@ -14097,16 +16399,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_ORD 102 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_ORD_STR_SORTABLE 00102 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_ORD 113 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_ORD_STR_SORTABLE 00113 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_SUPPORTS_ORDS \ - 103, /* /soc/dac@40007400 */ + 114, /* /soc/dac@40007400 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_EXISTS 1 @@ -14199,15 +16501,15 @@ #define DT_N_S_soc_S_dac_40007400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_dac_40007400_ORD 103 -#define DT_N_S_soc_S_dac_40007400_ORD_STR_SORTABLE 00103 +#define DT_N_S_soc_S_dac_40007400_ORD 114 +#define DT_N_S_soc_S_dac_40007400_ORD_STR_SORTABLE 00114 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_dac_40007400_REQUIRES_ORDS \ 4, /* /soc */ \ 9, /* /soc/rcc@58024400 */ \ - 101, /* /soc/pin-controller@58020000/dac1_out1_pa4 */ \ - 102, /* /soc/pin-controller@58020000/dac1_out2_pa5 */ + 112, /* /soc/pin-controller@58020000/dac1_out1_pa4 */ \ + 113, /* /soc/pin-controller@58020000/dac1_out2_pa5 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_dac_40007400_SUPPORTS_ORDS /* nothing */ @@ -14325,176 +16627,6 @@ #define DT_N_S_soc_S_dac_40007400_P_pinctrl_names_LEN 1 #define DT_N_S_soc_S_dac_40007400_P_pinctrl_names_EXISTS 1 -/* - * Devicetree node: /soc/dcmi@48020000 - * - * Node identifier: DT_N_S_soc_S_dcmi_48020000 - * - * Binding (compatible = st,stm32-dcmi): - * $ZEPHYR_BASE/dts/bindings/video/st,stm32-dcmi.yaml - * - * (Descriptions have moved to the Devicetree Bindings Index - * in the documentation.) - */ - -/* Node's full path: */ -#define DT_N_S_soc_S_dcmi_48020000_PATH "/soc/dcmi@48020000" - -/* Node's name with unit-address: */ -#define DT_N_S_soc_S_dcmi_48020000_FULL_NAME "dcmi@48020000" - -/* Node parent (/soc) identifier: */ -#define DT_N_S_soc_S_dcmi_48020000_PARENT DT_N_S_soc - -/* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_dcmi_48020000_CHILD_IDX 65 - -/* Helpers for dealing with node labels: */ -#define DT_N_S_soc_S_dcmi_48020000_NODELABEL_NUM 1 -#define DT_N_S_soc_S_dcmi_48020000_FOREACH_NODELABEL(fn) fn(dcmi) -#define DT_N_S_soc_S_dcmi_48020000_FOREACH_NODELABEL_VARGS(fn, ...) fn(dcmi, __VA_ARGS__) - -/* Helper macros for child nodes of this node. */ -#define DT_N_S_soc_S_dcmi_48020000_CHILD_NUM 0 -#define DT_N_S_soc_S_dcmi_48020000_CHILD_NUM_STATUS_OKAY 0 -#define DT_N_S_soc_S_dcmi_48020000_FOREACH_CHILD(fn) -#define DT_N_S_soc_S_dcmi_48020000_FOREACH_CHILD_SEP(fn, sep) -#define DT_N_S_soc_S_dcmi_48020000_FOREACH_CHILD_VARGS(fn, ...) -#define DT_N_S_soc_S_dcmi_48020000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) -#define DT_N_S_soc_S_dcmi_48020000_FOREACH_CHILD_STATUS_OKAY(fn) -#define DT_N_S_soc_S_dcmi_48020000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) -#define DT_N_S_soc_S_dcmi_48020000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) -#define DT_N_S_soc_S_dcmi_48020000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) - -/* Node's dependency ordinal: */ -#define DT_N_S_soc_S_dcmi_48020000_ORD 104 -#define DT_N_S_soc_S_dcmi_48020000_ORD_STR_SORTABLE 00104 - -/* Ordinals for what this node depends on directly: */ -#define DT_N_S_soc_S_dcmi_48020000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ - -/* Ordinals for what depends directly on this node: */ -#define DT_N_S_soc_S_dcmi_48020000_SUPPORTS_ORDS /* nothing */ - -/* Existence and alternate IDs: */ -#define DT_N_S_soc_S_dcmi_48020000_EXISTS 1 -#define DT_N_INST_0_st_stm32_dcmi DT_N_S_soc_S_dcmi_48020000 -#define DT_N_NODELABEL_dcmi DT_N_S_soc_S_dcmi_48020000 - -/* Macros for properties that are special in the specification: */ -#define DT_N_S_soc_S_dcmi_48020000_REG_NUM 1 -#define DT_N_S_soc_S_dcmi_48020000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_REG_IDX_0_VAL_ADDRESS 1208090624 /* 0x48020000 */ -#define DT_N_S_soc_S_dcmi_48020000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ -#define DT_N_S_soc_S_dcmi_48020000_RANGES_NUM 0 -#define DT_N_S_soc_S_dcmi_48020000_FOREACH_RANGE(fn) -#define DT_N_S_soc_S_dcmi_48020000_IRQ_NUM 1 -#define DT_N_S_soc_S_dcmi_48020000_IRQ_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_IRQ_IDX_0_VAL_irq 78 -#define DT_N_S_soc_S_dcmi_48020000_IRQ_IDX_0_VAL_irq_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_IRQ_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_IRQ_IDX_0_VAL_priority 0 -#define DT_N_S_soc_S_dcmi_48020000_IRQ_IDX_0_VAL_priority_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 -#define DT_N_S_soc_S_dcmi_48020000_IRQ_LEVEL 1 -#define DT_N_S_soc_S_dcmi_48020000_IRQ_NAME_dcmi_VAL_irq DT_N_S_soc_S_dcmi_48020000_IRQ_IDX_0_VAL_irq -#define DT_N_S_soc_S_dcmi_48020000_IRQ_NAME_dcmi_VAL_irq_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_IRQ_NAME_dcmi_VAL_priority DT_N_S_soc_S_dcmi_48020000_IRQ_IDX_0_VAL_priority -#define DT_N_S_soc_S_dcmi_48020000_IRQ_NAME_dcmi_VAL_priority_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_IRQ_NAME_dcmi_CONTROLLER DT_N_S_soc_S_dcmi_48020000_IRQ_IDX_0_CONTROLLER -#define DT_N_S_soc_S_dcmi_48020000_COMPAT_MATCHES_st_stm32_dcmi 1 -#define DT_N_S_soc_S_dcmi_48020000_COMPAT_VENDOR_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_COMPAT_VENDOR_IDX_0 "STMicroelectronics" -#define DT_N_S_soc_S_dcmi_48020000_COMPAT_MODEL_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_COMPAT_MODEL_IDX_0 "stm32-dcmi" -#define DT_N_S_soc_S_dcmi_48020000_STATUS_disabled 1 - -/* Pin control (pinctrl-, pinctrl-names) properties: */ -#define DT_N_S_soc_S_dcmi_48020000_PINCTRL_NUM 0 - -/* Generic property macros: */ -#define DT_N_S_soc_S_dcmi_48020000_P_wakeup_source 0 -#define DT_N_S_soc_S_dcmi_48020000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_dcmi_48020000_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_status "disabled" -#define DT_N_S_soc_S_dcmi_48020000_P_status_STRING_UNQUOTED disabled -#define DT_N_S_soc_S_dcmi_48020000_P_status_STRING_TOKEN disabled -#define DT_N_S_soc_S_dcmi_48020000_P_status_STRING_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_dcmi_48020000_P_status_IDX_0 "disabled" -#define DT_N_S_soc_S_dcmi_48020000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_dcmi_48020000_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_dcmi_48020000_P_status_ENUM_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_dcmi_48020000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dcmi_48020000, status, 0) -#define DT_N_S_soc_S_dcmi_48020000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000, status, 0) -#define DT_N_S_soc_S_dcmi_48020000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dcmi_48020000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dcmi_48020000_P_status_LEN 1 -#define DT_N_S_soc_S_dcmi_48020000_P_status_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_compatible {"st,stm32-dcmi"} -#define DT_N_S_soc_S_dcmi_48020000_P_compatible_IDX_0 "st,stm32-dcmi" -#define DT_N_S_soc_S_dcmi_48020000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-dcmi -#define DT_N_S_soc_S_dcmi_48020000_P_compatible_IDX_0_STRING_TOKEN st_stm32_dcmi -#define DT_N_S_soc_S_dcmi_48020000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_DCMI -#define DT_N_S_soc_S_dcmi_48020000_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dcmi_48020000, compatible, 0) -#define DT_N_S_soc_S_dcmi_48020000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000, compatible, 0) -#define DT_N_S_soc_S_dcmi_48020000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dcmi_48020000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dcmi_48020000_P_compatible_LEN 1 -#define DT_N_S_soc_S_dcmi_48020000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_reg {1208090624 /* 0x48020000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_dcmi_48020000_P_reg_IDX_0 1208090624 -#define DT_N_S_soc_S_dcmi_48020000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_dcmi_48020000_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_interrupts {78 /* 0x4e */, 0 /* 0x0 */} -#define DT_N_S_soc_S_dcmi_48020000_P_interrupts_IDX_0 78 -#define DT_N_S_soc_S_dcmi_48020000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_dcmi_48020000_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_interrupts_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names {"dcmi"} -#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_IDX_0 "dcmi" -#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_IDX_0_STRING_UNQUOTED dcmi -#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_IDX_0_STRING_TOKEN dcmi -#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN DCMI -#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dcmi_48020000, interrupt_names, 0) -#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000, interrupt_names, 0) -#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000, interrupt_names, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000, interrupt_names, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_LEN 1 -#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_dcmi_48020000_P_clocks_IDX_0_VAL_bus 220 -#define DT_N_S_soc_S_dcmi_48020000_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_clocks_IDX_0_VAL_bits 1 -#define DT_N_S_soc_S_dcmi_48020000_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dcmi_48020000, clocks, 0) -#define DT_N_S_soc_S_dcmi_48020000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000, clocks, 0) -#define DT_N_S_soc_S_dcmi_48020000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dcmi_48020000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dcmi_48020000_P_clocks_LEN 1 -#define DT_N_S_soc_S_dcmi_48020000_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_dcmi_48020000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_bus_width 8 -#define DT_N_S_soc_S_dcmi_48020000_P_bus_width_ENUM_IDX 0 -#define DT_N_S_soc_S_dcmi_48020000_P_bus_width_ENUM_VAL_8_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_bus_width_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_capture_rate 1 -#define DT_N_S_soc_S_dcmi_48020000_P_capture_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_dcmi_48020000_P_capture_rate_ENUM_VAL_1_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_capture_rate_EXISTS 1 - /* * Devicetree node: /soc/display-controller@50001000 * @@ -14537,8 +16669,8 @@ #define DT_N_S_soc_S_display_controller_50001000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_display_controller_50001000_ORD 105 -#define DT_N_S_soc_S_display_controller_50001000_ORD_STR_SORTABLE 00105 +#define DT_N_S_soc_S_display_controller_50001000_ORD 115 +#define DT_N_S_soc_S_display_controller_50001000_ORD_STR_SORTABLE 00115 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_display_controller_50001000_REQUIRES_ORDS \ @@ -14682,234 +16814,6 @@ #define DT_N_S_soc_S_display_controller_50001000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_display_controller_50001000_P_zephyr_deferred_init_EXISTS 1 -/* - * Devicetree node: /soc/dma@40020000 - * - * Node identifier: DT_N_S_soc_S_dma_40020000 - * - * Binding (compatible = st,stm32-dma-v1): - * $ZEPHYR_BASE/dts/bindings/dma/st,stm32-dma-v1.yaml - * - * (Descriptions have moved to the Devicetree Bindings Index - * in the documentation.) - */ - -/* Node's full path: */ -#define DT_N_S_soc_S_dma_40020000_PATH "/soc/dma@40020000" - -/* Node's name with unit-address: */ -#define DT_N_S_soc_S_dma_40020000_FULL_NAME "dma@40020000" - -/* Node parent (/soc) identifier: */ -#define DT_N_S_soc_S_dma_40020000_PARENT DT_N_S_soc - -/* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_dma_40020000_CHILD_IDX 53 - -/* Helpers for dealing with node labels: */ -#define DT_N_S_soc_S_dma_40020000_NODELABEL_NUM 1 -#define DT_N_S_soc_S_dma_40020000_FOREACH_NODELABEL(fn) fn(dma1) -#define DT_N_S_soc_S_dma_40020000_FOREACH_NODELABEL_VARGS(fn, ...) fn(dma1, __VA_ARGS__) - -/* Helper macros for child nodes of this node. */ -#define DT_N_S_soc_S_dma_40020000_CHILD_NUM 0 -#define DT_N_S_soc_S_dma_40020000_CHILD_NUM_STATUS_OKAY 0 -#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD(fn) -#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD_SEP(fn, sep) -#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD_VARGS(fn, ...) -#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) -#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD_STATUS_OKAY(fn) -#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) -#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) -#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) - -/* Node's dependency ordinal: */ -#define DT_N_S_soc_S_dma_40020000_ORD 106 -#define DT_N_S_soc_S_dma_40020000_ORD_STR_SORTABLE 00106 - -/* Ordinals for what this node depends on directly: */ -#define DT_N_S_soc_S_dma_40020000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ - -/* Ordinals for what depends directly on this node: */ -#define DT_N_S_soc_S_dma_40020000_SUPPORTS_ORDS /* nothing */ - -/* Existence and alternate IDs: */ -#define DT_N_S_soc_S_dma_40020000_EXISTS 1 -#define DT_N_INST_0_st_stm32_dma_v1 DT_N_S_soc_S_dma_40020000 -#define DT_N_NODELABEL_dma1 DT_N_S_soc_S_dma_40020000 - -/* Macros for properties that are special in the specification: */ -#define DT_N_S_soc_S_dma_40020000_REG_NUM 1 -#define DT_N_S_soc_S_dma_40020000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_REG_IDX_0_VAL_ADDRESS 1073872896 /* 0x40020000 */ -#define DT_N_S_soc_S_dma_40020000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ -#define DT_N_S_soc_S_dma_40020000_RANGES_NUM 0 -#define DT_N_S_soc_S_dma_40020000_FOREACH_RANGE(fn) -#define DT_N_S_soc_S_dma_40020000_IRQ_NUM 8 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_0_VAL_irq 11 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_0_VAL_irq_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_0_VAL_priority 0 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_0_VAL_priority_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_1_VAL_irq 12 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_1_VAL_irq_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_1_VAL_priority 0 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_1_VAL_priority_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_2_VAL_irq 13 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_2_VAL_irq_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_2_VAL_priority 0 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_2_VAL_priority_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_2_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_3_VAL_irq 14 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_3_VAL_irq_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_3_VAL_priority 0 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_3_VAL_priority_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_3_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_4_VAL_irq 15 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_4_VAL_irq_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_4_VAL_priority 0 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_4_VAL_priority_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_4_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_5_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_5_VAL_irq 16 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_5_VAL_irq_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_5_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_5_VAL_priority 0 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_5_VAL_priority_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_5_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_6_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_6_VAL_irq 17 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_6_VAL_irq_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_6_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_6_VAL_priority 0 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_6_VAL_priority_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_6_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_7_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_7_VAL_irq 47 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_7_VAL_irq_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_7_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_7_VAL_priority 0 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_7_VAL_priority_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_7_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 -#define DT_N_S_soc_S_dma_40020000_IRQ_LEVEL 1 -#define DT_N_S_soc_S_dma_40020000_COMPAT_MATCHES_st_stm32_dma_v1 1 -#define DT_N_S_soc_S_dma_40020000_COMPAT_VENDOR_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_COMPAT_VENDOR_IDX_0 "STMicroelectronics" -#define DT_N_S_soc_S_dma_40020000_COMPAT_MODEL_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_COMPAT_MODEL_IDX_0 "stm32-dma-v1" -#define DT_N_S_soc_S_dma_40020000_STATUS_disabled 1 - -/* Pin control (pinctrl-, pinctrl-names) properties: */ -#define DT_N_S_soc_S_dma_40020000_PINCTRL_NUM 0 - -/* Generic property macros: */ -#define DT_N_S_soc_S_dma_40020000_P_wakeup_source 0 -#define DT_N_S_soc_S_dma_40020000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_dma_40020000_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_status "disabled" -#define DT_N_S_soc_S_dma_40020000_P_status_STRING_UNQUOTED disabled -#define DT_N_S_soc_S_dma_40020000_P_status_STRING_TOKEN disabled -#define DT_N_S_soc_S_dma_40020000_P_status_STRING_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_dma_40020000_P_status_IDX_0 "disabled" -#define DT_N_S_soc_S_dma_40020000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_dma_40020000_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_dma_40020000_P_status_ENUM_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_dma_40020000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_40020000, status, 0) -#define DT_N_S_soc_S_dma_40020000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40020000, status, 0) -#define DT_N_S_soc_S_dma_40020000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40020000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dma_40020000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40020000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dma_40020000_P_status_LEN 1 -#define DT_N_S_soc_S_dma_40020000_P_status_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_compatible {"st,stm32-dma-v1"} -#define DT_N_S_soc_S_dma_40020000_P_compatible_IDX_0 "st,stm32-dma-v1" -#define DT_N_S_soc_S_dma_40020000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-dma-v1 -#define DT_N_S_soc_S_dma_40020000_P_compatible_IDX_0_STRING_TOKEN st_stm32_dma_v1 -#define DT_N_S_soc_S_dma_40020000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_DMA_V1 -#define DT_N_S_soc_S_dma_40020000_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_40020000, compatible, 0) -#define DT_N_S_soc_S_dma_40020000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40020000, compatible, 0) -#define DT_N_S_soc_S_dma_40020000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40020000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dma_40020000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40020000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dma_40020000_P_compatible_LEN 1 -#define DT_N_S_soc_S_dma_40020000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_reg {1073872896 /* 0x40020000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_dma_40020000_P_reg_IDX_0 1073872896 -#define DT_N_S_soc_S_dma_40020000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_dma_40020000_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts {11 /* 0xb */, 0 /* 0x0 */, 12 /* 0xc */, 0 /* 0x0 */, 13 /* 0xd */, 0 /* 0x0 */, 14 /* 0xe */, 0 /* 0x0 */, 15 /* 0xf */, 0 /* 0x0 */, 16 /* 0x10 */, 0 /* 0x0 */, 17 /* 0x11 */, 0 /* 0x0 */, 47 /* 0x2f */, 0 /* 0x0 */} -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_0 11 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_2 12 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_3 0 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_4 13 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_5 0 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_5_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_6 14 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_6_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_7 0 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_7_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_8 15 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_8_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_9 0 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_9_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_10 16 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_10_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_11 0 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_11_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_12 17 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_12_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_13 0 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_13_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_14 47 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_14_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_15 0 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_15_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_VAL_bus 216 -#define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_VAL_bits 1 -#define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_40020000, clocks, 0) -#define DT_N_S_soc_S_dma_40020000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40020000, clocks, 0) -#define DT_N_S_soc_S_dma_40020000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40020000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dma_40020000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40020000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dma_40020000_P_clocks_LEN 1 -#define DT_N_S_soc_S_dma_40020000_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_dma_40020000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_dma_requests 8 -#define DT_N_S_soc_S_dma_40020000_P_dma_requests_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_st_mem2mem 1 -#define DT_N_S_soc_S_dma_40020000_P_st_mem2mem_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_dma_offset 0 -#define DT_N_S_soc_S_dma_40020000_P_dma_offset_EXISTS 1 - /* * Devicetree node: /soc/dma@40020400 * @@ -14952,8 +16856,8 @@ #define DT_N_S_soc_S_dma_40020400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_dma_40020400_ORD 107 -#define DT_N_S_soc_S_dma_40020400_ORD_STR_SORTABLE 00107 +#define DT_N_S_soc_S_dma_40020400_ORD 116 +#define DT_N_S_soc_S_dma_40020400_ORD_STR_SORTABLE 00116 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_dma_40020400_REQUIRES_ORDS \ @@ -15180,8 +17084,8 @@ #define DT_N_S_soc_S_dmamux_58025800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_dmamux_58025800_ORD 108 -#define DT_N_S_soc_S_dmamux_58025800_ORD_STR_SORTABLE 00108 +#define DT_N_S_soc_S_dmamux_58025800_ORD 117 +#define DT_N_S_soc_S_dmamux_58025800_ORD_STR_SORTABLE 00117 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_dmamux_58025800_REQUIRES_ORDS \ @@ -15331,14 +17235,14 @@ #define DT_N_S_soc_S_dsihost_50000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_dsihost_50000000_ORD 109 -#define DT_N_S_soc_S_dsihost_50000000_ORD_STR_SORTABLE 00109 +#define DT_N_S_soc_S_dsihost_50000000_ORD 118 +#define DT_N_S_soc_S_dsihost_50000000_ORD_STR_SORTABLE 00118 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_dsihost_50000000_REQUIRES_ORDS \ 4, /* /soc */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ + 54, /* /soc/rcc@58024400/reset-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_dsihost_50000000_SUPPORTS_ORDS /* nothing */ @@ -15556,8 +17460,8 @@ #define DT_N_S_soc_S_dmamux_40020800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_dmamux_40020800_ORD 110 -#define DT_N_S_soc_S_dmamux_40020800_ORD_STR_SORTABLE 00110 +#define DT_N_S_soc_S_dmamux_40020800_ORD 119 +#define DT_N_S_soc_S_dmamux_40020800_ORD_STR_SORTABLE 00119 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_dmamux_40020800_REQUIRES_ORDS \ @@ -15567,9 +17471,9 @@ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_dmamux_40020800_SUPPORTS_ORDS \ - 111, /* /soc/i2s@40003800 */ \ - 112, /* /soc/i2s@40003c00 */ \ - 113, /* /soc/i2s@40013000 */ + 120, /* /soc/i2s@40003800 */ \ + 121, /* /soc/i2s@40003c00 */ \ + 122, /* /soc/i2s@40013000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_dmamux_40020800_EXISTS 1 @@ -15597,7 +17501,7 @@ #define DT_N_S_soc_S_dmamux_40020800_COMPAT_VENDOR_IDX_0 "STMicroelectronics" #define DT_N_S_soc_S_dmamux_40020800_COMPAT_MODEL_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dmamux_40020800_COMPAT_MODEL_IDX_0 "stm32-dmamux" -#define DT_N_S_soc_S_dmamux_40020800_STATUS_disabled 1 +#define DT_N_S_soc_S_dmamux_40020800_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_dmamux_40020800_PINCTRL_NUM 0 @@ -15607,16 +17511,16 @@ #define DT_N_S_soc_S_dmamux_40020800_P_wakeup_source_EXISTS 1 #define DT_N_S_soc_S_dmamux_40020800_P_zephyr_pm_device_runtime_auto 0 #define DT_N_S_soc_S_dmamux_40020800_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_dmamux_40020800_P_status "disabled" -#define DT_N_S_soc_S_dmamux_40020800_P_status_STRING_UNQUOTED disabled -#define DT_N_S_soc_S_dmamux_40020800_P_status_STRING_TOKEN disabled -#define DT_N_S_soc_S_dmamux_40020800_P_status_STRING_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_dmamux_40020800_P_status_IDX_0 "disabled" +#define DT_N_S_soc_S_dmamux_40020800_P_status "okay" +#define DT_N_S_soc_S_dmamux_40020800_P_status_STRING_UNQUOTED okay +#define DT_N_S_soc_S_dmamux_40020800_P_status_STRING_TOKEN okay +#define DT_N_S_soc_S_dmamux_40020800_P_status_STRING_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_dmamux_40020800_P_status_IDX_0 "okay" #define DT_N_S_soc_S_dmamux_40020800_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dmamux_40020800_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_dmamux_40020800_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_dmamux_40020800_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_dmamux_40020800_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_dmamux_40020800_P_status_ENUM_IDX 1 +#define DT_N_S_soc_S_dmamux_40020800_P_status_ENUM_VAL_okay_EXISTS 1 +#define DT_N_S_soc_S_dmamux_40020800_P_status_ENUM_TOKEN okay +#define DT_N_S_soc_S_dmamux_40020800_P_status_ENUM_UPPER_TOKEN OKAY #define DT_N_S_soc_S_dmamux_40020800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dmamux_40020800, status, 0) #define DT_N_S_soc_S_dmamux_40020800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dmamux_40020800, status, 0) #define DT_N_S_soc_S_dmamux_40020800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dmamux_40020800, status, 0, __VA_ARGS__) @@ -15710,15 +17614,15 @@ #define DT_N_S_soc_S_i2s_40003800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_i2s_40003800_ORD 111 -#define DT_N_S_soc_S_i2s_40003800_ORD_STR_SORTABLE 00111 +#define DT_N_S_soc_S_i2s_40003800_ORD 120 +#define DT_N_S_soc_S_i2s_40003800_ORD_STR_SORTABLE 00120 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_i2s_40003800_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 110, /* /soc/dmamux@40020800 */ + 119, /* /soc/dmamux@40020800 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_i2s_40003800_SUPPORTS_ORDS /* nothing */ @@ -15948,15 +17852,15 @@ #define DT_N_S_soc_S_i2s_40003c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_i2s_40003c00_ORD 112 -#define DT_N_S_soc_S_i2s_40003c00_ORD_STR_SORTABLE 00112 +#define DT_N_S_soc_S_i2s_40003c00_ORD 121 +#define DT_N_S_soc_S_i2s_40003c00_ORD_STR_SORTABLE 00121 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_i2s_40003c00_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 110, /* /soc/dmamux@40020800 */ + 119, /* /soc/dmamux@40020800 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_i2s_40003c00_SUPPORTS_ORDS /* nothing */ @@ -16186,15 +18090,15 @@ #define DT_N_S_soc_S_i2s_40013000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_i2s_40013000_ORD 113 -#define DT_N_S_soc_S_i2s_40013000_ORD_STR_SORTABLE 00113 +#define DT_N_S_soc_S_i2s_40013000_ORD 122 +#define DT_N_S_soc_S_i2s_40013000_ORD_STR_SORTABLE 00122 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_i2s_40013000_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 110, /* /soc/dmamux@40020800 */ + 119, /* /soc/dmamux@40020800 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_i2s_40013000_SUPPORTS_ORDS /* nothing */ @@ -16424,8 +18328,8 @@ #define DT_N_S_soc_S_interrupt_controller_58000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_interrupt_controller_58000000_ORD 114 -#define DT_N_S_soc_S_interrupt_controller_58000000_ORD_STR_SORTABLE 00114 +#define DT_N_S_soc_S_interrupt_controller_58000000_ORD 123 +#define DT_N_S_soc_S_interrupt_controller_58000000_ORD_STR_SORTABLE 00123 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_interrupt_controller_58000000_REQUIRES_ORDS \ @@ -16798,8 +18702,8 @@ #define DT_N_S_soc_S_mailbox_58026400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_mailbox_58026400_ORD 115 -#define DT_N_S_soc_S_mailbox_58026400_ORD_STR_SORTABLE 00115 +#define DT_N_S_soc_S_mailbox_58026400_ORD 124 +#define DT_N_S_soc_S_mailbox_58026400_ORD_STR_SORTABLE 00124 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_mailbox_58026400_REQUIRES_ORDS \ @@ -16958,8 +18862,8 @@ #define DT_N_S_soc_S_memory_38800000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_memory_38800000_ORD 116 -#define DT_N_S_soc_S_memory_38800000_ORD_STR_SORTABLE 00116 +#define DT_N_S_soc_S_memory_38800000_ORD 125 +#define DT_N_S_soc_S_memory_38800000_ORD_STR_SORTABLE 00125 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_memory_38800000_REQUIRES_ORDS \ @@ -17116,8 +19020,8 @@ #define DT_N_S_soc_S_rng_48021800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_rng_48021800_ORD 117 -#define DT_N_S_soc_S_rng_48021800_ORD_STR_SORTABLE 00117 +#define DT_N_S_soc_S_rng_48021800_ORD 126 +#define DT_N_S_soc_S_rng_48021800_ORD_STR_SORTABLE 00126 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_rng_48021800_REQUIRES_ORDS \ @@ -17261,15 +19165,15 @@ #define DT_N_S_soc_S_sdmmc_48022400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_sdmmc_48022400_ORD 118 -#define DT_N_S_soc_S_sdmmc_48022400_ORD_STR_SORTABLE 00118 +#define DT_N_S_soc_S_sdmmc_48022400_ORD 127 +#define DT_N_S_soc_S_sdmmc_48022400_ORD_STR_SORTABLE 00127 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_sdmmc_48022400_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ + 54, /* /soc/rcc@58024400/reset-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_sdmmc_48022400_SUPPORTS_ORDS /* nothing */ @@ -17435,15 +19339,15 @@ #define DT_N_S_soc_S_sdmmc_52007000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_sdmmc_52007000_ORD 119 -#define DT_N_S_soc_S_sdmmc_52007000_ORD_STR_SORTABLE 00119 +#define DT_N_S_soc_S_sdmmc_52007000_ORD 128 +#define DT_N_S_soc_S_sdmmc_52007000_ORD_STR_SORTABLE 00128 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_sdmmc_52007000_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ + 54, /* /soc/rcc@58024400/reset-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_sdmmc_52007000_SUPPORTS_ORDS /* nothing */ @@ -17609,15 +19513,15 @@ #define DT_N_S_soc_S_serial_40004400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_serial_40004400_ORD 120 -#define DT_N_S_soc_S_serial_40004400_ORD_STR_SORTABLE 00120 +#define DT_N_S_soc_S_serial_40004400_ORD 129 +#define DT_N_S_soc_S_serial_40004400_ORD_STR_SORTABLE 00129 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_serial_40004400_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ + 54, /* /soc/rcc@58024400/reset-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_serial_40004400_SUPPORTS_ORDS /* nothing */ @@ -17800,15 +19704,15 @@ #define DT_N_S_soc_S_serial_40004800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_serial_40004800_ORD 121 -#define DT_N_S_soc_S_serial_40004800_ORD_STR_SORTABLE 00121 +#define DT_N_S_soc_S_serial_40004800_ORD 130 +#define DT_N_S_soc_S_serial_40004800_ORD_STR_SORTABLE 00130 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_serial_40004800_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ + 54, /* /soc/rcc@58024400/reset-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_serial_40004800_SUPPORTS_ORDS /* nothing */ @@ -17968,7 +19872,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_CHILD_IDX 85 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_CHILD_IDX 103 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_NODELABEL_NUM 1 @@ -17988,16 +19892,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_ORD 122 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_ORD_STR_SORTABLE 00122 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_ORD 131 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_ORD_STR_SORTABLE 00131 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_SUPPORTS_ORDS \ - 124, /* /soc/serial@40004c00 */ + 133, /* /soc/serial@40004c00 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_EXISTS 1 @@ -18067,7 +19971,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_CHILD_IDX 89 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_CHILD_IDX 107 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_NODELABEL_NUM 1 @@ -18087,16 +19991,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_ORD 123 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_ORD_STR_SORTABLE 00123 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_ORD 132 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_ORD_STR_SORTABLE 00132 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_SUPPORTS_ORDS \ - 124, /* /soc/serial@40004c00 */ + 133, /* /soc/serial@40004c00 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_EXISTS 1 @@ -18189,17 +20093,17 @@ #define DT_N_S_soc_S_serial_40004c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_serial_40004c00_ORD 124 -#define DT_N_S_soc_S_serial_40004c00_ORD_STR_SORTABLE 00124 +#define DT_N_S_soc_S_serial_40004c00_ORD 133 +#define DT_N_S_soc_S_serial_40004c00_ORD_STR_SORTABLE 00133 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_serial_40004c00_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ \ - 122, /* /soc/pin-controller@58020000/uart4_rx_pi9 */ \ - 123, /* /soc/pin-controller@58020000/uart4_tx_ph13 */ + 54, /* /soc/rcc@58024400/reset-controller */ \ + 131, /* /soc/pin-controller@58020000/uart4_rx_pi9 */ \ + 132, /* /soc/pin-controller@58020000/uart4_tx_ph13 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_serial_40004c00_SUPPORTS_ORDS /* nothing */ @@ -18404,15 +20308,15 @@ #define DT_N_S_soc_S_serial_40005000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_serial_40005000_ORD 125 -#define DT_N_S_soc_S_serial_40005000_ORD_STR_SORTABLE 00125 +#define DT_N_S_soc_S_serial_40005000_ORD 134 +#define DT_N_S_soc_S_serial_40005000_ORD_STR_SORTABLE 00134 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_serial_40005000_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ + 54, /* /soc/rcc@58024400/reset-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_serial_40005000_SUPPORTS_ORDS /* nothing */ @@ -18580,15 +20484,15 @@ #define DT_N_S_soc_S_serial_40007c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_serial_40007c00_ORD 126 -#define DT_N_S_soc_S_serial_40007c00_ORD_STR_SORTABLE 00126 +#define DT_N_S_soc_S_serial_40007c00_ORD 135 +#define DT_N_S_soc_S_serial_40007c00_ORD_STR_SORTABLE 00135 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_serial_40007c00_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ + 54, /* /soc/rcc@58024400/reset-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_serial_40007c00_SUPPORTS_ORDS /* nothing */ @@ -18756,15 +20660,15 @@ #define DT_N_S_soc_S_serial_58000c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_serial_58000c00_ORD 127 -#define DT_N_S_soc_S_serial_58000c00_ORD_STR_SORTABLE 00127 +#define DT_N_S_soc_S_serial_58000c00_ORD 136 +#define DT_N_S_soc_S_serial_58000c00_ORD_STR_SORTABLE 00136 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_serial_58000c00_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ + 54, /* /soc/rcc@58024400/reset-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_serial_58000c00_SUPPORTS_ORDS /* nothing */ @@ -18947,8 +20851,8 @@ #define DT_N_S_soc_S_spi_40003800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_spi_40003800_ORD 128 -#define DT_N_S_soc_S_spi_40003800_ORD_STR_SORTABLE 00128 +#define DT_N_S_soc_S_spi_40003800_ORD 137 +#define DT_N_S_soc_S_spi_40003800_ORD_STR_SORTABLE 00137 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_spi_40003800_REQUIRES_ORDS \ @@ -19138,8 +21042,8 @@ #define DT_N_S_soc_S_spi_40003c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_spi_40003c00_ORD 129 -#define DT_N_S_soc_S_spi_40003c00_ORD_STR_SORTABLE 00129 +#define DT_N_S_soc_S_spi_40003c00_ORD 138 +#define DT_N_S_soc_S_spi_40003c00_ORD_STR_SORTABLE 00138 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_spi_40003c00_REQUIRES_ORDS \ @@ -19329,8 +21233,8 @@ #define DT_N_S_soc_S_spi_40013400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_spi_40013400_ORD 130 -#define DT_N_S_soc_S_spi_40013400_ORD_STR_SORTABLE 00130 +#define DT_N_S_soc_S_spi_40013400_ORD 139 +#define DT_N_S_soc_S_spi_40013400_ORD_STR_SORTABLE 00139 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_spi_40013400_REQUIRES_ORDS \ @@ -19510,8 +21414,8 @@ #define DT_N_S_soc_S_spi_58001400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_spi_58001400_ORD 131 -#define DT_N_S_soc_S_spi_58001400_ORD_STR_SORTABLE 00131 +#define DT_N_S_soc_S_spi_58001400_ORD 140 +#define DT_N_S_soc_S_spi_58001400_ORD_STR_SORTABLE 00140 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_spi_58001400_REQUIRES_ORDS \ @@ -19691,8 +21595,8 @@ #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timer_e000e010_ORD 132 -#define DT_N_S_soc_S_timer_e000e010_ORD_STR_SORTABLE 00132 +#define DT_N_S_soc_S_timer_e000e010_ORD 141 +#define DT_N_S_soc_S_timer_e000e010_ORD_STR_SORTABLE 00141 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timer_e000e010_REQUIRES_ORDS \ @@ -19793,8 +21697,8 @@ #define DT_N_S_soc_S_timers_40002400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40002400_ORD 133 -#define DT_N_S_soc_S_timers_40002400_ORD_STR_SORTABLE 00133 +#define DT_N_S_soc_S_timers_40002400_ORD 142 +#define DT_N_S_soc_S_timers_40002400_ORD_STR_SORTABLE 00142 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40002400_REQUIRES_ORDS \ @@ -19959,15 +21863,15 @@ #define DT_N_S_soc_S_usb_40040000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_usb_40040000_ORD 134 -#define DT_N_S_soc_S_usb_40040000_ORD_STR_SORTABLE 00134 +#define DT_N_S_soc_S_usb_40040000_ORD 143 +#define DT_N_S_soc_S_usb_40040000_ORD_STR_SORTABLE 00143 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_usb_40040000_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 71, /* /otghs_fs_phy */ + 82, /* /otghs_fs_phy */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_usb_40040000_SUPPORTS_ORDS /* nothing */ @@ -20237,8 +22141,8 @@ #define DT_N_S_soc_S_watchdog_50003000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_watchdog_50003000_ORD 135 -#define DT_N_S_soc_S_watchdog_50003000_ORD_STR_SORTABLE 00135 +#define DT_N_S_soc_S_watchdog_50003000_ORD 144 +#define DT_N_S_soc_S_watchdog_50003000_ORD_STR_SORTABLE 00144 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_watchdog_50003000_REQUIRES_ORDS \ @@ -20383,8 +22287,8 @@ #define DT_N_S_soc_S_watchdog_58004800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_watchdog_58004800_ORD 136 -#define DT_N_S_soc_S_watchdog_58004800_ORD_STR_SORTABLE 00136 +#define DT_N_S_soc_S_watchdog_58004800_ORD 145 +#define DT_N_S_soc_S_watchdog_58004800_ORD_STR_SORTABLE 00145 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_watchdog_58004800_REQUIRES_ORDS \ @@ -20460,6 +22364,224 @@ #define DT_N_S_soc_S_watchdog_58004800_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_watchdog_58004800_P_zephyr_deferred_init_EXISTS 1 +/* + * Devicetree node: /soc/adc@40022000/channel@0 + * + * Node identifier: DT_N_S_soc_S_adc_40022000_S_channel_0 + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_0_PATH "/soc/adc@40022000/channel@0" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_0_FULL_NAME "channel@0" + +/* Node parent (/soc/adc@40022000) identifier: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_0_PARENT DT_N_S_soc_S_adc_40022000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_0_CHILD_IDX 10 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_0_NODELABEL_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_FOREACH_NODELABEL(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_0_FOREACH_NODELABEL_VARGS(fn, ...) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_adc_40022000_S_channel_0_CHILD_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_0_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_adc_40022000_S_channel_0_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_adc_40022000_S_channel_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_adc_40022000_S_channel_0_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_adc_40022000_S_channel_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_adc_40022000_S_channel_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_0_ORD 146 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_ORD_STR_SORTABLE 00146 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_0_REQUIRES_ORDS \ + 51, /* /soc/adc@40022000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_0_SUPPORTS_ORDS /* nothing */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_0_EXISTS 1 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_0_REG_NUM 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_REG_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */ +#define DT_N_S_soc_S_adc_40022000_S_channel_0_RANGES_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_0_IRQ_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_IRQ_LEVEL 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_0_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_reg {0 /* 0x0 */} +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_reg_IDX_0 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_reg_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain "ADC_GAIN_1" +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_STRING_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_IDX_0 "ADC_GAIN_1" +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_ENUM_IDX 8 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_0, zephyr_gain, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_0, zephyr_gain, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_0, zephyr_gain, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_0, zephyr_gain, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_LEN 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference "ADC_REF_INTERNAL" +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_STRING_UNQUOTED ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_STRING_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_ENUM_IDX 4 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_0, zephyr_reference, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_0, zephyr_reference, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_0, zephyr_reference, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_0, zephyr_reference, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_LEN 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_acquisition_time 16383 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_acquisition_time_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_differential 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_differential_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_resolution 12 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_resolution_EXISTS 1 + +/* + * Devicetree node: /soc/adc@40022000/channel@1 + * + * Node identifier: DT_N_S_soc_S_adc_40022000_S_channel_1 + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_1_PATH "/soc/adc@40022000/channel@1" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_1_FULL_NAME "channel@1" + +/* Node parent (/soc/adc@40022000) identifier: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_1_PARENT DT_N_S_soc_S_adc_40022000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_1_CHILD_IDX 11 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_1_NODELABEL_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_FOREACH_NODELABEL(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_1_FOREACH_NODELABEL_VARGS(fn, ...) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_adc_40022000_S_channel_1_CHILD_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_1_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_adc_40022000_S_channel_1_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_adc_40022000_S_channel_1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_adc_40022000_S_channel_1_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_adc_40022000_S_channel_1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_adc_40022000_S_channel_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_1_ORD 147 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_ORD_STR_SORTABLE 00147 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_1_REQUIRES_ORDS \ + 51, /* /soc/adc@40022000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_1_SUPPORTS_ORDS /* nothing */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_1_EXISTS 1 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_1_REG_NUM 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_REG_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_REG_IDX_0_VAL_ADDRESS 1 /* 0x1 */ +#define DT_N_S_soc_S_adc_40022000_S_channel_1_RANGES_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_1_IRQ_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_IRQ_LEVEL 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_1_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_reg {1 /* 0x1 */} +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_reg_IDX_0 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_reg_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain "ADC_GAIN_1" +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_STRING_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_IDX_0 "ADC_GAIN_1" +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_ENUM_IDX 8 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_1, zephyr_gain, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_1, zephyr_gain, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_1, zephyr_gain, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_1, zephyr_gain, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_LEN 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference "ADC_REF_INTERNAL" +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_STRING_UNQUOTED ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_STRING_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_ENUM_IDX 4 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_1, zephyr_reference, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_1, zephyr_reference, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_1, zephyr_reference, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_1, zephyr_reference, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_LEN 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_acquisition_time 16383 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_acquisition_time_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_differential 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_differential_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_resolution 12 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_resolution_EXISTS 1 + /* * Devicetree node: /soc/adc@40022000/channel@4 * @@ -20499,12 +22621,12 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_4_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_4_ORD 137 -#define DT_N_S_soc_S_adc_40022000_S_channel_4_ORD_STR_SORTABLE 00137 +#define DT_N_S_soc_S_adc_40022000_S_channel_4_ORD 148 +#define DT_N_S_soc_S_adc_40022000_S_channel_4_ORD_STR_SORTABLE 00148 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_40022000_S_channel_4_REQUIRES_ORDS \ - 44, /* /soc/adc@40022000 */ + 51, /* /soc/adc@40022000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_40022000_S_channel_4_SUPPORTS_ORDS /* nothing */ @@ -20608,12 +22730,12 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_5_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_5_ORD 138 -#define DT_N_S_soc_S_adc_40022000_S_channel_5_ORD_STR_SORTABLE 00138 +#define DT_N_S_soc_S_adc_40022000_S_channel_5_ORD 149 +#define DT_N_S_soc_S_adc_40022000_S_channel_5_ORD_STR_SORTABLE 00149 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_40022000_S_channel_5_REQUIRES_ORDS \ - 44, /* /soc/adc@40022000 */ + 51, /* /soc/adc@40022000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_40022000_S_channel_5_SUPPORTS_ORDS /* nothing */ @@ -20717,12 +22839,12 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_8_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_8_ORD 139 -#define DT_N_S_soc_S_adc_40022000_S_channel_8_ORD_STR_SORTABLE 00139 +#define DT_N_S_soc_S_adc_40022000_S_channel_8_ORD 150 +#define DT_N_S_soc_S_adc_40022000_S_channel_8_ORD_STR_SORTABLE 00150 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_40022000_S_channel_8_REQUIRES_ORDS \ - 44, /* /soc/adc@40022000 */ + 51, /* /soc/adc@40022000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_40022000_S_channel_8_SUPPORTS_ORDS /* nothing */ @@ -20826,12 +22948,12 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_9_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_9_ORD 140 -#define DT_N_S_soc_S_adc_40022000_S_channel_9_ORD_STR_SORTABLE 00140 +#define DT_N_S_soc_S_adc_40022000_S_channel_9_ORD 151 +#define DT_N_S_soc_S_adc_40022000_S_channel_9_ORD_STR_SORTABLE 00151 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_40022000_S_channel_9_REQUIRES_ORDS \ - 44, /* /soc/adc@40022000 */ + 51, /* /soc/adc@40022000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_40022000_S_channel_9_SUPPORTS_ORDS /* nothing */ @@ -20896,6 +23018,333 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_resolution 12 #define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_resolution_EXISTS 1 +/* + * Devicetree node: /soc/adc@40022000/channel@a + * + * Node identifier: DT_N_S_soc_S_adc_40022000_S_channel_a + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_a_PATH "/soc/adc@40022000/channel@a" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_a_FULL_NAME "channel@a" + +/* Node parent (/soc/adc@40022000) identifier: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_a_PARENT DT_N_S_soc_S_adc_40022000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_a_CHILD_IDX 6 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_a_NODELABEL_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_FOREACH_NODELABEL(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_a_FOREACH_NODELABEL_VARGS(fn, ...) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_adc_40022000_S_channel_a_CHILD_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_a_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_adc_40022000_S_channel_a_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_adc_40022000_S_channel_a_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_adc_40022000_S_channel_a_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_a_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_adc_40022000_S_channel_a_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_adc_40022000_S_channel_a_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_a_ORD 152 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_ORD_STR_SORTABLE 00152 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_a_REQUIRES_ORDS \ + 51, /* /soc/adc@40022000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_a_SUPPORTS_ORDS /* nothing */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_a_EXISTS 1 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_a_REG_NUM 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_REG_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_REG_IDX_0_VAL_ADDRESS 10 /* 0xa */ +#define DT_N_S_soc_S_adc_40022000_S_channel_a_RANGES_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_a_IRQ_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_IRQ_LEVEL 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_a_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_reg {10 /* 0xa */} +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_reg_IDX_0 10 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_reg_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain "ADC_GAIN_1" +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_STRING_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_IDX_0 "ADC_GAIN_1" +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_ENUM_IDX 8 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_a, zephyr_gain, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_a, zephyr_gain, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_a, zephyr_gain, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_a, zephyr_gain, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_LEN 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference "ADC_REF_INTERNAL" +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_STRING_UNQUOTED ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_STRING_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_ENUM_IDX 4 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_a, zephyr_reference, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_a, zephyr_reference, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_a, zephyr_reference, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_a, zephyr_reference, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_LEN 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_acquisition_time 16383 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_acquisition_time_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_differential 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_differential_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_resolution 12 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_resolution_EXISTS 1 + +/* + * Devicetree node: /soc/adc@40022000/channel@c + * + * Node identifier: DT_N_S_soc_S_adc_40022000_S_channel_c + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_c_PATH "/soc/adc@40022000/channel@c" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_c_FULL_NAME "channel@c" + +/* Node parent (/soc/adc@40022000) identifier: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_c_PARENT DT_N_S_soc_S_adc_40022000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_c_CHILD_IDX 5 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_c_NODELABEL_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_FOREACH_NODELABEL(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_c_FOREACH_NODELABEL_VARGS(fn, ...) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_adc_40022000_S_channel_c_CHILD_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_c_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_adc_40022000_S_channel_c_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_adc_40022000_S_channel_c_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_adc_40022000_S_channel_c_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_c_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_adc_40022000_S_channel_c_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_adc_40022000_S_channel_c_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_c_ORD 153 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_ORD_STR_SORTABLE 00153 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_c_REQUIRES_ORDS \ + 51, /* /soc/adc@40022000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_c_SUPPORTS_ORDS /* nothing */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_c_EXISTS 1 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_c_REG_NUM 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_REG_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_REG_IDX_0_VAL_ADDRESS 12 /* 0xc */ +#define DT_N_S_soc_S_adc_40022000_S_channel_c_RANGES_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_c_IRQ_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_IRQ_LEVEL 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_c_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_reg {12 /* 0xc */} +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_reg_IDX_0 12 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_reg_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain "ADC_GAIN_1" +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_STRING_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_IDX_0 "ADC_GAIN_1" +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_ENUM_IDX 8 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_c, zephyr_gain, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_c, zephyr_gain, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_c, zephyr_gain, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_c, zephyr_gain, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_LEN 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference "ADC_REF_INTERNAL" +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_STRING_UNQUOTED ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_STRING_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_ENUM_IDX 4 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_c, zephyr_reference, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_c, zephyr_reference, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_c, zephyr_reference, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_c, zephyr_reference, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_LEN 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_acquisition_time 16383 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_acquisition_time_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_differential 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_differential_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_resolution 12 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_resolution_EXISTS 1 + +/* + * Devicetree node: /soc/adc@40022000/channel@d + * + * Node identifier: DT_N_S_soc_S_adc_40022000_S_channel_d + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_d_PATH "/soc/adc@40022000/channel@d" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_d_FULL_NAME "channel@d" + +/* Node parent (/soc/adc@40022000) identifier: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_d_PARENT DT_N_S_soc_S_adc_40022000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_d_CHILD_IDX 4 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_d_NODELABEL_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_FOREACH_NODELABEL(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_d_FOREACH_NODELABEL_VARGS(fn, ...) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_adc_40022000_S_channel_d_CHILD_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_d_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_adc_40022000_S_channel_d_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_adc_40022000_S_channel_d_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_adc_40022000_S_channel_d_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_d_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_adc_40022000_S_channel_d_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_adc_40022000_S_channel_d_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_d_ORD 154 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_ORD_STR_SORTABLE 00154 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_d_REQUIRES_ORDS \ + 51, /* /soc/adc@40022000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_d_SUPPORTS_ORDS /* nothing */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_d_EXISTS 1 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_d_REG_NUM 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_REG_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_REG_IDX_0_VAL_ADDRESS 13 /* 0xd */ +#define DT_N_S_soc_S_adc_40022000_S_channel_d_RANGES_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_d_IRQ_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_IRQ_LEVEL 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_d_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_reg {13 /* 0xd */} +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_reg_IDX_0 13 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_reg_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain "ADC_GAIN_1" +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_STRING_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_IDX_0 "ADC_GAIN_1" +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_ENUM_IDX 8 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_d, zephyr_gain, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_d, zephyr_gain, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_d, zephyr_gain, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_d, zephyr_gain, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_LEN 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference "ADC_REF_INTERNAL" +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_STRING_UNQUOTED ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_STRING_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_ENUM_IDX 4 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_d, zephyr_reference, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_d, zephyr_reference, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_d, zephyr_reference, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_d, zephyr_reference, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_LEN 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_acquisition_time 16383 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_acquisition_time_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_differential 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_differential_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_resolution 12 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_resolution_EXISTS 1 + /* * Devicetree node: /soc/adc@40022000/channel@10 * @@ -20915,7 +23364,7 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_10_PARENT DT_N_S_soc_S_adc_40022000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_10_CHILD_IDX 6 +#define DT_N_S_soc_S_adc_40022000_S_channel_10_CHILD_IDX 7 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_adc_40022000_S_channel_10_NODELABEL_NUM 0 @@ -20935,12 +23384,12 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_10_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_10_ORD 141 -#define DT_N_S_soc_S_adc_40022000_S_channel_10_ORD_STR_SORTABLE 00141 +#define DT_N_S_soc_S_adc_40022000_S_channel_10_ORD 155 +#define DT_N_S_soc_S_adc_40022000_S_channel_10_ORD_STR_SORTABLE 00155 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_40022000_S_channel_10_REQUIRES_ORDS \ - 44, /* /soc/adc@40022000 */ + 51, /* /soc/adc@40022000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_40022000_S_channel_10_SUPPORTS_ORDS /* nothing */ @@ -20951,7 +23400,7 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_adc_40022000_S_channel_10_REG_NUM 1 #define DT_N_S_soc_S_adc_40022000_S_channel_10_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_10_REG_IDX_0_VAL_ADDRESS 10 /* 0xa */ +#define DT_N_S_soc_S_adc_40022000_S_channel_10_REG_IDX_0_VAL_ADDRESS 16 /* 0x10 */ #define DT_N_S_soc_S_adc_40022000_S_channel_10_RANGES_NUM 0 #define DT_N_S_soc_S_adc_40022000_S_channel_10_FOREACH_RANGE(fn) #define DT_N_S_soc_S_adc_40022000_S_channel_10_IRQ_NUM 0 @@ -20962,8 +23411,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_10_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_10_P_reg {10 /* 0xa */} -#define DT_N_S_soc_S_adc_40022000_S_channel_10_P_reg_IDX_0 10 +#define DT_N_S_soc_S_adc_40022000_S_channel_10_P_reg {16 /* 0x10 */} +#define DT_N_S_soc_S_adc_40022000_S_channel_10_P_reg_IDX_0 16 #define DT_N_S_soc_S_adc_40022000_S_channel_10_P_reg_IDX_0_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_10_P_reg_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_gain "ADC_GAIN_1" @@ -21006,331 +23455,2344 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_resolution_EXISTS 1 /* - * Devicetree node: /soc/adc@40022000/channel@12 + * Devicetree node: /soc/adc@40022000/channel@12 + * + * Node identifier: DT_N_S_soc_S_adc_40022000_S_channel_12 + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_12_PATH "/soc/adc@40022000/channel@12" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_12_FULL_NAME "channel@12" + +/* Node parent (/soc/adc@40022000) identifier: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_12_PARENT DT_N_S_soc_S_adc_40022000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_12_CHILD_IDX 8 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_12_NODELABEL_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_NODELABEL(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_NODELABEL_VARGS(fn, ...) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_adc_40022000_S_channel_12_CHILD_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_12_ORD 156 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_ORD_STR_SORTABLE 00156 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_12_REQUIRES_ORDS \ + 51, /* /soc/adc@40022000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_12_SUPPORTS_ORDS /* nothing */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_12_EXISTS 1 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_12_REG_NUM 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_REG_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_REG_IDX_0_VAL_ADDRESS 18 /* 0x12 */ +#define DT_N_S_soc_S_adc_40022000_S_channel_12_RANGES_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_12_IRQ_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_IRQ_LEVEL 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_12_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_reg {18 /* 0x12 */} +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_reg_IDX_0 18 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_reg_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain "ADC_GAIN_1" +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_STRING_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_IDX_0 "ADC_GAIN_1" +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_ENUM_IDX 8 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, zephyr_gain, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, zephyr_gain, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, zephyr_gain, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, zephyr_gain, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_LEN 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference "ADC_REF_INTERNAL" +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_STRING_UNQUOTED ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_STRING_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_ENUM_IDX 4 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, zephyr_reference, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, zephyr_reference, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, zephyr_reference, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, zephyr_reference, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_LEN 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_acquisition_time 16383 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_acquisition_time_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_differential 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_differential_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_resolution 12 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_resolution_EXISTS 1 + +/* + * Devicetree node: /soc/adc@40022000/channel@13 + * + * Node identifier: DT_N_S_soc_S_adc_40022000_S_channel_13 + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_13_PATH "/soc/adc@40022000/channel@13" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_13_FULL_NAME "channel@13" + +/* Node parent (/soc/adc@40022000) identifier: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_13_PARENT DT_N_S_soc_S_adc_40022000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_13_CHILD_IDX 9 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_13_NODELABEL_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_NODELABEL(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_NODELABEL_VARGS(fn, ...) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_adc_40022000_S_channel_13_CHILD_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_13_ORD 157 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_ORD_STR_SORTABLE 00157 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_13_REQUIRES_ORDS \ + 51, /* /soc/adc@40022000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_13_SUPPORTS_ORDS /* nothing */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_13_EXISTS 1 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_13_REG_NUM 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_REG_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_REG_IDX_0_VAL_ADDRESS 19 /* 0x13 */ +#define DT_N_S_soc_S_adc_40022000_S_channel_13_RANGES_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_adc_40022000_S_channel_13_IRQ_NUM 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_IRQ_LEVEL 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_13_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_reg {19 /* 0x13 */} +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_reg_IDX_0 19 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_reg_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain "ADC_GAIN_1" +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_STRING_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_IDX_0 "ADC_GAIN_1" +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_ENUM_IDX 8 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, zephyr_gain, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, zephyr_gain, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, zephyr_gain, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, zephyr_gain, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_LEN 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference "ADC_REF_INTERNAL" +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_STRING_UNQUOTED ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_STRING_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_ENUM_IDX 4 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, zephyr_reference, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, zephyr_reference, 0) +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, zephyr_reference, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, zephyr_reference, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_LEN 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_acquisition_time 16383 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_acquisition_time_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_differential 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_differential_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_resolution 12 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_resolution_EXISTS 1 + +/* + * Devicetree node: /soc/adc@58026000/channel@0 + * + * Node identifier: DT_N_S_soc_S_adc_58026000_S_channel_0 + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_0_PATH "/soc/adc@58026000/channel@0" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_0_FULL_NAME "channel@0" + +/* Node parent (/soc/adc@58026000) identifier: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_0_PARENT DT_N_S_soc_S_adc_58026000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_0_CHILD_IDX 0 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_0_NODELABEL_NUM 0 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_FOREACH_NODELABEL(fn) +#define DT_N_S_soc_S_adc_58026000_S_channel_0_FOREACH_NODELABEL_VARGS(fn, ...) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_adc_58026000_S_channel_0_CHILD_NUM 0 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_adc_58026000_S_channel_0_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_adc_58026000_S_channel_0_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_adc_58026000_S_channel_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_adc_58026000_S_channel_0_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_adc_58026000_S_channel_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_adc_58026000_S_channel_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_adc_58026000_S_channel_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_0_ORD 158 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_ORD_STR_SORTABLE 00158 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_0_REQUIRES_ORDS \ + 13, /* /soc/adc@58026000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_0_SUPPORTS_ORDS /* nothing */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_0_EXISTS 1 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_0_REG_NUM 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_REG_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */ +#define DT_N_S_soc_S_adc_58026000_S_channel_0_RANGES_NUM 0 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_adc_58026000_S_channel_0_IRQ_NUM 0 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_IRQ_LEVEL 0 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_0_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_reg {0 /* 0x0 */} +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_reg_IDX_0 0 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_reg_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain "ADC_GAIN_1" +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_STRING_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_IDX_0 "ADC_GAIN_1" +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_ENUM_IDX 8 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, zephyr_gain, 0) +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, zephyr_gain, 0) +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, zephyr_gain, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, zephyr_gain, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_LEN 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference "ADC_REF_INTERNAL" +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_STRING_UNQUOTED ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_STRING_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_ENUM_IDX 4 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, zephyr_reference, 0) +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, zephyr_reference, 0) +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, zephyr_reference, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, zephyr_reference, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_LEN 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_acquisition_time 16383 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_acquisition_time_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_differential 0 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_differential_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_resolution 12 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_resolution_EXISTS 1 + +/* + * Devicetree node: /soc/adc@58026000/channel@1 + * + * Node identifier: DT_N_S_soc_S_adc_58026000_S_channel_1 + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_1_PATH "/soc/adc@58026000/channel@1" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_1_FULL_NAME "channel@1" + +/* Node parent (/soc/adc@58026000) identifier: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_1_PARENT DT_N_S_soc_S_adc_58026000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_1_CHILD_IDX 1 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_1_NODELABEL_NUM 0 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_FOREACH_NODELABEL(fn) +#define DT_N_S_soc_S_adc_58026000_S_channel_1_FOREACH_NODELABEL_VARGS(fn, ...) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_adc_58026000_S_channel_1_CHILD_NUM 0 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_adc_58026000_S_channel_1_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_adc_58026000_S_channel_1_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_adc_58026000_S_channel_1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_adc_58026000_S_channel_1_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_adc_58026000_S_channel_1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_adc_58026000_S_channel_1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_adc_58026000_S_channel_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_1_ORD 159 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_ORD_STR_SORTABLE 00159 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_1_REQUIRES_ORDS \ + 13, /* /soc/adc@58026000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_1_SUPPORTS_ORDS /* nothing */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_1_EXISTS 1 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_1_REG_NUM 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_REG_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_REG_IDX_0_VAL_ADDRESS 1 /* 0x1 */ +#define DT_N_S_soc_S_adc_58026000_S_channel_1_RANGES_NUM 0 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_adc_58026000_S_channel_1_IRQ_NUM 0 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_IRQ_LEVEL 0 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_1_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_reg {1 /* 0x1 */} +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_reg_IDX_0 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_reg_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain "ADC_GAIN_1" +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_STRING_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_IDX_0 "ADC_GAIN_1" +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_ENUM_IDX 8 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_58026000_S_channel_1, zephyr_gain, 0) +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_58026000_S_channel_1, zephyr_gain, 0) +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_58026000_S_channel_1, zephyr_gain, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_58026000_S_channel_1, zephyr_gain, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_LEN 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference "ADC_REF_INTERNAL" +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_STRING_UNQUOTED ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_STRING_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_ENUM_IDX 4 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_58026000_S_channel_1, zephyr_reference, 0) +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_58026000_S_channel_1, zephyr_reference, 0) +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_58026000_S_channel_1, zephyr_reference, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_58026000_S_channel_1, zephyr_reference, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_LEN 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_acquisition_time 16383 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_acquisition_time_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_differential 0 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_differential_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_resolution 12 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_resolution_EXISTS 1 + +/* + * Devicetree node: /soc/dma@40020000 + * + * Node identifier: DT_N_S_soc_S_dma_40020000 + * + * Binding (compatible = st,stm32-dma-v1): + * $ZEPHYR_BASE/dts/bindings/dma/st,stm32-dma-v1.yaml + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_dma_40020000_PATH "/soc/dma@40020000" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_dma_40020000_FULL_NAME "dma@40020000" + +/* Node parent (/soc) identifier: */ +#define DT_N_S_soc_S_dma_40020000_PARENT DT_N_S_soc + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_dma_40020000_CHILD_IDX 53 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_dma_40020000_NODELABEL_NUM 1 +#define DT_N_S_soc_S_dma_40020000_FOREACH_NODELABEL(fn) fn(dma1) +#define DT_N_S_soc_S_dma_40020000_FOREACH_NODELABEL_VARGS(fn, ...) fn(dma1, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_dma_40020000_CHILD_NUM 0 +#define DT_N_S_soc_S_dma_40020000_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_dma_40020000_ORD 160 +#define DT_N_S_soc_S_dma_40020000_ORD_STR_SORTABLE 00160 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_dma_40020000_REQUIRES_ORDS \ + 4, /* /soc */ \ + 5, /* /soc/interrupt-controller@e000e100 */ \ + 9, /* /soc/rcc@58024400 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_dma_40020000_SUPPORTS_ORDS \ + 173, /* /soc/dcmi@48020000 */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_dma_40020000_EXISTS 1 +#define DT_N_INST_0_st_stm32_dma_v1 DT_N_S_soc_S_dma_40020000 +#define DT_N_NODELABEL_dma1 DT_N_S_soc_S_dma_40020000 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_dma_40020000_REG_NUM 1 +#define DT_N_S_soc_S_dma_40020000_REG_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_REG_IDX_0_VAL_ADDRESS 1073872896 /* 0x40020000 */ +#define DT_N_S_soc_S_dma_40020000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_dma_40020000_RANGES_NUM 0 +#define DT_N_S_soc_S_dma_40020000_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_dma_40020000_IRQ_NUM 8 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_0_VAL_irq 11 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_0_VAL_irq_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_0_VAL_priority 0 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_0_VAL_priority_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_1_VAL_irq 12 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_1_VAL_irq_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_1_VAL_priority 0 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_1_VAL_priority_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_2_VAL_irq 13 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_2_VAL_irq_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_2_VAL_priority 0 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_2_VAL_priority_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_2_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_3_VAL_irq 14 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_3_VAL_irq_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_3_VAL_priority 0 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_3_VAL_priority_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_3_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_4_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_4_VAL_irq 15 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_4_VAL_irq_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_4_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_4_VAL_priority 0 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_4_VAL_priority_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_4_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_5_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_5_VAL_irq 16 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_5_VAL_irq_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_5_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_5_VAL_priority 0 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_5_VAL_priority_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_5_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_6_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_6_VAL_irq 17 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_6_VAL_irq_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_6_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_6_VAL_priority 0 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_6_VAL_priority_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_6_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_7_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_7_VAL_irq 47 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_7_VAL_irq_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_7_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_7_VAL_priority 0 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_7_VAL_priority_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_7_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 +#define DT_N_S_soc_S_dma_40020000_IRQ_LEVEL 1 +#define DT_N_S_soc_S_dma_40020000_COMPAT_MATCHES_st_stm32_dma_v1 1 +#define DT_N_S_soc_S_dma_40020000_COMPAT_VENDOR_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_COMPAT_VENDOR_IDX_0 "STMicroelectronics" +#define DT_N_S_soc_S_dma_40020000_COMPAT_MODEL_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_COMPAT_MODEL_IDX_0 "stm32-dma-v1" +#define DT_N_S_soc_S_dma_40020000_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_dma_40020000_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_dma_40020000_P_wakeup_source 0 +#define DT_N_S_soc_S_dma_40020000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_dma_40020000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_status "okay" +#define DT_N_S_soc_S_dma_40020000_P_status_STRING_UNQUOTED okay +#define DT_N_S_soc_S_dma_40020000_P_status_STRING_TOKEN okay +#define DT_N_S_soc_S_dma_40020000_P_status_STRING_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_dma_40020000_P_status_IDX_0 "okay" +#define DT_N_S_soc_S_dma_40020000_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_status_ENUM_IDX 1 +#define DT_N_S_soc_S_dma_40020000_P_status_ENUM_VAL_okay_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_status_ENUM_TOKEN okay +#define DT_N_S_soc_S_dma_40020000_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_dma_40020000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_40020000, status, 0) +#define DT_N_S_soc_S_dma_40020000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40020000, status, 0) +#define DT_N_S_soc_S_dma_40020000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40020000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dma_40020000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40020000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dma_40020000_P_status_LEN 1 +#define DT_N_S_soc_S_dma_40020000_P_status_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_compatible {"st,stm32-dma-v1"} +#define DT_N_S_soc_S_dma_40020000_P_compatible_IDX_0 "st,stm32-dma-v1" +#define DT_N_S_soc_S_dma_40020000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-dma-v1 +#define DT_N_S_soc_S_dma_40020000_P_compatible_IDX_0_STRING_TOKEN st_stm32_dma_v1 +#define DT_N_S_soc_S_dma_40020000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_DMA_V1 +#define DT_N_S_soc_S_dma_40020000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_40020000, compatible, 0) +#define DT_N_S_soc_S_dma_40020000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40020000, compatible, 0) +#define DT_N_S_soc_S_dma_40020000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40020000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dma_40020000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40020000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dma_40020000_P_compatible_LEN 1 +#define DT_N_S_soc_S_dma_40020000_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_reg {1073872896 /* 0x40020000 */, 1024 /* 0x400 */} +#define DT_N_S_soc_S_dma_40020000_P_reg_IDX_0 1073872896 +#define DT_N_S_soc_S_dma_40020000_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_dma_40020000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_reg_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts {11 /* 0xb */, 0 /* 0x0 */, 12 /* 0xc */, 0 /* 0x0 */, 13 /* 0xd */, 0 /* 0x0 */, 14 /* 0xe */, 0 /* 0x0 */, 15 /* 0xf */, 0 /* 0x0 */, 16 /* 0x10 */, 0 /* 0x0 */, 17 /* 0x11 */, 0 /* 0x0 */, 47 /* 0x2f */, 0 /* 0x0 */} +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_0 11 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_2 12 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_3 0 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_4 13 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_4_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_5 0 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_5_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_6 14 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_6_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_7 0 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_7_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_8 15 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_8_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_9 0 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_9_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_10 16 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_10_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_11 0 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_11_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_12 17 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_12_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_13 0 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_13_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_14 47 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_14_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_15 0 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_15_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_VAL_bus 216 +#define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_VAL_bits 1 +#define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_40020000, clocks, 0) +#define DT_N_S_soc_S_dma_40020000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40020000, clocks, 0) +#define DT_N_S_soc_S_dma_40020000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40020000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dma_40020000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40020000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dma_40020000_P_clocks_LEN 1 +#define DT_N_S_soc_S_dma_40020000_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_dma_40020000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_dma_requests 8 +#define DT_N_S_soc_S_dma_40020000_P_dma_requests_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_st_mem2mem 1 +#define DT_N_S_soc_S_dma_40020000_P_st_mem2mem_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_dma_offset 0 +#define DT_N_S_soc_S_dma_40020000_P_dma_offset_EXISTS 1 + +/* + * Devicetree node: /soc/i2c@58001c00/ov7670@21 + * + * Node identifier: DT_N_S_soc_S_i2c_58001c00_S_ov7670_21 + * + * Binding (compatible = ovti,ov7670): + * $ZEPHYR_BASE/dts/bindings/video/ovti,ov7670.yaml + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_PATH "/soc/i2c@58001c00/ov7670@21" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_FULL_NAME "ov7670@21" + +/* Node parent (/soc/i2c@58001c00) identifier: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_PARENT DT_N_S_soc_S_i2c_58001c00 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_CHILD_IDX 0 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_NODELABEL_NUM 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_FOREACH_NODELABEL(fn) fn(ov7670) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_FOREACH_NODELABEL_VARGS(fn, ...) fn(ov7670, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_CHILD_NUM 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_CHILD_NUM_STATUS_OKAY 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port, __VA_ARGS__) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_ORD 161 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_ORD_STR_SORTABLE 00161 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_REQUIRES_ORDS \ + 34, /* /soc/i2c@58001c00 */ \ + 69, /* /soc/pin-controller@58020000/gpio@58020000 */ \ + 72, /* /soc/pin-controller@58020000/gpio@58020C00 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_SUPPORTS_ORDS \ + 173, /* /soc/dcmi@48020000 */ \ + 184, /* /soc/i2c@58001c00/ov7670@21/port */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_EXISTS 1 +#define DT_N_INST_0_ovti_ov7670 DT_N_S_soc_S_i2c_58001c00_S_ov7670_21 +#define DT_N_NODELABEL_ov7670 DT_N_S_soc_S_i2c_58001c00_S_ov7670_21 + +/* Bus info (controller: '/soc/i2c@58001c00', type: '['i2c']') */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_BUS_i2c 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_BUS DT_N_S_soc_S_i2c_58001c00 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_REG_NUM 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_REG_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_REG_IDX_0_VAL_ADDRESS 33 /* 0x21 */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_RANGES_NUM 0 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_IRQ_NUM 0 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_IRQ_LEVEL 0 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_COMPAT_MATCHES_ovti_ov7670 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_COMPAT_VENDOR_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_COMPAT_VENDOR_IDX_0 "OmniVision Technologies Co., Ltd." +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_COMPAT_MODEL_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_COMPAT_MODEL_IDX_0 "ov7670" +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_wakeup_source 0 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible {"ovti,ov7670"} +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_IDX_0 "ovti,ov7670" +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_IDX_0_STRING_UNQUOTED ovti,ov7670 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_IDX_0_STRING_TOKEN ovti_ov7670 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_IDX_0_STRING_UPPER_TOKEN OVTI_OV7670 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, compatible, 0) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, compatible, 0) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_LEN 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reg {33 /* 0x21 */} +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reg_IDX_0 33 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reg_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reset_gpios_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reset_gpios_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reset_gpios_IDX_0_VAL_pin 4 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reset_gpios_IDX_0_VAL_pin_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reset_gpios_IDX_0_VAL_flags 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reset_gpios_IDX_0_VAL_flags_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reset_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, reset_gpios, 0) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reset_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, reset_gpios, 0) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reset_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, reset_gpios, 0, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reset_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, reset_gpios, 0, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reset_gpios_LEN 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reset_gpios_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_pwdn_gpios_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_pwdn_gpios_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_pwdn_gpios_IDX_0_VAL_pin 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_pwdn_gpios_IDX_0_VAL_pin_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_pwdn_gpios_IDX_0_VAL_flags 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_pwdn_gpios_IDX_0_VAL_flags_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_pwdn_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, pwdn_gpios, 0) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_pwdn_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, pwdn_gpios, 0) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_pwdn_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, pwdn_gpios, 0, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_pwdn_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, pwdn_gpios, 0, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_pwdn_gpios_LEN 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_pwdn_gpios_EXISTS 1 + +/* + * Devicetree node: /soc/pin-controller@58020000/dcmi_d0_ph9 + * + * Node identifier: DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9 + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_PATH "/soc/pin-controller@58020000/dcmi_d0_ph9" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_FULL_NAME "dcmi_d0_ph9" + +/* Node parent (/soc/pin-controller@58020000) identifier: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_PARENT DT_N_S_soc_S_pin_controller_58020000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_CHILD_IDX 30 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_NODELABEL_NUM 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_FOREACH_NODELABEL(fn) fn(dcmi_d0_ph9) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_FOREACH_NODELABEL_VARGS(fn, ...) fn(dcmi_d0_ph9, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_CHILD_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_ORD 162 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_ORD_STR_SORTABLE 00162 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_REQUIRES_ORDS \ + 10, /* /soc/pin-controller@58020000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_SUPPORTS_ORDS \ + 173, /* /soc/dcmi@48020000 */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_EXISTS 1 +#define DT_N_NODELABEL_dcmi_d0_ph9 DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_REG_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_RANGES_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_IRQ_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_IRQ_LEVEL 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_output_high_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_pinmux 3885 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_pinmux_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate "very-high-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_STRING_UNQUOTED very-high-speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_STRING_TOKEN very_high_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_IDX_0 "very-high-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_ENUM_TOKEN very_high_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_EXISTS 1 + +/* + * Devicetree node: /soc/pin-controller@58020000/dcmi_d1_ph10 + * + * Node identifier: DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10 + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_PATH "/soc/pin-controller@58020000/dcmi_d1_ph10" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_FULL_NAME "dcmi_d1_ph10" + +/* Node parent (/soc/pin-controller@58020000) identifier: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_PARENT DT_N_S_soc_S_pin_controller_58020000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_CHILD_IDX 31 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_NODELABEL_NUM 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_FOREACH_NODELABEL(fn) fn(dcmi_d1_ph10) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_FOREACH_NODELABEL_VARGS(fn, ...) fn(dcmi_d1_ph10, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_CHILD_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_ORD 163 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_ORD_STR_SORTABLE 00163 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_REQUIRES_ORDS \ + 10, /* /soc/pin-controller@58020000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_SUPPORTS_ORDS \ + 173, /* /soc/dcmi@48020000 */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_EXISTS 1 +#define DT_N_NODELABEL_dcmi_d1_ph10 DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_REG_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_RANGES_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_IRQ_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_IRQ_LEVEL 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_output_high_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_pinmux 3917 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_pinmux_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate "very-high-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_STRING_UNQUOTED very-high-speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_STRING_TOKEN very_high_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_IDX_0 "very-high-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_ENUM_TOKEN very_high_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_EXISTS 1 + +/* + * Devicetree node: /soc/pin-controller@58020000/dcmi_d2_ph11 + * + * Node identifier: DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11 + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_PATH "/soc/pin-controller@58020000/dcmi_d2_ph11" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_FULL_NAME "dcmi_d2_ph11" + +/* Node parent (/soc/pin-controller@58020000) identifier: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_PARENT DT_N_S_soc_S_pin_controller_58020000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_CHILD_IDX 32 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_NODELABEL_NUM 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_FOREACH_NODELABEL(fn) fn(dcmi_d2_ph11) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_FOREACH_NODELABEL_VARGS(fn, ...) fn(dcmi_d2_ph11, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_CHILD_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_ORD 164 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_ORD_STR_SORTABLE 00164 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_REQUIRES_ORDS \ + 10, /* /soc/pin-controller@58020000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_SUPPORTS_ORDS \ + 173, /* /soc/dcmi@48020000 */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_EXISTS 1 +#define DT_N_NODELABEL_dcmi_d2_ph11 DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_REG_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_RANGES_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_IRQ_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_IRQ_LEVEL 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_output_high_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_pinmux 3949 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_pinmux_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate "very-high-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_STRING_UNQUOTED very-high-speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_STRING_TOKEN very_high_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_IDX_0 "very-high-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_ENUM_TOKEN very_high_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_EXISTS 1 + +/* + * Devicetree node: /soc/pin-controller@58020000/dcmi_d3_pg11 + * + * Node identifier: DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11 + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_PATH "/soc/pin-controller@58020000/dcmi_d3_pg11" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_FULL_NAME "dcmi_d3_pg11" + +/* Node parent (/soc/pin-controller@58020000) identifier: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_PARENT DT_N_S_soc_S_pin_controller_58020000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_CHILD_IDX 28 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_NODELABEL_NUM 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_FOREACH_NODELABEL(fn) fn(dcmi_d3_pg11) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_FOREACH_NODELABEL_VARGS(fn, ...) fn(dcmi_d3_pg11, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_CHILD_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_ORD 165 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_ORD_STR_SORTABLE 00165 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_REQUIRES_ORDS \ + 10, /* /soc/pin-controller@58020000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_SUPPORTS_ORDS \ + 173, /* /soc/dcmi@48020000 */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_EXISTS 1 +#define DT_N_NODELABEL_dcmi_d3_pg11 DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_REG_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_RANGES_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_IRQ_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_IRQ_LEVEL 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_output_high_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_pinmux 3437 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_pinmux_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate "very-high-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_STRING_UNQUOTED very-high-speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_STRING_TOKEN very_high_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_IDX_0 "very-high-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_ENUM_TOKEN very_high_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_EXISTS 1 + +/* + * Devicetree node: /soc/pin-controller@58020000/dcmi_d4_ph14 + * + * Node identifier: DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14 + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_PATH "/soc/pin-controller@58020000/dcmi_d4_ph14" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_FULL_NAME "dcmi_d4_ph14" + +/* Node parent (/soc/pin-controller@58020000) identifier: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_PARENT DT_N_S_soc_S_pin_controller_58020000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_CHILD_IDX 33 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_NODELABEL_NUM 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_FOREACH_NODELABEL(fn) fn(dcmi_d4_ph14) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_FOREACH_NODELABEL_VARGS(fn, ...) fn(dcmi_d4_ph14, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_CHILD_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_ORD 166 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_ORD_STR_SORTABLE 00166 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_REQUIRES_ORDS \ + 10, /* /soc/pin-controller@58020000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_SUPPORTS_ORDS \ + 173, /* /soc/dcmi@48020000 */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_EXISTS 1 +#define DT_N_NODELABEL_dcmi_d4_ph14 DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_REG_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_RANGES_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_IRQ_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_IRQ_LEVEL 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_output_high_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_pinmux 4045 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_pinmux_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate "very-high-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_STRING_UNQUOTED very-high-speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_STRING_TOKEN very_high_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_IDX_0 "very-high-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_ENUM_TOKEN very_high_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_EXISTS 1 + +/* + * Devicetree node: /soc/pin-controller@58020000/dcmi_d5_pi4 + * + * Node identifier: DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4 + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_PATH "/soc/pin-controller@58020000/dcmi_d5_pi4" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_FULL_NAME "dcmi_d5_pi4" + +/* Node parent (/soc/pin-controller@58020000) identifier: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_PARENT DT_N_S_soc_S_pin_controller_58020000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_CHILD_IDX 34 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_NODELABEL_NUM 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_FOREACH_NODELABEL(fn) fn(dcmi_d5_pi4) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_FOREACH_NODELABEL_VARGS(fn, ...) fn(dcmi_d5_pi4, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_CHILD_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_ORD 167 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_ORD_STR_SORTABLE 00167 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_REQUIRES_ORDS \ + 10, /* /soc/pin-controller@58020000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_SUPPORTS_ORDS \ + 173, /* /soc/dcmi@48020000 */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_EXISTS 1 +#define DT_N_NODELABEL_dcmi_d5_pi4 DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_REG_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_RANGES_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_IRQ_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_IRQ_LEVEL 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_output_high_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_pinmux 4237 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_pinmux_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate "very-high-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_STRING_UNQUOTED very-high-speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_STRING_TOKEN very_high_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_IDX_0 "very-high-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_ENUM_TOKEN very_high_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_EXISTS 1 + +/* + * Devicetree node: /soc/pin-controller@58020000/dcmi_d6_pi6 + * + * Node identifier: DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6 + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_PATH "/soc/pin-controller@58020000/dcmi_d6_pi6" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_FULL_NAME "dcmi_d6_pi6" + +/* Node parent (/soc/pin-controller@58020000) identifier: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_PARENT DT_N_S_soc_S_pin_controller_58020000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_CHILD_IDX 36 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_NODELABEL_NUM 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_FOREACH_NODELABEL(fn) fn(dcmi_d6_pi6) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_FOREACH_NODELABEL_VARGS(fn, ...) fn(dcmi_d6_pi6, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_CHILD_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_ORD 168 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_ORD_STR_SORTABLE 00168 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_REQUIRES_ORDS \ + 10, /* /soc/pin-controller@58020000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_SUPPORTS_ORDS \ + 173, /* /soc/dcmi@48020000 */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_EXISTS 1 +#define DT_N_NODELABEL_dcmi_d6_pi6 DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_REG_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_RANGES_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_IRQ_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_IRQ_LEVEL 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_output_high_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_pinmux 4301 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_pinmux_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate "very-high-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_STRING_UNQUOTED very-high-speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_STRING_TOKEN very_high_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_IDX_0 "very-high-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_ENUM_TOKEN very_high_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_EXISTS 1 + +/* + * Devicetree node: /soc/pin-controller@58020000/dcmi_d7_pi7 + * + * Node identifier: DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7 + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_PATH "/soc/pin-controller@58020000/dcmi_d7_pi7" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_FULL_NAME "dcmi_d7_pi7" + +/* Node parent (/soc/pin-controller@58020000) identifier: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_PARENT DT_N_S_soc_S_pin_controller_58020000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_CHILD_IDX 37 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_NODELABEL_NUM 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_FOREACH_NODELABEL(fn) fn(dcmi_d7_pi7) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_FOREACH_NODELABEL_VARGS(fn, ...) fn(dcmi_d7_pi7, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_CHILD_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_ORD 169 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_ORD_STR_SORTABLE 00169 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_REQUIRES_ORDS \ + 10, /* /soc/pin-controller@58020000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_SUPPORTS_ORDS \ + 173, /* /soc/dcmi@48020000 */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_EXISTS 1 +#define DT_N_NODELABEL_dcmi_d7_pi7 DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_REG_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_RANGES_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_IRQ_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_IRQ_LEVEL 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_output_high_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_pinmux 4333 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_pinmux_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate "very-high-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_STRING_UNQUOTED very-high-speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_STRING_TOKEN very_high_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_IDX_0 "very-high-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_ENUM_TOKEN very_high_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_EXISTS 1 + +/* + * Devicetree node: /soc/pin-controller@58020000/dcmi_hsync_ph8 + * + * Node identifier: DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8 + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_PATH "/soc/pin-controller@58020000/dcmi_hsync_ph8" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_FULL_NAME "dcmi_hsync_ph8" + +/* Node parent (/soc/pin-controller@58020000) identifier: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_PARENT DT_N_S_soc_S_pin_controller_58020000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_CHILD_IDX 29 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_NODELABEL_NUM 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_FOREACH_NODELABEL(fn) fn(dcmi_hsync_ph8) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_FOREACH_NODELABEL_VARGS(fn, ...) fn(dcmi_hsync_ph8, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_CHILD_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_ORD 170 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_ORD_STR_SORTABLE 00170 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_REQUIRES_ORDS \ + 10, /* /soc/pin-controller@58020000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_SUPPORTS_ORDS \ + 173, /* /soc/dcmi@48020000 */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_EXISTS 1 +#define DT_N_NODELABEL_dcmi_hsync_ph8 DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_REG_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_RANGES_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_IRQ_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_IRQ_LEVEL 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_output_high_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_pinmux 3853 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_pinmux_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate "very-high-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_STRING_UNQUOTED very-high-speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_STRING_TOKEN very_high_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_IDX_0 "very-high-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_ENUM_TOKEN very_high_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_EXISTS 1 + +/* + * Devicetree node: /soc/pin-controller@58020000/dcmi_pixclk_pa6 + * + * Node identifier: DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6 + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_PATH "/soc/pin-controller@58020000/dcmi_pixclk_pa6" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_FULL_NAME "dcmi_pixclk_pa6" + +/* Node parent (/soc/pin-controller@58020000) identifier: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_PARENT DT_N_S_soc_S_pin_controller_58020000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_CHILD_IDX 27 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_NODELABEL_NUM 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_FOREACH_NODELABEL(fn) fn(dcmi_pixclk_pa6) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_FOREACH_NODELABEL_VARGS(fn, ...) fn(dcmi_pixclk_pa6, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_CHILD_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_ORD 171 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_ORD_STR_SORTABLE 00171 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_REQUIRES_ORDS \ + 10, /* /soc/pin-controller@58020000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_SUPPORTS_ORDS \ + 173, /* /soc/dcmi@48020000 */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_EXISTS 1 +#define DT_N_NODELABEL_dcmi_pixclk_pa6 DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_REG_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_RANGES_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_IRQ_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_IRQ_LEVEL 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_output_high_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_pinmux 205 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_pinmux_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate "very-high-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_STRING_UNQUOTED very-high-speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_STRING_TOKEN very_high_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_IDX_0 "very-high-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_ENUM_TOKEN very_high_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_EXISTS 1 + +/* + * Devicetree node: /soc/pin-controller@58020000/dcmi_vsync_pi5 + * + * Node identifier: DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5 + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_PATH "/soc/pin-controller@58020000/dcmi_vsync_pi5" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_FULL_NAME "dcmi_vsync_pi5" + +/* Node parent (/soc/pin-controller@58020000) identifier: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_PARENT DT_N_S_soc_S_pin_controller_58020000 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_CHILD_IDX 35 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_NODELABEL_NUM 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_FOREACH_NODELABEL(fn) fn(dcmi_vsync_pi5) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_FOREACH_NODELABEL_VARGS(fn, ...) fn(dcmi_vsync_pi5, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_CHILD_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_ORD 172 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_ORD_STR_SORTABLE 00172 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_REQUIRES_ORDS \ + 10, /* /soc/pin-controller@58020000 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_SUPPORTS_ORDS \ + 173, /* /soc/dcmi@48020000 */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_EXISTS 1 +#define DT_N_NODELABEL_dcmi_vsync_pi5 DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_REG_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_RANGES_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_IRQ_NUM 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_IRQ_LEVEL 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_output_high_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_pinmux 4269 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_pinmux_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate "very-high-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_STRING_UNQUOTED very-high-speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_STRING_TOKEN very_high_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_IDX_0 "very-high-speed" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_ENUM_TOKEN very_high_speed +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5, slew_rate, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5, slew_rate, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_EXISTS 1 + +/* + * Devicetree node: /soc/dcmi@48020000 * - * Node identifier: DT_N_S_soc_S_adc_40022000_S_channel_12 + * Node identifier: DT_N_S_soc_S_dcmi_48020000 + * + * Binding (compatible = st,stm32-dcmi): + * $ZEPHYR_BASE/dts/bindings/video/st,stm32-dcmi.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_12_PATH "/soc/adc@40022000/channel@12" +#define DT_N_S_soc_S_dcmi_48020000_PATH "/soc/dcmi@48020000" /* Node's name with unit-address: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_12_FULL_NAME "channel@12" +#define DT_N_S_soc_S_dcmi_48020000_FULL_NAME "dcmi@48020000" -/* Node parent (/soc/adc@40022000) identifier: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_12_PARENT DT_N_S_soc_S_adc_40022000 +/* Node parent (/soc) identifier: */ +#define DT_N_S_soc_S_dcmi_48020000_PARENT DT_N_S_soc /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_12_CHILD_IDX 5 +#define DT_N_S_soc_S_dcmi_48020000_CHILD_IDX 65 /* Helpers for dealing with node labels: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_12_NODELABEL_NUM 0 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_NODELABEL(fn) -#define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_NODELABEL_VARGS(fn, ...) +#define DT_N_S_soc_S_dcmi_48020000_NODELABEL_NUM 1 +#define DT_N_S_soc_S_dcmi_48020000_FOREACH_NODELABEL(fn) fn(dcmi) +#define DT_N_S_soc_S_dcmi_48020000_FOREACH_NODELABEL_VARGS(fn, ...) fn(dcmi, __VA_ARGS__) /* Helper macros for child nodes of this node. */ -#define DT_N_S_soc_S_adc_40022000_S_channel_12_CHILD_NUM 0 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_CHILD_NUM_STATUS_OKAY 0 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_CHILD(fn) -#define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_CHILD_SEP(fn, sep) -#define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_CHILD_VARGS(fn, ...) -#define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) -#define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_CHILD_STATUS_OKAY(fn) -#define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) -#define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) -#define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_dcmi_48020000_CHILD_NUM 1 +#define DT_N_S_soc_S_dcmi_48020000_CHILD_NUM_STATUS_OKAY 1 +#define DT_N_S_soc_S_dcmi_48020000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_dcmi_48020000_S_port) +#define DT_N_S_soc_S_dcmi_48020000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000_S_port) +#define DT_N_S_soc_S_dcmi_48020000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000_S_port, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000_S_port, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_dcmi_48020000_S_port) +#define DT_N_S_soc_S_dcmi_48020000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000_S_port) +#define DT_N_S_soc_S_dcmi_48020000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000_S_port, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000_S_port, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_12_ORD 142 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_ORD_STR_SORTABLE 00142 +#define DT_N_S_soc_S_dcmi_48020000_ORD 173 +#define DT_N_S_soc_S_dcmi_48020000_ORD_STR_SORTABLE 00173 /* Ordinals for what this node depends on directly: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_12_REQUIRES_ORDS \ - 44, /* /soc/adc@40022000 */ +#define DT_N_S_soc_S_dcmi_48020000_REQUIRES_ORDS \ + 4, /* /soc */ \ + 5, /* /soc/interrupt-controller@e000e100 */ \ + 9, /* /soc/rcc@58024400 */ \ + 160, /* /soc/dma@40020000 */ \ + 161, /* /soc/i2c@58001c00/ov7670@21 */ \ + 162, /* /soc/pin-controller@58020000/dcmi_d0_ph9 */ \ + 163, /* /soc/pin-controller@58020000/dcmi_d1_ph10 */ \ + 164, /* /soc/pin-controller@58020000/dcmi_d2_ph11 */ \ + 165, /* /soc/pin-controller@58020000/dcmi_d3_pg11 */ \ + 166, /* /soc/pin-controller@58020000/dcmi_d4_ph14 */ \ + 167, /* /soc/pin-controller@58020000/dcmi_d5_pi4 */ \ + 168, /* /soc/pin-controller@58020000/dcmi_d6_pi6 */ \ + 169, /* /soc/pin-controller@58020000/dcmi_d7_pi7 */ \ + 170, /* /soc/pin-controller@58020000/dcmi_hsync_ph8 */ \ + 171, /* /soc/pin-controller@58020000/dcmi_pixclk_pa6 */ \ + 172, /* /soc/pin-controller@58020000/dcmi_vsync_pi5 */ /* Ordinals for what depends directly on this node: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_12_SUPPORTS_ORDS /* nothing */ +#define DT_N_S_soc_S_dcmi_48020000_SUPPORTS_ORDS \ + 174, /* /soc/dcmi@48020000/port */ /* Existence and alternate IDs: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_12_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_EXISTS 1 +#define DT_N_INST_0_st_stm32_dcmi DT_N_S_soc_S_dcmi_48020000 +#define DT_N_NODELABEL_dcmi DT_N_S_soc_S_dcmi_48020000 /* Macros for properties that are special in the specification: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_12_REG_NUM 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_REG_IDX_0_VAL_ADDRESS 12 /* 0xc */ -#define DT_N_S_soc_S_adc_40022000_S_channel_12_RANGES_NUM 0 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_RANGE(fn) -#define DT_N_S_soc_S_adc_40022000_S_channel_12_IRQ_NUM 0 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_IRQ_LEVEL 0 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_STATUS_okay 1 +#define DT_N_S_soc_S_dcmi_48020000_REG_NUM 1 +#define DT_N_S_soc_S_dcmi_48020000_REG_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_REG_IDX_0_VAL_ADDRESS 1208090624 /* 0x48020000 */ +#define DT_N_S_soc_S_dcmi_48020000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_dcmi_48020000_RANGES_NUM 0 +#define DT_N_S_soc_S_dcmi_48020000_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_dcmi_48020000_IRQ_NUM 1 +#define DT_N_S_soc_S_dcmi_48020000_IRQ_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_IRQ_IDX_0_VAL_irq 78 +#define DT_N_S_soc_S_dcmi_48020000_IRQ_IDX_0_VAL_irq_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_IRQ_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_IRQ_IDX_0_VAL_priority 0 +#define DT_N_S_soc_S_dcmi_48020000_IRQ_IDX_0_VAL_priority_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 +#define DT_N_S_soc_S_dcmi_48020000_IRQ_LEVEL 1 +#define DT_N_S_soc_S_dcmi_48020000_IRQ_NAME_dcmi_VAL_irq DT_N_S_soc_S_dcmi_48020000_IRQ_IDX_0_VAL_irq +#define DT_N_S_soc_S_dcmi_48020000_IRQ_NAME_dcmi_VAL_irq_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_IRQ_NAME_dcmi_VAL_priority DT_N_S_soc_S_dcmi_48020000_IRQ_IDX_0_VAL_priority +#define DT_N_S_soc_S_dcmi_48020000_IRQ_NAME_dcmi_VAL_priority_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_IRQ_NAME_dcmi_CONTROLLER DT_N_S_soc_S_dcmi_48020000_IRQ_IDX_0_CONTROLLER +#define DT_N_S_soc_S_dcmi_48020000_COMPAT_MATCHES_st_stm32_dcmi 1 +#define DT_N_S_soc_S_dcmi_48020000_COMPAT_VENDOR_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_COMPAT_VENDOR_IDX_0 "STMicroelectronics" +#define DT_N_S_soc_S_dcmi_48020000_COMPAT_MODEL_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_COMPAT_MODEL_IDX_0 "stm32-dcmi" +#define DT_N_S_soc_S_dcmi_48020000_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_12_PINCTRL_NUM 0 +#define DT_N_S_soc_S_dcmi_48020000_PINCTRL_NUM 1 +#define DT_N_S_soc_S_dcmi_48020000_PINCTRL_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_PINCTRL_IDX_0_TOKEN default +#define DT_N_S_soc_S_dcmi_48020000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT +#define DT_N_S_soc_S_dcmi_48020000_PINCTRL_NAME_default_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_PINCTRL_NAME_default_IDX 0 +#define DT_N_S_soc_S_dcmi_48020000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8 +#define DT_N_S_soc_S_dcmi_48020000_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6 +#define DT_N_S_soc_S_dcmi_48020000_PINCTRL_NAME_default_IDX_2_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5 +#define DT_N_S_soc_S_dcmi_48020000_PINCTRL_NAME_default_IDX_3_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9 +#define DT_N_S_soc_S_dcmi_48020000_PINCTRL_NAME_default_IDX_4_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10 +#define DT_N_S_soc_S_dcmi_48020000_PINCTRL_NAME_default_IDX_5_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11 +#define DT_N_S_soc_S_dcmi_48020000_PINCTRL_NAME_default_IDX_6_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11 +#define DT_N_S_soc_S_dcmi_48020000_PINCTRL_NAME_default_IDX_7_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14 +#define DT_N_S_soc_S_dcmi_48020000_PINCTRL_NAME_default_IDX_8_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4 +#define DT_N_S_soc_S_dcmi_48020000_PINCTRL_NAME_default_IDX_9_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6 +#define DT_N_S_soc_S_dcmi_48020000_PINCTRL_NAME_default_IDX_10_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7 /* Generic property macros: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_reg {12 /* 0xc */} -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_reg_IDX_0 12 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_reg_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain "ADC_GAIN_1" -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_STRING_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_IDX_0 "ADC_GAIN_1" -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_ENUM_IDX 8 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, zephyr_gain, 0) -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, zephyr_gain, 0) -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, zephyr_gain, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, zephyr_gain, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_LEN 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference "ADC_REF_INTERNAL" -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_STRING_UNQUOTED ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_STRING_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_ENUM_IDX 4 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, zephyr_reference, 0) -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, zephyr_reference, 0) -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, zephyr_reference, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, zephyr_reference, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_LEN 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_acquisition_time 16383 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_acquisition_time_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_differential 0 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_differential_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_resolution 12 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_resolution_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_wakeup_source 0 +#define DT_N_S_soc_S_dcmi_48020000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_dcmi_48020000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_status "okay" +#define DT_N_S_soc_S_dcmi_48020000_P_status_STRING_UNQUOTED okay +#define DT_N_S_soc_S_dcmi_48020000_P_status_STRING_TOKEN okay +#define DT_N_S_soc_S_dcmi_48020000_P_status_STRING_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_dcmi_48020000_P_status_IDX_0 "okay" +#define DT_N_S_soc_S_dcmi_48020000_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_status_ENUM_IDX 1 +#define DT_N_S_soc_S_dcmi_48020000_P_status_ENUM_VAL_okay_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_status_ENUM_TOKEN okay +#define DT_N_S_soc_S_dcmi_48020000_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_dcmi_48020000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dcmi_48020000, status, 0) +#define DT_N_S_soc_S_dcmi_48020000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000, status, 0) +#define DT_N_S_soc_S_dcmi_48020000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_P_status_LEN 1 +#define DT_N_S_soc_S_dcmi_48020000_P_status_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_compatible {"st,stm32-dcmi"} +#define DT_N_S_soc_S_dcmi_48020000_P_compatible_IDX_0 "st,stm32-dcmi" +#define DT_N_S_soc_S_dcmi_48020000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-dcmi +#define DT_N_S_soc_S_dcmi_48020000_P_compatible_IDX_0_STRING_TOKEN st_stm32_dcmi +#define DT_N_S_soc_S_dcmi_48020000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_DCMI +#define DT_N_S_soc_S_dcmi_48020000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dcmi_48020000, compatible, 0) +#define DT_N_S_soc_S_dcmi_48020000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000, compatible, 0) +#define DT_N_S_soc_S_dcmi_48020000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_P_compatible_LEN 1 +#define DT_N_S_soc_S_dcmi_48020000_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_reg {1208090624 /* 0x48020000 */, 1024 /* 0x400 */} +#define DT_N_S_soc_S_dcmi_48020000_P_reg_IDX_0 1208090624 +#define DT_N_S_soc_S_dcmi_48020000_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_dcmi_48020000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_reg_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_interrupts {78 /* 0x4e */, 0 /* 0x0 */} +#define DT_N_S_soc_S_dcmi_48020000_P_interrupts_IDX_0 78 +#define DT_N_S_soc_S_dcmi_48020000_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_dcmi_48020000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_interrupts_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names {"dcmi"} +#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_IDX_0 "dcmi" +#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_IDX_0_STRING_UNQUOTED dcmi +#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_IDX_0_STRING_TOKEN dcmi +#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN DCMI +#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dcmi_48020000, interrupt_names, 0) +#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000, interrupt_names, 0) +#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000, interrupt_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000, interrupt_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_LEN 1 +#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_dcmi_48020000_P_clocks_IDX_0_VAL_bus 220 +#define DT_N_S_soc_S_dcmi_48020000_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_clocks_IDX_0_VAL_bits 1 +#define DT_N_S_soc_S_dcmi_48020000_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dcmi_48020000, clocks, 0) +#define DT_N_S_soc_S_dcmi_48020000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000, clocks, 0) +#define DT_N_S_soc_S_dcmi_48020000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_P_clocks_LEN 1 +#define DT_N_S_soc_S_dcmi_48020000_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_PH DT_N_S_soc_S_dma_40020000 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_channel 0 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_channel_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_slot 75 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_slot_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_channel_config 148608 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_channel_config_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_features 0 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_features_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dcmi_48020000, dmas, 0) +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000, dmas, 0) +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000, dmas, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000, dmas, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_LEN 1 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_dcmi_48020000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_2 DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_2_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_3 DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_3_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_4 DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_4_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_4_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_5 DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_5_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_5_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_6 DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_6_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_6_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_7 DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_7_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_7_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_8 DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_8_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_8_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_9 DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_9_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_9_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_10 DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_10_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_10_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 0) \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 1) \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 2) \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 3) \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 4) \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 5) \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 6) \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 7) \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 8) \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 9) \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 10) +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 1) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 2) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 3) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 4) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 5) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 6) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 7) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 8) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 9) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 10) +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 1, __VA_ARGS__) \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 2, __VA_ARGS__) \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 3, __VA_ARGS__) \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 4, __VA_ARGS__) \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 5, __VA_ARGS__) \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 6, __VA_ARGS__) \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 7, __VA_ARGS__) \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 8, __VA_ARGS__) \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 9, __VA_ARGS__) \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 10, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_0, 10, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_LEN 11 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names {"default"} +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names_IDX_0 "default" +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names_IDX_0_STRING_TOKEN default +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_names, 0) +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_names, 0) +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names_LEN 1 +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_sensor DT_N_S_soc_S_i2c_58001c00_S_ov7670_21 +#define DT_N_S_soc_S_dcmi_48020000_P_sensor_IDX_0 DT_N_S_soc_S_i2c_58001c00_S_ov7670_21 +#define DT_N_S_soc_S_dcmi_48020000_P_sensor_IDX_0_PH DT_N_S_soc_S_i2c_58001c00_S_ov7670_21 +#define DT_N_S_soc_S_dcmi_48020000_P_sensor_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_sensor_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dcmi_48020000, sensor, 0) +#define DT_N_S_soc_S_dcmi_48020000_P_sensor_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000, sensor, 0) +#define DT_N_S_soc_S_dcmi_48020000_P_sensor_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000, sensor, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_P_sensor_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000, sensor, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_P_sensor_LEN 1 +#define DT_N_S_soc_S_dcmi_48020000_P_sensor_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_bus_width 8 +#define DT_N_S_soc_S_dcmi_48020000_P_bus_width_ENUM_IDX 0 +#define DT_N_S_soc_S_dcmi_48020000_P_bus_width_ENUM_VAL_8_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_bus_width_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_hsync_active 0 +#define DT_N_S_soc_S_dcmi_48020000_P_hsync_active_ENUM_IDX 0 +#define DT_N_S_soc_S_dcmi_48020000_P_hsync_active_ENUM_VAL_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_hsync_active_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_vsync_active 0 +#define DT_N_S_soc_S_dcmi_48020000_P_vsync_active_ENUM_IDX 0 +#define DT_N_S_soc_S_dcmi_48020000_P_vsync_active_ENUM_VAL_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_vsync_active_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_pixelclk_active 0 +#define DT_N_S_soc_S_dcmi_48020000_P_pixelclk_active_ENUM_IDX 0 +#define DT_N_S_soc_S_dcmi_48020000_P_pixelclk_active_ENUM_VAL_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_pixelclk_active_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_capture_rate 1 +#define DT_N_S_soc_S_dcmi_48020000_P_capture_rate_ENUM_IDX 0 +#define DT_N_S_soc_S_dcmi_48020000_P_capture_rate_ENUM_VAL_1_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_capture_rate_EXISTS 1 /* - * Devicetree node: /soc/adc@40022000/channel@13 - * - * Node identifier: DT_N_S_soc_S_adc_40022000_S_channel_13 + * Devicetree node: /soc/dcmi@48020000/port * - * (Descriptions have moved to the Devicetree Bindings Index - * in the documentation.) + * Node identifier: DT_N_S_soc_S_dcmi_48020000_S_port */ /* Node's full path: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_13_PATH "/soc/adc@40022000/channel@13" +#define DT_N_S_soc_S_dcmi_48020000_S_port_PATH "/soc/dcmi@48020000/port" /* Node's name with unit-address: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_13_FULL_NAME "channel@13" +#define DT_N_S_soc_S_dcmi_48020000_S_port_FULL_NAME "port" -/* Node parent (/soc/adc@40022000) identifier: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_13_PARENT DT_N_S_soc_S_adc_40022000 +/* Node parent (/soc/dcmi@48020000) identifier: */ +#define DT_N_S_soc_S_dcmi_48020000_S_port_PARENT DT_N_S_soc_S_dcmi_48020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_13_CHILD_IDX 4 +#define DT_N_S_soc_S_dcmi_48020000_S_port_CHILD_IDX 0 /* Helpers for dealing with node labels: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_13_NODELABEL_NUM 0 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_NODELABEL(fn) -#define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_NODELABEL_VARGS(fn, ...) +#define DT_N_S_soc_S_dcmi_48020000_S_port_NODELABEL_NUM 0 +#define DT_N_S_soc_S_dcmi_48020000_S_port_FOREACH_NODELABEL(fn) +#define DT_N_S_soc_S_dcmi_48020000_S_port_FOREACH_NODELABEL_VARGS(fn, ...) /* Helper macros for child nodes of this node. */ -#define DT_N_S_soc_S_adc_40022000_S_channel_13_CHILD_NUM 0 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_CHILD_NUM_STATUS_OKAY 0 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_CHILD(fn) -#define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_CHILD_SEP(fn, sep) -#define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_CHILD_VARGS(fn, ...) -#define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) -#define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_CHILD_STATUS_OKAY(fn) -#define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) -#define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) -#define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_dcmi_48020000_S_port_CHILD_NUM 1 +#define DT_N_S_soc_S_dcmi_48020000_S_port_CHILD_NUM_STATUS_OKAY 1 +#define DT_N_S_soc_S_dcmi_48020000_S_port_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint) +#define DT_N_S_soc_S_dcmi_48020000_S_port_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint) +#define DT_N_S_soc_S_dcmi_48020000_S_port_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_S_port_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_S_port_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint) +#define DT_N_S_soc_S_dcmi_48020000_S_port_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint) +#define DT_N_S_soc_S_dcmi_48020000_S_port_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_S_port_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_13_ORD 143 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_ORD_STR_SORTABLE 00143 +#define DT_N_S_soc_S_dcmi_48020000_S_port_ORD 174 +#define DT_N_S_soc_S_dcmi_48020000_S_port_ORD_STR_SORTABLE 00174 /* Ordinals for what this node depends on directly: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_13_REQUIRES_ORDS \ - 44, /* /soc/adc@40022000 */ +#define DT_N_S_soc_S_dcmi_48020000_S_port_REQUIRES_ORDS \ + 173, /* /soc/dcmi@48020000 */ /* Ordinals for what depends directly on this node: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_13_SUPPORTS_ORDS /* nothing */ +#define DT_N_S_soc_S_dcmi_48020000_S_port_SUPPORTS_ORDS \ + 175, /* /soc/dcmi@48020000/port/endpoint */ /* Existence and alternate IDs: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_13_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_S_port_EXISTS 1 /* Macros for properties that are special in the specification: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_13_REG_NUM 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_REG_IDX_0_VAL_ADDRESS 13 /* 0xd */ -#define DT_N_S_soc_S_adc_40022000_S_channel_13_RANGES_NUM 0 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_RANGE(fn) -#define DT_N_S_soc_S_adc_40022000_S_channel_13_IRQ_NUM 0 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_IRQ_LEVEL 0 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_STATUS_okay 1 +#define DT_N_S_soc_S_dcmi_48020000_S_port_REG_NUM 0 +#define DT_N_S_soc_S_dcmi_48020000_S_port_RANGES_NUM 0 +#define DT_N_S_soc_S_dcmi_48020000_S_port_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_dcmi_48020000_S_port_IRQ_NUM 0 +#define DT_N_S_soc_S_dcmi_48020000_S_port_IRQ_LEVEL 0 +#define DT_N_S_soc_S_dcmi_48020000_S_port_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_13_PINCTRL_NUM 0 +#define DT_N_S_soc_S_dcmi_48020000_S_port_PINCTRL_NUM 0 -/* Generic property macros: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_reg {13 /* 0xd */} -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_reg_IDX_0 13 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_reg_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain "ADC_GAIN_1" -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_STRING_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_IDX_0 "ADC_GAIN_1" -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_ENUM_IDX 8 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, zephyr_gain, 0) -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, zephyr_gain, 0) -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, zephyr_gain, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, zephyr_gain, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_LEN 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference "ADC_REF_INTERNAL" -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_STRING_UNQUOTED ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_STRING_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_ENUM_IDX 4 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, zephyr_reference, 0) -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, zephyr_reference, 0) -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, zephyr_reference, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, zephyr_reference, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_LEN 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_acquisition_time 16383 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_acquisition_time_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_differential 0 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_differential_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_resolution 12 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_resolution_EXISTS 1 +/* (No generic property macros) */ /* - * Devicetree node: /soc/adc@40022000/channel@16 - * - * Node identifier: DT_N_S_soc_S_adc_40022000_S_channel_16 + * Devicetree node: /soc/dcmi@48020000/port/endpoint * - * (Descriptions have moved to the Devicetree Bindings Index - * in the documentation.) + * Node identifier: DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint */ /* Node's full path: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_16_PATH "/soc/adc@40022000/channel@16" +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_PATH "/soc/dcmi@48020000/port/endpoint" /* Node's name with unit-address: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_16_FULL_NAME "channel@16" +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_FULL_NAME "endpoint" -/* Node parent (/soc/adc@40022000) identifier: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_16_PARENT DT_N_S_soc_S_adc_40022000 - -/* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_16_CHILD_IDX 7 - -/* Helpers for dealing with node labels: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_16_NODELABEL_NUM 0 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_FOREACH_NODELABEL(fn) -#define DT_N_S_soc_S_adc_40022000_S_channel_16_FOREACH_NODELABEL_VARGS(fn, ...) - -/* Helper macros for child nodes of this node. */ -#define DT_N_S_soc_S_adc_40022000_S_channel_16_CHILD_NUM 0 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_CHILD_NUM_STATUS_OKAY 0 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_FOREACH_CHILD(fn) -#define DT_N_S_soc_S_adc_40022000_S_channel_16_FOREACH_CHILD_SEP(fn, sep) -#define DT_N_S_soc_S_adc_40022000_S_channel_16_FOREACH_CHILD_VARGS(fn, ...) -#define DT_N_S_soc_S_adc_40022000_S_channel_16_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) -#define DT_N_S_soc_S_adc_40022000_S_channel_16_FOREACH_CHILD_STATUS_OKAY(fn) -#define DT_N_S_soc_S_adc_40022000_S_channel_16_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) -#define DT_N_S_soc_S_adc_40022000_S_channel_16_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) -#define DT_N_S_soc_S_adc_40022000_S_channel_16_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) - -/* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_16_ORD 144 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_ORD_STR_SORTABLE 00144 - -/* Ordinals for what this node depends on directly: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_16_REQUIRES_ORDS \ - 44, /* /soc/adc@40022000 */ - -/* Ordinals for what depends directly on this node: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_16_SUPPORTS_ORDS /* nothing */ - -/* Existence and alternate IDs: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_16_EXISTS 1 - -/* Macros for properties that are special in the specification: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_16_REG_NUM 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_REG_IDX_0_VAL_ADDRESS 16 /* 0x10 */ -#define DT_N_S_soc_S_adc_40022000_S_channel_16_RANGES_NUM 0 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_FOREACH_RANGE(fn) -#define DT_N_S_soc_S_adc_40022000_S_channel_16_IRQ_NUM 0 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_IRQ_LEVEL 0 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_STATUS_okay 1 - -/* Pin control (pinctrl-, pinctrl-names) properties: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_16_PINCTRL_NUM 0 - -/* Generic property macros: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_reg {16 /* 0x10 */} -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_reg_IDX_0 16 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_reg_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_gain "ADC_GAIN_1" -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_gain_STRING_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_gain_IDX_0 "ADC_GAIN_1" -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_gain_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_gain_ENUM_IDX 8 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_16, zephyr_gain, 0) -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_16, zephyr_gain, 0) -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_16, zephyr_gain, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_gain_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_16, zephyr_gain, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_gain_LEN 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_gain_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_reference "ADC_REF_INTERNAL" -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_reference_STRING_UNQUOTED ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_reference_STRING_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_reference_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_reference_ENUM_IDX 4 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_16, zephyr_reference, 0) -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_16, zephyr_reference, 0) -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_16, zephyr_reference, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_reference_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_16, zephyr_reference, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_reference_LEN 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_reference_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_acquisition_time 16383 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_acquisition_time_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_differential 0 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_differential_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_resolution 12 -#define DT_N_S_soc_S_adc_40022000_S_channel_16_P_zephyr_resolution_EXISTS 1 +/* Node parent (/soc/dcmi@48020000/port) identifier: */ +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_PARENT DT_N_S_soc_S_dcmi_48020000_S_port + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_CHILD_IDX 0 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_NODELABEL_NUM 1 +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_FOREACH_NODELABEL(fn) fn(dcmi_ep_in) +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_FOREACH_NODELABEL_VARGS(fn, ...) fn(dcmi_ep_in, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_CHILD_NUM 0 +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_ORD 175 +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_ORD_STR_SORTABLE 00175 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_REQUIRES_ORDS \ + 174, /* /soc/dcmi@48020000/port */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_SUPPORTS_ORDS /* nothing */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_EXISTS 1 +#define DT_N_NODELABEL_dcmi_ep_in DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_REG_NUM 0 +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_RANGES_NUM 0 +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_IRQ_NUM 0 +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_IRQ_LEVEL 0 +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_PINCTRL_NUM 0 + +/* (No generic property macros) */ /* * Devicetree node: /soc/ethernet@40028000 @@ -21374,8 +25836,8 @@ #define DT_N_S_soc_S_ethernet_40028000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_ethernet_40028000_ORD 145 -#define DT_N_S_soc_S_ethernet_40028000_ORD_STR_SORTABLE 00145 +#define DT_N_S_soc_S_ethernet_40028000_ORD 176 +#define DT_N_S_soc_S_ethernet_40028000_ORD_STR_SORTABLE 00176 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_ethernet_40028000_REQUIRES_ORDS \ @@ -21385,7 +25847,7 @@ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_ethernet_40028000_SUPPORTS_ORDS \ - 146, /* /soc/ethernet@40028000/mdio */ + 177, /* /soc/ethernet@40028000/mdio */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_ethernet_40028000_EXISTS 1 @@ -21593,12 +26055,12 @@ #define DT_N_S_soc_S_ethernet_40028000_S_mdio_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_ethernet_40028000_S_mdio_ORD 146 -#define DT_N_S_soc_S_ethernet_40028000_S_mdio_ORD_STR_SORTABLE 00146 +#define DT_N_S_soc_S_ethernet_40028000_S_mdio_ORD 177 +#define DT_N_S_soc_S_ethernet_40028000_S_mdio_ORD_STR_SORTABLE 00177 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_ethernet_40028000_S_mdio_REQUIRES_ORDS \ - 145, /* /soc/ethernet@40028000 */ + 176, /* /soc/ethernet@40028000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_ethernet_40028000_S_mdio_SUPPORTS_ORDS /* nothing */ @@ -21706,8 +26168,8 @@ #define DT_N_S_soc_S_flash_controller_52002000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_flash_controller_52002000_ORD 147 -#define DT_N_S_soc_S_flash_controller_52002000_ORD_STR_SORTABLE 00147 +#define DT_N_S_soc_S_flash_controller_52002000_ORD 178 +#define DT_N_S_soc_S_flash_controller_52002000_ORD_STR_SORTABLE 00178 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_flash_controller_52002000_REQUIRES_ORDS \ @@ -21717,7 +26179,7 @@ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_flash_controller_52002000_SUPPORTS_ORDS \ - 148, /* /soc/flash-controller@52002000/flash@8000000 */ + 179, /* /soc/flash-controller@52002000/flash@8000000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_flash_controller_52002000_EXISTS 1 @@ -21853,16 +26315,16 @@ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_ORD 148 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_ORD_STR_SORTABLE 00148 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_ORD 179 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_ORD_STR_SORTABLE 00179 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_REQUIRES_ORDS \ - 147, /* /soc/flash-controller@52002000 */ + 178, /* /soc/flash-controller@52002000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_SUPPORTS_ORDS \ - 149, /* /soc/flash-controller@52002000/flash@8000000/partitions */ + 180, /* /soc/flash-controller@52002000/flash@8000000/partitions */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_EXISTS 1 @@ -21977,29 +26439,30 @@ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_FOREACH_NODELABEL_VARGS(fn, ...) /* Helper macros for child nodes of this node. */ -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_CHILD_NUM 2 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_CHILD_NUM_STATUS_OKAY 2 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000) -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000) -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000, __VA_ARGS__) -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000, __VA_ARGS__) -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000) -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000) -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000, __VA_ARGS__) -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000, __VA_ARGS__) +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_CHILD_NUM 3 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_CHILD_NUM_STATUS_OKAY 3 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000) +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000) +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000, __VA_ARGS__) +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000, __VA_ARGS__) +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000) +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000) +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000, __VA_ARGS__) +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_ORD 149 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_ORD_STR_SORTABLE 00149 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_ORD 180 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_ORD_STR_SORTABLE 00180 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_REQUIRES_ORDS \ - 148, /* /soc/flash-controller@52002000/flash@8000000 */ + 179, /* /soc/flash-controller@52002000/flash@8000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_SUPPORTS_ORDS \ - 150, /* /soc/flash-controller@52002000/flash@8000000/partitions/partition@0 */ \ - 151, /* /soc/flash-controller@52002000/flash@8000000/partitions/partition@40000 */ + 181, /* /soc/flash-controller@52002000/flash@8000000/partitions/partition@0 */ \ + 182, /* /soc/flash-controller@52002000/flash@8000000/partitions/partition@40000 */ \ + 183, /* /soc/flash-controller@52002000/flash@8000000/partitions/partition@e0000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_EXISTS 1 @@ -22041,9 +26504,9 @@ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_CHILD_IDX 0 /* Helpers for dealing with node labels: */ -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_NODELABEL_NUM 2 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_NODELABEL(fn) fn(boot_partition) fn(user_sketch) -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(boot_partition, __VA_ARGS__) fn(user_sketch, __VA_ARGS__) +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_NODELABEL_NUM 1 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_NODELABEL(fn) fn(boot_partition) +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(boot_partition, __VA_ARGS__) /* Helper macros for child nodes of this node. */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_CHILD_NUM 0 @@ -22058,12 +26521,12 @@ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_ORD 150 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_ORD_STR_SORTABLE 00150 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_ORD 181 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_ORD_STR_SORTABLE 00181 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_REQUIRES_ORDS \ - 149, /* /soc/flash-controller@52002000/flash@8000000/partitions */ + 180, /* /soc/flash-controller@52002000/flash@8000000/partitions */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_SUPPORTS_ORDS /* nothing */ @@ -22071,13 +26534,12 @@ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_EXISTS 1 #define DT_N_NODELABEL_boot_partition DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0 -#define DT_N_NODELABEL_user_sketch DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_REG_NUM 1 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS 917504 /* 0xe0000 */ -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE 131072 /* 0x20000 */ +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */ +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_RANGES_NUM 0 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_RANGE(fn) #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_IRQ_NUM 0 @@ -22105,10 +26567,10 @@ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_label_EXISTS 1 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_read_only 1 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_read_only_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_reg {917504 /* 0xe0000 */, 131072 /* 0x20000 */} -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_reg_IDX_0 917504 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_reg {0 /* 0x0 */, 262144 /* 0x40000 */} +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_reg_IDX_0 0 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_reg_IDX_1 131072 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_reg_IDX_1 262144 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_reg_EXISTS 1 @@ -22151,12 +26613,12 @@ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_ORD 151 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_ORD_STR_SORTABLE 00151 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_ORD 182 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_ORD_STR_SORTABLE 00182 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_REQUIRES_ORDS \ - 149, /* /soc/flash-controller@52002000/flash@8000000/partitions */ + 180, /* /soc/flash-controller@52002000/flash@8000000/partitions */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_SUPPORTS_ORDS /* nothing */ @@ -22204,6 +26666,220 @@ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_P_reg_IDX_1_EXISTS 1 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_P_reg_EXISTS 1 +/* + * Devicetree node: /soc/flash-controller@52002000/flash@8000000/partitions/partition@e0000 + * + * Node identifier: DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000 + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_PATH "/soc/flash-controller@52002000/flash@8000000/partitions/partition@e0000" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_FULL_NAME "partition@e0000" + +/* Node parent (/soc/flash-controller@52002000/flash@8000000/partitions) identifier: */ +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_PARENT DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_CHILD_IDX 2 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_NODELABEL_NUM 1 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_FOREACH_NODELABEL(fn) fn(user_sketch) +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_FOREACH_NODELABEL_VARGS(fn, ...) fn(user_sketch, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_CHILD_NUM 0 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_ORD 183 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_ORD_STR_SORTABLE 00183 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_REQUIRES_ORDS \ + 180, /* /soc/flash-controller@52002000/flash@8000000/partitions */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_SUPPORTS_ORDS /* nothing */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_EXISTS 1 +#define DT_N_NODELABEL_user_sketch DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_REG_NUM 1 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_REG_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_REG_IDX_0_VAL_ADDRESS 917504 /* 0xe0000 */ +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_REG_IDX_0_VAL_SIZE 131072 /* 0x20000 */ +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_RANGES_NUM 0 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_IRQ_NUM 0 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_IRQ_LEVEL 0 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_PINCTRL_NUM 0 + +/* fixed-partitions identifier: */ +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_PARTITION_ID 2 + +/* Generic property macros: */ +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_P_read_only 0 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_P_read_only_EXISTS 1 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_P_reg {917504 /* 0xe0000 */, 131072 /* 0x20000 */} +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_P_reg_IDX_0 917504 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_P_reg_IDX_1 131072 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_P_reg_EXISTS 1 + +/* + * Devicetree node: /soc/i2c@58001c00/ov7670@21/port + * + * Node identifier: DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_PATH "/soc/i2c@58001c00/ov7670@21/port" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_FULL_NAME "port" + +/* Node parent (/soc/i2c@58001c00/ov7670@21) identifier: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_PARENT DT_N_S_soc_S_i2c_58001c00_S_ov7670_21 + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_CHILD_IDX 0 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_NODELABEL_NUM 0 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_FOREACH_NODELABEL(fn) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_FOREACH_NODELABEL_VARGS(fn, ...) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_CHILD_NUM 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_CHILD_NUM_STATUS_OKAY 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint, __VA_ARGS__) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_ORD 184 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_ORD_STR_SORTABLE 00184 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_REQUIRES_ORDS \ + 161, /* /soc/i2c@58001c00/ov7670@21 */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_SUPPORTS_ORDS \ + 185, /* /soc/i2c@58001c00/ov7670@21/port/endpoint */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_EXISTS 1 + +/* Bus info (controller: '/soc/i2c@58001c00', type: '['i2c']') */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_BUS_i2c 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_BUS DT_N_S_soc_S_i2c_58001c00 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_REG_NUM 0 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_RANGES_NUM 0 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_IRQ_NUM 0 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_IRQ_LEVEL 0 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_PINCTRL_NUM 0 + +/* (No generic property macros) */ + +/* + * Devicetree node: /soc/i2c@58001c00/ov7670@21/port/endpoint + * + * Node identifier: DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint + */ + +/* Node's full path: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_PATH "/soc/i2c@58001c00/ov7670@21/port/endpoint" + +/* Node's name with unit-address: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_FULL_NAME "endpoint" + +/* Node parent (/soc/i2c@58001c00/ov7670@21/port) identifier: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_PARENT DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port + +/* Node's index in its parent's list of children: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_CHILD_IDX 0 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_NODELABEL_NUM 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_FOREACH_NODELABEL(fn) fn(ov7670_ep_out) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_FOREACH_NODELABEL_VARGS(fn, ...) fn(ov7670_ep_out, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_CHILD_NUM 0 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_ORD 185 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_ORD_STR_SORTABLE 00185 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_REQUIRES_ORDS \ + 184, /* /soc/i2c@58001c00/ov7670@21/port */ + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_SUPPORTS_ORDS /* nothing */ + +/* Existence and alternate IDs: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_EXISTS 1 +#define DT_N_NODELABEL_ov7670_ep_out DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint + +/* Bus info (controller: '/soc/i2c@58001c00', type: '['i2c']') */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_BUS_i2c 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_BUS DT_N_S_soc_S_i2c_58001c00 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_REG_NUM 0 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_RANGES_NUM 0 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_IRQ_NUM 0 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_IRQ_LEVEL 0 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_PINCTRL_NUM 0 + +/* (No generic property macros) */ + /* * Devicetree node: /soc/pin-controller@58020000/fmc_a0_pf0 * @@ -22223,7 +26899,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_CHILD_IDX 41 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_CHILD_IDX 58 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_NODELABEL_NUM 1 @@ -22243,16 +26919,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_ORD 152 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_ORD_STR_SORTABLE 00152 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_ORD 186 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_ORD_STR_SORTABLE 00186 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_EXISTS 1 @@ -22322,7 +26998,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_CHILD_IDX 52 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_CHILD_IDX 69 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_NODELABEL_NUM 1 @@ -22342,16 +27018,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_ORD 153 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_ORD_STR_SORTABLE 00153 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_ORD 187 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_ORD_STR_SORTABLE 00187 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_EXISTS 1 @@ -22421,7 +27097,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_CHILD_IDX 53 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_CHILD_IDX 70 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_NODELABEL_NUM 1 @@ -22441,16 +27117,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_ORD 154 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_ORD_STR_SORTABLE 00154 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_ORD 188 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_ORD_STR_SORTABLE 00188 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_EXISTS 1 @@ -22520,7 +27196,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_CHILD_IDX 54 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_CHILD_IDX 71 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_NODELABEL_NUM 1 @@ -22540,16 +27216,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_ORD 155 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_ORD_STR_SORTABLE 00155 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_ORD 189 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_ORD_STR_SORTABLE 00189 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_EXISTS 1 @@ -22619,7 +27295,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_CHILD_IDX 55 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_CHILD_IDX 72 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_NODELABEL_NUM 1 @@ -22639,16 +27315,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_ORD 156 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_ORD_STR_SORTABLE 00156 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_ORD 190 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_ORD_STR_SORTABLE 00190 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_EXISTS 1 @@ -22718,7 +27394,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_CHILD_IDX 56 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_CHILD_IDX 73 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_NODELABEL_NUM 1 @@ -22738,16 +27414,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_ORD 157 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_ORD_STR_SORTABLE 00157 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_ORD 191 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_ORD_STR_SORTABLE 00191 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_EXISTS 1 @@ -22817,7 +27493,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_CHILD_IDX 42 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_CHILD_IDX 59 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_NODELABEL_NUM 1 @@ -22837,16 +27513,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_ORD 158 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_ORD_STR_SORTABLE 00158 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_ORD 192 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_ORD_STR_SORTABLE 00192 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_EXISTS 1 @@ -22916,7 +27592,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_CHILD_IDX 43 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_CHILD_IDX 60 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_NODELABEL_NUM 1 @@ -22936,16 +27612,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_ORD 159 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_ORD_STR_SORTABLE 00159 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_ORD 193 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_ORD_STR_SORTABLE 00193 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_EXISTS 1 @@ -23015,7 +27691,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_CHILD_IDX 44 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_CHILD_IDX 61 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_NODELABEL_NUM 1 @@ -23035,16 +27711,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_ORD 160 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_ORD_STR_SORTABLE 00160 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_ORD 194 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_ORD_STR_SORTABLE 00194 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_EXISTS 1 @@ -23114,7 +27790,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_CHILD_IDX 45 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_CHILD_IDX 62 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_NODELABEL_NUM 1 @@ -23134,16 +27810,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_ORD 161 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_ORD_STR_SORTABLE 00161 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_ORD 195 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_ORD_STR_SORTABLE 00195 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_EXISTS 1 @@ -23213,7 +27889,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_CHILD_IDX 46 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_CHILD_IDX 63 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_NODELABEL_NUM 1 @@ -23233,16 +27909,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_ORD 162 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_ORD_STR_SORTABLE 00162 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_ORD 196 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_ORD_STR_SORTABLE 00196 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_EXISTS 1 @@ -23312,7 +27988,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_CHILD_IDX 48 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_CHILD_IDX 65 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_NODELABEL_NUM 1 @@ -23332,16 +28008,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_ORD 163 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_ORD_STR_SORTABLE 00163 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_ORD 197 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_ORD_STR_SORTABLE 00197 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_EXISTS 1 @@ -23411,7 +28087,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_CHILD_IDX 49 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_CHILD_IDX 66 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_NODELABEL_NUM 1 @@ -23431,16 +28107,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_ORD 164 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_ORD_STR_SORTABLE 00164 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_ORD 198 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_ORD_STR_SORTABLE 00198 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_EXISTS 1 @@ -23510,7 +28186,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_CHILD_IDX 50 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_CHILD_IDX 67 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_NODELABEL_NUM 1 @@ -23530,16 +28206,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_ORD 165 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_ORD_STR_SORTABLE 00165 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_ORD 199 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_ORD_STR_SORTABLE 00199 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_EXISTS 1 @@ -23609,7 +28285,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_CHILD_IDX 51 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_CHILD_IDX 68 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_NODELABEL_NUM 1 @@ -23629,16 +28305,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_ORD 166 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_ORD_STR_SORTABLE 00166 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_ORD 200 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_ORD_STR_SORTABLE 00200 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_EXISTS 1 @@ -23708,7 +28384,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_CHILD_IDX 28 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_CHILD_IDX 45 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_NODELABEL_NUM 1 @@ -23728,16 +28404,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_ORD 167 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_ORD_STR_SORTABLE 00167 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_ORD 201 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_ORD_STR_SORTABLE 00201 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_EXISTS 1 @@ -23807,7 +28483,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_CHILD_IDX 38 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_CHILD_IDX 55 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_NODELABEL_NUM 1 @@ -23827,16 +28503,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_ORD 168 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_ORD_STR_SORTABLE 00168 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_ORD 202 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_ORD_STR_SORTABLE 00202 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_EXISTS 1 @@ -23906,7 +28582,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_CHILD_IDX 39 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_CHILD_IDX 56 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_NODELABEL_NUM 1 @@ -23926,16 +28602,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_ORD 169 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_ORD_STR_SORTABLE 00169 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_ORD 203 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_ORD_STR_SORTABLE 00203 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_EXISTS 1 @@ -24005,7 +28681,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_CHILD_IDX 40 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_CHILD_IDX 57 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_NODELABEL_NUM 1 @@ -24025,16 +28701,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_ORD 170 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_ORD_STR_SORTABLE 00170 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_ORD 204 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_ORD_STR_SORTABLE 00204 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_EXISTS 1 @@ -24104,7 +28780,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_CHILD_IDX 25 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_CHILD_IDX 42 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_NODELABEL_NUM 1 @@ -24124,16 +28800,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_ORD 171 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_ORD_STR_SORTABLE 00171 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_ORD 205 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_ORD_STR_SORTABLE 00205 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_EXISTS 1 @@ -24203,7 +28879,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_CHILD_IDX 26 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_CHILD_IDX 43 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_NODELABEL_NUM 1 @@ -24223,16 +28899,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_ORD 172 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_ORD_STR_SORTABLE 00172 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_ORD 206 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_ORD_STR_SORTABLE 00206 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_EXISTS 1 @@ -24302,7 +28978,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_CHILD_IDX 27 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_CHILD_IDX 44 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_NODELABEL_NUM 1 @@ -24322,16 +28998,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_ORD 173 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_ORD_STR_SORTABLE 00173 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_ORD 207 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_ORD_STR_SORTABLE 00207 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_EXISTS 1 @@ -24401,7 +29077,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_CHILD_IDX 29 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_CHILD_IDX 46 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_NODELABEL_NUM 1 @@ -24421,16 +29097,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_ORD 174 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_ORD_STR_SORTABLE 00174 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_ORD 208 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_ORD_STR_SORTABLE 00208 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_EXISTS 1 @@ -24500,7 +29176,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_CHILD_IDX 23 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_CHILD_IDX 40 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_NODELABEL_NUM 1 @@ -24520,16 +29196,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_ORD 175 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_ORD_STR_SORTABLE 00175 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_ORD 209 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_ORD_STR_SORTABLE 00209 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_EXISTS 1 @@ -24599,7 +29275,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_CHILD_IDX 24 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_CHILD_IDX 41 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_NODELABEL_NUM 1 @@ -24619,16 +29295,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_ORD 176 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_ORD_STR_SORTABLE 00176 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_ORD 210 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_ORD_STR_SORTABLE 00210 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_EXISTS 1 @@ -24698,7 +29374,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_CHILD_IDX 32 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_CHILD_IDX 49 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_NODELABEL_NUM 1 @@ -24718,16 +29394,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_ORD 177 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_ORD_STR_SORTABLE 00177 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_ORD 211 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_ORD_STR_SORTABLE 00211 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_EXISTS 1 @@ -24797,7 +29473,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_CHILD_IDX 33 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_CHILD_IDX 50 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_NODELABEL_NUM 1 @@ -24817,16 +29493,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_ORD 178 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_ORD_STR_SORTABLE 00178 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_ORD 212 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_ORD_STR_SORTABLE 00212 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_EXISTS 1 @@ -24896,7 +29572,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_CHILD_IDX 34 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_CHILD_IDX 51 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_NODELABEL_NUM 1 @@ -24916,16 +29592,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_ORD 179 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_ORD_STR_SORTABLE 00179 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_ORD 213 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_ORD_STR_SORTABLE 00213 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_EXISTS 1 @@ -24995,7 +29671,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_CHILD_IDX 35 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_CHILD_IDX 52 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_NODELABEL_NUM 1 @@ -25015,16 +29691,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_ORD 180 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_ORD_STR_SORTABLE 00180 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_ORD 214 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_ORD_STR_SORTABLE 00214 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_EXISTS 1 @@ -25094,7 +29770,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_CHILD_IDX 36 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_CHILD_IDX 53 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_NODELABEL_NUM 1 @@ -25114,16 +29790,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_ORD 181 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_ORD_STR_SORTABLE 00181 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_ORD 215 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_ORD_STR_SORTABLE 00215 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_EXISTS 1 @@ -25193,7 +29869,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_CHILD_IDX 37 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_CHILD_IDX 54 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_NODELABEL_NUM 1 @@ -25213,16 +29889,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_ORD 182 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_ORD_STR_SORTABLE 00182 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_ORD 216 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_ORD_STR_SORTABLE 00216 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_EXISTS 1 @@ -25292,7 +29968,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_CHILD_IDX 30 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_CHILD_IDX 47 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_NODELABEL_NUM 1 @@ -25312,16 +29988,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_ORD 183 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_ORD_STR_SORTABLE 00183 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_ORD 217 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_ORD_STR_SORTABLE 00217 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_EXISTS 1 @@ -25391,7 +30067,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_CHILD_IDX 31 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_CHILD_IDX 48 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_NODELABEL_NUM 1 @@ -25411,16 +30087,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_ORD 184 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_ORD_STR_SORTABLE 00184 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_ORD 218 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_ORD_STR_SORTABLE 00218 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_EXISTS 1 @@ -25490,7 +30166,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_CHILD_IDX 59 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_CHILD_IDX 76 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_NODELABEL_NUM 1 @@ -25510,16 +30186,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_ORD 185 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_ORD_STR_SORTABLE 00185 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_ORD 219 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_ORD_STR_SORTABLE 00219 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_EXISTS 1 @@ -25589,7 +30265,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_CHILD_IDX 57 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_CHILD_IDX 74 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_NODELABEL_NUM 1 @@ -25609,16 +30285,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_ORD 186 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_ORD_STR_SORTABLE 00186 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_ORD 220 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_ORD_STR_SORTABLE 00220 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_EXISTS 1 @@ -25688,7 +30364,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_CHILD_IDX 58 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_CHILD_IDX 75 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_NODELABEL_NUM 1 @@ -25708,16 +30384,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_ORD 187 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_ORD_STR_SORTABLE 00187 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_ORD 221 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_ORD_STR_SORTABLE 00221 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_EXISTS 1 @@ -25787,7 +30463,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_CHILD_IDX 60 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_CHILD_IDX 77 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_NODELABEL_NUM 1 @@ -25807,16 +30483,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_ORD 188 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_ORD_STR_SORTABLE 00188 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_ORD 222 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_ORD_STR_SORTABLE 00222 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_EXISTS 1 @@ -25886,7 +30562,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_CHILD_IDX 47 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_CHILD_IDX 64 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_NODELABEL_NUM 1 @@ -25906,16 +30582,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_ORD 189 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_ORD_STR_SORTABLE 00189 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_ORD 223 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_ORD_STR_SORTABLE 00223 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_EXISTS 1 @@ -25985,7 +30661,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_CHILD_IDX 61 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_CHILD_IDX 78 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_NODELABEL_NUM 1 @@ -26005,16 +30681,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_ORD 190 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_ORD_STR_SORTABLE 00190 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_ORD 224 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_ORD_STR_SORTABLE 00224 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_SUPPORTS_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_EXISTS 1 @@ -26107,56 +30783,56 @@ #define DT_N_S_soc_S_memory_controller_52004000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_memory_controller_52004000_ORD 191 -#define DT_N_S_soc_S_memory_controller_52004000_ORD_STR_SORTABLE 00191 +#define DT_N_S_soc_S_memory_controller_52004000_ORD 225 +#define DT_N_S_soc_S_memory_controller_52004000_ORD_STR_SORTABLE 00225 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_memory_controller_52004000_REQUIRES_ORDS \ 4, /* /soc */ \ 9, /* /soc/rcc@58024400 */ \ - 152, /* /soc/pin-controller@58020000/fmc_a0_pf0 */ \ - 153, /* /soc/pin-controller@58020000/fmc_a10_pg0 */ \ - 154, /* /soc/pin-controller@58020000/fmc_a11_pg1 */ \ - 155, /* /soc/pin-controller@58020000/fmc_a12_pg2 */ \ - 156, /* /soc/pin-controller@58020000/fmc_a14_pg4 */ \ - 157, /* /soc/pin-controller@58020000/fmc_a15_pg5 */ \ - 158, /* /soc/pin-controller@58020000/fmc_a1_pf1 */ \ - 159, /* /soc/pin-controller@58020000/fmc_a2_pf2 */ \ - 160, /* /soc/pin-controller@58020000/fmc_a3_pf3 */ \ - 161, /* /soc/pin-controller@58020000/fmc_a4_pf4 */ \ - 162, /* /soc/pin-controller@58020000/fmc_a5_pf5 */ \ - 163, /* /soc/pin-controller@58020000/fmc_a6_pf12 */ \ - 164, /* /soc/pin-controller@58020000/fmc_a7_pf13 */ \ - 165, /* /soc/pin-controller@58020000/fmc_a8_pf14 */ \ - 166, /* /soc/pin-controller@58020000/fmc_a9_pf15 */ \ - 167, /* /soc/pin-controller@58020000/fmc_d0_pd14 */ \ - 168, /* /soc/pin-controller@58020000/fmc_d10_pe13 */ \ - 169, /* /soc/pin-controller@58020000/fmc_d11_pe14 */ \ - 170, /* /soc/pin-controller@58020000/fmc_d12_pe15 */ \ - 171, /* /soc/pin-controller@58020000/fmc_d13_pd8 */ \ - 172, /* /soc/pin-controller@58020000/fmc_d14_pd9 */ \ - 173, /* /soc/pin-controller@58020000/fmc_d15_pd10 */ \ - 174, /* /soc/pin-controller@58020000/fmc_d1_pd15 */ \ - 175, /* /soc/pin-controller@58020000/fmc_d2_pd0 */ \ - 176, /* /soc/pin-controller@58020000/fmc_d3_pd1 */ \ - 177, /* /soc/pin-controller@58020000/fmc_d4_pe7 */ \ - 178, /* /soc/pin-controller@58020000/fmc_d5_pe8 */ \ - 179, /* /soc/pin-controller@58020000/fmc_d6_pe9 */ \ - 180, /* /soc/pin-controller@58020000/fmc_d7_pe10 */ \ - 181, /* /soc/pin-controller@58020000/fmc_d8_pe11 */ \ - 182, /* /soc/pin-controller@58020000/fmc_d9_pe12 */ \ - 183, /* /soc/pin-controller@58020000/fmc_nbl0_pe0 */ \ - 184, /* /soc/pin-controller@58020000/fmc_nbl1_pe1 */ \ - 185, /* /soc/pin-controller@58020000/fmc_sdcke0_ph2 */ \ - 186, /* /soc/pin-controller@58020000/fmc_sdclk_pg8 */ \ - 187, /* /soc/pin-controller@58020000/fmc_sdncas_pg15 */ \ - 188, /* /soc/pin-controller@58020000/fmc_sdne0_ph3 */ \ - 189, /* /soc/pin-controller@58020000/fmc_sdnras_pf11 */ \ - 190, /* /soc/pin-controller@58020000/fmc_sdnwe_ph5 */ + 186, /* /soc/pin-controller@58020000/fmc_a0_pf0 */ \ + 187, /* /soc/pin-controller@58020000/fmc_a10_pg0 */ \ + 188, /* /soc/pin-controller@58020000/fmc_a11_pg1 */ \ + 189, /* /soc/pin-controller@58020000/fmc_a12_pg2 */ \ + 190, /* /soc/pin-controller@58020000/fmc_a14_pg4 */ \ + 191, /* /soc/pin-controller@58020000/fmc_a15_pg5 */ \ + 192, /* /soc/pin-controller@58020000/fmc_a1_pf1 */ \ + 193, /* /soc/pin-controller@58020000/fmc_a2_pf2 */ \ + 194, /* /soc/pin-controller@58020000/fmc_a3_pf3 */ \ + 195, /* /soc/pin-controller@58020000/fmc_a4_pf4 */ \ + 196, /* /soc/pin-controller@58020000/fmc_a5_pf5 */ \ + 197, /* /soc/pin-controller@58020000/fmc_a6_pf12 */ \ + 198, /* /soc/pin-controller@58020000/fmc_a7_pf13 */ \ + 199, /* /soc/pin-controller@58020000/fmc_a8_pf14 */ \ + 200, /* /soc/pin-controller@58020000/fmc_a9_pf15 */ \ + 201, /* /soc/pin-controller@58020000/fmc_d0_pd14 */ \ + 202, /* /soc/pin-controller@58020000/fmc_d10_pe13 */ \ + 203, /* /soc/pin-controller@58020000/fmc_d11_pe14 */ \ + 204, /* /soc/pin-controller@58020000/fmc_d12_pe15 */ \ + 205, /* /soc/pin-controller@58020000/fmc_d13_pd8 */ \ + 206, /* /soc/pin-controller@58020000/fmc_d14_pd9 */ \ + 207, /* /soc/pin-controller@58020000/fmc_d15_pd10 */ \ + 208, /* /soc/pin-controller@58020000/fmc_d1_pd15 */ \ + 209, /* /soc/pin-controller@58020000/fmc_d2_pd0 */ \ + 210, /* /soc/pin-controller@58020000/fmc_d3_pd1 */ \ + 211, /* /soc/pin-controller@58020000/fmc_d4_pe7 */ \ + 212, /* /soc/pin-controller@58020000/fmc_d5_pe8 */ \ + 213, /* /soc/pin-controller@58020000/fmc_d6_pe9 */ \ + 214, /* /soc/pin-controller@58020000/fmc_d7_pe10 */ \ + 215, /* /soc/pin-controller@58020000/fmc_d8_pe11 */ \ + 216, /* /soc/pin-controller@58020000/fmc_d9_pe12 */ \ + 217, /* /soc/pin-controller@58020000/fmc_nbl0_pe0 */ \ + 218, /* /soc/pin-controller@58020000/fmc_nbl1_pe1 */ \ + 219, /* /soc/pin-controller@58020000/fmc_sdcke0_ph2 */ \ + 220, /* /soc/pin-controller@58020000/fmc_sdclk_pg8 */ \ + 221, /* /soc/pin-controller@58020000/fmc_sdncas_pg15 */ \ + 222, /* /soc/pin-controller@58020000/fmc_sdne0_ph3 */ \ + 223, /* /soc/pin-controller@58020000/fmc_sdnras_pf11 */ \ + 224, /* /soc/pin-controller@58020000/fmc_sdnwe_ph5 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_memory_controller_52004000_SUPPORTS_ORDS \ - 192, /* /soc/memory-controller@52004000/sdram */ + 226, /* /soc/memory-controller@52004000/sdram */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_memory_controller_52004000_EXISTS 1 @@ -26625,16 +31301,16 @@ #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_ORD 192 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_ORD_STR_SORTABLE 00192 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_ORD 226 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_ORD_STR_SORTABLE 00226 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_REQUIRES_ORDS \ - 191, /* /soc/memory-controller@52004000 */ + 225, /* /soc/memory-controller@52004000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_SUPPORTS_ORDS \ - 193, /* /soc/memory-controller@52004000/sdram/bank@0 */ + 227, /* /soc/memory-controller@52004000/sdram/bank@0 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_EXISTS 1 @@ -26740,12 +31416,12 @@ #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_ORD 193 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_ORD_STR_SORTABLE 00193 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_ORD 227 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_ORD_STR_SORTABLE 00227 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_REQUIRES_ORDS \ - 192, /* /soc/memory-controller@52004000/sdram */ + 226, /* /soc/memory-controller@52004000/sdram */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_SUPPORTS_ORDS /* nothing */ @@ -26908,13 +31584,13 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_ORD 194 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_ORD_STR_SORTABLE 00194 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_ORD 228 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_ORD_STR_SORTABLE 00228 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_REQUIRES_ORDS \ 9, /* /soc/rcc@58024400 */ \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_SUPPORTS_ORDS /* nothing */ @@ -27004,7 +31680,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_CHILD_IDX 68 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_CHILD_IDX 85 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_NODELABEL_NUM 1 @@ -27024,16 +31700,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_ORD 195 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_ORD_STR_SORTABLE 00195 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_ORD 229 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_ORD_STR_SORTABLE 00229 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_SUPPORTS_ORDS \ - 201, /* /soc/quadspi@52005000 */ + 235, /* /soc/quadspi@52005000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_EXISTS 1 @@ -27103,7 +31779,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_CHILD_IDX 69 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_CHILD_IDX 86 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_NODELABEL_NUM 1 @@ -27123,16 +31799,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_ORD 196 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_ORD_STR_SORTABLE 00196 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_ORD 230 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_ORD_STR_SORTABLE 00230 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_SUPPORTS_ORDS \ - 201, /* /soc/quadspi@52005000 */ + 235, /* /soc/quadspi@52005000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_EXISTS 1 @@ -27202,7 +31878,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_CHILD_IDX 70 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_CHILD_IDX 87 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_NODELABEL_NUM 1 @@ -27222,16 +31898,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_ORD 197 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_ORD_STR_SORTABLE 00197 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_ORD 231 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_ORD_STR_SORTABLE 00231 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_SUPPORTS_ORDS \ - 201, /* /soc/quadspi@52005000 */ + 235, /* /soc/quadspi@52005000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_EXISTS 1 @@ -27301,7 +31977,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_CHILD_IDX 71 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_CHILD_IDX 88 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_NODELABEL_NUM 1 @@ -27321,16 +31997,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_ORD 198 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_ORD_STR_SORTABLE 00198 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_ORD 232 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_ORD_STR_SORTABLE 00232 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_SUPPORTS_ORDS \ - 201, /* /soc/quadspi@52005000 */ + 235, /* /soc/quadspi@52005000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_EXISTS 1 @@ -27400,7 +32076,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_CHILD_IDX 73 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_CHILD_IDX 90 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_NODELABEL_NUM 1 @@ -27420,16 +32096,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_ORD 199 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_ORD_STR_SORTABLE 00199 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_ORD 233 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_ORD_STR_SORTABLE 00233 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_SUPPORTS_ORDS \ - 201, /* /soc/quadspi@52005000 */ + 235, /* /soc/quadspi@52005000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_EXISTS 1 @@ -27499,7 +32175,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_CHILD_IDX 72 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_CHILD_IDX 89 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_NODELABEL_NUM 1 @@ -27519,16 +32195,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_ORD 200 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_ORD_STR_SORTABLE 00200 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_ORD 234 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_ORD_STR_SORTABLE 00234 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_SUPPORTS_ORDS \ - 201, /* /soc/quadspi@52005000 */ + 235, /* /soc/quadspi@52005000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_EXISTS 1 @@ -27621,24 +32297,24 @@ #define DT_N_S_soc_S_quadspi_52005000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_quadspi_52005000_ORD 201 -#define DT_N_S_soc_S_quadspi_52005000_ORD_STR_SORTABLE 00201 +#define DT_N_S_soc_S_quadspi_52005000_ORD 235 +#define DT_N_S_soc_S_quadspi_52005000_ORD_STR_SORTABLE 00235 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_quadspi_52005000_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 195, /* /soc/pin-controller@58020000/quadspi_bk1_io0_pd11 */ \ - 196, /* /soc/pin-controller@58020000/quadspi_bk1_io1_pd12 */ \ - 197, /* /soc/pin-controller@58020000/quadspi_bk1_io2_pe2 */ \ - 198, /* /soc/pin-controller@58020000/quadspi_bk1_io3_pf6 */ \ - 199, /* /soc/pin-controller@58020000/quadspi_bk1_ncs_pg6 */ \ - 200, /* /soc/pin-controller@58020000/quadspi_clk_pf10 */ + 229, /* /soc/pin-controller@58020000/quadspi_bk1_io0_pd11 */ \ + 230, /* /soc/pin-controller@58020000/quadspi_bk1_io1_pd12 */ \ + 231, /* /soc/pin-controller@58020000/quadspi_bk1_io2_pe2 */ \ + 232, /* /soc/pin-controller@58020000/quadspi_bk1_io3_pf6 */ \ + 233, /* /soc/pin-controller@58020000/quadspi_bk1_ncs_pg6 */ \ + 234, /* /soc/pin-controller@58020000/quadspi_clk_pf10 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_quadspi_52005000_SUPPORTS_ORDS \ - 202, /* /soc/quadspi@52005000/qspi-nor-flash@90000000 */ + 236, /* /soc/quadspi@52005000/qspi-nor-flash@90000000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_quadspi_52005000_EXISTS 1 @@ -27842,16 +32518,16 @@ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_ORD 202 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_ORD_STR_SORTABLE 00202 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_ORD 236 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_ORD_STR_SORTABLE 00236 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_REQUIRES_ORDS \ - 201, /* /soc/quadspi@52005000 */ + 235, /* /soc/quadspi@52005000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_SUPPORTS_ORDS \ - 203, /* /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions */ + 237, /* /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_EXISTS 1 @@ -27972,17 +32648,17 @@ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_ORD 203 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_ORD_STR_SORTABLE 00203 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_ORD 237 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_ORD_STR_SORTABLE 00237 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_REQUIRES_ORDS \ - 202, /* /soc/quadspi@52005000/qspi-nor-flash@90000000 */ + 236, /* /soc/quadspi@52005000/qspi-nor-flash@90000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_SUPPORTS_ORDS \ - 204, /* /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions/partition@0 */ \ - 205, /* /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions/partition@100000 */ + 238, /* /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions/partition@0 */ \ + 239, /* /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions/partition@100000 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_EXISTS 1 @@ -28041,12 +32717,12 @@ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_ORD 204 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_ORD_STR_SORTABLE 00204 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_ORD 238 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_ORD_STR_SORTABLE 00238 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_REQUIRES_ORDS \ - 203, /* /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions */ + 237, /* /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_SUPPORTS_ORDS /* nothing */ @@ -28070,7 +32746,7 @@ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_PINCTRL_NUM 0 /* fixed-partitions identifier: */ -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_PARTITION_ID 2 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_PARTITION_ID 3 /* Generic property macros: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_P_label "image-1" @@ -28133,12 +32809,12 @@ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_ORD 205 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_ORD_STR_SORTABLE 00205 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_ORD 239 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_ORD_STR_SORTABLE 00239 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_REQUIRES_ORDS \ - 203, /* /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions */ + 237, /* /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_SUPPORTS_ORDS /* nothing */ @@ -28162,7 +32838,7 @@ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_PINCTRL_NUM 0 /* fixed-partitions identifier: */ -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_PARTITION_ID 3 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_PARTITION_ID 4 /* Generic property macros: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_P_label "storage" @@ -28228,8 +32904,8 @@ #define DT_N_S_soc_S_rtc_58004000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_rtc_58004000_ORD 206 -#define DT_N_S_soc_S_rtc_58004000_ORD_STR_SORTABLE 00206 +#define DT_N_S_soc_S_rtc_58004000_ORD 240 +#define DT_N_S_soc_S_rtc_58004000_ORD_STR_SORTABLE 00240 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_rtc_58004000_REQUIRES_ORDS \ @@ -28239,7 +32915,7 @@ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_rtc_58004000_SUPPORTS_ORDS \ - 207, /* /soc/rtc@58004000/backup_regs */ + 241, /* /soc/rtc@58004000/backup_regs */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_rtc_58004000_EXISTS 1 @@ -28380,12 +33056,12 @@ #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_ORD 207 -#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_ORD_STR_SORTABLE 00207 +#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_ORD 241 +#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_ORD_STR_SORTABLE 00241 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_REQUIRES_ORDS \ - 206, /* /soc/rtc@58004000 */ + 240, /* /soc/rtc@58004000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_SUPPORTS_ORDS /* nothing */ @@ -28449,126 +33125,6 @@ #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_st_backup_regs 32 #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_st_backup_regs_EXISTS 1 -/* - * Devicetree node: /soc/pin-controller@58020000/gpio@58021800 - * - * Node identifier: DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800 - * - * Binding (compatible = st,stm32-gpio): - * $ZEPHYR_BASE/dts/bindings/gpio/st,stm32-gpio.yaml - * - * (Descriptions have moved to the Devicetree Bindings Index - * in the documentation.) - */ - -/* Node's full path: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_PATH "/soc/pin-controller@58020000/gpio@58021800" - -/* Node's name with unit-address: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FULL_NAME "gpio@58021800" - -/* Node parent (/soc/pin-controller@58020000) identifier: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_PARENT DT_N_S_soc_S_pin_controller_58020000 - -/* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_CHILD_IDX 6 - -/* Helpers for dealing with node labels: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_NODELABEL_NUM 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FOREACH_NODELABEL(fn) fn(gpiog) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpiog, __VA_ARGS__) - -/* Helper macros for child nodes of this node. */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_CHILD_NUM 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_CHILD_NUM_STATUS_OKAY 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FOREACH_CHILD(fn) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FOREACH_CHILD_SEP(fn, sep) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FOREACH_CHILD_VARGS(fn, ...) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FOREACH_CHILD_STATUS_OKAY(fn) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) - -/* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_ORD 208 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_ORD_STR_SORTABLE 00208 - -/* Ordinals for what this node depends on directly: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_REQUIRES_ORDS \ - 9, /* /soc/rcc@58024400 */ \ - 19, /* /soc/pin-controller@58020000 */ - -/* Ordinals for what depends directly on this node: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_SUPPORTS_ORDS \ - 215, /* /soc/serial@40007800/bt_hci_uart/murata-1dx */ - -/* Existence and alternate IDs: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_EXISTS 1 -#define DT_N_INST_6_st_stm32_gpio DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800 -#define DT_N_NODELABEL_gpiog DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800 - -/* Macros for properties that are special in the specification: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_REG_NUM 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_REG_IDX_0_VAL_ADDRESS 1476532224 /* 0x58021800 */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_RANGES_NUM 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FOREACH_RANGE(fn) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_IRQ_NUM 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_IRQ_LEVEL 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_COMPAT_MATCHES_st_stm32_gpio 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_COMPAT_VENDOR_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_COMPAT_VENDOR_IDX_0 "STMicroelectronics" -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_COMPAT_MODEL_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_COMPAT_MODEL_IDX_0 "stm32-gpio" -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_STATUS_okay 1 - -/* Pin control (pinctrl-, pinctrl-names) properties: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_PINCTRL_NUM 0 - -/* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_gpio_controller 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_gpio_controller_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_ngpios 32 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_ngpios_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_wakeup_source 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible {"st,stm32-gpio"} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_IDX_0 "st,stm32-gpio" -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_LEN 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_reg {1476532224 /* 0x58021800 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_reg_IDX_0 1476532224 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_reg_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_IDX_0_VAL_bus 224 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_IDX_0_VAL_bits 64 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, clocks, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, clocks, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_LEN 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_zephyr_deferred_init_EXISTS 1 - /* * Devicetree node: /soc/pin-controller@58020000/uart7_cts_pf9 * @@ -28588,7 +33144,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_CHILD_IDX 82 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_CHILD_IDX 100 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_NODELABEL_NUM 1 @@ -28608,16 +33164,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_ORD 209 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_ORD_STR_SORTABLE 00209 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_ORD 242 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_ORD_STR_SORTABLE 00242 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_SUPPORTS_ORDS \ - 213, /* /soc/serial@40007800 */ + 246, /* /soc/serial@40007800 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_EXISTS 1 @@ -28687,7 +33243,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_CHILD_IDX 83 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_CHILD_IDX 101 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_NODELABEL_NUM 1 @@ -28707,16 +33263,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_ORD 210 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_ORD_STR_SORTABLE 00210 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_ORD 243 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_ORD_STR_SORTABLE 00243 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_SUPPORTS_ORDS \ - 213, /* /soc/serial@40007800 */ + 246, /* /soc/serial@40007800 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_EXISTS 1 @@ -28786,7 +33342,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_CHILD_IDX 87 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_CHILD_IDX 105 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_NODELABEL_NUM 1 @@ -28806,16 +33362,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_ORD 211 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_ORD_STR_SORTABLE 00211 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_ORD 244 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_ORD_STR_SORTABLE 00244 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_SUPPORTS_ORDS \ - 213, /* /soc/serial@40007800 */ + 246, /* /soc/serial@40007800 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_EXISTS 1 @@ -28885,7 +33441,7 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_PARENT DT_N_S_soc_S_pin_controller_58020000 /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_CHILD_IDX 91 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_CHILD_IDX 109 /* Helpers for dealing with node labels: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_NODELABEL_NUM 1 @@ -28905,16 +33461,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_ORD 212 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_ORD_STR_SORTABLE 00212 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_ORD 245 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_ORD_STR_SORTABLE 00245 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_REQUIRES_ORDS \ - 19, /* /soc/pin-controller@58020000 */ + 10, /* /soc/pin-controller@58020000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_SUPPORTS_ORDS \ - 213, /* /soc/serial@40007800 */ + 246, /* /soc/serial@40007800 */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_EXISTS 1 @@ -29007,23 +33563,23 @@ #define DT_N_S_soc_S_serial_40007800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_serial_40007800_ORD 213 -#define DT_N_S_soc_S_serial_40007800_ORD_STR_SORTABLE 00213 +#define DT_N_S_soc_S_serial_40007800_ORD 246 +#define DT_N_S_soc_S_serial_40007800_ORD_STR_SORTABLE 00246 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_serial_40007800_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ \ - 209, /* /soc/pin-controller@58020000/uart7_cts_pf9 */ \ - 210, /* /soc/pin-controller@58020000/uart7_rts_pf8 */ \ - 211, /* /soc/pin-controller@58020000/uart7_rx_pa8 */ \ - 212, /* /soc/pin-controller@58020000/uart7_tx_pf7 */ + 54, /* /soc/rcc@58024400/reset-controller */ \ + 242, /* /soc/pin-controller@58020000/uart7_cts_pf9 */ \ + 243, /* /soc/pin-controller@58020000/uart7_rts_pf8 */ \ + 244, /* /soc/pin-controller@58020000/uart7_rx_pa8 */ \ + 245, /* /soc/pin-controller@58020000/uart7_tx_pf7 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_serial_40007800_SUPPORTS_ORDS \ - 214, /* /soc/serial@40007800/bt_hci_uart */ + 247, /* /soc/serial@40007800/bt_hci_uart */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_serial_40007800_EXISTS 1 @@ -29241,16 +33797,16 @@ #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_ORD 214 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_ORD_STR_SORTABLE 00214 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_ORD 247 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_ORD_STR_SORTABLE 00247 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_REQUIRES_ORDS \ - 213, /* /soc/serial@40007800 */ + 246, /* /soc/serial@40007800 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_SUPPORTS_ORDS \ - 215, /* /soc/serial@40007800/bt_hci_uart/murata-1dx */ + 248, /* /soc/serial@40007800/bt_hci_uart/murata-1dx */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_EXISTS 1 @@ -29385,15 +33941,15 @@ #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_ORD 215 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_ORD_STR_SORTABLE 00215 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_ORD 248 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_ORD_STR_SORTABLE 00248 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_REQUIRES_ORDS \ - 62, /* /soc/pin-controller@58020000/gpio@58020000 */ \ - 67, /* /soc/pin-controller@58020000/gpio@58021C00 */ \ - 208, /* /soc/pin-controller@58020000/gpio@58021800 */ \ - 214, /* /soc/serial@40007800/bt_hci_uart */ + 69, /* /soc/pin-controller@58020000/gpio@58020000 */ \ + 74, /* /soc/pin-controller@58020000/gpio@58021800 */ \ + 75, /* /soc/pin-controller@58020000/gpio@58021C00 */ \ + 247, /* /soc/serial@40007800/bt_hci_uart */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_SUPPORTS_ORDS /* nothing */ @@ -29522,20 +34078,20 @@ #define DT_N_S_soc_S_timers_40000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000000_ORD 216 -#define DT_N_S_soc_S_timers_40000000_ORD_STR_SORTABLE 00216 +#define DT_N_S_soc_S_timers_40000000_ORD 249 +#define DT_N_S_soc_S_timers_40000000_ORD_STR_SORTABLE 00249 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000000_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ + 54, /* /soc/rcc@58024400/reset-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000000_SUPPORTS_ORDS \ - 217, /* /soc/timers@40000000/counter */ \ - 218, /* /soc/timers@40000000/pwm */ + 250, /* /soc/timers@40000000/counter */ \ + 251, /* /soc/timers@40000000/pwm */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40000000_EXISTS 1 @@ -29701,12 +34257,12 @@ #define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000000_S_counter_ORD 217 -#define DT_N_S_soc_S_timers_40000000_S_counter_ORD_STR_SORTABLE 00217 +#define DT_N_S_soc_S_timers_40000000_S_counter_ORD 250 +#define DT_N_S_soc_S_timers_40000000_S_counter_ORD_STR_SORTABLE 00250 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000000_S_counter_REQUIRES_ORDS \ - 216, /* /soc/timers@40000000 */ + 249, /* /soc/timers@40000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000000_S_counter_SUPPORTS_ORDS /* nothing */ @@ -29809,12 +34365,12 @@ #define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000000_S_pwm_ORD 218 -#define DT_N_S_soc_S_timers_40000000_S_pwm_ORD_STR_SORTABLE 00218 +#define DT_N_S_soc_S_timers_40000000_S_pwm_ORD 251 +#define DT_N_S_soc_S_timers_40000000_S_pwm_ORD_STR_SORTABLE 00251 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000000_S_pwm_REQUIRES_ORDS \ - 216, /* /soc/timers@40000000 */ + 249, /* /soc/timers@40000000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000000_S_pwm_SUPPORTS_ORDS /* nothing */ @@ -29919,20 +34475,20 @@ #define DT_N_S_soc_S_timers_40000400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000400_ORD 219 -#define DT_N_S_soc_S_timers_40000400_ORD_STR_SORTABLE 00219 +#define DT_N_S_soc_S_timers_40000400_ORD 252 +#define DT_N_S_soc_S_timers_40000400_ORD_STR_SORTABLE 00252 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000400_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ + 54, /* /soc/rcc@58024400/reset-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000400_SUPPORTS_ORDS \ - 220, /* /soc/timers@40000400/counter */ \ - 221, /* /soc/timers@40000400/pwm */ + 253, /* /soc/timers@40000400/counter */ \ + 254, /* /soc/timers@40000400/pwm */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40000400_EXISTS 1 @@ -30098,12 +34654,12 @@ #define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000400_S_counter_ORD 220 -#define DT_N_S_soc_S_timers_40000400_S_counter_ORD_STR_SORTABLE 00220 +#define DT_N_S_soc_S_timers_40000400_S_counter_ORD 253 +#define DT_N_S_soc_S_timers_40000400_S_counter_ORD_STR_SORTABLE 00253 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000400_S_counter_REQUIRES_ORDS \ - 219, /* /soc/timers@40000400 */ + 252, /* /soc/timers@40000400 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000400_S_counter_SUPPORTS_ORDS /* nothing */ @@ -30206,12 +34762,12 @@ #define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000400_S_pwm_ORD 221 -#define DT_N_S_soc_S_timers_40000400_S_pwm_ORD_STR_SORTABLE 00221 +#define DT_N_S_soc_S_timers_40000400_S_pwm_ORD 254 +#define DT_N_S_soc_S_timers_40000400_S_pwm_ORD_STR_SORTABLE 00254 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000400_S_pwm_REQUIRES_ORDS \ - 219, /* /soc/timers@40000400 */ + 252, /* /soc/timers@40000400 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000400_S_pwm_SUPPORTS_ORDS /* nothing */ @@ -30316,20 +34872,20 @@ #define DT_N_S_soc_S_timers_40000800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000800_ORD 222 -#define DT_N_S_soc_S_timers_40000800_ORD_STR_SORTABLE 00222 +#define DT_N_S_soc_S_timers_40000800_ORD 255 +#define DT_N_S_soc_S_timers_40000800_ORD_STR_SORTABLE 00255 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000800_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ + 54, /* /soc/rcc@58024400/reset-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000800_SUPPORTS_ORDS \ - 223, /* /soc/timers@40000800/counter */ \ - 224, /* /soc/timers@40000800/pwm */ + 256, /* /soc/timers@40000800/counter */ \ + 257, /* /soc/timers@40000800/pwm */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40000800_EXISTS 1 @@ -30495,12 +35051,12 @@ #define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000800_S_counter_ORD 223 -#define DT_N_S_soc_S_timers_40000800_S_counter_ORD_STR_SORTABLE 00223 +#define DT_N_S_soc_S_timers_40000800_S_counter_ORD 256 +#define DT_N_S_soc_S_timers_40000800_S_counter_ORD_STR_SORTABLE 00256 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000800_S_counter_REQUIRES_ORDS \ - 222, /* /soc/timers@40000800 */ + 255, /* /soc/timers@40000800 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000800_S_counter_SUPPORTS_ORDS /* nothing */ @@ -30603,12 +35159,12 @@ #define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000800_S_pwm_ORD 224 -#define DT_N_S_soc_S_timers_40000800_S_pwm_ORD_STR_SORTABLE 00224 +#define DT_N_S_soc_S_timers_40000800_S_pwm_ORD 257 +#define DT_N_S_soc_S_timers_40000800_S_pwm_ORD_STR_SORTABLE 00257 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000800_S_pwm_REQUIRES_ORDS \ - 222, /* /soc/timers@40000800 */ + 255, /* /soc/timers@40000800 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000800_S_pwm_SUPPORTS_ORDS /* nothing */ @@ -30713,20 +35269,20 @@ #define DT_N_S_soc_S_timers_40000c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000c00_ORD 225 -#define DT_N_S_soc_S_timers_40000c00_ORD_STR_SORTABLE 00225 +#define DT_N_S_soc_S_timers_40000c00_ORD 258 +#define DT_N_S_soc_S_timers_40000c00_ORD_STR_SORTABLE 00258 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000c00_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ + 54, /* /soc/rcc@58024400/reset-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000c00_SUPPORTS_ORDS \ - 226, /* /soc/timers@40000c00/counter */ \ - 227, /* /soc/timers@40000c00/pwm */ + 259, /* /soc/timers@40000c00/counter */ \ + 260, /* /soc/timers@40000c00/pwm */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40000c00_EXISTS 1 @@ -30892,12 +35448,12 @@ #define DT_N_S_soc_S_timers_40000c00_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000c00_S_counter_ORD 226 -#define DT_N_S_soc_S_timers_40000c00_S_counter_ORD_STR_SORTABLE 00226 +#define DT_N_S_soc_S_timers_40000c00_S_counter_ORD 259 +#define DT_N_S_soc_S_timers_40000c00_S_counter_ORD_STR_SORTABLE 00259 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000c00_S_counter_REQUIRES_ORDS \ - 225, /* /soc/timers@40000c00 */ + 258, /* /soc/timers@40000c00 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000c00_S_counter_SUPPORTS_ORDS /* nothing */ @@ -31000,12 +35556,12 @@ #define DT_N_S_soc_S_timers_40000c00_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000c00_S_pwm_ORD 227 -#define DT_N_S_soc_S_timers_40000c00_S_pwm_ORD_STR_SORTABLE 00227 +#define DT_N_S_soc_S_timers_40000c00_S_pwm_ORD 260 +#define DT_N_S_soc_S_timers_40000c00_S_pwm_ORD_STR_SORTABLE 00260 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000c00_S_pwm_REQUIRES_ORDS \ - 225, /* /soc/timers@40000c00 */ + 258, /* /soc/timers@40000c00 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000c00_S_pwm_SUPPORTS_ORDS /* nothing */ @@ -31110,19 +35666,19 @@ #define DT_N_S_soc_S_timers_40001000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40001000_ORD 228 -#define DT_N_S_soc_S_timers_40001000_ORD_STR_SORTABLE 00228 +#define DT_N_S_soc_S_timers_40001000_ORD 261 +#define DT_N_S_soc_S_timers_40001000_ORD_STR_SORTABLE 00261 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40001000_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ + 54, /* /soc/rcc@58024400/reset-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40001000_SUPPORTS_ORDS \ - 229, /* /soc/timers@40001000/counter */ + 262, /* /soc/timers@40001000/counter */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40001000_EXISTS 1 @@ -31288,12 +35844,12 @@ #define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40001000_S_counter_ORD 229 -#define DT_N_S_soc_S_timers_40001000_S_counter_ORD_STR_SORTABLE 00229 +#define DT_N_S_soc_S_timers_40001000_S_counter_ORD 262 +#define DT_N_S_soc_S_timers_40001000_S_counter_ORD_STR_SORTABLE 00262 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40001000_S_counter_REQUIRES_ORDS \ - 228, /* /soc/timers@40001000 */ + 261, /* /soc/timers@40001000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40001000_S_counter_SUPPORTS_ORDS /* nothing */ @@ -31396,19 +35952,19 @@ #define DT_N_S_soc_S_timers_40001400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40001400_ORD 230 -#define DT_N_S_soc_S_timers_40001400_ORD_STR_SORTABLE 00230 +#define DT_N_S_soc_S_timers_40001400_ORD 263 +#define DT_N_S_soc_S_timers_40001400_ORD_STR_SORTABLE 00263 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40001400_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ + 54, /* /soc/rcc@58024400/reset-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40001400_SUPPORTS_ORDS \ - 231, /* /soc/timers@40001400/counter */ + 264, /* /soc/timers@40001400/counter */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40001400_EXISTS 1 @@ -31574,12 +36130,12 @@ #define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40001400_S_counter_ORD 231 -#define DT_N_S_soc_S_timers_40001400_S_counter_ORD_STR_SORTABLE 00231 +#define DT_N_S_soc_S_timers_40001400_S_counter_ORD 264 +#define DT_N_S_soc_S_timers_40001400_S_counter_ORD_STR_SORTABLE 00264 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40001400_S_counter_REQUIRES_ORDS \ - 230, /* /soc/timers@40001400 */ + 263, /* /soc/timers@40001400 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40001400_S_counter_SUPPORTS_ORDS /* nothing */ @@ -31682,20 +36238,20 @@ #define DT_N_S_soc_S_timers_40001800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40001800_ORD 232 -#define DT_N_S_soc_S_timers_40001800_ORD_STR_SORTABLE 00232 +#define DT_N_S_soc_S_timers_40001800_ORD 265 +#define DT_N_S_soc_S_timers_40001800_ORD_STR_SORTABLE 00265 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40001800_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ + 54, /* /soc/rcc@58024400/reset-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40001800_SUPPORTS_ORDS \ - 233, /* /soc/timers@40001800/counter */ \ - 234, /* /soc/timers@40001800/pwm */ + 266, /* /soc/timers@40001800/counter */ \ + 267, /* /soc/timers@40001800/pwm */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40001800_EXISTS 1 @@ -31861,12 +36417,12 @@ #define DT_N_S_soc_S_timers_40001800_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40001800_S_counter_ORD 233 -#define DT_N_S_soc_S_timers_40001800_S_counter_ORD_STR_SORTABLE 00233 +#define DT_N_S_soc_S_timers_40001800_S_counter_ORD 266 +#define DT_N_S_soc_S_timers_40001800_S_counter_ORD_STR_SORTABLE 00266 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40001800_S_counter_REQUIRES_ORDS \ - 232, /* /soc/timers@40001800 */ + 265, /* /soc/timers@40001800 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40001800_S_counter_SUPPORTS_ORDS /* nothing */ @@ -31969,12 +36525,12 @@ #define DT_N_S_soc_S_timers_40001800_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40001800_S_pwm_ORD 234 -#define DT_N_S_soc_S_timers_40001800_S_pwm_ORD_STR_SORTABLE 00234 +#define DT_N_S_soc_S_timers_40001800_S_pwm_ORD 267 +#define DT_N_S_soc_S_timers_40001800_S_pwm_ORD_STR_SORTABLE 00267 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40001800_S_pwm_REQUIRES_ORDS \ - 232, /* /soc/timers@40001800 */ + 265, /* /soc/timers@40001800 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40001800_S_pwm_SUPPORTS_ORDS /* nothing */ @@ -32079,20 +36635,20 @@ #define DT_N_S_soc_S_timers_40001c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40001c00_ORD 235 -#define DT_N_S_soc_S_timers_40001c00_ORD_STR_SORTABLE 00235 +#define DT_N_S_soc_S_timers_40001c00_ORD 268 +#define DT_N_S_soc_S_timers_40001c00_ORD_STR_SORTABLE 00268 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40001c00_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ + 54, /* /soc/rcc@58024400/reset-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40001c00_SUPPORTS_ORDS \ - 236, /* /soc/timers@40001c00/counter */ \ - 237, /* /soc/timers@40001c00/pwm */ + 269, /* /soc/timers@40001c00/counter */ \ + 270, /* /soc/timers@40001c00/pwm */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40001c00_EXISTS 1 @@ -32258,12 +36814,12 @@ #define DT_N_S_soc_S_timers_40001c00_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40001c00_S_counter_ORD 236 -#define DT_N_S_soc_S_timers_40001c00_S_counter_ORD_STR_SORTABLE 00236 +#define DT_N_S_soc_S_timers_40001c00_S_counter_ORD 269 +#define DT_N_S_soc_S_timers_40001c00_S_counter_ORD_STR_SORTABLE 00269 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40001c00_S_counter_REQUIRES_ORDS \ - 235, /* /soc/timers@40001c00 */ + 268, /* /soc/timers@40001c00 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40001c00_S_counter_SUPPORTS_ORDS /* nothing */ @@ -32366,12 +36922,12 @@ #define DT_N_S_soc_S_timers_40001c00_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40001c00_S_pwm_ORD 237 -#define DT_N_S_soc_S_timers_40001c00_S_pwm_ORD_STR_SORTABLE 00237 +#define DT_N_S_soc_S_timers_40001c00_S_pwm_ORD 270 +#define DT_N_S_soc_S_timers_40001c00_S_pwm_ORD_STR_SORTABLE 00270 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40001c00_S_pwm_REQUIRES_ORDS \ - 235, /* /soc/timers@40001c00 */ + 268, /* /soc/timers@40001c00 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40001c00_S_pwm_SUPPORTS_ORDS /* nothing */ @@ -32476,20 +37032,20 @@ #define DT_N_S_soc_S_timers_40002000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40002000_ORD 238 -#define DT_N_S_soc_S_timers_40002000_ORD_STR_SORTABLE 00238 +#define DT_N_S_soc_S_timers_40002000_ORD 271 +#define DT_N_S_soc_S_timers_40002000_ORD_STR_SORTABLE 00271 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40002000_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ + 54, /* /soc/rcc@58024400/reset-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40002000_SUPPORTS_ORDS \ - 239, /* /soc/timers@40002000/counter */ \ - 240, /* /soc/timers@40002000/pwm */ + 272, /* /soc/timers@40002000/counter */ \ + 273, /* /soc/timers@40002000/pwm */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40002000_EXISTS 1 @@ -32655,12 +37211,12 @@ #define DT_N_S_soc_S_timers_40002000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40002000_S_counter_ORD 239 -#define DT_N_S_soc_S_timers_40002000_S_counter_ORD_STR_SORTABLE 00239 +#define DT_N_S_soc_S_timers_40002000_S_counter_ORD 272 +#define DT_N_S_soc_S_timers_40002000_S_counter_ORD_STR_SORTABLE 00272 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40002000_S_counter_REQUIRES_ORDS \ - 238, /* /soc/timers@40002000 */ + 271, /* /soc/timers@40002000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40002000_S_counter_SUPPORTS_ORDS /* nothing */ @@ -32763,12 +37319,12 @@ #define DT_N_S_soc_S_timers_40002000_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40002000_S_pwm_ORD 240 -#define DT_N_S_soc_S_timers_40002000_S_pwm_ORD_STR_SORTABLE 00240 +#define DT_N_S_soc_S_timers_40002000_S_pwm_ORD 273 +#define DT_N_S_soc_S_timers_40002000_S_pwm_ORD_STR_SORTABLE 00273 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40002000_S_pwm_REQUIRES_ORDS \ - 238, /* /soc/timers@40002000 */ + 271, /* /soc/timers@40002000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40002000_S_pwm_SUPPORTS_ORDS /* nothing */ @@ -32832,367 +37388,127 @@ #define DT_N_S_soc_S_timers_40002000_S_pwm_P_four_channel_capture_support_EXISTS 1 /* - * Devicetree node: /soc/timers@40010000 - * - * Node identifier: DT_N_S_soc_S_timers_40010000 - * - * Binding (compatible = st,stm32-timers): - * $ZEPHYR_BASE/dts/bindings/timer/st,stm32-timers.yaml - * - * (Descriptions have moved to the Devicetree Bindings Index - * in the documentation.) - */ - -/* Node's full path: */ -#define DT_N_S_soc_S_timers_40010000_PATH "/soc/timers@40010000" - -/* Node's name with unit-address: */ -#define DT_N_S_soc_S_timers_40010000_FULL_NAME "timers@40010000" - -/* Node parent (/soc) identifier: */ -#define DT_N_S_soc_S_timers_40010000_PARENT DT_N_S_soc - -/* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_timers_40010000_CHILD_IDX 33 - -/* Helpers for dealing with node labels: */ -#define DT_N_S_soc_S_timers_40010000_NODELABEL_NUM 1 -#define DT_N_S_soc_S_timers_40010000_FOREACH_NODELABEL(fn) fn(timers1) -#define DT_N_S_soc_S_timers_40010000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers1, __VA_ARGS__) - -/* Helper macros for child nodes of this node. */ -#define DT_N_S_soc_S_timers_40010000_CHILD_NUM 1 -#define DT_N_S_soc_S_timers_40010000_CHILD_NUM_STATUS_OKAY 0 -#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm) -#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm) -#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD_STATUS_OKAY(fn) -#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) -#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) -#define DT_N_S_soc_S_timers_40010000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) - -/* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40010000_ORD 241 -#define DT_N_S_soc_S_timers_40010000_ORD_STR_SORTABLE 00241 - -/* Ordinals for what this node depends on directly: */ -#define DT_N_S_soc_S_timers_40010000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ - -/* Ordinals for what depends directly on this node: */ -#define DT_N_S_soc_S_timers_40010000_SUPPORTS_ORDS \ - 242, /* /soc/timers@40010000/pwm */ - -/* Existence and alternate IDs: */ -#define DT_N_S_soc_S_timers_40010000_EXISTS 1 -#define DT_N_INST_0_st_stm32_timers DT_N_S_soc_S_timers_40010000 -#define DT_N_NODELABEL_timers1 DT_N_S_soc_S_timers_40010000 - -/* Macros for properties that are special in the specification: */ -#define DT_N_S_soc_S_timers_40010000_REG_NUM 1 -#define DT_N_S_soc_S_timers_40010000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_REG_IDX_0_VAL_ADDRESS 1073807360 /* 0x40010000 */ -#define DT_N_S_soc_S_timers_40010000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ -#define DT_N_S_soc_S_timers_40010000_RANGES_NUM 0 -#define DT_N_S_soc_S_timers_40010000_FOREACH_RANGE(fn) -#define DT_N_S_soc_S_timers_40010000_IRQ_NUM 4 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_VAL_irq 24 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_VAL_irq_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_VAL_priority 0 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_VAL_priority_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_VAL_irq 25 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_VAL_irq_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_VAL_priority 0 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_VAL_priority_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_VAL_irq 26 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_VAL_irq_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_VAL_priority 0 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_VAL_priority_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_VAL_irq 27 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_VAL_irq_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_VAL_priority 0 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_VAL_priority_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 -#define DT_N_S_soc_S_timers_40010000_IRQ_LEVEL 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_brk_VAL_irq DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_VAL_irq -#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_brk_VAL_irq_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_brk_VAL_priority DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_VAL_priority -#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_brk_VAL_priority_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_brk_CONTROLLER DT_N_S_soc_S_timers_40010000_IRQ_IDX_0_CONTROLLER -#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_up_VAL_irq DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_VAL_irq -#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_up_VAL_irq_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_up_VAL_priority DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_VAL_priority -#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_up_VAL_priority_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_up_CONTROLLER DT_N_S_soc_S_timers_40010000_IRQ_IDX_1_CONTROLLER -#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_trgcom_VAL_irq DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_VAL_irq -#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_trgcom_VAL_irq_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_trgcom_VAL_priority DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_VAL_priority -#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_trgcom_VAL_priority_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_trgcom_CONTROLLER DT_N_S_soc_S_timers_40010000_IRQ_IDX_2_CONTROLLER -#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_cc_VAL_irq DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_VAL_irq -#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_cc_VAL_irq_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_cc_VAL_priority DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_VAL_priority -#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_cc_VAL_priority_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_IRQ_NAME_cc_CONTROLLER DT_N_S_soc_S_timers_40010000_IRQ_IDX_3_CONTROLLER -#define DT_N_S_soc_S_timers_40010000_COMPAT_MATCHES_st_stm32_timers 1 -#define DT_N_S_soc_S_timers_40010000_COMPAT_VENDOR_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_COMPAT_VENDOR_IDX_0 "STMicroelectronics" -#define DT_N_S_soc_S_timers_40010000_COMPAT_MODEL_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_COMPAT_MODEL_IDX_0 "stm32-timers" -#define DT_N_S_soc_S_timers_40010000_STATUS_disabled 1 - -/* Pin control (pinctrl-, pinctrl-names) properties: */ -#define DT_N_S_soc_S_timers_40010000_PINCTRL_NUM 0 - -/* Generic property macros: */ -#define DT_N_S_soc_S_timers_40010000_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40010000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40010000_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_status "disabled" -#define DT_N_S_soc_S_timers_40010000_P_status_STRING_UNQUOTED disabled -#define DT_N_S_soc_S_timers_40010000_P_status_STRING_TOKEN disabled -#define DT_N_S_soc_S_timers_40010000_P_status_STRING_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_timers_40010000_P_status_IDX_0 "disabled" -#define DT_N_S_soc_S_timers_40010000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40010000_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40010000_P_status_ENUM_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_timers_40010000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, status, 0) -#define DT_N_S_soc_S_timers_40010000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, status, 0) -#define DT_N_S_soc_S_timers_40010000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_P_status_LEN 1 -#define DT_N_S_soc_S_timers_40010000_P_status_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_compatible {"st,stm32-timers"} -#define DT_N_S_soc_S_timers_40010000_P_compatible_IDX_0 "st,stm32-timers" -#define DT_N_S_soc_S_timers_40010000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers -#define DT_N_S_soc_S_timers_40010000_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers -#define DT_N_S_soc_S_timers_40010000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS -#define DT_N_S_soc_S_timers_40010000_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, compatible, 0) -#define DT_N_S_soc_S_timers_40010000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, compatible, 0) -#define DT_N_S_soc_S_timers_40010000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_P_compatible_LEN 1 -#define DT_N_S_soc_S_timers_40010000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_reg {1073807360 /* 0x40010000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_timers_40010000_P_reg_IDX_0 1073807360 -#define DT_N_S_soc_S_timers_40010000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_timers_40010000_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_interrupts {24 /* 0x18 */, 0 /* 0x0 */, 25 /* 0x19 */, 0 /* 0x0 */, 26 /* 0x1a */, 0 /* 0x0 */, 27 /* 0x1b */, 0 /* 0x0 */} -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_0 24 -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_2 25 -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_3 0 -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_4 26 -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_5 0 -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_5_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_6 27 -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_6_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_7 0 -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_7_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_interrupts_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names {"brk", "up", "trgcom", "cc"} -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_0 "brk" -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_0_STRING_UNQUOTED brk -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_0_STRING_TOKEN brk -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN BRK -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_1 "up" -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_1_STRING_UNQUOTED up -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_1_STRING_TOKEN up -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN UP -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_2 "trgcom" -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_2_STRING_UNQUOTED trgcom -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_2_STRING_TOKEN trgcom -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_2_STRING_UPPER_TOKEN TRGCOM -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_3 "cc" -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_3_STRING_UNQUOTED cc -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_3_STRING_TOKEN cc -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_3_STRING_UPPER_TOKEN CC -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 0) \ - fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 1) \ - fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 2) \ - fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 3) -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 1) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 2) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 3) -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 1, __VA_ARGS__) \ - fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 2, __VA_ARGS__) \ - fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 3, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 3, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_LEN 4 -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_VAL_bus 240 -#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_VAL_bits 1 -#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, clocks, 0) -#define DT_N_S_soc_S_timers_40010000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, clocks, 0) -#define DT_N_S_soc_S_timers_40010000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_P_clocks_LEN 1 -#define DT_N_S_soc_S_timers_40010000_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_timers_40010000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_resets_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller -#define DT_N_S_soc_S_timers_40010000_P_resets_IDX_0_VAL_id 4864 -#define DT_N_S_soc_S_timers_40010000_P_resets_IDX_0_VAL_id_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, resets, 0) -#define DT_N_S_soc_S_timers_40010000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, resets, 0) -#define DT_N_S_soc_S_timers_40010000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_P_resets_LEN 1 -#define DT_N_S_soc_S_timers_40010000_P_resets_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_st_prescaler 0 -#define DT_N_S_soc_S_timers_40010000_P_st_prescaler_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_st_countermode 0 -#define DT_N_S_soc_S_timers_40010000_P_st_countermode_EXISTS 1 - -/* - * Devicetree node: /soc/timers@40010000/pwm + * Devicetree node: /soc/timers@40010000/pwm/pwmclock * - * Node identifier: DT_N_S_soc_S_timers_40010000_S_pwm + * Node identifier: DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock * - * Binding (compatible = st,stm32-pwm): - * $ZEPHYR_BASE/dts/bindings/pwm/st,stm32-pwm.yaml + * Binding (compatible = pwm-clock): + * $ZEPHYR_BASE/dts/bindings/clock/pwm-clock.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) */ /* Node's full path: */ -#define DT_N_S_soc_S_timers_40010000_S_pwm_PATH "/soc/timers@40010000/pwm" +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_PATH "/soc/timers@40010000/pwm/pwmclock" /* Node's name with unit-address: */ -#define DT_N_S_soc_S_timers_40010000_S_pwm_FULL_NAME "pwm" +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_FULL_NAME "pwmclock" -/* Node parent (/soc/timers@40010000) identifier: */ -#define DT_N_S_soc_S_timers_40010000_S_pwm_PARENT DT_N_S_soc_S_timers_40010000 +/* Node parent (/soc/timers@40010000/pwm) identifier: */ +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_PARENT DT_N_S_soc_S_timers_40010000_S_pwm /* Node's index in its parent's list of children: */ -#define DT_N_S_soc_S_timers_40010000_S_pwm_CHILD_IDX 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_CHILD_IDX 0 /* Helpers for dealing with node labels: */ -#define DT_N_S_soc_S_timers_40010000_S_pwm_NODELABEL_NUM 0 -#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_NODELABEL(fn) -#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_NODELABEL_VARGS(fn, ...) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_NODELABEL_NUM 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_FOREACH_NODELABEL(fn) fn(pwmclock) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwmclock, __VA_ARGS__) /* Helper macros for child nodes of this node. */ -#define DT_N_S_soc_S_timers_40010000_S_pwm_CHILD_NUM 0 -#define DT_N_S_soc_S_timers_40010000_S_pwm_CHILD_NUM_STATUS_OKAY 0 -#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD(fn) -#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD_SEP(fn, sep) -#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD_VARGS(fn, ...) -#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) -#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD_STATUS_OKAY(fn) -#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) -#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) -#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_CHILD_NUM 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_FOREACH_CHILD(fn) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40010000_S_pwm_ORD 242 -#define DT_N_S_soc_S_timers_40010000_S_pwm_ORD_STR_SORTABLE 00242 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_ORD 274 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_ORD_STR_SORTABLE 00274 /* Ordinals for what this node depends on directly: */ -#define DT_N_S_soc_S_timers_40010000_S_pwm_REQUIRES_ORDS \ - 241, /* /soc/timers@40010000 */ +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_REQUIRES_ORDS \ + 81, /* /soc/timers@40010000/pwm */ /* Ordinals for what depends directly on this node: */ -#define DT_N_S_soc_S_timers_40010000_S_pwm_SUPPORTS_ORDS /* nothing */ +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_SUPPORTS_ORDS /* nothing */ /* Existence and alternate IDs: */ -#define DT_N_S_soc_S_timers_40010000_S_pwm_EXISTS 1 -#define DT_N_INST_0_st_stm32_pwm DT_N_S_soc_S_timers_40010000_S_pwm +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_EXISTS 1 +#define DT_N_INST_0_pwm_clock DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock +#define DT_N_NODELABEL_pwmclock DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock /* Macros for properties that are special in the specification: */ -#define DT_N_S_soc_S_timers_40010000_S_pwm_REG_NUM 0 -#define DT_N_S_soc_S_timers_40010000_S_pwm_RANGES_NUM 0 -#define DT_N_S_soc_S_timers_40010000_S_pwm_FOREACH_RANGE(fn) -#define DT_N_S_soc_S_timers_40010000_S_pwm_IRQ_NUM 0 -#define DT_N_S_soc_S_timers_40010000_S_pwm_IRQ_LEVEL 0 -#define DT_N_S_soc_S_timers_40010000_S_pwm_COMPAT_MATCHES_st_stm32_pwm 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_COMPAT_VENDOR_IDX_0 "STMicroelectronics" -#define DT_N_S_soc_S_timers_40010000_S_pwm_COMPAT_MODEL_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_COMPAT_MODEL_IDX_0 "stm32-pwm" -#define DT_N_S_soc_S_timers_40010000_S_pwm_STATUS_disabled 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_REG_NUM 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_RANGES_NUM 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_FOREACH_RANGE(fn) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_IRQ_NUM 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_IRQ_LEVEL 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_COMPAT_MATCHES_pwm_clock 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_STATUS_okay 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ -#define DT_N_S_soc_S_timers_40010000_S_pwm_PINCTRL_NUM 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status "disabled" -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_STRING_UNQUOTED disabled -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_STRING_TOKEN disabled -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_IDX_0 "disabled" -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_ENUM_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm, status, 0) -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm, status, 0) -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_LEN 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible {"st,stm32-pwm"} -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_IDX_0 "st,stm32-pwm" -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm, compatible, 0) -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm, compatible, 0) -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_LEN 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_four_channel_capture_support 0 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_four_channel_capture_support_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status "okay" +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_STRING_UNQUOTED okay +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_STRING_TOKEN okay +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_STRING_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_IDX_0 "okay" +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_ENUM_IDX 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_ENUM_VAL_okay_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_ENUM_TOKEN okay +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, status, 0) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, status, 0) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_LEN 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_compatible {"pwm-clock"} +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_compatible_IDX_0 "pwm-clock" +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_compatible_IDX_0_STRING_UNQUOTED pwm-clock +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_compatible_IDX_0_STRING_TOKEN pwm_clock +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_compatible_IDX_0_STRING_UPPER_TOKEN PWM_CLOCK +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, compatible, 0) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, compatible, 0) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_compatible_LEN 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_PH DT_N_S_soc_S_timers_40010000_S_pwm +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_VAL_channel 3 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_VAL_channel_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_VAL_period 166 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_VAL_period_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_VAL_flags 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_VAL_flags_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, pwms, 0) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, pwms, 0) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, pwms, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, pwms, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_LEN 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_clock_frequency 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_clock_frequency_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwm_on_delay 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwm_on_delay_EXISTS 1 /* * Devicetree node: /soc/timers@40010400 @@ -33236,19 +37552,19 @@ #define DT_N_S_soc_S_timers_40010400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40010400_ORD 243 -#define DT_N_S_soc_S_timers_40010400_ORD_STR_SORTABLE 00243 +#define DT_N_S_soc_S_timers_40010400_ORD 275 +#define DT_N_S_soc_S_timers_40010400_ORD_STR_SORTABLE 00275 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40010400_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ + 54, /* /soc/rcc@58024400/reset-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40010400_SUPPORTS_ORDS \ - 244, /* /soc/timers@40010400/pwm */ + 276, /* /soc/timers@40010400/pwm */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40010400_EXISTS 1 @@ -33489,12 +37805,12 @@ #define DT_N_S_soc_S_timers_40010400_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40010400_S_pwm_ORD 244 -#define DT_N_S_soc_S_timers_40010400_S_pwm_ORD_STR_SORTABLE 00244 +#define DT_N_S_soc_S_timers_40010400_S_pwm_ORD 276 +#define DT_N_S_soc_S_timers_40010400_S_pwm_ORD_STR_SORTABLE 00276 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40010400_S_pwm_REQUIRES_ORDS \ - 243, /* /soc/timers@40010400 */ + 275, /* /soc/timers@40010400 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40010400_S_pwm_SUPPORTS_ORDS /* nothing */ @@ -33599,20 +37915,20 @@ #define DT_N_S_soc_S_timers_40014000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40014000_ORD 245 -#define DT_N_S_soc_S_timers_40014000_ORD_STR_SORTABLE 00245 +#define DT_N_S_soc_S_timers_40014000_ORD 277 +#define DT_N_S_soc_S_timers_40014000_ORD_STR_SORTABLE 00277 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40014000_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ + 54, /* /soc/rcc@58024400/reset-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40014000_SUPPORTS_ORDS \ - 246, /* /soc/timers@40014000/counter */ \ - 247, /* /soc/timers@40014000/pwm */ + 278, /* /soc/timers@40014000/counter */ \ + 279, /* /soc/timers@40014000/pwm */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40014000_EXISTS 1 @@ -33778,12 +38094,12 @@ #define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40014000_S_counter_ORD 246 -#define DT_N_S_soc_S_timers_40014000_S_counter_ORD_STR_SORTABLE 00246 +#define DT_N_S_soc_S_timers_40014000_S_counter_ORD 278 +#define DT_N_S_soc_S_timers_40014000_S_counter_ORD_STR_SORTABLE 00278 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40014000_S_counter_REQUIRES_ORDS \ - 245, /* /soc/timers@40014000 */ + 277, /* /soc/timers@40014000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40014000_S_counter_SUPPORTS_ORDS /* nothing */ @@ -33886,12 +38202,12 @@ #define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40014000_S_pwm_ORD 247 -#define DT_N_S_soc_S_timers_40014000_S_pwm_ORD_STR_SORTABLE 00247 +#define DT_N_S_soc_S_timers_40014000_S_pwm_ORD 279 +#define DT_N_S_soc_S_timers_40014000_S_pwm_ORD_STR_SORTABLE 00279 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40014000_S_pwm_REQUIRES_ORDS \ - 245, /* /soc/timers@40014000 */ + 277, /* /soc/timers@40014000 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40014000_S_pwm_SUPPORTS_ORDS /* nothing */ @@ -33996,20 +38312,20 @@ #define DT_N_S_soc_S_timers_40014400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40014400_ORD 248 -#define DT_N_S_soc_S_timers_40014400_ORD_STR_SORTABLE 00248 +#define DT_N_S_soc_S_timers_40014400_ORD 280 +#define DT_N_S_soc_S_timers_40014400_ORD_STR_SORTABLE 00280 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40014400_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ + 54, /* /soc/rcc@58024400/reset-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40014400_SUPPORTS_ORDS \ - 249, /* /soc/timers@40014400/counter */ \ - 250, /* /soc/timers@40014400/pwm */ + 281, /* /soc/timers@40014400/counter */ \ + 282, /* /soc/timers@40014400/pwm */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40014400_EXISTS 1 @@ -34175,12 +38491,12 @@ #define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40014400_S_counter_ORD 249 -#define DT_N_S_soc_S_timers_40014400_S_counter_ORD_STR_SORTABLE 00249 +#define DT_N_S_soc_S_timers_40014400_S_counter_ORD 281 +#define DT_N_S_soc_S_timers_40014400_S_counter_ORD_STR_SORTABLE 00281 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40014400_S_counter_REQUIRES_ORDS \ - 248, /* /soc/timers@40014400 */ + 280, /* /soc/timers@40014400 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40014400_S_counter_SUPPORTS_ORDS /* nothing */ @@ -34283,12 +38599,12 @@ #define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40014400_S_pwm_ORD 250 -#define DT_N_S_soc_S_timers_40014400_S_pwm_ORD_STR_SORTABLE 00250 +#define DT_N_S_soc_S_timers_40014400_S_pwm_ORD 282 +#define DT_N_S_soc_S_timers_40014400_S_pwm_ORD_STR_SORTABLE 00282 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40014400_S_pwm_REQUIRES_ORDS \ - 248, /* /soc/timers@40014400 */ + 280, /* /soc/timers@40014400 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40014400_S_pwm_SUPPORTS_ORDS /* nothing */ @@ -34393,20 +38709,20 @@ #define DT_N_S_soc_S_timers_40014800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40014800_ORD 251 -#define DT_N_S_soc_S_timers_40014800_ORD_STR_SORTABLE 00251 +#define DT_N_S_soc_S_timers_40014800_ORD 283 +#define DT_N_S_soc_S_timers_40014800_ORD_STR_SORTABLE 00283 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40014800_REQUIRES_ORDS \ 4, /* /soc */ \ 5, /* /soc/interrupt-controller@e000e100 */ \ 9, /* /soc/rcc@58024400 */ \ - 47, /* /soc/rcc@58024400/reset-controller */ + 54, /* /soc/rcc@58024400/reset-controller */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40014800_SUPPORTS_ORDS \ - 252, /* /soc/timers@40014800/counter */ \ - 253, /* /soc/timers@40014800/pwm */ + 284, /* /soc/timers@40014800/counter */ \ + 285, /* /soc/timers@40014800/pwm */ /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40014800_EXISTS 1 @@ -34572,12 +38888,12 @@ #define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40014800_S_counter_ORD 252 -#define DT_N_S_soc_S_timers_40014800_S_counter_ORD_STR_SORTABLE 00252 +#define DT_N_S_soc_S_timers_40014800_S_counter_ORD 284 +#define DT_N_S_soc_S_timers_40014800_S_counter_ORD_STR_SORTABLE 00284 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40014800_S_counter_REQUIRES_ORDS \ - 251, /* /soc/timers@40014800 */ + 283, /* /soc/timers@40014800 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40014800_S_counter_SUPPORTS_ORDS /* nothing */ @@ -34680,12 +38996,12 @@ #define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40014800_S_pwm_ORD 253 -#define DT_N_S_soc_S_timers_40014800_S_pwm_ORD_STR_SORTABLE 00253 +#define DT_N_S_soc_S_timers_40014800_S_pwm_ORD 285 +#define DT_N_S_soc_S_timers_40014800_S_pwm_ORD_STR_SORTABLE 00285 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40014800_S_pwm_REQUIRES_ORDS \ - 251, /* /soc/timers@40014800 */ + 283, /* /soc/timers@40014800 */ /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40014800_S_pwm_SUPPORTS_ORDS /* nothing */ @@ -34771,12 +39087,14 @@ #define DT_CHOSEN_zephyr_canbus_EXISTS 1 #define DT_CHOSEN_zephyr_code_partition DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000 #define DT_CHOSEN_zephyr_code_partition_EXISTS 1 +#define DT_CHOSEN_zephyr_camera DT_N_S_soc_S_dcmi_48020000 +#define DT_CHOSEN_zephyr_camera_EXISTS 1 /* Macros for iterating over all nodes and enabled nodes */ -#define DT_FOREACH_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_flash_controller_52002000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000) fn(DT_N_S_soc_S_rcc_58024400) fn(DT_N_S_soc_S_rcc_58024400_S_reset_controller) fn(DT_N_S_soc_S_interrupt_controller_58000000) fn(DT_N_S_soc_S_pin_controller_58020000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12) fn(DT_N_S_soc_S_watchdog_58004800) fn(DT_N_S_soc_S_watchdog_50003000) fn(DT_N_S_soc_S_serial_40011000) fn(DT_N_S_soc_S_serial_40004400) fn(DT_N_S_soc_S_serial_40004800) fn(DT_N_S_soc_S_serial_40004c00) fn(DT_N_S_soc_S_serial_40005000) fn(DT_N_S_soc_S_serial_40011400) fn(DT_N_S_soc_S_serial_40007800) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx) fn(DT_N_S_soc_S_serial_40007c00) fn(DT_N_S_soc_S_serial_58000c00) fn(DT_N_S_soc_S_rtc_58004000) fn(DT_N_S_soc_S_rtc_58004000_S_backup_regs) fn(DT_N_S_soc_S_i2c_40005400) fn(DT_N_S_soc_S_i2c_40005800) fn(DT_N_S_soc_S_i2c_40005c00) fn(DT_N_S_soc_S_i2c_58001c00) fn(DT_N_S_soc_S_spi_40013000) fn(DT_N_S_soc_S_spi_40003800) fn(DT_N_S_soc_S_spi_40003c00) fn(DT_N_S_soc_S_spi_40013400) fn(DT_N_S_soc_S_spi_40015000) fn(DT_N_S_soc_S_spi_58001400) fn(DT_N_S_soc_S_i2s_40013000) fn(DT_N_S_soc_S_i2s_40003800) fn(DT_N_S_soc_S_i2s_40003c00) fn(DT_N_S_soc_S_can_4000a000) fn(DT_N_S_soc_S_can_4000a400) fn(DT_N_S_soc_S_timers_40010000) fn(DT_N_S_soc_S_timers_40010000_S_pwm) fn(DT_N_S_soc_S_timers_40000000) fn(DT_N_S_soc_S_timers_40000000_S_pwm) fn(DT_N_S_soc_S_timers_40000000_S_counter) fn(DT_N_S_soc_S_timers_40000400) fn(DT_N_S_soc_S_timers_40000400_S_pwm) fn(DT_N_S_soc_S_timers_40000400_S_counter) fn(DT_N_S_soc_S_timers_40000800) fn(DT_N_S_soc_S_timers_40000800_S_pwm) fn(DT_N_S_soc_S_timers_40000800_S_counter) fn(DT_N_S_soc_S_timers_40000c00) fn(DT_N_S_soc_S_timers_40000c00_S_pwm) fn(DT_N_S_soc_S_timers_40000c00_S_counter) fn(DT_N_S_soc_S_timers_40001000) fn(DT_N_S_soc_S_timers_40001000_S_counter) fn(DT_N_S_soc_S_timers_40001400) fn(DT_N_S_soc_S_timers_40001400_S_counter) fn(DT_N_S_soc_S_timers_40010400) fn(DT_N_S_soc_S_timers_40010400_S_pwm) fn(DT_N_S_soc_S_timers_40001800) fn(DT_N_S_soc_S_timers_40001800_S_pwm) fn(DT_N_S_soc_S_timers_40001800_S_counter) fn(DT_N_S_soc_S_timers_40001c00) fn(DT_N_S_soc_S_timers_40001c00_S_pwm) fn(DT_N_S_soc_S_timers_40001c00_S_counter) fn(DT_N_S_soc_S_timers_40002000) fn(DT_N_S_soc_S_timers_40002000_S_pwm) fn(DT_N_S_soc_S_timers_40002000_S_counter) fn(DT_N_S_soc_S_timers_40014000) fn(DT_N_S_soc_S_timers_40014000_S_pwm) fn(DT_N_S_soc_S_timers_40014000_S_counter) fn(DT_N_S_soc_S_timers_40014400) fn(DT_N_S_soc_S_timers_40014400_S_pwm) fn(DT_N_S_soc_S_timers_40014400_S_counter) fn(DT_N_S_soc_S_timers_40014800) fn(DT_N_S_soc_S_timers_40014800_S_pwm) fn(DT_N_S_soc_S_timers_40014800_S_counter) fn(DT_N_S_soc_S_timers_40002400) fn(DT_N_S_soc_S_adc_40022000) fn(DT_N_S_soc_S_adc_40022000_S_channel_4) fn(DT_N_S_soc_S_adc_40022000_S_channel_8) fn(DT_N_S_soc_S_adc_40022000_S_channel_9) fn(DT_N_S_soc_S_adc_40022000_S_channel_5) fn(DT_N_S_soc_S_adc_40022000_S_channel_13) fn(DT_N_S_soc_S_adc_40022000_S_channel_12) fn(DT_N_S_soc_S_adc_40022000_S_channel_10) fn(DT_N_S_soc_S_adc_40022000_S_channel_16) fn(DT_N_S_soc_S_adc_40022100) fn(DT_N_S_soc_S_adc_40022300) fn(DT_N_S_soc_S_adc_58026000) fn(DT_N_S_soc_S_dac_40007400) fn(DT_N_S_soc_S_dma_40020000) fn(DT_N_S_soc_S_dma_40020400) fn(DT_N_S_soc_S_bdma_58025400) fn(DT_N_S_soc_S_dmamux_40020800) fn(DT_N_S_soc_S_dmamux_58025800) fn(DT_N_S_soc_S_rng_48021800) fn(DT_N_S_soc_S_sdmmc_52007000) fn(DT_N_S_soc_S_sdmmc_48022400) fn(DT_N_S_soc_S_ethernet_40028000) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio) fn(DT_N_S_soc_S_memory_controller_52004000) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0) fn(DT_N_S_soc_S_memory_38800000) fn(DT_N_S_soc_S_quadspi_52005000) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000) fn(DT_N_S_soc_S_dcmi_48020000) fn(DT_N_S_soc_S_mailbox_58026400) fn(DT_N_S_soc_S_display_controller_50001000) fn(DT_N_S_soc_S_usb_40040000) fn(DT_N_S_soc_S_usb_40080000) fn(DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0) fn(DT_N_S_soc_S_dsihost_50000000) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) fn(DT_N_S_memory_90000000) fn(DT_N_S_clocks) fn(DT_N_S_clocks_S_clk_hse) fn(DT_N_S_clocks_S_clk_hsi) fn(DT_N_S_clocks_S_clk_hsi48) fn(DT_N_S_clocks_S_clk_csi) fn(DT_N_S_clocks_S_clk_lse) fn(DT_N_S_clocks_S_clk_lsi) fn(DT_N_S_clocks_S_pll_0) fn(DT_N_S_clocks_S_pll_1) fn(DT_N_S_clocks_S_pll_2) fn(DT_N_S_clocks_S_perck) fn(DT_N_S_dietemp) fn(DT_N_S_vbat) fn(DT_N_S_vref) fn(DT_N_S_smbus1) fn(DT_N_S_smbus2) fn(DT_N_S_smbus3) fn(DT_N_S_smbus4) fn(DT_N_S_memory_24000000) fn(DT_N_S_memory_30000000) fn(DT_N_S_memory_30020000) fn(DT_N_S_memory_30040000) fn(DT_N_S_memory_38000000) fn(DT_N_S_otghs_fs_phy) fn(DT_N_S_connector) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_gpio_keys) fn(DT_N_S_gpio_keys_S_button_0) fn(DT_N_S_sdram_c0000000) fn(DT_N_S_zephyr_user) -#define DT_FOREACH_OKAY_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_flash_controller_52002000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000) fn(DT_N_S_soc_S_rcc_58024400) fn(DT_N_S_soc_S_rcc_58024400_S_reset_controller) fn(DT_N_S_soc_S_interrupt_controller_58000000) fn(DT_N_S_soc_S_pin_controller_58020000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12) fn(DT_N_S_soc_S_serial_40011000) fn(DT_N_S_soc_S_serial_40011400) fn(DT_N_S_soc_S_serial_40007800) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx) fn(DT_N_S_soc_S_i2c_58001c00) fn(DT_N_S_soc_S_spi_40013000) fn(DT_N_S_soc_S_spi_40015000) fn(DT_N_S_soc_S_can_4000a400) fn(DT_N_S_soc_S_adc_40022000) fn(DT_N_S_soc_S_adc_40022000_S_channel_4) fn(DT_N_S_soc_S_adc_40022000_S_channel_8) fn(DT_N_S_soc_S_adc_40022000_S_channel_9) fn(DT_N_S_soc_S_adc_40022000_S_channel_5) fn(DT_N_S_soc_S_adc_40022000_S_channel_13) fn(DT_N_S_soc_S_adc_40022000_S_channel_12) fn(DT_N_S_soc_S_adc_40022000_S_channel_10) fn(DT_N_S_soc_S_adc_40022000_S_channel_16) fn(DT_N_S_soc_S_dac_40007400) fn(DT_N_S_soc_S_rng_48021800) fn(DT_N_S_soc_S_memory_controller_52004000) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0) fn(DT_N_S_soc_S_quadspi_52005000) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000) fn(DT_N_S_soc_S_mailbox_58026400) fn(DT_N_S_soc_S_usb_40080000) fn(DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) fn(DT_N_S_memory_90000000) fn(DT_N_S_clocks) fn(DT_N_S_clocks_S_clk_hse) fn(DT_N_S_clocks_S_clk_hsi48) fn(DT_N_S_clocks_S_clk_lse) fn(DT_N_S_clocks_S_pll_0) fn(DT_N_S_memory_24000000) fn(DT_N_S_memory_30000000) fn(DT_N_S_memory_30020000) fn(DT_N_S_memory_30040000) fn(DT_N_S_memory_38000000) fn(DT_N_S_otghs_fs_phy) fn(DT_N_S_connector) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_gpio_keys) fn(DT_N_S_gpio_keys_S_button_0) fn(DT_N_S_sdram_c0000000) fn(DT_N_S_zephyr_user) -#define DT_FOREACH_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_58024400, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_58024400_S_reset_controller, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_58000000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_58004800, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_50003000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004c00, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40005000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007c00, __VA_ARGS__) fn(DT_N_S_soc_S_serial_58000c00, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_58004000, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_58004000_S_backup_regs, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005400, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005800, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005c00, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003800, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003c00, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013400, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40015000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_58001400, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_40003800, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_40003c00, __VA_ARGS__) fn(DT_N_S_soc_S_can_4000a000, __VA_ARGS__) fn(DT_N_S_soc_S_can_4000a400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000c00, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000c00_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000c00_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001800, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001800_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001800_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001c00, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001c00_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001c00_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40002000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40002000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40002000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014800, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014800_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014800_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40002400, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_4, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_8, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_9, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_5, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_10, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_16, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022100, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022300, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000, __VA_ARGS__) fn(DT_N_S_soc_S_dac_40007400, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40020400, __VA_ARGS__) fn(DT_N_S_soc_S_bdma_58025400, __VA_ARGS__) fn(DT_N_S_soc_S_dmamux_40020800, __VA_ARGS__) fn(DT_N_S_soc_S_dmamux_58025800, __VA_ARGS__) fn(DT_N_S_soc_S_rng_48021800, __VA_ARGS__) fn(DT_N_S_soc_S_sdmmc_52007000, __VA_ARGS__) fn(DT_N_S_soc_S_sdmmc_48022400, __VA_ARGS__) fn(DT_N_S_soc_S_ethernet_40028000, __VA_ARGS__) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0, __VA_ARGS__) fn(DT_N_S_soc_S_memory_38800000, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000, __VA_ARGS__) fn(DT_N_S_soc_S_dcmi_48020000, __VA_ARGS__) fn(DT_N_S_soc_S_mailbox_58026400, __VA_ARGS__) fn(DT_N_S_soc_S_display_controller_50001000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40040000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40080000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0, __VA_ARGS__) fn(DT_N_S_soc_S_dsihost_50000000, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) fn(DT_N_S_memory_90000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hsi, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hsi48, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_csi, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lsi, __VA_ARGS__) fn(DT_N_S_clocks_S_pll_0, __VA_ARGS__) fn(DT_N_S_clocks_S_pll_1, __VA_ARGS__) fn(DT_N_S_clocks_S_pll_2, __VA_ARGS__) fn(DT_N_S_clocks_S_perck, __VA_ARGS__) fn(DT_N_S_dietemp, __VA_ARGS__) fn(DT_N_S_vbat, __VA_ARGS__) fn(DT_N_S_vref, __VA_ARGS__) fn(DT_N_S_smbus1, __VA_ARGS__) fn(DT_N_S_smbus2, __VA_ARGS__) fn(DT_N_S_smbus3, __VA_ARGS__) fn(DT_N_S_smbus4, __VA_ARGS__) fn(DT_N_S_memory_24000000, __VA_ARGS__) fn(DT_N_S_memory_30000000, __VA_ARGS__) fn(DT_N_S_memory_30020000, __VA_ARGS__) fn(DT_N_S_memory_30040000, __VA_ARGS__) fn(DT_N_S_memory_38000000, __VA_ARGS__) fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__) fn(DT_N_S_gpio_keys_S_button_0, __VA_ARGS__) fn(DT_N_S_sdram_c0000000, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__) -#define DT_FOREACH_OKAY_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_58024400, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_58024400_S_reset_controller, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_58000000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40015000, __VA_ARGS__) fn(DT_N_S_soc_S_can_4000a400, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_4, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_8, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_9, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_5, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_10, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_16, __VA_ARGS__) fn(DT_N_S_soc_S_dac_40007400, __VA_ARGS__) fn(DT_N_S_soc_S_rng_48021800, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000, __VA_ARGS__) fn(DT_N_S_soc_S_mailbox_58026400, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40080000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) fn(DT_N_S_memory_90000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hsi48, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lse, __VA_ARGS__) fn(DT_N_S_clocks_S_pll_0, __VA_ARGS__) fn(DT_N_S_memory_24000000, __VA_ARGS__) fn(DT_N_S_memory_30000000, __VA_ARGS__) fn(DT_N_S_memory_30020000, __VA_ARGS__) fn(DT_N_S_memory_30040000, __VA_ARGS__) fn(DT_N_S_memory_38000000, __VA_ARGS__) fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__) fn(DT_N_S_gpio_keys_S_button_0, __VA_ARGS__) fn(DT_N_S_sdram_c0000000, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__) +#define DT_FOREACH_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_flash_controller_52002000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000) fn(DT_N_S_soc_S_rcc_58024400) fn(DT_N_S_soc_S_rcc_58024400_S_reset_controller) fn(DT_N_S_soc_S_interrupt_controller_58000000) fn(DT_N_S_soc_S_pin_controller_58020000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12) fn(DT_N_S_soc_S_watchdog_58004800) fn(DT_N_S_soc_S_watchdog_50003000) fn(DT_N_S_soc_S_serial_40011000) fn(DT_N_S_soc_S_serial_40004400) fn(DT_N_S_soc_S_serial_40004800) fn(DT_N_S_soc_S_serial_40004c00) fn(DT_N_S_soc_S_serial_40005000) fn(DT_N_S_soc_S_serial_40011400) fn(DT_N_S_soc_S_serial_40007800) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx) fn(DT_N_S_soc_S_serial_40007c00) fn(DT_N_S_soc_S_serial_58000c00) fn(DT_N_S_soc_S_rtc_58004000) fn(DT_N_S_soc_S_rtc_58004000_S_backup_regs) fn(DT_N_S_soc_S_i2c_40005400) fn(DT_N_S_soc_S_i2c_40005800) fn(DT_N_S_soc_S_i2c_40005c00) fn(DT_N_S_soc_S_i2c_58001c00) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint) fn(DT_N_S_soc_S_spi_40013000) fn(DT_N_S_soc_S_spi_40003800) fn(DT_N_S_soc_S_spi_40003c00) fn(DT_N_S_soc_S_spi_40013400) fn(DT_N_S_soc_S_spi_40015000) fn(DT_N_S_soc_S_spi_58001400) fn(DT_N_S_soc_S_i2s_40013000) fn(DT_N_S_soc_S_i2s_40003800) fn(DT_N_S_soc_S_i2s_40003c00) fn(DT_N_S_soc_S_can_4000a000) fn(DT_N_S_soc_S_can_4000a400) fn(DT_N_S_soc_S_timers_40010000) fn(DT_N_S_soc_S_timers_40010000_S_pwm) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock) fn(DT_N_S_soc_S_timers_40000000) fn(DT_N_S_soc_S_timers_40000000_S_pwm) fn(DT_N_S_soc_S_timers_40000000_S_counter) fn(DT_N_S_soc_S_timers_40000400) fn(DT_N_S_soc_S_timers_40000400_S_pwm) fn(DT_N_S_soc_S_timers_40000400_S_counter) fn(DT_N_S_soc_S_timers_40000800) fn(DT_N_S_soc_S_timers_40000800_S_pwm) fn(DT_N_S_soc_S_timers_40000800_S_counter) fn(DT_N_S_soc_S_timers_40000c00) fn(DT_N_S_soc_S_timers_40000c00_S_pwm) fn(DT_N_S_soc_S_timers_40000c00_S_counter) fn(DT_N_S_soc_S_timers_40001000) fn(DT_N_S_soc_S_timers_40001000_S_counter) fn(DT_N_S_soc_S_timers_40001400) fn(DT_N_S_soc_S_timers_40001400_S_counter) fn(DT_N_S_soc_S_timers_40010400) fn(DT_N_S_soc_S_timers_40010400_S_pwm) fn(DT_N_S_soc_S_timers_40001800) fn(DT_N_S_soc_S_timers_40001800_S_pwm) fn(DT_N_S_soc_S_timers_40001800_S_counter) fn(DT_N_S_soc_S_timers_40001c00) fn(DT_N_S_soc_S_timers_40001c00_S_pwm) fn(DT_N_S_soc_S_timers_40001c00_S_counter) fn(DT_N_S_soc_S_timers_40002000) fn(DT_N_S_soc_S_timers_40002000_S_pwm) fn(DT_N_S_soc_S_timers_40002000_S_counter) fn(DT_N_S_soc_S_timers_40014000) fn(DT_N_S_soc_S_timers_40014000_S_pwm) fn(DT_N_S_soc_S_timers_40014000_S_counter) fn(DT_N_S_soc_S_timers_40014400) fn(DT_N_S_soc_S_timers_40014400_S_pwm) fn(DT_N_S_soc_S_timers_40014400_S_counter) fn(DT_N_S_soc_S_timers_40014800) fn(DT_N_S_soc_S_timers_40014800_S_pwm) fn(DT_N_S_soc_S_timers_40014800_S_counter) fn(DT_N_S_soc_S_timers_40002400) fn(DT_N_S_soc_S_adc_40022000) fn(DT_N_S_soc_S_adc_40022000_S_channel_4) fn(DT_N_S_soc_S_adc_40022000_S_channel_8) fn(DT_N_S_soc_S_adc_40022000_S_channel_9) fn(DT_N_S_soc_S_adc_40022000_S_channel_5) fn(DT_N_S_soc_S_adc_40022000_S_channel_d) fn(DT_N_S_soc_S_adc_40022000_S_channel_c) fn(DT_N_S_soc_S_adc_40022000_S_channel_a) fn(DT_N_S_soc_S_adc_40022000_S_channel_10) fn(DT_N_S_soc_S_adc_40022000_S_channel_12) fn(DT_N_S_soc_S_adc_40022000_S_channel_13) fn(DT_N_S_soc_S_adc_40022000_S_channel_0) fn(DT_N_S_soc_S_adc_40022000_S_channel_1) fn(DT_N_S_soc_S_adc_40022100) fn(DT_N_S_soc_S_adc_40022300) fn(DT_N_S_soc_S_adc_58026000) fn(DT_N_S_soc_S_adc_58026000_S_channel_0) fn(DT_N_S_soc_S_adc_58026000_S_channel_1) fn(DT_N_S_soc_S_dac_40007400) fn(DT_N_S_soc_S_dma_40020000) fn(DT_N_S_soc_S_dma_40020400) fn(DT_N_S_soc_S_bdma_58025400) fn(DT_N_S_soc_S_dmamux_40020800) fn(DT_N_S_soc_S_dmamux_58025800) fn(DT_N_S_soc_S_rng_48021800) fn(DT_N_S_soc_S_sdmmc_52007000) fn(DT_N_S_soc_S_sdmmc_48022400) fn(DT_N_S_soc_S_ethernet_40028000) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio) fn(DT_N_S_soc_S_memory_controller_52004000) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0) fn(DT_N_S_soc_S_memory_38800000) fn(DT_N_S_soc_S_quadspi_52005000) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000) fn(DT_N_S_soc_S_dcmi_48020000) fn(DT_N_S_soc_S_dcmi_48020000_S_port) fn(DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint) fn(DT_N_S_soc_S_mailbox_58026400) fn(DT_N_S_soc_S_display_controller_50001000) fn(DT_N_S_soc_S_usb_40040000) fn(DT_N_S_soc_S_usb_40080000) fn(DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0) fn(DT_N_S_soc_S_dsihost_50000000) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) fn(DT_N_S_memory_90000000) fn(DT_N_S_clocks) fn(DT_N_S_clocks_S_clk_hse) fn(DT_N_S_clocks_S_clk_hsi) fn(DT_N_S_clocks_S_clk_hsi48) fn(DT_N_S_clocks_S_clk_csi) fn(DT_N_S_clocks_S_clk_lse) fn(DT_N_S_clocks_S_clk_lsi) fn(DT_N_S_clocks_S_pll_0) fn(DT_N_S_clocks_S_pll_1) fn(DT_N_S_clocks_S_pll_2) fn(DT_N_S_clocks_S_perck) fn(DT_N_S_dietemp) fn(DT_N_S_vbat) fn(DT_N_S_vref) fn(DT_N_S_smbus1) fn(DT_N_S_smbus2) fn(DT_N_S_smbus3) fn(DT_N_S_smbus4) fn(DT_N_S_memory_24000000) fn(DT_N_S_memory_30000000) fn(DT_N_S_memory_30020000) fn(DT_N_S_memory_30040000) fn(DT_N_S_memory_38000000) fn(DT_N_S_otghs_fs_phy) fn(DT_N_S_connector) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_gpio_keys) fn(DT_N_S_gpio_keys_S_button_0) fn(DT_N_S_sdram_c0000000) fn(DT_N_S_gpio_deadbeef) fn(DT_N_S_zephyr_user) +#define DT_FOREACH_OKAY_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_flash_controller_52002000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000) fn(DT_N_S_soc_S_rcc_58024400) fn(DT_N_S_soc_S_rcc_58024400_S_reset_controller) fn(DT_N_S_soc_S_interrupt_controller_58000000) fn(DT_N_S_soc_S_pin_controller_58020000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12) fn(DT_N_S_soc_S_serial_40011000) fn(DT_N_S_soc_S_serial_40011400) fn(DT_N_S_soc_S_serial_40007800) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx) fn(DT_N_S_soc_S_i2c_58001c00) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint) fn(DT_N_S_soc_S_spi_40013000) fn(DT_N_S_soc_S_spi_40015000) fn(DT_N_S_soc_S_can_4000a400) fn(DT_N_S_soc_S_timers_40010000) fn(DT_N_S_soc_S_timers_40010000_S_pwm) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock) fn(DT_N_S_soc_S_adc_40022000) fn(DT_N_S_soc_S_adc_40022000_S_channel_4) fn(DT_N_S_soc_S_adc_40022000_S_channel_8) fn(DT_N_S_soc_S_adc_40022000_S_channel_9) fn(DT_N_S_soc_S_adc_40022000_S_channel_5) fn(DT_N_S_soc_S_adc_40022000_S_channel_d) fn(DT_N_S_soc_S_adc_40022000_S_channel_c) fn(DT_N_S_soc_S_adc_40022000_S_channel_a) fn(DT_N_S_soc_S_adc_40022000_S_channel_10) fn(DT_N_S_soc_S_adc_40022000_S_channel_12) fn(DT_N_S_soc_S_adc_40022000_S_channel_13) fn(DT_N_S_soc_S_adc_40022000_S_channel_0) fn(DT_N_S_soc_S_adc_40022000_S_channel_1) fn(DT_N_S_soc_S_adc_58026000) fn(DT_N_S_soc_S_adc_58026000_S_channel_0) fn(DT_N_S_soc_S_adc_58026000_S_channel_1) fn(DT_N_S_soc_S_dac_40007400) fn(DT_N_S_soc_S_dma_40020000) fn(DT_N_S_soc_S_dmamux_40020800) fn(DT_N_S_soc_S_rng_48021800) fn(DT_N_S_soc_S_memory_controller_52004000) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0) fn(DT_N_S_soc_S_quadspi_52005000) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000) fn(DT_N_S_soc_S_dcmi_48020000) fn(DT_N_S_soc_S_dcmi_48020000_S_port) fn(DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint) fn(DT_N_S_soc_S_mailbox_58026400) fn(DT_N_S_soc_S_usb_40080000) fn(DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) fn(DT_N_S_memory_90000000) fn(DT_N_S_clocks) fn(DT_N_S_clocks_S_clk_hse) fn(DT_N_S_clocks_S_clk_hsi48) fn(DT_N_S_clocks_S_clk_lse) fn(DT_N_S_clocks_S_pll_0) fn(DT_N_S_memory_24000000) fn(DT_N_S_memory_30000000) fn(DT_N_S_memory_30020000) fn(DT_N_S_memory_30040000) fn(DT_N_S_memory_38000000) fn(DT_N_S_otghs_fs_phy) fn(DT_N_S_connector) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_gpio_keys) fn(DT_N_S_gpio_keys_S_button_0) fn(DT_N_S_sdram_c0000000) fn(DT_N_S_gpio_deadbeef) fn(DT_N_S_zephyr_user) +#define DT_FOREACH_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_58024400, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_58024400_S_reset_controller, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_58000000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_58004800, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_50003000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004c00, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40005000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007c00, __VA_ARGS__) fn(DT_N_S_soc_S_serial_58000c00, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_58004000, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_58004000_S_backup_regs, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005400, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005800, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005c00, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003800, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003c00, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013400, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40015000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_58001400, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_40003800, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_40003c00, __VA_ARGS__) fn(DT_N_S_soc_S_can_4000a000, __VA_ARGS__) fn(DT_N_S_soc_S_can_4000a400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000c00, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000c00_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000c00_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001800, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001800_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001800_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001c00, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001c00_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001c00_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40002000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40002000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40002000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014800, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014800_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014800_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40002400, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_4, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_8, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_9, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_5, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_d, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_c, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_a, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_10, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_0, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_1, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022100, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022300, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000_S_channel_1, __VA_ARGS__) fn(DT_N_S_soc_S_dac_40007400, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40020400, __VA_ARGS__) fn(DT_N_S_soc_S_bdma_58025400, __VA_ARGS__) fn(DT_N_S_soc_S_dmamux_40020800, __VA_ARGS__) fn(DT_N_S_soc_S_dmamux_58025800, __VA_ARGS__) fn(DT_N_S_soc_S_rng_48021800, __VA_ARGS__) fn(DT_N_S_soc_S_sdmmc_52007000, __VA_ARGS__) fn(DT_N_S_soc_S_sdmmc_48022400, __VA_ARGS__) fn(DT_N_S_soc_S_ethernet_40028000, __VA_ARGS__) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0, __VA_ARGS__) fn(DT_N_S_soc_S_memory_38800000, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000, __VA_ARGS__) fn(DT_N_S_soc_S_dcmi_48020000, __VA_ARGS__) fn(DT_N_S_soc_S_dcmi_48020000_S_port, __VA_ARGS__) fn(DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint, __VA_ARGS__) fn(DT_N_S_soc_S_mailbox_58026400, __VA_ARGS__) fn(DT_N_S_soc_S_display_controller_50001000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40040000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40080000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0, __VA_ARGS__) fn(DT_N_S_soc_S_dsihost_50000000, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) fn(DT_N_S_memory_90000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hsi, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hsi48, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_csi, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lsi, __VA_ARGS__) fn(DT_N_S_clocks_S_pll_0, __VA_ARGS__) fn(DT_N_S_clocks_S_pll_1, __VA_ARGS__) fn(DT_N_S_clocks_S_pll_2, __VA_ARGS__) fn(DT_N_S_clocks_S_perck, __VA_ARGS__) fn(DT_N_S_dietemp, __VA_ARGS__) fn(DT_N_S_vbat, __VA_ARGS__) fn(DT_N_S_vref, __VA_ARGS__) fn(DT_N_S_smbus1, __VA_ARGS__) fn(DT_N_S_smbus2, __VA_ARGS__) fn(DT_N_S_smbus3, __VA_ARGS__) fn(DT_N_S_smbus4, __VA_ARGS__) fn(DT_N_S_memory_24000000, __VA_ARGS__) fn(DT_N_S_memory_30000000, __VA_ARGS__) fn(DT_N_S_memory_30020000, __VA_ARGS__) fn(DT_N_S_memory_30040000, __VA_ARGS__) fn(DT_N_S_memory_38000000, __VA_ARGS__) fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__) fn(DT_N_S_gpio_keys_S_button_0, __VA_ARGS__) fn(DT_N_S_sdram_c0000000, __VA_ARGS__) fn(DT_N_S_gpio_deadbeef, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__) +#define DT_FOREACH_OKAY_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_58024400, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_58024400_S_reset_controller, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_58000000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40015000, __VA_ARGS__) fn(DT_N_S_soc_S_can_4000a400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_4, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_8, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_9, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_5, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_d, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_c, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_a, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_10, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_0, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_1, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000_S_channel_1, __VA_ARGS__) fn(DT_N_S_soc_S_dac_40007400, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_dmamux_40020800, __VA_ARGS__) fn(DT_N_S_soc_S_rng_48021800, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000, __VA_ARGS__) fn(DT_N_S_soc_S_dcmi_48020000, __VA_ARGS__) fn(DT_N_S_soc_S_dcmi_48020000_S_port, __VA_ARGS__) fn(DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint, __VA_ARGS__) fn(DT_N_S_soc_S_mailbox_58026400, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40080000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) fn(DT_N_S_memory_90000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hsi48, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lse, __VA_ARGS__) fn(DT_N_S_clocks_S_pll_0, __VA_ARGS__) fn(DT_N_S_memory_24000000, __VA_ARGS__) fn(DT_N_S_memory_30000000, __VA_ARGS__) fn(DT_N_S_memory_30020000, __VA_ARGS__) fn(DT_N_S_memory_30040000, __VA_ARGS__) fn(DT_N_S_memory_38000000, __VA_ARGS__) fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__) fn(DT_N_S_gpio_keys_S_button_0, __VA_ARGS__) fn(DT_N_S_sdram_c0000000, __VA_ARGS__) fn(DT_N_S_gpio_deadbeef, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__) #define DT_COMPAT_fixed_partitions_LABEL_bootloader DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0 #define DT_COMPAT_fixed_partitions_LABEL_bootloader_EXISTS 1 #define DT_COMPAT_fixed_partitions_LABEL_image_0 DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000 @@ -34810,17 +39128,24 @@ #define DT_COMPAT_HAS_OKAY_zephyr_bt_hci_uart 1 #define DT_COMPAT_HAS_OKAY_infineon_cyw43xxx_bt_hci 1 #define DT_COMPAT_HAS_OKAY_st_stm32_i2c_v2 1 +#define DT_COMPAT_HAS_OKAY_ovti_ov7670 1 #define DT_COMPAT_HAS_OKAY_st_stm32h7_spi 1 #define DT_COMPAT_HAS_OKAY_st_stm32_spi_fifo 1 #define DT_COMPAT_HAS_OKAY_st_stm32_spi 1 #define DT_COMPAT_HAS_OKAY_st_stm32h7_fdcan 1 +#define DT_COMPAT_HAS_OKAY_st_stm32_timers 1 +#define DT_COMPAT_HAS_OKAY_st_stm32_pwm 1 +#define DT_COMPAT_HAS_OKAY_pwm_clock 1 #define DT_COMPAT_HAS_OKAY_st_stm32_adc 1 #define DT_COMPAT_HAS_OKAY_st_stm32_dac 1 +#define DT_COMPAT_HAS_OKAY_st_stm32_dma_v1 1 +#define DT_COMPAT_HAS_OKAY_st_stm32_dmamux 1 #define DT_COMPAT_HAS_OKAY_st_stm32_rng 1 #define DT_COMPAT_HAS_OKAY_st_stm32h7_fmc 1 #define DT_COMPAT_HAS_OKAY_st_stm32_fmc_sdram 1 #define DT_COMPAT_HAS_OKAY_st_stm32_qspi 1 #define DT_COMPAT_HAS_OKAY_st_stm32_qspi_nor 1 +#define DT_COMPAT_HAS_OKAY_st_stm32_dcmi 1 #define DT_COMPAT_HAS_OKAY_st_stm32_hsem_mailbox 1 #define DT_COMPAT_HAS_OKAY_st_mbox_stm32_hsem 1 #define DT_COMPAT_HAS_OKAY_st_stm32_otgfs 1 @@ -34837,6 +39162,7 @@ #define DT_COMPAT_HAS_OKAY_arduino_header_r3 1 #define DT_COMPAT_HAS_OKAY_gpio_leds 1 #define DT_COMPAT_HAS_OKAY_gpio_keys 1 +#define DT_COMPAT_HAS_OKAY_vnd_gpio 1 /* * Macros for status "okay" instances of each compatible @@ -34862,17 +39188,24 @@ #define DT_N_INST_zephyr_bt_hci_uart_NUM_OKAY 1 #define DT_N_INST_infineon_cyw43xxx_bt_hci_NUM_OKAY 1 #define DT_N_INST_st_stm32_i2c_v2_NUM_OKAY 1 +#define DT_N_INST_ovti_ov7670_NUM_OKAY 1 #define DT_N_INST_st_stm32h7_spi_NUM_OKAY 2 #define DT_N_INST_st_stm32_spi_fifo_NUM_OKAY 2 #define DT_N_INST_st_stm32_spi_NUM_OKAY 2 #define DT_N_INST_st_stm32h7_fdcan_NUM_OKAY 1 -#define DT_N_INST_st_stm32_adc_NUM_OKAY 1 +#define DT_N_INST_st_stm32_timers_NUM_OKAY 1 +#define DT_N_INST_st_stm32_pwm_NUM_OKAY 1 +#define DT_N_INST_pwm_clock_NUM_OKAY 1 +#define DT_N_INST_st_stm32_adc_NUM_OKAY 2 #define DT_N_INST_st_stm32_dac_NUM_OKAY 1 +#define DT_N_INST_st_stm32_dma_v1_NUM_OKAY 1 +#define DT_N_INST_st_stm32_dmamux_NUM_OKAY 1 #define DT_N_INST_st_stm32_rng_NUM_OKAY 1 #define DT_N_INST_st_stm32h7_fmc_NUM_OKAY 1 #define DT_N_INST_st_stm32_fmc_sdram_NUM_OKAY 1 #define DT_N_INST_st_stm32_qspi_NUM_OKAY 1 #define DT_N_INST_st_stm32_qspi_nor_NUM_OKAY 1 +#define DT_N_INST_st_stm32_dcmi_NUM_OKAY 1 #define DT_N_INST_st_stm32_hsem_mailbox_NUM_OKAY 1 #define DT_N_INST_st_mbox_stm32_hsem_NUM_OKAY 1 #define DT_N_INST_st_stm32_otgfs_NUM_OKAY 1 @@ -34889,6 +39222,7 @@ #define DT_N_INST_arduino_header_r3_NUM_OKAY 1 #define DT_N_INST_gpio_leds_NUM_OKAY 1 #define DT_N_INST_gpio_keys_NUM_OKAY 1 +#define DT_N_INST_vnd_gpio_NUM_OKAY 1 #define DT_FOREACH_OKAY_arduino_giga_r1(fn) fn(DT_N) #define DT_FOREACH_OKAY_VARGS_arduino_giga_r1(fn, ...) fn(DT_N, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_arduino_giga_r1(fn) fn(0) @@ -34973,6 +39307,10 @@ #define DT_FOREACH_OKAY_VARGS_st_stm32_i2c_v2(fn, ...) fn(DT_N_S_soc_S_i2c_58001c00, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_st_stm32_i2c_v2(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_st_stm32_i2c_v2(fn, ...) fn(0, __VA_ARGS__) +#define DT_FOREACH_OKAY_ovti_ov7670(fn) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21) +#define DT_FOREACH_OKAY_VARGS_ovti_ov7670(fn, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, __VA_ARGS__) +#define DT_FOREACH_OKAY_INST_ovti_ov7670(fn) fn(0) +#define DT_FOREACH_OKAY_INST_VARGS_ovti_ov7670(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_st_stm32h7_spi(fn) fn(DT_N_S_soc_S_spi_40013000) fn(DT_N_S_soc_S_spi_40015000) #define DT_FOREACH_OKAY_VARGS_st_stm32h7_spi(fn, ...) fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40015000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_st_stm32h7_spi(fn) fn(0) fn(1) @@ -34989,14 +39327,34 @@ #define DT_FOREACH_OKAY_VARGS_st_stm32h7_fdcan(fn, ...) fn(DT_N_S_soc_S_can_4000a400, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_st_stm32h7_fdcan(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_st_stm32h7_fdcan(fn, ...) fn(0, __VA_ARGS__) -#define DT_FOREACH_OKAY_st_stm32_adc(fn) fn(DT_N_S_soc_S_adc_40022000) -#define DT_FOREACH_OKAY_VARGS_st_stm32_adc(fn, ...) fn(DT_N_S_soc_S_adc_40022000, __VA_ARGS__) -#define DT_FOREACH_OKAY_INST_st_stm32_adc(fn) fn(0) -#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_adc(fn, ...) fn(0, __VA_ARGS__) +#define DT_FOREACH_OKAY_st_stm32_timers(fn) fn(DT_N_S_soc_S_timers_40010000) +#define DT_FOREACH_OKAY_VARGS_st_stm32_timers(fn, ...) fn(DT_N_S_soc_S_timers_40010000, __VA_ARGS__) +#define DT_FOREACH_OKAY_INST_st_stm32_timers(fn) fn(0) +#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_timers(fn, ...) fn(0, __VA_ARGS__) +#define DT_FOREACH_OKAY_st_stm32_pwm(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm) +#define DT_FOREACH_OKAY_VARGS_st_stm32_pwm(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, __VA_ARGS__) +#define DT_FOREACH_OKAY_INST_st_stm32_pwm(fn) fn(0) +#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_pwm(fn, ...) fn(0, __VA_ARGS__) +#define DT_FOREACH_OKAY_pwm_clock(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock) +#define DT_FOREACH_OKAY_VARGS_pwm_clock(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, __VA_ARGS__) +#define DT_FOREACH_OKAY_INST_pwm_clock(fn) fn(0) +#define DT_FOREACH_OKAY_INST_VARGS_pwm_clock(fn, ...) fn(0, __VA_ARGS__) +#define DT_FOREACH_OKAY_st_stm32_adc(fn) fn(DT_N_S_soc_S_adc_40022000) fn(DT_N_S_soc_S_adc_58026000) +#define DT_FOREACH_OKAY_VARGS_st_stm32_adc(fn, ...) fn(DT_N_S_soc_S_adc_40022000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000, __VA_ARGS__) +#define DT_FOREACH_OKAY_INST_st_stm32_adc(fn) fn(0) fn(1) +#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_adc(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) #define DT_FOREACH_OKAY_st_stm32_dac(fn) fn(DT_N_S_soc_S_dac_40007400) #define DT_FOREACH_OKAY_VARGS_st_stm32_dac(fn, ...) fn(DT_N_S_soc_S_dac_40007400, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_st_stm32_dac(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_st_stm32_dac(fn, ...) fn(0, __VA_ARGS__) +#define DT_FOREACH_OKAY_st_stm32_dma_v1(fn) fn(DT_N_S_soc_S_dma_40020000) +#define DT_FOREACH_OKAY_VARGS_st_stm32_dma_v1(fn, ...) fn(DT_N_S_soc_S_dma_40020000, __VA_ARGS__) +#define DT_FOREACH_OKAY_INST_st_stm32_dma_v1(fn) fn(0) +#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_dma_v1(fn, ...) fn(0, __VA_ARGS__) +#define DT_FOREACH_OKAY_st_stm32_dmamux(fn) fn(DT_N_S_soc_S_dmamux_40020800) +#define DT_FOREACH_OKAY_VARGS_st_stm32_dmamux(fn, ...) fn(DT_N_S_soc_S_dmamux_40020800, __VA_ARGS__) +#define DT_FOREACH_OKAY_INST_st_stm32_dmamux(fn) fn(0) +#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_dmamux(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_st_stm32_rng(fn) fn(DT_N_S_soc_S_rng_48021800) #define DT_FOREACH_OKAY_VARGS_st_stm32_rng(fn, ...) fn(DT_N_S_soc_S_rng_48021800, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_st_stm32_rng(fn) fn(0) @@ -35017,6 +39375,10 @@ #define DT_FOREACH_OKAY_VARGS_st_stm32_qspi_nor(fn, ...) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_st_stm32_qspi_nor(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_st_stm32_qspi_nor(fn, ...) fn(0, __VA_ARGS__) +#define DT_FOREACH_OKAY_st_stm32_dcmi(fn) fn(DT_N_S_soc_S_dcmi_48020000) +#define DT_FOREACH_OKAY_VARGS_st_stm32_dcmi(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000, __VA_ARGS__) +#define DT_FOREACH_OKAY_INST_st_stm32_dcmi(fn) fn(0) +#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_dcmi(fn, ...) fn(0, __VA_ARGS__) #define DT_FOREACH_OKAY_st_stm32_hsem_mailbox(fn) fn(DT_N_S_soc_S_mailbox_58026400) #define DT_FOREACH_OKAY_VARGS_st_stm32_hsem_mailbox(fn, ...) fn(DT_N_S_soc_S_mailbox_58026400, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_st_stm32_hsem_mailbox(fn) fn(0) @@ -35081,11 +39443,16 @@ #define DT_FOREACH_OKAY_VARGS_gpio_keys(fn, ...) fn(DT_N_S_gpio_keys, __VA_ARGS__) #define DT_FOREACH_OKAY_INST_gpio_keys(fn) fn(0) #define DT_FOREACH_OKAY_INST_VARGS_gpio_keys(fn, ...) fn(0, __VA_ARGS__) +#define DT_FOREACH_OKAY_vnd_gpio(fn) fn(DT_N_S_gpio_deadbeef) +#define DT_FOREACH_OKAY_VARGS_vnd_gpio(fn, ...) fn(DT_N_S_gpio_deadbeef, __VA_ARGS__) +#define DT_FOREACH_OKAY_INST_vnd_gpio(fn) fn(0) +#define DT_FOREACH_OKAY_INST_VARGS_vnd_gpio(fn, ...) fn(0, __VA_ARGS__) /* * Bus information for status "okay" nodes of each compatible */ #define DT_COMPAT_zephyr_bt_hci_uart_BUS_uart 1 #define DT_COMPAT_infineon_cyw43xxx_bt_hci_BUS_uart 1 +#define DT_COMPAT_ovti_ov7670_BUS_i2c 1 #define DT_COMPAT_st_stm32_qspi_nor_BUS_qspi 1 #define DT_COMPAT_zephyr_cdc_acm_uart_BUS_usb 1 diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/driver-validation.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/driver-validation.h index 546f3cd9..136c9d4d 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/driver-validation.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/driver-validation.h @@ -6,6 +6,8 @@ #define K_SYSCALL_DRIVER_ADC(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, adc, ADC) +#define K_SYSCALL_DRIVER_DMA(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, dma, DMA) + #define K_SYSCALL_DRIVER_FLASH(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, flash, FLASH) #define K_SYSCALL_DRIVER_GPIO(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, gpio, GPIO) @@ -50,8 +52,6 @@ #define K_SYSCALL_DRIVER_DISPLAY(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, display, DISPLAY) -#define K_SYSCALL_DRIVER_DMA(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, dma, DMA) - #define K_SYSCALL_DRIVER_EDAC(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, edac, EDAC) #define K_SYSCALL_DRIVER_EEPROM(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, eeprom, EEPROM) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/kobj-types-enum.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/kobj-types-enum.h index a3fdfbad..bc465b92 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/kobj-types-enum.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/kobj-types-enum.h @@ -41,6 +41,7 @@ K_OBJ_SENSOR_DECODER_API, #endif /* Driver subsystems */ K_OBJ_DRIVER_ADC, +K_OBJ_DRIVER_DMA, K_OBJ_DRIVER_FLASH, K_OBJ_DRIVER_GPIO, K_OBJ_DRIVER_I2C, @@ -63,7 +64,6 @@ K_OBJ_DRIVER_COUNTER, K_OBJ_DRIVER_DAC, K_OBJ_DRIVER_DAI, K_OBJ_DRIVER_DISPLAY, -K_OBJ_DRIVER_DMA, K_OBJ_DRIVER_EDAC, K_OBJ_DRIVER_EEPROM, K_OBJ_DRIVER_EMUL_BBRAM, diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/otype-to-str.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/otype-to-str.h index d9641e8e..7d7fbdfe 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/otype-to-str.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/otype-to-str.h @@ -41,6 +41,7 @@ case K_OBJ_SENSOR_DECODER_API: ret = "sensor_decoder_api"; break; #endif /* Driver subsystems */ case K_OBJ_DRIVER_ADC: ret = "adc driver"; break; +case K_OBJ_DRIVER_DMA: ret = "dma driver"; break; case K_OBJ_DRIVER_FLASH: ret = "flash driver"; break; case K_OBJ_DRIVER_GPIO: ret = "gpio driver"; break; case K_OBJ_DRIVER_I2C: ret = "i2c driver"; break; @@ -63,7 +64,6 @@ case K_OBJ_DRIVER_COUNTER: ret = "counter driver"; break; case K_OBJ_DRIVER_DAC: ret = "dac driver"; break; case K_OBJ_DRIVER_DAI: ret = "dai driver"; break; case K_OBJ_DRIVER_DISPLAY: ret = "display driver"; break; -case K_OBJ_DRIVER_DMA: ret = "dma driver"; break; case K_OBJ_DRIVER_EDAC: ret = "edac driver"; break; case K_OBJ_DRIVER_EEPROM: ret = "eeprom driver"; break; case K_OBJ_DRIVER_EMUL_BBRAM: ret = "emul_bbram driver"; break; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscall_list.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscall_list.h index bd8cf6f0..74704a43 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscall_list.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscall_list.h @@ -10,295 +10,295 @@ #define K_SYSCALL_DEVICE_GET_BY_DT_NODELABEL 4 #define K_SYSCALL_DEVICE_INIT 5 #define K_SYSCALL_DEVICE_IS_READY 6 -#define K_SYSCALL_FLASH_ERASE 7 -#define K_SYSCALL_FLASH_EX_OP 8 -#define K_SYSCALL_FLASH_FILL 9 -#define K_SYSCALL_FLASH_FLATTEN 10 -#define K_SYSCALL_FLASH_GET_PAGE_COUNT 11 -#define K_SYSCALL_FLASH_GET_PAGE_INFO_BY_IDX 12 -#define K_SYSCALL_FLASH_GET_PAGE_INFO_BY_OFFS 13 -#define K_SYSCALL_FLASH_GET_PARAMETERS 14 -#define K_SYSCALL_FLASH_GET_WRITE_BLOCK_SIZE 15 -#define K_SYSCALL_FLASH_READ 16 -#define K_SYSCALL_FLASH_READ_JEDEC_ID 17 -#define K_SYSCALL_FLASH_SFDP_READ 18 -#define K_SYSCALL_FLASH_WRITE 19 -#define K_SYSCALL_GPIO_GET_PENDING_INT 20 -#define K_SYSCALL_GPIO_PIN_CONFIGURE 21 -#define K_SYSCALL_GPIO_PIN_GET_CONFIG 22 -#define K_SYSCALL_GPIO_PIN_INTERRUPT_CONFIGURE 23 -#define K_SYSCALL_GPIO_PORT_CLEAR_BITS_RAW 24 -#define K_SYSCALL_GPIO_PORT_GET_DIRECTION 25 -#define K_SYSCALL_GPIO_PORT_GET_RAW 26 -#define K_SYSCALL_GPIO_PORT_SET_BITS_RAW 27 -#define K_SYSCALL_GPIO_PORT_SET_MASKED_RAW 28 -#define K_SYSCALL_GPIO_PORT_TOGGLE_BITS 29 -#define K_SYSCALL_HWINFO_CLEAR_RESET_CAUSE 30 -#define K_SYSCALL_HWINFO_GET_DEVICE_EUI64 31 -#define K_SYSCALL_HWINFO_GET_DEVICE_ID 32 -#define K_SYSCALL_HWINFO_GET_RESET_CAUSE 33 -#define K_SYSCALL_HWINFO_GET_SUPPORTED_RESET_CAUSE 34 -#define K_SYSCALL_I2C_CONFIGURE 35 -#define K_SYSCALL_I2C_GET_CONFIG 36 -#define K_SYSCALL_I2C_RECOVER_BUS 37 -#define K_SYSCALL_I2C_TARGET_DRIVER_REGISTER 38 -#define K_SYSCALL_I2C_TARGET_DRIVER_UNREGISTER 39 -#define K_SYSCALL_I2C_TRANSFER 40 -#define K_SYSCALL_K_BUSY_WAIT 41 -#define K_SYSCALL_K_CONDVAR_BROADCAST 42 -#define K_SYSCALL_K_CONDVAR_INIT 43 -#define K_SYSCALL_K_CONDVAR_SIGNAL 44 -#define K_SYSCALL_K_CONDVAR_WAIT 45 -#define K_SYSCALL_K_EVENT_CLEAR 46 -#define K_SYSCALL_K_EVENT_INIT 47 -#define K_SYSCALL_K_EVENT_POST 48 -#define K_SYSCALL_K_EVENT_SET 49 -#define K_SYSCALL_K_EVENT_SET_MASKED 50 -#define K_SYSCALL_K_EVENT_WAIT 51 -#define K_SYSCALL_K_EVENT_WAIT_ALL 52 -#define K_SYSCALL_K_FLOAT_DISABLE 53 -#define K_SYSCALL_K_FLOAT_ENABLE 54 -#define K_SYSCALL_K_FUTEX_WAIT 55 -#define K_SYSCALL_K_FUTEX_WAKE 56 -#define K_SYSCALL_K_IS_PREEMPT_THREAD 57 -#define K_SYSCALL_K_MSGQ_ALLOC_INIT 58 -#define K_SYSCALL_K_MSGQ_GET 59 -#define K_SYSCALL_K_MSGQ_GET_ATTRS 60 -#define K_SYSCALL_K_MSGQ_NUM_FREE_GET 61 -#define K_SYSCALL_K_MSGQ_NUM_USED_GET 62 -#define K_SYSCALL_K_MSGQ_PEEK 63 -#define K_SYSCALL_K_MSGQ_PEEK_AT 64 -#define K_SYSCALL_K_MSGQ_PURGE 65 -#define K_SYSCALL_K_MSGQ_PUT 66 -#define K_SYSCALL_K_MUTEX_INIT 67 -#define K_SYSCALL_K_MUTEX_LOCK 68 -#define K_SYSCALL_K_MUTEX_UNLOCK 69 -#define K_SYSCALL_K_OBJECT_ACCESS_GRANT 70 -#define K_SYSCALL_K_OBJECT_ALLOC 71 -#define K_SYSCALL_K_OBJECT_ALLOC_SIZE 72 -#define K_SYSCALL_K_OBJECT_RELEASE 73 -#define K_SYSCALL_K_PIPE_ALLOC_INIT 74 -#define K_SYSCALL_K_PIPE_BUFFER_FLUSH 75 -#define K_SYSCALL_K_PIPE_FLUSH 76 -#define K_SYSCALL_K_PIPE_GET 77 -#define K_SYSCALL_K_PIPE_PUT 78 -#define K_SYSCALL_K_PIPE_READ_AVAIL 79 -#define K_SYSCALL_K_PIPE_WRITE_AVAIL 80 -#define K_SYSCALL_K_POLL 81 -#define K_SYSCALL_K_POLL_SIGNAL_CHECK 82 -#define K_SYSCALL_K_POLL_SIGNAL_INIT 83 -#define K_SYSCALL_K_POLL_SIGNAL_RAISE 84 -#define K_SYSCALL_K_POLL_SIGNAL_RESET 85 -#define K_SYSCALL_K_QUEUE_ALLOC_APPEND 86 -#define K_SYSCALL_K_QUEUE_ALLOC_PREPEND 87 -#define K_SYSCALL_K_QUEUE_CANCEL_WAIT 88 -#define K_SYSCALL_K_QUEUE_GET 89 -#define K_SYSCALL_K_QUEUE_INIT 90 -#define K_SYSCALL_K_QUEUE_IS_EMPTY 91 -#define K_SYSCALL_K_QUEUE_PEEK_HEAD 92 -#define K_SYSCALL_K_QUEUE_PEEK_TAIL 93 -#define K_SYSCALL_K_SCHED_CURRENT_THREAD_QUERY 94 -#define K_SYSCALL_K_SEM_COUNT_GET 95 -#define K_SYSCALL_K_SEM_GIVE 96 -#define K_SYSCALL_K_SEM_INIT 97 -#define K_SYSCALL_K_SEM_RESET 98 -#define K_SYSCALL_K_SEM_TAKE 99 -#define K_SYSCALL_K_SLEEP 100 -#define K_SYSCALL_K_STACK_ALLOC_INIT 101 -#define K_SYSCALL_K_STACK_POP 102 -#define K_SYSCALL_K_STACK_PUSH 103 -#define K_SYSCALL_K_STR_OUT 104 -#define K_SYSCALL_K_THREAD_ABORT 105 -#define K_SYSCALL_K_THREAD_CREATE 106 -#define K_SYSCALL_K_THREAD_CUSTOM_DATA_GET 107 -#define K_SYSCALL_K_THREAD_CUSTOM_DATA_SET 108 -#define K_SYSCALL_K_THREAD_DEADLINE_SET 109 -#define K_SYSCALL_K_THREAD_JOIN 110 -#define K_SYSCALL_K_THREAD_NAME_COPY 111 -#define K_SYSCALL_K_THREAD_NAME_SET 112 -#define K_SYSCALL_K_THREAD_PRIORITY_GET 113 -#define K_SYSCALL_K_THREAD_PRIORITY_SET 114 -#define K_SYSCALL_K_THREAD_RESUME 115 -#define K_SYSCALL_K_THREAD_STACK_ALLOC 116 -#define K_SYSCALL_K_THREAD_STACK_FREE 117 -#define K_SYSCALL_K_THREAD_STACK_SPACE_GET 118 -#define K_SYSCALL_K_THREAD_START 119 -#define K_SYSCALL_K_THREAD_SUSPEND 120 -#define K_SYSCALL_K_THREAD_TIMEOUT_EXPIRES_TICKS 121 -#define K_SYSCALL_K_THREAD_TIMEOUT_REMAINING_TICKS 122 -#define K_SYSCALL_K_TIMER_EXPIRES_TICKS 123 -#define K_SYSCALL_K_TIMER_REMAINING_TICKS 124 -#define K_SYSCALL_K_TIMER_START 125 -#define K_SYSCALL_K_TIMER_STATUS_GET 126 -#define K_SYSCALL_K_TIMER_STATUS_SYNC 127 -#define K_SYSCALL_K_TIMER_STOP 128 -#define K_SYSCALL_K_TIMER_USER_DATA_GET 129 -#define K_SYSCALL_K_TIMER_USER_DATA_SET 130 -#define K_SYSCALL_K_UPTIME_TICKS 131 -#define K_SYSCALL_K_USLEEP 132 -#define K_SYSCALL_K_WAKEUP 133 -#define K_SYSCALL_K_YIELD 134 -#define K_SYSCALL_LLEXT_GET_FN_TABLE 135 -#define K_SYSCALL_LOG_BUFFERED_CNT 136 -#define K_SYSCALL_LOG_FILTER_SET 137 -#define K_SYSCALL_LOG_FRONTEND_FILTER_SET 138 -#define K_SYSCALL_LOG_PANIC 139 -#define K_SYSCALL_LOG_PROCESS 140 -#define K_SYSCALL_PWM_CAPTURE_CYCLES 141 -#define K_SYSCALL_PWM_DISABLE_CAPTURE 142 -#define K_SYSCALL_PWM_ENABLE_CAPTURE 143 -#define K_SYSCALL_PWM_GET_CYCLES_PER_SEC 144 -#define K_SYSCALL_PWM_SET_CYCLES 145 -#define K_SYSCALL_RESET_LINE_ASSERT 146 -#define K_SYSCALL_RESET_LINE_DEASSERT 147 -#define K_SYSCALL_RESET_LINE_TOGGLE 148 -#define K_SYSCALL_RESET_STATUS 149 -#define K_SYSCALL_SPI_RELEASE 150 -#define K_SYSCALL_SPI_TRANSCEIVE 151 -#define K_SYSCALL_SYS_CACHE_DATA_FLUSH_AND_INVD_RANGE 152 -#define K_SYSCALL_SYS_CACHE_DATA_FLUSH_RANGE 153 -#define K_SYSCALL_SYS_CACHE_DATA_INVD_RANGE 154 -#define K_SYSCALL_SYS_CLOCK_HW_CYCLES_PER_SEC_RUNTIME_GET 155 -#define K_SYSCALL_UART_CONFIGURE 156 -#define K_SYSCALL_UART_CONFIG_GET 157 -#define K_SYSCALL_UART_DRV_CMD 158 -#define K_SYSCALL_UART_ERR_CHECK 159 -#define K_SYSCALL_UART_IRQ_ERR_DISABLE 160 -#define K_SYSCALL_UART_IRQ_ERR_ENABLE 161 -#define K_SYSCALL_UART_IRQ_IS_PENDING 162 -#define K_SYSCALL_UART_IRQ_RX_DISABLE 163 -#define K_SYSCALL_UART_IRQ_RX_ENABLE 164 -#define K_SYSCALL_UART_IRQ_TX_DISABLE 165 -#define K_SYSCALL_UART_IRQ_TX_ENABLE 166 -#define K_SYSCALL_UART_IRQ_UPDATE 167 -#define K_SYSCALL_UART_LINE_CTRL_GET 168 -#define K_SYSCALL_UART_LINE_CTRL_SET 169 -#define K_SYSCALL_UART_POLL_IN 170 -#define K_SYSCALL_UART_POLL_IN_U16 171 -#define K_SYSCALL_UART_POLL_OUT 172 -#define K_SYSCALL_UART_POLL_OUT_U16 173 -#define K_SYSCALL_UART_RX_DISABLE 174 -#define K_SYSCALL_UART_RX_ENABLE 175 -#define K_SYSCALL_UART_RX_ENABLE_U16 176 -#define K_SYSCALL_UART_TX 177 -#define K_SYSCALL_UART_TX_ABORT 178 -#define K_SYSCALL_UART_TX_U16 179 -#define K_SYSCALL_ZEPHYR_FPUTC 180 -#define K_SYSCALL_ZEPHYR_FWRITE 181 -#define K_SYSCALL_ZEPHYR_READ_STDIN 182 -#define K_SYSCALL_ZEPHYR_WRITE_STDOUT 183 -#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_0 184 -#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_1 185 -#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_2 186 -#define K_SYSCALL_Z_LOG_MSG_STATIC_CREATE 187 -#define K_SYSCALL_Z_SYS_MUTEX_KERNEL_LOCK 188 -#define K_SYSCALL_Z_SYS_MUTEX_KERNEL_UNLOCK 189 -#define K_SYSCALL_BAD 190 -#define K_SYSCALL_LIMIT 191 +#define K_SYSCALL_DMA_CHAN_FILTER 7 +#define K_SYSCALL_DMA_RELEASE_CHANNEL 8 +#define K_SYSCALL_DMA_REQUEST_CHANNEL 9 +#define K_SYSCALL_DMA_RESUME 10 +#define K_SYSCALL_DMA_START 11 +#define K_SYSCALL_DMA_STOP 12 +#define K_SYSCALL_DMA_SUSPEND 13 +#define K_SYSCALL_FLASH_ERASE 14 +#define K_SYSCALL_FLASH_EX_OP 15 +#define K_SYSCALL_FLASH_FILL 16 +#define K_SYSCALL_FLASH_FLATTEN 17 +#define K_SYSCALL_FLASH_GET_PAGE_COUNT 18 +#define K_SYSCALL_FLASH_GET_PAGE_INFO_BY_IDX 19 +#define K_SYSCALL_FLASH_GET_PAGE_INFO_BY_OFFS 20 +#define K_SYSCALL_FLASH_GET_PARAMETERS 21 +#define K_SYSCALL_FLASH_GET_WRITE_BLOCK_SIZE 22 +#define K_SYSCALL_FLASH_READ 23 +#define K_SYSCALL_FLASH_READ_JEDEC_ID 24 +#define K_SYSCALL_FLASH_SFDP_READ 25 +#define K_SYSCALL_FLASH_WRITE 26 +#define K_SYSCALL_GPIO_GET_PENDING_INT 27 +#define K_SYSCALL_GPIO_PIN_CONFIGURE 28 +#define K_SYSCALL_GPIO_PIN_GET_CONFIG 29 +#define K_SYSCALL_GPIO_PIN_INTERRUPT_CONFIGURE 30 +#define K_SYSCALL_GPIO_PORT_CLEAR_BITS_RAW 31 +#define K_SYSCALL_GPIO_PORT_GET_DIRECTION 32 +#define K_SYSCALL_GPIO_PORT_GET_RAW 33 +#define K_SYSCALL_GPIO_PORT_SET_BITS_RAW 34 +#define K_SYSCALL_GPIO_PORT_SET_MASKED_RAW 35 +#define K_SYSCALL_GPIO_PORT_TOGGLE_BITS 36 +#define K_SYSCALL_HWINFO_CLEAR_RESET_CAUSE 37 +#define K_SYSCALL_HWINFO_GET_DEVICE_EUI64 38 +#define K_SYSCALL_HWINFO_GET_DEVICE_ID 39 +#define K_SYSCALL_HWINFO_GET_RESET_CAUSE 40 +#define K_SYSCALL_HWINFO_GET_SUPPORTED_RESET_CAUSE 41 +#define K_SYSCALL_I2C_CONFIGURE 42 +#define K_SYSCALL_I2C_GET_CONFIG 43 +#define K_SYSCALL_I2C_RECOVER_BUS 44 +#define K_SYSCALL_I2C_TARGET_DRIVER_REGISTER 45 +#define K_SYSCALL_I2C_TARGET_DRIVER_UNREGISTER 46 +#define K_SYSCALL_I2C_TRANSFER 47 +#define K_SYSCALL_K_BUSY_WAIT 48 +#define K_SYSCALL_K_CONDVAR_BROADCAST 49 +#define K_SYSCALL_K_CONDVAR_INIT 50 +#define K_SYSCALL_K_CONDVAR_SIGNAL 51 +#define K_SYSCALL_K_CONDVAR_WAIT 52 +#define K_SYSCALL_K_EVENT_CLEAR 53 +#define K_SYSCALL_K_EVENT_INIT 54 +#define K_SYSCALL_K_EVENT_POST 55 +#define K_SYSCALL_K_EVENT_SET 56 +#define K_SYSCALL_K_EVENT_SET_MASKED 57 +#define K_SYSCALL_K_EVENT_WAIT 58 +#define K_SYSCALL_K_EVENT_WAIT_ALL 59 +#define K_SYSCALL_K_FLOAT_DISABLE 60 +#define K_SYSCALL_K_FLOAT_ENABLE 61 +#define K_SYSCALL_K_FUTEX_WAIT 62 +#define K_SYSCALL_K_FUTEX_WAKE 63 +#define K_SYSCALL_K_IS_PREEMPT_THREAD 64 +#define K_SYSCALL_K_MSGQ_ALLOC_INIT 65 +#define K_SYSCALL_K_MSGQ_GET 66 +#define K_SYSCALL_K_MSGQ_GET_ATTRS 67 +#define K_SYSCALL_K_MSGQ_NUM_FREE_GET 68 +#define K_SYSCALL_K_MSGQ_NUM_USED_GET 69 +#define K_SYSCALL_K_MSGQ_PEEK 70 +#define K_SYSCALL_K_MSGQ_PEEK_AT 71 +#define K_SYSCALL_K_MSGQ_PURGE 72 +#define K_SYSCALL_K_MSGQ_PUT 73 +#define K_SYSCALL_K_MUTEX_INIT 74 +#define K_SYSCALL_K_MUTEX_LOCK 75 +#define K_SYSCALL_K_MUTEX_UNLOCK 76 +#define K_SYSCALL_K_OBJECT_ACCESS_GRANT 77 +#define K_SYSCALL_K_OBJECT_ALLOC 78 +#define K_SYSCALL_K_OBJECT_ALLOC_SIZE 79 +#define K_SYSCALL_K_OBJECT_RELEASE 80 +#define K_SYSCALL_K_PIPE_ALLOC_INIT 81 +#define K_SYSCALL_K_PIPE_BUFFER_FLUSH 82 +#define K_SYSCALL_K_PIPE_FLUSH 83 +#define K_SYSCALL_K_PIPE_GET 84 +#define K_SYSCALL_K_PIPE_PUT 85 +#define K_SYSCALL_K_PIPE_READ_AVAIL 86 +#define K_SYSCALL_K_PIPE_WRITE_AVAIL 87 +#define K_SYSCALL_K_POLL 88 +#define K_SYSCALL_K_POLL_SIGNAL_CHECK 89 +#define K_SYSCALL_K_POLL_SIGNAL_INIT 90 +#define K_SYSCALL_K_POLL_SIGNAL_RAISE 91 +#define K_SYSCALL_K_POLL_SIGNAL_RESET 92 +#define K_SYSCALL_K_QUEUE_ALLOC_APPEND 93 +#define K_SYSCALL_K_QUEUE_ALLOC_PREPEND 94 +#define K_SYSCALL_K_QUEUE_CANCEL_WAIT 95 +#define K_SYSCALL_K_QUEUE_GET 96 +#define K_SYSCALL_K_QUEUE_INIT 97 +#define K_SYSCALL_K_QUEUE_IS_EMPTY 98 +#define K_SYSCALL_K_QUEUE_PEEK_HEAD 99 +#define K_SYSCALL_K_QUEUE_PEEK_TAIL 100 +#define K_SYSCALL_K_SCHED_CURRENT_THREAD_QUERY 101 +#define K_SYSCALL_K_SEM_COUNT_GET 102 +#define K_SYSCALL_K_SEM_GIVE 103 +#define K_SYSCALL_K_SEM_INIT 104 +#define K_SYSCALL_K_SEM_RESET 105 +#define K_SYSCALL_K_SEM_TAKE 106 +#define K_SYSCALL_K_SLEEP 107 +#define K_SYSCALL_K_STACK_ALLOC_INIT 108 +#define K_SYSCALL_K_STACK_POP 109 +#define K_SYSCALL_K_STACK_PUSH 110 +#define K_SYSCALL_K_STR_OUT 111 +#define K_SYSCALL_K_THREAD_ABORT 112 +#define K_SYSCALL_K_THREAD_CREATE 113 +#define K_SYSCALL_K_THREAD_CUSTOM_DATA_GET 114 +#define K_SYSCALL_K_THREAD_CUSTOM_DATA_SET 115 +#define K_SYSCALL_K_THREAD_DEADLINE_SET 116 +#define K_SYSCALL_K_THREAD_JOIN 117 +#define K_SYSCALL_K_THREAD_NAME_COPY 118 +#define K_SYSCALL_K_THREAD_NAME_SET 119 +#define K_SYSCALL_K_THREAD_PRIORITY_GET 120 +#define K_SYSCALL_K_THREAD_PRIORITY_SET 121 +#define K_SYSCALL_K_THREAD_RESUME 122 +#define K_SYSCALL_K_THREAD_STACK_ALLOC 123 +#define K_SYSCALL_K_THREAD_STACK_FREE 124 +#define K_SYSCALL_K_THREAD_STACK_SPACE_GET 125 +#define K_SYSCALL_K_THREAD_START 126 +#define K_SYSCALL_K_THREAD_SUSPEND 127 +#define K_SYSCALL_K_THREAD_TIMEOUT_EXPIRES_TICKS 128 +#define K_SYSCALL_K_THREAD_TIMEOUT_REMAINING_TICKS 129 +#define K_SYSCALL_K_TIMER_EXPIRES_TICKS 130 +#define K_SYSCALL_K_TIMER_REMAINING_TICKS 131 +#define K_SYSCALL_K_TIMER_START 132 +#define K_SYSCALL_K_TIMER_STATUS_GET 133 +#define K_SYSCALL_K_TIMER_STATUS_SYNC 134 +#define K_SYSCALL_K_TIMER_STOP 135 +#define K_SYSCALL_K_TIMER_USER_DATA_GET 136 +#define K_SYSCALL_K_TIMER_USER_DATA_SET 137 +#define K_SYSCALL_K_UPTIME_TICKS 138 +#define K_SYSCALL_K_USLEEP 139 +#define K_SYSCALL_K_WAKEUP 140 +#define K_SYSCALL_K_YIELD 141 +#define K_SYSCALL_LLEXT_GET_FN_TABLE 142 +#define K_SYSCALL_LOG_BUFFERED_CNT 143 +#define K_SYSCALL_LOG_FILTER_SET 144 +#define K_SYSCALL_LOG_FRONTEND_FILTER_SET 145 +#define K_SYSCALL_LOG_PANIC 146 +#define K_SYSCALL_LOG_PROCESS 147 +#define K_SYSCALL_PWM_CAPTURE_CYCLES 148 +#define K_SYSCALL_PWM_DISABLE_CAPTURE 149 +#define K_SYSCALL_PWM_ENABLE_CAPTURE 150 +#define K_SYSCALL_PWM_GET_CYCLES_PER_SEC 151 +#define K_SYSCALL_PWM_SET_CYCLES 152 +#define K_SYSCALL_RESET_LINE_ASSERT 153 +#define K_SYSCALL_RESET_LINE_DEASSERT 154 +#define K_SYSCALL_RESET_LINE_TOGGLE 155 +#define K_SYSCALL_RESET_STATUS 156 +#define K_SYSCALL_SPI_RELEASE 157 +#define K_SYSCALL_SPI_TRANSCEIVE 158 +#define K_SYSCALL_SYS_CACHE_DATA_FLUSH_AND_INVD_RANGE 159 +#define K_SYSCALL_SYS_CACHE_DATA_FLUSH_RANGE 160 +#define K_SYSCALL_SYS_CACHE_DATA_INVD_RANGE 161 +#define K_SYSCALL_SYS_CLOCK_HW_CYCLES_PER_SEC_RUNTIME_GET 162 +#define K_SYSCALL_UART_CONFIGURE 163 +#define K_SYSCALL_UART_CONFIG_GET 164 +#define K_SYSCALL_UART_DRV_CMD 165 +#define K_SYSCALL_UART_ERR_CHECK 166 +#define K_SYSCALL_UART_IRQ_ERR_DISABLE 167 +#define K_SYSCALL_UART_IRQ_ERR_ENABLE 168 +#define K_SYSCALL_UART_IRQ_IS_PENDING 169 +#define K_SYSCALL_UART_IRQ_RX_DISABLE 170 +#define K_SYSCALL_UART_IRQ_RX_ENABLE 171 +#define K_SYSCALL_UART_IRQ_TX_DISABLE 172 +#define K_SYSCALL_UART_IRQ_TX_ENABLE 173 +#define K_SYSCALL_UART_IRQ_UPDATE 174 +#define K_SYSCALL_UART_LINE_CTRL_GET 175 +#define K_SYSCALL_UART_LINE_CTRL_SET 176 +#define K_SYSCALL_UART_POLL_IN 177 +#define K_SYSCALL_UART_POLL_IN_U16 178 +#define K_SYSCALL_UART_POLL_OUT 179 +#define K_SYSCALL_UART_POLL_OUT_U16 180 +#define K_SYSCALL_UART_RX_DISABLE 181 +#define K_SYSCALL_UART_RX_ENABLE 182 +#define K_SYSCALL_UART_RX_ENABLE_U16 183 +#define K_SYSCALL_UART_TX 184 +#define K_SYSCALL_UART_TX_ABORT 185 +#define K_SYSCALL_UART_TX_U16 186 +#define K_SYSCALL_ZEPHYR_FPUTC 187 +#define K_SYSCALL_ZEPHYR_FWRITE 188 +#define K_SYSCALL_ZEPHYR_READ_STDIN 189 +#define K_SYSCALL_ZEPHYR_WRITE_STDOUT 190 +#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_0 191 +#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_1 192 +#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_2 193 +#define K_SYSCALL_Z_LOG_MSG_STATIC_CREATE 194 +#define K_SYSCALL_Z_SYS_MUTEX_KERNEL_LOCK 195 +#define K_SYSCALL_Z_SYS_MUTEX_KERNEL_UNLOCK 196 +#define K_SYSCALL_BAD 197 +#define K_SYSCALL_LIMIT 198 /* Following syscalls are not used in image */ -#define K_SYSCALL_ATOMIC_ADD 192 -#define K_SYSCALL_ATOMIC_AND 193 -#define K_SYSCALL_ATOMIC_CAS 194 -#define K_SYSCALL_ATOMIC_NAND 195 -#define K_SYSCALL_ATOMIC_OR 196 -#define K_SYSCALL_ATOMIC_PTR_CAS 197 -#define K_SYSCALL_ATOMIC_PTR_SET 198 -#define K_SYSCALL_ATOMIC_SET 199 -#define K_SYSCALL_ATOMIC_SUB 200 -#define K_SYSCALL_ATOMIC_XOR 201 -#define K_SYSCALL_AUXDISPLAY_BACKLIGHT_GET 202 -#define K_SYSCALL_AUXDISPLAY_BACKLIGHT_SET 203 -#define K_SYSCALL_AUXDISPLAY_BRIGHTNESS_GET 204 -#define K_SYSCALL_AUXDISPLAY_BRIGHTNESS_SET 205 -#define K_SYSCALL_AUXDISPLAY_CAPABILITIES_GET 206 -#define K_SYSCALL_AUXDISPLAY_CLEAR 207 -#define K_SYSCALL_AUXDISPLAY_CURSOR_POSITION_GET 208 -#define K_SYSCALL_AUXDISPLAY_CURSOR_POSITION_SET 209 -#define K_SYSCALL_AUXDISPLAY_CURSOR_SET_ENABLED 210 -#define K_SYSCALL_AUXDISPLAY_CURSOR_SHIFT_SET 211 -#define K_SYSCALL_AUXDISPLAY_CUSTOM_CHARACTER_SET 212 -#define K_SYSCALL_AUXDISPLAY_CUSTOM_COMMAND 213 -#define K_SYSCALL_AUXDISPLAY_DISPLAY_OFF 214 -#define K_SYSCALL_AUXDISPLAY_DISPLAY_ON 215 -#define K_SYSCALL_AUXDISPLAY_DISPLAY_POSITION_GET 216 -#define K_SYSCALL_AUXDISPLAY_DISPLAY_POSITION_SET 217 -#define K_SYSCALL_AUXDISPLAY_IS_BUSY 218 -#define K_SYSCALL_AUXDISPLAY_POSITION_BLINKING_SET_ENABLED 219 -#define K_SYSCALL_AUXDISPLAY_WRITE 220 -#define K_SYSCALL_BBRAM_CHECK_INVALID 221 -#define K_SYSCALL_BBRAM_CHECK_POWER 222 -#define K_SYSCALL_BBRAM_CHECK_STANDBY_POWER 223 -#define K_SYSCALL_BBRAM_GET_SIZE 224 -#define K_SYSCALL_BBRAM_READ 225 -#define K_SYSCALL_BBRAM_WRITE 226 -#define K_SYSCALL_BC12_SET_RESULT_CB 227 -#define K_SYSCALL_BC12_SET_ROLE 228 -#define K_SYSCALL_CAN_ADD_RX_FILTER_MSGQ 229 -#define K_SYSCALL_CAN_CALC_TIMING 230 -#define K_SYSCALL_CAN_CALC_TIMING_DATA 231 -#define K_SYSCALL_CAN_GET_BITRATE_MAX 232 -#define K_SYSCALL_CAN_GET_BITRATE_MIN 233 -#define K_SYSCALL_CAN_GET_CAPABILITIES 234 -#define K_SYSCALL_CAN_GET_CORE_CLOCK 235 -#define K_SYSCALL_CAN_GET_MAX_FILTERS 236 -#define K_SYSCALL_CAN_GET_MODE 237 -#define K_SYSCALL_CAN_GET_STATE 238 -#define K_SYSCALL_CAN_GET_TIMING_DATA_MAX 239 -#define K_SYSCALL_CAN_GET_TIMING_DATA_MIN 240 -#define K_SYSCALL_CAN_GET_TIMING_MAX 241 -#define K_SYSCALL_CAN_GET_TIMING_MIN 242 -#define K_SYSCALL_CAN_GET_TRANSCEIVER 243 -#define K_SYSCALL_CAN_RECOVER 244 -#define K_SYSCALL_CAN_REMOVE_RX_FILTER 245 -#define K_SYSCALL_CAN_SEND 246 -#define K_SYSCALL_CAN_SET_BITRATE 247 -#define K_SYSCALL_CAN_SET_BITRATE_DATA 248 -#define K_SYSCALL_CAN_SET_MODE 249 -#define K_SYSCALL_CAN_SET_TIMING 250 -#define K_SYSCALL_CAN_SET_TIMING_DATA 251 -#define K_SYSCALL_CAN_START 252 -#define K_SYSCALL_CAN_STATS_GET_ACK_ERRORS 253 -#define K_SYSCALL_CAN_STATS_GET_BIT0_ERRORS 254 -#define K_SYSCALL_CAN_STATS_GET_BIT1_ERRORS 255 -#define K_SYSCALL_CAN_STATS_GET_BIT_ERRORS 256 -#define K_SYSCALL_CAN_STATS_GET_CRC_ERRORS 257 -#define K_SYSCALL_CAN_STATS_GET_FORM_ERRORS 258 -#define K_SYSCALL_CAN_STATS_GET_RX_OVERRUNS 259 -#define K_SYSCALL_CAN_STATS_GET_STUFF_ERRORS 260 -#define K_SYSCALL_CAN_STOP 261 -#define K_SYSCALL_CHARGER_CHARGE_ENABLE 262 -#define K_SYSCALL_CHARGER_GET_PROP 263 -#define K_SYSCALL_CHARGER_SET_PROP 264 -#define K_SYSCALL_COUNTER_CANCEL_CHANNEL_ALARM 265 -#define K_SYSCALL_COUNTER_GET_FREQUENCY 266 -#define K_SYSCALL_COUNTER_GET_GUARD_PERIOD 267 -#define K_SYSCALL_COUNTER_GET_MAX_TOP_VALUE 268 -#define K_SYSCALL_COUNTER_GET_NUM_OF_CHANNELS 269 -#define K_SYSCALL_COUNTER_GET_PENDING_INT 270 -#define K_SYSCALL_COUNTER_GET_TOP_VALUE 271 -#define K_SYSCALL_COUNTER_GET_VALUE 272 -#define K_SYSCALL_COUNTER_GET_VALUE_64 273 -#define K_SYSCALL_COUNTER_IS_COUNTING_UP 274 -#define K_SYSCALL_COUNTER_SET_CHANNEL_ALARM 275 -#define K_SYSCALL_COUNTER_SET_GUARD_PERIOD 276 -#define K_SYSCALL_COUNTER_SET_TOP_VALUE 277 -#define K_SYSCALL_COUNTER_START 278 -#define K_SYSCALL_COUNTER_STOP 279 -#define K_SYSCALL_COUNTER_TICKS_TO_US 280 -#define K_SYSCALL_COUNTER_US_TO_TICKS 281 -#define K_SYSCALL_DAC_CHANNEL_SETUP 282 -#define K_SYSCALL_DAC_WRITE_VALUE 283 -#define K_SYSCALL_DEVMUX_SELECT_GET 284 -#define K_SYSCALL_DEVMUX_SELECT_SET 285 -#define K_SYSCALL_DMA_CHAN_FILTER 286 -#define K_SYSCALL_DMA_RELEASE_CHANNEL 287 -#define K_SYSCALL_DMA_REQUEST_CHANNEL 288 -#define K_SYSCALL_DMA_RESUME 289 -#define K_SYSCALL_DMA_START 290 -#define K_SYSCALL_DMA_STOP 291 -#define K_SYSCALL_DMA_SUSPEND 292 +#define K_SYSCALL_ATOMIC_ADD 199 +#define K_SYSCALL_ATOMIC_AND 200 +#define K_SYSCALL_ATOMIC_CAS 201 +#define K_SYSCALL_ATOMIC_NAND 202 +#define K_SYSCALL_ATOMIC_OR 203 +#define K_SYSCALL_ATOMIC_PTR_CAS 204 +#define K_SYSCALL_ATOMIC_PTR_SET 205 +#define K_SYSCALL_ATOMIC_SET 206 +#define K_SYSCALL_ATOMIC_SUB 207 +#define K_SYSCALL_ATOMIC_XOR 208 +#define K_SYSCALL_AUXDISPLAY_BACKLIGHT_GET 209 +#define K_SYSCALL_AUXDISPLAY_BACKLIGHT_SET 210 +#define K_SYSCALL_AUXDISPLAY_BRIGHTNESS_GET 211 +#define K_SYSCALL_AUXDISPLAY_BRIGHTNESS_SET 212 +#define K_SYSCALL_AUXDISPLAY_CAPABILITIES_GET 213 +#define K_SYSCALL_AUXDISPLAY_CLEAR 214 +#define K_SYSCALL_AUXDISPLAY_CURSOR_POSITION_GET 215 +#define K_SYSCALL_AUXDISPLAY_CURSOR_POSITION_SET 216 +#define K_SYSCALL_AUXDISPLAY_CURSOR_SET_ENABLED 217 +#define K_SYSCALL_AUXDISPLAY_CURSOR_SHIFT_SET 218 +#define K_SYSCALL_AUXDISPLAY_CUSTOM_CHARACTER_SET 219 +#define K_SYSCALL_AUXDISPLAY_CUSTOM_COMMAND 220 +#define K_SYSCALL_AUXDISPLAY_DISPLAY_OFF 221 +#define K_SYSCALL_AUXDISPLAY_DISPLAY_ON 222 +#define K_SYSCALL_AUXDISPLAY_DISPLAY_POSITION_GET 223 +#define K_SYSCALL_AUXDISPLAY_DISPLAY_POSITION_SET 224 +#define K_SYSCALL_AUXDISPLAY_IS_BUSY 225 +#define K_SYSCALL_AUXDISPLAY_POSITION_BLINKING_SET_ENABLED 226 +#define K_SYSCALL_AUXDISPLAY_WRITE 227 +#define K_SYSCALL_BBRAM_CHECK_INVALID 228 +#define K_SYSCALL_BBRAM_CHECK_POWER 229 +#define K_SYSCALL_BBRAM_CHECK_STANDBY_POWER 230 +#define K_SYSCALL_BBRAM_GET_SIZE 231 +#define K_SYSCALL_BBRAM_READ 232 +#define K_SYSCALL_BBRAM_WRITE 233 +#define K_SYSCALL_BC12_SET_RESULT_CB 234 +#define K_SYSCALL_BC12_SET_ROLE 235 +#define K_SYSCALL_CAN_ADD_RX_FILTER_MSGQ 236 +#define K_SYSCALL_CAN_CALC_TIMING 237 +#define K_SYSCALL_CAN_CALC_TIMING_DATA 238 +#define K_SYSCALL_CAN_GET_BITRATE_MAX 239 +#define K_SYSCALL_CAN_GET_BITRATE_MIN 240 +#define K_SYSCALL_CAN_GET_CAPABILITIES 241 +#define K_SYSCALL_CAN_GET_CORE_CLOCK 242 +#define K_SYSCALL_CAN_GET_MAX_FILTERS 243 +#define K_SYSCALL_CAN_GET_MODE 244 +#define K_SYSCALL_CAN_GET_STATE 245 +#define K_SYSCALL_CAN_GET_TIMING_DATA_MAX 246 +#define K_SYSCALL_CAN_GET_TIMING_DATA_MIN 247 +#define K_SYSCALL_CAN_GET_TIMING_MAX 248 +#define K_SYSCALL_CAN_GET_TIMING_MIN 249 +#define K_SYSCALL_CAN_GET_TRANSCEIVER 250 +#define K_SYSCALL_CAN_RECOVER 251 +#define K_SYSCALL_CAN_REMOVE_RX_FILTER 252 +#define K_SYSCALL_CAN_SEND 253 +#define K_SYSCALL_CAN_SET_BITRATE 254 +#define K_SYSCALL_CAN_SET_BITRATE_DATA 255 +#define K_SYSCALL_CAN_SET_MODE 256 +#define K_SYSCALL_CAN_SET_TIMING 257 +#define K_SYSCALL_CAN_SET_TIMING_DATA 258 +#define K_SYSCALL_CAN_START 259 +#define K_SYSCALL_CAN_STATS_GET_ACK_ERRORS 260 +#define K_SYSCALL_CAN_STATS_GET_BIT0_ERRORS 261 +#define K_SYSCALL_CAN_STATS_GET_BIT1_ERRORS 262 +#define K_SYSCALL_CAN_STATS_GET_BIT_ERRORS 263 +#define K_SYSCALL_CAN_STATS_GET_CRC_ERRORS 264 +#define K_SYSCALL_CAN_STATS_GET_FORM_ERRORS 265 +#define K_SYSCALL_CAN_STATS_GET_RX_OVERRUNS 266 +#define K_SYSCALL_CAN_STATS_GET_STUFF_ERRORS 267 +#define K_SYSCALL_CAN_STOP 268 +#define K_SYSCALL_CHARGER_CHARGE_ENABLE 269 +#define K_SYSCALL_CHARGER_GET_PROP 270 +#define K_SYSCALL_CHARGER_SET_PROP 271 +#define K_SYSCALL_COUNTER_CANCEL_CHANNEL_ALARM 272 +#define K_SYSCALL_COUNTER_GET_FREQUENCY 273 +#define K_SYSCALL_COUNTER_GET_GUARD_PERIOD 274 +#define K_SYSCALL_COUNTER_GET_MAX_TOP_VALUE 275 +#define K_SYSCALL_COUNTER_GET_NUM_OF_CHANNELS 276 +#define K_SYSCALL_COUNTER_GET_PENDING_INT 277 +#define K_SYSCALL_COUNTER_GET_TOP_VALUE 278 +#define K_SYSCALL_COUNTER_GET_VALUE 279 +#define K_SYSCALL_COUNTER_GET_VALUE_64 280 +#define K_SYSCALL_COUNTER_IS_COUNTING_UP 281 +#define K_SYSCALL_COUNTER_SET_CHANNEL_ALARM 282 +#define K_SYSCALL_COUNTER_SET_GUARD_PERIOD 283 +#define K_SYSCALL_COUNTER_SET_TOP_VALUE 284 +#define K_SYSCALL_COUNTER_START 285 +#define K_SYSCALL_COUNTER_STOP 286 +#define K_SYSCALL_COUNTER_TICKS_TO_US 287 +#define K_SYSCALL_COUNTER_US_TO_TICKS 288 +#define K_SYSCALL_DAC_CHANNEL_SETUP 289 +#define K_SYSCALL_DAC_WRITE_VALUE 290 +#define K_SYSCALL_DEVMUX_SELECT_GET 291 +#define K_SYSCALL_DEVMUX_SELECT_SET 292 #define K_SYSCALL_EEPROM_GET_SIZE 293 #define K_SYSCALL_EEPROM_READ 294 #define K_SYSCALL_EEPROM_WRITE 295 diff --git a/variants/arduino_portenta_h7/llext-edk/include/zephyr/include/generated/zephyr/linker-kobject-prebuilt-data.h b/variants/arduino_portenta_h7/llext-edk/include/zephyr/include/generated/zephyr/linker-kobject-prebuilt-data.h deleted file mode 100644 index 82ef179e..00000000 --- a/variants/arduino_portenta_h7/llext-edk/include/zephyr/include/generated/zephyr/linker-kobject-prebuilt-data.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef KOBJECT_DATA_ALIGN -#define KOBJECT_DATA_ALIGN 4 -#endif - -#ifndef KOBJECT_DATA_SZ -#define KOBJECT_DATA_SZ 8496 -#endif - diff --git a/variants/arduino_portenta_h7/llext-edk/include/zephyr/include/generated/zephyr/linker-kobject-prebuilt-priv-stacks.h b/variants/arduino_portenta_h7/llext-edk/include/zephyr/include/generated/zephyr/linker-kobject-prebuilt-priv-stacks.h deleted file mode 100644 index ef65767d..00000000 --- a/variants/arduino_portenta_h7/llext-edk/include/zephyr/include/generated/zephyr/linker-kobject-prebuilt-priv-stacks.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef KOBJECT_PRIV_STACKS_ALIGN -#define KOBJECT_PRIV_STACKS_ALIGN 128 -#endif - -#ifndef KOBJECT_PRIV_STACKS_SZ -#define KOBJECT_PRIV_STACKS_SZ 3456 -#endif - diff --git a/variants/arduino_portenta_h7/llext-edk/include/zephyr/include/generated/zephyr/linker-kobject-prebuilt-rodata.h b/variants/arduino_portenta_h7/llext-edk/include/zephyr/include/generated/zephyr/linker-kobject-prebuilt-rodata.h deleted file mode 100644 index 00435a78..00000000 --- a/variants/arduino_portenta_h7/llext-edk/include/zephyr/include/generated/zephyr/linker-kobject-prebuilt-rodata.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef KOBJECT_RODATA_ALIGN -#define KOBJECT_RODATA_ALIGN 4 -#endif - -#ifndef KOBJECT_RODATA_SZ -#define KOBJECT_RODATA_SZ 552 -#endif -