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vcstap.tre
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ÀÄvcstap
ÃÄMAIN 0/484 Ram=2
³ ÃÄ@cinit1 (Inline) Ram=0
³ ÃÄ??0??
³ ÃÄinit 0/124 Ram=0
³ ³ ÃÄ@delay_ms1 0/40 Ram=1
³ ³ ÃÄuart_init 0/124 Ram=0
³ ³ ³ ÃÄ@delay_ms1 0/40 Ram=1
³ ³ ³ ÃÄ@delay_ms1 0/40 Ram=1
³ ³ ³ ÃÄuart_write 0/88 Ram=3
³ ³ ³ ³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ³ ÀÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ÃÄuart_write 0/88 Ram=3
³ ³ ³ ³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ³ ÀÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ÃÄuart_write 0/88 Ram=3
³ ³ ³ ³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ³ ÀÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ÃÄuart_write 0/88 Ram=3
³ ³ ³ ³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ³ ÀÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ÃÄuart_write 0/88 Ram=3
³ ³ ³ ³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ³ ÀÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ÃÄuart_write 0/88 Ram=3
³ ³ ³ ³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ³ ÀÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ÀÄuart_write 0/88 Ram=3
³ ³ ³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ÀÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ÃÄcan_init 0/242 Ram=1
³ ³ ³ ÃÄcan_set_mode 0/38 Ram=2
³ ³ ³ ÃÄcan_set_baud 0/14 Ram=0
³ ³ ³ ÃÄcan_set_id 0/308 Ram=13
³ ³ ³ ÃÄcan_set_id 0/308 Ram=13
³ ³ ³ ÃÄcan_set_id 0/308 Ram=13
³ ³ ³ ÃÄcan_set_id 0/308 Ram=13
³ ³ ³ ÃÄcan_set_id 0/308 Ram=13
³ ³ ³ ÃÄcan_set_id 0/308 Ram=13
³ ³ ³ ÃÄcan_set_id 0/308 Ram=13
³ ³ ³ ÃÄcan_set_id 0/308 Ram=13
³ ³ ³ ÀÄcan_set_mode 0/38 Ram=2
³ ³ ÃÄ@MEMSET 0/26 Ram=0
³ ³ ÀÄ@MEMSET 0/26 Ram=0
³ ÃÄread_param_file 0/88 Ram=3
³ ³ ÃÄEEPROMDataRead 0/140 Ram=12
³ ³ ³ ÀÄxor_crc (Inline) Ram=2
³ ³ ÀÄwrite_default_param_file 0/48 Ram=0
³ ³ ÀÄwrite_param_file 0/84 Ram=3
³ ³ ÀÄEEPROMDataWrite 0/164 Ram=10
³ ³ ÀÄxor_crc (Inline) Ram=2
³ ÃÄwrite_default_param_file 0/48 Ram=0
³ ³ ÀÄwrite_param_file 0/84 Ram=3
³ ³ ÀÄEEPROMDataWrite 0/164 Ram=10
³ ³ ÀÄxor_crc (Inline) Ram=2
³ ÃÄ@PSTRINGCN_9600_31766_31767 0/42 Ram=3
³ ÃÄ@PSTRINGC_9600_31766_31767 0/34 Ram=2
³ ÃÄ@PSTRINGCN_9600_31766_31767 0/42 Ram=3
³ ÃÄ@PRINTF_LU_9600_31766_31767 0/172 Ram=9
³ ÃÄ@PSTRINGC_9600_31766_31767 0/34 Ram=2
³ ÃÄ@PSTRINGC_9600_31766_31767 0/34 Ram=2
³ ÃÄ@PSTRINGC_9600_31766_31767 0/34 Ram=2
³ ÃÄ@PSTRINGC_9600_31766_31767 0/34 Ram=2
³ ÃÄ@PSTRINGC_9600_31766_31767 0/34 Ram=2
³ ÃÄ@PSTRINGC_9600_31766_31767 0/34 Ram=2
³ ÃÄ@PSTRINGC_9600_31766_31767 0/34 Ram=2
³ ÃÄ@PSTRINGC_9600_31766_31767 0/34 Ram=2
³ ÃÄ@delay_ms1 0/40 Ram=1
³ ÃÄ@delay_ms1 0/40 Ram=1
³ ÃÄ@delay_ms1 0/40 Ram=1
³ ÃÄread_data_xrw2g 0/60 Ram=3
³ ³ ÃÄuart_kbhit 0/18 Ram=1
³ ³ ³ ÀÄuart_read 0/140 Ram=3
³ ³ ³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ÀÄ@I2C_READ_1 0/78 Ram=3
³ ³ ÃÄuart_kbhit 0/18 Ram=1
³ ³ ³ ÀÄuart_read 0/140 Ram=3
³ ³ ³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ³ ÀÄ@I2C_READ_1 0/78 Ram=3
³ ³ ÀÄuart_getc (Inline) Ram=0
³ ³ ÀÄuart_read 0/140 Ram=3
³ ³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ³ ÀÄ@I2C_READ_1 0/78 Ram=3
³ ÃÄsend_can_query 0/72 Ram=9
³ ³ ÃÄcan_putd 0/210 Ram=17
³ ³ ³ ÀÄcan_set_id 0/308 Ram=13
³ ³ ÀÄcan_init 0/242 Ram=1
³ ³ ÃÄcan_set_mode 0/38 Ram=2
³ ³ ÃÄcan_set_baud 0/14 Ram=0
³ ³ ÃÄcan_set_id 0/308 Ram=13
³ ³ ÃÄcan_set_id 0/308 Ram=13
³ ³ ÃÄcan_set_id 0/308 Ram=13
³ ³ ÃÄcan_set_id 0/308 Ram=13
³ ³ ÃÄcan_set_id 0/308 Ram=13
³ ³ ÃÄcan_set_id 0/308 Ram=13
³ ³ ÃÄcan_set_id 0/308 Ram=13
³ ³ ÃÄcan_set_id 0/308 Ram=13
³ ³ ÀÄcan_set_mode 0/38 Ram=2
³ ÃÄlive_send_vcs 0/462 Ram=184
³ ³ ÃÄ@MEMSET 0/26 Ram=0
³ ³ ÃÄcrc_chk 0/102 Ram=8
³ ³ ÃÄ@PUTCHARI_BIU_1 0/8 Ram=0
³ ³ ÃÄ@PUTCHARI_BIU_1 0/8 Ram=0
³ ³ ÀÄ@PUTCHARI_BIU_1 0/8 Ram=0
³ ÀÄlive_send_xrw2g 0/344 Ram=8
³ ÃÄcrc_chk 0/102 Ram=8
³ ÃÄcrc_chk 0/102 Ram=8
³ ÃÄ@PUTCHARI_BIU_1 0/8 Ram=0
³ ÀÄuart_putc 0/18 Ram=1
³ ÀÄuart_write 0/88 Ram=3
³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ÃÄ@I2C_WRITE_1 0/82 Ram=1
³ ÀÄ@I2C_WRITE_1 0/82 Ram=1
ÃÄmodbus_timeout_now 0/50 Ram=0
³ ÀÄmodbus_enable_timeout 0/20 Ram=1
ÃÄisr_1ms 0/108 Ram=0
ÃÄisr_serial_inverter 0/118 Ram=3
³ ÃÄ@GETCH_BIU_1 0/24 Ram=0
³ ÃÄmodbus_calc_crc 0/46 Ram=2
³ ³ ÃÄ@const690 0/272 Ram=0
³ ³ ÀÄ@const693 0/272 Ram=0
³ ÀÄmodbus_enable_timeout 0/20 Ram=1
ÃÄisr_can_rx0 0/434 Ram=0
³ ÀÄcan_receive (Inline) Ram=16
³ ÀÄcan_getd (Inline) Ram=14
³ ÀÄcan_get_id 0/504 Ram=14
ÃÄisr_can_rx1 0/434 Ram=0
³ ÀÄcan_receive (Inline) Ram=16
³ ÀÄcan_getd (Inline) Ram=14
³ ÀÄcan_get_id 0/504 Ram=14
ÀÄisr_canirx 0/8 Ram=0