From ea181e2621c332ef0b911c339a26d467fa4de880 Mon Sep 17 00:00:00 2001 From: hujun5 Date: Mon, 25 Mar 2024 10:18:44 +0800 Subject: [PATCH] arm: armv7-a/r and armv8-r up_cpu_index inline reason: inline small code to improve performance Signed-off-by: hujun5 --- arch/arm/include/arm/irq.h | 23 ++++++++++ arch/arm/include/armv6-m/irq.h | 22 +++++++++ arch/arm/include/armv7-a/irq.h | 52 +++++++++++++++++++++ arch/arm/include/armv7-m/irq.h | 22 +++++++++ arch/arm/include/armv7-r/irq.h | 52 +++++++++++++++++++++ arch/arm/include/armv8-m/irq.h | 22 +++++++++ arch/arm/include/armv8-r/irq.h | 52 +++++++++++++++++++++ arch/arm/include/irq.h | 22 --------- arch/arm/include/tlsr82/irq.h | 22 +++++++++ arch/arm/src/armv7-a/CMakeLists.txt | 9 +--- arch/arm/src/armv7-a/Make.defs | 2 +- arch/arm/src/armv7-a/arm_cpuindex.c | 71 ----------------------------- arch/arm/src/armv7-a/sctlr.h | 22 --------- arch/arm/src/armv7-r/CMakeLists.txt | 1 - arch/arm/src/armv7-r/Make.defs | 2 +- arch/arm/src/armv7-r/arm_cpuindex.c | 71 ----------------------------- arch/arm/src/armv7-r/sctlr.h | 21 --------- arch/arm/src/armv8-r/sctlr.h | 21 --------- 18 files changed, 270 insertions(+), 239 deletions(-) delete mode 100644 arch/arm/src/armv7-a/arm_cpuindex.c delete mode 100644 arch/arm/src/armv7-r/arm_cpuindex.c diff --git a/arch/arm/include/arm/irq.h b/arch/arm/include/arm/irq.h index dd7ab7cb0a673..88ecca4210f05 100644 --- a/arch/arm/include/arm/irq.h +++ b/arch/arm/include/arm/irq.h @@ -219,6 +219,29 @@ static inline irqstate_t up_irq_enable(void) : "cc", "memory"); return flags; } + +/**************************************************************************** + * Name: up_cpu_index + * + * Description: + * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + * Input Parameters: + * None + * + * Returned Value: + * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + ****************************************************************************/ + +#ifdef CONFIG_SMP +int up_cpu_index(void) noinstrument_function; +#else +# define up_cpu_index() 0 +#endif /* CONFIG_SMP */ + #endif /* __ASSEMBLY__ */ /**************************************************************************** diff --git a/arch/arm/include/armv6-m/irq.h b/arch/arm/include/armv6-m/irq.h index 29720afcf2043..9a0426a2dfb29 100644 --- a/arch/arm/include/armv6-m/irq.h +++ b/arch/arm/include/armv6-m/irq.h @@ -331,6 +331,28 @@ static inline void setcontrol(uint32_t control) : "memory"); } +/**************************************************************************** + * Name: up_cpu_index + * + * Description: + * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + * Input Parameters: + * None + * + * Returned Value: + * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + ****************************************************************************/ + +#ifdef CONFIG_SMP +int up_cpu_index(void) noinstrument_function; +#else +# define up_cpu_index() 0 +#endif /* CONFIG_SMP */ + static inline_function uint32_t up_getsp(void) { register uint32_t sp; diff --git a/arch/arm/include/armv7-a/irq.h b/arch/arm/include/armv7-a/irq.h index a158e056dbdc5..cb8f14831cf66 100644 --- a/arch/arm/include/armv7-a/irq.h +++ b/arch/arm/include/armv7-a/irq.h @@ -198,6 +198,20 @@ #define REG_PIC REG_R10 +/* Multiprocessor Affinity Register (MPIDR): CRn=c0, opc1=0, CRm=c0, opc2=5 */ + +#define MPIDR_CPUID_SHIFT (0) /* Bits 0-1: CPU ID */ +#define MPIDR_CPUID_MASK (3 << MPIDR_CPUID_SHIFT) +# define MPIDR_CPUID_CPU0 (0 << MPIDR_CPUID_SHIFT) +# define MPIDR_CPUID_CPU1 (1 << MPIDR_CPUID_SHIFT) +# define MPIDR_CPUID_CPU2 (2 << MPIDR_CPUID_SHIFT) +# define MPIDR_CPUID_CPU3 (3 << MPIDR_CPUID_SHIFT) + /* Bits 2-7: Reserved */ +#define MPIDR_CLUSTID_SHIFT (8) /* Bits 8-11: Cluster ID value */ +#define MPIDR_CLUSTID_MASK (15 << MPIDR_CLUSTID_SHIFT) + /* Bits 12-29: Reserved */ +#define MPIDR_U (1 << 30) /* Bit 30: Multiprocessing Extensions. */ + /**************************************************************************** * Public Types ****************************************************************************/ @@ -425,6 +439,44 @@ noinstrument_function static inline void up_irq_restore(irqstate_t flags) ); } +/**************************************************************************** + * Name: up_cpu_index + * + * Description: + * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + * Input Parameters: + * None + * + * Returned Value: + * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + ****************************************************************************/ + +#ifdef CONFIG_SMP +noinstrument_function +static inline_function int up_cpu_index(void) +{ + unsigned int mpidr; + + /* Read the Multiprocessor Affinity Register (MPIDR) */ + + __asm__ __volatile__ + ( + "mrc " "p15, " "0" ", %0, " "c0" ", " "c0" ", " "5" "\n" + : "=r"(mpidr) + ); + + /* And return the CPU ID field */ + + return (mpidr & MPIDR_CPUID_MASK) >> MPIDR_CPUID_SHIFT; +} +#else +# define up_cpu_index() 0 +#endif /* CONFIG_SMP */ + static inline_function uint32_t up_getsp(void) { register uint32_t sp; diff --git a/arch/arm/include/armv7-m/irq.h b/arch/arm/include/armv7-m/irq.h index cd6fa0b7aa10a..1c78a60140e54 100644 --- a/arch/arm/include/armv7-m/irq.h +++ b/arch/arm/include/armv7-m/irq.h @@ -536,6 +536,28 @@ static inline void setcontrol(uint32_t control) : "memory"); } +/**************************************************************************** + * Name: up_cpu_index + * + * Description: + * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + * Input Parameters: + * None + * + * Returned Value: + * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + ****************************************************************************/ + +#ifdef CONFIG_SMP +int up_cpu_index(void) noinstrument_function; +#else +# define up_cpu_index() 0 +#endif /* CONFIG_SMP */ + static inline_function uint32_t up_getsp(void) { register uint32_t sp; diff --git a/arch/arm/include/armv7-r/irq.h b/arch/arm/include/armv7-r/irq.h index cbfaab73152bb..a19070b79abd8 100644 --- a/arch/arm/include/armv7-r/irq.h +++ b/arch/arm/include/armv7-r/irq.h @@ -198,6 +198,20 @@ #define REG_PIC REG_R10 +/* Multiprocessor Affinity Register (MPIDR): CRn=c0, opc1=0, CRm=c0, opc2=5 */ + +#define MPIDR_CPUID_SHIFT (0) /* Bits 0-1: CPU ID */ +#define MPIDR_CPUID_MASK (3 << MPIDR_CPUID_SHIFT) +# define MPIDR_CPUID_CPU0 (0 << MPIDR_CPUID_SHIFT) +# define MPIDR_CPUID_CPU1 (1 << MPIDR_CPUID_SHIFT) +# define MPIDR_CPUID_CPU2 (2 << MPIDR_CPUID_SHIFT) +# define MPIDR_CPUID_CPU3 (3 << MPIDR_CPUID_SHIFT) + /* Bits 2-7: Reserved */ +#define MPIDR_CLUSTID_SHIFT (8) /* Bits 8-11: Cluster ID value */ +#define MPIDR_CLUSTID_MASK (15 << MPIDR_CLUSTID_SHIFT) + /* Bits 12-29: Reserved */ +#define MPIDR_U (1 << 30) /* Bit 30: Multiprocessing Extensions. */ + /**************************************************************************** * Public Types ****************************************************************************/ @@ -420,6 +434,44 @@ static inline void up_irq_restore(irqstate_t flags) ); } +/**************************************************************************** + * Name: up_cpu_index + * + * Description: + * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + * Input Parameters: + * None + * + * Returned Value: + * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + ****************************************************************************/ + +#ifdef CONFIG_SMP +noinstrument_function +static inline_function int up_cpu_index(void) +{ + uint32_t mpidr; + + /* Read the Multiprocessor Affinity Register (MPIDR) */ + + __asm__ __volatile__ + ( + "mrc " "p15, " "0" ", %0, " "c0" ", " "c0" ", " "5" "\n" + : "=r"(mpidr) + ); + + /* And return the CPU ID field */ + + return (mpidr & MPIDR_CPUID_MASK) >> MPIDR_CPUID_SHIFT; +} +#else +# define up_cpu_index() 0 +#endif /* CONFIG_SMP */ + static inline_function uint32_t up_getsp(void) { register uint32_t sp; diff --git a/arch/arm/include/armv8-m/irq.h b/arch/arm/include/armv8-m/irq.h index 8908d0a2ca9ce..60c43a6149d7e 100644 --- a/arch/arm/include/armv8-m/irq.h +++ b/arch/arm/include/armv8-m/irq.h @@ -509,6 +509,28 @@ static inline void setcontrol(uint32_t control) : "memory"); } +/**************************************************************************** + * Name: up_cpu_index + * + * Description: + * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + * Input Parameters: + * None + * + * Returned Value: + * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + ****************************************************************************/ + +#ifdef CONFIG_SMP +int up_cpu_index(void) noinstrument_function; +#else +# define up_cpu_index() 0 +#endif /* CONFIG_SMP */ + static inline_function uint32_t up_getsp(void) { uint32_t sp; diff --git a/arch/arm/include/armv8-r/irq.h b/arch/arm/include/armv8-r/irq.h index 2f4216fb04103..25cd71c3f3e41 100644 --- a/arch/arm/include/armv8-r/irq.h +++ b/arch/arm/include/armv8-r/irq.h @@ -198,6 +198,20 @@ #define REG_PIC REG_R10 +/* Multiprocessor Affinity Register (MPIDR): CRn=c0, opc1=0, CRm=c0, opc2=5 */ + +#define MPIDR_CPUID_SHIFT (0) /* Bits 0-1: CPU ID */ +#define MPIDR_CPUID_MASK (3 << MPIDR_CPUID_SHIFT) +# define MPIDR_CPUID_CPU0 (0 << MPIDR_CPUID_SHIFT) +# define MPIDR_CPUID_CPU1 (1 << MPIDR_CPUID_SHIFT) +# define MPIDR_CPUID_CPU2 (2 << MPIDR_CPUID_SHIFT) +# define MPIDR_CPUID_CPU3 (3 << MPIDR_CPUID_SHIFT) + /* Bits 2-7: Reserved */ +#define MPIDR_CLUSTID_SHIFT (8) /* Bits 8-11: Cluster ID value */ +#define MPIDR_CLUSTID_MASK (15 << MPIDR_CLUSTID_SHIFT) + /* Bits 12-29: Reserved */ +#define MPIDR_U (1 << 30) /* Bit 30: Multiprocessing Extensions. */ + /**************************************************************************** * Public Types ****************************************************************************/ @@ -420,6 +434,44 @@ static inline void up_irq_restore(irqstate_t flags) ); } +/**************************************************************************** + * Name: up_cpu_index + * + * Description: + * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + * Input Parameters: + * None + * + * Returned Value: + * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + ****************************************************************************/ + +#ifdef CONFIG_SMP +noinstrument_function +static inline_function int up_cpu_index(void) +{ + uint32_t mpidr; + + /* Read the Multiprocessor Affinity Register (MPIDR) */ + + __asm__ __volatile__ + ( + "mrc " "p15, " "0" ", %0, " "c0" ", " "c0" ", " "5" "\n" + : "=r"(mpidr) + ); + + /* And return the CPU ID field */ + + return (mpidr & MPIDR_CPUID_MASK) >> MPIDR_CPUID_SHIFT; +} +#else +# define up_cpu_index() 0 +#endif /* CONFIG_SMP */ + static inline_function uint32_t up_getsp(void) { register uint32_t sp; diff --git a/arch/arm/include/irq.h b/arch/arm/include/irq.h index ccd28abb7a4b8..300db41904c76 100644 --- a/arch/arm/include/irq.h +++ b/arch/arm/include/irq.h @@ -105,28 +105,6 @@ EXTERN volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; * Public Function Prototypes ****************************************************************************/ -/**************************************************************************** - * Name: up_cpu_index - * - * Description: - * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that - * corresponds to the currently executing CPU. - * - * Input Parameters: - * None - * - * Returned Value: - * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that - * corresponds to the currently executing CPU. - * - ****************************************************************************/ - -#ifdef CONFIG_SMP -int up_cpu_index(void) noinstrument_function; -#else -# define up_cpu_index() (0) -#endif - /**************************************************************************** * Inline functions ****************************************************************************/ diff --git a/arch/arm/include/tlsr82/irq.h b/arch/arm/include/tlsr82/irq.h index edb15a170273c..077ef8c0ed5b4 100644 --- a/arch/arm/include/tlsr82/irq.h +++ b/arch/arm/include/tlsr82/irq.h @@ -236,6 +236,28 @@ static inline uint32_t getcontrol(void) return 0; } +/**************************************************************************** + * Name: up_cpu_index + * + * Description: + * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + * Input Parameters: + * None + * + * Returned Value: + * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + ****************************************************************************/ + +#ifdef CONFIG_SMP +int up_cpu_index(void) noinstrument_function; +#else +# define up_cpu_index() 0 +#endif /* CONFIG_SMP */ + static inline_function uint32_t up_getsp(void) { register uint32_t sp; diff --git a/arch/arm/src/armv7-a/CMakeLists.txt b/arch/arm/src/armv7-a/CMakeLists.txt index 33660f6d3611a..cd390645d1e11 100644 --- a/arch/arm/src/armv7-a/CMakeLists.txt +++ b/arch/arm/src/armv7-a/CMakeLists.txt @@ -105,14 +105,7 @@ if(CONFIG_ARCH_FPU) endif() if(CONFIG_SMP) - list( - APPEND - SRCS - arm_cpuindex.c - arm_cpustart.c - arm_cpupause.c - arm_cpuidlestack.c - arm_scu.c) + list(APPEND SRCS arm_cpustart.c arm_cpupause.c arm_cpuidlestack.c arm_scu.c) endif() if(CONFIG_ARCH_HAVE_PSCI) diff --git a/arch/arm/src/armv7-a/Make.defs b/arch/arm/src/armv7-a/Make.defs index 7227039291e7c..331bb62fc11ad 100644 --- a/arch/arm/src/armv7-a/Make.defs +++ b/arch/arm/src/armv7-a/Make.defs @@ -90,7 +90,7 @@ ifeq ($(CONFIG_ARCH_FPU),y) endif ifeq ($(CONFIG_SMP),y) - CMN_CSRCS += arm_cpuindex.c arm_cpustart.c arm_cpupause.c arm_cpuidlestack.c + CMN_CSRCS += arm_cpustart.c arm_cpupause.c arm_cpuidlestack.c CMN_CSRCS += arm_scu.c endif diff --git a/arch/arm/src/armv7-a/arm_cpuindex.c b/arch/arm/src/armv7-a/arm_cpuindex.c deleted file mode 100644 index d94f3f9dd6c8c..0000000000000 --- a/arch/arm/src/armv7-a/arm_cpuindex.c +++ /dev/null @@ -1,71 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-a/arm_cpuindex.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "cp15.h" -#include "sctlr.h" - -#ifdef CONFIG_SMP - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_cpu_index - * - * Description: - * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that - * corresponds to the currently executing CPU. - * - * If TLS is enabled, then the RTOS can get this information from the TLS - * info structure. Otherwise, the MCU-specific logic must provide some - * mechanism to provide the CPU index. - * - * Input Parameters: - * None - * - * Returned Value: - * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that - * corresponds to the currently executing CPU. - * - ****************************************************************************/ - -int up_cpu_index(void) -{ - /* Read the Multiprocessor Affinity Register (MPIDR) */ - - uint32_t mpidr = cp15_rdmpidr(); - - /* And return the CPU ID field */ - - return (mpidr & MPIDR_CPUID_MASK) >> MPIDR_CPUID_SHIFT; -} - -#endif /* CONFIG_SMP */ diff --git a/arch/arm/src/armv7-a/sctlr.h b/arch/arm/src/armv7-a/sctlr.h index 9f8b7cc24f46d..917cd7dcb0899 100644 --- a/arch/arm/src/armv7-a/sctlr.h +++ b/arch/arm/src/armv7-a/sctlr.h @@ -62,20 +62,6 @@ * Tightly CoupledMemory (TCM), so this register always Reads-As-Zero (RAZ). */ -/* Multiprocessor Affinity Register (MPIDR) */ - -#define MPIDR_CPUID_SHIFT (0) /* Bits 0-1: CPU ID */ -#define MPIDR_CPUID_MASK (3 << MPIDR_CPUID_SHIFT) -# define MPIDR_CPUID_CPU0 (0 << MPIDR_CPUID_SHIFT) -# define MPIDR_CPUID_CPU1 (1 << MPIDR_CPUID_SHIFT) -# define MPIDR_CPUID_CPU2 (2 << MPIDR_CPUID_SHIFT) -# define MPIDR_CPUID_CPU3 (3 << MPIDR_CPUID_SHIFT) - /* Bits 2-7: Reserved */ -#define MPIDR_CLUSTID_SHIFT (8) /* Bits 8-11: Cluster ID value */ -#define MPIDR_CLUSTID_MASK (15 << MPIDR_CLUSTID_SHIFT) - /* Bits 12-29: Reserved */ -#define MPIDR_U (1 << 30) /* Bit 30: Multiprocessing Extensions. */ - /* Processor Feature Register 0 (ID_PFR0) */ /* TODO: To be provided */ @@ -461,14 +447,6 @@ static inline unsigned int cp15_rdid(void) return CP15_GET(MIDR); } -/* Get the Multiprocessor Affinity Register (MPIDR) */ - -noinstrument_function -static inline unsigned int cp15_rdmpidr(void) -{ - return CP15_GET(MPIDR); -} - /* Read/write the system control register (SCTLR) */ static inline unsigned int cp15_rdsctlr(void) diff --git a/arch/arm/src/armv7-r/CMakeLists.txt b/arch/arm/src/armv7-r/CMakeLists.txt index e2b2cce85a7f8..784b9ab0946c6 100644 --- a/arch/arm/src/armv7-r/CMakeLists.txt +++ b/arch/arm/src/armv7-r/CMakeLists.txt @@ -70,7 +70,6 @@ if(CONFIG_SMP) APPEND SRCS arm_cpuhead.S - arm_cpuindex.c arm_cpustart.c arm_cpupause.c arm_cpuidlestack.c diff --git a/arch/arm/src/armv7-r/Make.defs b/arch/arm/src/armv7-r/Make.defs index be004c67fe30f..8cf8645ba261f 100644 --- a/arch/arm/src/armv7-r/Make.defs +++ b/arch/arm/src/armv7-r/Make.defs @@ -59,6 +59,6 @@ endif ifeq ($(CONFIG_SMP),y) CMN_ASRCS += arm_cpuhead.S - CMN_CSRCS += arm_cpuindex.c arm_cpustart.c arm_cpupause.c + CMN_CSRCS += arm_cpustart.c arm_cpupause.c CMN_CSRCS += arm_cpuidlestack.c arm_scu.c endif diff --git a/arch/arm/src/armv7-r/arm_cpuindex.c b/arch/arm/src/armv7-r/arm_cpuindex.c deleted file mode 100644 index c36cd0d2f88a2..0000000000000 --- a/arch/arm/src/armv7-r/arm_cpuindex.c +++ /dev/null @@ -1,71 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-r/arm_cpuindex.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "cp15.h" -#include "sctlr.h" - -#ifdef CONFIG_SMP - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_cpu_index - * - * Description: - * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that - * corresponds to the currently executing CPU. - * - * If TLS is enabled, then the RTOS can get this information from the TLS - * info structure. Otherwise, the MCU-specific logic must provide some - * mechanism to provide the CPU index. - * - * Input Parameters: - * None - * - * Returned Value: - * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that - * corresponds to the currently executing CPU. - * - ****************************************************************************/ - -int up_cpu_index(void) -{ - /* Read the Multiprocessor Affinity Register (MPIDR) */ - - uint32_t mpidr = cp15_rdmpidr(); - - /* And return the CPU ID field */ - - return (mpidr & MPIDR_CPUID_MASK) >> MPIDR_CPUID_SHIFT; -} - -#endif /* CONFIG_SMP */ diff --git a/arch/arm/src/armv7-r/sctlr.h b/arch/arm/src/armv7-r/sctlr.h index 5da84ed8f2225..610024daa3321 100644 --- a/arch/arm/src/armv7-r/sctlr.h +++ b/arch/arm/src/armv7-r/sctlr.h @@ -61,20 +61,6 @@ * TODO: To be provided */ -/* Multiprocessor Affinity Register (MPIDR): CRn=c0, opc1=0, CRm=c0, opc2=5 */ - -#define MPIDR_CPUID_SHIFT (0) /* Bits 0-1: CPU ID */ -#define MPIDR_CPUID_MASK (3 << MPIDR_CPUID_SHIFT) -# define MPIDR_CPUID_CPU0 (0 << MPIDR_CPUID_SHIFT) -# define MPIDR_CPUID_CPU1 (1 << MPIDR_CPUID_SHIFT) -# define MPIDR_CPUID_CPU2 (2 << MPIDR_CPUID_SHIFT) -# define MPIDR_CPUID_CPU3 (3 << MPIDR_CPUID_SHIFT) - /* Bits 2-7: Reserved */ -#define MPIDR_CLUSTID_SHIFT (8) /* Bits 8-11: Cluster ID value */ -#define MPIDR_CLUSTID_MASK (15 << MPIDR_CLUSTID_SHIFT) - /* Bits 12-29: Reserved */ -#define MPIDR_U (1 << 30) /* Bit 30: Multiprocessing Extensions. */ - /* Revision ID Register (REVIDR): CRn=c0, opc1=0, CRm=c0, opc2=6 * TODO: To be provided */ @@ -521,13 +507,6 @@ static inline unsigned int cp15_rdid(void) return CP15_GET(MIDR); } -/* Get the Multiprocessor Affinity Register (MPIDR) */ - -static inline unsigned int cp15_rdmpidr(void) -{ - return CP15_GET(MPIDR); -} - /* Read/write the system control register (SCTLR) */ static inline unsigned int cp15_rdsctlr(void) diff --git a/arch/arm/src/armv8-r/sctlr.h b/arch/arm/src/armv8-r/sctlr.h index bbfaadd194311..76309d1e82e16 100644 --- a/arch/arm/src/armv8-r/sctlr.h +++ b/arch/arm/src/armv8-r/sctlr.h @@ -61,20 +61,6 @@ * TODO: To be provided */ -/* Multiprocessor Affinity Register (MPIDR): CRn=c0, opc1=0, CRm=c0, opc2=5 */ - -#define MPIDR_CPUID_SHIFT (0) /* Bits 0-1: CPU ID */ -#define MPIDR_CPUID_MASK (3 << MPIDR_CPUID_SHIFT) -# define MPIDR_CPUID_CPU0 (0 << MPIDR_CPUID_SHIFT) -# define MPIDR_CPUID_CPU1 (1 << MPIDR_CPUID_SHIFT) -# define MPIDR_CPUID_CPU2 (2 << MPIDR_CPUID_SHIFT) -# define MPIDR_CPUID_CPU3 (3 << MPIDR_CPUID_SHIFT) - /* Bits 2-7: Reserved */ -#define MPIDR_CLUSTID_SHIFT (8) /* Bits 8-11: Cluster ID value */ -#define MPIDR_CLUSTID_MASK (15 << MPIDR_CLUSTID_SHIFT) - /* Bits 12-29: Reserved */ -#define MPIDR_U (1 << 30) /* Bit 30: Multiprocessing Extensions. */ - /* Revision ID Register (REVIDR): CRn=c0, opc1=0, CRm=c0, opc2=6 * TODO: To be provided */ @@ -521,13 +507,6 @@ static inline unsigned int cp15_rdid(void) return CP15_GET(MIDR); } -/* Get the Multiprocessor Affinity Register (MPIDR) */ - -static inline unsigned int cp15_rdmpidr(void) -{ - return CP15_GET(MPIDR); -} - /* Read/write the system control register (SCTLR) */ static inline unsigned int cp15_rdsctlr(void)