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lahaina-camera.dtsi
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lahaina-camera.dtsi
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#include <dt-bindings/msm/msm-camera.h>
&soc {
qcom,cam-req-mgr {
compatible = "qcom,cam-req-mgr";
status = "ok";
};
qcom,cam-sync {
compatible = "qcom,cam-sync";
status = "ok";
};
cam_csiphy0: qcom,csiphy0 {
cell-index = <0>;
compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy";
reg = <0x0ac6a000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0x6a000>;
interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csiphy0";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
csi-vdd-1p2-supply = <&pm8350_l6>;
csi-vdd-0p9-supply = <&pm8350_l5>;
rgltr-cntrl-support;
rgltr-enable-sync = <1>;
regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9";
rgltr-min-voltage = <0 1200000 880000>;
rgltr-max-voltage = <0 1208000 888000>;
rgltr-load-current = <0 54000 96400>;
clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&clock_camcc CAM_CC_CSIPHY0_CLK>,
<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>;
clock-names = "cphy_rx_clk_src",
"csiphy0_clk",
"csi0phytimer_clk_src",
"csi0phytimer_clk";
src-clock-name = "csi0phytimer_clk_src";
clock-cntl-level = "nominal";
clock-rates =
<400000000 0 300000000 0>;
status = "ok";
};
cam_csiphy1: qcom,csiphy1 {
cell-index = <1>;
compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy";
reg = <0xac6c000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0x6c000>;
interrupts = <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csiphy1";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
csi-vdd-1p2-supply = <&pm8350_l6>;
csi-vdd-0p9-supply = <&pm8350_l5>;
rgltr-cntrl-support;
rgltr-enable-sync = <1>;
regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9";
rgltr-min-voltage = <0 1200000 880000>;
rgltr-max-voltage = <0 1208000 888000>;
rgltr-load-current = <0 54000 96400>;
clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&clock_camcc CAM_CC_CSIPHY1_CLK>,
<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>;
clock-names = "cphy_rx_clk_src",
"csiphy1_clk",
"csi1phytimer_clk_src",
"csi1phytimer_clk";
src-clock-name = "csi1phytimer_clk_src";
clock-cntl-level = "nominal";
clock-rates =
<400000000 0 300000000 0>;
status = "ok";
};
cam_csiphy2: qcom,csiphy2 {
cell-index = <2>;
compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy";
reg = <0xac6e000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0x6e000>;
interrupts = <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csiphy2";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
csi-vdd-1p2-supply = <&pm8350_l6>;
csi-vdd-0p9-supply = <&pm8350_l5>;
rgltr-cntrl-support;
rgltr-enable-sync = <1>;
regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9";
rgltr-min-voltage = <0 1200000 880000>;
rgltr-max-voltage = <0 1208000 888000>;
rgltr-load-current = <0 54000 96400>;
clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&clock_camcc CAM_CC_CSIPHY2_CLK>,
<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>;
clock-names = "cphy_rx_clk_src",
"csiphy2_clk",
"csi2phytimer_clk_src",
"csi2phytimer_clk";
src-clock-name = "csi2phytimer_clk_src";
clock-cntl-level = "nominal";
clock-rates =
<400000000 0 300000000 0>;
status = "ok";
};
cam_csiphy3: qcom,csiphy3 {
cell-index = <3>;
compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy";
reg = <0xac70000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0x70000>;
interrupts = <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csiphy3";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
csi-vdd-1p2-supply = <&pm8350_l6>;
csi-vdd-0p9-supply = <&pm8350_l5>;
rgltr-cntrl-support;
rgltr-enable-sync = <1>;
regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9";
rgltr-min-voltage = <0 1200000 880000>;
rgltr-max-voltage = <0 1208000 888000>;
rgltr-load-current = <0 54000 96400>;
clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&clock_camcc CAM_CC_CSIPHY3_CLK>,
<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>;
clock-names = "cphy_rx_clk_src",
"csiphy3_clk",
"csi3phytimer_clk_src",
"csi3phytimer_clk";
src-clock-name = "csi3phytimer_clk_src";
clock-cntl-level = "nominal";
clock-rates =
<400000000 0 300000000 0>;
status = "ok";
};
cam_csiphy4: qcom,csiphy4 {
cell-index = <4>;
compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy";
reg = <0xac72000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0x72000>;
interrupts = <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csiphy4";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
csi-vdd-1p2-supply = <&pm8350_l6>;
csi-vdd-0p9-supply = <&pm8350_l5>;
rgltr-cntrl-support;
rgltr-enable-sync = <1>;
regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9";
rgltr-min-voltage = <0 1200000 880000>;
rgltr-max-voltage = <0 1208000 888000>;
rgltr-load-current = <0 54000 96400>;
clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&clock_camcc CAM_CC_CSIPHY4_CLK>,
<&clock_camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSI4PHYTIMER_CLK>;
clock-names = "cphy_rx_clk_src",
"csiphy4_clk",
"csi4phytimer_clk_src",
"csi4phytimer_clk";
src-clock-name = "csi4phytimer_clk_src";
clock-cntl-level = "nominal";
clock-rates =
<400000000 0 300000000 0>;
status = "ok";
};
cam_csiphy5: qcom,csiphy5 {
cell-index = <5>;
compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy";
reg = <0xac74000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0x74000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csiphy5";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
csi-vdd-1p2-supply = <&pm8350_l6>;
csi-vdd-0p9-supply = <&pm8350_l5>;
rgltr-cntrl-support;
rgltr-enable-sync = <1>;
regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9";
rgltr-min-voltage = <0 1200000 880000>;
rgltr-max-voltage = <0 1208000 888000>;
rgltr-load-current = <0 54000 96400>;
clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&clock_camcc CAM_CC_CSIPHY5_CLK>,
<&clock_camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSI5PHYTIMER_CLK>;
clock-names = "cphy_rx_clk_src",
"csiphy5_clk",
"csi5phytimer_clk_src",
"csi5phytimer_clk";
src-clock-name = "csi5phytimer_clk_src";
clock-cntl-level = "nominal";
clock-rates =
<400000000 0 300000000 0>;
status = "ok";
};
cam_cci0: qcom,cci0 {
cell-index = <0>;
compatible = "qcom,cci", "simple-bus";
reg = <0xac4f000 0x1000>;
reg-names = "cci";
reg-cam-base = <0x4f000>;
interrupt-names = "cci";
interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
status = "ok";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
regulator-names = "gdscr";
clocks = <&clock_camcc CAM_CC_CCI_0_CLK_SRC>,
<&clock_camcc CAM_CC_CCI_0_CLK>;
clock-names = "cci_0_clk_src",
"cci_0_clk";
src-clock-name = "cci_0_clk_src";
clock-cntl-level = "lowsvs";
clock-rates = <37500000 0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cci0_active &cci1_active>;
pinctrl-1 = <&cci0_suspend &cci1_suspend>;
gpios = <&tlmm 107 0>,
<&tlmm 108 0>,
<&tlmm 109 0>,
<&tlmm 110 0>;
gpio-req-tbl-num = <0 1 2 3>;
gpio-req-tbl-flags = <1 1 1 1>;
gpio-req-tbl-label = "CCI_I2C_DATA0",
"CCI_I2C_CLK0",
"CCI_I2C_DATA1",
"CCI_I2C_CLK1";
i2c_freq_100Khz_cci0: qcom,i2c_standard_mode {
hw-thigh = <201>;
hw-tlow = <174>;
hw-tsu-sto = <204>;
hw-tsu-sta = <231>;
hw-thd-dat = <22>;
hw-thd-sta = <162>;
hw-tbuf = <227>;
hw-scl-stretch-en = <0>;
hw-trdhld = <6>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_400Khz_cci0: qcom,i2c_fast_mode {
hw-thigh = <38>;
hw-tlow = <56>;
hw-tsu-sto = <40>;
hw-tsu-sta = <40>;
hw-thd-dat = <22>;
hw-thd-sta = <35>;
hw-tbuf = <62>;
hw-scl-stretch-en = <0>;
hw-trdhld = <6>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_custom_cci0: qcom,i2c_custom_mode {
hw-thigh = <38>;
hw-tlow = <56>;
hw-tsu-sto = <40>;
hw-tsu-sta = <40>;
hw-thd-dat = <22>;
hw-thd-sta = <35>;
hw-tbuf = <62>;
hw-scl-stretch-en = <1>;
hw-trdhld = <6>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode {
hw-thigh = <16>;
hw-tlow = <22>;
hw-tsu-sto = <17>;
hw-tsu-sta = <18>;
hw-thd-dat = <16>;
hw-thd-sta = <15>;
hw-tbuf = <24>;
hw-scl-stretch-en = <0>;
hw-trdhld = <3>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
};
cam_cci1: qcom,cci1 {
cell-index = <1>;
compatible = "qcom,cci", "simple-bus";
reg = <0xac50000 0x1000>;
reg-names = "cci";
reg-cam-base = <0x50000>;
interrupt-names = "cci";
interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
status = "ok";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
regulator-names = "gdscr";
clocks = <&clock_camcc CAM_CC_CCI_1_CLK_SRC>,
<&clock_camcc CAM_CC_CCI_1_CLK>;
clock-names = "cci_1_clk_src",
"cci_1_clk";
src-clock-name = "cci_1_clk_src";
clock-cntl-level = "lowsvs";
clock-rates = <37500000 0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cci2_active &cci3_active>;
pinctrl-1 = <&cci2_suspend &cci3_suspend>;
gpios = <&tlmm 111 0>,
<&tlmm 112 0>,
<&tlmm 113 0>,
<&tlmm 114 0>;
gpio-req-tbl-num = <0 1 2 3>;
gpio-req-tbl-flags = <1 1 1 1>;
gpio-req-tbl-label = "CCI_I2C_DATA2",
"CCI_I2C_CLK2",
"CCI_I2C_DATA3",
"CCI_I2C_CLK3";
i2c_freq_100Khz_cci1: qcom,i2c_standard_mode {
hw-thigh = <201>;
hw-tlow = <174>;
hw-tsu-sto = <204>;
hw-tsu-sta = <231>;
hw-thd-dat = <22>;
hw-thd-sta = <162>;
hw-tbuf = <227>;
hw-scl-stretch-en = <0>;
hw-trdhld = <6>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_400Khz_cci1: qcom,i2c_fast_mode {
hw-thigh = <38>;
hw-tlow = <56>;
hw-tsu-sto = <40>;
hw-tsu-sta = <40>;
hw-thd-dat = <22>;
hw-thd-sta = <35>;
hw-tbuf = <62>;
hw-scl-stretch-en = <0>;
hw-trdhld = <6>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_custom_cci1: qcom,i2c_custom_mode {
hw-thigh = <38>;
hw-tlow = <56>;
hw-tsu-sto = <40>;
hw-tsu-sta = <40>;
hw-thd-dat = <22>;
hw-thd-sta = <35>;
hw-tbuf = <62>;
hw-scl-stretch-en = <1>;
hw-trdhld = <6>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode {
hw-thigh = <16>;
hw-tlow = <22>;
hw-tsu-sto = <17>;
hw-tsu-sta = <18>;
hw-thd-dat = <16>;
hw-thd-sta = <15>;
hw-tbuf = <24>;
hw-scl-stretch-en = <0>;
hw-trdhld = <3>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
};
qcom,cam_smmu {
compatible = "qcom,msm-cam-smmu", "simple-bus";
status = "ok";
msm_cam_smmu_ife {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x800 0x440>,
<&apps_smmu 0x840 0x440>,
<&apps_smmu 0xC00 0x440>,
<&apps_smmu 0xC40 0x440>;
qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>;
dma-coherent-hint-cached;
cam-smmu-label = "ife", "ife-cdm";
multiple-client-devices;
ife_iova_mem_map: iova-mem-map {
/* IO region is approximately 4.0 GB */
iova-mem-region-io {
iova-region-name = "io";
/* 1 MB pad for start */
iova-region-start = <0x100000>;
/* 1 MB pad for end */
iova-region-len = <0xffe00000>;
iova-region-id = <0x3>;
status = "ok";
};
};
};
msm_cam_smmu_jpeg {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x2040 0x400>,
<&apps_smmu 0x2440 0x400>;
cam-smmu-label = "jpeg";
qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>;
dma-coherent-hint-cached;
jpeg_iova_mem_map: iova-mem-map {
/* IO region is approximately 4.0 GB */
iova-mem-region-io {
iova-region-name = "io";
/* 1 MB pad for start */
iova-region-start = <0x100000>;
/* 1 MB pad for end */
iova-region-len = <0xffe00000>;
iova-region-id = <0x3>;
status = "ok";
};
};
};
msm_cam_icp_fw {
compatible = "qcom,msm-cam-smmu-fw-dev";
label="icp";
memory-region = <&pil_camera_mem>;
};
msm_cam_smmu_icp {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x20E2 0x400>,
<&apps_smmu 0x24E2 0x400>,
<&apps_smmu 0x2000 0x400>,
<&apps_smmu 0x2400 0x400>,
<&apps_smmu 0x2060 0x400>,
<&apps_smmu 0x2460 0x400>,
<&apps_smmu 0x2020 0x400>,
<&apps_smmu 0x2420 0x400>;
cam-smmu-label = "icp";
qcom,iommu-dma-addr-pool = <0x10c00000 0xee300000>;
iova-region-discard = <0xdff00000 0x300000>;
dma-coherent-hint-cached;
icp_iova_mem_map: iova-mem-map {
iova-mem-region-firmware {
/* Firmware region is 5MB */
iova-region-name = "firmware";
iova-region-start = <0x0>;
iova-region-len = <0x500000>;
iova-region-id = <0x0>;
status = "ok";
};
iova-mem-region-shared {
/* Shared region is 261MB long */
iova-region-name = "shared";
iova-region-start = <0x500000>;
iova-region-len = <0x10500000>;
iova-region-id = <0x1>;
status = "ok";
};
iova-mem-region-secondary-heap {
/* Secondary heap region is 1MB long */
iova-region-name = "secheap";
iova-region-start = <0x10a00000>;
iova-region-len = <0x100000>;
iova-region-id = <0x4>;
status = "ok";
};
iova-mem-region-io {
/* IO region is approximately 3.7 GB */
iova-region-name = "io";
iova-region-start = <0x10c00000>;
iova-region-len = <0xee300000>;
iova-region-id = <0x3>;
iova-region-discard = <0xdff00000 0x300000>;
status = "ok";
};
iova-mem-qdss-region {
/* QDSS region is appropriate 1MB */
iova-region-name = "qdss";
iova-region-start = <0x10b00000>;
iova-region-len = <0x100000>;
iova-region-id = <0x5>;
qdss-phy-addr = <0x16790000>;
status = "ok";
};
};
};
msm_cam_smmu_cpas_cdm {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x20C0 0x400>,
<&apps_smmu 0x24C0 0x400>;
cam-smmu-label = "cpas-cdm";
qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>;
dma-coherent-hint-cached;
cpas_cdm_iova_mem_map: iova-mem-map {
iova-mem-region-io {
/* IO region is approximately 4.0 GB */
iova-region-name = "io";
/* 1 MB pad for start */
iova-region-start = <0x100000>;
/* 1 MB pad for end */
iova-region-len = <0xffe00000>;
iova-region-id = <0x3>;
status = "ok";
};
};
};
msm_cam_smmu_secure {
compatible = "qcom,msm-cam-smmu-cb";
cam-smmu-label = "cam-secure";
qcom,secure-cb;
};
};
qcom,cam-cpas {
cell-index = <0>;
compatible = "qcom,cam-cpas";
label = "cpas";
arch-compat = "cpas_top";
status = "ok";
reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh";
reg = <0xac40000 0x1000>,
<0xac42000 0x8000>,
<0xbbf0000 0x1F00>;
reg-cam-base = <0x40000 0x42000 0x0BBF0000>;
interrupt-names = "cpas_camnoc";
interrupts = <GIC_SPI 459 IRQ_TYPE_EDGE_RISING>;
camnoc-axi-min-ib-bw = <3000000000>;
regulator-names = "camss-vdd";
camss-vdd-supply = <&cam_cc_titan_top_gdsc>;
clock-names =
"gcc_ahb_clk",
"gcc_axi_hf_clk",
"gcc_axi_sf_clk",
"slow_ahb_clk_src",
"cpas_ahb_clk",
"cpas_core_ahb_clk",
"camnoc_axi_clk_src",
"camnoc_axi_clk",
"cpas_fast_ahb_clk_src";
clocks =
<&clock_gcc GCC_CAMERA_AHB_CLK>,
<&clock_gcc GCC_CAMERA_HF_AXI_CLK>,
<&clock_gcc GCC_CAMERA_SF_AXI_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&clock_camcc CAM_CC_CPAS_AHB_CLK>,
<&clock_camcc CAM_CC_CORE_AHB_CLK>,
<&clock_camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
<&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>;
src-clock-name = "camnoc_axi_clk_src";
clock-rates =
<0 0 0 0 0 0 0 0 0>,
<0 0 0 80000000 0 0 300000000 0 100000000>,
<0 0 0 80000000 0 0 400000000 0 200000000>,
<0 0 0 80000000 0 0 400000000 0 300000000>,
<0 0 0 80000000 0 0 400000000 0 400000000>,
<0 0 0 80000000 0 0 400000000 0 400000000>,
<0 0 0 80000000 0 0 480000000 0 400000000>;
clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1",
"nominal", "nominal_l1", "turbo";
control-camnoc-axi-clk;
camnoc-bus-width = <32>;
camnoc-axi-clk-bw-margin-perc = <20>;
interconnect-names = "cam_ahb";
interconnects =<&gem_noc MASTER_APPSS_PROC
&config_noc SLAVE_CAMERA_CFG>;
rpmh-bcm-info = <12 0x4 0x800 0 4>;
cam-ahb-num-cases = <8>;
cam-ahb-bw-KBps =
<0 0>, <0 76800>, <0 76800>, <0 150000>, <0 150000>,
<0 300000>, <0 300000>, <0 300000>;
vdd-corners = <RPMH_REGULATOR_LEVEL_RETENTION
RPMH_REGULATOR_LEVEL_MIN_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_SVS
RPMH_REGULATOR_LEVEL_SVS_L1
RPMH_REGULATOR_LEVEL_NOM
RPMH_REGULATOR_LEVEL_NOM_L1
RPMH_REGULATOR_LEVEL_NOM_L2
RPMH_REGULATOR_LEVEL_TURBO
RPMH_REGULATOR_LEVEL_TURBO_L1>;
vdd-corner-ahb-mapping = "suspend", "lowsvs",
"lowsvs", "svs", "svs_l1",
"nominal", "nominal", "nominal",
"turbo", "turbo";
client-id-based;
client-names =
"csiphy0", "csiphy1", "csiphy2", "csiphy3",
"csiphy4", "csiphy5", "cci0", "cci1",
"csid0", "csid1", "csid2", "csid3",
"csid4", "ife0", "ife1", "ife2", "ife3", "ife4",
"custom0", "custom1", "ipe0", "cam-cdm-intf0",
"ife-cdm0", "ife-cdm1", "ife-cdm2", "cpas-cdm0",
"bps0", "icp0", "jpeg-dma0", "jpeg-enc0",
"tpg0", "tpg1";
camera-bus-nodes {
level3-nodes {
level-index = <3>;
level3_rt0_rd_wr_sum: level3-rt0-rd-wr-sum {
cell-index = <0>;
node-name = "level3-rt0-rd-wr-sum";
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
ib-bw-voting-needed;
qcom,axi-port-mnoc {
interconnect-names = "cam_hf_0";
interconnects =
<&mmss_noc MASTER_CAMNOC_HF
&mc_virt SLAVE_EBI1>;
};
};
level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum {
cell-index = <1>;
node-name = "level3-nrt0-rd-wr-sum";
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
qcom,axi-port-mnoc {
interconnect-names = "cam_sf_0";
interconnects =
<&mmss_noc MASTER_CAMNOC_SF
&mc_virt SLAVE_EBI1>;
};
};
level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum {
cell-index = <2>;
node-name = "level3-nrt1-rd-wr-sum";
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
qcom,axi-port-mnoc {
interconnect-names =
"cam_sf_icp";
interconnects =
<&mmss_noc MASTER_CAMNOC_ICP
&mc_virt SLAVE_EBI1>;
};
};
};
level2-nodes {
level-index = <2>;
camnoc-max-needed;
level2_rt0_wr: level2-rt0-wr {
cell-index = <3>;
node-name = "level2-rt0-wr";
parent-node = <&level3_rt0_rd_wr_sum>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
};
level2_rt0_rd: level2-rt0-rd {
cell-index = <4>;
node-name = "level2-rt0-rd";
parent-node = <&level3_rt0_rd_wr_sum>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
};
level2_nrt0_wr: level2-nrt0-wr {
cell-index = <5>;
node-name = "level2-nrt0-wr";
parent-node = <&level3_nrt0_rd_wr_sum>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
};
level2_nrt0_rd: level2-nrt0-rd {
cell-index = <6>;
node-name = "level2-nrt0-rd";
parent-node = <&level3_nrt0_rd_wr_sum>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
};
level2_nrt1_rd: level2-nrt1-rd {
cell-index = <7>;
node-name = "level2-nrt1-rd";
parent-node = <&level3_nrt1_rd_wr_sum>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
bus-width-factor = <4>;
};
};
level1-nodes {
level-index = <1>;
camnoc-max-needed;
level1_rt0_wr0: level1-rt0-wr0 {
cell-index = <8>;
node-name = "level1-rt0-wr0";
parent-node = <&level2_rt0_wr>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
};
level1_rt0_wr1: level1-rt0-wr1 {
cell-index = <9>;
node-name = "level1-rt0-wr1";
parent-node = <&level2_rt0_wr>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
};
level1_rt0_wr2: level1-rt0-wr2 {
cell-index = <10>;
node-name = "level1-rt0-wr2";
parent-node = <&level2_rt0_wr>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
};
level1_rt0_rd0: level1-rt0-rd0 {
cell-index = <11>;
node-name = "level1-rt0-rd0";
parent-node = <&level2_rt0_rd>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
};
level1_rt0_wr3: level1-rt0-wr3 {
cell-index = <12>;
node-name = "level1-rt0-wr3";
parent-node = <&level2_rt0_wr>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
};
level1_rt0_wr4: level1-rt0-wr4 {
cell-index = <13>;
node-name = "level1-rt0-wr4";
parent-node = <&level2_rt0_wr>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
};
level1_nrt0_wr0: level1-nrt0-wr0 {
cell-index = <14>;
node-name = "level1-nrt0-wr0";
parent-node = <&level2_nrt0_wr>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
};
level1_nrt0_rd0: level1-nrt0-rd0 {
cell-index = <15>;
node-name = "level1-nrt0-rd0";
parent-node = <&level2_nrt0_rd>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
};
level1_nrt0_wr1: level1-nrt0-wr1 {
cell-index = <16>;
node-name = "level1-nrt0-wr1";
parent-node = <&level2_nrt0_wr>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
};
level1_nrt0_rd1: level1-nrt0-rd1 {
cell-index = <17>;
node-name = "level1-nrt0-rd2";
parent-node = <&level2_nrt0_rd>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
};
};
level0-nodes {
level-index = <0>;
ife2_ubwc_stats_wr: ife2-ubwc-stats-wr {
cell-index = <18>;
node-name = "ife2-ubwc-stats-wr";
client-name = "ife2";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_UBWC_STATS>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IFE_VID
CAM_CPAS_PATH_DATA_IFE_DISP
CAM_CPAS_PATH_DATA_IFE_STATS>;
parent-node = <&level1_rt0_wr0>;
};
ife0_ubwc_stats_wr: ife0-ubwc-stats-wr {
cell-index = <19>;
node-name = "ife0-ubwc-stats-wr";
client-name = "ife0";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_UBWC_STATS>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IFE_VID
CAM_CPAS_PATH_DATA_IFE_DISP
CAM_CPAS_PATH_DATA_IFE_STATS>;
parent-node = <&level1_rt0_wr1>;
};
ife1_ubwc_stats_wr: ife1-ubwc-stats-wr {
cell-index = <20>;
node-name = "ife1-ubwc-stats-wr";
client-name = "ife1";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_UBWC_STATS>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IFE_VID
CAM_CPAS_PATH_DATA_IFE_DISP
CAM_CPAS_PATH_DATA_IFE_STATS>;
parent-node = <&level1_rt0_wr1>;
};
ife0_linear_pdaf_wr: ife0-linear-pdaf-wr {
cell-index = <21>;
node-name = "ife0-linear-pdaf-wr";
client-name = "ife0";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_LINEAR_PDAF>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IFE_LINEAR
CAM_CPAS_PATH_DATA_IFE_PDAF>;
parent-node = <&level1_rt0_wr2>;
};
ife1_linear_pdaf_wr: ife1-linear-pdaf-wr {
cell-index = <22>;
node-name = "ife1-linear-pdaf-wr";
client-name = "ife1";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_LINEAR_PDAF>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IFE_LINEAR
CAM_CPAS_PATH_DATA_IFE_PDAF>;
parent-node = <&level1_rt0_wr2>;
};
ife2_linear_pdaf_wr: ife2-linear-pdaf-wr {
cell-index = <23>;
node-name = "ife2-linear-pdaf-wr";
client-name = "ife2";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_LINEAR_PDAF>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IFE_LINEAR
CAM_CPAS_PATH_DATA_IFE_PDAF>;
parent-node = <&level1_rt0_wr2>;
};
ife3_rdi_all_wr: ife3-rdi-all-wr {
cell-index = <24>;
node-name = "ife3-rdi-all-wr";
client-name = "ife3";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IFE_RDI0
CAM_CPAS_PATH_DATA_IFE_RDI1
CAM_CPAS_PATH_DATA_IFE_RDI2
CAM_CPAS_PATH_DATA_IFE_RDI3>;
parent-node = <&level1_rt0_wr2>;
};
ife0_rdi_all_rd: ife0-rdi-all-rd {
cell-index = <25>;
node-name = "ife0-rdi-all-rd";
client-name = "ife0";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_READ>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IFE_RDI0
CAM_CPAS_PATH_DATA_IFE_RDI1
CAM_CPAS_PATH_DATA_IFE_RDI2
CAM_CPAS_PATH_DATA_IFE_RDI3>;
parent-node = <&level1_rt0_rd0>;
};
ife1_rdi_all_rd: ife1-rdi-all-rd {
cell-index = <26>;
node-name = "ife1-rdi-all-rd";
client-name = "ife1";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_READ>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IFE_RDI0
CAM_CPAS_PATH_DATA_IFE_RDI1
CAM_CPAS_PATH_DATA_IFE_RDI2
CAM_CPAS_PATH_DATA_IFE_RDI3>;
parent-node = <&level1_rt0_rd0>;
};
ife2_rdi_all_rd: ife2-rdi-all-rd {
cell-index = <27>;
node-name = "ife2-rdi-all-rd";
client-name = "ife2";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_READ>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IFE_RDI0
CAM_CPAS_PATH_DATA_IFE_RDI1
CAM_CPAS_PATH_DATA_IFE_RDI2
CAM_CPAS_PATH_DATA_IFE_RDI3>;
parent-node = <&level1_rt0_rd0>;
};
custom0_rd: custom0-rd {
cell-index = <28>;
node-name = "custom0-rd";
client-name = "custom0";
traffic-data =
<CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_READ>;
parent-node = <&level1_rt0_rd0>;
};
custom1_rd: custom1-rd {
cell-index = <29>;
node-name = "custom1-rd";
client-name = "custom1";
traffic-data =
<CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_READ>;
parent-node = <&level1_rt0_rd0>;
};
ife2_rdi_pixel_raw_wr: ife2-rdi-pixel-raw-wr {
cell-index = <30>;
node-name = "ife2-rdi-pixel-raw-wr";
client-name = "ife2";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IFE_RDI0
CAM_CPAS_PATH_DATA_IFE_RDI1
CAM_CPAS_PATH_DATA_IFE_RDI2
CAM_CPAS_PATH_DATA_IFE_PIXEL_RAW>;
parent-node = <&level1_rt0_wr3>;
};
ife4_rdi_all_wr: ife4-rdi-all-wr {
cell-index = <31>;
node-name = "ife4-rdi-all-wr";
client-name = "ife4";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IFE_RDI0
CAM_CPAS_PATH_DATA_IFE_RDI1
CAM_CPAS_PATH_DATA_IFE_RDI2
CAM_CPAS_PATH_DATA_IFE_RDI3>;