diff --git a/openlane/wishbone_sram/config.json b/openlane/wishbone_sram/config.json
index e6cc1f2..9701cbd 100644
--- a/openlane/wishbone_sram/config.json
+++ b/openlane/wishbone_sram/config.json
@@ -3,10 +3,9 @@
     "VERILOG_FILES": [
         "dir::../../verilog/rtl/wishbone_sram.v",
         "dir::../../ip/EFSRAM_01024x032_008_18/hdl/ram_controller.v",
-        "dir::../../ip/EFSRAM_01024x032_008_18/hdl/SRAM_1024x32.v",
         "dir::../../ip/EFSRAM_01024x032_008_18/hdl/EFSRAM_1024x32_wrapper.v"
     ],
-    "VERILOG_DEFINES": ["USE_PG_PIN", "PnR"],
+    "SYNTH_DEFINES": ["USE_PG_PIN", "PnR"],
     "CLOCK_PERIOD": 25,
     "CLOCK_PORT": "wb_clk_i",
     "FP_SIZING": "absolute",
@@ -19,16 +18,15 @@
     "PNR_SDC_FILE": "dir::base.sdc",
     "SIGNOFF_SDC_FILE": "dir::base.sdc",
     "RUN_IRDROP_REPORT": false,
-    "ERROR_ON_LINTER_ERRORS": false,
     "QUIT_ON_LINTER_ERRORS": false,
-    "PL_TARGET_DENSITY_PCT": 15,
+    "PL_TARGET_DENSITY": 0.15,
     "PL_TIME_DRIVEN": false,
     "PL_ROUTABILITY_DRIVEN": true,
     "GRT_ALLOW_CONGESTION": true,
     "GRT_ADJUSTMENT": 0,
-    "RUN_POST_GRT_DESIGN_REPAIR": true,
-    "RUN_POST_GRT_RESIZER_TIMING": true,
-    "RUN_ANTENNA_REPAIR": false,
+    "//RUN_POST_GRT_DESIGN_REPAIR": true,
+    "//RUN_POST_GRT_RESIZER_TIMING": true,
+    "GRT_REPAIR_ANTENNAS": false,
     "MAGIC_DRC_USE_GDS": true,
     "QUIT_ON_MAGIC_DRC": false,
     "QUIT_ON_KLAYOUT_DRC": false,
@@ -63,19 +61,22 @@
     "FP_PDN_HSPACING": 10,
     "FP_PDN_VPITCH": 50,
     "FP_PDN_HPITCH": 50,
-    "PDN_MACRO_CONNECTIONS": [
-        "my_4k_sram vpwra vgnd  VPWR VGND",
-        "my_4k_sram vpb   vnb   VPWR VGND",
-        "my_4k_sram vpwrp vgnd  VPWR VGND",
-        "my_4k_sram vpwrm vgnd  VPWR VGND"
+    "FP_PDN_MACRO_HOOKS": [
+        "SRAM_0 vpwra vgnd  vccd1 vssd1",
+        "SRAM_0 vpb   vnb   vccd1 vssd1",
+        "SRAM_0 vpwrp vgnd  vccd1 vssd1",
+        "SRAM_0 vpwrm vgnd  vccd1 vssd1"
     ],
-    "QUIT_ON_PDN_VIOLATIONS": false,
-    "VERILOG_POWER_DEFINE": "USE_POWER_PINS",
-    "ROUTING_OBSTRUCTIONS": [
+    "//SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
+    "GRT_OBS": [
         "met1 0 40 314 435",
         "met2 0 40 314 435",
         "met3 0 40 314 435",
         "met4 0 40 314 435",
         "met5 0 40 314 435"
-    ]
+    ],
+
+    "////FP_PDN_CHECK_NODES": true,
+    "////QUIT_ON_PDN_VIOLATIONS": false,
+    "////FP_PDN_ENABLE_RAILS": false
 }
diff --git a/openlane/wishbone_sram/macro.cfg b/openlane/wishbone_sram/macro.cfg
index 42cc96d..741dbc9 100644
--- a/openlane/wishbone_sram/macro.cfg
+++ b/openlane/wishbone_sram/macro.cfg
@@ -1 +1 @@
-my_4k_sram 10.1 40 W
+SRAM_0 10.1 40 W
diff --git a/openlane/wishbone_sram/pin_order.cfg b/openlane/wishbone_sram/pin_order.cfg
index 6dac9a2..b3f6b26 100644
--- a/openlane/wishbone_sram/pin_order.cfg
+++ b/openlane/wishbone_sram/pin_order.cfg
@@ -1,6 +1,7 @@
 #BUS_SORT
 
 #S
+sram_selected
 $20
 wb_.*
 wbs_.*
diff --git a/verilog/rtl/wishbone_sram.v b/verilog/rtl/wishbone_sram.v
index 8ee7064..56b692d 100644
--- a/verilog/rtl/wishbone_sram.v
+++ b/verilog/rtl/wishbone_sram.v
@@ -23,9 +23,9 @@
 
 // This could be used as the basis for making a more-sophisticated Wishbone mux.
 
-`ifdef USE_POWER_PINS
-  `define USE_PG_PIN 
-`endif
+// `ifdef USE_POWER_PINS
+//   `define USE_PG_PIN 
+// `endif
 
 module wishbone_sram (
 `ifdef USE_POWER_PINS
@@ -69,14 +69,20 @@ module wishbone_sram (
   // "*_wbs_cycle" inputs using an "always @(*)" block with a case
   // statement sensitive to various bit patterns on wbs_adr_i.
 
-  // Instantiate the soft (Verilog) Efabless-supplied Wishbone wrapper
-  // that is provided as one of the interfaces to the SRAM hard IP block.
-  // This in turn includes a WB RAM controller & actual SRAM IP.
-  SRAM_1024x32 my_4k_sram (
-  `ifdef USE_POWER_PINS
-    .VPWR       (vccd1),
-    .VGND       (vssd1),
-  `endif
+  // The code below is MOSTLY as-is from the Efabless
+  // ip/EFSRAM_01024x32_008_18/hdl/SRAM_1024x32.v reference design...
+
+  // RAM ports that connect between ram_controller and SRAM_0:
+  wire [31:0]   DO;
+  wire [31:0]   DI;
+  wire [31:0]   BEN;
+  wire  [9:0]   AD;
+  wire          EN;
+  wire          R_WB;
+  wire          CLKin;
+
+  // Wishbone-to-SRAM controller interface:
+  ram_controller #(.AW(10)) ram_controller(
     // These are "gated" (or muxed) Wishbone signals specifically
     // for THIS device on the Wishbone bus:
     .wbs_cyc_i  (sram_wbs_cycle),
@@ -90,7 +96,46 @@ module wishbone_sram (
     .wbs_we_i   (wbs_we_i),
     .wbs_sel_i  (wbs_sel_i),
     .wbs_dat_i  (wbs_dat_i),
-    .wbs_adr_i  (wbs_adr_i)
+    .wbs_adr_i  (wbs_adr_i),
+    // These are the signals that bridge to the SRAM_0 macro:
+    .DO         (DO),
+    .DI         (DI),
+    .BEN        (BEN),
+    .AD         (AD),
+    .EN         (EN),
+    .R_WB       (R_WB),
+    .CLKin      (CLKin)
+  );
+
+  // Wrapper for the EFSRAM hard IP macro, instantiated as "SRAM_0":
+  EFSRAM_1024x32_wrapper SRAM_0 (
+  `ifdef USE_POWER_PINS
+    .vgnd       (vssd1),
+    .vnb        (vssd1),
+    .vpb        (vccd1),
+    .vpwra      (vccd1),
+    .vpwrm      (vccd1),
+    .vpwrp      (vccd1),
+  `endif
+    .vpwrac     (1'b1),
+    .vpwrpc     (1'b1),
+    // access ports
+    .DO         (DO),
+    .DI         (DI),
+    .BEN        (BEN),
+    .AD         (AD),
+    .EN         (EN),
+    .R_WB       (R_WB),
+    .CLKin      (CLKin),
+    // scan ports
+    .TM         (1'b0),
+    .SM         (1'b0),
+    .ScanInCC   (1'b0),
+    .ScanInDL   (1'b0),
+    .ScanInDR   (1'b0),
+    .ScanOutCC  (),
+    .WLBI       (1'b0),
+    .WLOFF      (1'b0)
   );
 
 endmodule