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.metrics.json
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.metrics.json
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{
"variables": {
"RISCV": "/mux-flow/tools/riscv",
"LM_LICENSE_FILE": "2700@license-1",
"IMPERAS_QUEUE_LICENSE" : "1"
},
"builds": {
"list": [
{
"name": "uvmt_cv32",
"image": "cv32-simulation-tools:20200316.10.0",
"cmd": "cd cv32/sim/uvmt_cv32; make corev-dv SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work; make comp SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make corev-dv SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work; make comp SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work WAVES=1"
}
]
},
"regressions": [
{
"name": "cv32_ci_check_regression",
"description": "Commit sanity for CV32",
"verbose": "true",
"tests": {
"resultsDir": "/mux-flow/build/results",
"builds": ["uvmt_cv32"],
"list": [
{
"name": "uvm_hello_world_test",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make hello-world SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make hello-world SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=hello-world.vcd",
"metricsFile": "hello-world/metrics.db",
"wavesFile" : "hello-world/hello-world.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "Static riscv-dv ebreak test",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=riscv_ebreak_test_0 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=riscv_ebreak_test_0 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=riscv_ebreak_test_0.vcd",
"metricsFile": "riscv_ebreak_test_0/metrics.db",
"wavesFile" : "riscv_ebreak_test_0/riscv_ebreak_test_0.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "Static riscv-dv arithmetic test 0",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=riscv_arithmetic_basic_test_0 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=riscv_arithmetic_basic_test_0 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=riscv_arithmetic_basic_test_0.vcd",
"metricsFile": "riscv_arithmetic_basic_test_0/metrics.db",
"wavesFile" : "riscv_arithmetic_basic_test_0/riscv_arithmetic_basic_test_0.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "Generated riscv-dv arithmetic test 0",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_arithmetic_base_test_0 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_arithmetic_base_test_0 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=corev_arithmetic_base_test_0.vcd",
"metricsFile": "corev_arithmetic_base_test_0/metrics.db",
"wavesFile" : "corev_arithmetic_base_test_0/corev_arithmetic_base_test_0.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "Generated riscv-dv arithmetic test 1",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_arithmetic_base_test_1 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_arithmetic_base_test_1 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=corev_arithmetic_base_test_1.vcd",
"metricsFile": "corev_arithmetic_base_test_1/metrics.db",
"wavesFile" : "corev_arithmetic_base_test_1/corev_arithmetic_base_test_1.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "Generated riscv-dv random instruction test 0",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_rand_instr_test_0 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_rand_instr_test_0 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=corev_rand_instr_test_0.vcd",
"metricsFile": "corev_rand_instr_test_0/metrics.db",
"wavesFile" : "corev_rand_instr_test_0/corev_rand_instr_test_0.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "Generated riscv-dv random instruction test 1",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_rand_instr_test_1 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_rand_instr_test_1 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=corev_rand_instr_test_1.vcd",
"metricsFile": "corev_rand_instr_test_1/metrics.db",
"wavesFile" : "corev_rand_instr_test_1/corev_rand_instr_test_1.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "Generated riscv-dv jump stress test 0",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_jump_stress_test_0 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_jump_stress_test_0 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=corev_jump_stress_test_0.vcd",
"metricsFile": "corev_jump_stress_test_0/metrics.db",
"wavesFile" : "corev_jump_stress_test_0/corev_jump_stress_test_0.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "Generated riscv-dv jump stress test 1",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_jump_stress_test_1 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_jump_stress_test_1 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=corev_jump_stress_test_1.vcd",
"metricsFile": "corev_jump_stress_test_1/metrics.db",
"wavesFile" : "corev_jump_stress_test_1/corev_jump_stress_test_1.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "illegal-riscv-tests",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=illegal SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=illegal SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=illegal.vcd",
"metricsFile": "illegal/metrics.db",
"wavesFile" : "illegal/illegal.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
}
]
}
},
{
"name": "cv32_full_regression",
"description": "Full regression (all tests) for CV32",
"verbose": "true",
"tests": {
"resultsDir": "/mux-flow/build/results",
"builds": ["uvmt_cv32"],
"list": [
{
"name": "uvm_hello_world_test",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make hello-world SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make hello-world SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=hello-world.vcd",
"metricsFile": "hello-world/metrics.db",
"wavesFile" : "hello-world/hello-world.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "Static riscv-dv ebreak test",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=riscv_ebreak_test_0 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=riscv_ebreak_test_0 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=riscv_ebreak_test_0.vcd",
"metricsFile": "riscv_ebreak_test_0/metrics.db",
"wavesFile" : "riscv_ebreak_test_0/riscv_ebreak_test_0.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "Static riscv-dv arithmetic test 0",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=riscv_arithmetic_basic_test_0 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=riscv_arithmetic_basic_test_0 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=riscv_arithmetic_basic_test_0.vcd",
"metricsFile": "riscv_arithmetic_basic_test_0/metrics.db",
"wavesFile" : "riscv_arithmetic_basic_test_0/riscv_arithmetic_basic_test_0.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "Static riscv-dv arithmetic test 1",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=riscv_arithmetic_basic_test_1 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=riscv_arithmetic_basic_test_1 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=riscv_arithmetic_basic_test_1.vcd",
"metricsFile": "riscv_arithmetic_basic_test_1/metrics.db",
"wavesFile" : "riscv_arithmetic_basic_test_1/riscv_arithmetic_basic_test_1.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "Generated riscv-dv arithmetic test 0",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_arithmetic_base_test_0 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_arithmetic_base_test_0 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=corev_arithmetic_base_test_0.vcd",
"metricsFile": "corev_arithmetic_base_test_0/metrics.db",
"wavesFile" : "corev_arithmetic_base_test_0/corev_arithmetic_base_test_0.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "Generated riscv-dv arithmetic test 1",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_arithmetic_base_test_1 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_arithmetic_base_test_1 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=corev_arithmetic_base_test_1.vcd",
"metricsFile": "corev_arithmetic_base_test_1/metrics.db",
"wavesFile" : "corev_arithmetic_base_test_1/corev_arithmetic_base_test_1.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "Generated riscv-dv random instruction test 0",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_rand_instr_test_0 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_rand_instr_test_0 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=corev_rand_instr_test_0.vcd",
"metricsFile": "corev_rand_instr_test_0/metrics.db",
"wavesFile" : "corev_rand_instr_test_0/corev_rand_instr_test_0.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "Generated riscv-dv random instruction test 1",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_rand_instr_test_1 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_rand_instr_test_1 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=corev_rand_instr_test_1.vcd",
"metricsFile": "corev_rand_instr_test_1/metrics.db",
"wavesFile" : "corev_rand_instr_test_1/corev_rand_instr_test_1.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "Generated riscv-dv jump stress test 0",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_jump_stress_test_0 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_jump_stress_test_0 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=corev_jump_stress_test_0.vcd",
"metricsFile": "corev_jump_stress_test_0/metrics.db",
"wavesFile" : "corev_jump_stress_test_0/corev_jump_stress_test_0.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "Generated riscv-dv jump stress test 1",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_jump_stress_test_1 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=corev_jump_stress_test_1 SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=corev_jump_stress_test_1.vcd",
"metricsFile": "corev_jump_stress_test_1/metrics.db",
"wavesFile" : "corev_jump_stress_test_1/corev_jump_stress_test_1.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "cv32-riscv-compliance-tests",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make cv32-riscv-compliance-tests SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make cv32-riscv-compliance-tests SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=cv32-riscv-compliance-tests.vcd",
"metricsFile": "cv32-riscv-compliance-tests/metrics.db",
"wavesFile" : "cv32-riscv-compliance-tests/cv32-riscv-compliance-tests.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "illegal-riscv-tests",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=illegal SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=illegal SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=illegal.vcd",
"metricsFile": "illegal/metrics.db",
"wavesFile" : "illegal/illegal.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "fibonacci-test",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=fibonacci SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=fibonacci SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=fibonacci.vcd",
"metricsFile": "fibonacci/metrics.db",
"wavesFile" : "fibonacci/fibonacci.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "misalign-test",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=misalign SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=misalign SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=misalign.vcd",
"metricsFile": "misalign/metrics.db",
"wavesFile" : "misalign/misalign.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "dhrystone-test",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=dhrystone SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=dhrystone SIMULATOR=dsim USE_ISS=YES DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=dhrystone.vcd",
"metricsFile": "dhrystone/metrics.db",
"wavesFile" : "dhrystone/dhrystone.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
},
{
"name": "pulp_general_alu",
"build": "uvmt_cv32",
"cmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=pulp_general_alu SIMULATOR=dsim USE_ISS=NO DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results",
"wavesCmd": "cd cv32/sim/uvmt_cv32; make custom CUSTOM_PROG=pulp_general_alu SIMULATOR=dsim USE_ISS=NO DSIM_WORK=/mux-flow/build/repo/dsim_work DSIM_RESULTS=/mux-flow/build/results WAVES=1 DSIM_DMP_FILE=pulp_general_alu.vcd",
"metricsFile": "pulp_general_alu/metrics.db",
"wavesFile" : "pulp_general_alu/pulp_general_alu.vcd",
"isPass": "SIMULATION PASSED",
"seed": 1
}
]
}
}
]
}