Just A Question

[mikef656]

Hi Alex,
Thanks for the great IP.
Can you explain concept of the frame WRT AXI-S, and how you use it?
Thanks
Mike

[alexforencich]

A frame is just a block of data that is transferred across multiple cycles. Useful if you're moving things like Ethernet frames over AXI stream.

[mikef656]

ok, How do you determine a frame error? From the diagram, its tlast & tuser asserted during the same clock? Is there a meaning defined for tuser? Thanks Mike

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On Sat, Jul 3, 2021 at 5:29 PM Alex Forencich ***@***.***> wrote: A frame is just a block of data that is transferred across multiple cycles. Useful if you're moving things like Ethernet frames over AXI stream. — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub <#14 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ABLFICCZTXHGTVTXNOUZAVTTV6FN5ANCNFSM47YRGWQA> .

[alexforencich]

There isn't a standard way of reporting bad frames in AXI stream. What I usually do is use tuser[0] to mark bad frames, asserted coincident with tlast.

[mikef656]

ok, tuser[0] means 'bad frame' as determined by some upstream module in the system. What is the design intent of axis_fifo when notified "you just stored a bad frame"? Does it rewind the read pointer so that the bad frame is functionally removed from the fifo? Thanks Mike

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On Sat, Jul 3, 2021 at 6:11 PM Alex Forencich ***@***.***> wrote: There isn't a standard way of reporting bad frames in AXI stream. What I usually do is use tuser[0] to mark bad frames, asserted coincident with tlast. — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub <#14 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ABLFICB72BKSRAU4QFC6BBLTV6KJPANCNFSM47YRGWQA> .

[alexforencich]

Yep. The FIFOs, in frame mode, can look at any bit of tuser for the bad frame indication. And yes, the response is to revert the write pointer back to the start of the frame to remove the frame from the FIFO. Note that this is only possible in frame FIFO mode where the complete frame is spooled in the FIFO before it is released.

[mikef656]

It is a great idea; sounds complex though because what if part of that data has already been read? Maybe then the pointer is not moved. Maybe the surrounding state machines are smart enough not to start reading until they see a non-bad frame enter the fifo. Poking around on the internet it sounds like some people use a tuser bit for a start_of_frame indication in video applications. https://lauri.võsandi.com/hdl/zynq/axi-stream.html <https://lauri.xn--vsandi-pxa.com/hdl/zynq/axi-stream.html> Thanks MIke

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On Sat, Jul 3, 2021 at 7:20 PM Alex Forencich ***@***.***> wrote: Yep. The FIFOs, in frame mode, can look at any bit of tuser for the bad frame indication. And yes, the response is to revert the write pointer back to the start of the frame to remove the frame from the FIFO. Note that this is only possible in frame FIFO mode where the complete frame is spooled in the FIFO before it is released. — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub <#14 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ABLFICA3ZHJMLQNVMXKQO2DTV6SNHANCNFSM47YRGWQA> .

[alexforencich]

In frame FIFO mode, the write pointer is only transferred to the read side when once the entire frame is in the FIFO.

[mikef656]

So in frame FIFO mode, the acts a a full packet accumulation buffer. Nice.

[mikef656]

Another Question on axi_register module:
Does it register the both valid ready?

[alexforencich]

Yes. An additional benefit to frame FIFO mode is that each packet is guaranteed to be delivered without any gaps (tvalid = 0 before tlast = 1), which is useful when feeding Ethernet MACs and similar that cannot tolerate gaps.

The axis_register module will register both the tvalid and tready signals, if it is not bypassed. There are 3 different REG_TYPE values, 0 means bypassed, 1 means a single register slice with 50% throughput, 2 means a full skid buffer with 100% throughput. Both the single register slice and the skid buffer will put a flip flop in the tready path (incidentally, the presence of this register is what limits the single register slice to 50% throughput).