From 4e902b9924ac6e62a65687cfe94e40fde3aec8ef Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Wed, 17 Jan 2024 12:15:53 -0800
Subject: [PATCH] Fix FIFO output pause logic

Signed-off-by: Alex Forencich <alex@alexforencich.com>
---
 rtl/axis_async_fifo.v | 19 +++++++++++--------
 rtl/axis_fifo.v       | 19 +++++++++++--------
 2 files changed, 22 insertions(+), 16 deletions(-)

diff --git a/rtl/axis_async_fifo.v b/rtl/axis_async_fifo.v
index 76eeb8d..4b9f4d6 100644
--- a/rtl/axis_async_fifo.v
+++ b/rtl/axis_async_fifo.v
@@ -861,17 +861,20 @@ if (PAUSE_ENABLE) begin : pause
 
     always @(posedge m_clk) begin
         if (FRAME_PAUSE) begin
-            if (m_axis_tvalid && m_axis_tready) begin
-                if (m_axis_tlast) begin
+            if (pause_reg) begin
+                // paused; update pause status
+                pause_reg <= m_pause_req || s_pause_req_sync3_reg;
+            end else if (m_axis_tvalid_out) begin
+                // fame transfer; set frame bit
+                pause_frame_reg <= 1'b1;
+                if (m_axis_tready && m_axis_tlast) begin
+                    // end of frame; clear frame bit and update pause status
                     pause_frame_reg <= 1'b0;
                     pause_reg <= m_pause_req || s_pause_req_sync3_reg;
-                end else begin
-                    pause_frame_reg <= 1'b1;
-                end
-            end else begin
-                if (!pause_frame_reg) begin
-                    pause_reg <= m_pause_req || s_pause_req_sync3_reg;
                 end
+            end else if (!pause_frame_reg) begin
+                // idle; update pause status
+                pause_reg <= m_pause_req || s_pause_req_sync3_reg;
             end
         end else begin
             pause_reg <= m_pause_req || s_pause_req_sync3_reg;
diff --git a/rtl/axis_fifo.v b/rtl/axis_fifo.v
index e9c9258..1c2fa7f 100644
--- a/rtl/axis_fifo.v
+++ b/rtl/axis_fifo.v
@@ -517,17 +517,20 @@ if (PAUSE_ENABLE) begin : pause
 
     always @(posedge clk) begin
         if (FRAME_PAUSE) begin
-            if (m_axis_tvalid && m_axis_tready) begin
-                if (m_axis_tlast) begin
+            if (pause_reg) begin
+                // paused; update pause status
+                pause_reg <= pause_req;
+            end else if (m_axis_tvalid_out) begin
+                // fame transfer; set frame bit
+                pause_frame_reg <= 1'b1;
+                if (m_axis_tready && m_axis_tlast) begin
+                    // end of frame; clear frame bit and update pause status
                     pause_frame_reg <= 1'b0;
                     pause_reg <= pause_req;
-                end else begin
-                    pause_frame_reg <= 1'b1;
-                end
-            end else begin
-                if (!pause_frame_reg) begin
-                    pause_reg <= pause_req;
                 end
+            end else if (!pause_frame_reg) begin
+                // idle; update pause status
+                pause_reg <= pause_req;
             end
         end else begin
             pause_reg <= pause_req;