CORE-V Wally is functionally tested in the following ways. Each test is run in lock-step against ImperasDV to ensure all architectural state is correct after each instruction.
Tests | Section | TRL3 | TRL5 | Coverage Method | Status | Command |
---|---|---|---|---|---|---|
Verilator Lint | 5.3 | All configs | rv64gc | lint-wally | PASS | regression-wally --nightly |
Instructions | 3.7 | All configs | rv64gc | riscv-arch-test | PASS | regression-wally --nightly |
Privileged | 3.7 | All configs | rv64gc | wally-riscv-arch-test | PASS | regression-wally --nightly |
Floating-point | 5.11.7, 16.5.3 | rv{32/64}gc + derived | rv64gc | TestFloat | FAIL | regression-wally --nightly |
CoreMark | 21.1 | Many configs | rv64gc | CoreMark | regression-wally --nightly | |
Embench | 21.2 | rv32* | n/a | Embench | regression-wally --nightly | |
Cache PV | 21.3.1 | rv{32/64}gc | rv64gc | TBD | TBD | TBD |
Cache PV | 21.3.2 | rv{32/64}gc | rv64gc | TBD | TBD | TBD |
Linux Boot | 22.3.2 | rv64gc | rv64gc | TBD | TBD | TBD |
FPGA Linux Boot | 23.2 | rv64gc | TBD | TBD | TBD | |
Code Coverage | 5.11.10 | rv64gc | TBD | TBD | TBD | |
Functional Coverage | 5.11.11 | rv64gc | TBD | TBD | TBD |
- Run RISC-V Architecture Compatibility Tests in lock-step against the ImperasDV reference model.
- Run custom tests to cover virtual memory, PMP, privileged unit, and peripherals in lock step against ImperasDV.
- ***pending: Run random tests generated by risc-dv
- Run CoreMark and Embench benchmarks.
- Run performance validation against reference models for the branch predictor and caches.
- Run the TestFloat suite against all precisions of all operations for the FPU unit.
- *** 83.5% coverage of statements, branches, expressions, and FSM states and transitions
- Boot Buildroot Linux in lock-step against ImperasDV.
- Boot Buildroot Linux on an FPGA and run programs.
The test plans for specific units are lined below:
- Privileged Unit
- Memory Management Unit
- Peripherals
- Branch Predictor Performance Validation
- Cache Performance Validation
Wally is described in an upcoming textbook, RISC-V System-on-Chip Design, by Harris, Stine, Thompson, and Harris.