From 86e1080f05d6ab999e7fd393b81ba10aa9231c7f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 27 Mar 2024 23:54:51 +0100 Subject: [PATCH 1/6] cellmatch: New pass --- passes/techmap/Makefile.inc | 1 + passes/techmap/cellmatch.cc | 340 ++++++++++++++++++++++++++++++++++++ 2 files changed, 341 insertions(+) create mode 100644 passes/techmap/cellmatch.cc diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 9d57e3d71af..74813bca93f 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -48,6 +48,7 @@ OBJS += passes/techmap/dfflegalize.o OBJS += passes/techmap/dffunmap.o OBJS += passes/techmap/flowmap.o OBJS += passes/techmap/extractinv.o +OBJS += passes/techmap/cellmatch.o endif ifeq ($(DISABLE_SPAWN),0) diff --git a/passes/techmap/cellmatch.cc b/passes/techmap/cellmatch.cc new file mode 100644 index 00000000000..7c75418e3bc --- /dev/null +++ b/passes/techmap/cellmatch.cc @@ -0,0 +1,340 @@ +#include "kernel/celltypes.h" +#include "kernel/register.h" +#include "kernel/rtlil.h" +#include "kernel/sigtools.h" +#include "kernel/utils.h" + +#include + +USING_YOSYS_NAMESPACE +YOSYS_NAMESPACE_BEGIN + +// return module's inputs in canonical order +SigSpec module_inputs(Module *m) +{ + SigSpec ret; + for (auto port : m->ports) { + Wire *w = m->wire(port); + if (!w->port_input) + continue; + if (w->width != 1) + log_error("Unsupported wide port (%s) of non-unit width found in module %s.\n", + log_id(w), log_id(m)); + ret.append(w); + } + return ret; +} + +// return module's outputs in canonical order +SigSpec module_outputs(Module *m) +{ + SigSpec ret; + for (auto port : m->ports) { + Wire *w = m->wire(port); + if (!w->port_output) + continue; + if (w->width != 1) + log_error("Unsupported wide port (%s) of non-unit width found in module %s.\n", + log_id(w), log_id(m)); + ret.append(w); + } + return ret; +} + +uint64_t permute_lut(uint64_t lut, const std::vector &varmap) +{ + int k = varmap.size(); + uint64_t ret = 0; + for (int j = 0; j < 1 << k; j++) { + int m = 0; + for (int l = 0; l < k; l++) + if (j & 1 << l) + m |= 1 << varmap[l]; + if (lut & 1 << m) + ret |= 1 << j; + } + return ret; +} + +uint64_t p_class(int k, uint64_t lut) +{ + std::vector map; + for (int j = 0; j < k; j++) + map.push_back(j); + + uint64_t repr = ~(uint64_t) 0; + std::vector repr_vars; + while (true) { + uint64_t perm = permute_lut(lut, map); + if (perm <= repr) { + repr = perm; + repr_vars = map; + } + if (!std::next_permutation(map.begin(), map.end())) + break; + } + return repr; +} + +bool derive_module_luts(Module *m, std::vector &luts) +{ + SigMap sigmap(m); + CellTypes ff_types; + ff_types.setup_stdcells_mem(); + + dict driver; + for (auto cell : m->selected_cells()) { + if (cell->type.in(ID($specify2), ID($specify3), ID($specrule))) + continue; + + if (ff_types.cell_known(cell->type)) { + log("Ignoring module '%s' which isn't purely combinational.\n", log_id(m)); + return false; + } + + if (!cell->type.in(ID($_NOT_), ID($_AND_))) + log_error("Unsupported cell in module '%s': %s of type %s\n", + log_id(m), log_id(cell), log_id(cell->type)); + + driver[sigmap(cell->getPort(ID::Y))] = cell; + } + + TopoSort sort; + for (auto cell : m->cells()) + if (cell->type.in(ID($_NOT_), ID($_AND_))) { + sort.node(cell); + SigSpec inputs = cell->type == ID($_AND_) + ? SigSpec({cell->getPort(ID::B), cell->getPort(ID::A)}) + : cell->getPort(ID::A); + for (auto bit : sigmap(inputs)) + if (driver.count(bit)) + sort.edge(driver.at(bit), cell); + } + + if (!sort.sort()) + log_error("Module %s contains combinational loops.\n", log_id(m)); + + dict states; + states[State::S0] = 0; + states[State::S1] = ~(uint64_t) 1; + + { + uint64_t sieves[6] = { + 0xaaaaaaaaaaaaaaaa, + 0xcccccccccccccccc, + 0xf0f0f0f0f0f0f0f0, + 0xff00ff00ff00ff00, + 0xffff0000ffff0000, + 0xffffffff00000000, + }; + + SigSpec inputs = sigmap(module_inputs(m)); + if (inputs.size() > 6) { + log_warning("Skipping module %s with more than 6 inputs bits.\n", log_id(m)); + return false; + } + + for (int i = 0; i < inputs.size(); i++) + states[inputs[i]] = sieves[i] & ((((uint64_t) 1) << (1 << inputs.size())) - 1); + } + + for (auto cell : sort.sorted) { + if (cell->type.in(ID($specify2), ID($specify3), ID($specrule))) + continue; + + if (cell->type == ID($_AND_)) { + SigSpec a = sigmap(cell->getPort(ID::A)); + SigSpec b = sigmap(cell->getPort(ID::B)); + if (!states.count(a) || !states.count(b)) + log_error("Cell %s in module %s sources an undriven wire!", + log_id(cell), log_id(m)); + states[sigmap(cell->getPort(ID::Y))] = \ + states.at(a) & states.at(b); + } else if (cell->type == ID($_NOT_)) { + SigSpec a = sigmap(cell->getPort(ID::A)); + if (!states.count(a)) + log_error("Cell %s in module %s sources an undriven wire!", + log_id(cell), log_id(m)); + states[sigmap(cell->getPort(ID::Y))] = ~states.at(a); + } else { + log_abort(); + } + } + + for (auto bit : module_outputs(m)) { + if (!states.count(sigmap(bit))) + log_error("Output port %s in module %s is undriven!", + log_signal(bit), log_id(m)); + luts.push_back(states.at(sigmap(bit))); + } + return true; +} + +struct CellmatchPass : Pass { + CellmatchPass() : Pass("cellmatch", "match cells to their targets in cell library") {} + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" cellmatch -lib [module selection]\n"); + log("\n"); + log("This pass identifies functionally equivalent counterparts between each of the\n"); + log("selected modules and a module from the secondary design . For every such\n"); + log("correspondence found, a techmap rule is generated for mapping instances of the\n"); + log("former to instances of the latter. This techmap rule is saved in yet another\n"); + log("design called '$cellmatch_map', which is created if non-existent.\n"); + log("\n"); + log("This pass restricts itself to combinational modules which must be modeled with an\n"); + log("and-inverter graph. Run 'aigmap' first if necessary. Modules are functionally\n"); + log("equivalent as long as their truth tables are identical upto a permutation of\n"); + log("inputs and outputs. The number of inputs is limited to 6.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *d) override + { + log_header(d, "Executing CELLMATCH pass. (match cells)\n"); + + size_t argidx; + bool lut_attrs = false; + Design *lib = NULL; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-lut_attrs") { + // an undocumented debugging option + lut_attrs = true; + } else if (args[argidx] == "-lib" && argidx + 1 < args.size()) { + if (!saved_designs.count(args[++argidx])) + log_cmd_error("No design '%s' found!\n", args[argidx].c_str()); + lib = saved_designs.at(args[argidx]); + } else { + break; + } + } + extra_args(args, argidx, d); + + if (!lib && !lut_attrs) + log_cmd_error("Missing required -lib option.\n"); + + struct Target { + Module *module; + std::vector luts; + }; + + dict, std::vector> targets; + + if (lib) + for (auto m : lib->modules()) { + pool p_classes; + + // produce a fingerprint in p_classes + int ninputs = module_inputs(m).size(); + std::vector luts; + if (!derive_module_luts(m, luts)) + continue; + for (auto lut : luts) + p_classes.insert(p_class(ninputs, lut)); + + // save as a viable target + targets[p_classes].push_back(Target{m, luts}); + } + + auto r = saved_designs.emplace("$cellmatch_map", nullptr); + if (r.second) + r.first->second = new Design; + Design *map_design = r.first->second; + + for (auto m : d->selected_whole_modules_warn()) { + std::vector luts; + if (!derive_module_luts(m, luts)) + continue; + + SigSpec inputs = module_inputs(m); + SigSpec outputs = module_outputs(m); + + if (lut_attrs) { + int no = 0; + for (auto bit : outputs) { + log_assert(bit.is_wire()); + bit.wire->attributes[ID(p_class)] = p_class(inputs.size(), luts[no]); + bit.wire->attributes[ID(lut)] = luts[no++]; + } + } + + // fingerprint + pool p_classes; + for (auto lut : luts) + p_classes.insert(p_class(inputs.size(), lut)); + + for (auto target : targets[p_classes]) { + log_debug("Candidate %s for matching to %s\n", log_id(target.module), log_id(m)); + + SigSpec target_inputs = module_inputs(target.module); + SigSpec target_outputs = module_outputs(target.module); + + if (target_inputs.size() != inputs.size()) + continue; + + if (target_outputs.size() != outputs.size()) + continue; + + std::vector input_map; + for (int i = 0; i < inputs.size(); i++) + input_map.push_back(i); + + bool found_match = false; + while (!found_match) { + std::vector output_map; + for (int i = 0; i < outputs.size(); i++) + output_map.push_back(i); + + while (!found_match) { + int out_no = 0; + bool match = true; + for (auto lut : luts) { + if (permute_lut(target.luts[output_map[out_no++]], input_map) != lut) { + match = false; + break; + } + } + + if (match) { + log("Module %s matches %s\n", log_id(m), log_id(target.module)); + Module *map = map_design->addModule(stringf("\\_60_%s_%s", log_id(m), log_id(target.module))); + Cell *cell = map->addCell(ID::_TECHMAP_REPLACE_, target.module->name); + + map->attributes[ID(techmap_celltype)] = m->name.str(); + + for (int i = 0; i < outputs.size(); i++) { + log_assert(outputs[i].is_wire()); + Wire *w = map->addWire(outputs[i].wire->name, 1); + w->port_id = outputs[i].wire->port_id; + w->port_output = true; + log_assert(target_outputs[output_map[i]].is_wire()); + cell->setPort(target_outputs[output_map[i]].wire->name, w); + } + + for (int i = 0; i < inputs.size(); i++) { + log_assert(inputs[i].is_wire()); + Wire *w = map->addWire(inputs[i].wire->name, 1); + w->port_id = inputs[i].wire->port_id; + w->port_input = true; + log_assert(target_inputs[input_map[i]].is_wire()); + cell->setPort(target_inputs[input_map[i]].wire->name, w); + } + + map->fixup_ports(); + found_match = true; + } + + if (!std::next_permutation(output_map.begin(), output_map.end())) + break; + } + + if (!std::next_permutation(input_map.begin(), input_map.end())) + break; + } + } + } + } +} CellmatchPass; + +YOSYS_NAMESPACE_END From 6a9858cdad96322ddca73d50602ce643c82edc04 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 13 Apr 2024 16:56:36 +0200 Subject: [PATCH 2/6] cellmatch: Delegate evaluation to `ConstEval` --- passes/techmap/cellmatch.cc | 107 ++++++++++-------------------------- 1 file changed, 30 insertions(+), 77 deletions(-) diff --git a/passes/techmap/cellmatch.cc b/passes/techmap/cellmatch.cc index 7c75418e3bc..9459c112fe7 100644 --- a/passes/techmap/cellmatch.cc +++ b/passes/techmap/cellmatch.cc @@ -2,6 +2,7 @@ #include "kernel/register.h" #include "kernel/rtlil.h" #include "kernel/sigtools.h" +#include "kernel/consteval.h" #include "kernel/utils.h" #include @@ -78,95 +79,48 @@ uint64_t p_class(int k, uint64_t lut) bool derive_module_luts(Module *m, std::vector &luts) { - SigMap sigmap(m); CellTypes ff_types; ff_types.setup_stdcells_mem(); - - dict driver; - for (auto cell : m->selected_cells()) { - if (cell->type.in(ID($specify2), ID($specify3), ID($specrule))) - continue; - + for (auto cell : m->cells()) { if (ff_types.cell_known(cell->type)) { log("Ignoring module '%s' which isn't purely combinational.\n", log_id(m)); return false; } - - if (!cell->type.in(ID($_NOT_), ID($_AND_))) - log_error("Unsupported cell in module '%s': %s of type %s\n", - log_id(m), log_id(cell), log_id(cell->type)); - - driver[sigmap(cell->getPort(ID::Y))] = cell; } - TopoSort sort; - for (auto cell : m->cells()) - if (cell->type.in(ID($_NOT_), ID($_AND_))) { - sort.node(cell); - SigSpec inputs = cell->type == ID($_AND_) - ? SigSpec({cell->getPort(ID::B), cell->getPort(ID::A)}) - : cell->getPort(ID::A); - for (auto bit : sigmap(inputs)) - if (driver.count(bit)) - sort.edge(driver.at(bit), cell); - } - - if (!sort.sort()) - log_error("Module %s contains combinational loops.\n", log_id(m)); - - dict states; - states[State::S0] = 0; - states[State::S1] = ~(uint64_t) 1; - - { - uint64_t sieves[6] = { - 0xaaaaaaaaaaaaaaaa, - 0xcccccccccccccccc, - 0xf0f0f0f0f0f0f0f0, - 0xff00ff00ff00ff00, - 0xffff0000ffff0000, - 0xffffffff00000000, - }; - - SigSpec inputs = sigmap(module_inputs(m)); - if (inputs.size() > 6) { - log_warning("Skipping module %s with more than 6 inputs bits.\n", log_id(m)); - return false; - } + SigSpec inputs = module_inputs(m); + SigSpec outputs = module_outputs(m); + int ninputs = inputs.size(), noutputs = outputs.size(); - for (int i = 0; i < inputs.size(); i++) - states[inputs[i]] = sieves[i] & ((((uint64_t) 1) << (1 << inputs.size())) - 1); + if (ninputs > 6) { + log_warning("Skipping module %s with more than 6 inputs bits.\n", log_id(m)); + return false; } - for (auto cell : sort.sorted) { - if (cell->type.in(ID($specify2), ID($specify3), ID($specrule))) - continue; + luts.clear(); + luts.resize(noutputs); + + ConstEval ceval(m); + for (int i = 0; i < 1 << ninputs; i++) { + ceval.clear(); + for (int j = 0; j < ninputs; j++) + ceval.set(inputs[j], (i & (1 << j)) ? State::S1 : State::S0); + for (int j = 0; j < noutputs; j++) { + SigSpec bit = outputs[j]; + + if (!ceval.eval(bit)) { + log("Failed to evaluate output '%s' in module '%s'.\n", + log_signal(outputs[j]), log_id(m)); + return false; + } - if (cell->type == ID($_AND_)) { - SigSpec a = sigmap(cell->getPort(ID::A)); - SigSpec b = sigmap(cell->getPort(ID::B)); - if (!states.count(a) || !states.count(b)) - log_error("Cell %s in module %s sources an undriven wire!", - log_id(cell), log_id(m)); - states[sigmap(cell->getPort(ID::Y))] = \ - states.at(a) & states.at(b); - } else if (cell->type == ID($_NOT_)) { - SigSpec a = sigmap(cell->getPort(ID::A)); - if (!states.count(a)) - log_error("Cell %s in module %s sources an undriven wire!", - log_id(cell), log_id(m)); - states[sigmap(cell->getPort(ID::Y))] = ~states.at(a); - } else { - log_abort(); + log_assert(ceval.eval(bit)); + + if (bit[0] == State::S1) + luts[j] |= 1 << i; } } - for (auto bit : module_outputs(m)) { - if (!states.count(sigmap(bit))) - log_error("Output port %s in module %s is undriven!", - log_signal(bit), log_id(m)); - luts.push_back(states.at(sigmap(bit))); - } return true; } @@ -184,10 +138,9 @@ struct CellmatchPass : Pass { log("former to instances of the latter. This techmap rule is saved in yet another\n"); log("design called '$cellmatch_map', which is created if non-existent.\n"); log("\n"); - log("This pass restricts itself to combinational modules which must be modeled with an\n"); - log("and-inverter graph. Run 'aigmap' first if necessary. Modules are functionally\n"); + log("This pass restricts itself to combinational modules. Modules are functionally\n"); log("equivalent as long as their truth tables are identical upto a permutation of\n"); - log("inputs and outputs. The number of inputs is limited to 6.\n"); + log("inputs and outputs. The supported number of inputs is limited to 6.\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *d) override From c0e68dcc4d232542272d1ad436767175a6f04481 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 13 Apr 2024 16:56:44 +0200 Subject: [PATCH 3/6] cellmatch: Add debug print --- passes/techmap/cellmatch.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/passes/techmap/cellmatch.cc b/passes/techmap/cellmatch.cc index 9459c112fe7..5301cc99bfd 100644 --- a/passes/techmap/cellmatch.cc +++ b/passes/techmap/cellmatch.cc @@ -185,6 +185,8 @@ struct CellmatchPass : Pass { continue; for (auto lut : luts) p_classes.insert(p_class(ninputs, lut)); + + log_debug("Registered %s\n", log_id(m)); // save as a viable target targets[p_classes].push_back(Target{m, luts}); From 913bc87c4419303e32f4ca86ed437fe1e8ee015e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 13 Apr 2024 17:12:53 +0200 Subject: [PATCH 4/6] cellmatch: Add test --- tests/techmap/cellmatch.ys | 79 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 tests/techmap/cellmatch.ys diff --git a/tests/techmap/cellmatch.ys b/tests/techmap/cellmatch.ys new file mode 100644 index 00000000000..46960fc1430 --- /dev/null +++ b/tests/techmap/cellmatch.ys @@ -0,0 +1,79 @@ +read_verilog < Date: Sat, 13 Apr 2024 17:20:32 +0200 Subject: [PATCH 5/6] cellmatch: Rename the special design to `$cellmatch` --- passes/techmap/cellmatch.cc | 4 ++-- tests/techmap/cellmatch.ys | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/passes/techmap/cellmatch.cc b/passes/techmap/cellmatch.cc index 5301cc99bfd..d1da6babd63 100644 --- a/passes/techmap/cellmatch.cc +++ b/passes/techmap/cellmatch.cc @@ -136,7 +136,7 @@ struct CellmatchPass : Pass { log("selected modules and a module from the secondary design . For every such\n"); log("correspondence found, a techmap rule is generated for mapping instances of the\n"); log("former to instances of the latter. This techmap rule is saved in yet another\n"); - log("design called '$cellmatch_map', which is created if non-existent.\n"); + log("design called '$cellmatch', which is created if non-existent.\n"); log("\n"); log("This pass restricts itself to combinational modules. Modules are functionally\n"); log("equivalent as long as their truth tables are identical upto a permutation of\n"); @@ -192,7 +192,7 @@ struct CellmatchPass : Pass { targets[p_classes].push_back(Target{m, luts}); } - auto r = saved_designs.emplace("$cellmatch_map", nullptr); + auto r = saved_designs.emplace("$cellmatch", nullptr); if (r.second) r.first->second = new Design; Design *map_design = r.first->second; diff --git a/tests/techmap/cellmatch.ys b/tests/techmap/cellmatch.ys index 46960fc1430..bea2f598d94 100644 --- a/tests/techmap/cellmatch.ys +++ b/tests/techmap/cellmatch.ys @@ -61,7 +61,7 @@ prep cellmatch -lib gatelib FA A:gate design -save gold -techmap -map %$cellmatch_map +techmap -map %$cellmatch design -save gate select -assert-none ripple_carry/t:FA From e939182e68edc26b4267f011f644067e29c7c25a Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Fri, 3 May 2024 12:11:55 +0200 Subject: [PATCH 6/6] cellmatch: add comments --- passes/techmap/cellmatch.cc | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/passes/techmap/cellmatch.cc b/passes/techmap/cellmatch.cc index d1da6babd63..a21a4fbadc2 100644 --- a/passes/techmap/cellmatch.cc +++ b/passes/techmap/cellmatch.cc @@ -42,10 +42,16 @@ SigSpec module_outputs(Module *m) return ret; } +// Permute the inputs of a single-output k-LUT according to varmap uint64_t permute_lut(uint64_t lut, const std::vector &varmap) { int k = varmap.size(); uint64_t ret = 0; + // Index j iterates over all bits in lut. + // When (j & 1 << n) is true, + // (lut & 1 << j) represents an output value where input var n is set. + // We use this fact to permute the LUT such that + // every variable n is remapped to varmap[n]. for (int j = 0; j < 1 << k; j++) { int m = 0; for (int l = 0; l < k; l++) @@ -57,6 +63,10 @@ uint64_t permute_lut(uint64_t lut, const std::vector &varmap) return ret; } +// Find the LUT with the minimum integer representation +// such that it is a permutation of the given lut. +// The resulting LUT becomes the "fingerprint" of the "permutation class". +// This function checks all possible input permutations. uint64_t p_class(int k, uint64_t lut) { std::vector map; @@ -77,6 +87,9 @@ uint64_t p_class(int k, uint64_t lut) return repr; } +// Represent module m as N single-output k-LUTs +// where k is the number of module inputs, +// and N is the number of module outputs. bool derive_module_luts(Module *m, std::vector &luts) { CellTypes ff_types; @@ -185,7 +198,7 @@ struct CellmatchPass : Pass { continue; for (auto lut : luts) p_classes.insert(p_class(ninputs, lut)); - + log_debug("Registered %s\n", log_id(m)); // save as a viable target @@ -210,7 +223,7 @@ struct CellmatchPass : Pass { for (auto bit : outputs) { log_assert(bit.is_wire()); bit.wire->attributes[ID(p_class)] = p_class(inputs.size(), luts[no]); - bit.wire->attributes[ID(lut)] = luts[no++]; + bit.wire->attributes[ID(lut)] = luts[no++]; } } @@ -236,11 +249,13 @@ struct CellmatchPass : Pass { input_map.push_back(i); bool found_match = false; + // For each input_map while (!found_match) { std::vector output_map; for (int i = 0; i < outputs.size(); i++) output_map.push_back(i); + // For each output_map while (!found_match) { int out_no = 0; bool match = true; @@ -253,6 +268,8 @@ struct CellmatchPass : Pass { if (match) { log("Module %s matches %s\n", log_id(m), log_id(target.module)); + // Add target.module to map_design ("$cellmatch") + // as a techmap rule to match m and replace it with target.module Module *map = map_design->addModule(stringf("\\_60_%s_%s", log_id(m), log_id(target.module))); Cell *cell = map->addCell(ID::_TECHMAP_REPLACE_, target.module->name); @@ -281,7 +298,7 @@ struct CellmatchPass : Pass { } if (!std::next_permutation(output_map.begin(), output_map.end())) - break; + break; } if (!std::next_permutation(input_map.begin(), input_map.end()))