Recommendations for when nextprn can't meet timing but icecube2 can?

[pbozeman]

I have a design for which nextprn-ice40 can no longer meet timing, even with trying seeds ranging from 0 to 256. icecube2 can easily meet timing on the same design with an fmax of ~120mhz.

Other than --freq 100 and --seed n, I'm not passing any other pnr related options to nextprn (other than the yosys input file, output options, etc.)

Are there any suggested options to help nextprn, or docs on how to better meet timing with nextprn? I see a bunch of place and route options, but it isn't clear to me how they interact and which are newer/better options and which are options to go back to older/legacy behavior.

Thanks

[rowanG077]

You mention nextpnr "can no longer meet timing". Did the same design used to meet timing using nextpnr? If so it might be interesting to check if there is a regression.

Did you use yosys for synthesis? I'm personally not familiar with icecube but I guess it uses some other synthesis tool. So it's possible a significant part is the synthesis result and not place and routing.

[pbozeman]

When I said, "can no longer meet timing" I meant that as I kept adding to the design, I stopped being able to find a seed. At first, yosys/nextpnr could always meet timing without doing anything. Then I had to find seeds, which I used to do manually and would find them within a few tries. Then I had to write a script an searched up to 16, which always worked. Then I had to extend to 32 seeds and would it would sometimes find them all the way up in the 20s. Now I can't find them at all anymore.

I'm using yosys for synthesis, and am not using any flags of significance there either.

Icecube2 is the official Lattice synthesis and PnR. I think it uses Synopsys for synthesis under the covers, but that's entirely hidden unless you go searching for it. I'm not sure what it's doing for PNR. (The official lattice tools are ungodly slow, but they are working. I'm hoping to not have to use them and get back to being able to work with yosys/nextpnr.)

[povik]

@pbozeman are you willing to share the design together with details on the F_max you can achieve with the vendor tool?

[pbozeman]

@povik Sure. I made a branch that enables the designs that don't meet timing at https://github.com/pbozeman/vanilla-ice40/tree/yosyshq

I added instructions at the top of the readme for how to build, including just the stand alone yosys and nextprn commands to run on a specific design so that you don't have to use the makefile. I checked in a timing report from the vendors tools as well.

Let me know if you want me to try to trim this down, or if you need any other artifacts from the vendor tools.

Also, I'm new to both pcb design and verilog, so please forgive any weirdness in what I'm doing :)