how does yosys synthesize initial blocks

[pm100]

I am curious to see what it does given that icecube says its ignores them. I ran a small file through yosys and captured the generated rtl using write_verilog. I compared the output for 'reg <=0' and 'reg<= 42' so I could easily spot where the init code is, but the two files are identical.

[KrystalDelusion]

It depends on what you're assigning to, how you're using it, and what yosys commands you call as to how an initial value might be optimised. If you're using memory for example, the memory primitives will often have an INIT parameter that gets assigned. Registers can be quite easily optimised out if they have a constant value or if the value is never read. You may also have more luck with write_rtlil, or you can call dump if you just want it to output to the log instead of a file. Also if you haven't yet, I would recommend checking out the synthesis starter document. It runs through the synthesis process step by step for a simple (FIFO buffer) design.