How to get detailed report on memory to RAM mappings?

[tomverbeure]

Hi,

My design has a bunch of RAMs that get successfully mapped to ECP5 BRAMs.

However, I'm trying to get a detail mapping report. Right now, the Yosys log has the following:

3.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing Cube2Top.core_u_cpu.u_cpu.cpu.RegFilePlugin_regFile write port 0.
  Analyzing Cube2Top.core_u_cpu.u_cpu.ram.ram_symbol0 write port 0.
  Analyzing Cube2Top.core_u_cpu.u_cpu.ram.ram_symbol1 write port 0.
  Analyzing Cube2Top.core_u_cpu.u_cpu.ram.ram_symbol2 write port 0.
  Analyzing Cube2Top.core_u_cpu.u_cpu.ram.ram_symbol3 write port 0.
  Analyzing Cube2Top.core_u_hub75_streamer.u_output_fifo.logic_ram write port 0.
  Analyzing Cube2Top.core_u_led_mem._zz_1 write port 0.
  Analyzing Cube2Top.core_u_led_mem._zz_10 write port 0.
  Analyzing Cube2Top.core_u_led_mem._zz_13 write port 0.
  Analyzing Cube2Top.core_u_led_mem._zz_4 write port 0.
  Analyzing Cube2Top.core_u_led_mem._zz_7 write port 0.

...

3.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\core_u_cpu.u_cpu.cpu.RegFilePlugin_regFile'[0] in module `\Cube2Top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\core_u_cpu.u_cpu.cpu.RegFilePlugin_regFile'[1] in module `\Cube2Top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\core_u_cpu.u_cpu.ram.ram_symbol0'[0] in module `\Cube2Top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\core_u_cpu.u_cpu.ram.ram_symbol1'[0] in module `\Cube2Top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\core_u_cpu.u_cpu.ram.ram_symbol2'[0] in module `\Cube2Top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\core_u_cpu.u_cpu.ram.ram_symbol3'[0] in module `\Cube2Top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\core_u_hub75_streamer.u_output_fifo.logic_ram'[0] in module `\Cube2Top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\core_u_led_mem._zz_1'[0] in module `\Cube2Top': merging output FF to cell.
    Write port 0: don't care on collision.
Checking read port `\core_u_led_mem._zz_1'[1] in module `\Cube2Top': merging output FF to cell.
    Write port 0: don't care on collision.
Checking read port `\core_u_led_mem._zz_10'[0] in module `\Cube2Top': merging output FF to cell.
    Write port 0: don't care on collision.
Checking read port `\core_u_led_mem._zz_13'[0] in module `\Cube2Top': merging output FF to cell.
    Write port 0: don't care on collision.
Checking read port `\core_u_led_mem._zz_4'[0] in module `\Cube2Top': merging output FF to cell.
    Write port 0: don't care on collision.
Checking read port `\core_u_led_mem._zz_7'[0] in module `\Cube2Top': merging output FF to cell.
    Write port 0: don't care on collision.

...

3.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory Cube2Top.core_u_cpu.u_cpu.cpu.RegFilePlugin_regFile via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of Cube2Top.core_u_cpu.u_cpu.cpu.RegFilePlugin_regFile: $\core_u_cpu.u_cpu.cpu.RegFilePlugin_regFile$rdreg[0]
Extracted data FF from read port 1 of Cube2Top.core_u_cpu.u_cpu.cpu.RegFilePlugin_regFile: $\core_u_cpu.u_cpu.cpu.RegFilePlugin_regFile$rdreg[1]
mapping memory Cube2Top.core_u_cpu.u_cpu.ram.ram_symbol0 via $__ECP5_DP16KD_
mapping memory Cube2Top.core_u_cpu.u_cpu.ram.ram_symbol1 via $__ECP5_DP16KD_
mapping memory Cube2Top.core_u_cpu.u_cpu.ram.ram_symbol2 via $__ECP5_DP16KD_
mapping memory Cube2Top.core_u_cpu.u_cpu.ram.ram_symbol3 via $__ECP5_DP16KD_
mapping memory Cube2Top.core_u_hub75_streamer.u_output_fifo.logic_ram via $__ECP5_PDPW16KD_
mapping memory Cube2Top.core_u_led_mem._zz_1 via $__ECP5_DP16KD_
mapping memory Cube2Top.core_u_led_mem._zz_10 via $__ECP5_DP16KD_
mapping memory Cube2Top.core_u_led_mem._zz_13 via $__ECP5_DP16KD_
mapping memory Cube2Top.core_u_led_mem._zz_4 via $__ECP5_DP16KD_
mapping memory Cube2Top.core_u_led_mem._zz_7 via $__ECP5_DP16KD_

...

It's something, I guess, but it doesn't compare to the kind of tech mapping reports that you get with Quartus or Vivid, where it will list each memory as declared in the Verily, with size, bus width, access mode and so forth, and then lists how it was mapped to LUT or block RAMs: the number of RAMs, whether or not additional output FFs were used etc.

I looked around a little bit, but I can't find anything that gives me that information.

Does such a report command exist?
And, if not, is this information even available in the design database after conversion steps have been performed?

Thanks,
Tom

[nakengelhardt]

memory_libmap can output a bit more information that covers some of what you're requesting in debug mode, but that's a bit difficult to enable for just the one command. You can either enable it globally (but beware, the log file will get very long), or if you don't mind recompiling yosys, you can change this line:

yosys/techlibs/ecp5/synth_ecp5.cc

Line 313 in 5691cd0

run("memory_libmap -lib +/ecp5/lutrams.txt -lib +/ecp5/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");

to run("debug memory_libmap ...

(Or, I suppose you could try changing memory_libmap to output more information by default...)
After memory_libmap I don't think there's any way to reconstitute this information.

[tomverbeure]

Ok!

I just tried it with the global debug mode by adding -p "logger -debug" to the command line.

That gives me more information than I need, but that's better than nothing. :-)

Thanks!
Tom