From f193bcf683b8dcbfa11132ea2e20858cd63cd176 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 16 Sep 2024 14:20:33 +0200 Subject: [PATCH] clockgate: help string --- passes/techmap/clockgate.cc | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/passes/techmap/clockgate.cc b/passes/techmap/clockgate.cc index da40ae07641..bf53b02bbc8 100644 --- a/passes/techmap/clockgate.cc +++ b/passes/techmap/clockgate.cc @@ -44,10 +44,9 @@ struct ClockgatePass : public Pass { log("\n"); log(" clockgate [options] [selection]\n"); log("\n"); - log("Creates gated clock nets for sets of FFs with clock enable\n"); - log("sharing a clock and replaces the FFs with versions without\n"); - log("clock enable inputs. Intended to reduce power consumption\n"); - log("in ASIC designs.\n"); + log("This pass transforms each set of FFs sharing the same clock and\n"); + log("enable signal into a clock-gating cell and a set of enable-less FFs.\n"); + log("Primarily a power-saving transformation on ASIC designs.\n"); log("\n"); log(" -pos ::\n"); log(" If specified, rising-edge FFs will have CE inputs\n");