From 76f30d0011b50c1b76493df719408b9525a3ead5 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Thu, 2 May 2024 23:49:50 +0200
Subject: [PATCH] techmap: add dynamic cell type test

---
 tests/techmap/techmap_chtype.ys | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 tests/techmap/techmap_chtype.ys

diff --git a/tests/techmap/techmap_chtype.ys b/tests/techmap/techmap_chtype.ys
new file mode 100644
index 00000000000..7c339842013
--- /dev/null
+++ b/tests/techmap/techmap_chtype.ys
@@ -0,0 +1,33 @@
+read_verilog <<EOT
+
+(* techmap_celltype="foo" *)
+module _80_lcu_primitive(P, G, CI, CO);
+	parameter WIDTH = 10;
+
+	(* force_downto *)
+	input wire [WIDTH-1:0] P;
+	(* force_downto *)
+	input wire [WIDTH-1:0] G;
+	input wire CI;
+	(* force_downto *)
+	output wire [WIDTH-1:0] CO;
+
+	(* techmap_chtype=$sformatf("LCU_%0d", WIDTH) *)
+	_TECHMAP_PLACEHOLDER_ #(.WIDTH(WIDTH)) _TECHMAP_REPLACE_(.P(P), .G(G), .CI(CI), .CO(CO));
+endmodule
+
+EOT
+design -stash techmap
+
+read_verilog <<EOT
+module top(input [3:0] pi, input [3:0] gi, input ci, output [3:0] co);
+foo #(.WIDTH(8)) suuuub(pi, gi, ci, co);
+endmodule
+EOT
+
+hierarchy -auto-top
+proc
+opt
+techmap -map %techmap
+
+select -assert-count 1 t:LCU_8