diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 81fb3189d94..d62f06ae549 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -759,7 +759,7 @@ struct AST_INTERNAL::ProcessGenerator
 						arg.realtime = true;
 					} else {
 						arg.type = VerilogFmtArg::INTEGER;
-						arg.sig = node->genRTLIL();
+						arg.sig = node->genWidthRTLIL(-1, false, &subst_rvalue_map.stdmap());
 						arg.signed_ = is_signed;
 					}
 					args.push_back(arg);