From a8809989c4f31e284a2bed593d71e9a11deec771 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 22 Aug 2023 10:50:11 +0200 Subject: [PATCH 1/7] ecp5_gsr -> lattice_gsr, change opt_lut_ins to accept lattice as tech --- passes/opt/opt_lut_ins.cc | 14 +++++++------- techlibs/ecp5/Makefile.inc | 2 +- techlibs/ecp5/synth_ecp5.cc | 4 ++-- techlibs/lattice/Makefile.inc | 1 + .../{ecp5/ecp5_gsr.cc => lattice/lattice_gsr.cc} | 10 +++++----- techlibs/machxo2/synth_machxo2.cc | 2 +- 6 files changed, 17 insertions(+), 16 deletions(-) create mode 100644 techlibs/lattice/Makefile.inc rename techlibs/{ecp5/ecp5_gsr.cc => lattice/lattice_gsr.cc} (93%) diff --git a/passes/opt/opt_lut_ins.cc b/passes/opt/opt_lut_ins.cc index 2f7c392b29a..652fce1e2d5 100644 --- a/passes/opt/opt_lut_ins.cc +++ b/passes/opt/opt_lut_ins.cc @@ -39,7 +39,7 @@ struct OptLutInsPass : public Pass { log("\n"); log(" -tech \n"); log(" Instead of generic $lut cells, operate on LUT cells specific\n"); - log(" to the given technology. Valid values are: xilinx, ecp5, gowin.\n"); + log(" to the given technology. Valid values are: xilinx, lattice, gowin.\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *design) override @@ -58,7 +58,7 @@ struct OptLutInsPass : public Pass { } extra_args(args, argidx, design); - if (techname != "" && techname != "xilinx" && techname != "ecp5" && techname != "gowin") + if (techname != "" && techname != "xilinx" && techname != "lattice" && techname != "ecp5" && techname != "gowin") log_cmd_error("Unsupported technology: '%s'\n", techname.c_str()); for (auto module : design->selected_modules()) @@ -130,7 +130,7 @@ struct OptLutInsPass : public Pass { output = cell->getPort(ID::O); else output = cell->getPort(ID::F); - } else if (techname == "ecp5") { + } else if (techname == "lattice" || techname == "ecp5") { if (cell->type == ID(LUT4)) { inputs = { cell->getPort(ID::A), @@ -181,7 +181,7 @@ struct OptLutInsPass : public Pass { if (!doit) continue; log(" Optimizing lut %s (%d -> %d)\n", log_id(cell), GetSize(inputs), GetSize(new_inputs)); - if (techname == "ecp5") { + if (techname == "lattice" || techname == "ecp5") { // Pad the LUT to 4 inputs, adding consts from the front. int extra = 4 - GetSize(new_inputs); log_assert(extra >= 0); @@ -215,9 +215,9 @@ struct OptLutInsPass : public Pass { } new_lut[i] = lut[lidx]; } - // For ecp5, and gowin do not replace with a const driver — the nextpnr + // For lattice, and gowin do not replace with a const driver — the nextpnr // packer requires a complete set of LUTs for wide LUT muxes. - if (new_inputs.empty() && techname != "ecp5" && techname != "gowin") { + if (new_inputs.empty() && techname != "lattice" && techname != "ecp5" && techname != "gowin") { // const driver. remove_cells.push_back(cell); module->connect(output, new_lut[0]); @@ -226,7 +226,7 @@ struct OptLutInsPass : public Pass { cell->setParam(ID::LUT, new_lut); cell->setParam(ID::WIDTH, GetSize(new_inputs)); cell->setPort(ID::A, new_inputs); - } else if (techname == "ecp5") { + } else if (techname == "lattice" || techname == "ecp5") { log_assert(GetSize(new_inputs) == 4); cell->setParam(ID::INIT, new_lut); cell->setPort(ID::A, new_inputs[0]); diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc index f9fa79ab9ad..a1c9bfc5233 100644 --- a/techlibs/ecp5/Makefile.inc +++ b/techlibs/ecp5/Makefile.inc @@ -1,5 +1,5 @@ -OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_gsr.o +OBJS += techlibs/ecp5/synth_ecp5.o $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_ff.vh)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_io.vh)) diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 82e23486844..fdc36e55267 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -359,7 +359,7 @@ struct SynthEcp5Pass : public ScriptPass run("techmap -D NO_LUT -map +/ecp5/cells_map.v"); run("opt_expr -undriven -mux_undef"); run("simplemap"); - run("ecp5_gsr"); + run("lattice_gsr"); run("attrmvcp -copy -attr syn_useioff"); run("opt_clean"); } @@ -404,7 +404,7 @@ struct SynthEcp5Pass : public ScriptPass run("techmap -map +/ecp5/cells_map.v", "(skip if -vpr)"); else if (!vpr) run("techmap -map +/ecp5/cells_map.v"); - run("opt_lut_ins -tech ecp5"); + run("opt_lut_ins -tech lattice"); run("clean"); } diff --git a/techlibs/lattice/Makefile.inc b/techlibs/lattice/Makefile.inc new file mode 100644 index 00000000000..b198de0cc11 --- /dev/null +++ b/techlibs/lattice/Makefile.inc @@ -0,0 +1 @@ +OBJS += techlibs/lattice/lattice_gsr.o diff --git a/techlibs/ecp5/ecp5_gsr.cc b/techlibs/lattice/lattice_gsr.cc similarity index 93% rename from techlibs/ecp5/ecp5_gsr.cc rename to techlibs/lattice/lattice_gsr.cc index 62b231aab3b..d7d41eca519 100644 --- a/techlibs/ecp5/ecp5_gsr.cc +++ b/techlibs/lattice/lattice_gsr.cc @@ -24,13 +24,13 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -struct Ecp5GsrPass : public Pass { - Ecp5GsrPass() : Pass("ecp5_gsr", "ECP5: handle GSR") { } +struct LatticeGsrPass : public Pass { + LatticeGsrPass() : Pass("lattice_gsr", "Lattice: handle GSR") { } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" ecp5_gsr [options] [selection]\n"); + log(" lattice_gsr [options] [selection]\n"); log("\n"); log("Trim active low async resets connected to GSR and resolve GSR parameter,\n"); log("if a GSR or SGSR primitive is used in the design.\n"); @@ -42,7 +42,7 @@ struct Ecp5GsrPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { - log_header(design, "Executing ECP5_GSR pass (implement FF init values).\n"); + log_header(design, "Executing LATTICE_GSR pass (implement FF init values).\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -130,6 +130,6 @@ struct Ecp5GsrPass : public Pass { } } -} Ecp5GsrPass; +} LatticeGsrPass; PRIVATE_NAMESPACE_END diff --git a/techlibs/machxo2/synth_machxo2.cc b/techlibs/machxo2/synth_machxo2.cc index 2b684a7d8fd..907c6659ed8 100644 --- a/techlibs/machxo2/synth_machxo2.cc +++ b/techlibs/machxo2/synth_machxo2.cc @@ -239,7 +239,7 @@ struct SynthMachXO2Pass : public ScriptPass run("techmap -D NO_LUT -map +/machxo2/cells_map.v"); run("opt_expr -undriven -mux_undef"); run("simplemap"); - run("ecp5_gsr"); + run("lattice_gsr"); run("attrmvcp -copy -attr syn_useioff"); run("opt_clean"); } From e3c15f003e1d976c4d27c2ffc08196b50576bd26 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 23 Aug 2023 10:53:21 +0200 Subject: [PATCH 2/7] Create synth_lattice --- techlibs/lattice/Makefile.inc | 26 + techlibs/lattice/arith_map_ccu2c.v | 90 +++ techlibs/lattice/arith_map_ccu2d.v | 90 +++ techlibs/lattice/brams_16kd.txt | 52 ++ techlibs/lattice/brams_8kc.txt | 50 ++ techlibs/lattice/brams_map_16kd.v | 489 +++++++++++++ techlibs/lattice/brams_map_8kc.v | 337 +++++++++ techlibs/lattice/ccu2c_sim.vh | 61 ++ techlibs/lattice/ccu2d_sim.vh | 33 + techlibs/lattice/cells_bb_ecp5.v | 1067 ++++++++++++++++++++++++++++ techlibs/lattice/cells_bb_xo2.v | 293 ++++++++ techlibs/lattice/cells_bb_xo3.v | 293 ++++++++ techlibs/lattice/cells_bb_xo3d.v | 293 ++++++++ techlibs/lattice/cells_ff.vh | 40 ++ techlibs/lattice/cells_io.vh | 14 + techlibs/lattice/cells_map.v | 191 +++++ techlibs/lattice/cells_sim_ecp5.v | 9 + techlibs/lattice/cells_sim_xo2.v | 9 + techlibs/lattice/cells_sim_xo3.v | 9 + techlibs/lattice/cells_sim_xo3d.v | 9 + techlibs/lattice/common_sim.vh | 402 +++++++++++ techlibs/lattice/dsp_map_18x18.v | 17 + techlibs/lattice/latches_map.v | 11 + techlibs/lattice/lutrams.txt | 12 + techlibs/lattice/lutrams_map.v | 30 + techlibs/lattice/synth_lattice.cc | 574 +++++++++++++++ 26 files changed, 4501 insertions(+) create mode 100644 techlibs/lattice/arith_map_ccu2c.v create mode 100644 techlibs/lattice/arith_map_ccu2d.v create mode 100644 techlibs/lattice/brams_16kd.txt create mode 100644 techlibs/lattice/brams_8kc.txt create mode 100644 techlibs/lattice/brams_map_16kd.v create mode 100644 techlibs/lattice/brams_map_8kc.v create mode 100644 techlibs/lattice/ccu2c_sim.vh create mode 100644 techlibs/lattice/ccu2d_sim.vh create mode 100644 techlibs/lattice/cells_bb_ecp5.v create mode 100644 techlibs/lattice/cells_bb_xo2.v create mode 100644 techlibs/lattice/cells_bb_xo3.v create mode 100644 techlibs/lattice/cells_bb_xo3d.v create mode 100644 techlibs/lattice/cells_ff.vh create mode 100644 techlibs/lattice/cells_io.vh create mode 100644 techlibs/lattice/cells_map.v create mode 100644 techlibs/lattice/cells_sim_ecp5.v create mode 100644 techlibs/lattice/cells_sim_xo2.v create mode 100644 techlibs/lattice/cells_sim_xo3.v create mode 100644 techlibs/lattice/cells_sim_xo3d.v create mode 100644 techlibs/lattice/common_sim.vh create mode 100644 techlibs/lattice/dsp_map_18x18.v create mode 100644 techlibs/lattice/latches_map.v create mode 100644 techlibs/lattice/lutrams.txt create mode 100644 techlibs/lattice/lutrams_map.v create mode 100644 techlibs/lattice/synth_lattice.cc diff --git a/techlibs/lattice/Makefile.inc b/techlibs/lattice/Makefile.inc index b198de0cc11..4a908fa3ead 100644 --- a/techlibs/lattice/Makefile.inc +++ b/techlibs/lattice/Makefile.inc @@ -1 +1,27 @@ + +OBJS += techlibs/lattice/synth_lattice.o OBJS += techlibs/lattice/lattice_gsr.o + +$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_ff.vh)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_io.vh)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_map.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/common_sim.vh)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/ccu2d_sim.vh)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/ccu2c_sim.vh)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_ecp5.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo2.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo3.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo3d.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_ecp5.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_xo2.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_xo3.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams_map.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams.txt)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_map_16kd.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_16kd.txt)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_map_8kc.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_8kc.txt)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/arith_map_ccu2c.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/arith_map_ccu2d.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/latches_map.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/dsp_map_18x18.v)) diff --git a/techlibs/lattice/arith_map_ccu2c.v b/techlibs/lattice/arith_map_ccu2c.v new file mode 100644 index 00000000000..a5efc35613a --- /dev/null +++ b/techlibs/lattice/arith_map_ccu2c.v @@ -0,0 +1,90 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * Copyright (C) 2018 gatecat + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +(* techmap_celltype = "$alu" *) +module _80_ccu2c_alu (A, B, CI, BI, X, Y, CO); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + (* force_downto *) + input [A_WIDTH-1:0] A; + (* force_downto *) + input [B_WIDTH-1:0] B; + (* force_downto *) + output [Y_WIDTH-1:0] X, Y; + + input CI, BI; + (* force_downto *) + output [Y_WIDTH-1:0] CO; + + wire _TECHMAP_FAIL_ = Y_WIDTH <= 4; + + (* force_downto *) + wire [Y_WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + + function integer round_up2; + input integer N; + begin + round_up2 = ((N + 1) / 2) * 2; + end + endfunction + + localparam Y_WIDTH2 = round_up2(Y_WIDTH); + + (* force_downto *) + wire [Y_WIDTH2-1:0] AA = A_buf; + (* force_downto *) + wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf; + (* force_downto *) + wire [Y_WIDTH2-1:0] BX = B_buf; + (* force_downto *) + wire [Y_WIDTH2-1:0] C = {CO, CI}; + (* force_downto *) + wire [Y_WIDTH2-1:0] FCO, Y1; + + genvar i; + generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice + CCU2C #( + .INIT0(16'b1001011010101010), + .INIT1(16'b1001011010101010), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) ccu2c_i ( + .CIN(C[i]), + .A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b1), + .A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b1), + .S0(Y[i]), .S1(Y1[i]), + .COUT(FCO[i]) + ); + + assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i])); + if (i+1 < Y_WIDTH) begin + assign CO[i+1] = FCO[i]; + assign Y[i+1] = Y1[i]; + end + end endgenerate + + assign X = AA ^ BB; +endmodule diff --git a/techlibs/lattice/arith_map_ccu2d.v b/techlibs/lattice/arith_map_ccu2d.v new file mode 100644 index 00000000000..31e4afe09a1 --- /dev/null +++ b/techlibs/lattice/arith_map_ccu2d.v @@ -0,0 +1,90 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * Copyright (C) 2018 gatecat + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +(* techmap_celltype = "$alu" *) +module _80_ccu2d_alu (A, B, CI, BI, X, Y, CO); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + (* force_downto *) + input [A_WIDTH-1:0] A; + (* force_downto *) + input [B_WIDTH-1:0] B; + (* force_downto *) + output [Y_WIDTH-1:0] X, Y; + + input CI, BI; + (* force_downto *) + output [Y_WIDTH-1:0] CO; + + wire _TECHMAP_FAIL_ = Y_WIDTH <= 4; + + (* force_downto *) + wire [Y_WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + + function integer round_up2; + input integer N; + begin + round_up2 = ((N + 1) / 2) * 2; + end + endfunction + + localparam Y_WIDTH2 = round_up2(Y_WIDTH); + + (* force_downto *) + wire [Y_WIDTH2-1:0] AA = A_buf; + (* force_downto *) + wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf; + (* force_downto *) + wire [Y_WIDTH2-1:0] BX = B_buf; + (* force_downto *) + wire [Y_WIDTH2-1:0] C = {CO, CI}; + (* force_downto *) + wire [Y_WIDTH2-1:0] FCO, Y1; + + genvar i; + generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice + CCU2D #( + .INIT0(16'b0101_1010_1001_0110), + .INIT1(16'b0101_1010_1001_0110), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) ccu2d_i ( + .CIN(C[i]), + .A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b0), + .A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b0), + .S0(Y[i]), .S1(Y1[i]), + .COUT(FCO[i]) + ); + + assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i])); + if (i+1 < Y_WIDTH) begin + assign CO[i+1] = FCO[i]; + assign Y[i+1] = Y1[i]; + end + end endgenerate + + assign X = AA ^ BB; +endmodule diff --git a/techlibs/lattice/brams_16kd.txt b/techlibs/lattice/brams_16kd.txt new file mode 100644 index 00000000000..ccdf490501f --- /dev/null +++ b/techlibs/lattice/brams_16kd.txt @@ -0,0 +1,52 @@ +ram block $__DP16KD_ { + abits 14; + widths 1 2 4 9 18 per_port; + byte 9; + cost 128; + init no_undef; + port srsw "A" "B" { + clock anyedge; + clken; + wrbe_separate; + portoption "WRITEMODE" "NORMAL" { + rdwr no_change; + } + portoption "WRITEMODE" "WRITETHROUGH" { + rdwr new; + } + portoption "WRITEMODE" "READBEFOREWRITE" { + rdwr old; + } + option "RESETMODE" "SYNC" { + rdsrst zero ungated block_wr; + } + option "RESETMODE" "ASYNC" { + rdarst zero; + } + rdinit zero; + } +} + +ram block $__PDPW16KD_ { + abits 14; + widths 1 2 4 9 18 36 per_port; + byte 9; + cost 128; + init no_undef; + port sr "R" { + clock anyedge; + clken; + option "RESETMODE" "SYNC" { + rdsrst zero ungated; + } + option "RESETMODE" "ASYNC" { + rdarst zero; + } + rdinit zero; + } + port sw "W" { + width 36; + clock anyedge; + clken; + } +} diff --git a/techlibs/lattice/brams_8kc.txt b/techlibs/lattice/brams_8kc.txt new file mode 100644 index 00000000000..3afbeda07e6 --- /dev/null +++ b/techlibs/lattice/brams_8kc.txt @@ -0,0 +1,50 @@ +ram block $__DP8KC_ { + abits 13; + widths 1 2 4 9 per_port; + cost 64; + init no_undef; + port srsw "A" "B" { + clock posedge; + clken; + portoption "WRITEMODE" "NORMAL" { + rdwr no_change; + } + portoption "WRITEMODE" "WRITETHROUGH" { + rdwr new; + } + portoption "WRITEMODE" "READBEFOREWRITE" { + rdwr old; + } + option "RESETMODE" "SYNC" { + rdsrst zero ungated block_wr; + } + option "RESETMODE" "ASYNC" { + rdarst zero; + } + rdinit zero; + } +} + +ram block $__PDPW8KC_ { + abits 13; + widths 1 2 4 9 18 per_port; + byte 9; + cost 64; + init no_undef; + port sr "R" { + clock posedge; + clken; + option "RESETMODE" "SYNC" { + rdsrst zero ungated; + } + option "RESETMODE" "ASYNC" { + rdarst zero; + } + rdinit zero; + } + port sw "W" { + width 18; + clock posedge; + clken; + } +} diff --git a/techlibs/lattice/brams_map_16kd.v b/techlibs/lattice/brams_map_16kd.v new file mode 100644 index 00000000000..da4d8041770 --- /dev/null +++ b/techlibs/lattice/brams_map_16kd.v @@ -0,0 +1,489 @@ +module $__DP16KD_ (...); + +parameter INIT = 0; +parameter OPTION_RESETMODE = "SYNC"; + +parameter PORT_A_WIDTH = 18; +parameter PORT_A_WR_BE_WIDTH = 2; +parameter PORT_A_CLK_POL = 1; +parameter PORT_A_OPTION_WRITEMODE = "NORMAL"; + +input PORT_A_CLK; +input PORT_A_CLK_EN; +input PORT_A_WR_EN; +input PORT_A_RD_SRST; +input PORT_A_RD_ARST; +input [13:0] PORT_A_ADDR; +input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE; +input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA; +output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA; + +parameter PORT_B_WIDTH = 18; +parameter PORT_B_WR_BE_WIDTH = 2; +parameter PORT_B_CLK_POL = 1; +parameter PORT_B_OPTION_WRITEMODE = "NORMAL"; + +input PORT_B_CLK; +input PORT_B_CLK_EN; +input PORT_B_WR_EN; +input PORT_B_RD_SRST; +input PORT_B_RD_ARST; +input [13:0] PORT_B_ADDR; +input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE; +input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA; +output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA; + +function [319:0] init_slice; + input integer idx; + integer i, j; + init_slice = 0; + for (i = 0; i < 16; i = i + 1) begin + init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18]; + end +endfunction + +wire [17:0] DOA; +wire [17:0] DOB; +wire [17:0] DIA = PORT_A_WR_DATA; +wire [17:0] DIB = PORT_B_WR_DATA; + +assign PORT_A_RD_DATA = DOA; +assign PORT_B_RD_DATA = DOB; + +DP16KD #( + .INITVAL_00(init_slice('h00)), + .INITVAL_01(init_slice('h01)), + .INITVAL_02(init_slice('h02)), + .INITVAL_03(init_slice('h03)), + .INITVAL_04(init_slice('h04)), + .INITVAL_05(init_slice('h05)), + .INITVAL_06(init_slice('h06)), + .INITVAL_07(init_slice('h07)), + .INITVAL_08(init_slice('h08)), + .INITVAL_09(init_slice('h09)), + .INITVAL_0A(init_slice('h0a)), + .INITVAL_0B(init_slice('h0b)), + .INITVAL_0C(init_slice('h0c)), + .INITVAL_0D(init_slice('h0d)), + .INITVAL_0E(init_slice('h0e)), + .INITVAL_0F(init_slice('h0f)), + .INITVAL_10(init_slice('h10)), + .INITVAL_11(init_slice('h11)), + .INITVAL_12(init_slice('h12)), + .INITVAL_13(init_slice('h13)), + .INITVAL_14(init_slice('h14)), + .INITVAL_15(init_slice('h15)), + .INITVAL_16(init_slice('h16)), + .INITVAL_17(init_slice('h17)), + .INITVAL_18(init_slice('h18)), + .INITVAL_19(init_slice('h19)), + .INITVAL_1A(init_slice('h1a)), + .INITVAL_1B(init_slice('h1b)), + .INITVAL_1C(init_slice('h1c)), + .INITVAL_1D(init_slice('h1d)), + .INITVAL_1E(init_slice('h1e)), + .INITVAL_1F(init_slice('h1f)), + .INITVAL_20(init_slice('h20)), + .INITVAL_21(init_slice('h21)), + .INITVAL_22(init_slice('h22)), + .INITVAL_23(init_slice('h23)), + .INITVAL_24(init_slice('h24)), + .INITVAL_25(init_slice('h25)), + .INITVAL_26(init_slice('h26)), + .INITVAL_27(init_slice('h27)), + .INITVAL_28(init_slice('h28)), + .INITVAL_29(init_slice('h29)), + .INITVAL_2A(init_slice('h2a)), + .INITVAL_2B(init_slice('h2b)), + .INITVAL_2C(init_slice('h2c)), + .INITVAL_2D(init_slice('h2d)), + .INITVAL_2E(init_slice('h2e)), + .INITVAL_2F(init_slice('h2f)), + .INITVAL_30(init_slice('h30)), + .INITVAL_31(init_slice('h31)), + .INITVAL_32(init_slice('h32)), + .INITVAL_33(init_slice('h33)), + .INITVAL_34(init_slice('h34)), + .INITVAL_35(init_slice('h35)), + .INITVAL_36(init_slice('h36)), + .INITVAL_37(init_slice('h37)), + .INITVAL_38(init_slice('h38)), + .INITVAL_39(init_slice('h39)), + .INITVAL_3A(init_slice('h3a)), + .INITVAL_3B(init_slice('h3b)), + .INITVAL_3C(init_slice('h3c)), + .INITVAL_3D(init_slice('h3d)), + .INITVAL_3E(init_slice('h3e)), + .INITVAL_3F(init_slice('h3f)), + .DATA_WIDTH_A(PORT_A_WIDTH), + .DATA_WIDTH_B(PORT_B_WIDTH), + .REGMODE_A("NOREG"), + .REGMODE_B("NOREG"), + .RESETMODE(OPTION_RESETMODE), + .ASYNC_RESET_RELEASE(OPTION_RESETMODE), + .CSDECODE_A("0b000"), + .CSDECODE_B("0b000"), + .CLKAMUX(PORT_A_CLK_POL ? "CLKA" : "INV"), + .CLKBMUX(PORT_B_CLK_POL ? "CLKB" : "INV"), + .WRITEMODE_A(PORT_A_OPTION_WRITEMODE), + .WRITEMODE_B(PORT_B_OPTION_WRITEMODE), + .GSR("AUTO") +) _TECHMAP_REPLACE_ ( + .CLKA(PORT_A_CLK), + .WEA(PORT_A_WIDTH == 18 ? PORT_A_WR_EN : (PORT_A_WR_EN | PORT_A_WR_BE[0])), + .CEA(PORT_A_CLK_EN), + .OCEA(1'b1), + .RSTA(OPTION_RESETMODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST), + .CSA0(1'b0), + .CSA1(1'b0), + .CSA2(1'b0), + .ADA0(PORT_A_WIDTH == 18 ? PORT_A_WR_BE[0] : PORT_A_ADDR[0]), + .ADA1(PORT_A_WIDTH == 18 ? PORT_A_WR_BE[1] : PORT_A_ADDR[1]), + .ADA2(PORT_A_ADDR[2]), + .ADA3(PORT_A_ADDR[3]), + .ADA4(PORT_A_ADDR[4]), + .ADA5(PORT_A_ADDR[5]), + .ADA6(PORT_A_ADDR[6]), + .ADA7(PORT_A_ADDR[7]), + .ADA8(PORT_A_ADDR[8]), + .ADA9(PORT_A_ADDR[9]), + .ADA10(PORT_A_ADDR[10]), + .ADA11(PORT_A_ADDR[11]), + .ADA12(PORT_A_ADDR[12]), + .ADA13(PORT_A_ADDR[13]), + .DIA0(DIA[0]), + .DIA1(DIA[1]), + .DIA2(DIA[2]), + .DIA3(DIA[3]), + .DIA4(DIA[4]), + .DIA5(DIA[5]), + .DIA6(DIA[6]), + .DIA7(DIA[7]), + .DIA8(DIA[8]), + .DIA9(DIA[9]), + .DIA10(DIA[10]), + .DIA11(DIA[11]), + .DIA12(DIA[12]), + .DIA13(DIA[13]), + .DIA14(DIA[14]), + .DIA15(DIA[15]), + .DIA16(DIA[16]), + .DIA17(DIA[17]), + .DOA0(DOA[0]), + .DOA1(DOA[1]), + .DOA2(DOA[2]), + .DOA3(DOA[3]), + .DOA4(DOA[4]), + .DOA5(DOA[5]), + .DOA6(DOA[6]), + .DOA7(DOA[7]), + .DOA8(DOA[8]), + .DOA9(DOA[9]), + .DOA10(DOA[10]), + .DOA11(DOA[11]), + .DOA12(DOA[12]), + .DOA13(DOA[13]), + .DOA14(DOA[14]), + .DOA15(DOA[15]), + .DOA16(DOA[16]), + .DOA17(DOA[17]), + + .CLKB(PORT_B_CLK), + .WEB(PORT_B_WIDTH == 18 ? PORT_B_WR_EN : (PORT_B_WR_EN | PORT_B_WR_BE[0])), + .CEB(PORT_B_CLK_EN), + .OCEB(1'b1), + .RSTB(OPTION_RESETMODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST), + .CSB0(1'b0), + .CSB1(1'b0), + .CSB2(1'b0), + .ADB0(PORT_B_WIDTH == 18 ? PORT_B_WR_BE[0] : PORT_B_ADDR[0]), + .ADB1(PORT_B_WIDTH == 18 ? PORT_B_WR_BE[1] : PORT_B_ADDR[1]), + .ADB2(PORT_B_ADDR[2]), + .ADB3(PORT_B_ADDR[3]), + .ADB4(PORT_B_ADDR[4]), + .ADB5(PORT_B_ADDR[5]), + .ADB6(PORT_B_ADDR[6]), + .ADB7(PORT_B_ADDR[7]), + .ADB8(PORT_B_ADDR[8]), + .ADB9(PORT_B_ADDR[9]), + .ADB10(PORT_B_ADDR[10]), + .ADB11(PORT_B_ADDR[11]), + .ADB12(PORT_B_ADDR[12]), + .ADB13(PORT_B_ADDR[13]), + .DIB0(DIB[0]), + .DIB1(DIB[1]), + .DIB2(DIB[2]), + .DIB3(DIB[3]), + .DIB4(DIB[4]), + .DIB5(DIB[5]), + .DIB6(DIB[6]), + .DIB7(DIB[7]), + .DIB8(DIB[8]), + .DIB9(DIB[9]), + .DIB10(DIB[10]), + .DIB11(DIB[11]), + .DIB12(DIB[12]), + .DIB13(DIB[13]), + .DIB14(DIB[14]), + .DIB15(DIB[15]), + .DIB16(DIB[16]), + .DIB17(DIB[17]), + .DOB0(DOB[0]), + .DOB1(DOB[1]), + .DOB2(DOB[2]), + .DOB3(DOB[3]), + .DOB4(DOB[4]), + .DOB5(DOB[5]), + .DOB6(DOB[6]), + .DOB7(DOB[7]), + .DOB8(DOB[8]), + .DOB9(DOB[9]), + .DOB10(DOB[10]), + .DOB11(DOB[11]), + .DOB12(DOB[12]), + .DOB13(DOB[13]), + .DOB14(DOB[14]), + .DOB15(DOB[15]), + .DOB16(DOB[16]), + .DOB17(DOB[17]), +); + +endmodule + + +module $__PDPW16KD_ (...); + +parameter INIT = 0; +parameter OPTION_RESETMODE = "SYNC"; + +parameter PORT_R_WIDTH = 36; +parameter PORT_R_CLK_POL = 1; + +input PORT_R_CLK; +input PORT_R_CLK_EN; +input PORT_R_RD_SRST; +input PORT_R_RD_ARST; +input [13:0] PORT_R_ADDR; +output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA; + +parameter PORT_W_WIDTH = 36; +parameter PORT_W_WR_EN_WIDTH = 4; +parameter PORT_W_CLK_POL = 1; + +input PORT_W_CLK; +input PORT_W_CLK_EN; +input [13:0] PORT_W_ADDR; +input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN; +input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA; + +function [319:0] init_slice; + input integer idx; + integer i, j; + init_slice = 0; + for (i = 0; i < 16; i = i + 1) begin + init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18]; + end +endfunction + +wire [35:0] DI = PORT_W_WR_DATA; +wire [35:0] DO; + +assign PORT_R_RD_DATA = PORT_R_WIDTH == 36 ? DO : DO[35:18]; + +DP16KD #( + .INITVAL_00(init_slice('h00)), + .INITVAL_01(init_slice('h01)), + .INITVAL_02(init_slice('h02)), + .INITVAL_03(init_slice('h03)), + .INITVAL_04(init_slice('h04)), + .INITVAL_05(init_slice('h05)), + .INITVAL_06(init_slice('h06)), + .INITVAL_07(init_slice('h07)), + .INITVAL_08(init_slice('h08)), + .INITVAL_09(init_slice('h09)), + .INITVAL_0A(init_slice('h0a)), + .INITVAL_0B(init_slice('h0b)), + .INITVAL_0C(init_slice('h0c)), + .INITVAL_0D(init_slice('h0d)), + .INITVAL_0E(init_slice('h0e)), + .INITVAL_0F(init_slice('h0f)), + .INITVAL_10(init_slice('h10)), + .INITVAL_11(init_slice('h11)), + .INITVAL_12(init_slice('h12)), + .INITVAL_13(init_slice('h13)), + .INITVAL_14(init_slice('h14)), + .INITVAL_15(init_slice('h15)), + .INITVAL_16(init_slice('h16)), + .INITVAL_17(init_slice('h17)), + .INITVAL_18(init_slice('h18)), + .INITVAL_19(init_slice('h19)), + .INITVAL_1A(init_slice('h1a)), + .INITVAL_1B(init_slice('h1b)), + .INITVAL_1C(init_slice('h1c)), + .INITVAL_1D(init_slice('h1d)), + .INITVAL_1E(init_slice('h1e)), + .INITVAL_1F(init_slice('h1f)), + .INITVAL_20(init_slice('h20)), + .INITVAL_21(init_slice('h21)), + .INITVAL_22(init_slice('h22)), + .INITVAL_23(init_slice('h23)), + .INITVAL_24(init_slice('h24)), + .INITVAL_25(init_slice('h25)), + .INITVAL_26(init_slice('h26)), + .INITVAL_27(init_slice('h27)), + .INITVAL_28(init_slice('h28)), + .INITVAL_29(init_slice('h29)), + .INITVAL_2A(init_slice('h2a)), + .INITVAL_2B(init_slice('h2b)), + .INITVAL_2C(init_slice('h2c)), + .INITVAL_2D(init_slice('h2d)), + .INITVAL_2E(init_slice('h2e)), + .INITVAL_2F(init_slice('h2f)), + .INITVAL_30(init_slice('h30)), + .INITVAL_31(init_slice('h31)), + .INITVAL_32(init_slice('h32)), + .INITVAL_33(init_slice('h33)), + .INITVAL_34(init_slice('h34)), + .INITVAL_35(init_slice('h35)), + .INITVAL_36(init_slice('h36)), + .INITVAL_37(init_slice('h37)), + .INITVAL_38(init_slice('h38)), + .INITVAL_39(init_slice('h39)), + .INITVAL_3A(init_slice('h3a)), + .INITVAL_3B(init_slice('h3b)), + .INITVAL_3C(init_slice('h3c)), + .INITVAL_3D(init_slice('h3d)), + .INITVAL_3E(init_slice('h3e)), + .INITVAL_3F(init_slice('h3f)), + .DATA_WIDTH_A(PORT_W_WIDTH), + .DATA_WIDTH_B(PORT_R_WIDTH), + .REGMODE_A("NOREG"), + .REGMODE_B("NOREG"), + .RESETMODE(OPTION_RESETMODE), + .ASYNC_RESET_RELEASE(OPTION_RESETMODE), + .CSDECODE_A("0b000"), + .CSDECODE_B("0b000"), + .CLKAMUX(PORT_W_CLK_POL ? "CLKA" : "INV"), + .CLKBMUX(PORT_R_CLK_POL ? "CLKB" : "INV"), + .GSR("AUTO") +) _TECHMAP_REPLACE_ ( + .CLKA(PORT_W_CLK), + .WEA(PORT_W_WIDTH >= 18 ? 1'b1 : PORT_W_WR_EN[0]), + .CEA(PORT_W_CLK_EN), + .OCEA(1'b0), + .RSTA(1'b0), + .CSA0(1'b0), + .CSA1(1'b0), + .CSA2(1'b0), + .ADA0(PORT_W_WIDTH >= 18 ? PORT_W_WR_EN[0] : PORT_W_ADDR[0]), + .ADA1(PORT_W_WIDTH >= 18 ? PORT_W_WR_EN[1] : PORT_W_ADDR[1]), + .ADA2(PORT_W_WIDTH >= 36 ? PORT_W_WR_EN[2] : PORT_W_ADDR[2]), + .ADA3(PORT_W_WIDTH >= 36 ? PORT_W_WR_EN[3] : PORT_W_ADDR[3]), + .ADA4(PORT_W_ADDR[4]), + .ADA5(PORT_W_ADDR[5]), + .ADA6(PORT_W_ADDR[6]), + .ADA7(PORT_W_ADDR[7]), + .ADA8(PORT_W_ADDR[8]), + .ADA9(PORT_W_ADDR[9]), + .ADA10(PORT_W_ADDR[10]), + .ADA11(PORT_W_ADDR[11]), + .ADA12(PORT_W_ADDR[12]), + .ADA13(PORT_W_ADDR[13]), + .DIA0(DI[0]), + .DIA1(DI[1]), + .DIA2(DI[2]), + .DIA3(DI[3]), + .DIA4(DI[4]), + .DIA5(DI[5]), + .DIA6(DI[6]), + .DIA7(DI[7]), + .DIA8(DI[8]), + .DIA9(DI[9]), + .DIA10(DI[10]), + .DIA11(DI[11]), + .DIA12(DI[12]), + .DIA13(DI[13]), + .DIA14(DI[14]), + .DIA15(DI[15]), + .DIA16(DI[16]), + .DIA17(DI[17]), + .DIB0(DI[18]), + .DIB1(DI[19]), + .DIB2(DI[20]), + .DIB3(DI[21]), + .DIB4(DI[22]), + .DIB5(DI[23]), + .DIB6(DI[24]), + .DIB7(DI[25]), + .DIB8(DI[26]), + .DIB9(DI[27]), + .DIB10(DI[28]), + .DIB11(DI[29]), + .DIB12(DI[30]), + .DIB13(DI[31]), + .DIB14(DI[32]), + .DIB15(DI[33]), + .DIB16(DI[34]), + .DIB17(DI[35]), + + .CLKB(PORT_R_CLK), + .WEB(1'b0), + .CEB(PORT_R_CLK_EN), + .OCEB(1'b1), + .RSTB(OPTION_RESETMODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST), + .CSB0(1'b0), + .CSB1(1'b0), + .CSB2(1'b0), + .ADB0(PORT_R_ADDR[0]), + .ADB1(PORT_R_ADDR[1]), + .ADB2(PORT_R_ADDR[2]), + .ADB3(PORT_R_ADDR[3]), + .ADB4(PORT_R_ADDR[4]), + .ADB5(PORT_R_ADDR[5]), + .ADB6(PORT_R_ADDR[6]), + .ADB7(PORT_R_ADDR[7]), + .ADB8(PORT_R_ADDR[8]), + .ADB9(PORT_R_ADDR[9]), + .ADB10(PORT_R_ADDR[10]), + .ADB11(PORT_R_ADDR[11]), + .ADB12(PORT_R_ADDR[12]), + .ADB13(PORT_R_ADDR[13]), + .DOA0(DO[0]), + .DOA1(DO[1]), + .DOA2(DO[2]), + .DOA3(DO[3]), + .DOA4(DO[4]), + .DOA5(DO[5]), + .DOA6(DO[6]), + .DOA7(DO[7]), + .DOA8(DO[8]), + .DOA9(DO[9]), + .DOA10(DO[10]), + .DOA11(DO[11]), + .DOA12(DO[12]), + .DOA13(DO[13]), + .DOA14(DO[14]), + .DOA15(DO[15]), + .DOA16(DO[16]), + .DOA17(DO[17]), + .DOB0(DO[18]), + .DOB1(DO[19]), + .DOB2(DO[20]), + .DOB3(DO[21]), + .DOB4(DO[22]), + .DOB5(DO[23]), + .DOB6(DO[24]), + .DOB7(DO[25]), + .DOB8(DO[26]), + .DOB9(DO[27]), + .DOB10(DO[28]), + .DOB11(DO[29]), + .DOB12(DO[30]), + .DOB13(DO[31]), + .DOB14(DO[32]), + .DOB15(DO[33]), + .DOB16(DO[34]), + .DOB17(DO[35]), +); + +endmodule diff --git a/techlibs/lattice/brams_map_8kc.v b/techlibs/lattice/brams_map_8kc.v new file mode 100644 index 00000000000..6783e5b2902 --- /dev/null +++ b/techlibs/lattice/brams_map_8kc.v @@ -0,0 +1,337 @@ +module $__DP8KC_ (...); + +parameter INIT = 0; +parameter OPTION_RESETMODE = "SYNC"; + +parameter PORT_A_WIDTH = 18; +parameter PORT_A_OPTION_WRITEMODE = "NORMAL"; + +input PORT_A_CLK; +input PORT_A_CLK_EN; +input PORT_A_WR_EN; +input PORT_A_RD_SRST; +input PORT_A_RD_ARST; +input [12:0] PORT_A_ADDR; +input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA; +output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA; + +parameter PORT_B_WIDTH = 18; +parameter PORT_B_OPTION_WRITEMODE = "NORMAL"; + +input PORT_B_CLK; +input PORT_B_CLK_EN; +input PORT_B_WR_EN; +input PORT_B_RD_SRST; +input PORT_B_RD_ARST; +input [12:0] PORT_B_ADDR; +input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA; +output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA; + +function [319:0] init_slice; + input integer idx; + integer i, j; + init_slice = 0; + for (i = 0; i < 16; i = i + 1) begin + init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18]; + end +endfunction + +wire [8:0] DOA; +wire [8:0] DOB; +wire [8:0] DIA = PORT_A_WR_DATA; +wire [8:0] DIB = PORT_B_WR_DATA; + +assign PORT_A_RD_DATA = DOA; +assign PORT_B_RD_DATA = DOB; + +DP8KC #( + .INITVAL_00(init_slice('h00)), + .INITVAL_01(init_slice('h01)), + .INITVAL_02(init_slice('h02)), + .INITVAL_03(init_slice('h03)), + .INITVAL_04(init_slice('h04)), + .INITVAL_05(init_slice('h05)), + .INITVAL_06(init_slice('h06)), + .INITVAL_07(init_slice('h07)), + .INITVAL_08(init_slice('h08)), + .INITVAL_09(init_slice('h09)), + .INITVAL_0A(init_slice('h0a)), + .INITVAL_0B(init_slice('h0b)), + .INITVAL_0C(init_slice('h0c)), + .INITVAL_0D(init_slice('h0d)), + .INITVAL_0E(init_slice('h0e)), + .INITVAL_0F(init_slice('h0f)), + .INITVAL_10(init_slice('h10)), + .INITVAL_11(init_slice('h11)), + .INITVAL_12(init_slice('h12)), + .INITVAL_13(init_slice('h13)), + .INITVAL_14(init_slice('h14)), + .INITVAL_15(init_slice('h15)), + .INITVAL_16(init_slice('h16)), + .INITVAL_17(init_slice('h17)), + .INITVAL_18(init_slice('h18)), + .INITVAL_19(init_slice('h19)), + .INITVAL_1A(init_slice('h1a)), + .INITVAL_1B(init_slice('h1b)), + .INITVAL_1C(init_slice('h1c)), + .INITVAL_1D(init_slice('h1d)), + .INITVAL_1E(init_slice('h1e)), + .INITVAL_1F(init_slice('h1f)), + .DATA_WIDTH_A(PORT_A_WIDTH), + .DATA_WIDTH_B(PORT_B_WIDTH), + .REGMODE_A("NOREG"), + .REGMODE_B("NOREG"), + .RESETMODE(OPTION_RESETMODE), + .ASYNC_RESET_RELEASE(OPTION_RESETMODE), + .CSDECODE_A("0b000"), + .CSDECODE_B("0b000"), + .WRITEMODE_A(PORT_A_OPTION_WRITEMODE), + .WRITEMODE_B(PORT_B_OPTION_WRITEMODE), + .GSR("AUTO") +) _TECHMAP_REPLACE_ ( + .CLKA(PORT_A_CLK), + .WEA(PORT_A_WR_EN), + .CEA(PORT_A_CLK_EN), + .OCEA(1'b1), + .RSTA(OPTION_RESETMODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST), + .CSA0(1'b0), + .CSA1(1'b0), + .CSA2(1'b0), + .ADA0(PORT_A_WIDTH == 9 ? 1'b1 : PORT_A_ADDR[0]), + .ADA1(PORT_A_ADDR[1]), + .ADA2(PORT_A_ADDR[2]), + .ADA3(PORT_A_ADDR[3]), + .ADA4(PORT_A_ADDR[4]), + .ADA5(PORT_A_ADDR[5]), + .ADA6(PORT_A_ADDR[6]), + .ADA7(PORT_A_ADDR[7]), + .ADA8(PORT_A_ADDR[8]), + .ADA9(PORT_A_ADDR[9]), + .ADA10(PORT_A_ADDR[10]), + .ADA11(PORT_A_ADDR[11]), + .ADA12(PORT_A_ADDR[12]), + .DIA0(DIA[0]), + .DIA1(DIA[1]), + .DIA2(DIA[2]), + .DIA3(DIA[3]), + .DIA4(DIA[4]), + .DIA5(DIA[5]), + .DIA6(DIA[6]), + .DIA7(DIA[7]), + .DIA8(DIA[8]), + .DOA0(DOA[0]), + .DOA1(DOA[1]), + .DOA2(DOA[2]), + .DOA3(DOA[3]), + .DOA4(DOA[4]), + .DOA5(DOA[5]), + .DOA6(DOA[6]), + .DOA7(DOA[7]), + .DOA8(DOA[8]), + + .CLKB(PORT_B_CLK), + .WEB(PORT_B_WR_EN), + .CEB(PORT_B_CLK_EN), + .OCEB(1'b1), + .RSTB(OPTION_RESETMODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST), + .CSB0(1'b0), + .CSB1(1'b0), + .CSB2(1'b0), + .ADB0(PORT_B_WIDTH == 9 ? 1'b1 : PORT_B_ADDR[0]), + .ADB1(PORT_B_ADDR[1]), + .ADB2(PORT_B_ADDR[2]), + .ADB3(PORT_B_ADDR[3]), + .ADB4(PORT_B_ADDR[4]), + .ADB5(PORT_B_ADDR[5]), + .ADB6(PORT_B_ADDR[6]), + .ADB7(PORT_B_ADDR[7]), + .ADB8(PORT_B_ADDR[8]), + .ADB9(PORT_B_ADDR[9]), + .ADB10(PORT_B_ADDR[10]), + .ADB11(PORT_B_ADDR[11]), + .ADB12(PORT_B_ADDR[12]), + .DIB0(DIB[0]), + .DIB1(DIB[1]), + .DIB2(DIB[2]), + .DIB3(DIB[3]), + .DIB4(DIB[4]), + .DIB5(DIB[5]), + .DIB6(DIB[6]), + .DIB7(DIB[7]), + .DIB8(DIB[8]), + .DOB0(DOB[0]), + .DOB1(DOB[1]), + .DOB2(DOB[2]), + .DOB3(DOB[3]), + .DOB4(DOB[4]), + .DOB5(DOB[5]), + .DOB6(DOB[6]), + .DOB7(DOB[7]), + .DOB8(DOB[8]), +); + +endmodule + + +module $__PDPW8KC_ (...); + +parameter INIT = 0; +parameter OPTION_RESETMODE = "SYNC"; + +parameter PORT_R_WIDTH = 18; + +input PORT_R_CLK; +input PORT_R_CLK_EN; +input PORT_R_RD_SRST; +input PORT_R_RD_ARST; +input [12:0] PORT_R_ADDR; +output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA; + +parameter PORT_W_WIDTH = 18; +parameter PORT_W_WR_EN_WIDTH = 2; + +input PORT_W_CLK; +input PORT_W_CLK_EN; +input [12:0] PORT_W_ADDR; +input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN; +input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA; + +function [319:0] init_slice; + input integer idx; + integer i, j; + init_slice = 0; + for (i = 0; i < 16; i = i + 1) begin + init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18]; + end +endfunction + +wire [17:0] DI = PORT_W_WR_DATA; +wire [17:0] DO; + +assign PORT_R_RD_DATA = PORT_R_WIDTH == 18 ? DO : DO[17:9]; + +DP8KC #( + .INITVAL_00(init_slice('h00)), + .INITVAL_01(init_slice('h01)), + .INITVAL_02(init_slice('h02)), + .INITVAL_03(init_slice('h03)), + .INITVAL_04(init_slice('h04)), + .INITVAL_05(init_slice('h05)), + .INITVAL_06(init_slice('h06)), + .INITVAL_07(init_slice('h07)), + .INITVAL_08(init_slice('h08)), + .INITVAL_09(init_slice('h09)), + .INITVAL_0A(init_slice('h0a)), + .INITVAL_0B(init_slice('h0b)), + .INITVAL_0C(init_slice('h0c)), + .INITVAL_0D(init_slice('h0d)), + .INITVAL_0E(init_slice('h0e)), + .INITVAL_0F(init_slice('h0f)), + .INITVAL_10(init_slice('h10)), + .INITVAL_11(init_slice('h11)), + .INITVAL_12(init_slice('h12)), + .INITVAL_13(init_slice('h13)), + .INITVAL_14(init_slice('h14)), + .INITVAL_15(init_slice('h15)), + .INITVAL_16(init_slice('h16)), + .INITVAL_17(init_slice('h17)), + .INITVAL_18(init_slice('h18)), + .INITVAL_19(init_slice('h19)), + .INITVAL_1A(init_slice('h1a)), + .INITVAL_1B(init_slice('h1b)), + .INITVAL_1C(init_slice('h1c)), + .INITVAL_1D(init_slice('h1d)), + .INITVAL_1E(init_slice('h1e)), + .INITVAL_1F(init_slice('h1f)), + .DATA_WIDTH_A(PORT_W_WIDTH), + .DATA_WIDTH_B(PORT_R_WIDTH), + .REGMODE_A("NOREG"), + .REGMODE_B("NOREG"), + .RESETMODE(OPTION_RESETMODE), + .ASYNC_RESET_RELEASE(OPTION_RESETMODE), + .CSDECODE_A("0b000"), + .CSDECODE_B("0b000"), + .GSR("AUTO") +) _TECHMAP_REPLACE_ ( + .CLKA(PORT_W_CLK), + .WEA(PORT_W_WIDTH >= 9 ? 1'b1 : PORT_W_WR_EN[0]), + .CEA(PORT_W_CLK_EN), + .OCEA(1'b0), + .RSTA(1'b0), + .CSA0(1'b0), + .CSA1(1'b0), + .CSA2(1'b0), + .ADA0(PORT_W_WIDTH >= 9 ? PORT_W_WR_EN[0] : PORT_W_ADDR[0]), + .ADA1(PORT_W_WIDTH >= 18 ? PORT_W_WR_EN[1] : PORT_W_ADDR[1]), + .ADA2(PORT_W_ADDR[2]), + .ADA3(PORT_W_ADDR[3]), + .ADA4(PORT_W_ADDR[4]), + .ADA5(PORT_W_ADDR[5]), + .ADA6(PORT_W_ADDR[6]), + .ADA7(PORT_W_ADDR[7]), + .ADA8(PORT_W_ADDR[8]), + .ADA9(PORT_W_ADDR[9]), + .ADA10(PORT_W_ADDR[10]), + .ADA11(PORT_W_ADDR[11]), + .ADA12(PORT_W_ADDR[12]), + .DIA0(DI[0]), + .DIA1(DI[1]), + .DIA2(DI[2]), + .DIA3(DI[3]), + .DIA4(DI[4]), + .DIA5(DI[5]), + .DIA6(DI[6]), + .DIA7(DI[7]), + .DIA8(DI[8]), + .DIB0(DI[9]), + .DIB1(DI[10]), + .DIB2(DI[11]), + .DIB3(DI[12]), + .DIB4(DI[13]), + .DIB5(DI[14]), + .DIB6(DI[15]), + .DIB7(DI[16]), + .DIB8(DI[17]), + + .CLKB(PORT_R_CLK), + .WEB(1'b0), + .CEB(PORT_R_CLK_EN), + .OCEB(1'b1), + .RSTB(OPTION_RESETMODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST), + .CSB0(1'b0), + .CSB1(1'b0), + .CSB2(1'b0), + .ADB0(PORT_R_ADDR[0]), + .ADB1(PORT_R_ADDR[1]), + .ADB2(PORT_R_ADDR[2]), + .ADB3(PORT_R_ADDR[3]), + .ADB4(PORT_R_ADDR[4]), + .ADB5(PORT_R_ADDR[5]), + .ADB6(PORT_R_ADDR[6]), + .ADB7(PORT_R_ADDR[7]), + .ADB8(PORT_R_ADDR[8]), + .ADB9(PORT_R_ADDR[9]), + .ADB10(PORT_R_ADDR[10]), + .ADB11(PORT_R_ADDR[11]), + .ADB12(PORT_R_ADDR[12]), + .DOA0(DO[0]), + .DOA1(DO[1]), + .DOA2(DO[2]), + .DOA3(DO[3]), + .DOA4(DO[4]), + .DOA5(DO[5]), + .DOA6(DO[6]), + .DOA7(DO[7]), + .DOA8(DO[8]), + .DOB0(DO[9]), + .DOB1(DO[10]), + .DOB2(DO[11]), + .DOB3(DO[12]), + .DOB4(DO[13]), + .DOB5(DO[14]), + .DOB6(DO[15]), + .DOB7(DO[16]), + .DOB8(DO[17]), +); + +endmodule diff --git a/techlibs/lattice/ccu2c_sim.vh b/techlibs/lattice/ccu2c_sim.vh new file mode 100644 index 00000000000..d9eb69ab455 --- /dev/null +++ b/techlibs/lattice/ccu2c_sim.vh @@ -0,0 +1,61 @@ +// --------------------------------------- +(* abc9_box, lib_whitebox *) +module CCU2C( + (* abc9_carry *) + input CIN, + input A0, B0, C0, D0, A1, B1, C1, D1, + output S0, S1, + (* abc9_carry *) + output COUT +); + parameter [15:0] INIT0 = 16'h0000; + parameter [15:0] INIT1 = 16'h0000; + parameter INJECT1_0 = "YES"; + parameter INJECT1_1 = "YES"; + + // First half + wire LUT4_0, LUT2_0; + LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0)); + LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0)); + wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN; + assign S0 = LUT4_0 ^ gated_cin_0; + + wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0; + wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN); + + // Second half + wire LUT4_1, LUT2_1; + LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1)); + LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1)); + wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0; + assign S1 = LUT4_1 ^ gated_cin_1; + + wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1; + assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0); + + specify + (A0 => S0) = 379; + (B0 => S0) = 379; + (C0 => S0) = 275; + (D0 => S0) = 141; + (CIN => S0) = 257; + (A0 => S1) = 630; + (B0 => S1) = 630; + (C0 => S1) = 526; + (D0 => S1) = 392; + (A1 => S1) = 379; + (B1 => S1) = 379; + (C1 => S1) = 275; + (D1 => S1) = 141; + (CIN => S1) = 273; + (A0 => COUT) = 516; + (B0 => COUT) = 516; + (C0 => COUT) = 412; + (D0 => COUT) = 278; + (A1 => COUT) = 516; + (B1 => COUT) = 516; + (C1 => COUT) = 412; + (D1 => COUT) = 278; + (CIN => COUT) = 43; + endspecify +endmodule diff --git a/techlibs/lattice/ccu2d_sim.vh b/techlibs/lattice/ccu2d_sim.vh new file mode 100644 index 00000000000..5b9c95cc9ef --- /dev/null +++ b/techlibs/lattice/ccu2d_sim.vh @@ -0,0 +1,33 @@ +// --------------------------------------- +(* lib_whitebox *) +module CCU2D ( + input CIN, + input A0, B0, C0, D0, A1, B1, C1, D1, + output S0, S1, + output COUT +); + parameter [15:0] INIT0 = 16'h0000; + parameter [15:0] INIT1 = 16'h0000; + parameter INJECT1_0 = "YES"; + parameter INJECT1_1 = "YES"; + + // First half + wire LUT4_0, LUT2_0; + LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0)); + LUT2 #(.INIT(~INIT0[15:12])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0)); + wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN; + assign S0 = LUT4_0 ^ gated_cin_0; + + wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0; + wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN); + + // Second half + wire LUT4_1, LUT2_1; + LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1)); + LUT2 #(.INIT(~INIT1[15:12])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1)); + wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0; + assign S1 = LUT4_1 ^ gated_cin_1; + + wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1; + assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0); +endmodule diff --git a/techlibs/lattice/cells_bb_ecp5.v b/techlibs/lattice/cells_bb_ecp5.v new file mode 100644 index 00000000000..5cb90b97efc --- /dev/null +++ b/techlibs/lattice/cells_bb_ecp5.v @@ -0,0 +1,1067 @@ +// ECP5 Blackbox cells +// FIXME: Create sim models + +(* blackbox *) +module DP16KD( + input DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9, DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, + input ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0, + input CEA, OCEA, CLKA, WEA, RSTA, + input CSA2, CSA1, CSA0, + output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, + + input DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0, + input ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, + input CEB, OCEB, CLKB, WEB, RSTB, + input CSB2, CSB1, CSB0, + output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0 +); + parameter DATA_WIDTH_A = 18; + parameter DATA_WIDTH_B = 18; + + parameter REGMODE_A = "NOREG"; + parameter REGMODE_B = "NOREG"; + + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + + parameter CSDECODE_A = "0b000"; + parameter CSDECODE_B = "0b000"; + + parameter WRITEMODE_A = "NORMAL"; + parameter WRITEMODE_B = "NORMAL"; + + parameter DIA17MUX = "DIA17"; + parameter DIA16MUX = "DIA16"; + parameter DIA15MUX = "DIA15"; + parameter DIA14MUX = "DIA14"; + parameter DIA13MUX = "DIA13"; + parameter DIA12MUX = "DIA12"; + parameter DIA11MUX = "DIA11"; + parameter DIA10MUX = "DIA10"; + parameter DIA9MUX = "DIA9"; + parameter DIA8MUX = "DIA8"; + parameter DIA7MUX = "DIA7"; + parameter DIA6MUX = "DIA6"; + parameter DIA5MUX = "DIA5"; + parameter DIA4MUX = "DIA4"; + parameter DIA3MUX = "DIA3"; + parameter DIA2MUX = "DIA2"; + parameter DIA1MUX = "DIA1"; + parameter DIA0MUX = "DIA0"; + parameter ADA13MUX = "ADA13"; + parameter ADA12MUX = "ADA12"; + parameter ADA11MUX = "ADA11"; + parameter ADA10MUX = "ADA10"; + parameter ADA9MUX = "ADA9"; + parameter ADA8MUX = "ADA8"; + parameter ADA7MUX = "ADA7"; + parameter ADA6MUX = "ADA6"; + parameter ADA5MUX = "ADA5"; + parameter ADA4MUX = "ADA4"; + parameter ADA3MUX = "ADA3"; + parameter ADA2MUX = "ADA2"; + parameter ADA1MUX = "ADA1"; + parameter ADA0MUX = "ADA0"; + parameter CEAMUX = "CEA"; + parameter OCEAMUX = "OCEA"; + parameter CLKAMUX = "CLKA"; + parameter WEAMUX = "WEA"; + parameter RSTAMUX = "RSTA"; + parameter CSA2MUX = "CSA2"; + parameter CSA1MUX = "CSA1"; + parameter CSA0MUX = "CSA0"; + parameter DOA17MUX = "DOA17"; + parameter DOA16MUX = "DOA16"; + parameter DOA15MUX = "DOA15"; + parameter DOA14MUX = "DOA14"; + parameter DOA13MUX = "DOA13"; + parameter DOA12MUX = "DOA12"; + parameter DOA11MUX = "DOA11"; + parameter DOA10MUX = "DOA10"; + parameter DOA9MUX = "DOA9"; + parameter DOA8MUX = "DOA8"; + parameter DOA7MUX = "DOA7"; + parameter DOA6MUX = "DOA6"; + parameter DOA5MUX = "DOA5"; + parameter DOA4MUX = "DOA4"; + parameter DOA3MUX = "DOA3"; + parameter DOA2MUX = "DOA2"; + parameter DOA1MUX = "DOA1"; + parameter DOA0MUX = "DOA0"; + parameter DIB17MUX = "DIB17"; + parameter DIB16MUX = "DIB16"; + parameter DIB15MUX = "DIB15"; + parameter DIB14MUX = "DIB14"; + parameter DIB13MUX = "DIB13"; + parameter DIB12MUX = "DIB12"; + parameter DIB11MUX = "DIB11"; + parameter DIB10MUX = "DIB10"; + parameter DIB9MUX = "DIB9"; + parameter DIB8MUX = "DIB8"; + parameter DIB7MUX = "DIB7"; + parameter DIB6MUX = "DIB6"; + parameter DIB5MUX = "DIB5"; + parameter DIB4MUX = "DIB4"; + parameter DIB3MUX = "DIB3"; + parameter DIB2MUX = "DIB2"; + parameter DIB1MUX = "DIB1"; + parameter DIB0MUX = "DIB0"; + parameter ADB13MUX = "ADB13"; + parameter ADB12MUX = "ADB12"; + parameter ADB11MUX = "ADB11"; + parameter ADB10MUX = "ADB10"; + parameter ADB9MUX = "ADB9"; + parameter ADB8MUX = "ADB8"; + parameter ADB7MUX = "ADB7"; + parameter ADB6MUX = "ADB6"; + parameter ADB5MUX = "ADB5"; + parameter ADB4MUX = "ADB4"; + parameter ADB3MUX = "ADB3"; + parameter ADB2MUX = "ADB2"; + parameter ADB1MUX = "ADB1"; + parameter ADB0MUX = "ADB0"; + parameter CEBMUX = "CEB"; + parameter OCEBMUX = "OCEB"; + parameter CLKBMUX = "CLKB"; + parameter WEBMUX = "WEB"; + parameter RSTBMUX = "RSTB"; + parameter CSB2MUX = "CSB2"; + parameter CSB1MUX = "CSB1"; + parameter CSB0MUX = "CSB0"; + parameter DOB17MUX = "DOB17"; + parameter DOB16MUX = "DOB16"; + parameter DOB15MUX = "DOB15"; + parameter DOB14MUX = "DOB14"; + parameter DOB13MUX = "DOB13"; + parameter DOB12MUX = "DOB12"; + parameter DOB11MUX = "DOB11"; + parameter DOB10MUX = "DOB10"; + parameter DOB9MUX = "DOB9"; + parameter DOB8MUX = "DOB8"; + parameter DOB7MUX = "DOB7"; + parameter DOB6MUX = "DOB6"; + parameter DOB5MUX = "DOB5"; + parameter DOB4MUX = "DOB4"; + parameter DOB3MUX = "DOB3"; + parameter DOB2MUX = "DOB2"; + parameter DOB1MUX = "DOB1"; + parameter DOB0MUX = "DOB0"; + + parameter WID = 0; + + parameter GSR = "ENABLED"; + + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_DATA = "STATIC"; +endmodule + +(* blackbox *) +module MULT18X18D( + input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, + input B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, + input C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, + input SIGNEDA, SIGNEDB, SOURCEA, SOURCEB, + input CLK0, CLK1, CLK2, CLK3, + input CE0, CE1, CE2, CE3, + input RST0, RST1, RST2, RST3, + input SRIA0, SRIA1, SRIA2, SRIA3, SRIA4, SRIA5, SRIA6, SRIA7, SRIA8, SRIA9, SRIA10, SRIA11, SRIA12, SRIA13, SRIA14, SRIA15, SRIA16, SRIA17, + input SRIB0, SRIB1, SRIB2, SRIB3, SRIB4, SRIB5, SRIB6, SRIB7, SRIB8, SRIB9, SRIB10, SRIB11, SRIB12, SRIB13, SRIB14, SRIB15, SRIB16, SRIB17, + output SROA0, SROA1, SROA2, SROA3, SROA4, SROA5, SROA6, SROA7, SROA8, SROA9, SROA10, SROA11, SROA12, SROA13, SROA14, SROA15, SROA16, SROA17, + output SROB0, SROB1, SROB2, SROB3, SROB4, SROB5, SROB6, SROB7, SROB8, SROB9, SROB10, SROB11, SROB12, SROB13, SROB14, SROB15, SROB16, SROB17, + output ROA0, ROA1, ROA2, ROA3, ROA4, ROA5, ROA6, ROA7, ROA8, ROA9, ROA10, ROA11, ROA12, ROA13, ROA14, ROA15, ROA16, ROA17, + output ROB0, ROB1, ROB2, ROB3, ROB4, ROB5, ROB6, ROB7, ROB8, ROB9, ROB10, ROB11, ROB12, ROB13, ROB14, ROB15, ROB16, ROB17, + output ROC0, ROC1, ROC2, ROC3, ROC4, ROC5, ROC6, ROC7, ROC8, ROC9, ROC10, ROC11, ROC12, ROC13, ROC14, ROC15, ROC16, ROC17, + output P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26, P27, P28, P29, P30, P31, P32, P33, P34, P35, + output SIGNEDP +); + parameter REG_INPUTA_CLK = "NONE"; + parameter REG_INPUTA_CE = "CE0"; + parameter REG_INPUTA_RST = "RST0"; + parameter REG_INPUTB_CLK = "NONE"; + parameter REG_INPUTB_CE = "CE0"; + parameter REG_INPUTB_RST = "RST0"; + parameter REG_INPUTC_CLK = "NONE"; + parameter REG_INPUTC_CE = "CE0"; + parameter REG_INPUTC_RST = "RST0"; + parameter REG_PIPELINE_CLK = "NONE"; + parameter REG_PIPELINE_CE = "CE0"; + parameter REG_PIPELINE_RST = "RST0"; + parameter REG_OUTPUT_CLK = "NONE"; + parameter REG_OUTPUT_CE = "CE0"; + parameter REG_OUTPUT_RST = "RST0"; + parameter [127:0] CLK0_DIV = "ENABLED"; + parameter [127:0] CLK1_DIV = "ENABLED"; + parameter [127:0] CLK2_DIV = "ENABLED"; + parameter [127:0] CLK3_DIV = "ENABLED"; + parameter HIGHSPEED_CLK = "NONE"; + parameter [127:0] GSR = "ENABLED"; + parameter CAS_MATCH_REG = "FALSE"; + parameter [127:0] SOURCEB_MODE = "B_SHIFT"; + parameter [127:0] MULT_BYPASS = "DISABLED"; + parameter [127:0] RESETMODE = "SYNC"; +endmodule + +(* blackbox *) +module ALU54B( + input CLK0, CLK1, CLK2, CLK3, + input CE0, CE1, CE2, CE3, + input RST0, RST1, RST2, RST3, + input SIGNEDIA, SIGNEDIB, SIGNEDCIN, + input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, A32, A33, A34, A35, + input B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18, B19, B20, B21, B22, B23, B24, B25, B26, B27, B28, B29, B30, B31, B32, B33, B34, B35, + input C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, C37, C38, C39, C40, C41, C42, C43, C44, C45, C46, C47, C48, C49, C50, C51, C52, C53, + input CFB0, CFB1, CFB2, CFB3, CFB4, CFB5, CFB6, CFB7, CFB8, CFB9, CFB10, CFB11, CFB12, CFB13, CFB14, CFB15, CFB16, CFB17, CFB18, CFB19, CFB20, CFB21, CFB22, CFB23, CFB24, CFB25, CFB26, CFB27, CFB28, CFB29, CFB30, CFB31, CFB32, CFB33, CFB34, CFB35, CFB36, CFB37, CFB38, CFB39, CFB40, CFB41, CFB42, CFB43, CFB44, CFB45, CFB46, CFB47, CFB48, CFB49, CFB50, CFB51, CFB52, CFB53, + input MA0, MA1, MA2, MA3, MA4, MA5, MA6, MA7, MA8, MA9, MA10, MA11, MA12, MA13, MA14, MA15, MA16, MA17, MA18, MA19, MA20, MA21, MA22, MA23, MA24, MA25, MA26, MA27, MA28, MA29, MA30, MA31, MA32, MA33, MA34, MA35, + input MB0, MB1, MB2, MB3, MB4, MB5, MB6, MB7, MB8, MB9, MB10, MB11, MB12, MB13, MB14, MB15, MB16, MB17, MB18, MB19, MB20, MB21, MB22, MB23, MB24, MB25, MB26, MB27, MB28, MB29, MB30, MB31, MB32, MB33, MB34, MB35, + input CIN0, CIN1, CIN2, CIN3, CIN4, CIN5, CIN6, CIN7, CIN8, CIN9, CIN10, CIN11, CIN12, CIN13, CIN14, CIN15, CIN16, CIN17, CIN18, CIN19, CIN20, CIN21, CIN22, CIN23, CIN24, CIN25, CIN26, CIN27, CIN28, CIN29, CIN30, CIN31, CIN32, CIN33, CIN34, CIN35, CIN36, CIN37, CIN38, CIN39, CIN40, CIN41, CIN42, CIN43, CIN44, CIN45, CIN46, CIN47, CIN48, CIN49, CIN50, CIN51, CIN52, CIN53, + input OP0, OP1, OP2, OP3, OP4, OP5, OP6, OP7, OP8, OP9, OP10, + output R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, + output CO0, CO1, CO2, CO3, CO4, CO5, CO6, CO7, CO8, CO9, CO10, CO11, CO12, CO13, CO14, CO15, CO16, CO17, CO18, CO19, CO20, CO21, CO22, CO23, CO24, CO25, CO26, CO27, CO28, CO29, CO30, CO31, CO32, CO33, CO34, CO35, CO36, CO37, CO38, CO39, CO40, CO41, CO42, CO43, CO44, CO45, CO46, CO47, CO48, CO49, CO50, CO51, CO52, CO53, + output EQZ, EQZM, EQOM, EQPAT, EQPATB, + output OVER, UNDER, OVERUNDER, + output SIGNEDR +); + parameter REG_INPUTC0_CLK = "NONE"; + parameter REG_INPUTC0_CE = "CE0"; + parameter REG_INPUTC0_RST = "RST0"; + parameter REG_INPUTC1_CLK = "NONE"; + parameter REG_INPUTC1_CE = "CE0"; + parameter REG_INPUTC1_RST = "RST0"; + parameter REG_OPCODEOP0_0_CLK = "NONE"; + parameter REG_OPCODEOP0_0_CE = "CE0"; + parameter REG_OPCODEOP0_0_RST = "RST0"; + parameter REG_OPCODEOP1_0_CLK = "NONE"; + parameter REG_OPCODEOP0_1_CLK = "NONE"; + parameter REG_OPCODEOP0_1_CE = "CE0"; + parameter REG_OPCODEOP0_1_RST = "RST0"; + parameter REG_OPCODEOP1_1_CLK = "NONE"; + parameter REG_OPCODEIN_0_CLK = "NONE"; + parameter REG_OPCODEIN_0_CE = "CE0"; + parameter REG_OPCODEIN_0_RST = "RST0"; + parameter REG_OPCODEIN_1_CLK = "NONE"; + parameter REG_OPCODEIN_1_CE = "CE0"; + parameter REG_OPCODEIN_1_RST = "RST0"; + parameter REG_OUTPUT0_CLK = "NONE"; + parameter REG_OUTPUT0_CE = "CE0"; + parameter REG_OUTPUT0_RST = "RST0"; + parameter REG_OUTPUT1_CLK = "NONE"; + parameter REG_OUTPUT1_CE = "CE0"; + parameter REG_OUTPUT1_RST = "RST0"; + parameter REG_FLAG_CLK = "NONE"; + parameter REG_FLAG_CE = "CE0"; + parameter REG_FLAG_RST = "RST0"; + parameter REG_INPUTCFB_CLK = "NONE"; + parameter REG_INPUTCFB_CE = "CE0"; + parameter REG_INPUTCFB_RST = "RST0"; + parameter [127:0] MCPAT_SOURCE = "STATIC"; + parameter [127:0] MASKPAT_SOURCE = "STATIC"; + parameter MASK01 = "0x00000000000000"; + parameter [127:0] CLK0_DIV = "ENABLED"; + parameter [127:0] CLK1_DIV = "ENABLED"; + parameter [127:0] CLK2_DIV = "ENABLED"; + parameter [127:0] CLK3_DIV = "ENABLED"; + parameter MCPAT = "0x00000000000000"; + parameter MASKPAT = "0x00000000000000"; + parameter RNDPAT = "0x00000000000000"; + parameter [127:0] GSR = "ENABLED"; + parameter [127:0] RESETMODE = "SYNC"; + parameter MULT9_MODE = "DISABLED"; + parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED"; + parameter LEGACY = "DISABLED"; +endmodule + +(* blackbox *) +module EHXPLLL ( + input CLKI, CLKFB, + input PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, PHASELOADREG, + input STDBY, PLLWAKESYNC, + input RST, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, + output CLKOP, CLKOS, CLKOS2, CLKOS3, + output LOCK, INTLOCK, + output REFCLK, CLKINTFB +); + parameter CLKI_DIV = 1; + parameter CLKFB_DIV = 1; + parameter CLKOP_DIV = 8; + parameter CLKOS_DIV = 8; + parameter CLKOS2_DIV = 8; + parameter CLKOS3_DIV = 8; + parameter CLKOP_ENABLE = "ENABLED"; + parameter CLKOS_ENABLE = "DISABLED"; + parameter CLKOS2_ENABLE = "DISABLED"; + parameter CLKOS3_ENABLE = "DISABLED"; + parameter CLKOP_CPHASE = 0; + parameter CLKOS_CPHASE = 0; + parameter CLKOS2_CPHASE = 0; + parameter CLKOS3_CPHASE = 0; + parameter CLKOP_FPHASE = 0; + parameter CLKOS_FPHASE = 0; + parameter CLKOS2_FPHASE = 0; + parameter CLKOS3_FPHASE = 0; + parameter FEEDBK_PATH = "CLKOP"; + parameter CLKOP_TRIM_POL = "RISING"; + parameter CLKOP_TRIM_DELAY = 0; + parameter CLKOS_TRIM_POL = "RISING"; + parameter CLKOS_TRIM_DELAY = 0; + parameter OUTDIVIDER_MUXA = "DIVA"; + parameter OUTDIVIDER_MUXB = "DIVB"; + parameter OUTDIVIDER_MUXC = "DIVC"; + parameter OUTDIVIDER_MUXD = "DIVD"; + parameter PLL_LOCK_MODE = 0; + parameter PLL_LOCK_DELAY = 200; + parameter STDBY_ENABLE = "DISABLED"; + parameter REFIN_RESET = "DISABLED"; + parameter SYNC_ENABLE = "DISABLED"; + parameter INT_LOCK_STICKY = "ENABLED"; + parameter DPHASE_SOURCE = "DISABLED"; + parameter PLLRST_ENA = "DISABLED"; + parameter INTFB_WAKE = "DISABLED"; +endmodule + +(* blackbox *) +module DTR( + input STARTPULSE, + output DTROUT7, DTROUT6, DTROUT5, DTROUT4, DTROUT3, DTROUT2, DTROUT1, DTROUT0 +); +endmodule + +(* blackbox *) +module OSCG( + output OSC +); +parameter DIV = 128; +endmodule + +(* blackbox *) (* keep *) +module USRMCLK( + input USRMCLKI, USRMCLKTS, + output USRMCLKO +); +endmodule + +(* blackbox *) (* keep *) +module JTAGG( + (* iopad_external_pin *) + input TCK, + (* iopad_external_pin *) + input TMS, + (* iopad_external_pin *) + input TDI, + input JTDO2, JTDO1, + (* iopad_external_pin *) + output TDO, + output JTDI, JTCK, JRTI2, JRTI1, + output JSHIFT, JUPDATE, JRSTN, JCE2, JCE1 +); +parameter ER1 = "ENABLED"; +parameter ER2 = "ENABLED"; +endmodule + +(* blackbox *) +module DELAYF( + input A, LOADN, MOVE, DIRECTION, + output Z, CFLAG +); + parameter DEL_MODE = "USER_DEFINED"; + parameter DEL_VALUE = 0; +endmodule + +(* blackbox *) +module DELAYG( + input A, + output Z +); + parameter DEL_MODE = "USER_DEFINED"; + parameter DEL_VALUE = 0; +endmodule + +(* blackbox *) +module IDDRX1F( + input D, SCLK, RST, + output Q0, Q1 +); + parameter GSR = "ENABLED"; +endmodule + +(* blackbox *) +module IDDRX2F( + input D, SCLK, ECLK, RST, ALIGNWD, + output Q0, Q1, Q2, Q3 +); + parameter GSR = "ENABLED"; +endmodule + +(* blackbox *) +module IDDR71B( + input D, SCLK, ECLK, RST, ALIGNWD, + output Q0, Q1, Q2, Q3, Q4, Q5, Q6 +); + parameter GSR = "ENABLED"; +endmodule + +(* blackbox *) +module IDDRX2DQA( + input D, DQSR90, ECLK, SCLK, RST, + input RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, + output Q0, Q1, Q2, Q3, QWL +); + parameter GSR = "ENABLED"; +endmodule + +(* blackbox *) +module ODDRX1F( + input SCLK, RST, D0, D1, + output Q +); + parameter GSR = "ENABLED"; +endmodule + +(* blackbox *) +module ODDRX2F( + input SCLK, ECLK, RST, D0, D1, D2, D3, + output Q +); + parameter GSR = "ENABLED"; +endmodule + +(* blackbox *) +module ODDR71B( + input SCLK, ECLK, RST, D0, D1, D2, D3, D4, D5, D6, + output Q +); + parameter GSR = "ENABLED"; +endmodule + +(* blackbox *) +module OSHX2A( + input D0, D1, RST, ECLK, SCLK, + output Q +); + parameter GSR = "ENABLED"; +endmodule + +(* blackbox *) +module ODDRX2DQA( + input D0, D1, D2, D3, RST, ECLK, SCLK, DQSW270, + output Q +); + parameter GSR = "ENABLED"; +endmodule + +(* blackbox *) +module ODDRX2DQSB( + input D0, D1, D2, D3, RST, ECLK, SCLK, DQSW, + output Q +); + parameter GSR = "ENABLED"; +endmodule + +(* blackbox *) +module TSHX2DQA( + input T0, T1, SCLK, ECLK, DQSW270, RST, + output Q +); + parameter GSR = "ENABLED"; + parameter REGSET = "SET"; +endmodule + +(* blackbox *) +module TSHX2DQSA( + input T0, T1, SCLK, ECLK, DQSW, RST, + output Q +); + parameter GSR = "ENABLED"; + parameter REGSET = "SET"; +endmodule + +(* blackbox *) +module DQSBUFM( + input DQSI, READ1, READ0, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL, + input ECLK, SCLK, + input DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4, + input DYNDELAY3, DYNDELAY2, DYNDELAY1, DYNDELAY0, + input RST, RDLOADN, RDMOVE, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, PAUSE, + output DQSR90, DQSW, DQSW270, + output RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, + output DATAVALID, BURSTDET, RDCFLAG, WRCFLAG +); + parameter DQS_LI_DEL_ADJ = "FACTORYONLY"; + parameter DQS_LI_DEL_VAL = 0; + parameter DQS_LO_DEL_ADJ = "FACTORYONLY"; + parameter DQS_LO_DEL_VAL = 0; + parameter GSR = "ENABLED"; +endmodule + +(* blackbox *) +module DDRDLLA( + input CLK, RST, UDDCNTLN, FREEZE, + output LOCK, DDRDEL, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1, DCNTL0 +); + parameter FORCE_MAX_DELAY = "NO"; + parameter GSR = "ENABLED"; +endmodule + +(* blackbox *) +module DLLDELD( + input A, DDRDEL, LOADN, MOVE, DIRECTION, + output Z, CFLAG +); + parameter DEL_ADJ = "PLUS"; + parameter DEL_VAL = 0; +endmodule + +(* blackbox *) +module CLKDIVF( + input CLKI, RST, ALIGNWD, + output CDIVX +); + parameter GSR = "DISABLED"; + parameter DIV = "2.0"; +endmodule + +(* blackbox *) +module ECLKSYNCB( + input ECLKI, STOP, + output ECLKO +); +endmodule + +(* blackbox *) +module ECLKBRIDGECS( + input CLK0, CLK1, SEL, + output ECSOUT +); +endmodule + +(* blackbox *) +module DCCA( + input CLKI, CE, + output CLKO +); +endmodule + +(* blackbox *) +module DCSC( + input CLK1, CLK0, + input SEL1, SEL0, + input MODESEL, + output DCSOUT +); + parameter DCSMODE = "POS"; +endmodule + +(* blackbox *) (* keep *) +module DCUA( + (* iopad_external_pin *) + input CH0_HDINP, + (* iopad_external_pin *) + input CH1_HDINP, + (* iopad_external_pin *) + input CH0_HDINN, + (* iopad_external_pin *) + input CH1_HDINN, + input D_TXBIT_CLKP_FROM_ND, D_TXBIT_CLKN_FROM_ND, D_SYNC_ND, D_TXPLL_LOL_FROM_ND, + input CH0_RX_REFCLK, CH1_RX_REFCLK, CH0_FF_RXI_CLK, CH1_FF_RXI_CLK, CH0_FF_TXI_CLK, CH1_FF_TXI_CLK, CH0_FF_EBRD_CLK, CH1_FF_EBRD_CLK, + input CH0_FF_TX_D_0, CH1_FF_TX_D_0, CH0_FF_TX_D_1, CH1_FF_TX_D_1, CH0_FF_TX_D_2, CH1_FF_TX_D_2, CH0_FF_TX_D_3, CH1_FF_TX_D_3, + input CH0_FF_TX_D_4, CH1_FF_TX_D_4, CH0_FF_TX_D_5, CH1_FF_TX_D_5, CH0_FF_TX_D_6, CH1_FF_TX_D_6, CH0_FF_TX_D_7, CH1_FF_TX_D_7, + input CH0_FF_TX_D_8, CH1_FF_TX_D_8, CH0_FF_TX_D_9, CH1_FF_TX_D_9, CH0_FF_TX_D_10, CH1_FF_TX_D_10, CH0_FF_TX_D_11, CH1_FF_TX_D_11, + input CH0_FF_TX_D_12, CH1_FF_TX_D_12, CH0_FF_TX_D_13, CH1_FF_TX_D_13, CH0_FF_TX_D_14, CH1_FF_TX_D_14, CH0_FF_TX_D_15, CH1_FF_TX_D_15, + input CH0_FF_TX_D_16, CH1_FF_TX_D_16, CH0_FF_TX_D_17, CH1_FF_TX_D_17, CH0_FF_TX_D_18, CH1_FF_TX_D_18, CH0_FF_TX_D_19, CH1_FF_TX_D_19, + input CH0_FF_TX_D_20, CH1_FF_TX_D_20, CH0_FF_TX_D_21, CH1_FF_TX_D_21, CH0_FF_TX_D_22, CH1_FF_TX_D_22, CH0_FF_TX_D_23, CH1_FF_TX_D_23, + input CH0_FFC_EI_EN, CH1_FFC_EI_EN, CH0_FFC_PCIE_DET_EN, CH1_FFC_PCIE_DET_EN, CH0_FFC_PCIE_CT, CH1_FFC_PCIE_CT, CH0_FFC_SB_INV_RX, CH1_FFC_SB_INV_RX, + input CH0_FFC_ENABLE_CGALIGN, CH1_FFC_ENABLE_CGALIGN, CH0_FFC_SIGNAL_DETECT, CH1_FFC_SIGNAL_DETECT, CH0_FFC_FB_LOOPBACK, CH1_FFC_FB_LOOPBACK, CH0_FFC_SB_PFIFO_LP, CH1_FFC_SB_PFIFO_LP, + input CH0_FFC_PFIFO_CLR, CH1_FFC_PFIFO_CLR, CH0_FFC_RATE_MODE_RX, CH1_FFC_RATE_MODE_RX, CH0_FFC_RATE_MODE_TX, CH1_FFC_RATE_MODE_TX, CH0_FFC_DIV11_MODE_RX, CH1_FFC_DIV11_MODE_RX, CH0_FFC_RX_GEAR_MODE, CH1_FFC_RX_GEAR_MODE, CH0_FFC_TX_GEAR_MODE, CH1_FFC_TX_GEAR_MODE, + input CH0_FFC_DIV11_MODE_TX, CH1_FFC_DIV11_MODE_TX, CH0_FFC_LDR_CORE2TX_EN, CH1_FFC_LDR_CORE2TX_EN, CH0_FFC_LANE_TX_RST, CH1_FFC_LANE_TX_RST, CH0_FFC_LANE_RX_RST, CH1_FFC_LANE_RX_RST, + input CH0_FFC_RRST, CH1_FFC_RRST, CH0_FFC_TXPWDNB, CH1_FFC_TXPWDNB, CH0_FFC_RXPWDNB, CH1_FFC_RXPWDNB, CH0_LDR_CORE2TX, CH1_LDR_CORE2TX, + input D_SCIWDATA0, D_SCIWDATA1, D_SCIWDATA2, D_SCIWDATA3, D_SCIWDATA4, D_SCIWDATA5, D_SCIWDATA6, D_SCIWDATA7, + input D_SCIADDR0, D_SCIADDR1, D_SCIADDR2, D_SCIADDR3, D_SCIADDR4, D_SCIADDR5, D_SCIENAUX, D_SCISELAUX, + input CH0_SCIEN, CH1_SCIEN, CH0_SCISEL, CH1_SCISEL, D_SCIRD, D_SCIWSTN, D_CYAWSTN, D_FFC_SYNC_TOGGLE, + input D_FFC_DUAL_RST, D_FFC_MACRO_RST, D_FFC_MACROPDB, D_FFC_TRST, CH0_FFC_CDR_EN_BITSLIP, CH1_FFC_CDR_EN_BITSLIP, D_SCAN_ENABLE, D_SCAN_IN_0, + input D_SCAN_IN_1, D_SCAN_IN_2, D_SCAN_IN_3, D_SCAN_IN_4, D_SCAN_IN_5, D_SCAN_IN_6, D_SCAN_IN_7, D_SCAN_MODE, + input D_SCAN_RESET, D_CIN0, D_CIN1, D_CIN2, D_CIN3, D_CIN4, D_CIN5, D_CIN6,D_CIN7, D_CIN8, D_CIN9, D_CIN10, D_CIN11, + output CH0_HDOUTP, CH1_HDOUTP, CH0_HDOUTN, CH1_HDOUTN, D_TXBIT_CLKP_TO_ND, D_TXBIT_CLKN_TO_ND, D_SYNC_PULSE2ND, D_TXPLL_LOL_TO_ND, + output CH0_FF_RX_F_CLK, CH1_FF_RX_F_CLK, CH0_FF_RX_H_CLK, CH1_FF_RX_H_CLK, CH0_FF_TX_F_CLK, CH1_FF_TX_F_CLK, CH0_FF_TX_H_CLK, CH1_FF_TX_H_CLK, + output CH0_FF_RX_PCLK, CH1_FF_RX_PCLK, CH0_FF_TX_PCLK, CH1_FF_TX_PCLK, CH0_FF_RX_D_0, CH1_FF_RX_D_0, CH0_FF_RX_D_1, CH1_FF_RX_D_1, + output CH0_FF_RX_D_2, CH1_FF_RX_D_2, CH0_FF_RX_D_3, CH1_FF_RX_D_3, CH0_FF_RX_D_4, CH1_FF_RX_D_4, CH0_FF_RX_D_5, CH1_FF_RX_D_5, + output CH0_FF_RX_D_6, CH1_FF_RX_D_6, CH0_FF_RX_D_7, CH1_FF_RX_D_7, CH0_FF_RX_D_8, CH1_FF_RX_D_8, CH0_FF_RX_D_9, CH1_FF_RX_D_9, + output CH0_FF_RX_D_10, CH1_FF_RX_D_10, CH0_FF_RX_D_11, CH1_FF_RX_D_11, CH0_FF_RX_D_12, CH1_FF_RX_D_12, CH0_FF_RX_D_13, CH1_FF_RX_D_13, + output CH0_FF_RX_D_14, CH1_FF_RX_D_14, CH0_FF_RX_D_15, CH1_FF_RX_D_15, CH0_FF_RX_D_16, CH1_FF_RX_D_16, CH0_FF_RX_D_17, CH1_FF_RX_D_17, + output CH0_FF_RX_D_18, CH1_FF_RX_D_18, CH0_FF_RX_D_19, CH1_FF_RX_D_19, CH0_FF_RX_D_20, CH1_FF_RX_D_20, CH0_FF_RX_D_21, CH1_FF_RX_D_21, + output CH0_FF_RX_D_22, CH1_FF_RX_D_22, CH0_FF_RX_D_23, CH1_FF_RX_D_23, CH0_FFS_PCIE_DONE, CH1_FFS_PCIE_DONE, CH0_FFS_PCIE_CON, CH1_FFS_PCIE_CON, + output CH0_FFS_RLOS, CH1_FFS_RLOS, CH0_FFS_LS_SYNC_STATUS, CH1_FFS_LS_SYNC_STATUS, CH0_FFS_CC_UNDERRUN, CH1_FFS_CC_UNDERRUN, CH0_FFS_CC_OVERRUN, CH1_FFS_CC_OVERRUN, + output CH0_FFS_RXFBFIFO_ERROR, CH1_FFS_RXFBFIFO_ERROR, CH0_FFS_TXFBFIFO_ERROR, CH1_FFS_TXFBFIFO_ERROR, CH0_FFS_RLOL, CH1_FFS_RLOL, CH0_FFS_SKP_ADDED, CH1_FFS_SKP_ADDED, + output CH0_FFS_SKP_DELETED, CH1_FFS_SKP_DELETED, CH0_LDR_RX2CORE, CH1_LDR_RX2CORE, D_SCIRDATA0, D_SCIRDATA1, D_SCIRDATA2, D_SCIRDATA3, + output D_SCIRDATA4, D_SCIRDATA5, D_SCIRDATA6, D_SCIRDATA7, D_SCIINT, D_SCAN_OUT_0, D_SCAN_OUT_1, D_SCAN_OUT_2, D_SCAN_OUT_3, D_SCAN_OUT_4, D_SCAN_OUT_5, D_SCAN_OUT_6, D_SCAN_OUT_7, + output D_COUT0, D_COUT1, D_COUT2, D_COUT3, D_COUT4, D_COUT5, D_COUT6, D_COUT7, D_COUT8, D_COUT9, D_COUT10, D_COUT11, D_COUT12, D_COUT13, D_COUT14, D_COUT15, D_COUT16, D_COUT17, D_COUT18, D_COUT19, + + input D_REFCLKI, + output D_FFS_PLOL +); + parameter CH0_AUTO_CALIB_EN = "0b0"; + parameter CH0_AUTO_FACQ_EN = "0b0"; + parameter CH0_BAND_THRESHOLD = "0b000000"; + parameter CH0_CALIB_CK_MODE = "0b0"; + parameter CH0_CC_MATCH_1 = "0b0000000000"; + parameter CH0_CC_MATCH_2 = "0b0000000000"; + parameter CH0_CC_MATCH_3 = "0b0000000000"; + parameter CH0_CC_MATCH_4 = "0b0000000000"; + parameter CH0_CDR_CNT4SEL = "0b00"; + parameter CH0_CDR_CNT8SEL = "0b00"; + parameter CH0_CTC_BYPASS = "0b0"; + parameter CH0_DCOATDCFG = "0b00"; + parameter CH0_DCOATDDLY = "0b00"; + parameter CH0_DCOBYPSATD = "0b0"; + parameter CH0_DCOCALDIV = "0b000"; + parameter CH0_DCOCTLGI = "0b000"; + parameter CH0_DCODISBDAVOID = "0b0"; + parameter CH0_DCOFLTDAC = "0b00"; + parameter CH0_DCOFTNRG = "0b000"; + parameter CH0_DCOIOSTUNE = "0b000"; + parameter CH0_DCOITUNE = "0b00"; + parameter CH0_DCOITUNE4LSB = "0b000"; + parameter CH0_DCOIUPDNX2 = "0b0"; + parameter CH0_DCONUOFLSB = "0b000"; + parameter CH0_DCOSCALEI = "0b00"; + parameter CH0_DCOSTARTVAL = "0b000"; + parameter CH0_DCOSTEP = "0b00"; + parameter CH0_DEC_BYPASS = "0b0"; + parameter CH0_ENABLE_CG_ALIGN = "0b0"; + parameter CH0_ENC_BYPASS = "0b0"; + parameter CH0_FF_RX_F_CLK_DIS = "0b0"; + parameter CH0_FF_RX_H_CLK_EN = "0b0"; + parameter CH0_FF_TX_F_CLK_DIS = "0b0"; + parameter CH0_FF_TX_H_CLK_EN = "0b0"; + parameter CH0_GE_AN_ENABLE = "0b0"; + parameter CH0_INVERT_RX = "0b0"; + parameter CH0_INVERT_TX = "0b0"; + parameter CH0_LDR_CORE2TX_SEL = "0b0"; + parameter CH0_LDR_RX2CORE_SEL = "0b0"; + parameter CH0_LEQ_OFFSET_SEL = "0b0"; + parameter CH0_LEQ_OFFSET_TRIM = "0b000"; + parameter CH0_LSM_DISABLE = "0b0"; + parameter CH0_MATCH_2_ENABLE = "0b0"; + parameter CH0_MATCH_4_ENABLE = "0b0"; + parameter CH0_MIN_IPG_CNT = "0b00"; + parameter CH0_PCIE_EI_EN = "0b0"; + parameter CH0_PCIE_MODE = "0b0"; + parameter CH0_PCS_DET_TIME_SEL = "0b00"; + parameter CH0_PDEN_SEL = "0b0"; + parameter CH0_PRBS_ENABLE = "0b0"; + parameter CH0_PRBS_LOCK = "0b0"; + parameter CH0_PRBS_SELECTION = "0b0"; + parameter CH0_RATE_MODE_RX = "0b0"; + parameter CH0_RATE_MODE_TX = "0b0"; + parameter CH0_RCV_DCC_EN = "0b0"; + parameter CH0_REG_BAND_OFFSET = "0b0000"; + parameter CH0_REG_BAND_SEL = "0b000000"; + parameter CH0_REG_IDAC_EN = "0b0"; + parameter CH0_REG_IDAC_SEL = "0b0000000000"; + parameter CH0_REQ_EN = "0b0"; + parameter CH0_REQ_LVL_SET = "0b00"; + parameter CH0_RIO_MODE = "0b0"; + parameter CH0_RLOS_SEL = "0b0"; + parameter CH0_RPWDNB = "0b0"; + parameter CH0_RTERM_RX = "0b00000"; + parameter CH0_RTERM_TX = "0b00000"; + parameter CH0_RXIN_CM = "0b00"; + parameter CH0_RXTERM_CM = "0b00"; + parameter CH0_RX_DCO_CK_DIV = "0b000"; + parameter CH0_RX_DIV11_SEL = "0b0"; + parameter CH0_RX_GEAR_BYPASS = "0b0"; + parameter CH0_RX_GEAR_MODE = "0b0"; + parameter CH0_RX_LOS_CEQ = "0b00"; + parameter CH0_RX_LOS_EN = "0b0"; + parameter CH0_RX_LOS_HYST_EN = "0b0"; + parameter CH0_RX_LOS_LVL = "0b000"; + parameter CH0_RX_RATE_SEL = "0b0000"; + parameter CH0_RX_SB_BYPASS = "0b0"; + parameter CH0_SB_BYPASS = "0b0"; + parameter CH0_SEL_SD_RX_CLK = "0b0"; + parameter CH0_TDRV_DAT_SEL = "0b00"; + parameter CH0_TDRV_POST_EN = "0b0"; + parameter CH0_TDRV_PRE_EN = "0b0"; + parameter CH0_TDRV_SLICE0_CUR = "0b000"; + parameter CH0_TDRV_SLICE0_SEL = "0b00"; + parameter CH0_TDRV_SLICE1_CUR = "0b000"; + parameter CH0_TDRV_SLICE1_SEL = "0b00"; + parameter CH0_TDRV_SLICE2_CUR = "0b00"; + parameter CH0_TDRV_SLICE2_SEL = "0b00"; + parameter CH0_TDRV_SLICE3_CUR = "0b00"; + parameter CH0_TDRV_SLICE3_SEL = "0b00"; + parameter CH0_TDRV_SLICE4_CUR = "0b00"; + parameter CH0_TDRV_SLICE4_SEL = "0b00"; + parameter CH0_TDRV_SLICE5_CUR = "0b00"; + parameter CH0_TDRV_SLICE5_SEL = "0b00"; + parameter CH0_TPWDNB = "0b0"; + parameter CH0_TX_CM_SEL = "0b00"; + parameter CH0_TX_DIV11_SEL = "0b0"; + parameter CH0_TX_GEAR_BYPASS = "0b0"; + parameter CH0_TX_GEAR_MODE = "0b0"; + parameter CH0_TX_POST_SIGN = "0b0"; + parameter CH0_TX_PRE_SIGN = "0b0"; + parameter CH0_UC_MODE = "0b0"; + parameter CH0_UDF_COMMA_A = "0b0000000000"; + parameter CH0_UDF_COMMA_B = "0b0000000000"; + parameter CH0_UDF_COMMA_MASK = "0b0000000000"; + parameter CH0_WA_BYPASS = "0b0"; + parameter CH0_WA_MODE = "0b0"; + parameter CH1_AUTO_CALIB_EN = "0b0"; + parameter CH1_AUTO_FACQ_EN = "0b0"; + parameter CH1_BAND_THRESHOLD = "0b000000"; + parameter CH1_CALIB_CK_MODE = "0b0"; + parameter CH1_CC_MATCH_1 = "0b0000000000"; + parameter CH1_CC_MATCH_2 = "0b0000000000"; + parameter CH1_CC_MATCH_3 = "0b0000000000"; + parameter CH1_CC_MATCH_4 = "0b0000000000"; + parameter CH1_CDR_CNT4SEL = "0b00"; + parameter CH1_CDR_CNT8SEL = "0b00"; + parameter CH1_CTC_BYPASS = "0b0"; + parameter CH1_DCOATDCFG = "0b00"; + parameter CH1_DCOATDDLY = "0b00"; + parameter CH1_DCOBYPSATD = "0b0"; + parameter CH1_DCOCALDIV = "0b000"; + parameter CH1_DCOCTLGI = "0b000"; + parameter CH1_DCODISBDAVOID = "0b0"; + parameter CH1_DCOFLTDAC = "0b00"; + parameter CH1_DCOFTNRG = "0b000"; + parameter CH1_DCOIOSTUNE = "0b000"; + parameter CH1_DCOITUNE = "0b00"; + parameter CH1_DCOITUNE4LSB = "0b000"; + parameter CH1_DCOIUPDNX2 = "0b0"; + parameter CH1_DCONUOFLSB = "0b000"; + parameter CH1_DCOSCALEI = "0b00"; + parameter CH1_DCOSTARTVAL = "0b000"; + parameter CH1_DCOSTEP = "0b00"; + parameter CH1_DEC_BYPASS = "0b0"; + parameter CH1_ENABLE_CG_ALIGN = "0b0"; + parameter CH1_ENC_BYPASS = "0b0"; + parameter CH1_FF_RX_F_CLK_DIS = "0b0"; + parameter CH1_FF_RX_H_CLK_EN = "0b0"; + parameter CH1_FF_TX_F_CLK_DIS = "0b0"; + parameter CH1_FF_TX_H_CLK_EN = "0b0"; + parameter CH1_GE_AN_ENABLE = "0b0"; + parameter CH1_INVERT_RX = "0b0"; + parameter CH1_INVERT_TX = "0b0"; + parameter CH1_LDR_CORE2TX_SEL = "0b0"; + parameter CH1_LDR_RX2CORE_SEL = "0b0"; + parameter CH1_LEQ_OFFSET_SEL = "0b0"; + parameter CH1_LEQ_OFFSET_TRIM = "0b000"; + parameter CH1_LSM_DISABLE = "0b0"; + parameter CH1_MATCH_2_ENABLE = "0b0"; + parameter CH1_MATCH_4_ENABLE = "0b0"; + parameter CH1_MIN_IPG_CNT = "0b00"; + parameter CH1_PCIE_EI_EN = "0b0"; + parameter CH1_PCIE_MODE = "0b0"; + parameter CH1_PCS_DET_TIME_SEL = "0b00"; + parameter CH1_PDEN_SEL = "0b0"; + parameter CH1_PRBS_ENABLE = "0b0"; + parameter CH1_PRBS_LOCK = "0b0"; + parameter CH1_PRBS_SELECTION = "0b0"; + parameter CH1_RATE_MODE_RX = "0b0"; + parameter CH1_RATE_MODE_TX = "0b0"; + parameter CH1_RCV_DCC_EN = "0b0"; + parameter CH1_REG_BAND_OFFSET = "0b0000"; + parameter CH1_REG_BAND_SEL = "0b000000"; + parameter CH1_REG_IDAC_EN = "0b0"; + parameter CH1_REG_IDAC_SEL = "0b0000000000"; + parameter CH1_REQ_EN = "0b0"; + parameter CH1_REQ_LVL_SET = "0b00"; + parameter CH1_RIO_MODE = "0b0"; + parameter CH1_RLOS_SEL = "0b0"; + parameter CH1_RPWDNB = "0b0"; + parameter CH1_RTERM_RX = "0b00000"; + parameter CH1_RTERM_TX = "0b00000"; + parameter CH1_RXIN_CM = "0b00"; + parameter CH1_RXTERM_CM = "0b00"; + parameter CH1_RX_DCO_CK_DIV = "0b000"; + parameter CH1_RX_DIV11_SEL = "0b0"; + parameter CH1_RX_GEAR_BYPASS = "0b0"; + parameter CH1_RX_GEAR_MODE = "0b0"; + parameter CH1_RX_LOS_CEQ = "0b00"; + parameter CH1_RX_LOS_EN = "0b0"; + parameter CH1_RX_LOS_HYST_EN = "0b0"; + parameter CH1_RX_LOS_LVL = "0b000"; + parameter CH1_RX_RATE_SEL = "0b0000"; + parameter CH1_RX_SB_BYPASS = "0b0"; + parameter CH1_SB_BYPASS = "0b0"; + parameter CH1_SEL_SD_RX_CLK = "0b0"; + parameter CH1_TDRV_DAT_SEL = "0b00"; + parameter CH1_TDRV_POST_EN = "0b0"; + parameter CH1_TDRV_PRE_EN = "0b0"; + parameter CH1_TDRV_SLICE0_CUR = "0b000"; + parameter CH1_TDRV_SLICE0_SEL = "0b00"; + parameter CH1_TDRV_SLICE1_CUR = "0b000"; + parameter CH1_TDRV_SLICE1_SEL = "0b00"; + parameter CH1_TDRV_SLICE2_CUR = "0b00"; + parameter CH1_TDRV_SLICE2_SEL = "0b00"; + parameter CH1_TDRV_SLICE3_CUR = "0b00"; + parameter CH1_TDRV_SLICE3_SEL = "0b00"; + parameter CH1_TDRV_SLICE4_CUR = "0b00"; + parameter CH1_TDRV_SLICE4_SEL = "0b00"; + parameter CH1_TDRV_SLICE5_CUR = "0b00"; + parameter CH1_TDRV_SLICE5_SEL = "0b00"; + parameter CH1_TPWDNB = "0b0"; + parameter CH1_TX_CM_SEL = "0b00"; + parameter CH1_TX_DIV11_SEL = "0b0"; + parameter CH1_TX_GEAR_BYPASS = "0b0"; + parameter CH1_TX_GEAR_MODE = "0b0"; + parameter CH1_TX_POST_SIGN = "0b0"; + parameter CH1_TX_PRE_SIGN = "0b0"; + parameter CH1_UC_MODE = "0b0"; + parameter CH1_UDF_COMMA_A = "0b0000000000"; + parameter CH1_UDF_COMMA_B = "0b0000000000"; + parameter CH1_UDF_COMMA_MASK = "0b0000000000"; + parameter CH1_WA_BYPASS = "0b0"; + parameter CH1_WA_MODE = "0b0"; + parameter D_BITCLK_FROM_ND_EN = "0b0"; + parameter D_BITCLK_LOCAL_EN = "0b0"; + parameter D_BITCLK_ND_EN = "0b0"; + parameter D_BUS8BIT_SEL = "0b0"; + parameter D_CDR_LOL_SET = "0b00"; + parameter D_CMUSETBIASI = "0b00"; + parameter D_CMUSETI4CPP = "0b0000"; + parameter D_CMUSETI4CPZ = "0b0000"; + parameter D_CMUSETI4VCO = "0b00"; + parameter D_CMUSETICP4P = "0b00"; + parameter D_CMUSETICP4Z = "0b000"; + parameter D_CMUSETINITVCT = "0b00"; + parameter D_CMUSETISCL4VCO = "0b000"; + parameter D_CMUSETP1GM = "0b000"; + parameter D_CMUSETP2AGM = "0b000"; + parameter D_CMUSETZGM = "0b000"; + parameter D_DCO_CALIB_TIME_SEL = "0b00"; + parameter D_HIGH_MARK = "0b0000"; + parameter D_IB_PWDNB = "0b0"; + parameter D_ISETLOS = "0b00000000"; + parameter D_LOW_MARK = "0b0000"; + parameter D_MACROPDB = "0b0"; + parameter D_PD_ISET = "0b00"; + parameter D_PLL_LOL_SET = "0b00"; + parameter D_REFCK_MODE = "0b000"; + parameter D_REQ_ISET = "0b000"; + parameter D_RG_EN = "0b0"; + parameter D_RG_SET = "0b00"; + parameter D_SETICONST_AUX = "0b00"; + parameter D_SETICONST_CH = "0b00"; + parameter D_SETIRPOLY_AUX = "0b00"; + parameter D_SETIRPOLY_CH = "0b00"; + parameter D_SETPLLRC = "0b000000"; + parameter D_SYNC_LOCAL_EN = "0b0"; + parameter D_SYNC_ND_EN = "0b0"; + parameter D_TXPLL_PWDNB = "0b0"; + parameter D_TX_VCO_CK_DIV = "0b000"; + parameter D_XGE_MODE = "0b0"; + +// These parameters don't do anything but are +// needed for compatibility with Diamond + parameter D_TX_MAX_RATE = "2.5"; + parameter D_RX_MAX_RATE = "2.5"; + parameter CH0_TXAMPLITUDE = "0d1300"; + parameter CH1_TXAMPLITUDE = "0d1300"; + parameter CH0_PROTOCOL = "8B10B"; + parameter CH1_PROTOCOL = "8B10B"; + parameter CH0_CDR_MAX_RATE = "2.5"; + parameter CH1_CDR_MAX_RATE = "2.5"; + parameter CH0_TXDEPRE = "DISABLED"; + parameter CH1_TXDEPRE = "DISABLED"; + parameter CH0_TXDEPOST = "DISABLED"; + parameter CH1_TXDEPOST = "DISABLED"; +endmodule + +(* blackbox *) +module EXTREFB ( + (* iopad_external_pin *) + input REFCLKP, + (* iopad_external_pin *) + input REFCLKN, + output REFCLKO +); + parameter REFCK_PWDNB = "0b0"; + parameter REFCK_RTERM = "0b0"; + parameter REFCK_DCBIAS_EN = "0b0"; +endmodule + +(* blackbox *) +module PCSCLKDIV ( + input CLKI, RST, SEL2, SEL1, SEL0, + output CDIV1, CDIVX +); + parameter GSR = "DISABLED"; +endmodule + +// Note: this module is not marked keep as we want it swept away in synth (sim use only) +(* blackbox *) +module PUR ( + input PUR +); + parameter RST_PULSE = 1; +endmodule + +(* blackbox, keep *) +module GSR ( + input GSR +); +endmodule + +(* blackbox, keep *) +module SGSR ( + input GSR, CLK +); +endmodule + + +(* blackbox *) +module PDPW16KD ( + input DI35, DI34, DI33, DI32, DI31, DI30, DI29, DI28, DI27, DI26, DI25, DI24, DI23, DI22, DI21, DI20, DI19, DI18, + input DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, + input ADW8, ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, + input BE3, BE2, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0, + input ADR13, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5, ADR4, ADR3, ADR2, ADR1, ADR0, + input CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, + output DO35, DO34, DO33, DO32, DO31, DO30, DO29, DO28, DO27, DO26, DO25, DO24, DO23, DO22, DO21, DO20, DO19, DO18, + output DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 +); + parameter DATA_WIDTH_W = 36; + parameter DATA_WIDTH_R = 36; + parameter GSR = "ENABLED"; + + parameter REGMODE = "NOREG"; + + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + + parameter CSDECODE_W = "0b000"; + parameter CSDECODE_R = "0b000"; + + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_DATA = "STATIC"; + parameter CLKWMUX = "CLKW"; + parameter CLKRMUX = "CLKR"; + +endmodule diff --git a/techlibs/lattice/cells_bb_xo2.v b/techlibs/lattice/cells_bb_xo2.v new file mode 100644 index 00000000000..3363ed5710d --- /dev/null +++ b/techlibs/lattice/cells_bb_xo2.v @@ -0,0 +1,293 @@ +(* blackbox *) +module DP8KC( + input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, + input ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0, + input CEA, OCEA, CLKA, WEA, RSTA, + input CSA2, CSA1, CSA0, + output DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, + + input DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0, + input ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, + input CEB, OCEB, CLKB, WEB, RSTB, + input CSB2, CSB1, CSB0, + output DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0 +); + parameter DATA_WIDTH_A = 9; + parameter DATA_WIDTH_B = 9; + + parameter REGMODE_A = "NOREG"; + parameter REGMODE_B = "NOREG"; + + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + + parameter CSDECODE_A = "0b000"; + parameter CSDECODE_B = "0b000"; + + parameter WRITEMODE_A = "NORMAL"; + parameter WRITEMODE_B = "NORMAL"; + + parameter GSR = "ENABLED"; + parameter INIT_DATA = "STATIC"; + + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; +endmodule + +(* blackbox *) +module EHXPLLJ ( + input CLKI, CLKFB, + input PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, + input LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD, + input ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE, + input PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0, + input PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0, + output CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK, + output PLLDATO7, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK, + output DPHSRC, CLKINTFB +); + parameter CLKI_DIV = 1; + parameter CLKFB_DIV = 1; + parameter CLKOP_DIV = 8; + parameter CLKOS_DIV = 8; + parameter CLKOS2_DIV = 8; + parameter CLKOS3_DIV = 8; + parameter CLKOP_ENABLE = "ENABLED"; + parameter CLKOS_ENABLE = "ENABLED"; + parameter CLKOS2_ENABLE = "ENABLED"; + parameter CLKOS3_ENABLE = "ENABLED"; + parameter VCO_BYPASS_A0 = "DISABLED"; + parameter VCO_BYPASS_B0 = "DISABLED"; + parameter VCO_BYPASS_C0 = "DISABLED"; + parameter VCO_BYPASS_D0 = "DISABLED"; + parameter CLKOP_CPHASE = 0; + parameter CLKOS_CPHASE = 0; + parameter CLKOS2_CPHASE = 0; + parameter CLKOS3_CPHASE = 0; + parameter CLKOP_FPHASE = 0; + parameter CLKOS_FPHASE = 0; + parameter CLKOS2_FPHASE = 0; + parameter CLKOS3_FPHASE = 0; + parameter FEEDBK_PATH = "CLKOP"; + parameter FRACN_ENABLE = "DISABLED"; + parameter FRACN_DIV = 0; + parameter CLKOP_TRIM_POL = "RISING"; + parameter CLKOP_TRIM_DELAY = 0; + parameter CLKOS_TRIM_POL = "RISING"; + parameter CLKOS_TRIM_DELAY = 0; + parameter PLL_USE_WB = "DISABLED"; + parameter PREDIVIDER_MUXA1 = 0; + parameter PREDIVIDER_MUXB1 = 0; + parameter PREDIVIDER_MUXC1 = 0; + parameter PREDIVIDER_MUXD1 = 0; + parameter OUTDIVIDER_MUXA2 = "DIVA"; + parameter OUTDIVIDER_MUXB2 = "DIVB"; + parameter OUTDIVIDER_MUXC2 = "DIVC"; + parameter OUTDIVIDER_MUXD2 = "DIVD"; + parameter PLL_LOCK_MODE = 0; + parameter STDBY_ENABLE = "DISABLED"; + parameter DPHASE_SOURCE = "DISABLED"; + parameter PLLRST_ENA = "DISABLED"; + parameter MRST_ENA = "DISABLED"; + parameter DCRST_ENA = "DISABLED"; + parameter DDRST_ENA = "DISABLED"; + parameter INTFB_WAKE = "DISABLED"; +endmodule + +(* blackbox *) +module OSCH #( + parameter NOM_FREQ = "2.08" +) ( + input STDBY, + output OSC, + output SEDSTDBY +); +endmodule + +(* blackbox *) +module DCCA ( + input CLKI, + input CE, + output CLKO +); +endmodule + +(* blackbox *) +module DCMA ( + input CLK0, + input CLK1, + input SEL, + output DCMOUT +); +endmodule + +(* blackbox *) +module PDPW8KC ( + input DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, + input ADW8, ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, + input BE1, BE0, + input CEW, CLKW, CSW2, CSW1, CSW0, + input ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5, ADR4, ADR3, ADR2, ADR1, ADR0, + input CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, + output DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 +); + parameter DATA_WIDTH_W = 18; + parameter DATA_WIDTH_R = 9; + + parameter GSR = "ENABLED"; + + parameter REGMODE = "NOREG"; + + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + + parameter CSDECODE_W = "0b000"; + parameter CSDECODE_R = "0b000"; + + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_DATA = "STATIC"; + +endmodule + +(* blackbox *) +module SP8KC ( + input DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, + input AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0, + input CE, OCE, CLK, WE, CS2, CS1, CS0, RST, + output DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 +); + parameter DATA_WIDTH = 9; + parameter GSR = "ENABLED"; + + parameter REGMODE = "NOREG"; + + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + + parameter CSDECODE = "0b000"; + + parameter WRITEMODE = "NORMAL"; + + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_DATA = "STATIC"; +endmodule + +(* blackbox *) +module FIFO8KB ( + input DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, + input CSW0, CSW1, CSR0, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI, + output DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17, + input EF, AEF, AFF, FF +); + parameter DATA_WIDTH_W = 18; + parameter DATA_WIDTH_R = 18; + + parameter GSR = "DISABLED"; + + parameter REGMODE = "NOREG"; + + parameter RESETMODE = "ASYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + + parameter CSDECODE_W = "0b00"; + parameter CSDECODE_R = "0b00"; + + parameter AEPOINTER = "0b00000000000000"; + parameter AEPOINTER1 = "0b00000000000000"; + parameter AFPOINTER = "0b00000000000000"; + parameter AFPOINTER1 = "0b00000000000000"; + parameter FULLPOINTER = "0b00000000000000"; + parameter FULLPOINTER1 = "0b00000000000000"; +endmodule diff --git a/techlibs/lattice/cells_bb_xo3.v b/techlibs/lattice/cells_bb_xo3.v new file mode 100644 index 00000000000..3363ed5710d --- /dev/null +++ b/techlibs/lattice/cells_bb_xo3.v @@ -0,0 +1,293 @@ +(* blackbox *) +module DP8KC( + input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, + input ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0, + input CEA, OCEA, CLKA, WEA, RSTA, + input CSA2, CSA1, CSA0, + output DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, + + input DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0, + input ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, + input CEB, OCEB, CLKB, WEB, RSTB, + input CSB2, CSB1, CSB0, + output DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0 +); + parameter DATA_WIDTH_A = 9; + parameter DATA_WIDTH_B = 9; + + parameter REGMODE_A = "NOREG"; + parameter REGMODE_B = "NOREG"; + + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + + parameter CSDECODE_A = "0b000"; + parameter CSDECODE_B = "0b000"; + + parameter WRITEMODE_A = "NORMAL"; + parameter WRITEMODE_B = "NORMAL"; + + parameter GSR = "ENABLED"; + parameter INIT_DATA = "STATIC"; + + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; +endmodule + +(* blackbox *) +module EHXPLLJ ( + input CLKI, CLKFB, + input PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, + input LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD, + input ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE, + input PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0, + input PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0, + output CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK, + output PLLDATO7, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK, + output DPHSRC, CLKINTFB +); + parameter CLKI_DIV = 1; + parameter CLKFB_DIV = 1; + parameter CLKOP_DIV = 8; + parameter CLKOS_DIV = 8; + parameter CLKOS2_DIV = 8; + parameter CLKOS3_DIV = 8; + parameter CLKOP_ENABLE = "ENABLED"; + parameter CLKOS_ENABLE = "ENABLED"; + parameter CLKOS2_ENABLE = "ENABLED"; + parameter CLKOS3_ENABLE = "ENABLED"; + parameter VCO_BYPASS_A0 = "DISABLED"; + parameter VCO_BYPASS_B0 = "DISABLED"; + parameter VCO_BYPASS_C0 = "DISABLED"; + parameter VCO_BYPASS_D0 = "DISABLED"; + parameter CLKOP_CPHASE = 0; + parameter CLKOS_CPHASE = 0; + parameter CLKOS2_CPHASE = 0; + parameter CLKOS3_CPHASE = 0; + parameter CLKOP_FPHASE = 0; + parameter CLKOS_FPHASE = 0; + parameter CLKOS2_FPHASE = 0; + parameter CLKOS3_FPHASE = 0; + parameter FEEDBK_PATH = "CLKOP"; + parameter FRACN_ENABLE = "DISABLED"; + parameter FRACN_DIV = 0; + parameter CLKOP_TRIM_POL = "RISING"; + parameter CLKOP_TRIM_DELAY = 0; + parameter CLKOS_TRIM_POL = "RISING"; + parameter CLKOS_TRIM_DELAY = 0; + parameter PLL_USE_WB = "DISABLED"; + parameter PREDIVIDER_MUXA1 = 0; + parameter PREDIVIDER_MUXB1 = 0; + parameter PREDIVIDER_MUXC1 = 0; + parameter PREDIVIDER_MUXD1 = 0; + parameter OUTDIVIDER_MUXA2 = "DIVA"; + parameter OUTDIVIDER_MUXB2 = "DIVB"; + parameter OUTDIVIDER_MUXC2 = "DIVC"; + parameter OUTDIVIDER_MUXD2 = "DIVD"; + parameter PLL_LOCK_MODE = 0; + parameter STDBY_ENABLE = "DISABLED"; + parameter DPHASE_SOURCE = "DISABLED"; + parameter PLLRST_ENA = "DISABLED"; + parameter MRST_ENA = "DISABLED"; + parameter DCRST_ENA = "DISABLED"; + parameter DDRST_ENA = "DISABLED"; + parameter INTFB_WAKE = "DISABLED"; +endmodule + +(* blackbox *) +module OSCH #( + parameter NOM_FREQ = "2.08" +) ( + input STDBY, + output OSC, + output SEDSTDBY +); +endmodule + +(* blackbox *) +module DCCA ( + input CLKI, + input CE, + output CLKO +); +endmodule + +(* blackbox *) +module DCMA ( + input CLK0, + input CLK1, + input SEL, + output DCMOUT +); +endmodule + +(* blackbox *) +module PDPW8KC ( + input DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, + input ADW8, ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, + input BE1, BE0, + input CEW, CLKW, CSW2, CSW1, CSW0, + input ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5, ADR4, ADR3, ADR2, ADR1, ADR0, + input CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, + output DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 +); + parameter DATA_WIDTH_W = 18; + parameter DATA_WIDTH_R = 9; + + parameter GSR = "ENABLED"; + + parameter REGMODE = "NOREG"; + + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + + parameter CSDECODE_W = "0b000"; + parameter CSDECODE_R = "0b000"; + + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_DATA = "STATIC"; + +endmodule + +(* blackbox *) +module SP8KC ( + input DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, + input AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0, + input CE, OCE, CLK, WE, CS2, CS1, CS0, RST, + output DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 +); + parameter DATA_WIDTH = 9; + parameter GSR = "ENABLED"; + + parameter REGMODE = "NOREG"; + + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + + parameter CSDECODE = "0b000"; + + parameter WRITEMODE = "NORMAL"; + + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_DATA = "STATIC"; +endmodule + +(* blackbox *) +module FIFO8KB ( + input DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, + input CSW0, CSW1, CSR0, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI, + output DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17, + input EF, AEF, AFF, FF +); + parameter DATA_WIDTH_W = 18; + parameter DATA_WIDTH_R = 18; + + parameter GSR = "DISABLED"; + + parameter REGMODE = "NOREG"; + + parameter RESETMODE = "ASYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + + parameter CSDECODE_W = "0b00"; + parameter CSDECODE_R = "0b00"; + + parameter AEPOINTER = "0b00000000000000"; + parameter AEPOINTER1 = "0b00000000000000"; + parameter AFPOINTER = "0b00000000000000"; + parameter AFPOINTER1 = "0b00000000000000"; + parameter FULLPOINTER = "0b00000000000000"; + parameter FULLPOINTER1 = "0b00000000000000"; +endmodule diff --git a/techlibs/lattice/cells_bb_xo3d.v b/techlibs/lattice/cells_bb_xo3d.v new file mode 100644 index 00000000000..3363ed5710d --- /dev/null +++ b/techlibs/lattice/cells_bb_xo3d.v @@ -0,0 +1,293 @@ +(* blackbox *) +module DP8KC( + input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, + input ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0, + input CEA, OCEA, CLKA, WEA, RSTA, + input CSA2, CSA1, CSA0, + output DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, + + input DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0, + input ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, + input CEB, OCEB, CLKB, WEB, RSTB, + input CSB2, CSB1, CSB0, + output DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0 +); + parameter DATA_WIDTH_A = 9; + parameter DATA_WIDTH_B = 9; + + parameter REGMODE_A = "NOREG"; + parameter REGMODE_B = "NOREG"; + + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + + parameter CSDECODE_A = "0b000"; + parameter CSDECODE_B = "0b000"; + + parameter WRITEMODE_A = "NORMAL"; + parameter WRITEMODE_B = "NORMAL"; + + parameter GSR = "ENABLED"; + parameter INIT_DATA = "STATIC"; + + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; +endmodule + +(* blackbox *) +module EHXPLLJ ( + input CLKI, CLKFB, + input PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, + input LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD, + input ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE, + input PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0, + input PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0, + output CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK, + output PLLDATO7, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK, + output DPHSRC, CLKINTFB +); + parameter CLKI_DIV = 1; + parameter CLKFB_DIV = 1; + parameter CLKOP_DIV = 8; + parameter CLKOS_DIV = 8; + parameter CLKOS2_DIV = 8; + parameter CLKOS3_DIV = 8; + parameter CLKOP_ENABLE = "ENABLED"; + parameter CLKOS_ENABLE = "ENABLED"; + parameter CLKOS2_ENABLE = "ENABLED"; + parameter CLKOS3_ENABLE = "ENABLED"; + parameter VCO_BYPASS_A0 = "DISABLED"; + parameter VCO_BYPASS_B0 = "DISABLED"; + parameter VCO_BYPASS_C0 = "DISABLED"; + parameter VCO_BYPASS_D0 = "DISABLED"; + parameter CLKOP_CPHASE = 0; + parameter CLKOS_CPHASE = 0; + parameter CLKOS2_CPHASE = 0; + parameter CLKOS3_CPHASE = 0; + parameter CLKOP_FPHASE = 0; + parameter CLKOS_FPHASE = 0; + parameter CLKOS2_FPHASE = 0; + parameter CLKOS3_FPHASE = 0; + parameter FEEDBK_PATH = "CLKOP"; + parameter FRACN_ENABLE = "DISABLED"; + parameter FRACN_DIV = 0; + parameter CLKOP_TRIM_POL = "RISING"; + parameter CLKOP_TRIM_DELAY = 0; + parameter CLKOS_TRIM_POL = "RISING"; + parameter CLKOS_TRIM_DELAY = 0; + parameter PLL_USE_WB = "DISABLED"; + parameter PREDIVIDER_MUXA1 = 0; + parameter PREDIVIDER_MUXB1 = 0; + parameter PREDIVIDER_MUXC1 = 0; + parameter PREDIVIDER_MUXD1 = 0; + parameter OUTDIVIDER_MUXA2 = "DIVA"; + parameter OUTDIVIDER_MUXB2 = "DIVB"; + parameter OUTDIVIDER_MUXC2 = "DIVC"; + parameter OUTDIVIDER_MUXD2 = "DIVD"; + parameter PLL_LOCK_MODE = 0; + parameter STDBY_ENABLE = "DISABLED"; + parameter DPHASE_SOURCE = "DISABLED"; + parameter PLLRST_ENA = "DISABLED"; + parameter MRST_ENA = "DISABLED"; + parameter DCRST_ENA = "DISABLED"; + parameter DDRST_ENA = "DISABLED"; + parameter INTFB_WAKE = "DISABLED"; +endmodule + +(* blackbox *) +module OSCH #( + parameter NOM_FREQ = "2.08" +) ( + input STDBY, + output OSC, + output SEDSTDBY +); +endmodule + +(* blackbox *) +module DCCA ( + input CLKI, + input CE, + output CLKO +); +endmodule + +(* blackbox *) +module DCMA ( + input CLK0, + input CLK1, + input SEL, + output DCMOUT +); +endmodule + +(* blackbox *) +module PDPW8KC ( + input DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, + input ADW8, ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, + input BE1, BE0, + input CEW, CLKW, CSW2, CSW1, CSW0, + input ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5, ADR4, ADR3, ADR2, ADR1, ADR0, + input CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, + output DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 +); + parameter DATA_WIDTH_W = 18; + parameter DATA_WIDTH_R = 9; + + parameter GSR = "ENABLED"; + + parameter REGMODE = "NOREG"; + + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + + parameter CSDECODE_W = "0b000"; + parameter CSDECODE_R = "0b000"; + + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_DATA = "STATIC"; + +endmodule + +(* blackbox *) +module SP8KC ( + input DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, + input AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0, + input CE, OCE, CLK, WE, CS2, CS1, CS0, RST, + output DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 +); + parameter DATA_WIDTH = 9; + parameter GSR = "ENABLED"; + + parameter REGMODE = "NOREG"; + + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + + parameter CSDECODE = "0b000"; + + parameter WRITEMODE = "NORMAL"; + + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_DATA = "STATIC"; +endmodule + +(* blackbox *) +module FIFO8KB ( + input DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, + input CSW0, CSW1, CSR0, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI, + output DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17, + input EF, AEF, AFF, FF +); + parameter DATA_WIDTH_W = 18; + parameter DATA_WIDTH_R = 18; + + parameter GSR = "DISABLED"; + + parameter REGMODE = "NOREG"; + + parameter RESETMODE = "ASYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + + parameter CSDECODE_W = "0b00"; + parameter CSDECODE_R = "0b00"; + + parameter AEPOINTER = "0b00000000000000"; + parameter AEPOINTER1 = "0b00000000000000"; + parameter AFPOINTER = "0b00000000000000"; + parameter AFPOINTER1 = "0b00000000000000"; + parameter FULLPOINTER = "0b00000000000000"; + parameter FULLPOINTER1 = "0b00000000000000"; +endmodule diff --git a/techlibs/lattice/cells_ff.vh b/techlibs/lattice/cells_ff.vh new file mode 100644 index 00000000000..6b745f391ee --- /dev/null +++ b/techlibs/lattice/cells_ff.vh @@ -0,0 +1,40 @@ +// Diamond flip-flops +module FD1P3AX(input D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .CE(SP), .DI(D), .Q(Q)); endmodule +module FD1P3AY(input D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .CE(SP), .DI(D), .Q(Q)); endmodule +module FD1P3BX(input PD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module FD1P3DX(input CD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module FD1P3IX(input CD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module FD1P3JX(input PD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module FD1S3AX(input D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .DI(D), .Q(Q)); endmodule +module FD1S3AY(input D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .DI(D), .Q(Q)); endmodule +module FD1S3BX(input PD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule +module FD1S3DX(input CD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule +module FD1S3IX(input CD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule +module FD1S3JX(input PD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule + +// TODO: Diamond latches +// module FL1P3AY(); endmodule +// module FL1P3AZ(); endmodule +// module FL1P3BX(); endmodule +// module FL1P3DX(); endmodule +// module FL1P3IY(); endmodule +// module FL1P3JY(); endmodule +// module FL1S3AX(); endmodule +// module FL1S3AY(); endmodule + +// Diamond I/O registers +module IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule + +module OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule + +// TODO: Diamond I/O latches +// module IFS1S1B(input PD, D, SCLK, output Q); endmodule +// module IFS1S1D(input CD, D, SCLK, output Q); endmodule +// module IFS1S1I(input PD, D, SCLK, output Q); endmodule +// module IFS1S1J(input CD, D, SCLK, output Q); endmodule diff --git a/techlibs/lattice/cells_io.vh b/techlibs/lattice/cells_io.vh new file mode 100644 index 00000000000..220460c4467 --- /dev/null +++ b/techlibs/lattice/cells_io.vh @@ -0,0 +1,14 @@ +// Diamond I/O buffers +module IB ((* iopad_external_pin *) input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule +module IBPU ((* iopad_external_pin *) input I, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule +module IBPD ((* iopad_external_pin *) input I, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule +module OB (input I, (* iopad_external_pin *) output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule +module OBZ (input I, T, (* iopad_external_pin *) output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule +module OBZPU(input I, T, (* iopad_external_pin *) output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule +module OBZPD(input I, T, (* iopad_external_pin *) output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule +module OBCO (input I, output OT, OC); OLVDS olvds (.A(I), .Z(OT), .ZN(OC)); endmodule +module BB (input I, T, output O, (* iopad_external_pin *) inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule +module BBPU (input I, T, output O, (* iopad_external_pin *) inout B); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule +module BBPD (input I, T, output O, (* iopad_external_pin *) inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule +module ILVDS(input A, AN, (* iopad_external_pin *) output Z ); TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule +module OLVDS(input A, (* iopad_external_pin *) output Z, output ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule diff --git a/techlibs/lattice/cells_map.v b/techlibs/lattice/cells_map.v new file mode 100644 index 00000000000..4944ece4569 --- /dev/null +++ b/techlibs/lattice/cells_map.v @@ -0,0 +1,191 @@ +module \$_DFF_N_ (input D, C, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); + else + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; +endmodule + +module \$_DFF_P_ (input D, C, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); + else + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; +endmodule + +module \$_DFFE_NN_ (input D, C, E, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); + else + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; +endmodule + +module \$_DFFE_PN_ (input D, C, E, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); + else + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; +endmodule + +module \$_DFFE_NP_ (input D, C, E, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); + else + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; +endmodule + +module \$_DFFE_PP_ (input D, C, E, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); + else + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; +endmodule + +module \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule + +module \$_SDFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_SDFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_SDFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_SDFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule + +module \$_DFFE_NP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_DFFE_NP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_DFFE_PP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_DFFE_PP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule + +module \$_DFFE_NP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_DFFE_NP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_DFFE_PP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_DFFE_PP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule + +module \$_SDFFE_NP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_SDFFE_NP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_SDFFE_PP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_SDFFE_PP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule + +module \$_SDFFE_NP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_SDFFE_NP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_SDFFE_PP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_SDFFE_PP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule + +module \$_ALDFF_NP_ (input C, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule +module \$_ALDFF_PP_ (input C, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule + +module \$_ALDFFE_NPN_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule +module \$_ALDFFE_NPP_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule +module \$_ALDFFE_PPN_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule +module \$_ALDFFE_PPP_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule + +`include "cells_ff.vh" +`include "cells_io.vh" + +`ifndef NO_LUT +module \$lut (A, Y); + parameter WIDTH = 0; + parameter LUT = 0; + + (* force_downto *) + input [WIDTH-1:0] A; + output Y; + + generate + if (WIDTH == 1) begin + localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}}; + LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y), + .A(1'b0), .B(1'b0), .C(1'b0), .D(A[0])); + end else + if (WIDTH == 2) begin + localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}}; + LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y), + .A(1'b0), .B(1'b0), .C(A[0]), .D(A[1])); + end else + if (WIDTH == 3) begin + localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}}; + LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y), + .A(1'b0), .B(A[0]), .C(A[1]), .D(A[2])); + end else + if (WIDTH == 4) begin + LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + `ifndef NO_PFUMUX + end else + if (WIDTH == 5) begin + wire f0, f1; + LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + PFUMX mux5(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(Y)); + end else + if (WIDTH == 6) begin + wire f0, f1, f2, f3, g0, g1; + LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0)); + PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1)); + L6MUX21 mux6 (.D0(g0), .D1(g1), .SD(A[5]), .Z(Y)); + end else + if (WIDTH == 7) begin + wire f0, f1, f2, f3, f4, f5, f6, f7, g0, g1, g2, g3, h0, h1; + LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + LUT4 #(.INIT(LUT[79:64])) lut4 (.Z(f4), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[95:80])) lut5 (.Z(f5), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + LUT4 #(.INIT(LUT[111: 96])) lut6 (.Z(f6), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[127:112])) lut7 (.Z(f7), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0)); + PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1)); + PFUMX mux52(.ALUT(f5), .BLUT(f4), .C0(A[4]), .Z(g2)); + PFUMX mux53(.ALUT(f7), .BLUT(f6), .C0(A[4]), .Z(g3)); + L6MUX21 mux60 (.D0(g0), .D1(g1), .SD(A[5]), .Z(h0)); + L6MUX21 mux61 (.D0(g2), .D1(g3), .SD(A[5]), .Z(h1)); + L6MUX21 mux7 (.D0(h0), .D1(h1), .SD(A[6]), .Z(Y)); + `endif + end else begin + wire _TECHMAP_FAIL_ = 1; + end + endgenerate +endmodule +`endif diff --git a/techlibs/lattice/cells_sim_ecp5.v b/techlibs/lattice/cells_sim_ecp5.v new file mode 100644 index 00000000000..9439e3a5b31 --- /dev/null +++ b/techlibs/lattice/cells_sim_ecp5.v @@ -0,0 +1,9 @@ +`include "common_sim.vh" +`include "ccu2c_sim.vh" + +`ifndef NO_INCLUDES + +`include "cells_ff.vh" +`include "cells_io.vh" + +`endif diff --git a/techlibs/lattice/cells_sim_xo2.v b/techlibs/lattice/cells_sim_xo2.v new file mode 100644 index 00000000000..54414287572 --- /dev/null +++ b/techlibs/lattice/cells_sim_xo2.v @@ -0,0 +1,9 @@ +`include "common_sim.vh" +`include "ccu2d_sim.vh" + +`ifndef NO_INCLUDES + +`include "cells_ff.vh" +`include "cells_io.vh" + +`endif diff --git a/techlibs/lattice/cells_sim_xo3.v b/techlibs/lattice/cells_sim_xo3.v new file mode 100644 index 00000000000..54414287572 --- /dev/null +++ b/techlibs/lattice/cells_sim_xo3.v @@ -0,0 +1,9 @@ +`include "common_sim.vh" +`include "ccu2d_sim.vh" + +`ifndef NO_INCLUDES + +`include "cells_ff.vh" +`include "cells_io.vh" + +`endif diff --git a/techlibs/lattice/cells_sim_xo3d.v b/techlibs/lattice/cells_sim_xo3d.v new file mode 100644 index 00000000000..54414287572 --- /dev/null +++ b/techlibs/lattice/cells_sim_xo3d.v @@ -0,0 +1,9 @@ +`include "common_sim.vh" +`include "ccu2d_sim.vh" + +`ifndef NO_INCLUDES + +`include "cells_ff.vh" +`include "cells_io.vh" + +`endif diff --git a/techlibs/lattice/common_sim.vh b/techlibs/lattice/common_sim.vh new file mode 100644 index 00000000000..e6c2e57b507 --- /dev/null +++ b/techlibs/lattice/common_sim.vh @@ -0,0 +1,402 @@ +// --------------------------------------- + +(* abc9_lut=1, lib_whitebox *) +module LUT4(input A, B, C, D, output Z); + parameter [15:0] INIT = 16'h0000; + wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0]; + wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0]; + wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0]; + assign Z = A ? s1[1] : s1[0]; + specify + (A => Z) = 141; + (B => Z) = 275; + (C => Z) = 379; + (D => Z) = 379; + endspecify +endmodule + +// This is a placeholder for ABC9 to extract the area/delay +// cost of 5-input LUTs and is not intended to be instantiated +// LUT5 = 2x LUT4 + PFUMX +(* abc9_lut=2 *) +module \$__ABC9_LUT5 (input M0, D, C, B, A, output Z); + specify + (M0 => Z) = 151; + (D => Z) = 239; + (C => Z) = 373; + (B => Z) = 477; + (A => Z) = 477; + endspecify +endmodule + +// This is a placeholder for ABC9 to extract the area/delay +// of 6-input LUTs and is not intended to be instantiated +// LUT6 = 2x LUT5 + MUX2 +(* abc9_lut=4 *) +module \$__ABC9_LUT6 (input M1, M0, D, C, B, A, output Z); + specify + (M1 => Z) = 148; + (M0 => Z) = 292; + (D => Z) = 380; + (C => Z) = 514; + (B => Z) = 618; + (A => Z) = 618; + endspecify +endmodule + +// This is a placeholder for ABC9 to extract the area/delay +// of 7-input LUTs and is not intended to be instantiated +// LUT7 = 2x LUT6 + MUX2 +(* abc9_lut=8 *) +module \$__ABC9_LUT7 (input M2, M1, M0, D, C, B, A, output Z); + specify + (M2 => Z) = 148; + (M1 => Z) = 289; + (M0 => Z) = 433; + (D => Z) = 521; + (C => Z) = 655; + (B => Z) = 759; + (A => Z) = 759; + endspecify +endmodule + +// --------------------------------------- +(* abc9_box, lib_whitebox *) +module L6MUX21 (input D0, D1, SD, output Z); + assign Z = SD ? D1 : D0; + specify + (D0 => Z) = 140; + (D1 => Z) = 141; + (SD => Z) = 148; + endspecify +endmodule + +// --------------------------------------- + +module TRELLIS_RAM16X2 ( + input DI0, DI1, + input WAD0, WAD1, WAD2, WAD3, + input WRE, WCK, + input RAD0, RAD1, RAD2, RAD3, + output DO0, DO1 +); + parameter WCKMUX = "WCK"; + parameter WREMUX = "WRE"; + parameter INITVAL_0 = 16'h0000; + parameter INITVAL_1 = 16'h0000; + + reg [1:0] mem[15:0]; + + integer i; + initial begin + for (i = 0; i < 16; i = i + 1) + mem[i] <= {INITVAL_1[i], INITVAL_0[i]}; + end + + wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK; + + reg muxwre; + always @(*) + case (WREMUX) + "1": muxwre = 1'b1; + "0": muxwre = 1'b0; + "INV": muxwre = ~WRE; + default: muxwre = WRE; + endcase + + + always @(posedge muxwck) + if (muxwre) + mem[{WAD3, WAD2, WAD1, WAD0}] <= {DI1, DI0}; + + assign {DO1, DO0} = mem[{RAD3, RAD2, RAD1, RAD0}]; +endmodule + +// --------------------------------------- +(* abc9_box, lib_whitebox *) +module PFUMX (input ALUT, BLUT, C0, output Z); + assign Z = C0 ? ALUT : BLUT; + specify + (ALUT => Z) = 98; + (BLUT => Z) = 98; + (C0 => Z) = 151; + endspecify +endmodule + +// --------------------------------------- +(* abc9_box, lib_whitebox *) +module TRELLIS_DPR16X4 ( + input [3:0] DI, + input [3:0] WAD, + input WRE, + input WCK, + input [3:0] RAD, + output [3:0] DO +); + parameter WCKMUX = "WCK"; + parameter WREMUX = "WRE"; + parameter [63:0] INITVAL = 64'h0000000000000000; + + reg [3:0] mem[15:0]; + + integer i; + initial begin + for (i = 0; i < 16; i = i + 1) + mem[i] <= INITVAL[4*i +: 4]; + end + + wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK; + + reg muxwre; + always @(*) + case (WREMUX) + "1": muxwre = 1'b1; + "0": muxwre = 1'b0; + "INV": muxwre = ~WRE; + default: muxwre = WRE; + endcase + + always @(posedge muxwck) + if (muxwre) + mem[WAD] <= DI; + + assign DO = mem[RAD]; + + specify + // TODO + (RAD *> DO) = 0; + endspecify +endmodule + +// --------------------------------------- + +(* abc9_box, lib_whitebox *) +module DPR16X4C ( + input [3:0] DI, + input WCK, WRE, + input [3:0] RAD, + input [3:0] WAD, + output [3:0] DO +); + // For legacy Lattice compatibility, INITIVAL is a hex + // string rather than a numeric parameter + parameter INITVAL = "0x0000000000000000"; + + function [63:0] convert_initval; + input [143:0] hex_initval; + reg done; + reg [63:0] temp; + reg [7:0] char; + integer i; + begin + done = 1'b0; + temp = 0; + for (i = 0; i < 16; i = i + 1) begin + if (!done) begin + char = hex_initval[8*i +: 8]; + if (char == "x") begin + done = 1'b1; + end else begin + if (char >= "0" && char <= "9") + temp[4*i +: 4] = char - "0"; + else if (char >= "A" && char <= "F") + temp[4*i +: 4] = 10 + char - "A"; + else if (char >= "a" && char <= "f") + temp[4*i +: 4] = 10 + char - "a"; + end + end + end + convert_initval = temp; + end + endfunction + + localparam conv_initval = convert_initval(INITVAL); + + reg [3:0] ram[0:15]; + integer i; + initial begin + for (i = 0; i < 15; i = i + 1) begin + ram[i] <= conv_initval[4*i +: 4]; + end + end + + always @(posedge WCK) + if (WRE) + ram[WAD] <= DI; + + assign DO = ram[RAD]; + + specify + // TODO + (RAD *> DO) = 0; + endspecify +endmodule + +// --------------------------------------- + +(* lib_whitebox *) +module LUT2(input A, B, output Z); + parameter [3:0] INIT = 4'h0; + wire [1:0] s1 = B ? INIT[ 3:2] : INIT[1:0]; + assign Z = A ? s1[1] : s1[0]; +endmodule + +// --------------------------------------- + +`ifdef YOSYS +(* abc9_flop=(SRMODE != "ASYNC"), abc9_box=(SRMODE == "ASYNC"), lib_whitebox *) +`endif +module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q); + parameter GSR = "ENABLED"; + parameter [127:0] CEMUX = "1"; + parameter CLKMUX = "CLK"; + parameter LSRMUX = "LSR"; + parameter SRMODE = "LSR_OVER_CE"; + parameter REGSET = "RESET"; + parameter [127:0] LSRMODE = "LSR"; + + wire muxce; + generate + case (CEMUX) + "1": assign muxce = 1'b1; + "0": assign muxce = 1'b0; + "INV": assign muxce = ~CE; + default: assign muxce = CE; + endcase + endgenerate + + wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR; + wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK; + wire srval; + generate + if (LSRMODE == "PRLD") + assign srval = M; + else + assign srval = (REGSET == "SET") ? 1'b1 : 1'b0; + endgenerate + + initial Q = srval; + + generate + if (SRMODE == "ASYNC") begin + always @(posedge muxclk, posedge muxlsr) + if (muxlsr) + Q <= srval; + else if (muxce) + Q <= DI; + end else begin + always @(posedge muxclk) + if (muxlsr) + Q <= srval; + else if (muxce) + Q <= DI; + end + endgenerate + + specify + $setup(DI, negedge CLK &&& CLKMUX == "INV", 0); + $setup(CE, negedge CLK &&& CLKMUX == "INV", 0); + $setup(LSR, negedge CLK &&& CLKMUX == "INV", 0); + $setup(DI, posedge CLK &&& CLKMUX != "INV", 0); + $setup(CE, posedge CLK &&& CLKMUX != "INV", 0); + $setup(LSR, posedge CLK &&& CLKMUX != "INV", 0); +`ifndef YOSYS + if (SRMODE == "ASYNC" && muxlsr && CLKMUX == "INV") (negedge CLK => (Q : srval)) = 0; + if (SRMODE == "ASYNC" && muxlsr && CLKMUX != "INV") (posedge CLK => (Q : srval)) = 0; +`else + if (SRMODE == "ASYNC" && muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif + if (!muxlsr && muxce && CLKMUX == "INV") (negedge CLK => (Q : DI)) = 0; + if (!muxlsr && muxce && CLKMUX != "INV") (posedge CLK => (Q : DI)) = 0; + endspecify +endmodule + +// --------------------------------------- +(* keep *) +module TRELLIS_IO( + (* iopad_external_pin *) + inout B, + input I, + input T, + output O +); + parameter DIR = "INPUT"; + reg T_pd; + always @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T; + + generate + if (DIR == "INPUT") begin + assign B = 1'bz; + assign O = B; + end else if (DIR == "OUTPUT") begin + assign B = T_pd ? 1'bz : I; + assign O = 1'bx; + end else if (DIR == "BIDIR") begin + assign B = T_pd ? 1'bz : I; + assign O = B; + end else begin + ERROR_UNKNOWN_IO_MODE error(); + end + endgenerate + +endmodule + +// --------------------------------------- + +module INV(input A, output Z); + assign Z = !A; +endmodule + +// --------------------------------------- + +module TRELLIS_COMB( + input A, B, C, D, M, + input FCI, F1, FXA, FXB, + input WD, + input WAD0, WAD1, WAD2, WAD3, + input WRE, WCK, + output F, FCO, OFX +); + parameter MODE = "LOGIC"; + parameter INITVAL = 16'h0; + parameter CCU2_INJECT1 = "NO"; + parameter WREMUX = "WRE"; + parameter IS_Z1 = 1'b0; + + generate + if (MODE == "LOGIC") begin: mode_logic + LUT4 #(.INIT(INITVAL)) lut4 (.A(A), .B(B), .C(C), .D(D), .Z(F)); + end else if (MODE == "CCU2") begin: mode_ccu2 + wire l4o, l2o; + LUT4 #(.INIT(INITVAL)) lut4_0(.A(A), .B(B), .C(C), .D(D), .Z(l4o)); + LUT2 #(.INIT(INITVAL[3:0])) lut2_0(.A(A), .B(B), .Z(l2o)); + wire gated_cin_0 = (CCU2_INJECT1 == "YES") ? 1'b0 : FCI; + assign F = l4o ^ gated_cin_0; + wire gated_lut2_0 = (CCU2_INJECT1 == "YES") ? 1'b0 : l2o; + wire FCO = (~l4o & gated_lut2_0) | (l4o & FCI); + end else if (MODE == "DPRAM") begin: mode_dpram + reg [15:0] ram = INITVAL; + always @(posedge WCK) + if (WRE) + ram[{WAD3, WAD2, WAD1, WAD0}] <= WD; + assign F = ram[{A, C, B, D}]; + end else begin + $error("unsupported COMB mode %s", MODE); + end + + if (IS_Z1) + L6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M), .Z(OFX)); + else + PFUMX lut5_mux (.ALUT(F1), .BLUT(F), .C0(M), .Z(OFX)); + endgenerate + +endmodule + +`ifndef NO_INCLUDES + +`include "cells_ff.vh" +`include "cells_io.vh" + +`endif diff --git a/techlibs/lattice/dsp_map_18x18.v b/techlibs/lattice/dsp_map_18x18.v new file mode 100644 index 00000000000..df54d1d9f9f --- /dev/null +++ b/techlibs/lattice/dsp_map_18x18.v @@ -0,0 +1,17 @@ +module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); + + parameter A_WIDTH = 18; + parameter B_WIDTH = 18; + parameter Y_WIDTH = 36; + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + + MULT18X18D _TECHMAP_REPLACE_ ( + .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]), + .B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]), + .C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0), + .SIGNEDA(A_SIGNED ? 1'b1 : 1'b0), .SIGNEDB(B_SIGNED ? 1'b1 : 1'b0), .SOURCEA(1'b0), .SOURCEB(1'b0), + + .P0(Y[0]), .P1(Y[1]), .P2(Y[2]), .P3(Y[3]), .P4(Y[4]), .P5(Y[5]), .P6(Y[6]), .P7(Y[7]), .P8(Y[8]), .P9(Y[9]), .P10(Y[10]), .P11(Y[11]), .P12(Y[12]), .P13(Y[13]), .P14(Y[14]), .P15(Y[15]), .P16(Y[16]), .P17(Y[17]), .P18(Y[18]), .P19(Y[19]), .P20(Y[20]), .P21(Y[21]), .P22(Y[22]), .P23(Y[23]), .P24(Y[24]), .P25(Y[25]), .P26(Y[26]), .P27(Y[27]), .P28(Y[28]), .P29(Y[29]), .P30(Y[30]), .P31(Y[31]), .P32(Y[32]), .P33(Y[33]), .P34(Y[34]), .P35(Y[35]) + ); +endmodule diff --git a/techlibs/lattice/latches_map.v b/techlibs/lattice/latches_map.v new file mode 100644 index 00000000000..c28f88cf767 --- /dev/null +++ b/techlibs/lattice/latches_map.v @@ -0,0 +1,11 @@ +module \$_DLATCH_N_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = !E ? D : Q; +endmodule + +module \$_DLATCH_P_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = E ? D : Q; +endmodule diff --git a/techlibs/lattice/lutrams.txt b/techlibs/lattice/lutrams.txt new file mode 100644 index 00000000000..ea42d4fcb5e --- /dev/null +++ b/techlibs/lattice/lutrams.txt @@ -0,0 +1,12 @@ +ram distributed $__TRELLIS_DPR16X4_ { + abits 4; + width 4; + cost 4; + init any; + prune_rom; + port sw "W" { + clock anyedge; + } + port ar "R" { + } +} diff --git a/techlibs/lattice/lutrams_map.v b/techlibs/lattice/lutrams_map.v new file mode 100644 index 00000000000..3cb325f041e --- /dev/null +++ b/techlibs/lattice/lutrams_map.v @@ -0,0 +1,30 @@ +module $__TRELLIS_DPR16X4_(...); + +parameter INIT = 64'bx; +parameter PORT_W_CLK_POL = 1; + +input PORT_W_CLK; +input [3:0] PORT_W_ADDR; +input [3:0] PORT_W_WR_DATA; +input PORT_W_WR_EN; + +input [3:0] PORT_R_ADDR; +output [3:0] PORT_R_RD_DATA; + +localparam WCKMUX = PORT_W_CLK_POL ? "WCK" : "INV"; + +TRELLIS_DPR16X4 #( + .INITVAL(INIT), + .WCKMUX(WCKMUX), + .WREMUX("WRE") +) _TECHMAP_REPLACE_ ( + .RAD(PORT_R_ADDR), + .DO(PORT_R_RD_DATA), + + .WAD(PORT_W_ADDR), + .DI(PORT_W_WR_DATA), + .WCK(PORT_W_CLK), + .WRE(PORT_W_WR_EN) +); + +endmodule diff --git a/techlibs/lattice/synth_lattice.cc b/techlibs/lattice/synth_lattice.cc new file mode 100644 index 00000000000..edca6855e08 --- /dev/null +++ b/techlibs/lattice/synth_lattice.cc @@ -0,0 +1,574 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * Copyright (C) 2018 gatecat + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/celltypes.h" +#include "kernel/rtlil.h" +#include "kernel/log.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct SynthLatticePass : public ScriptPass +{ + SynthLatticePass() : ScriptPass("synth_lattice", "synthesis for Lattice FPGAs") { } + + void on_register() override + { + RTLIL::constpad["synth_lattice.abc9.W"] = "300"; + } + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" synth_lattice [options]\n"); + log("\n"); + log("This command runs synthesis for Lattice FPGAs.\n"); + log("\n"); + log(" -top \n"); + log(" use the specified module as top module\n"); + log("\n"); + log(" -family \n"); + log(" run synthesis for the specified Lattice architecture\n"); + log(" generate the synthesis netlist for the specified family.\n"); + log(" supported values:\n"); + log(" - ecp5: ECP5\n"); + log(" - xo2: MachXO2\n"); + log(" - xo3: MachXO3L/LF\n"); + log(" - xo3d: MachXO3D\n"); + //log(" - xo: MachXO (EXPERIMENTAL)\n"); + //log(" - pm: Platform Manager (EXPERIMENTAL)\n"); + //log(" - pm2: Platform Manager 2 (EXPERIMENTAL)\n"); + //log(" - xp: LatticeXP (EXPERIMENTAL)\n"); + //log(" - xp2: LatticeXP2 (EXPERIMENTAL)\n"); + //log(" - ecp: LatticeECP/EC (EXPERIMENTAL)\n"); + //log(" - sm: LatticeSC/M (EXPERIMENTAL)\n"); + //log(" - ecp2: LatticeECP2/M (EXPERIMENTAL)\n"); + //log(" - ecp3: LatticeECP3 (EXPERIMENTAL)\n"); + //log(" - lifmd: LIFMD (EXPERIMENTAL)\n"); + //log(" - lifmdf: LIFMDF (EXPERIMENTAL)\n"); + log("\n"); + log(" -blif \n"); + log(" write the design to the specified BLIF file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -edif \n"); + log(" write the design to the specified EDIF file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -json \n"); + log(" write the design to the specified JSON file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -run :\n"); + log(" only run the commands between the labels (see below). an empty\n"); + log(" from label is synonymous to 'begin', and empty to label is\n"); + log(" synonymous to the end of the command list.\n"); + log("\n"); + log(" -noflatten\n"); + log(" do not flatten design before synthesis\n"); + log("\n"); + log(" -dff\n"); + log(" run 'abc'/'abc9' with -dff option\n"); + log("\n"); + log(" -retime\n"); + log(" run 'abc' with '-dff -D 1' options\n"); + log("\n"); + log(" -noccu2\n"); + log(" do not use CCU2 cells in output netlist\n"); + log("\n"); + log(" -nodffe\n"); + log(" do not use flipflops with CE in output netlist\n"); + log("\n"); + log(" -nobram\n"); + log(" do not use block RAM cells in output netlist\n"); + log("\n"); + log(" -nolutram\n"); + log(" do not use LUT RAM cells in output netlist\n"); + log("\n"); + log(" -nowidelut\n"); + log(" do not use PFU muxes to implement LUTs larger than LUT4s\n"); + log("\n"); + log(" -asyncprld\n"); + log(" use async PRLD mode to implement ALDFF (EXPERIMENTAL)\n"); + log("\n"); + log(" -abc2\n"); + log(" run two passes of 'abc' for slightly improved logic density\n"); + log("\n"); + log(" -abc9\n"); + log(" use new ABC9 flow (EXPERIMENTAL)\n"); + log("\n"); + log(" -vpr\n"); + log(" generate an output netlist (and BLIF file) suitable for VPR\n"); + log(" (this feature is experimental and incomplete)\n"); + log("\n"); + log(" -iopad\n"); + log(" insert IO buffers\n"); + log("\n"); + log(" -nodsp\n"); + log(" do not map multipliers to MULT18X18D\n"); + log("\n"); + log(" -no-rw-check\n"); + log(" marks all recognized read ports as \"return don't-care value on\n"); + log(" read/write collision\" (same result as setting the no_rw_check\n"); + log(" attribute on all memories).\n"); + log("\n"); + log("\n"); + log("The following commands are executed by this synthesis command:\n"); + help_script(); + log("\n"); + } + + string top_opt, blif_file, edif_file, json_file, family; + bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, iopad, nodsp, vpr, no_rw_check, have_dsp; + string postfix, arith_map, brams_map, dsp_map; + + void clear_flags() override + { + top_opt = "-auto-top"; + blif_file = ""; + edif_file = ""; + json_file = ""; + family = ""; + noccu2 = false; + nodffe = false; + nobram = false; + nolutram = false; + nowidelut = false; + asyncprld = false; + flatten = true; + dff = false; + retime = false; + abc2 = false; + vpr = false; + abc9 = false; + iopad = false; + nodsp = false; + no_rw_check = false; + postfix = ""; + arith_map = ""; + brams_map = ""; + dsp_map = ""; + have_dsp = false; + } + + void execute(std::vector args, RTLIL::Design *design) override + { + string run_from, run_to; + clear_flags(); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-top" && argidx+1 < args.size()) { + top_opt = "-top " + args[++argidx]; + continue; + } + if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) { + family = args[++argidx]; + continue; + } + if (args[argidx] == "-blif" && argidx+1 < args.size()) { + blif_file = args[++argidx]; + continue; + } + if (args[argidx] == "-edif" && argidx+1 < args.size()) { + edif_file = args[++argidx]; + continue; + } + if (args[argidx] == "-json" && argidx+1 < args.size()) { + json_file = args[++argidx]; + continue; + } + if (args[argidx] == "-run" && argidx+1 < args.size()) { + size_t pos = args[argidx+1].find(':'); + if (pos == std::string::npos) + break; + run_from = args[++argidx].substr(0, pos); + run_to = args[argidx].substr(pos+1); + continue; + } + if (args[argidx] == "-flatten") { + flatten = true; + continue; + } + if (args[argidx] == "-noflatten") { + flatten = false; + continue; + } + if (args[argidx] == "-dff") { + dff = true; + continue; + } + if (args[argidx] == "-retime") { + retime = true; + continue; + } + if (args[argidx] == "-noccu2") { + noccu2 = true; + continue; + } + if (args[argidx] == "-nodffe") { + nodffe = true; + continue; + } + if (args[argidx] == "-nobram") { + nobram = true; + continue; + } + if (args[argidx] == "-asyncprld") { + asyncprld = true; + continue; + } + if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") { + nolutram = true; + continue; + } + if (args[argidx] == "-nowidelut" || /*deprecated alias*/ args[argidx] == "-nomux") { + nowidelut = true; + continue; + } + if (args[argidx] == "-abc2") { + abc2 = true; + continue; + } + if (args[argidx] == "-vpr") { + vpr = true; + continue; + } + if (args[argidx] == "-abc9") { + abc9 = true; + continue; + } + if (args[argidx] == "-iopad") { + iopad = true; + continue; + } + if (args[argidx] == "-nodsp") { + nodsp = true; + continue; + } + if (args[argidx] == "-no-rw-check") { + no_rw_check = true; + continue; + } + break; + } + extra_args(args, argidx, design); + + if (family.empty()) + log_cmd_error("Lattice family parameter must be set.\n"); + + if (family == "ecp5") { + postfix = "_ecp5"; + arith_map = "_ccu2c"; + brams_map = "_16kd"; + dsp_map = "_18x18"; + have_dsp = true; + } else if (family == "xo2" || + family == "xo3" || + family == "xo3d" /* || + family == "pm2"*/) { + postfix = "_" + family; + arith_map = "_ccu2d"; + brams_map = "_8kc"; + have_dsp = false; +/* } else if (family == "xo" || + family == "pm") { + } else if (family == "xp" || + family == "xp2" || + family == "ecp" || + family == "sm" || + family == "ecp2" || + family == "ecp3" || + family == "lifmd" || + family == "lifmdf") {*/ + } else + log_cmd_error("Invalid Lattice -family setting: '%s'.\n", family.c_str()); + + if (!design->full_selection()) + log_cmd_error("This command only operates on fully selected designs!\n"); + + if (abc9 && retime) + log_cmd_error("-retime option not currently compatible with -abc9!\n"); + + log_header(design, "Executing SYNTH_LATTICE pass.\n"); + log_push(); + + run_script(design, run_from, run_to); + + log_pop(); + } + + void script() override + { + std::string no_rw_check_opt = ""; + if (no_rw_check) + no_rw_check_opt = " -no-rw-check"; + if (help_mode) + no_rw_check_opt = " [-no-rw-check]"; + + if (check_label("begin")) + { + run("read_verilog -lib -specify +/lattice/cells_sim" + postfix + ".v +/lattice/cells_bb" + postfix + ".v"); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + } + + if (check_label("coarse")) + { + run("proc"); + if (flatten || help_mode) + run("flatten"); + run("tribuf -logic"); + run("deminout"); + run("opt_expr"); + run("opt_clean"); + run("check"); + run("opt -nodffe -nosdff"); + run("fsm"); + run("opt"); + run("wreduce"); + run("peepopt"); + run("opt_clean"); + run("share"); + run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4"); + run("opt_expr"); + run("opt_clean"); + if (have_dsp && !nodsp) { + run("techmap -map +/mul2dsp.v -map +/lattice/dsp_map" + dsp_map + ".v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=$__MUL18X18", "(unless -nodsp)"); + run("chtype -set $mul t:$__soft_mul", "(unless -nodsp)"); + } + run("alumacc"); + run("opt"); + run("memory -nomap" + no_rw_check_opt); + run("opt_clean"); + } + + if (check_label("map_ram")) + { + std::string args = ""; + if (nobram) + args += " -no-auto-block"; + if (nolutram) + args += " -no-auto-distributed"; + if (help_mode) + args += " [-no-auto-block] [-no-auto-distributed]"; + run("memory_libmap -lib +/lattice/lutrams.txt -lib +/lattice/brams" + brams_map + ".txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)"); + run("techmap -map +/lattice/lutrams_map.v -map +/lattice/brams_map" + brams_map + ".v"); + } + + if (check_label("map_ffram")) + { + run("opt -fast -mux_undef -undriven -fine"); + run("memory_map"); + run("opt -undriven -fine"); + } + + if (check_label("map_gates")) + { + if (noccu2) + run("techmap"); + else + run("techmap -map +/techmap.v -map +/lattice/arith_map" + arith_map + ".v"); + if (help_mode || iopad) { + run("iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad OBZ ~T:I:O -tinoutpad BB ~T:O:I:B A:top", "(only if '-iopad')"); + run("attrmvcp -attr src -attr LOC t:OB %x:+[O] t:OBZ %x:+[O] t:BB %x:+[B]"); + run("attrmvcp -attr src -attr LOC -driven t:IB %x:+[I]"); + } + run("opt -fast"); + if (retime || help_mode) + run("abc -dff -D 1", "(only if -retime)"); + } + + if (check_label("map_ffs")) + { + run("opt_clean"); + std::string dfflegalize_args = " -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r"; + if (help_mode) { + dfflegalize_args += " [-cell $_DFFE_??_ 01 -cell $_DFFE_?P??_ r -cell $_SDFFE_?P??_ r]"; + } else if (!nodffe) { + dfflegalize_args += " -cell $_DFFE_??_ 01 -cell $_DFFE_?P??_ r -cell $_SDFFE_?P??_ r"; + } + if (help_mode) { + dfflegalize_args += " [-cell $_ALDFF_?P_ x -cell $_ALDFFE_?P?_ x] [-cell $_DLATCH_?_ x]"; + } else if (asyncprld) { + dfflegalize_args += " -cell $_ALDFF_?P_ x -cell $_ALDFFE_?P?_ x"; + } else { + dfflegalize_args += " -cell $_DLATCH_?_ x"; + } + run("dfflegalize" + dfflegalize_args, "($_ALDFF_*_ only if -asyncprld, $_DLATCH_* only if not -asyncprld, $_*DFFE_* only if not -nodffe)"); + if ((abc9 && dff) || help_mode) + run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "(only if -abc9 and -dff)"); + run("techmap -D NO_LUT -map +/lattice/cells_map.v"); + run("opt_expr -undriven -mux_undef"); + run("simplemap"); + run("lattice_gsr"); + run("attrmvcp -copy -attr syn_useioff"); + run("opt_clean"); + } + + if (check_label("map_luts")) + { + if (abc2 || help_mode) + run("abc", " (only if -abc2)"); + if (!asyncprld || help_mode) + run("techmap -map +/lattice/latches_map.v", "(skip if -asyncprld)"); + + if (abc9) { + std::string abc9_opts; + if (nowidelut) + abc9_opts += " -maxlut 4"; + std::string k = "synth_lattice.abc9.W"; + if (active_design && active_design->scratchpad.count(k)) + abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str()); + else + abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str()); + if (nowidelut) + abc9_opts += " -maxlut 4"; + if (dff) + abc9_opts += " -dff"; + run("abc9" + abc9_opts); + } else { + std::string abc_args = " -dress"; + if (nowidelut) + abc_args += " -lut 4"; + else + abc_args += " -lut 4:7"; + if (dff) + abc_args += " -dff"; + run("abc" + abc_args); + } + run("clean"); + } + + if (check_label("map_cells")) + { + if (help_mode) + run("techmap -map +/lattice/cells_map.v", "(skip if -vpr)"); + else if (!vpr) + run("techmap -map +/lattice/cells_map.v"); + run("opt_lut_ins -tech lattice"); + run("clean"); + } + + if (check_label("check")) + { + run("autoname"); + run("hierarchy -check"); + run("stat"); + run("check -noinit"); + run("blackbox =A:whitebox"); + } + + if (check_label("blif")) + { + if (!blif_file.empty() || help_mode) { + if (vpr || help_mode) { + run(stringf("opt_clean -purge"), + " (vpr mode)"); + run(stringf("write_blif -attr -cname -conn -param %s", + help_mode ? "" : blif_file.c_str()), + " (vpr mode)"); + } + if (!vpr) + run(stringf("write_blif -gates -attr -param %s", + help_mode ? "" : blif_file.c_str()), + " (non-vpr mode)"); + } + } + + if (check_label("edif")) + { + if (!edif_file.empty() || help_mode) + run(stringf("write_edif %s", help_mode ? "" : edif_file.c_str())); + } + + if (check_label("json")) + { + if (!json_file.empty() || help_mode) + run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); + } + } +} SynthLatticePass; + +/* +struct SynthEcp5Pass : public Pass +{ + SynthEcp5Pass() : Pass("synth_ecp5", "synthesis for ECP5 FPGAs") { } + + void execute(std::vector args, RTLIL::Design *design) override + { + args[0] = "synth_lattice"; + args.insert(args.begin()+1, std::string()); + args.insert(args.begin()+1, std::string()); + args[1] = "-family"; + args[2] = "ecp5"; + Pass::call(design, args); + } +} SynthEcp5Pass; +*/ + +struct SynthMachXO2Pass : public Pass +{ + SynthMachXO2Pass() : Pass("synth_machxo2", "synthesis for MachXO2 FPGAs.") { } + + void execute(std::vector args, RTLIL::Design *design) override + { + args[0] = "synth_lattice"; + args.insert(args.begin()+1, std::string()); + args.insert(args.begin()+1, std::string()); + args[1] = "-family"; + args[2] = "xo2"; + Pass::call(design, args); + } +} SynthMachXO2Pass; + +struct SynthMachXO3Pass : public Pass +{ + SynthMachXO3Pass() : Pass("synth_machxo3", "synthesis for MachXO3 FPGAs.") { } + + void execute(std::vector args, RTLIL::Design *design) override + { + args[0] = "synth_lattice"; + args.insert(args.begin()+1, std::string()); + args.insert(args.begin()+1, std::string()); + args[1] = "-family"; + args[2] = "xo3"; + Pass::call(design, args); + } +} SynthMachXO3Pass; + +struct SynthMachXO3DPass : public Pass +{ + SynthMachXO3DPass() : Pass("synth_machxo3d", "synthesis for MachXO3D FPGAs.") { } + + void execute(std::vector args, RTLIL::Design *design) override + { + args[0] = "synth_lattice"; + args.insert(args.begin()+1, std::string()); + args.insert(args.begin()+1, std::string()); + args[1] = "-family"; + args[2] = "xo3d"; + Pass::call(design, args); + } +} SynthMachXO3DPass; + +PRIVATE_NAMESPACE_END From 75fd706487d16c3d4cbd48665c86cef1c1f70959 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 23 Aug 2023 10:54:17 +0200 Subject: [PATCH 3/7] delete machxo2 since it is now supported in lattice --- techlibs/machxo2/Makefile.inc | 14 -- techlibs/machxo2/arith_map.v | 90 ------- techlibs/machxo2/brams.txt | 50 ---- techlibs/machxo2/brams_map.v | 337 -------------------------- techlibs/machxo2/cells_bb.v | 227 ------------------ techlibs/machxo2/cells_map.v | 117 --------- techlibs/machxo2/cells_sim.v | 385 ------------------------------ techlibs/machxo2/synth_machxo2.cc | 297 ----------------------- 8 files changed, 1517 deletions(-) delete mode 100644 techlibs/machxo2/Makefile.inc delete mode 100644 techlibs/machxo2/arith_map.v delete mode 100644 techlibs/machxo2/brams.txt delete mode 100644 techlibs/machxo2/brams_map.v delete mode 100644 techlibs/machxo2/cells_bb.v delete mode 100644 techlibs/machxo2/cells_map.v delete mode 100644 techlibs/machxo2/cells_sim.v delete mode 100644 techlibs/machxo2/synth_machxo2.cc diff --git a/techlibs/machxo2/Makefile.inc b/techlibs/machxo2/Makefile.inc deleted file mode 100644 index cd4e27884fc..00000000000 --- a/techlibs/machxo2/Makefile.inc +++ /dev/null @@ -1,14 +0,0 @@ - -OBJS += techlibs/machxo2/synth_machxo2.o - -$(eval $(call add_share_file,share/machxo2,techlibs/ecp5/cells_io.vh)) -$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_map.v)) -$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_sim.v)) -$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_bb.v)) - -$(eval $(call add_share_file,share/machxo2,techlibs/ecp5/lutrams.txt)) -$(eval $(call add_share_file,share/machxo2,techlibs/ecp5/lutrams_map.v)) - -$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/brams.txt)) -$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/brams_map.v)) -$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/arith_map.v)) diff --git a/techlibs/machxo2/arith_map.v b/techlibs/machxo2/arith_map.v deleted file mode 100644 index ab4a6b1da6c..00000000000 --- a/techlibs/machxo2/arith_map.v +++ /dev/null @@ -1,90 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Claire Xenia Wolf - * Copyright (C) 2018 gatecat - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -(* techmap_celltype = "$alu" *) -module _80_ecp5_alu (A, B, CI, BI, X, Y, CO); - parameter A_SIGNED = 0; - parameter B_SIGNED = 0; - parameter A_WIDTH = 1; - parameter B_WIDTH = 1; - parameter Y_WIDTH = 1; - - (* force_downto *) - input [A_WIDTH-1:0] A; - (* force_downto *) - input [B_WIDTH-1:0] B; - (* force_downto *) - output [Y_WIDTH-1:0] X, Y; - - input CI, BI; - (* force_downto *) - output [Y_WIDTH-1:0] CO; - - wire _TECHMAP_FAIL_ = Y_WIDTH <= 4; - - (* force_downto *) - wire [Y_WIDTH-1:0] A_buf, B_buf; - \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); - \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); - - function integer round_up2; - input integer N; - begin - round_up2 = ((N + 1) / 2) * 2; - end - endfunction - - localparam Y_WIDTH2 = round_up2(Y_WIDTH); - - (* force_downto *) - wire [Y_WIDTH2-1:0] AA = A_buf; - (* force_downto *) - wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf; - (* force_downto *) - wire [Y_WIDTH2-1:0] BX = B_buf; - (* force_downto *) - wire [Y_WIDTH2-1:0] C = {CO, CI}; - (* force_downto *) - wire [Y_WIDTH2-1:0] FCO, Y1; - - genvar i; - generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice - CCU2D #( - .INIT0(16'b0101_1010_1001_0110), - .INIT1(16'b0101_1010_1001_0110), - .INJECT1_0("NO"), - .INJECT1_1("NO") - ) ccu2d_i ( - .CIN(C[i]), - .A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b0), - .A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b0), - .S0(Y[i]), .S1(Y1[i]), - .COUT(FCO[i]) - ); - - assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i])); - if (i+1 < Y_WIDTH) begin - assign CO[i+1] = FCO[i]; - assign Y[i+1] = Y1[i]; - end - end endgenerate - - assign X = AA ^ BB; -endmodule diff --git a/techlibs/machxo2/brams.txt b/techlibs/machxo2/brams.txt deleted file mode 100644 index 3afbeda07e6..00000000000 --- a/techlibs/machxo2/brams.txt +++ /dev/null @@ -1,50 +0,0 @@ -ram block $__DP8KC_ { - abits 13; - widths 1 2 4 9 per_port; - cost 64; - init no_undef; - port srsw "A" "B" { - clock posedge; - clken; - portoption "WRITEMODE" "NORMAL" { - rdwr no_change; - } - portoption "WRITEMODE" "WRITETHROUGH" { - rdwr new; - } - portoption "WRITEMODE" "READBEFOREWRITE" { - rdwr old; - } - option "RESETMODE" "SYNC" { - rdsrst zero ungated block_wr; - } - option "RESETMODE" "ASYNC" { - rdarst zero; - } - rdinit zero; - } -} - -ram block $__PDPW8KC_ { - abits 13; - widths 1 2 4 9 18 per_port; - byte 9; - cost 64; - init no_undef; - port sr "R" { - clock posedge; - clken; - option "RESETMODE" "SYNC" { - rdsrst zero ungated; - } - option "RESETMODE" "ASYNC" { - rdarst zero; - } - rdinit zero; - } - port sw "W" { - width 18; - clock posedge; - clken; - } -} diff --git a/techlibs/machxo2/brams_map.v b/techlibs/machxo2/brams_map.v deleted file mode 100644 index 6783e5b2902..00000000000 --- a/techlibs/machxo2/brams_map.v +++ /dev/null @@ -1,337 +0,0 @@ -module $__DP8KC_ (...); - -parameter INIT = 0; -parameter OPTION_RESETMODE = "SYNC"; - -parameter PORT_A_WIDTH = 18; -parameter PORT_A_OPTION_WRITEMODE = "NORMAL"; - -input PORT_A_CLK; -input PORT_A_CLK_EN; -input PORT_A_WR_EN; -input PORT_A_RD_SRST; -input PORT_A_RD_ARST; -input [12:0] PORT_A_ADDR; -input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA; -output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA; - -parameter PORT_B_WIDTH = 18; -parameter PORT_B_OPTION_WRITEMODE = "NORMAL"; - -input PORT_B_CLK; -input PORT_B_CLK_EN; -input PORT_B_WR_EN; -input PORT_B_RD_SRST; -input PORT_B_RD_ARST; -input [12:0] PORT_B_ADDR; -input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA; -output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA; - -function [319:0] init_slice; - input integer idx; - integer i, j; - init_slice = 0; - for (i = 0; i < 16; i = i + 1) begin - init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18]; - end -endfunction - -wire [8:0] DOA; -wire [8:0] DOB; -wire [8:0] DIA = PORT_A_WR_DATA; -wire [8:0] DIB = PORT_B_WR_DATA; - -assign PORT_A_RD_DATA = DOA; -assign PORT_B_RD_DATA = DOB; - -DP8KC #( - .INITVAL_00(init_slice('h00)), - .INITVAL_01(init_slice('h01)), - .INITVAL_02(init_slice('h02)), - .INITVAL_03(init_slice('h03)), - .INITVAL_04(init_slice('h04)), - .INITVAL_05(init_slice('h05)), - .INITVAL_06(init_slice('h06)), - .INITVAL_07(init_slice('h07)), - .INITVAL_08(init_slice('h08)), - .INITVAL_09(init_slice('h09)), - .INITVAL_0A(init_slice('h0a)), - .INITVAL_0B(init_slice('h0b)), - .INITVAL_0C(init_slice('h0c)), - .INITVAL_0D(init_slice('h0d)), - .INITVAL_0E(init_slice('h0e)), - .INITVAL_0F(init_slice('h0f)), - .INITVAL_10(init_slice('h10)), - .INITVAL_11(init_slice('h11)), - .INITVAL_12(init_slice('h12)), - .INITVAL_13(init_slice('h13)), - .INITVAL_14(init_slice('h14)), - .INITVAL_15(init_slice('h15)), - .INITVAL_16(init_slice('h16)), - .INITVAL_17(init_slice('h17)), - .INITVAL_18(init_slice('h18)), - .INITVAL_19(init_slice('h19)), - .INITVAL_1A(init_slice('h1a)), - .INITVAL_1B(init_slice('h1b)), - .INITVAL_1C(init_slice('h1c)), - .INITVAL_1D(init_slice('h1d)), - .INITVAL_1E(init_slice('h1e)), - .INITVAL_1F(init_slice('h1f)), - .DATA_WIDTH_A(PORT_A_WIDTH), - .DATA_WIDTH_B(PORT_B_WIDTH), - .REGMODE_A("NOREG"), - .REGMODE_B("NOREG"), - .RESETMODE(OPTION_RESETMODE), - .ASYNC_RESET_RELEASE(OPTION_RESETMODE), - .CSDECODE_A("0b000"), - .CSDECODE_B("0b000"), - .WRITEMODE_A(PORT_A_OPTION_WRITEMODE), - .WRITEMODE_B(PORT_B_OPTION_WRITEMODE), - .GSR("AUTO") -) _TECHMAP_REPLACE_ ( - .CLKA(PORT_A_CLK), - .WEA(PORT_A_WR_EN), - .CEA(PORT_A_CLK_EN), - .OCEA(1'b1), - .RSTA(OPTION_RESETMODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST), - .CSA0(1'b0), - .CSA1(1'b0), - .CSA2(1'b0), - .ADA0(PORT_A_WIDTH == 9 ? 1'b1 : PORT_A_ADDR[0]), - .ADA1(PORT_A_ADDR[1]), - .ADA2(PORT_A_ADDR[2]), - .ADA3(PORT_A_ADDR[3]), - .ADA4(PORT_A_ADDR[4]), - .ADA5(PORT_A_ADDR[5]), - .ADA6(PORT_A_ADDR[6]), - .ADA7(PORT_A_ADDR[7]), - .ADA8(PORT_A_ADDR[8]), - .ADA9(PORT_A_ADDR[9]), - .ADA10(PORT_A_ADDR[10]), - .ADA11(PORT_A_ADDR[11]), - .ADA12(PORT_A_ADDR[12]), - .DIA0(DIA[0]), - .DIA1(DIA[1]), - .DIA2(DIA[2]), - .DIA3(DIA[3]), - .DIA4(DIA[4]), - .DIA5(DIA[5]), - .DIA6(DIA[6]), - .DIA7(DIA[7]), - .DIA8(DIA[8]), - .DOA0(DOA[0]), - .DOA1(DOA[1]), - .DOA2(DOA[2]), - .DOA3(DOA[3]), - .DOA4(DOA[4]), - .DOA5(DOA[5]), - .DOA6(DOA[6]), - .DOA7(DOA[7]), - .DOA8(DOA[8]), - - .CLKB(PORT_B_CLK), - .WEB(PORT_B_WR_EN), - .CEB(PORT_B_CLK_EN), - .OCEB(1'b1), - .RSTB(OPTION_RESETMODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST), - .CSB0(1'b0), - .CSB1(1'b0), - .CSB2(1'b0), - .ADB0(PORT_B_WIDTH == 9 ? 1'b1 : PORT_B_ADDR[0]), - .ADB1(PORT_B_ADDR[1]), - .ADB2(PORT_B_ADDR[2]), - .ADB3(PORT_B_ADDR[3]), - .ADB4(PORT_B_ADDR[4]), - .ADB5(PORT_B_ADDR[5]), - .ADB6(PORT_B_ADDR[6]), - .ADB7(PORT_B_ADDR[7]), - .ADB8(PORT_B_ADDR[8]), - .ADB9(PORT_B_ADDR[9]), - .ADB10(PORT_B_ADDR[10]), - .ADB11(PORT_B_ADDR[11]), - .ADB12(PORT_B_ADDR[12]), - .DIB0(DIB[0]), - .DIB1(DIB[1]), - .DIB2(DIB[2]), - .DIB3(DIB[3]), - .DIB4(DIB[4]), - .DIB5(DIB[5]), - .DIB6(DIB[6]), - .DIB7(DIB[7]), - .DIB8(DIB[8]), - .DOB0(DOB[0]), - .DOB1(DOB[1]), - .DOB2(DOB[2]), - .DOB3(DOB[3]), - .DOB4(DOB[4]), - .DOB5(DOB[5]), - .DOB6(DOB[6]), - .DOB7(DOB[7]), - .DOB8(DOB[8]), -); - -endmodule - - -module $__PDPW8KC_ (...); - -parameter INIT = 0; -parameter OPTION_RESETMODE = "SYNC"; - -parameter PORT_R_WIDTH = 18; - -input PORT_R_CLK; -input PORT_R_CLK_EN; -input PORT_R_RD_SRST; -input PORT_R_RD_ARST; -input [12:0] PORT_R_ADDR; -output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA; - -parameter PORT_W_WIDTH = 18; -parameter PORT_W_WR_EN_WIDTH = 2; - -input PORT_W_CLK; -input PORT_W_CLK_EN; -input [12:0] PORT_W_ADDR; -input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN; -input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA; - -function [319:0] init_slice; - input integer idx; - integer i, j; - init_slice = 0; - for (i = 0; i < 16; i = i + 1) begin - init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18]; - end -endfunction - -wire [17:0] DI = PORT_W_WR_DATA; -wire [17:0] DO; - -assign PORT_R_RD_DATA = PORT_R_WIDTH == 18 ? DO : DO[17:9]; - -DP8KC #( - .INITVAL_00(init_slice('h00)), - .INITVAL_01(init_slice('h01)), - .INITVAL_02(init_slice('h02)), - .INITVAL_03(init_slice('h03)), - .INITVAL_04(init_slice('h04)), - .INITVAL_05(init_slice('h05)), - .INITVAL_06(init_slice('h06)), - .INITVAL_07(init_slice('h07)), - .INITVAL_08(init_slice('h08)), - .INITVAL_09(init_slice('h09)), - .INITVAL_0A(init_slice('h0a)), - .INITVAL_0B(init_slice('h0b)), - .INITVAL_0C(init_slice('h0c)), - .INITVAL_0D(init_slice('h0d)), - .INITVAL_0E(init_slice('h0e)), - .INITVAL_0F(init_slice('h0f)), - .INITVAL_10(init_slice('h10)), - .INITVAL_11(init_slice('h11)), - .INITVAL_12(init_slice('h12)), - .INITVAL_13(init_slice('h13)), - .INITVAL_14(init_slice('h14)), - .INITVAL_15(init_slice('h15)), - .INITVAL_16(init_slice('h16)), - .INITVAL_17(init_slice('h17)), - .INITVAL_18(init_slice('h18)), - .INITVAL_19(init_slice('h19)), - .INITVAL_1A(init_slice('h1a)), - .INITVAL_1B(init_slice('h1b)), - .INITVAL_1C(init_slice('h1c)), - .INITVAL_1D(init_slice('h1d)), - .INITVAL_1E(init_slice('h1e)), - .INITVAL_1F(init_slice('h1f)), - .DATA_WIDTH_A(PORT_W_WIDTH), - .DATA_WIDTH_B(PORT_R_WIDTH), - .REGMODE_A("NOREG"), - .REGMODE_B("NOREG"), - .RESETMODE(OPTION_RESETMODE), - .ASYNC_RESET_RELEASE(OPTION_RESETMODE), - .CSDECODE_A("0b000"), - .CSDECODE_B("0b000"), - .GSR("AUTO") -) _TECHMAP_REPLACE_ ( - .CLKA(PORT_W_CLK), - .WEA(PORT_W_WIDTH >= 9 ? 1'b1 : PORT_W_WR_EN[0]), - .CEA(PORT_W_CLK_EN), - .OCEA(1'b0), - .RSTA(1'b0), - .CSA0(1'b0), - .CSA1(1'b0), - .CSA2(1'b0), - .ADA0(PORT_W_WIDTH >= 9 ? PORT_W_WR_EN[0] : PORT_W_ADDR[0]), - .ADA1(PORT_W_WIDTH >= 18 ? PORT_W_WR_EN[1] : PORT_W_ADDR[1]), - .ADA2(PORT_W_ADDR[2]), - .ADA3(PORT_W_ADDR[3]), - .ADA4(PORT_W_ADDR[4]), - .ADA5(PORT_W_ADDR[5]), - .ADA6(PORT_W_ADDR[6]), - .ADA7(PORT_W_ADDR[7]), - .ADA8(PORT_W_ADDR[8]), - .ADA9(PORT_W_ADDR[9]), - .ADA10(PORT_W_ADDR[10]), - .ADA11(PORT_W_ADDR[11]), - .ADA12(PORT_W_ADDR[12]), - .DIA0(DI[0]), - .DIA1(DI[1]), - .DIA2(DI[2]), - .DIA3(DI[3]), - .DIA4(DI[4]), - .DIA5(DI[5]), - .DIA6(DI[6]), - .DIA7(DI[7]), - .DIA8(DI[8]), - .DIB0(DI[9]), - .DIB1(DI[10]), - .DIB2(DI[11]), - .DIB3(DI[12]), - .DIB4(DI[13]), - .DIB5(DI[14]), - .DIB6(DI[15]), - .DIB7(DI[16]), - .DIB8(DI[17]), - - .CLKB(PORT_R_CLK), - .WEB(1'b0), - .CEB(PORT_R_CLK_EN), - .OCEB(1'b1), - .RSTB(OPTION_RESETMODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST), - .CSB0(1'b0), - .CSB1(1'b0), - .CSB2(1'b0), - .ADB0(PORT_R_ADDR[0]), - .ADB1(PORT_R_ADDR[1]), - .ADB2(PORT_R_ADDR[2]), - .ADB3(PORT_R_ADDR[3]), - .ADB4(PORT_R_ADDR[4]), - .ADB5(PORT_R_ADDR[5]), - .ADB6(PORT_R_ADDR[6]), - .ADB7(PORT_R_ADDR[7]), - .ADB8(PORT_R_ADDR[8]), - .ADB9(PORT_R_ADDR[9]), - .ADB10(PORT_R_ADDR[10]), - .ADB11(PORT_R_ADDR[11]), - .ADB12(PORT_R_ADDR[12]), - .DOA0(DO[0]), - .DOA1(DO[1]), - .DOA2(DO[2]), - .DOA3(DO[3]), - .DOA4(DO[4]), - .DOA5(DO[5]), - .DOA6(DO[6]), - .DOA7(DO[7]), - .DOA8(DO[8]), - .DOB0(DO[9]), - .DOB1(DO[10]), - .DOB2(DO[11]), - .DOB3(DO[12]), - .DOB4(DO[13]), - .DOB5(DO[14]), - .DOB6(DO[15]), - .DOB7(DO[16]), - .DOB8(DO[17]), -); - -endmodule diff --git a/techlibs/machxo2/cells_bb.v b/techlibs/machxo2/cells_bb.v deleted file mode 100644 index 3d047b1692a..00000000000 --- a/techlibs/machxo2/cells_bb.v +++ /dev/null @@ -1,227 +0,0 @@ -(* blackbox *) -module EHXPLLJ ( - input CLKI, CLKFB, - input PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, - input LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD, - input ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE, - input PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0, - input PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0, - output CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK, - output PLLDATO7, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK, - output DPHSRC, CLKINTFB -); - parameter CLKI_DIV = 1; - parameter CLKFB_DIV = 1; - parameter CLKOP_DIV = 8; - parameter CLKOS_DIV = 8; - parameter CLKOS2_DIV = 8; - parameter CLKOS3_DIV = 8; - parameter CLKOP_ENABLE = "ENABLED"; - parameter CLKOS_ENABLE = "ENABLED"; - parameter CLKOS2_ENABLE = "ENABLED"; - parameter CLKOS3_ENABLE = "ENABLED"; - parameter VCO_BYPASS_A0 = "DISABLED"; - parameter VCO_BYPASS_B0 = "DISABLED"; - parameter VCO_BYPASS_C0 = "DISABLED"; - parameter VCO_BYPASS_D0 = "DISABLED"; - parameter CLKOP_CPHASE = 0; - parameter CLKOS_CPHASE = 0; - parameter CLKOS2_CPHASE = 0; - parameter CLKOS3_CPHASE = 0; - parameter CLKOP_FPHASE = 0; - parameter CLKOS_FPHASE = 0; - parameter CLKOS2_FPHASE = 0; - parameter CLKOS3_FPHASE = 0; - parameter FEEDBK_PATH = "CLKOP"; - parameter FRACN_ENABLE = "DISABLED"; - parameter FRACN_DIV = 0; - parameter CLKOP_TRIM_POL = "RISING"; - parameter CLKOP_TRIM_DELAY = 0; - parameter CLKOS_TRIM_POL = "RISING"; - parameter CLKOS_TRIM_DELAY = 0; - parameter PLL_USE_WB = "DISABLED"; - parameter PREDIVIDER_MUXA1 = 0; - parameter PREDIVIDER_MUXB1 = 0; - parameter PREDIVIDER_MUXC1 = 0; - parameter PREDIVIDER_MUXD1 = 0; - parameter OUTDIVIDER_MUXA2 = "DIVA"; - parameter OUTDIVIDER_MUXB2 = "DIVB"; - parameter OUTDIVIDER_MUXC2 = "DIVC"; - parameter OUTDIVIDER_MUXD2 = "DIVD"; - parameter PLL_LOCK_MODE = 0; - parameter STDBY_ENABLE = "DISABLED"; - parameter DPHASE_SOURCE = "DISABLED"; - parameter PLLRST_ENA = "DISABLED"; - parameter MRST_ENA = "DISABLED"; - parameter DCRST_ENA = "DISABLED"; - parameter DDRST_ENA = "DISABLED"; - parameter INTFB_WAKE = "DISABLED"; -endmodule - -(* blackbox *) -module OSCH #( - parameter NOM_FREQ = "2.08" -) ( - input STDBY, - output OSC, - output SEDSTDBY -); -endmodule - -(* blackbox *) -module DCCA ( - input CLKI, - input CE, - output CLKO -); -endmodule - -(* blackbox *) -module DCMA ( - input CLK0, - input CLK1, - input SEL, - output DCMOUT -); -endmodule - -(* blackbox *) -module PDPW8KC ( - input DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, - input ADW8, ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, - input BE1, BE0, - input CEW, CLKW, CSW2, CSW1, CSW0, - input ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5, ADR4, ADR3, ADR2, ADR1, ADR0, - input CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, - output DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 -); - parameter DATA_WIDTH_W = 18; - parameter DATA_WIDTH_R = 9; - - parameter GSR = "ENABLED"; - - parameter REGMODE = "NOREG"; - - parameter RESETMODE = "SYNC"; - parameter ASYNC_RESET_RELEASE = "SYNC"; - - parameter CSDECODE_W = "0b000"; - parameter CSDECODE_R = "0b000"; - - parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_DATA = "STATIC"; - -endmodule - -(* blackbox *) -module SP8KC ( - input DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, - input AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0, - input CE, OCE, CLK, WE, CS2, CS1, CS0, RST, - output DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 -); - parameter DATA_WIDTH = 9; - parameter GSR = "ENABLED"; - - parameter REGMODE = "NOREG"; - - parameter RESETMODE = "SYNC"; - parameter ASYNC_RESET_RELEASE = "SYNC"; - - parameter CSDECODE = "0b000"; - - parameter WRITEMODE = "NORMAL"; - - parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_DATA = "STATIC"; -endmodule - -(* blackbox *) -module FIFO8KB ( - input DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, - input CSW0, CSW1, CSR0, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI, - output DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17, - input EF, AEF, AFF, FF -); - parameter DATA_WIDTH_W = 18; - parameter DATA_WIDTH_R = 18; - - parameter GSR = "DISABLED"; - - parameter REGMODE = "NOREG"; - - parameter RESETMODE = "ASYNC"; - parameter ASYNC_RESET_RELEASE = "SYNC"; - - parameter CSDECODE_W = "0b00"; - parameter CSDECODE_R = "0b00"; - - parameter AEPOINTER = "0b00000000000000"; - parameter AEPOINTER1 = "0b00000000000000"; - parameter AFPOINTER = "0b00000000000000"; - parameter AFPOINTER1 = "0b00000000000000"; - parameter FULLPOINTER = "0b00000000000000"; - parameter FULLPOINTER1 = "0b00000000000000"; -endmodule diff --git a/techlibs/machxo2/cells_map.v b/techlibs/machxo2/cells_map.v deleted file mode 100644 index 22994a634df..00000000000 --- a/techlibs/machxo2/cells_map.v +++ /dev/null @@ -1,117 +0,0 @@ -module \$_DFF_N_ (input D, C, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) - TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); - else - TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; -endmodule - -module \$_DFF_P_ (input D, C, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) - TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); - else - TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; -endmodule - -module \$_DFFE_NN_ (input D, C, E, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) - TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); - else - TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; -endmodule - -module \$_DFFE_PN_ (input D, C, E, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) - TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); - else - TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; -endmodule - -module \$_DFFE_NP_ (input D, C, E, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) - TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); - else - TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; -endmodule - -module \$_DFFE_PP_ (input D, C, E, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) - TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); - else - TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; -endmodule - -module \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule -module \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule -module \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule -module \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule - -module \$_SDFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule -module \$_SDFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule -module \$_SDFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule -module \$_SDFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule - -module \$_DFFE_NP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule -module \$_DFFE_NP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule -module \$_DFFE_PP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule -module \$_DFFE_PP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule - -module \$_DFFE_NP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule -module \$_DFFE_NP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule -module \$_DFFE_PP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule -module \$_DFFE_PP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule - -module \$_SDFFE_NP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule -module \$_SDFFE_NP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule -module \$_SDFFE_PP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule -module \$_SDFFE_PP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule - -module \$_SDFFE_NP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule -module \$_SDFFE_NP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule -module \$_SDFFE_PP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule -module \$_SDFFE_PP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule - -module \$lut (A, Y); - parameter WIDTH = 0; - parameter LUT = 0; - input [WIDTH-1:0] A; - output Y; - - localparam rep = 1<<(4-WIDTH); - wire [3:0] I; - - generate - if(WIDTH == 1) begin - assign I = {1'b0, 1'b0, 1'b0, A[0]}; - end else if(WIDTH == 2) begin - assign I = {1'b0, 1'b0, A[1], A[0]}; - end else if(WIDTH == 3) begin - assign I = {1'b0, A[2], A[1], A[0]}; - end else if(WIDTH == 4) begin - assign I = {A[3], A[2], A[1], A[0]}; - end else begin - wire _TECHMAP_FAIL_ = 1; - end - endgenerate - - LUT4 #(.INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.A(I[0]), .B(I[1]), .C(I[2]), .D(I[3]), .Z(Y)); -endmodule - -`include "cells_io.vh" diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v deleted file mode 100644 index 8e0e411791c..00000000000 --- a/techlibs/machxo2/cells_sim.v +++ /dev/null @@ -1,385 +0,0 @@ -module LUT2(input A, B, output Z); - parameter [3:0] INIT = 4'h0; - wire [1:0] s1 = B ? INIT[ 3:2] : INIT[1:0]; - assign Z = A ? s1[1] : s1[0]; -endmodule - -module LUT4 #( - parameter [15:0] INIT = 0 -) ( - input A, B, C, D, - output Z -); - // This form of LUT propagates as few x's as possible. - wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0]; - wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0]; - wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0]; - assign Z = A ? s1[1] : s1[0]; -endmodule - -module TRELLIS_FF #( - parameter GSR = "ENABLED", - parameter CEMUX = "1", - parameter CLKMUX = "0", - parameter LSRMUX = "LSR", - parameter LSRONMUX = "LSRMUX", - parameter SRMODE = "LSR_OVER_CE", - parameter REGSET = "SET", - parameter REGMODE = "FF" -) ( - input CLK, DI, LSR, CE, - output reg Q -); - - wire muxce; - generate - case (CEMUX) - "1": assign muxce = 1'b1; - "0": assign muxce = 1'b0; - "INV": assign muxce = ~CE; - default: assign muxce = CE; - endcase - endgenerate - - wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR; - wire muxlsron = (LSRONMUX == "LSRMUX") ? muxlsr : 1'b0; - wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK; - wire srval = (REGSET == "SET") ? 1'b1 : 1'b0; - - initial Q = srval; - - generate - if (REGMODE == "FF") begin - if (SRMODE == "ASYNC") begin - always @(posedge muxclk, posedge muxlsron) - if (muxlsron) - Q <= srval; - else if (muxce) - Q <= DI; - end else begin - always @(posedge muxclk) - if (muxlsron) - Q <= srval; - else if (muxce) - Q <= DI; - end - end else if (REGMODE == "LATCH") begin - ERROR_UNSUPPORTED_FF_MODE error(); - end else begin - ERROR_UNKNOWN_FF_MODE error(); - end - endgenerate -endmodule - -/* For consistency with ECP5; represents F0/F1 => OFX0 mux in a slice. */ -module PFUMX (input ALUT, BLUT, C0, output Z); - assign Z = C0 ? ALUT : BLUT; -endmodule - -/* For consistency with ECP5; represents FXA/FXB => OFX1 mux in a slice. */ -module L6MUX21 (input D0, D1, SD, output Z); - assign Z = SD ? D1 : D0; -endmodule - -/* For consistency, input order matches TRELLIS_SLICE even though the BELs in -prjtrellis were filled in clockwise order from bottom left. */ -module TRELLIS_SLICE #( - parameter MODE = "LOGIC", - parameter GSR = "ENABLED", - parameter SRMODE = "LSR_OVER_CE", - parameter CEMUX = "1", - parameter CLKMUX = "0", - parameter LSRMUX = "LSR", - parameter LSRONMUX = "LSRMUX", - parameter LUT0_INITVAL = 16'hFFFF, - parameter LUT1_INITVAL = 16'hFFFF, - parameter REGMODE = "FF", - parameter REG0_SD = "1", - parameter REG1_SD = "1", - parameter REG0_REGSET = "SET", - parameter REG1_REGSET = "SET", - parameter CCU2_INJECT1_0 = "YES", - parameter CCU2_INJECT1_1 = "YES", - parameter WREMUX = "INV" -) ( - input A0, B0, C0, D0, - input A1, B1, C1, D1, - input M0, M1, - input FCI, FXA, FXB, - - input CLK, LSR, CE, - input DI0, DI1, - - input WD0, WD1, - input WAD0, WAD1, WAD2, WAD3, - input WRE, WCK, - - output F0, Q0, - output F1, Q1, - output FCO, OFX0, OFX1, - - output WDO0, WDO1, WDO2, WDO3, - output WADO0, WADO1, WADO2, WADO3 -); - - generate - if (MODE == "LOGIC") begin - L6MUX21 FXMUX (.D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - wire k0; - wire k1; - PFUMX K0K1MUX (.ALUT(k1), .BLUT(k0), .C0(M0), .Z(OFX0)); - - LUT4 #(.INIT(LUT0_INITVAL)) LUT_0 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(k0)); - LUT4 #(.INIT(LUT1_INITVAL)) LUT_1 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(k1)); - - assign F0 = k0; - assign F1 = k1; - end else if (MODE == "CCU2") begin - ERROR_UNSUPPORTED_SLICE_MODE error(); - end else if (MODE == "DPRAM") begin - ERROR_UNSUPPORTED_SLICE_MODE error(); - end else begin - ERROR_UNKNOWN_SLICE_MODE error(); - end - endgenerate - - /* Reg can be fed either by M, or DI inputs; DI inputs muxes OFX and F - outputs (in other words, feeds back into TRELLIS_SLICE). */ - wire di0 = (REG0_SD == "1") ? DI0 : M0; - wire di1 = (REG1_SD == "1") ? DI1 : M1; - - TRELLIS_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX), - .LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG0_REGSET), - .REGMODE(REGMODE)) REG_0 (.CLK(CLK), .DI(di0), .LSR(LSR), .CE(CE), .Q(Q0)); - TRELLIS_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX), - .LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG1_REGSET), - .REGMODE(REGMODE)) REG_1 (.CLK(CLK), .DI(di1), .LSR(LSR), .CE(CE), .Q(Q1)); -endmodule - -module TRELLIS_IO #( - parameter DIR = "INPUT" -) ( - (* iopad_external_pin *) - inout B, - input I, T, - output O -); - generate - if (DIR == "INPUT") begin - assign O = B; - end else if (DIR == "OUTPUT") begin - assign B = T ? 1'bz : I; - end else if (DIR == "BIDIR") begin - assign B = T ? 1'bz : I; - assign O = B; - end else begin - ERROR_UNKNOWN_IO_MODE error(); - end - endgenerate -endmodule - -(* abc9_box, lib_whitebox *) -module TRELLIS_DPR16X4 ( - input [3:0] DI, - input [3:0] WAD, - input WRE, - input WCK, - input [3:0] RAD, - output [3:0] DO -); - parameter WCKMUX = "WCK"; - parameter WREMUX = "WRE"; - parameter [63:0] INITVAL = 64'h0000000000000000; - - reg [3:0] mem[15:0]; - - integer i; - initial begin - for (i = 0; i < 16; i = i + 1) - mem[i] <= INITVAL[4*i +: 4]; - end - - wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK; - - reg muxwre; - always @(*) - case (WREMUX) - "1": muxwre = 1'b1; - "0": muxwre = 1'b0; - "INV": muxwre = ~WRE; - default: muxwre = WRE; - endcase - - always @(posedge muxwck) - if (muxwre) - mem[WAD] <= DI; - - assign DO = mem[RAD]; - - specify - // TODO - (RAD *> DO) = 0; - endspecify -endmodule - -(* abc9_box, lib_whitebox *) -module DPR16X4C ( - input [3:0] DI, - input WCK, WRE, - input [3:0] RAD, - input [3:0] WAD, - output [3:0] DO -); - parameter INITVAL = "0x0000000000000000"; - - function [63:0] convert_initval; - input [143:0] hex_initval; - reg done; - reg [63:0] temp; - reg [7:0] char; - integer i; - begin - done = 1'b0; - temp = 0; - for (i = 0; i < 16; i = i + 1) begin - if (!done) begin - char = hex_initval[8*i +: 8]; - if (char == "x") begin - done = 1'b1; - end else begin - if (char >= "0" && char <= "9") - temp[4*i +: 4] = char - "0"; - else if (char >= "A" && char <= "F") - temp[4*i +: 4] = 10 + char - "A"; - else if (char >= "a" && char <= "f") - temp[4*i +: 4] = 10 + char - "a"; - end - end - end - convert_initval = temp; - end - endfunction - - localparam conv_initval = convert_initval(INITVAL); - - reg [3:0] ram[0:15]; - integer i; - initial begin - for (i = 0; i < 15; i = i + 1) begin - ram[i] <= conv_initval[4*i +: 4]; - end - end - - always @(posedge WCK) - if (WRE) - ram[WAD] <= DI; - - assign DO = ram[RAD]; -endmodule - -// --------------------------------------- -(* lib_whitebox *) -module CCU2D ( - input CIN, - input A0, B0, C0, D0, A1, B1, C1, D1, - output S0, S1, - output COUT -); - parameter [15:0] INIT0 = 16'h0000; - parameter [15:0] INIT1 = 16'h0000; - parameter INJECT1_0 = "YES"; - parameter INJECT1_1 = "YES"; - - // First half - wire LUT4_0, LUT2_0; - LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0)); - LUT2 #(.INIT(~INIT0[15:12])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0)); - wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN; - assign S0 = LUT4_0 ^ gated_cin_0; - - wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0; - wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN); - - // Second half - wire LUT4_1, LUT2_1; - LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1)); - LUT2 #(.INIT(~INIT1[15:12])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1)); - wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0; - assign S1 = LUT4_1 ^ gated_cin_1; - - wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1; - assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0); -endmodule - -(* blackbox *) -module DP8KC( - input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, - input ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0, - input CEA, OCEA, CLKA, WEA, RSTA, - input CSA2, CSA1, CSA0, - output DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, - - input DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0, - input ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, - input CEB, OCEB, CLKB, WEB, RSTB, - input CSB2, CSB1, CSB0, - output DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0 -); - parameter DATA_WIDTH_A = 9; - parameter DATA_WIDTH_B = 9; - - parameter REGMODE_A = "NOREG"; - parameter REGMODE_B = "NOREG"; - - parameter RESETMODE = "SYNC"; - parameter ASYNC_RESET_RELEASE = "SYNC"; - - parameter CSDECODE_A = "0b000"; - parameter CSDECODE_B = "0b000"; - - parameter WRITEMODE_A = "NORMAL"; - parameter WRITEMODE_B = "NORMAL"; - - parameter GSR = "ENABLED"; - parameter INIT_DATA = "STATIC"; - - parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; -endmodule - -`ifndef NO_INCLUDES - -`include "cells_io.vh" - -`endif diff --git a/techlibs/machxo2/synth_machxo2.cc b/techlibs/machxo2/synth_machxo2.cc deleted file mode 100644 index 907c6659ed8..00000000000 --- a/techlibs/machxo2/synth_machxo2.cc +++ /dev/null @@ -1,297 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2020 William D. Jones - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "kernel/register.h" -#include "kernel/celltypes.h" -#include "kernel/rtlil.h" -#include "kernel/log.h" - -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN - -struct SynthMachXO2Pass : public ScriptPass -{ - SynthMachXO2Pass() : ScriptPass("synth_machxo2", "synthesis for MachXO2 FPGAs. This work is experimental.") { } - - void help() override - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" synth_machxo2 [options]\n"); - log("\n"); - log("This command runs synthesis for MachXO2 FPGAs.\n"); - log("\n"); - log(" -top \n"); - log(" use the specified module as top module\n"); - log("\n"); - log(" -blif \n"); - log(" write the design to the specified BLIF file. writing of an output file\n"); - log(" is omitted if this parameter is not specified.\n"); - log("\n"); - log(" -edif \n"); - log(" write the design to the specified EDIF file. writing of an output file\n"); - log(" is omitted if this parameter is not specified.\n"); - log("\n"); - log(" -json \n"); - log(" write the design to the specified JSON file. writing of an output file\n"); - log(" is omitted if this parameter is not specified.\n"); - log("\n"); - log(" -run :\n"); - log(" only run the commands between the labels (see below). an empty\n"); - log(" from label is synonymous to 'begin', and empty to label is\n"); - log(" synonymous to the end of the command list.\n"); - log("\n"); - log(" -nobram\n"); - log(" do not use block RAM cells in output netlist\n"); - log("\n"); - log(" -nolutram\n"); - log(" do not use LUT RAM cells in output netlist\n"); - log("\n"); - log(" -noflatten\n"); - log(" do not flatten design before synthesis\n"); - log("\n"); - log(" -noiopad\n"); - log(" do not insert IO buffers\n"); - log("\n"); - log(" -ccu2\n"); - log(" use CCU2 cells in output netlist\n"); - log("\n"); - log(" -vpr\n"); - log(" generate an output netlist (and BLIF file) suitable for VPR\n"); - log(" (this feature is experimental and incomplete)\n"); - log("\n"); - log("\n"); - log("The following commands are executed by this synthesis command:\n"); - help_script(); - log("\n"); - } - - string top_opt, blif_file, edif_file, json_file; - bool ccu2, nobram, nolutram, flatten, vpr, noiopad; - - void clear_flags() override - { - top_opt = "-auto-top"; - blif_file = ""; - edif_file = ""; - json_file = ""; - ccu2 = false; - nobram = false; - nolutram = false; - flatten = true; - vpr = false; - noiopad = false; - } - - void execute(std::vector args, RTLIL::Design *design) override - { - string run_from, run_to; - clear_flags(); - - size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) - { - if (args[argidx] == "-top" && argidx+1 < args.size()) { - top_opt = "-top " + args[++argidx]; - continue; - } - if (args[argidx] == "-blif" && argidx+1 < args.size()) { - blif_file = args[++argidx]; - continue; - } - if (args[argidx] == "-edif" && argidx+1 < args.size()) { - edif_file = args[++argidx]; - continue; - } - if (args[argidx] == "-json" && argidx+1 < args.size()) { - json_file = args[++argidx]; - continue; - } - if (args[argidx] == "-run" && argidx+1 < args.size()) { - size_t pos = args[argidx+1].find(':'); - if (pos == std::string::npos) - break; - run_from = args[++argidx].substr(0, pos); - run_to = args[argidx].substr(pos+1); - continue; - } - if (args[argidx] == "-flatten") { - flatten = true; - continue; - } - if (args[argidx] == "-noflatten") { - flatten = false; - continue; - } - if (args[argidx] == "-nobram") { - nobram = true; - continue; - } - if (args[argidx] == "-nolutram") { - nolutram = true; - continue; - } - if (args[argidx] == "-noiopad") { - noiopad = true; - continue; - } - if (args[argidx] == "-ccu2") { - ccu2 = true; - continue; - } - if (args[argidx] == "-vpr") { - vpr = true; - continue; - } - break; - } - extra_args(args, argidx, design); - - if (!design->full_selection()) - log_cmd_error("This command only operates on fully selected designs!\n"); - - log_header(design, "Executing SYNTH_MACHXO2 pass.\n"); - log_push(); - - run_script(design, run_from, run_to); - - log_pop(); - } - - void script() override - { - if (check_label("begin")) - { - run("read_verilog -lib -icells +/machxo2/cells_sim.v +/machxo2/cells_bb.v"); - run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); - } - - if (check_label("flatten", "(unless -noflatten)")) - { - if (flatten || help_mode) { - run("proc"); - run("flatten"); - run("tribuf -logic"); - run("deminout"); - } - } - - if (check_label("coarse")) - { - run("synth -run coarse"); - } - - if (check_label("map_ram")) - { - std::string args = ""; - if (nobram) - args += " -no-auto-block"; - if (nolutram) - args += " -no-auto-distributed"; - if (help_mode) - args += " [-no-auto-block] [-no-auto-distributed]"; - run("memory_libmap -lib +/machxo2/lutrams.txt -lib +/machxo2/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)"); - run("techmap -map +/machxo2/lutrams_map.v -map +/machxo2/brams_map.v"); - } - - if (check_label("fine")) - { - run("opt -fast -mux_undef -undriven -fine"); - run("memory_map"); - run("opt -undriven -fine"); - } - - if (check_label("map_gates", "(unless -noiopad)")) - { - if (!ccu2) - run("techmap"); - else - run("techmap -map +/techmap.v -map +/machxo2/arith_map.v"); - if (!noiopad || help_mode) - { - run("iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad OBZ ~T:I:O -tinoutpad BB ~T:O:I:B A:top", "(only if '-iopad')"); - run("attrmvcp -attr src -attr LOC t:OB %x:+[O] t:OBZ %x:+[O] t:BB %x:+[B]"); - run("attrmvcp -attr src -attr LOC -driven t:IB %x:+[I]"); - } - } - - if (check_label("map_ffs")) - { - run("opt_clean"); - std::string dfflegalize_args = " -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r"; - run("dfflegalize" + dfflegalize_args); - run("techmap -D NO_LUT -map +/machxo2/cells_map.v"); - run("opt_expr -undriven -mux_undef"); - run("simplemap"); - run("lattice_gsr"); - run("attrmvcp -copy -attr syn_useioff"); - run("opt_clean"); - } - - if (check_label("map_luts")) - { - run("abc -lut 4 -dress"); - run("clean"); - } - - if (check_label("map_cells")) - { - run("techmap -map +/machxo2/cells_map.v"); - run("clean"); - } - - if (check_label("check")) - { - run("hierarchy -check"); - run("stat"); - run("blackbox =A:whitebox"); - } - - if (check_label("blif")) - { - if (!blif_file.empty() || help_mode) { - if (vpr || help_mode) { - run(stringf("opt_clean -purge"), - " (vpr mode)"); - run(stringf("write_blif -attr -cname -conn -param %s", - help_mode ? "" : blif_file.c_str()), - " (vpr mode)"); - } - if (!vpr) - run(stringf("write_blif -gates -attr -param %s", - help_mode ? "" : blif_file.c_str()), - " (non-vpr mode)"); - } - } - - if (check_label("edif")) - { - if (!edif_file.empty() || help_mode) - run(stringf("write_edif %s", help_mode ? "" : edif_file.c_str())); - } - - if (check_label("json")) - { - if (!json_file.empty() || help_mode) - run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); - } - } -} SynthMachXO2Pass; - -PRIVATE_NAMESPACE_END From ea50d96135ad5c337f41169c08383c460bf97e83 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 23 Aug 2023 10:54:29 +0200 Subject: [PATCH 4/7] fixed tests --- tests/arch/machxo2/add_sub.ys | 2 +- tests/arch/machxo2/adffs.ys | 8 ++++---- tests/arch/machxo2/counter.ys | 2 +- tests/arch/machxo2/dffs.ys | 6 +++--- tests/arch/machxo2/fsm.ys | 2 +- tests/arch/machxo2/logic.ys | 2 +- tests/arch/machxo2/lutram.ys | 2 +- tests/arch/machxo2/mux.ys | 8 ++++---- tests/arch/machxo2/shifter.ys | 2 +- tests/arch/machxo2/tribuf.ys | 7 +++---- 10 files changed, 20 insertions(+), 21 deletions(-) diff --git a/tests/arch/machxo2/add_sub.ys b/tests/arch/machxo2/add_sub.ys index 97ee90fbbe2..6897363aaee 100644 --- a/tests/arch/machxo2/add_sub.ys +++ b/tests/arch/machxo2/add_sub.ys @@ -1,7 +1,7 @@ read_verilog ../common/add_sub.v hierarchy -top top proc -equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 10 t:LUT4 diff --git a/tests/arch/machxo2/adffs.ys b/tests/arch/machxo2/adffs.ys index a9f8980c6e4..f1134a6ac67 100644 --- a/tests/arch/machxo2/adffs.ys +++ b/tests/arch/machxo2/adffs.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top adff proc -equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check +equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module select -assert-count 1 t:TRELLIS_FF @@ -12,7 +12,7 @@ select -assert-none t:TRELLIS_FF %% t:* %D design -load read hierarchy -top adffn proc -equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check +equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module select -assert-count 1 t:TRELLIS_FF @@ -22,7 +22,7 @@ select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D design -load read hierarchy -top dffs proc -equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check +equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:TRELLIS_FF @@ -32,7 +32,7 @@ select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D design -load read hierarchy -top ndffnr proc -equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check +equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:TRELLIS_FF diff --git a/tests/arch/machxo2/counter.ys b/tests/arch/machxo2/counter.ys index 54ee80066ff..11560b551fc 100644 --- a/tests/arch/machxo2/counter.ys +++ b/tests/arch/machxo2/counter.ys @@ -2,7 +2,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -assert -multiclock -map +/machxo2/cells_sim.v synth_machxo2 -ccu2 -noiopad # equivalency check +equiv_opt -assert -multiclock -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 4 t:CCU2D diff --git a/tests/arch/machxo2/dffs.ys b/tests/arch/machxo2/dffs.ys index 29dcafe2383..663a64294bf 100644 --- a/tests/arch/machxo2/dffs.ys +++ b/tests/arch/machxo2/dffs.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top dff proc -equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module select -assert-count 1 t:TRELLIS_FF @@ -12,8 +12,8 @@ select -assert-none t:TRELLIS_FF t:TRELLIS_IO %% t:* %D design -load read hierarchy -top dffe proc -equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module -select -assert-count 2 t:TRELLIS_FF t:LUT4 +select -assert-count 1 t:TRELLIS_FF t:LUT4 select -assert-none t:TRELLIS_FF t:LUT4 t:TRELLIS_IO %% t:* %D diff --git a/tests/arch/machxo2/fsm.ys b/tests/arch/machxo2/fsm.ys index a61357fcdd2..70e1a632bdf 100644 --- a/tests/arch/machxo2/fsm.ys +++ b/tests/arch/machxo2/fsm.ys @@ -3,7 +3,7 @@ hierarchy -top fsm proc flatten -equiv_opt -run :prove -map +/machxo2/cells_sim.v synth_machxo2 +equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut miter -equiv -make_assert -flatten gold gate miter sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter diff --git a/tests/arch/machxo2/logic.ys b/tests/arch/machxo2/logic.ys index 0cf57310c81..5c799530519 100644 --- a/tests/arch/machxo2/logic.ys +++ b/tests/arch/machxo2/logic.ys @@ -1,7 +1,7 @@ read_verilog ../common/logic.v hierarchy -top top proc -equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 9 t:LUT4 diff --git a/tests/arch/machxo2/lutram.ys b/tests/arch/machxo2/lutram.ys index dc6b86fd349..8f1918587c9 100644 --- a/tests/arch/machxo2/lutram.ys +++ b/tests/arch/machxo2/lutram.ys @@ -2,7 +2,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w1r proc memory -nomap -equiv_opt -run :prove -map +/machxo2/cells_sim.v synth_machxo2 -noiopad +equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut memory opt -full diff --git a/tests/arch/machxo2/mux.ys b/tests/arch/machxo2/mux.ys index 27bffbe63aa..4fa1bd2fcc8 100644 --- a/tests/arch/machxo2/mux.ys +++ b/tests/arch/machxo2/mux.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top mux2 proc -equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT4 @@ -12,7 +12,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D design -load read hierarchy -top mux4 proc -equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module select -assert-count 2 t:LUT4 @@ -22,7 +22,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D design -load read hierarchy -top mux8 proc -equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module select -assert-count 5 t:LUT4 @@ -32,7 +32,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D design -load read hierarchy -top mux16 proc -equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module select -assert-max 12 t:LUT4 diff --git a/tests/arch/machxo2/shifter.ys b/tests/arch/machxo2/shifter.ys index bff881fb734..f6440c025e8 100644 --- a/tests/arch/machxo2/shifter.ys +++ b/tests/arch/machxo2/shifter.ys @@ -2,7 +2,7 @@ read_verilog ../common/shifter.v hierarchy -top top proc flatten -equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/machxo2/tribuf.ys b/tests/arch/machxo2/tribuf.ys index 840979439f8..08c86008da5 100644 --- a/tests/arch/machxo2/tribuf.ys +++ b/tests/arch/machxo2/tribuf.ys @@ -2,9 +2,8 @@ read_verilog ../common/tribuf.v hierarchy -top tristate proc flatten -equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v -map +/simcells.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd tristate # Constrain all select calls below inside the top module -select -assert-count 3 t:TRELLIS_IO -select -assert-count 1 t:LUT4 -select -assert-none t:TRELLIS_IO t:LUT4 %% t:* %D +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D From 541c1ab567cb060cfc528b0143404e62efef126b Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 23 Aug 2023 11:51:00 +0200 Subject: [PATCH 5/7] add script for blackbox extraction --- techlibs/lattice/cells_bb_ecp5.v | 3040 ++++++++++++++++++++---------- techlibs/lattice/cells_bb_xo2.v | 634 +++++-- techlibs/lattice/cells_bb_xo3.v | 634 +++++-- techlibs/lattice/cells_bb_xo3d.v | 635 +++++-- techlibs/lattice/cells_xtra.py | 854 +++++++++ 5 files changed, 4244 insertions(+), 1553 deletions(-) create mode 100644 techlibs/lattice/cells_xtra.py diff --git a/techlibs/lattice/cells_bb_ecp5.v b/techlibs/lattice/cells_bb_ecp5.v index 5cb90b97efc..9c4d1fde4ef 100644 --- a/techlibs/lattice/cells_bb_ecp5.v +++ b/techlibs/lattice/cells_bb_ecp5.v @@ -1,1067 +1,2177 @@ -// ECP5 Blackbox cells -// FIXME: Create sim models +// Created by cells_xtra.py from Lattice models -(* blackbox *) -module DP16KD( - input DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9, DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, - input ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0, - input CEA, OCEA, CLKA, WEA, RSTA, - input CSA2, CSA1, CSA0, - output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, - - input DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0, - input ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, - input CEB, OCEB, CLKB, WEB, RSTB, - input CSB2, CSB1, CSB0, - output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0 -); - parameter DATA_WIDTH_A = 18; - parameter DATA_WIDTH_B = 18; - - parameter REGMODE_A = "NOREG"; - parameter REGMODE_B = "NOREG"; - - parameter RESETMODE = "SYNC"; - parameter ASYNC_RESET_RELEASE = "SYNC"; - - parameter CSDECODE_A = "0b000"; - parameter CSDECODE_B = "0b000"; - - parameter WRITEMODE_A = "NORMAL"; - parameter WRITEMODE_B = "NORMAL"; - - parameter DIA17MUX = "DIA17"; - parameter DIA16MUX = "DIA16"; - parameter DIA15MUX = "DIA15"; - parameter DIA14MUX = "DIA14"; - parameter DIA13MUX = "DIA13"; - parameter DIA12MUX = "DIA12"; - parameter DIA11MUX = "DIA11"; - parameter DIA10MUX = "DIA10"; - parameter DIA9MUX = "DIA9"; - parameter DIA8MUX = "DIA8"; - parameter DIA7MUX = "DIA7"; - parameter DIA6MUX = "DIA6"; - parameter DIA5MUX = "DIA5"; - parameter DIA4MUX = "DIA4"; - parameter DIA3MUX = "DIA3"; - parameter DIA2MUX = "DIA2"; - parameter DIA1MUX = "DIA1"; - parameter DIA0MUX = "DIA0"; - parameter ADA13MUX = "ADA13"; - parameter ADA12MUX = "ADA12"; - parameter ADA11MUX = "ADA11"; - parameter ADA10MUX = "ADA10"; - parameter ADA9MUX = "ADA9"; - parameter ADA8MUX = "ADA8"; - parameter ADA7MUX = "ADA7"; - parameter ADA6MUX = "ADA6"; - parameter ADA5MUX = "ADA5"; - parameter ADA4MUX = "ADA4"; - parameter ADA3MUX = "ADA3"; - parameter ADA2MUX = "ADA2"; - parameter ADA1MUX = "ADA1"; - parameter ADA0MUX = "ADA0"; - parameter CEAMUX = "CEA"; - parameter OCEAMUX = "OCEA"; - parameter CLKAMUX = "CLKA"; - parameter WEAMUX = "WEA"; - parameter RSTAMUX = "RSTA"; - parameter CSA2MUX = "CSA2"; - parameter CSA1MUX = "CSA1"; - parameter CSA0MUX = "CSA0"; - parameter DOA17MUX = "DOA17"; - parameter DOA16MUX = "DOA16"; - parameter DOA15MUX = "DOA15"; - parameter DOA14MUX = "DOA14"; - parameter DOA13MUX = "DOA13"; - parameter DOA12MUX = "DOA12"; - parameter DOA11MUX = "DOA11"; - parameter DOA10MUX = "DOA10"; - parameter DOA9MUX = "DOA9"; - parameter DOA8MUX = "DOA8"; - parameter DOA7MUX = "DOA7"; - parameter DOA6MUX = "DOA6"; - parameter DOA5MUX = "DOA5"; - parameter DOA4MUX = "DOA4"; - parameter DOA3MUX = "DOA3"; - parameter DOA2MUX = "DOA2"; - parameter DOA1MUX = "DOA1"; - parameter DOA0MUX = "DOA0"; - parameter DIB17MUX = "DIB17"; - parameter DIB16MUX = "DIB16"; - parameter DIB15MUX = "DIB15"; - parameter DIB14MUX = "DIB14"; - parameter DIB13MUX = "DIB13"; - parameter DIB12MUX = "DIB12"; - parameter DIB11MUX = "DIB11"; - parameter DIB10MUX = "DIB10"; - parameter DIB9MUX = "DIB9"; - parameter DIB8MUX = "DIB8"; - parameter DIB7MUX = "DIB7"; - parameter DIB6MUX = "DIB6"; - parameter DIB5MUX = "DIB5"; - parameter DIB4MUX = "DIB4"; - parameter DIB3MUX = "DIB3"; - parameter DIB2MUX = "DIB2"; - parameter DIB1MUX = "DIB1"; - parameter DIB0MUX = "DIB0"; - parameter ADB13MUX = "ADB13"; - parameter ADB12MUX = "ADB12"; - parameter ADB11MUX = "ADB11"; - parameter ADB10MUX = "ADB10"; - parameter ADB9MUX = "ADB9"; - parameter ADB8MUX = "ADB8"; - parameter ADB7MUX = "ADB7"; - parameter ADB6MUX = "ADB6"; - parameter ADB5MUX = "ADB5"; - parameter ADB4MUX = "ADB4"; - parameter ADB3MUX = "ADB3"; - parameter ADB2MUX = "ADB2"; - parameter ADB1MUX = "ADB1"; - parameter ADB0MUX = "ADB0"; - parameter CEBMUX = "CEB"; - parameter OCEBMUX = "OCEB"; - parameter CLKBMUX = "CLKB"; - parameter WEBMUX = "WEB"; - parameter RSTBMUX = "RSTB"; - parameter CSB2MUX = "CSB2"; - parameter CSB1MUX = "CSB1"; - parameter CSB0MUX = "CSB0"; - parameter DOB17MUX = "DOB17"; - parameter DOB16MUX = "DOB16"; - parameter DOB15MUX = "DOB15"; - parameter DOB14MUX = "DOB14"; - parameter DOB13MUX = "DOB13"; - parameter DOB12MUX = "DOB12"; - parameter DOB11MUX = "DOB11"; - parameter DOB10MUX = "DOB10"; - parameter DOB9MUX = "DOB9"; - parameter DOB8MUX = "DOB8"; - parameter DOB7MUX = "DOB7"; - parameter DOB6MUX = "DOB6"; - parameter DOB5MUX = "DOB5"; - parameter DOB4MUX = "DOB4"; - parameter DOB3MUX = "DOB3"; - parameter DOB2MUX = "DOB2"; - parameter DOB1MUX = "DOB1"; - parameter DOB0MUX = "DOB0"; - - parameter WID = 0; - - parameter GSR = "ENABLED"; - - parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_DATA = "STATIC"; +(* blackbox *) (* keep *) +module GSR (...); + input GSR; endmodule (* blackbox *) -module MULT18X18D( - input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, - input B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, - input C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, - input SIGNEDA, SIGNEDB, SOURCEA, SOURCEB, - input CLK0, CLK1, CLK2, CLK3, - input CE0, CE1, CE2, CE3, - input RST0, RST1, RST2, RST3, - input SRIA0, SRIA1, SRIA2, SRIA3, SRIA4, SRIA5, SRIA6, SRIA7, SRIA8, SRIA9, SRIA10, SRIA11, SRIA12, SRIA13, SRIA14, SRIA15, SRIA16, SRIA17, - input SRIB0, SRIB1, SRIB2, SRIB3, SRIB4, SRIB5, SRIB6, SRIB7, SRIB8, SRIB9, SRIB10, SRIB11, SRIB12, SRIB13, SRIB14, SRIB15, SRIB16, SRIB17, - output SROA0, SROA1, SROA2, SROA3, SROA4, SROA5, SROA6, SROA7, SROA8, SROA9, SROA10, SROA11, SROA12, SROA13, SROA14, SROA15, SROA16, SROA17, - output SROB0, SROB1, SROB2, SROB3, SROB4, SROB5, SROB6, SROB7, SROB8, SROB9, SROB10, SROB11, SROB12, SROB13, SROB14, SROB15, SROB16, SROB17, - output ROA0, ROA1, ROA2, ROA3, ROA4, ROA5, ROA6, ROA7, ROA8, ROA9, ROA10, ROA11, ROA12, ROA13, ROA14, ROA15, ROA16, ROA17, - output ROB0, ROB1, ROB2, ROB3, ROB4, ROB5, ROB6, ROB7, ROB8, ROB9, ROB10, ROB11, ROB12, ROB13, ROB14, ROB15, ROB16, ROB17, - output ROC0, ROC1, ROC2, ROC3, ROC4, ROC5, ROC6, ROC7, ROC8, ROC9, ROC10, ROC11, ROC12, ROC13, ROC14, ROC15, ROC16, ROC17, - output P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26, P27, P28, P29, P30, P31, P32, P33, P34, P35, - output SIGNEDP -); - parameter REG_INPUTA_CLK = "NONE"; - parameter REG_INPUTA_CE = "CE0"; - parameter REG_INPUTA_RST = "RST0"; - parameter REG_INPUTB_CLK = "NONE"; - parameter REG_INPUTB_CE = "CE0"; - parameter REG_INPUTB_RST = "RST0"; - parameter REG_INPUTC_CLK = "NONE"; - parameter REG_INPUTC_CE = "CE0"; - parameter REG_INPUTC_RST = "RST0"; - parameter REG_PIPELINE_CLK = "NONE"; - parameter REG_PIPELINE_CE = "CE0"; - parameter REG_PIPELINE_RST = "RST0"; - parameter REG_OUTPUT_CLK = "NONE"; - parameter REG_OUTPUT_CE = "CE0"; - parameter REG_OUTPUT_RST = "RST0"; - parameter [127:0] CLK0_DIV = "ENABLED"; - parameter [127:0] CLK1_DIV = "ENABLED"; - parameter [127:0] CLK2_DIV = "ENABLED"; - parameter [127:0] CLK3_DIV = "ENABLED"; - parameter HIGHSPEED_CLK = "NONE"; - parameter [127:0] GSR = "ENABLED"; - parameter CAS_MATCH_REG = "FALSE"; - parameter [127:0] SOURCEB_MODE = "B_SHIFT"; - parameter [127:0] MULT_BYPASS = "DISABLED"; - parameter [127:0] RESETMODE = "SYNC"; +module PUR (...); + parameter RST_PULSE = 1; + input PUR; endmodule -(* blackbox *) -module ALU54B( - input CLK0, CLK1, CLK2, CLK3, - input CE0, CE1, CE2, CE3, - input RST0, RST1, RST2, RST3, - input SIGNEDIA, SIGNEDIB, SIGNEDCIN, - input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, A32, A33, A34, A35, - input B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18, B19, B20, B21, B22, B23, B24, B25, B26, B27, B28, B29, B30, B31, B32, B33, B34, B35, - input C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, C37, C38, C39, C40, C41, C42, C43, C44, C45, C46, C47, C48, C49, C50, C51, C52, C53, - input CFB0, CFB1, CFB2, CFB3, CFB4, CFB5, CFB6, CFB7, CFB8, CFB9, CFB10, CFB11, CFB12, CFB13, CFB14, CFB15, CFB16, CFB17, CFB18, CFB19, CFB20, CFB21, CFB22, CFB23, CFB24, CFB25, CFB26, CFB27, CFB28, CFB29, CFB30, CFB31, CFB32, CFB33, CFB34, CFB35, CFB36, CFB37, CFB38, CFB39, CFB40, CFB41, CFB42, CFB43, CFB44, CFB45, CFB46, CFB47, CFB48, CFB49, CFB50, CFB51, CFB52, CFB53, - input MA0, MA1, MA2, MA3, MA4, MA5, MA6, MA7, MA8, MA9, MA10, MA11, MA12, MA13, MA14, MA15, MA16, MA17, MA18, MA19, MA20, MA21, MA22, MA23, MA24, MA25, MA26, MA27, MA28, MA29, MA30, MA31, MA32, MA33, MA34, MA35, - input MB0, MB1, MB2, MB3, MB4, MB5, MB6, MB7, MB8, MB9, MB10, MB11, MB12, MB13, MB14, MB15, MB16, MB17, MB18, MB19, MB20, MB21, MB22, MB23, MB24, MB25, MB26, MB27, MB28, MB29, MB30, MB31, MB32, MB33, MB34, MB35, - input CIN0, CIN1, CIN2, CIN3, CIN4, CIN5, CIN6, CIN7, CIN8, CIN9, CIN10, CIN11, CIN12, CIN13, CIN14, CIN15, CIN16, CIN17, CIN18, CIN19, CIN20, CIN21, CIN22, CIN23, CIN24, CIN25, CIN26, CIN27, CIN28, CIN29, CIN30, CIN31, CIN32, CIN33, CIN34, CIN35, CIN36, CIN37, CIN38, CIN39, CIN40, CIN41, CIN42, CIN43, CIN44, CIN45, CIN46, CIN47, CIN48, CIN49, CIN50, CIN51, CIN52, CIN53, - input OP0, OP1, OP2, OP3, OP4, OP5, OP6, OP7, OP8, OP9, OP10, - output R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, - output CO0, CO1, CO2, CO3, CO4, CO5, CO6, CO7, CO8, CO9, CO10, CO11, CO12, CO13, CO14, CO15, CO16, CO17, CO18, CO19, CO20, CO21, CO22, CO23, CO24, CO25, CO26, CO27, CO28, CO29, CO30, CO31, CO32, CO33, CO34, CO35, CO36, CO37, CO38, CO39, CO40, CO41, CO42, CO43, CO44, CO45, CO46, CO47, CO48, CO49, CO50, CO51, CO52, CO53, - output EQZ, EQZM, EQOM, EQPAT, EQPATB, - output OVER, UNDER, OVERUNDER, - output SIGNEDR -); - parameter REG_INPUTC0_CLK = "NONE"; - parameter REG_INPUTC0_CE = "CE0"; - parameter REG_INPUTC0_RST = "RST0"; - parameter REG_INPUTC1_CLK = "NONE"; - parameter REG_INPUTC1_CE = "CE0"; - parameter REG_INPUTC1_RST = "RST0"; - parameter REG_OPCODEOP0_0_CLK = "NONE"; - parameter REG_OPCODEOP0_0_CE = "CE0"; - parameter REG_OPCODEOP0_0_RST = "RST0"; - parameter REG_OPCODEOP1_0_CLK = "NONE"; - parameter REG_OPCODEOP0_1_CLK = "NONE"; - parameter REG_OPCODEOP0_1_CE = "CE0"; - parameter REG_OPCODEOP0_1_RST = "RST0"; - parameter REG_OPCODEOP1_1_CLK = "NONE"; - parameter REG_OPCODEIN_0_CLK = "NONE"; - parameter REG_OPCODEIN_0_CE = "CE0"; - parameter REG_OPCODEIN_0_RST = "RST0"; - parameter REG_OPCODEIN_1_CLK = "NONE"; - parameter REG_OPCODEIN_1_CE = "CE0"; - parameter REG_OPCODEIN_1_RST = "RST0"; - parameter REG_OUTPUT0_CLK = "NONE"; - parameter REG_OUTPUT0_CE = "CE0"; - parameter REG_OUTPUT0_RST = "RST0"; - parameter REG_OUTPUT1_CLK = "NONE"; - parameter REG_OUTPUT1_CE = "CE0"; - parameter REG_OUTPUT1_RST = "RST0"; - parameter REG_FLAG_CLK = "NONE"; - parameter REG_FLAG_CE = "CE0"; - parameter REG_FLAG_RST = "RST0"; - parameter REG_INPUTCFB_CLK = "NONE"; - parameter REG_INPUTCFB_CE = "CE0"; - parameter REG_INPUTCFB_RST = "RST0"; - parameter [127:0] MCPAT_SOURCE = "STATIC"; - parameter [127:0] MASKPAT_SOURCE = "STATIC"; - parameter MASK01 = "0x00000000000000"; - parameter [127:0] CLK0_DIV = "ENABLED"; - parameter [127:0] CLK1_DIV = "ENABLED"; - parameter [127:0] CLK2_DIV = "ENABLED"; - parameter [127:0] CLK3_DIV = "ENABLED"; - parameter MCPAT = "0x00000000000000"; - parameter MASKPAT = "0x00000000000000"; - parameter RNDPAT = "0x00000000000000"; - parameter [127:0] GSR = "ENABLED"; - parameter [127:0] RESETMODE = "SYNC"; - parameter MULT9_MODE = "DISABLED"; - parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED"; - parameter LEGACY = "DISABLED"; +(* blackbox *) (* keep *) +module SGSR (...); + input GSR; + input CLK; endmodule (* blackbox *) -module EHXPLLL ( - input CLKI, CLKFB, - input PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, PHASELOADREG, - input STDBY, PLLWAKESYNC, - input RST, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, - output CLKOP, CLKOS, CLKOS2, CLKOS3, - output LOCK, INTLOCK, - output REFCLK, CLKINTFB -); - parameter CLKI_DIV = 1; - parameter CLKFB_DIV = 1; - parameter CLKOP_DIV = 8; - parameter CLKOS_DIV = 8; - parameter CLKOS2_DIV = 8; - parameter CLKOS3_DIV = 8; - parameter CLKOP_ENABLE = "ENABLED"; - parameter CLKOS_ENABLE = "DISABLED"; - parameter CLKOS2_ENABLE = "DISABLED"; - parameter CLKOS3_ENABLE = "DISABLED"; - parameter CLKOP_CPHASE = 0; - parameter CLKOS_CPHASE = 0; - parameter CLKOS2_CPHASE = 0; - parameter CLKOS3_CPHASE = 0; - parameter CLKOP_FPHASE = 0; - parameter CLKOS_FPHASE = 0; - parameter CLKOS2_FPHASE = 0; - parameter CLKOS3_FPHASE = 0; - parameter FEEDBK_PATH = "CLKOP"; - parameter CLKOP_TRIM_POL = "RISING"; - parameter CLKOP_TRIM_DELAY = 0; - parameter CLKOS_TRIM_POL = "RISING"; - parameter CLKOS_TRIM_DELAY = 0; - parameter OUTDIVIDER_MUXA = "DIVA"; - parameter OUTDIVIDER_MUXB = "DIVB"; - parameter OUTDIVIDER_MUXC = "DIVC"; - parameter OUTDIVIDER_MUXD = "DIVD"; - parameter PLL_LOCK_MODE = 0; - parameter PLL_LOCK_DELAY = 200; - parameter STDBY_ENABLE = "DISABLED"; - parameter REFIN_RESET = "DISABLED"; - parameter SYNC_ENABLE = "DISABLED"; - parameter INT_LOCK_STICKY = "ENABLED"; - parameter DPHASE_SOURCE = "DISABLED"; - parameter PLLRST_ENA = "DISABLED"; - parameter INTFB_WAKE = "DISABLED"; +module DP16KD (...); + parameter DATA_WIDTH_A = 18; + parameter DATA_WIDTH_B = 18; + parameter REGMODE_A = "NOREG"; + parameter REGMODE_B = "NOREG"; + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter WRITEMODE_A = "NORMAL"; + parameter WRITEMODE_B = "NORMAL"; + parameter CSDECODE_A = "0b000"; + parameter CSDECODE_B = "0b000"; + parameter GSR = "ENABLED"; + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_DATA = "STATIC"; + input DIA17; + input DIA16; + input DIA15; + input DIA14; + input DIA13; + input DIA12; + input DIA11; + input DIA10; + input DIA9; + input DIA8; + input DIA7; + input DIA6; + input DIA5; + input DIA4; + input DIA3; + input DIA2; + input DIA1; + input DIA0; + input ADA13; + input ADA12; + input ADA11; + input ADA10; + input ADA9; + input ADA8; + input ADA7; + input ADA6; + input ADA5; + input ADA4; + input ADA3; + input ADA2; + input ADA1; + input ADA0; + input CEA; + input OCEA; + input CLKA; + input WEA; + input CSA2; + input CSA1; + input CSA0; + input RSTA; + input DIB17; + input DIB16; + input DIB15; + input DIB14; + input DIB13; + input DIB12; + input DIB11; + input DIB10; + input DIB9; + input DIB8; + input DIB7; + input DIB6; + input DIB5; + input DIB4; + input DIB3; + input DIB2; + input DIB1; + input DIB0; + input ADB13; + input ADB12; + input ADB11; + input ADB10; + input ADB9; + input ADB8; + input ADB7; + input ADB6; + input ADB5; + input ADB4; + input ADB3; + input ADB2; + input ADB1; + input ADB0; + input CEB; + input OCEB; + input CLKB; + input WEB; + input CSB2; + input CSB1; + input CSB0; + input RSTB; + output DOA17; + output DOA16; + output DOA15; + output DOA14; + output DOA13; + output DOA12; + output DOA11; + output DOA10; + output DOA9; + output DOA8; + output DOA7; + output DOA6; + output DOA5; + output DOA4; + output DOA3; + output DOA2; + output DOA1; + output DOA0; + output DOB17; + output DOB16; + output DOB15; + output DOB14; + output DOB13; + output DOB12; + output DOB11; + output DOB10; + output DOB9; + output DOB8; + output DOB7; + output DOB6; + output DOB5; + output DOB4; + output DOB3; + output DOB2; + output DOB1; + output DOB0; endmodule (* blackbox *) -module DTR( - input STARTPULSE, - output DTROUT7, DTROUT6, DTROUT5, DTROUT4, DTROUT3, DTROUT2, DTROUT1, DTROUT0 -); +module PDPW16KD (...); + parameter DATA_WIDTH_W = 36; + parameter DATA_WIDTH_R = 36; + parameter GSR = "ENABLED"; + parameter REGMODE = "NOREG"; + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter CSDECODE_W = "0b000"; + parameter CSDECODE_R = "0b000"; + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_DATA = "STATIC"; + input DI35; + input DI34; + input DI33; + input DI32; + input DI31; + input DI30; + input DI29; + input DI28; + input DI27; + input DI26; + input DI25; + input DI24; + input DI23; + input DI22; + input DI21; + input DI20; + input DI19; + input DI18; + input DI17; + input DI16; + input DI15; + input DI14; + input DI13; + input DI12; + input DI11; + input DI10; + input DI9; + input DI8; + input DI7; + input DI6; + input DI5; + input DI4; + input DI3; + input DI2; + input DI1; + input DI0; + input ADW8; + input ADW7; + input ADW6; + input ADW5; + input ADW4; + input ADW3; + input ADW2; + input ADW1; + input ADW0; + input BE3; + input BE2; + input BE1; + input BE0; + input CEW; + input CLKW; + input CSW2; + input CSW1; + input CSW0; + input ADR13; + input ADR12; + input ADR11; + input ADR10; + input ADR9; + input ADR8; + input ADR7; + input ADR6; + input ADR5; + input ADR4; + input ADR3; + input ADR2; + input ADR1; + input ADR0; + input CER; + input OCER; + input CLKR; + input CSR2; + input CSR1; + input CSR0; + input RST; + output DO35; + output DO34; + output DO33; + output DO32; + output DO31; + output DO30; + output DO29; + output DO28; + output DO27; + output DO26; + output DO25; + output DO24; + output DO23; + output DO22; + output DO21; + output DO20; + output DO19; + output DO18; + output DO17; + output DO16; + output DO15; + output DO14; + output DO13; + output DO12; + output DO11; + output DO10; + output DO9; + output DO8; + output DO7; + output DO6; + output DO5; + output DO4; + output DO3; + output DO2; + output DO1; + output DO0; endmodule (* blackbox *) -module OSCG( - output OSC -); -parameter DIV = 128; +module MULT18X18D (...); + parameter REG_INPUTA_CLK = "NONE"; + parameter REG_INPUTA_CE = "CE0"; + parameter REG_INPUTA_RST = "RST0"; + parameter REG_INPUTB_CLK = "NONE"; + parameter REG_INPUTB_CE = "CE0"; + parameter REG_INPUTB_RST = "RST0"; + parameter REG_INPUTC_CLK = "NONE"; + parameter REG_INPUTC_CE = "CE0"; + parameter REG_INPUTC_RST = "RST0"; + parameter REG_PIPELINE_CLK = "NONE"; + parameter REG_PIPELINE_CE = "CE0"; + parameter REG_PIPELINE_RST = "RST0"; + parameter REG_OUTPUT_CLK = "NONE"; + parameter REG_OUTPUT_CE = "CE0"; + parameter REG_OUTPUT_RST = "RST0"; + parameter CLK0_DIV = "ENABLED"; + parameter CLK1_DIV = "ENABLED"; + parameter CLK2_DIV = "ENABLED"; + parameter CLK3_DIV = "ENABLED"; + parameter HIGHSPEED_CLK = "NONE"; + parameter GSR = "ENABLED"; + parameter CAS_MATCH_REG = "FALSE"; + parameter SOURCEB_MODE = "B_SHIFT"; + parameter MULT_BYPASS = "DISABLED"; + parameter RESETMODE = "SYNC"; + input A17; + input A16; + input A15; + input A14; + input A13; + input A12; + input A11; + input A10; + input A9; + input A8; + input A7; + input A6; + input A5; + input A4; + input A3; + input A2; + input A1; + input A0; + input B17; + input B16; + input B15; + input B14; + input B13; + input B12; + input B11; + input B10; + input B9; + input B8; + input B7; + input B6; + input B5; + input B4; + input B3; + input B2; + input B1; + input B0; + input C17; + input C16; + input C15; + input C14; + input C13; + input C12; + input C11; + input C10; + input C9; + input C8; + input C7; + input C6; + input C5; + input C4; + input C3; + input C2; + input C1; + input C0; + input SIGNEDA; + input SIGNEDB; + input SOURCEA; + input SOURCEB; + input CLK3; + input CLK2; + input CLK1; + input CLK0; + input CE3; + input CE2; + input CE1; + input CE0; + input RST3; + input RST2; + input RST1; + input RST0; + input SRIA17; + input SRIA16; + input SRIA15; + input SRIA14; + input SRIA13; + input SRIA12; + input SRIA11; + input SRIA10; + input SRIA9; + input SRIA8; + input SRIA7; + input SRIA6; + input SRIA5; + input SRIA4; + input SRIA3; + input SRIA2; + input SRIA1; + input SRIA0; + input SRIB17; + input SRIB16; + input SRIB15; + input SRIB14; + input SRIB13; + input SRIB12; + input SRIB11; + input SRIB10; + input SRIB9; + input SRIB8; + input SRIB7; + input SRIB6; + input SRIB5; + input SRIB4; + input SRIB3; + input SRIB2; + input SRIB1; + input SRIB0; + output SROA17; + output SROA16; + output SROA15; + output SROA14; + output SROA13; + output SROA12; + output SROA11; + output SROA10; + output SROA9; + output SROA8; + output SROA7; + output SROA6; + output SROA5; + output SROA4; + output SROA3; + output SROA2; + output SROA1; + output SROA0; + output SROB17; + output SROB16; + output SROB15; + output SROB14; + output SROB13; + output SROB12; + output SROB11; + output SROB10; + output SROB9; + output SROB8; + output SROB7; + output SROB6; + output SROB5; + output SROB4; + output SROB3; + output SROB2; + output SROB1; + output SROB0; + output ROA17; + output ROA16; + output ROA15; + output ROA14; + output ROA13; + output ROA12; + output ROA11; + output ROA10; + output ROA9; + output ROA8; + output ROA7; + output ROA6; + output ROA5; + output ROA4; + output ROA3; + output ROA2; + output ROA1; + output ROA0; + output ROB17; + output ROB16; + output ROB15; + output ROB14; + output ROB13; + output ROB12; + output ROB11; + output ROB10; + output ROB9; + output ROB8; + output ROB7; + output ROB6; + output ROB5; + output ROB4; + output ROB3; + output ROB2; + output ROB1; + output ROB0; + output ROC17; + output ROC16; + output ROC15; + output ROC14; + output ROC13; + output ROC12; + output ROC11; + output ROC10; + output ROC9; + output ROC8; + output ROC7; + output ROC6; + output ROC5; + output ROC4; + output ROC3; + output ROC2; + output ROC1; + output ROC0; + output P35; + output P34; + output P33; + output P32; + output P31; + output P30; + output P29; + output P28; + output P27; + output P26; + output P25; + output P24; + output P23; + output P22; + output P21; + output P20; + output P19; + output P18; + output P17; + output P16; + output P15; + output P14; + output P13; + output P12; + output P11; + output P10; + output P9; + output P8; + output P7; + output P6; + output P5; + output P4; + output P3; + output P2; + output P1; + output P0; + output SIGNEDP; endmodule -(* blackbox *) (* keep *) -module USRMCLK( - input USRMCLKI, USRMCLKTS, - output USRMCLKO -); +(* blackbox *) +module ALU54B (...); + parameter REG_INPUTC0_CLK = "NONE"; + parameter REG_INPUTC0_CE = "CE0"; + parameter REG_INPUTC0_RST = "RST0"; + parameter REG_INPUTC1_CLK = "NONE"; + parameter REG_INPUTC1_CE = "CE0"; + parameter REG_INPUTC1_RST = "RST0"; + parameter REG_OPCODEOP0_0_CLK = "NONE"; + parameter REG_OPCODEOP0_0_CE = "CE0"; + parameter REG_OPCODEOP0_0_RST = "RST0"; + parameter REG_OPCODEOP1_0_CLK = "NONE"; + parameter REG_OPCODEOP0_1_CLK = "NONE"; + parameter REG_OPCODEOP0_1_CE = "CE0"; + parameter REG_OPCODEOP0_1_RST = "RST0"; + parameter REG_OPCODEOP1_1_CLK = "NONE"; + parameter REG_OPCODEIN_0_CLK = "NONE"; + parameter REG_OPCODEIN_0_CE = "CE0"; + parameter REG_OPCODEIN_0_RST = "RST0"; + parameter REG_OPCODEIN_1_CLK = "NONE"; + parameter REG_OPCODEIN_1_CE = "CE0"; + parameter REG_OPCODEIN_1_RST = "RST0"; + parameter REG_OUTPUT0_CLK = "NONE"; + parameter REG_OUTPUT0_CE = "CE0"; + parameter REG_OUTPUT0_RST = "RST0"; + parameter REG_OUTPUT1_CLK = "NONE"; + parameter REG_OUTPUT1_CE = "CE0"; + parameter REG_OUTPUT1_RST = "RST0"; + parameter REG_FLAG_CLK = "NONE"; + parameter REG_FLAG_CE = "CE0"; + parameter REG_FLAG_RST = "RST0"; + parameter MCPAT_SOURCE = "STATIC"; + parameter MASKPAT_SOURCE = "STATIC"; + parameter MASK01 = "0x00000000000000"; + parameter REG_INPUTCFB_CLK = "NONE"; + parameter REG_INPUTCFB_CE = "CE0"; + parameter REG_INPUTCFB_RST = "RST0"; + parameter CLK0_DIV = "ENABLED"; + parameter CLK1_DIV = "ENABLED"; + parameter CLK2_DIV = "ENABLED"; + parameter CLK3_DIV = "ENABLED"; + parameter MCPAT = "0x00000000000000"; + parameter MASKPAT = "0x00000000000000"; + parameter RNDPAT = "0x00000000000000"; + parameter GSR = "ENABLED"; + parameter RESETMODE = "SYNC"; + parameter MULT9_MODE = "DISABLED"; + parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED"; + parameter LEGACY = "DISABLED"; + input CE3; + input CE2; + input CE1; + input CE0; + input CLK3; + input CLK2; + input CLK1; + input CLK0; + input RST3; + input RST2; + input RST1; + input RST0; + input SIGNEDIA; + input SIGNEDIB; + input SIGNEDCIN; + input A35; + input A34; + input A33; + input A32; + input A31; + input A30; + input A29; + input A28; + input A27; + input A26; + input A25; + input A24; + input A23; + input A22; + input A21; + input A20; + input A19; + input A18; + input A17; + input A16; + input A15; + input A14; + input A13; + input A12; + input A11; + input A10; + input A9; + input A8; + input A7; + input A6; + input A5; + input A4; + input A3; + input A2; + input A1; + input A0; + input B35; + input B34; + input B33; + input B32; + input B31; + input B30; + input B29; + input B28; + input B27; + input B26; + input B25; + input B24; + input B23; + input B22; + input B21; + input B20; + input B19; + input B18; + input B17; + input B16; + input B15; + input B14; + input B13; + input B12; + input B11; + input B10; + input B9; + input B8; + input B7; + input B6; + input B5; + input B4; + input B3; + input B2; + input B1; + input B0; + input C53; + input C52; + input C51; + input C50; + input C49; + input C48; + input C47; + input C46; + input C45; + input C44; + input C43; + input C42; + input C41; + input C40; + input C39; + input C38; + input C37; + input C36; + input C35; + input C34; + input C33; + input C32; + input C31; + input C30; + input C29; + input C28; + input C27; + input C26; + input C25; + input C24; + input C23; + input C22; + input C21; + input C20; + input C19; + input C18; + input C17; + input C16; + input C15; + input C14; + input C13; + input C12; + input C11; + input C10; + input C9; + input C8; + input C7; + input C6; + input C5; + input C4; + input C3; + input C2; + input C1; + input C0; + input CFB53; + input CFB52; + input CFB51; + input CFB50; + input CFB49; + input CFB48; + input CFB47; + input CFB46; + input CFB45; + input CFB44; + input CFB43; + input CFB42; + input CFB41; + input CFB40; + input CFB39; + input CFB38; + input CFB37; + input CFB36; + input CFB35; + input CFB34; + input CFB33; + input CFB32; + input CFB31; + input CFB30; + input CFB29; + input CFB28; + input CFB27; + input CFB26; + input CFB25; + input CFB24; + input CFB23; + input CFB22; + input CFB21; + input CFB20; + input CFB19; + input CFB18; + input CFB17; + input CFB16; + input CFB15; + input CFB14; + input CFB13; + input CFB12; + input CFB11; + input CFB10; + input CFB9; + input CFB8; + input CFB7; + input CFB6; + input CFB5; + input CFB4; + input CFB3; + input CFB2; + input CFB1; + input CFB0; + input MA35; + input MA34; + input MA33; + input MA32; + input MA31; + input MA30; + input MA29; + input MA28; + input MA27; + input MA26; + input MA25; + input MA24; + input MA23; + input MA22; + input MA21; + input MA20; + input MA19; + input MA18; + input MA17; + input MA16; + input MA15; + input MA14; + input MA13; + input MA12; + input MA11; + input MA10; + input MA9; + input MA8; + input MA7; + input MA6; + input MA5; + input MA4; + input MA3; + input MA2; + input MA1; + input MA0; + input MB35; + input MB34; + input MB33; + input MB32; + input MB31; + input MB30; + input MB29; + input MB28; + input MB27; + input MB26; + input MB25; + input MB24; + input MB23; + input MB22; + input MB21; + input MB20; + input MB19; + input MB18; + input MB17; + input MB16; + input MB15; + input MB14; + input MB13; + input MB12; + input MB11; + input MB10; + input MB9; + input MB8; + input MB7; + input MB6; + input MB5; + input MB4; + input MB3; + input MB2; + input MB1; + input MB0; + input CIN53; + input CIN52; + input CIN51; + input CIN50; + input CIN49; + input CIN48; + input CIN47; + input CIN46; + input CIN45; + input CIN44; + input CIN43; + input CIN42; + input CIN41; + input CIN40; + input CIN39; + input CIN38; + input CIN37; + input CIN36; + input CIN35; + input CIN34; + input CIN33; + input CIN32; + input CIN31; + input CIN30; + input CIN29; + input CIN28; + input CIN27; + input CIN26; + input CIN25; + input CIN24; + input CIN23; + input CIN22; + input CIN21; + input CIN20; + input CIN19; + input CIN18; + input CIN17; + input CIN16; + input CIN15; + input CIN14; + input CIN13; + input CIN12; + input CIN11; + input CIN10; + input CIN9; + input CIN8; + input CIN7; + input CIN6; + input CIN5; + input CIN4; + input CIN3; + input CIN2; + input CIN1; + input CIN0; + input OP10; + input OP9; + input OP8; + input OP7; + input OP6; + input OP5; + input OP4; + input OP3; + input OP2; + input OP1; + input OP0; + output R53; + output R52; + output R51; + output R50; + output R49; + output R48; + output R47; + output R46; + output R45; + output R44; + output R43; + output R42; + output R41; + output R40; + output R39; + output R38; + output R37; + output R36; + output R35; + output R34; + output R33; + output R32; + output R31; + output R30; + output R29; + output R28; + output R27; + output R26; + output R25; + output R24; + output R23; + output R22; + output R21; + output R20; + output R19; + output R18; + output R17; + output R16; + output R15; + output R14; + output R13; + output R12; + output R11; + output R10; + output R9; + output R8; + output R7; + output R6; + output R5; + output R4; + output R3; + output R2; + output R1; + output R0; + output CO53; + output CO52; + output CO51; + output CO50; + output CO49; + output CO48; + output CO47; + output CO46; + output CO45; + output CO44; + output CO43; + output CO42; + output CO41; + output CO40; + output CO39; + output CO38; + output CO37; + output CO36; + output CO35; + output CO34; + output CO33; + output CO32; + output CO31; + output CO30; + output CO29; + output CO28; + output CO27; + output CO26; + output CO25; + output CO24; + output CO23; + output CO22; + output CO21; + output CO20; + output CO19; + output CO18; + output CO17; + output CO16; + output CO15; + output CO14; + output CO13; + output CO12; + output CO11; + output CO10; + output CO9; + output CO8; + output CO7; + output CO6; + output CO5; + output CO4; + output CO3; + output CO2; + output CO1; + output CO0; + output EQZ; + output EQZM; + output EQOM; + output EQPAT; + output EQPATB; + output OVER; + output UNDER; + output OVERUNDER; + output SIGNEDR; endmodule -(* blackbox *) (* keep *) -module JTAGG( - (* iopad_external_pin *) - input TCK, - (* iopad_external_pin *) - input TMS, - (* iopad_external_pin *) - input TDI, - input JTDO2, JTDO1, - (* iopad_external_pin *) - output TDO, - output JTDI, JTCK, JRTI2, JRTI1, - output JSHIFT, JUPDATE, JRSTN, JCE2, JCE1 -); -parameter ER1 = "ENABLED"; -parameter ER2 = "ENABLED"; +(* blackbox *) +module CLKDIVF (...); + parameter GSR = "DISABLED"; + parameter DIV = "2.0"; + input CLKI; + input RST; + input ALIGNWD; + output CDIVX; endmodule (* blackbox *) -module DELAYF( - input A, LOADN, MOVE, DIRECTION, - output Z, CFLAG -); - parameter DEL_MODE = "USER_DEFINED"; - parameter DEL_VALUE = 0; +module PCSCLKDIV (...); + parameter GSR = "DISABLED"; + input CLKI; + input RST; + input SEL2; + input SEL1; + input SEL0; + output CDIV1; + output CDIVX; endmodule (* blackbox *) -module DELAYG( - input A, - output Z -); - parameter DEL_MODE = "USER_DEFINED"; - parameter DEL_VALUE = 0; +module DCSC (...); + parameter DCSMODE = "POS"; + input CLK1; + input CLK0; + input SEL1; + input SEL0; + input MODESEL; + output DCSOUT; endmodule (* blackbox *) -module IDDRX1F( - input D, SCLK, RST, - output Q0, Q1 -); - parameter GSR = "ENABLED"; +module DCCA (...); + input CLKI; + input CE; + output CLKO; endmodule (* blackbox *) -module IDDRX2F( - input D, SCLK, ECLK, RST, ALIGNWD, - output Q0, Q1, Q2, Q3 -); - parameter GSR = "ENABLED"; +module ECLKSYNCB (...); + input ECLKI; + input STOP; + output ECLKO; endmodule (* blackbox *) -module IDDR71B( - input D, SCLK, ECLK, RST, ALIGNWD, - output Q0, Q1, Q2, Q3, Q4, Q5, Q6 -); - parameter GSR = "ENABLED"; +module ECLKBRIDGECS (...); + input CLK0; + input CLK1; + input SEL; + output ECSOUT; endmodule (* blackbox *) -module IDDRX2DQA( - input D, DQSR90, ECLK, SCLK, RST, - input RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, - output Q0, Q1, Q2, Q3, QWL -); - parameter GSR = "ENABLED"; +module DELAYF (...); + parameter DEL_MODE = "USER_DEFINED"; + parameter DEL_VALUE = 0; + input A; + input LOADN; + input MOVE; + input DIRECTION; + output Z; + output CFLAG; endmodule (* blackbox *) -module ODDRX1F( - input SCLK, RST, D0, D1, - output Q -); - parameter GSR = "ENABLED"; +module DELAYG (...); + parameter DEL_MODE = "USER_DEFINED"; + parameter DEL_VALUE = 0; + input A; + output Z; endmodule -(* blackbox *) -module ODDRX2F( - input SCLK, ECLK, RST, D0, D1, D2, D3, - output Q -); - parameter GSR = "ENABLED"; +(* blackbox *) (* keep *) +module USRMCLK (...); + input USRMCLKI; + input USRMCLKTS; endmodule (* blackbox *) -module ODDR71B( - input SCLK, ECLK, RST, D0, D1, D2, D3, D4, D5, D6, - output Q -); - parameter GSR = "ENABLED"; +module DQSBUFM (...); + parameter DQS_LI_DEL_VAL = 4; + parameter DQS_LI_DEL_ADJ = "FACTORYONLY"; + parameter DQS_LO_DEL_VAL = 0; + parameter DQS_LO_DEL_ADJ = "FACTORYONLY"; + parameter GSR = "ENABLED"; + input DQSI; + input READ1; + input READ0; + input READCLKSEL2; + input READCLKSEL1; + input READCLKSEL0; + input DDRDEL; + input ECLK; + input SCLK; + input RST; + input DYNDELAY7; + input DYNDELAY6; + input DYNDELAY5; + input DYNDELAY4; + input DYNDELAY3; + input DYNDELAY2; + input DYNDELAY1; + input DYNDELAY0; + input PAUSE; + input RDLOADN; + input RDMOVE; + input RDDIRECTION; + input WRLOADN; + input WRMOVE; + input WRDIRECTION; + output DQSR90; + output DQSW; + output DQSW270; + output RDPNTR2; + output RDPNTR1; + output RDPNTR0; + output WRPNTR2; + output WRPNTR1; + output WRPNTR0; + output DATAVALID; + output BURSTDET; + output RDCFLAG; + output WRCFLAG; endmodule (* blackbox *) -module OSHX2A( - input D0, D1, RST, ECLK, SCLK, - output Q -); - parameter GSR = "ENABLED"; +module DDRDLLA (...); + parameter FORCE_MAX_DELAY = "NO"; + parameter GSR = "ENABLED"; + input CLK; + input RST; + input UDDCNTLN; + input FREEZE; + output DDRDEL; + output LOCK; + output DCNTL7; + output DCNTL6; + output DCNTL5; + output DCNTL4; + output DCNTL3; + output DCNTL2; + output DCNTL1; + output DCNTL0; endmodule (* blackbox *) -module ODDRX2DQA( - input D0, D1, D2, D3, RST, ECLK, SCLK, DQSW270, - output Q -); - parameter GSR = "ENABLED"; +module DLLDELD (...); + input A; + input DDRDEL; + input LOADN; + input MOVE; + input DIRECTION; + output Z; + output CFLAG; endmodule (* blackbox *) -module ODDRX2DQSB( - input D0, D1, D2, D3, RST, ECLK, SCLK, DQSW, - output Q -); - parameter GSR = "ENABLED"; +module IDDRX1F (...); + parameter GSR = "ENABLED"; + input D; + input SCLK; + input RST; + output Q0; + output Q1; endmodule (* blackbox *) -module TSHX2DQA( - input T0, T1, SCLK, ECLK, DQSW270, RST, - output Q -); - parameter GSR = "ENABLED"; - parameter REGSET = "SET"; +module IDDRX2F (...); + parameter GSR = "ENABLED"; + input D; + input SCLK; + input ECLK; + input RST; + input ALIGNWD; + output Q3; + output Q2; + output Q1; + output Q0; endmodule (* blackbox *) -module TSHX2DQSA( - input T0, T1, SCLK, ECLK, DQSW, RST, - output Q -); - parameter GSR = "ENABLED"; - parameter REGSET = "SET"; +module IDDR71B (...); + parameter GSR = "ENABLED"; + input D; + input SCLK; + input ECLK; + input RST; + input ALIGNWD; + output Q6; + output Q5; + output Q4; + output Q3; + output Q2; + output Q1; + output Q0; endmodule (* blackbox *) -module DQSBUFM( - input DQSI, READ1, READ0, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL, - input ECLK, SCLK, - input DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4, - input DYNDELAY3, DYNDELAY2, DYNDELAY1, DYNDELAY0, - input RST, RDLOADN, RDMOVE, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, PAUSE, - output DQSR90, DQSW, DQSW270, - output RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, - output DATAVALID, BURSTDET, RDCFLAG, WRCFLAG -); - parameter DQS_LI_DEL_ADJ = "FACTORYONLY"; - parameter DQS_LI_DEL_VAL = 0; - parameter DQS_LO_DEL_ADJ = "FACTORYONLY"; - parameter DQS_LO_DEL_VAL = 0; - parameter GSR = "ENABLED"; +module IDDRX2DQA (...); + parameter GSR = "ENABLED"; + input SCLK; + input ECLK; + input DQSR90; + input D; + input RST; + input RDPNTR2; + input RDPNTR1; + input RDPNTR0; + input WRPNTR2; + input WRPNTR1; + input WRPNTR0; + output Q3; + output Q2; + output Q1; + output Q0; + output QWL; endmodule (* blackbox *) -module DDRDLLA( - input CLK, RST, UDDCNTLN, FREEZE, - output LOCK, DDRDEL, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1, DCNTL0 -); - parameter FORCE_MAX_DELAY = "NO"; - parameter GSR = "ENABLED"; +module ODDRX1F (...); + parameter GSR = "ENABLED"; + input SCLK; + input RST; + input D0; + input D1; + output Q; endmodule (* blackbox *) -module DLLDELD( - input A, DDRDEL, LOADN, MOVE, DIRECTION, - output Z, CFLAG -); - parameter DEL_ADJ = "PLUS"; - parameter DEL_VAL = 0; +module ODDRX2F (...); + parameter GSR = "ENABLED"; + input SCLK; + input ECLK; + input RST; + input D3; + input D2; + input D1; + input D0; + output Q; endmodule (* blackbox *) -module CLKDIVF( - input CLKI, RST, ALIGNWD, - output CDIVX -); - parameter GSR = "DISABLED"; - parameter DIV = "2.0"; +module ODDR71B (...); + parameter GSR = "ENABLED"; + input SCLK; + input ECLK; + input RST; + input D6; + input D5; + input D4; + input D3; + input D2; + input D1; + input D0; + output Q; endmodule (* blackbox *) -module ECLKSYNCB( - input ECLKI, STOP, - output ECLKO -); +module OSHX2A (...); + parameter GSR = "ENABLED"; + input D1; + input D0; + input SCLK; + input ECLK; + input RST; + output Q; endmodule (* blackbox *) -module ECLKBRIDGECS( - input CLK0, CLK1, SEL, - output ECSOUT -); +module TSHX2DQA (...); + parameter GSR = "ENABLED"; + parameter REGSET = "SET"; + input T1; + input T0; + input SCLK; + input ECLK; + input DQSW270; + input RST; + output Q; endmodule (* blackbox *) -module DCCA( - input CLKI, CE, - output CLKO -); +module TSHX2DQSA (...); + parameter GSR = "ENABLED"; + parameter REGSET = "SET"; + input T1; + input T0; + input SCLK; + input ECLK; + input DQSW; + input RST; + output Q; endmodule (* blackbox *) -module DCSC( - input CLK1, CLK0, - input SEL1, SEL0, - input MODESEL, - output DCSOUT -); - parameter DCSMODE = "POS"; +module ODDRX2DQA (...); + parameter GSR = "ENABLED"; + input D3; + input D2; + input D1; + input D0; + input DQSW270; + input SCLK; + input ECLK; + input RST; + output Q; endmodule -(* blackbox *) (* keep *) -module DCUA( - (* iopad_external_pin *) - input CH0_HDINP, - (* iopad_external_pin *) - input CH1_HDINP, - (* iopad_external_pin *) - input CH0_HDINN, - (* iopad_external_pin *) - input CH1_HDINN, - input D_TXBIT_CLKP_FROM_ND, D_TXBIT_CLKN_FROM_ND, D_SYNC_ND, D_TXPLL_LOL_FROM_ND, - input CH0_RX_REFCLK, CH1_RX_REFCLK, CH0_FF_RXI_CLK, CH1_FF_RXI_CLK, CH0_FF_TXI_CLK, CH1_FF_TXI_CLK, CH0_FF_EBRD_CLK, CH1_FF_EBRD_CLK, - input CH0_FF_TX_D_0, CH1_FF_TX_D_0, CH0_FF_TX_D_1, CH1_FF_TX_D_1, CH0_FF_TX_D_2, CH1_FF_TX_D_2, CH0_FF_TX_D_3, CH1_FF_TX_D_3, - input CH0_FF_TX_D_4, CH1_FF_TX_D_4, CH0_FF_TX_D_5, CH1_FF_TX_D_5, CH0_FF_TX_D_6, CH1_FF_TX_D_6, CH0_FF_TX_D_7, CH1_FF_TX_D_7, - input CH0_FF_TX_D_8, CH1_FF_TX_D_8, CH0_FF_TX_D_9, CH1_FF_TX_D_9, CH0_FF_TX_D_10, CH1_FF_TX_D_10, CH0_FF_TX_D_11, CH1_FF_TX_D_11, - input CH0_FF_TX_D_12, CH1_FF_TX_D_12, CH0_FF_TX_D_13, CH1_FF_TX_D_13, CH0_FF_TX_D_14, CH1_FF_TX_D_14, CH0_FF_TX_D_15, CH1_FF_TX_D_15, - input CH0_FF_TX_D_16, CH1_FF_TX_D_16, CH0_FF_TX_D_17, CH1_FF_TX_D_17, CH0_FF_TX_D_18, CH1_FF_TX_D_18, CH0_FF_TX_D_19, CH1_FF_TX_D_19, - input CH0_FF_TX_D_20, CH1_FF_TX_D_20, CH0_FF_TX_D_21, CH1_FF_TX_D_21, CH0_FF_TX_D_22, CH1_FF_TX_D_22, CH0_FF_TX_D_23, CH1_FF_TX_D_23, - input CH0_FFC_EI_EN, CH1_FFC_EI_EN, CH0_FFC_PCIE_DET_EN, CH1_FFC_PCIE_DET_EN, CH0_FFC_PCIE_CT, CH1_FFC_PCIE_CT, CH0_FFC_SB_INV_RX, CH1_FFC_SB_INV_RX, - input CH0_FFC_ENABLE_CGALIGN, CH1_FFC_ENABLE_CGALIGN, CH0_FFC_SIGNAL_DETECT, CH1_FFC_SIGNAL_DETECT, CH0_FFC_FB_LOOPBACK, CH1_FFC_FB_LOOPBACK, CH0_FFC_SB_PFIFO_LP, CH1_FFC_SB_PFIFO_LP, - input CH0_FFC_PFIFO_CLR, CH1_FFC_PFIFO_CLR, CH0_FFC_RATE_MODE_RX, CH1_FFC_RATE_MODE_RX, CH0_FFC_RATE_MODE_TX, CH1_FFC_RATE_MODE_TX, CH0_FFC_DIV11_MODE_RX, CH1_FFC_DIV11_MODE_RX, CH0_FFC_RX_GEAR_MODE, CH1_FFC_RX_GEAR_MODE, CH0_FFC_TX_GEAR_MODE, CH1_FFC_TX_GEAR_MODE, - input CH0_FFC_DIV11_MODE_TX, CH1_FFC_DIV11_MODE_TX, CH0_FFC_LDR_CORE2TX_EN, CH1_FFC_LDR_CORE2TX_EN, CH0_FFC_LANE_TX_RST, CH1_FFC_LANE_TX_RST, CH0_FFC_LANE_RX_RST, CH1_FFC_LANE_RX_RST, - input CH0_FFC_RRST, CH1_FFC_RRST, CH0_FFC_TXPWDNB, CH1_FFC_TXPWDNB, CH0_FFC_RXPWDNB, CH1_FFC_RXPWDNB, CH0_LDR_CORE2TX, CH1_LDR_CORE2TX, - input D_SCIWDATA0, D_SCIWDATA1, D_SCIWDATA2, D_SCIWDATA3, D_SCIWDATA4, D_SCIWDATA5, D_SCIWDATA6, D_SCIWDATA7, - input D_SCIADDR0, D_SCIADDR1, D_SCIADDR2, D_SCIADDR3, D_SCIADDR4, D_SCIADDR5, D_SCIENAUX, D_SCISELAUX, - input CH0_SCIEN, CH1_SCIEN, CH0_SCISEL, CH1_SCISEL, D_SCIRD, D_SCIWSTN, D_CYAWSTN, D_FFC_SYNC_TOGGLE, - input D_FFC_DUAL_RST, D_FFC_MACRO_RST, D_FFC_MACROPDB, D_FFC_TRST, CH0_FFC_CDR_EN_BITSLIP, CH1_FFC_CDR_EN_BITSLIP, D_SCAN_ENABLE, D_SCAN_IN_0, - input D_SCAN_IN_1, D_SCAN_IN_2, D_SCAN_IN_3, D_SCAN_IN_4, D_SCAN_IN_5, D_SCAN_IN_6, D_SCAN_IN_7, D_SCAN_MODE, - input D_SCAN_RESET, D_CIN0, D_CIN1, D_CIN2, D_CIN3, D_CIN4, D_CIN5, D_CIN6,D_CIN7, D_CIN8, D_CIN9, D_CIN10, D_CIN11, - output CH0_HDOUTP, CH1_HDOUTP, CH0_HDOUTN, CH1_HDOUTN, D_TXBIT_CLKP_TO_ND, D_TXBIT_CLKN_TO_ND, D_SYNC_PULSE2ND, D_TXPLL_LOL_TO_ND, - output CH0_FF_RX_F_CLK, CH1_FF_RX_F_CLK, CH0_FF_RX_H_CLK, CH1_FF_RX_H_CLK, CH0_FF_TX_F_CLK, CH1_FF_TX_F_CLK, CH0_FF_TX_H_CLK, CH1_FF_TX_H_CLK, - output CH0_FF_RX_PCLK, CH1_FF_RX_PCLK, CH0_FF_TX_PCLK, CH1_FF_TX_PCLK, CH0_FF_RX_D_0, CH1_FF_RX_D_0, CH0_FF_RX_D_1, CH1_FF_RX_D_1, - output CH0_FF_RX_D_2, CH1_FF_RX_D_2, CH0_FF_RX_D_3, CH1_FF_RX_D_3, CH0_FF_RX_D_4, CH1_FF_RX_D_4, CH0_FF_RX_D_5, CH1_FF_RX_D_5, - output CH0_FF_RX_D_6, CH1_FF_RX_D_6, CH0_FF_RX_D_7, CH1_FF_RX_D_7, CH0_FF_RX_D_8, CH1_FF_RX_D_8, CH0_FF_RX_D_9, CH1_FF_RX_D_9, - output CH0_FF_RX_D_10, CH1_FF_RX_D_10, CH0_FF_RX_D_11, CH1_FF_RX_D_11, CH0_FF_RX_D_12, CH1_FF_RX_D_12, CH0_FF_RX_D_13, CH1_FF_RX_D_13, - output CH0_FF_RX_D_14, CH1_FF_RX_D_14, CH0_FF_RX_D_15, CH1_FF_RX_D_15, CH0_FF_RX_D_16, CH1_FF_RX_D_16, CH0_FF_RX_D_17, CH1_FF_RX_D_17, - output CH0_FF_RX_D_18, CH1_FF_RX_D_18, CH0_FF_RX_D_19, CH1_FF_RX_D_19, CH0_FF_RX_D_20, CH1_FF_RX_D_20, CH0_FF_RX_D_21, CH1_FF_RX_D_21, - output CH0_FF_RX_D_22, CH1_FF_RX_D_22, CH0_FF_RX_D_23, CH1_FF_RX_D_23, CH0_FFS_PCIE_DONE, CH1_FFS_PCIE_DONE, CH0_FFS_PCIE_CON, CH1_FFS_PCIE_CON, - output CH0_FFS_RLOS, CH1_FFS_RLOS, CH0_FFS_LS_SYNC_STATUS, CH1_FFS_LS_SYNC_STATUS, CH0_FFS_CC_UNDERRUN, CH1_FFS_CC_UNDERRUN, CH0_FFS_CC_OVERRUN, CH1_FFS_CC_OVERRUN, - output CH0_FFS_RXFBFIFO_ERROR, CH1_FFS_RXFBFIFO_ERROR, CH0_FFS_TXFBFIFO_ERROR, CH1_FFS_TXFBFIFO_ERROR, CH0_FFS_RLOL, CH1_FFS_RLOL, CH0_FFS_SKP_ADDED, CH1_FFS_SKP_ADDED, - output CH0_FFS_SKP_DELETED, CH1_FFS_SKP_DELETED, CH0_LDR_RX2CORE, CH1_LDR_RX2CORE, D_SCIRDATA0, D_SCIRDATA1, D_SCIRDATA2, D_SCIRDATA3, - output D_SCIRDATA4, D_SCIRDATA5, D_SCIRDATA6, D_SCIRDATA7, D_SCIINT, D_SCAN_OUT_0, D_SCAN_OUT_1, D_SCAN_OUT_2, D_SCAN_OUT_3, D_SCAN_OUT_4, D_SCAN_OUT_5, D_SCAN_OUT_6, D_SCAN_OUT_7, - output D_COUT0, D_COUT1, D_COUT2, D_COUT3, D_COUT4, D_COUT5, D_COUT6, D_COUT7, D_COUT8, D_COUT9, D_COUT10, D_COUT11, D_COUT12, D_COUT13, D_COUT14, D_COUT15, D_COUT16, D_COUT17, D_COUT18, D_COUT19, - - input D_REFCLKI, - output D_FFS_PLOL -); - parameter CH0_AUTO_CALIB_EN = "0b0"; - parameter CH0_AUTO_FACQ_EN = "0b0"; - parameter CH0_BAND_THRESHOLD = "0b000000"; - parameter CH0_CALIB_CK_MODE = "0b0"; - parameter CH0_CC_MATCH_1 = "0b0000000000"; - parameter CH0_CC_MATCH_2 = "0b0000000000"; - parameter CH0_CC_MATCH_3 = "0b0000000000"; - parameter CH0_CC_MATCH_4 = "0b0000000000"; - parameter CH0_CDR_CNT4SEL = "0b00"; - parameter CH0_CDR_CNT8SEL = "0b00"; - parameter CH0_CTC_BYPASS = "0b0"; - parameter CH0_DCOATDCFG = "0b00"; - parameter CH0_DCOATDDLY = "0b00"; - parameter CH0_DCOBYPSATD = "0b0"; - parameter CH0_DCOCALDIV = "0b000"; - parameter CH0_DCOCTLGI = "0b000"; - parameter CH0_DCODISBDAVOID = "0b0"; - parameter CH0_DCOFLTDAC = "0b00"; - parameter CH0_DCOFTNRG = "0b000"; - parameter CH0_DCOIOSTUNE = "0b000"; - parameter CH0_DCOITUNE = "0b00"; - parameter CH0_DCOITUNE4LSB = "0b000"; - parameter CH0_DCOIUPDNX2 = "0b0"; - parameter CH0_DCONUOFLSB = "0b000"; - parameter CH0_DCOSCALEI = "0b00"; - parameter CH0_DCOSTARTVAL = "0b000"; - parameter CH0_DCOSTEP = "0b00"; - parameter CH0_DEC_BYPASS = "0b0"; - parameter CH0_ENABLE_CG_ALIGN = "0b0"; - parameter CH0_ENC_BYPASS = "0b0"; - parameter CH0_FF_RX_F_CLK_DIS = "0b0"; - parameter CH0_FF_RX_H_CLK_EN = "0b0"; - parameter CH0_FF_TX_F_CLK_DIS = "0b0"; - parameter CH0_FF_TX_H_CLK_EN = "0b0"; - parameter CH0_GE_AN_ENABLE = "0b0"; - parameter CH0_INVERT_RX = "0b0"; - parameter CH0_INVERT_TX = "0b0"; - parameter CH0_LDR_CORE2TX_SEL = "0b0"; - parameter CH0_LDR_RX2CORE_SEL = "0b0"; - parameter CH0_LEQ_OFFSET_SEL = "0b0"; - parameter CH0_LEQ_OFFSET_TRIM = "0b000"; - parameter CH0_LSM_DISABLE = "0b0"; - parameter CH0_MATCH_2_ENABLE = "0b0"; - parameter CH0_MATCH_4_ENABLE = "0b0"; - parameter CH0_MIN_IPG_CNT = "0b00"; - parameter CH0_PCIE_EI_EN = "0b0"; - parameter CH0_PCIE_MODE = "0b0"; - parameter CH0_PCS_DET_TIME_SEL = "0b00"; - parameter CH0_PDEN_SEL = "0b0"; - parameter CH0_PRBS_ENABLE = "0b0"; - parameter CH0_PRBS_LOCK = "0b0"; - parameter CH0_PRBS_SELECTION = "0b0"; - parameter CH0_RATE_MODE_RX = "0b0"; - parameter CH0_RATE_MODE_TX = "0b0"; - parameter CH0_RCV_DCC_EN = "0b0"; - parameter CH0_REG_BAND_OFFSET = "0b0000"; - parameter CH0_REG_BAND_SEL = "0b000000"; - parameter CH0_REG_IDAC_EN = "0b0"; - parameter CH0_REG_IDAC_SEL = "0b0000000000"; - parameter CH0_REQ_EN = "0b0"; - parameter CH0_REQ_LVL_SET = "0b00"; - parameter CH0_RIO_MODE = "0b0"; - parameter CH0_RLOS_SEL = "0b0"; - parameter CH0_RPWDNB = "0b0"; - parameter CH0_RTERM_RX = "0b00000"; - parameter CH0_RTERM_TX = "0b00000"; - parameter CH0_RXIN_CM = "0b00"; - parameter CH0_RXTERM_CM = "0b00"; - parameter CH0_RX_DCO_CK_DIV = "0b000"; - parameter CH0_RX_DIV11_SEL = "0b0"; - parameter CH0_RX_GEAR_BYPASS = "0b0"; - parameter CH0_RX_GEAR_MODE = "0b0"; - parameter CH0_RX_LOS_CEQ = "0b00"; - parameter CH0_RX_LOS_EN = "0b0"; - parameter CH0_RX_LOS_HYST_EN = "0b0"; - parameter CH0_RX_LOS_LVL = "0b000"; - parameter CH0_RX_RATE_SEL = "0b0000"; - parameter CH0_RX_SB_BYPASS = "0b0"; - parameter CH0_SB_BYPASS = "0b0"; - parameter CH0_SEL_SD_RX_CLK = "0b0"; - parameter CH0_TDRV_DAT_SEL = "0b00"; - parameter CH0_TDRV_POST_EN = "0b0"; - parameter CH0_TDRV_PRE_EN = "0b0"; - parameter CH0_TDRV_SLICE0_CUR = "0b000"; - parameter CH0_TDRV_SLICE0_SEL = "0b00"; - parameter CH0_TDRV_SLICE1_CUR = "0b000"; - parameter CH0_TDRV_SLICE1_SEL = "0b00"; - parameter CH0_TDRV_SLICE2_CUR = "0b00"; - parameter CH0_TDRV_SLICE2_SEL = "0b00"; - parameter CH0_TDRV_SLICE3_CUR = "0b00"; - parameter CH0_TDRV_SLICE3_SEL = "0b00"; - parameter CH0_TDRV_SLICE4_CUR = "0b00"; - parameter CH0_TDRV_SLICE4_SEL = "0b00"; - parameter CH0_TDRV_SLICE5_CUR = "0b00"; - parameter CH0_TDRV_SLICE5_SEL = "0b00"; - parameter CH0_TPWDNB = "0b0"; - parameter CH0_TX_CM_SEL = "0b00"; - parameter CH0_TX_DIV11_SEL = "0b0"; - parameter CH0_TX_GEAR_BYPASS = "0b0"; - parameter CH0_TX_GEAR_MODE = "0b0"; - parameter CH0_TX_POST_SIGN = "0b0"; - parameter CH0_TX_PRE_SIGN = "0b0"; - parameter CH0_UC_MODE = "0b0"; - parameter CH0_UDF_COMMA_A = "0b0000000000"; - parameter CH0_UDF_COMMA_B = "0b0000000000"; - parameter CH0_UDF_COMMA_MASK = "0b0000000000"; - parameter CH0_WA_BYPASS = "0b0"; - parameter CH0_WA_MODE = "0b0"; - parameter CH1_AUTO_CALIB_EN = "0b0"; - parameter CH1_AUTO_FACQ_EN = "0b0"; - parameter CH1_BAND_THRESHOLD = "0b000000"; - parameter CH1_CALIB_CK_MODE = "0b0"; - parameter CH1_CC_MATCH_1 = "0b0000000000"; - parameter CH1_CC_MATCH_2 = "0b0000000000"; - parameter CH1_CC_MATCH_3 = "0b0000000000"; - parameter CH1_CC_MATCH_4 = "0b0000000000"; - parameter CH1_CDR_CNT4SEL = "0b00"; - parameter CH1_CDR_CNT8SEL = "0b00"; - parameter CH1_CTC_BYPASS = "0b0"; - parameter CH1_DCOATDCFG = "0b00"; - parameter CH1_DCOATDDLY = "0b00"; - parameter CH1_DCOBYPSATD = "0b0"; - parameter CH1_DCOCALDIV = "0b000"; - parameter CH1_DCOCTLGI = "0b000"; - parameter CH1_DCODISBDAVOID = "0b0"; - parameter CH1_DCOFLTDAC = "0b00"; - parameter CH1_DCOFTNRG = "0b000"; - parameter CH1_DCOIOSTUNE = "0b000"; - parameter CH1_DCOITUNE = "0b00"; - parameter CH1_DCOITUNE4LSB = "0b000"; - parameter CH1_DCOIUPDNX2 = "0b0"; - parameter CH1_DCONUOFLSB = "0b000"; - parameter CH1_DCOSCALEI = "0b00"; - parameter CH1_DCOSTARTVAL = "0b000"; - parameter CH1_DCOSTEP = "0b00"; - parameter CH1_DEC_BYPASS = "0b0"; - parameter CH1_ENABLE_CG_ALIGN = "0b0"; - parameter CH1_ENC_BYPASS = "0b0"; - parameter CH1_FF_RX_F_CLK_DIS = "0b0"; - parameter CH1_FF_RX_H_CLK_EN = "0b0"; - parameter CH1_FF_TX_F_CLK_DIS = "0b0"; - parameter CH1_FF_TX_H_CLK_EN = "0b0"; - parameter CH1_GE_AN_ENABLE = "0b0"; - parameter CH1_INVERT_RX = "0b0"; - parameter CH1_INVERT_TX = "0b0"; - parameter CH1_LDR_CORE2TX_SEL = "0b0"; - parameter CH1_LDR_RX2CORE_SEL = "0b0"; - parameter CH1_LEQ_OFFSET_SEL = "0b0"; - parameter CH1_LEQ_OFFSET_TRIM = "0b000"; - parameter CH1_LSM_DISABLE = "0b0"; - parameter CH1_MATCH_2_ENABLE = "0b0"; - parameter CH1_MATCH_4_ENABLE = "0b0"; - parameter CH1_MIN_IPG_CNT = "0b00"; - parameter CH1_PCIE_EI_EN = "0b0"; - parameter CH1_PCIE_MODE = "0b0"; - parameter CH1_PCS_DET_TIME_SEL = "0b00"; - parameter CH1_PDEN_SEL = "0b0"; - parameter CH1_PRBS_ENABLE = "0b0"; - parameter CH1_PRBS_LOCK = "0b0"; - parameter CH1_PRBS_SELECTION = "0b0"; - parameter CH1_RATE_MODE_RX = "0b0"; - parameter CH1_RATE_MODE_TX = "0b0"; - parameter CH1_RCV_DCC_EN = "0b0"; - parameter CH1_REG_BAND_OFFSET = "0b0000"; - parameter CH1_REG_BAND_SEL = "0b000000"; - parameter CH1_REG_IDAC_EN = "0b0"; - parameter CH1_REG_IDAC_SEL = "0b0000000000"; - parameter CH1_REQ_EN = "0b0"; - parameter CH1_REQ_LVL_SET = "0b00"; - parameter CH1_RIO_MODE = "0b0"; - parameter CH1_RLOS_SEL = "0b0"; - parameter CH1_RPWDNB = "0b0"; - parameter CH1_RTERM_RX = "0b00000"; - parameter CH1_RTERM_TX = "0b00000"; - parameter CH1_RXIN_CM = "0b00"; - parameter CH1_RXTERM_CM = "0b00"; - parameter CH1_RX_DCO_CK_DIV = "0b000"; - parameter CH1_RX_DIV11_SEL = "0b0"; - parameter CH1_RX_GEAR_BYPASS = "0b0"; - parameter CH1_RX_GEAR_MODE = "0b0"; - parameter CH1_RX_LOS_CEQ = "0b00"; - parameter CH1_RX_LOS_EN = "0b0"; - parameter CH1_RX_LOS_HYST_EN = "0b0"; - parameter CH1_RX_LOS_LVL = "0b000"; - parameter CH1_RX_RATE_SEL = "0b0000"; - parameter CH1_RX_SB_BYPASS = "0b0"; - parameter CH1_SB_BYPASS = "0b0"; - parameter CH1_SEL_SD_RX_CLK = "0b0"; - parameter CH1_TDRV_DAT_SEL = "0b00"; - parameter CH1_TDRV_POST_EN = "0b0"; - parameter CH1_TDRV_PRE_EN = "0b0"; - parameter CH1_TDRV_SLICE0_CUR = "0b000"; - parameter CH1_TDRV_SLICE0_SEL = "0b00"; - parameter CH1_TDRV_SLICE1_CUR = "0b000"; - parameter CH1_TDRV_SLICE1_SEL = "0b00"; - parameter CH1_TDRV_SLICE2_CUR = "0b00"; - parameter CH1_TDRV_SLICE2_SEL = "0b00"; - parameter CH1_TDRV_SLICE3_CUR = "0b00"; - parameter CH1_TDRV_SLICE3_SEL = "0b00"; - parameter CH1_TDRV_SLICE4_CUR = "0b00"; - parameter CH1_TDRV_SLICE4_SEL = "0b00"; - parameter CH1_TDRV_SLICE5_CUR = "0b00"; - parameter CH1_TDRV_SLICE5_SEL = "0b00"; - parameter CH1_TPWDNB = "0b0"; - parameter CH1_TX_CM_SEL = "0b00"; - parameter CH1_TX_DIV11_SEL = "0b0"; - parameter CH1_TX_GEAR_BYPASS = "0b0"; - parameter CH1_TX_GEAR_MODE = "0b0"; - parameter CH1_TX_POST_SIGN = "0b0"; - parameter CH1_TX_PRE_SIGN = "0b0"; - parameter CH1_UC_MODE = "0b0"; - parameter CH1_UDF_COMMA_A = "0b0000000000"; - parameter CH1_UDF_COMMA_B = "0b0000000000"; - parameter CH1_UDF_COMMA_MASK = "0b0000000000"; - parameter CH1_WA_BYPASS = "0b0"; - parameter CH1_WA_MODE = "0b0"; - parameter D_BITCLK_FROM_ND_EN = "0b0"; - parameter D_BITCLK_LOCAL_EN = "0b0"; - parameter D_BITCLK_ND_EN = "0b0"; - parameter D_BUS8BIT_SEL = "0b0"; - parameter D_CDR_LOL_SET = "0b00"; - parameter D_CMUSETBIASI = "0b00"; - parameter D_CMUSETI4CPP = "0b0000"; - parameter D_CMUSETI4CPZ = "0b0000"; - parameter D_CMUSETI4VCO = "0b00"; - parameter D_CMUSETICP4P = "0b00"; - parameter D_CMUSETICP4Z = "0b000"; - parameter D_CMUSETINITVCT = "0b00"; - parameter D_CMUSETISCL4VCO = "0b000"; - parameter D_CMUSETP1GM = "0b000"; - parameter D_CMUSETP2AGM = "0b000"; - parameter D_CMUSETZGM = "0b000"; - parameter D_DCO_CALIB_TIME_SEL = "0b00"; - parameter D_HIGH_MARK = "0b0000"; - parameter D_IB_PWDNB = "0b0"; - parameter D_ISETLOS = "0b00000000"; - parameter D_LOW_MARK = "0b0000"; - parameter D_MACROPDB = "0b0"; - parameter D_PD_ISET = "0b00"; - parameter D_PLL_LOL_SET = "0b00"; - parameter D_REFCK_MODE = "0b000"; - parameter D_REQ_ISET = "0b000"; - parameter D_RG_EN = "0b0"; - parameter D_RG_SET = "0b00"; - parameter D_SETICONST_AUX = "0b00"; - parameter D_SETICONST_CH = "0b00"; - parameter D_SETIRPOLY_AUX = "0b00"; - parameter D_SETIRPOLY_CH = "0b00"; - parameter D_SETPLLRC = "0b000000"; - parameter D_SYNC_LOCAL_EN = "0b0"; - parameter D_SYNC_ND_EN = "0b0"; - parameter D_TXPLL_PWDNB = "0b0"; - parameter D_TX_VCO_CK_DIV = "0b000"; - parameter D_XGE_MODE = "0b0"; - -// These parameters don't do anything but are -// needed for compatibility with Diamond - parameter D_TX_MAX_RATE = "2.5"; - parameter D_RX_MAX_RATE = "2.5"; - parameter CH0_TXAMPLITUDE = "0d1300"; - parameter CH1_TXAMPLITUDE = "0d1300"; - parameter CH0_PROTOCOL = "8B10B"; - parameter CH1_PROTOCOL = "8B10B"; - parameter CH0_CDR_MAX_RATE = "2.5"; - parameter CH1_CDR_MAX_RATE = "2.5"; - parameter CH0_TXDEPRE = "DISABLED"; - parameter CH1_TXDEPRE = "DISABLED"; - parameter CH0_TXDEPOST = "DISABLED"; - parameter CH1_TXDEPOST = "DISABLED"; +(* blackbox *) +module ODDRX2DQSB (...); + parameter GSR = "ENABLED"; + input D3; + input D2; + input D1; + input D0; + input SCLK; + input ECLK; + input DQSW; + input RST; + output Q; endmodule (* blackbox *) -module EXTREFB ( - (* iopad_external_pin *) - input REFCLKP, - (* iopad_external_pin *) - input REFCLKN, - output REFCLKO -); - parameter REFCK_PWDNB = "0b0"; - parameter REFCK_RTERM = "0b0"; - parameter REFCK_DCBIAS_EN = "0b0"; +module EHXPLLL (...); + parameter CLKI_DIV = 1; + parameter CLKFB_DIV = 1; + parameter CLKOP_DIV = 8; + parameter CLKOS_DIV = 8; + parameter CLKOS2_DIV = 8; + parameter CLKOS3_DIV = 8; + parameter CLKOP_ENABLE = "ENABLED"; + parameter CLKOS_ENABLE = "DISABLED"; + parameter CLKOS2_ENABLE = "DISABLED"; + parameter CLKOS3_ENABLE = "DISABLED"; + parameter CLKOP_CPHASE = 0; + parameter CLKOS_CPHASE = 0; + parameter CLKOS2_CPHASE = 0; + parameter CLKOS3_CPHASE = 0; + parameter CLKOP_FPHASE = 0; + parameter CLKOS_FPHASE = 0; + parameter CLKOS2_FPHASE = 0; + parameter CLKOS3_FPHASE = 0; + parameter FEEDBK_PATH = "CLKOP"; + parameter CLKOP_TRIM_POL = "RISING"; + parameter CLKOP_TRIM_DELAY = 0; + parameter CLKOS_TRIM_POL = "RISING"; + parameter CLKOS_TRIM_DELAY = 0; + parameter OUTDIVIDER_MUXA = "DIVA"; + parameter OUTDIVIDER_MUXB = "DIVB"; + parameter OUTDIVIDER_MUXC = "DIVC"; + parameter OUTDIVIDER_MUXD = "DIVD"; + parameter PLL_LOCK_MODE = 0; + parameter PLL_LOCK_DELAY = 200; + parameter STDBY_ENABLE = "DISABLED"; + parameter REFIN_RESET = "DISABLED"; + parameter SYNC_ENABLE = "DISABLED"; + parameter INT_LOCK_STICKY = "ENABLED"; + parameter DPHASE_SOURCE = "DISABLED"; + parameter PLLRST_ENA = "DISABLED"; + parameter INTFB_WAKE = "DISABLED"; + input CLKI; + input CLKFB; + input PHASESEL1; + input PHASESEL0; + input PHASEDIR; + input PHASESTEP; + input PHASELOADREG; + input STDBY; + input PLLWAKESYNC; + input RST; + input ENCLKOP; + input ENCLKOS; + input ENCLKOS2; + input ENCLKOS3; + output CLKOP; + output CLKOS; + output CLKOS2; + output CLKOS3; + output LOCK; + output INTLOCK; + output REFCLK; + output CLKINTFB; endmodule (* blackbox *) -module PCSCLKDIV ( - input CLKI, RST, SEL2, SEL1, SEL0, - output CDIV1, CDIVX -); - parameter GSR = "DISABLED"; +module DTR (...); + parameter DTR_TEMP = 25; + input STARTPULSE; + output DTROUT7; + output DTROUT6; + output DTROUT5; + output DTROUT4; + output DTROUT3; + output DTROUT2; + output DTROUT1; + output DTROUT0; endmodule -// Note: this module is not marked keep as we want it swept away in synth (sim use only) (* blackbox *) -module PUR ( - input PUR -); - parameter RST_PULSE = 1; +module OSCG (...); + parameter DIV = 128; + output OSC; endmodule -(* blackbox, keep *) -module GSR ( - input GSR -); +(* blackbox *) +module EXTREFB (...); + parameter REFCK_PWDNB = "DONTCARE"; + parameter REFCK_RTERM = "DONTCARE"; + parameter REFCK_DCBIAS_EN = "DONTCARE"; + (* iopad_external_pin *) + input REFCLKP; + (* iopad_external_pin *) + input REFCLKN; + output REFCLKO; + output ; endmodule -(* blackbox, keep *) -module SGSR ( - input GSR, CLK -); +(* blackbox *) (* keep *) +module JTAGG (...); + parameter ER1 = "ENABLED"; + parameter ER2 = "ENABLED"; + (* iopad_external_pin *) + input TCK; + (* iopad_external_pin *) + input TMS; + (* iopad_external_pin *) + input TDI; + input JTDO2; + input JTDO1; + (* iopad_external_pin *) + output TDO; + output JTDI; + output JTCK; + output JRTI2; + output JRTI1; + output JSHIFT; + output JUPDATE; + output JRSTN; + output JCE2; + output JCE1; endmodule - -(* blackbox *) -module PDPW16KD ( - input DI35, DI34, DI33, DI32, DI31, DI30, DI29, DI28, DI27, DI26, DI25, DI24, DI23, DI22, DI21, DI20, DI19, DI18, - input DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, - input ADW8, ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, - input BE3, BE2, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0, - input ADR13, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5, ADR4, ADR3, ADR2, ADR1, ADR0, - input CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, - output DO35, DO34, DO33, DO32, DO31, DO30, DO29, DO28, DO27, DO26, DO25, DO24, DO23, DO22, DO21, DO20, DO19, DO18, - output DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 -); - parameter DATA_WIDTH_W = 36; - parameter DATA_WIDTH_R = 36; - parameter GSR = "ENABLED"; - - parameter REGMODE = "NOREG"; - - parameter RESETMODE = "SYNC"; - parameter ASYNC_RESET_RELEASE = "SYNC"; - - parameter CSDECODE_W = "0b000"; - parameter CSDECODE_R = "0b000"; - - parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_DATA = "STATIC"; - parameter CLKWMUX = "CLKW"; - parameter CLKRMUX = "CLKR"; - +(* blackbox *) (* keep *) +module DCUA (...); + parameter D_MACROPDB = "DONTCARE"; + parameter D_IB_PWDNB = "DONTCARE"; + parameter D_XGE_MODE = "DONTCARE"; + parameter D_LOW_MARK = "DONTCARE"; + parameter D_HIGH_MARK = "DONTCARE"; + parameter D_BUS8BIT_SEL = "DONTCARE"; + parameter D_CDR_LOL_SET = "DONTCARE"; + parameter D_BITCLK_LOCAL_EN = "DONTCARE"; + parameter D_BITCLK_ND_EN = "DONTCARE"; + parameter D_BITCLK_FROM_ND_EN = "DONTCARE"; + parameter D_SYNC_LOCAL_EN = "DONTCARE"; + parameter D_SYNC_ND_EN = "DONTCARE"; + parameter CH0_UC_MODE = "DONTCARE"; + parameter CH1_UC_MODE = "DONTCARE"; + parameter CH0_PCIE_MODE = "DONTCARE"; + parameter CH1_PCIE_MODE = "DONTCARE"; + parameter CH0_RIO_MODE = "DONTCARE"; + parameter CH1_RIO_MODE = "DONTCARE"; + parameter CH0_WA_MODE = "DONTCARE"; + parameter CH1_WA_MODE = "DONTCARE"; + parameter CH0_INVERT_RX = "DONTCARE"; + parameter CH1_INVERT_RX = "DONTCARE"; + parameter CH0_INVERT_TX = "DONTCARE"; + parameter CH1_INVERT_TX = "DONTCARE"; + parameter CH0_PRBS_SELECTION = "DONTCARE"; + parameter CH1_PRBS_SELECTION = "DONTCARE"; + parameter CH0_GE_AN_ENABLE = "DONTCARE"; + parameter CH1_GE_AN_ENABLE = "DONTCARE"; + parameter CH0_PRBS_LOCK = "DONTCARE"; + parameter CH1_PRBS_LOCK = "DONTCARE"; + parameter CH0_PRBS_ENABLE = "DONTCARE"; + parameter CH1_PRBS_ENABLE = "DONTCARE"; + parameter CH0_ENABLE_CG_ALIGN = "DONTCARE"; + parameter CH1_ENABLE_CG_ALIGN = "DONTCARE"; + parameter CH0_TX_GEAR_MODE = "DONTCARE"; + parameter CH1_TX_GEAR_MODE = "DONTCARE"; + parameter CH0_RX_GEAR_MODE = "DONTCARE"; + parameter CH1_RX_GEAR_MODE = "DONTCARE"; + parameter CH0_PCS_DET_TIME_SEL = "DONTCARE"; + parameter CH1_PCS_DET_TIME_SEL = "DONTCARE"; + parameter CH0_PCIE_EI_EN = "DONTCARE"; + parameter CH1_PCIE_EI_EN = "DONTCARE"; + parameter CH0_TX_GEAR_BYPASS = "DONTCARE"; + parameter CH1_TX_GEAR_BYPASS = "DONTCARE"; + parameter CH0_ENC_BYPASS = "DONTCARE"; + parameter CH1_ENC_BYPASS = "DONTCARE"; + parameter CH0_SB_BYPASS = "DONTCARE"; + parameter CH1_SB_BYPASS = "DONTCARE"; + parameter CH0_RX_SB_BYPASS = "DONTCARE"; + parameter CH1_RX_SB_BYPASS = "DONTCARE"; + parameter CH0_WA_BYPASS = "DONTCARE"; + parameter CH1_WA_BYPASS = "DONTCARE"; + parameter CH0_DEC_BYPASS = "DONTCARE"; + parameter CH1_DEC_BYPASS = "DONTCARE"; + parameter CH0_CTC_BYPASS = "DONTCARE"; + parameter CH1_CTC_BYPASS = "DONTCARE"; + parameter CH0_RX_GEAR_BYPASS = "DONTCARE"; + parameter CH1_RX_GEAR_BYPASS = "DONTCARE"; + parameter CH0_LSM_DISABLE = "DONTCARE"; + parameter CH1_LSM_DISABLE = "DONTCARE"; + parameter CH0_MATCH_2_ENABLE = "DONTCARE"; + parameter CH1_MATCH_2_ENABLE = "DONTCARE"; + parameter CH0_MATCH_4_ENABLE = "DONTCARE"; + parameter CH1_MATCH_4_ENABLE = "DONTCARE"; + parameter CH0_MIN_IPG_CNT = "DONTCARE"; + parameter CH1_MIN_IPG_CNT = "DONTCARE"; + parameter CH0_CC_MATCH_1 = "DONTCARE"; + parameter CH1_CC_MATCH_1 = "DONTCARE"; + parameter CH0_CC_MATCH_2 = "DONTCARE"; + parameter CH1_CC_MATCH_2 = "DONTCARE"; + parameter CH0_CC_MATCH_3 = "DONTCARE"; + parameter CH1_CC_MATCH_3 = "DONTCARE"; + parameter CH0_CC_MATCH_4 = "DONTCARE"; + parameter CH1_CC_MATCH_4 = "DONTCARE"; + parameter CH0_UDF_COMMA_MASK = "DONTCARE"; + parameter CH1_UDF_COMMA_MASK = "DONTCARE"; + parameter CH0_UDF_COMMA_A = "DONTCARE"; + parameter CH1_UDF_COMMA_A = "DONTCARE"; + parameter CH0_UDF_COMMA_B = "DONTCARE"; + parameter CH1_UDF_COMMA_B = "DONTCARE"; + parameter CH0_RX_DCO_CK_DIV = "DONTCARE"; + parameter CH1_RX_DCO_CK_DIV = "DONTCARE"; + parameter CH0_RCV_DCC_EN = "DONTCARE"; + parameter CH1_RCV_DCC_EN = "DONTCARE"; + parameter CH0_REQ_LVL_SET = "DONTCARE"; + parameter CH1_REQ_LVL_SET = "DONTCARE"; + parameter CH0_REQ_EN = "DONTCARE"; + parameter CH1_REQ_EN = "DONTCARE"; + parameter CH0_RTERM_RX = "DONTCARE"; + parameter CH1_RTERM_RX = "DONTCARE"; + parameter CH0_PDEN_SEL = "DONTCARE"; + parameter CH1_PDEN_SEL = "DONTCARE"; + parameter CH0_LDR_RX2CORE_SEL = "DONTCARE"; + parameter CH1_LDR_RX2CORE_SEL = "DONTCARE"; + parameter CH0_LDR_CORE2TX_SEL = "DONTCARE"; + parameter CH1_LDR_CORE2TX_SEL = "DONTCARE"; + parameter CH0_TPWDNB = "DONTCARE"; + parameter CH1_TPWDNB = "DONTCARE"; + parameter CH0_RATE_MODE_TX = "DONTCARE"; + parameter CH1_RATE_MODE_TX = "DONTCARE"; + parameter CH0_RTERM_TX = "DONTCARE"; + parameter CH1_RTERM_TX = "DONTCARE"; + parameter CH0_TX_CM_SEL = "DONTCARE"; + parameter CH1_TX_CM_SEL = "DONTCARE"; + parameter CH0_TDRV_PRE_EN = "DONTCARE"; + parameter CH1_TDRV_PRE_EN = "DONTCARE"; + parameter CH0_TDRV_SLICE0_SEL = "DONTCARE"; + parameter CH1_TDRV_SLICE0_SEL = "DONTCARE"; + parameter CH0_TDRV_SLICE1_SEL = "DONTCARE"; + parameter CH1_TDRV_SLICE1_SEL = "DONTCARE"; + parameter CH0_TDRV_SLICE2_SEL = "DONTCARE"; + parameter CH1_TDRV_SLICE2_SEL = "DONTCARE"; + parameter CH0_TDRV_SLICE3_SEL = "DONTCARE"; + parameter CH1_TDRV_SLICE3_SEL = "DONTCARE"; + parameter CH0_TDRV_SLICE4_SEL = "DONTCARE"; + parameter CH1_TDRV_SLICE4_SEL = "DONTCARE"; + parameter CH0_TDRV_SLICE5_SEL = "DONTCARE"; + parameter CH1_TDRV_SLICE5_SEL = "DONTCARE"; + parameter CH0_TDRV_SLICE0_CUR = "DONTCARE"; + parameter CH1_TDRV_SLICE0_CUR = "DONTCARE"; + parameter CH0_TDRV_SLICE1_CUR = "DONTCARE"; + parameter CH1_TDRV_SLICE1_CUR = "DONTCARE"; + parameter CH0_TDRV_SLICE2_CUR = "DONTCARE"; + parameter CH1_TDRV_SLICE2_CUR = "DONTCARE"; + parameter CH0_TDRV_SLICE3_CUR = "DONTCARE"; + parameter CH1_TDRV_SLICE3_CUR = "DONTCARE"; + parameter CH0_TDRV_SLICE4_CUR = "DONTCARE"; + parameter CH1_TDRV_SLICE4_CUR = "DONTCARE"; + parameter CH0_TDRV_SLICE5_CUR = "DONTCARE"; + parameter CH1_TDRV_SLICE5_CUR = "DONTCARE"; + parameter CH0_TDRV_DAT_SEL = "DONTCARE"; + parameter CH1_TDRV_DAT_SEL = "DONTCARE"; + parameter CH0_TX_DIV11_SEL = "DONTCARE"; + parameter CH1_TX_DIV11_SEL = "DONTCARE"; + parameter CH0_RPWDNB = "DONTCARE"; + parameter CH1_RPWDNB = "DONTCARE"; + parameter CH0_RATE_MODE_RX = "DONTCARE"; + parameter CH1_RATE_MODE_RX = "DONTCARE"; + parameter CH0_RLOS_SEL = "DONTCARE"; + parameter CH1_RLOS_SEL = "DONTCARE"; + parameter CH0_RX_LOS_LVL = "DONTCARE"; + parameter CH1_RX_LOS_LVL = "DONTCARE"; + parameter CH0_RX_LOS_CEQ = "DONTCARE"; + parameter CH1_RX_LOS_CEQ = "DONTCARE"; + parameter CH0_RX_LOS_HYST_EN = "DONTCARE"; + parameter CH1_RX_LOS_HYST_EN = "DONTCARE"; + parameter CH0_RX_LOS_EN = "DONTCARE"; + parameter CH1_RX_LOS_EN = "DONTCARE"; + parameter CH0_RX_DIV11_SEL = "DONTCARE"; + parameter CH1_RX_DIV11_SEL = "DONTCARE"; + parameter CH0_SEL_SD_RX_CLK = "DONTCARE"; + parameter CH1_SEL_SD_RX_CLK = "DONTCARE"; + parameter CH0_FF_RX_H_CLK_EN = "DONTCARE"; + parameter CH1_FF_RX_H_CLK_EN = "DONTCARE"; + parameter CH0_FF_RX_F_CLK_DIS = "DONTCARE"; + parameter CH1_FF_RX_F_CLK_DIS = "DONTCARE"; + parameter CH0_FF_TX_H_CLK_EN = "DONTCARE"; + parameter CH1_FF_TX_H_CLK_EN = "DONTCARE"; + parameter CH0_FF_TX_F_CLK_DIS = "DONTCARE"; + parameter CH1_FF_TX_F_CLK_DIS = "DONTCARE"; + parameter CH0_RX_RATE_SEL = "DONTCARE"; + parameter CH1_RX_RATE_SEL = "DONTCARE"; + parameter CH0_TDRV_POST_EN = "DONTCARE"; + parameter CH1_TDRV_POST_EN = "DONTCARE"; + parameter CH0_TX_POST_SIGN = "DONTCARE"; + parameter CH1_TX_POST_SIGN = "DONTCARE"; + parameter CH0_TX_PRE_SIGN = "DONTCARE"; + parameter CH1_TX_PRE_SIGN = "DONTCARE"; + parameter CH0_RXTERM_CM = "DONTCARE"; + parameter CH1_RXTERM_CM = "DONTCARE"; + parameter CH0_RXIN_CM = "DONTCARE"; + parameter CH1_RXIN_CM = "DONTCARE"; + parameter CH0_LEQ_OFFSET_SEL = "DONTCARE"; + parameter CH1_LEQ_OFFSET_SEL = "DONTCARE"; + parameter CH0_LEQ_OFFSET_TRIM = "DONTCARE"; + parameter CH1_LEQ_OFFSET_TRIM = "DONTCARE"; + parameter D_TX_MAX_RATE = "DONTCARE"; + parameter CH0_CDR_MAX_RATE = "DONTCARE"; + parameter CH1_CDR_MAX_RATE = "DONTCARE"; + parameter CH0_TXAMPLITUDE = "DONTCARE"; + parameter CH1_TXAMPLITUDE = "DONTCARE"; + parameter CH0_TXDEPRE = "DONTCARE"; + parameter CH1_TXDEPRE = "DONTCARE"; + parameter CH0_TXDEPOST = "DONTCARE"; + parameter CH1_TXDEPOST = "DONTCARE"; + parameter CH0_PROTOCOL = "DONTCARE"; + parameter CH1_PROTOCOL = "DONTCARE"; + parameter D_ISETLOS = "DONTCARE"; + parameter D_SETIRPOLY_AUX = "DONTCARE"; + parameter D_SETICONST_AUX = "DONTCARE"; + parameter D_SETIRPOLY_CH = "DONTCARE"; + parameter D_SETICONST_CH = "DONTCARE"; + parameter D_REQ_ISET = "DONTCARE"; + parameter D_PD_ISET = "DONTCARE"; + parameter D_DCO_CALIB_TIME_SEL = "DONTCARE"; + parameter CH0_DCOCTLGI = "DONTCARE"; + parameter CH1_DCOCTLGI = "DONTCARE"; + parameter CH0_DCOATDDLY = "DONTCARE"; + parameter CH1_DCOATDDLY = "DONTCARE"; + parameter CH0_DCOATDCFG = "DONTCARE"; + parameter CH1_DCOATDCFG = "DONTCARE"; + parameter CH0_DCOBYPSATD = "DONTCARE"; + parameter CH1_DCOBYPSATD = "DONTCARE"; + parameter CH0_DCOSCALEI = "DONTCARE"; + parameter CH1_DCOSCALEI = "DONTCARE"; + parameter CH0_DCOITUNE4LSB = "DONTCARE"; + parameter CH1_DCOITUNE4LSB = "DONTCARE"; + parameter CH0_DCOIOSTUNE = "DONTCARE"; + parameter CH1_DCOIOSTUNE = "DONTCARE"; + parameter CH0_DCODISBDAVOID = "DONTCARE"; + parameter CH1_DCODISBDAVOID = "DONTCARE"; + parameter CH0_DCOCALDIV = "DONTCARE"; + parameter CH1_DCOCALDIV = "DONTCARE"; + parameter CH0_DCONUOFLSB = "DONTCARE"; + parameter CH1_DCONUOFLSB = "DONTCARE"; + parameter CH0_DCOIUPDNX2 = "DONTCARE"; + parameter CH1_DCOIUPDNX2 = "DONTCARE"; + parameter CH0_DCOSTEP = "DONTCARE"; + parameter CH1_DCOSTEP = "DONTCARE"; + parameter CH0_DCOSTARTVAL = "DONTCARE"; + parameter CH1_DCOSTARTVAL = "DONTCARE"; + parameter CH0_DCOFLTDAC = "DONTCARE"; + parameter CH1_DCOFLTDAC = "DONTCARE"; + parameter CH0_DCOITUNE = "DONTCARE"; + parameter CH1_DCOITUNE = "DONTCARE"; + parameter CH0_DCOFTNRG = "DONTCARE"; + parameter CH1_DCOFTNRG = "DONTCARE"; + parameter CH0_CDR_CNT4SEL = "DONTCARE"; + parameter CH1_CDR_CNT4SEL = "DONTCARE"; + parameter CH0_CDR_CNT8SEL = "DONTCARE"; + parameter CH1_CDR_CNT8SEL = "DONTCARE"; + parameter CH0_BAND_THRESHOLD = "DONTCARE"; + parameter CH1_BAND_THRESHOLD = "DONTCARE"; + parameter CH0_AUTO_FACQ_EN = "DONTCARE"; + parameter CH1_AUTO_FACQ_EN = "DONTCARE"; + parameter CH0_AUTO_CALIB_EN = "DONTCARE"; + parameter CH1_AUTO_CALIB_EN = "DONTCARE"; + parameter CH0_CALIB_CK_MODE = "DONTCARE"; + parameter CH1_CALIB_CK_MODE = "DONTCARE"; + parameter CH0_REG_BAND_OFFSET = "DONTCARE"; + parameter CH1_REG_BAND_OFFSET = "DONTCARE"; + parameter CH0_REG_BAND_SEL = "DONTCARE"; + parameter CH1_REG_BAND_SEL = "DONTCARE"; + parameter CH0_REG_IDAC_SEL = "DONTCARE"; + parameter CH1_REG_IDAC_SEL = "DONTCARE"; + parameter CH0_REG_IDAC_EN = "DONTCARE"; + parameter CH1_REG_IDAC_EN = "DONTCARE"; + parameter D_TXPLL_PWDNB = "DONTCARE"; + parameter D_SETPLLRC = "DONTCARE"; + parameter D_REFCK_MODE = "DONTCARE"; + parameter D_TX_VCO_CK_DIV = "DONTCARE"; + parameter D_PLL_LOL_SET = "DONTCARE"; + parameter D_RG_EN = "DONTCARE"; + parameter D_RG_SET = "DONTCARE"; + parameter D_CMUSETISCL4VCO = "DONTCARE"; + parameter D_CMUSETI4VCO = "DONTCARE"; + parameter D_CMUSETINITVCT = "DONTCARE"; + parameter D_CMUSETZGM = "DONTCARE"; + parameter D_CMUSETP2AGM = "DONTCARE"; + parameter D_CMUSETP1GM = "DONTCARE"; + parameter D_CMUSETI4CPZ = "DONTCARE"; + parameter D_CMUSETI4CPP = "DONTCARE"; + parameter D_CMUSETICP4Z = "DONTCARE"; + parameter D_CMUSETICP4P = "DONTCARE"; + parameter D_CMUSETBIASI = "DONTCARE"; + (* iopad_external_pin *) + (* iopad_external_pin *) + input CH0_HDINP; + (* iopad_external_pin *) + input CH1_HDINP; + (* iopad_external_pin *) + input CH0_HDINN; + (* iopad_external_pin *) + input CH1_HDINN; + input D_TXBIT_CLKP_FROM_ND; + input D_TXBIT_CLKN_FROM_ND; + input D_SYNC_ND; + input D_TXPLL_LOL_FROM_ND; + input CH0_RX_REFCLK; + input CH1_RX_REFCLK; + input CH0_FF_RXI_CLK; + input CH1_FF_RXI_CLK; + input CH0_FF_TXI_CLK; + input CH1_FF_TXI_CLK; + input CH0_FF_EBRD_CLK; + input CH1_FF_EBRD_CLK; + input CH0_FF_TX_D_0; + input CH1_FF_TX_D_0; + input CH0_FF_TX_D_1; + input CH1_FF_TX_D_1; + input CH0_FF_TX_D_2; + input CH1_FF_TX_D_2; + input CH0_FF_TX_D_3; + input CH1_FF_TX_D_3; + input CH0_FF_TX_D_4; + input CH1_FF_TX_D_4; + input CH0_FF_TX_D_5; + input CH1_FF_TX_D_5; + input CH0_FF_TX_D_6; + input CH1_FF_TX_D_6; + input CH0_FF_TX_D_7; + input CH1_FF_TX_D_7; + input CH0_FF_TX_D_8; + input CH1_FF_TX_D_8; + input CH0_FF_TX_D_9; + input CH1_FF_TX_D_9; + input CH0_FF_TX_D_10; + input CH1_FF_TX_D_10; + input CH0_FF_TX_D_11; + input CH1_FF_TX_D_11; + input CH0_FF_TX_D_12; + input CH1_FF_TX_D_12; + input CH0_FF_TX_D_13; + input CH1_FF_TX_D_13; + input CH0_FF_TX_D_14; + input CH1_FF_TX_D_14; + input CH0_FF_TX_D_15; + input CH1_FF_TX_D_15; + input CH0_FF_TX_D_16; + input CH1_FF_TX_D_16; + input CH0_FF_TX_D_17; + input CH1_FF_TX_D_17; + input CH0_FF_TX_D_18; + input CH1_FF_TX_D_18; + input CH0_FF_TX_D_19; + input CH1_FF_TX_D_19; + input CH0_FF_TX_D_20; + input CH1_FF_TX_D_20; + input CH0_FF_TX_D_21; + input CH1_FF_TX_D_21; + input CH0_FF_TX_D_22; + input CH1_FF_TX_D_22; + input CH0_FF_TX_D_23; + input CH1_FF_TX_D_23; + input CH0_FFC_EI_EN; + input CH1_FFC_EI_EN; + input CH0_FFC_PCIE_DET_EN; + input CH1_FFC_PCIE_DET_EN; + input CH0_FFC_PCIE_CT; + input CH1_FFC_PCIE_CT; + input CH0_FFC_SB_INV_RX; + input CH1_FFC_SB_INV_RX; + input CH0_FFC_ENABLE_CGALIGN; + input CH1_FFC_ENABLE_CGALIGN; + input CH0_FFC_SIGNAL_DETECT; + input CH1_FFC_SIGNAL_DETECT; + input CH0_FFC_FB_LOOPBACK; + input CH1_FFC_FB_LOOPBACK; + input CH0_FFC_SB_PFIFO_LP; + input CH1_FFC_SB_PFIFO_LP; + input CH0_FFC_PFIFO_CLR; + input CH1_FFC_PFIFO_CLR; + input CH0_FFC_RATE_MODE_RX; + input CH1_FFC_RATE_MODE_RX; + input CH0_FFC_RATE_MODE_TX; + input CH1_FFC_RATE_MODE_TX; + input CH0_FFC_DIV11_MODE_RX; + input CH1_FFC_DIV11_MODE_RX; + input CH0_FFC_RX_GEAR_MODE; + input CH1_FFC_RX_GEAR_MODE; + input CH0_FFC_TX_GEAR_MODE; + input CH1_FFC_TX_GEAR_MODE; + input CH0_FFC_DIV11_MODE_TX; + input CH1_FFC_DIV11_MODE_TX; + input CH0_FFC_LDR_CORE2TX_EN; + input CH1_FFC_LDR_CORE2TX_EN; + input CH0_FFC_LANE_TX_RST; + input CH1_FFC_LANE_TX_RST; + input CH0_FFC_LANE_RX_RST; + input CH1_FFC_LANE_RX_RST; + input CH0_FFC_RRST; + input CH1_FFC_RRST; + input CH0_FFC_TXPWDNB; + input CH1_FFC_TXPWDNB; + input CH0_FFC_RXPWDNB; + input CH1_FFC_RXPWDNB; + input CH0_LDR_CORE2TX; + input CH1_LDR_CORE2TX; + input D_SCIWDATA0; + input D_SCIWDATA1; + input D_SCIWDATA2; + input D_SCIWDATA3; + input D_SCIWDATA4; + input D_SCIWDATA5; + input D_SCIWDATA6; + input D_SCIWDATA7; + input D_SCIADDR0; + input D_SCIADDR1; + input D_SCIADDR2; + input D_SCIADDR3; + input D_SCIADDR4; + input D_SCIADDR5; + input D_SCIENAUX; + input D_SCISELAUX; + input CH0_SCIEN; + input CH1_SCIEN; + input CH0_SCISEL; + input CH1_SCISEL; + input D_SCIRD; + input D_SCIWSTN; + input D_CYAWSTN; + input D_FFC_SYNC_TOGGLE; + input D_FFC_DUAL_RST; + input D_FFC_MACRO_RST; + input D_FFC_MACROPDB; + input D_FFC_TRST; + input CH0_FFC_CDR_EN_BITSLIP; + input CH1_FFC_CDR_EN_BITSLIP; + input D_SCAN_ENABLE; + input D_SCAN_IN_0; + input D_SCAN_IN_1; + input D_SCAN_IN_2; + input D_SCAN_IN_3; + input D_SCAN_IN_4; + input D_SCAN_IN_5; + input D_SCAN_IN_6; + input D_SCAN_IN_7; + input D_SCAN_MODE; + input D_SCAN_RESET; + input D_CIN0; + input D_CIN1; + input D_CIN2; + input D_CIN3; + input D_CIN4; + input D_CIN5; + input D_CIN6; + input D_CIN7; + input D_CIN8; + input D_CIN9; + input D_CIN10; + input D_CIN11; + output CH0_HDOUTP; + output CH1_HDOUTP; + output CH0_HDOUTN; + output CH1_HDOUTN; + output D_TXBIT_CLKP_TO_ND; + output D_TXBIT_CLKN_TO_ND; + output D_SYNC_PULSE2ND; + output D_TXPLL_LOL_TO_ND; + output CH0_FF_RX_F_CLK; + output CH1_FF_RX_F_CLK; + output CH0_FF_RX_H_CLK; + output CH1_FF_RX_H_CLK; + output CH0_FF_TX_F_CLK; + output CH1_FF_TX_F_CLK; + output CH0_FF_TX_H_CLK; + output CH1_FF_TX_H_CLK; + output CH0_FF_RX_PCLK; + output CH1_FF_RX_PCLK; + output CH0_FF_TX_PCLK; + output CH1_FF_TX_PCLK; + output CH0_FF_RX_D_0; + output CH1_FF_RX_D_0; + output CH0_FF_RX_D_1; + output CH1_FF_RX_D_1; + output CH0_FF_RX_D_2; + output CH1_FF_RX_D_2; + output CH0_FF_RX_D_3; + output CH1_FF_RX_D_3; + output CH0_FF_RX_D_4; + output CH1_FF_RX_D_4; + output CH0_FF_RX_D_5; + output CH1_FF_RX_D_5; + output CH0_FF_RX_D_6; + output CH1_FF_RX_D_6; + output CH0_FF_RX_D_7; + output CH1_FF_RX_D_7; + output CH0_FF_RX_D_8; + output CH1_FF_RX_D_8; + output CH0_FF_RX_D_9; + output CH1_FF_RX_D_9; + output CH0_FF_RX_D_10; + output CH1_FF_RX_D_10; + output CH0_FF_RX_D_11; + output CH1_FF_RX_D_11; + output CH0_FF_RX_D_12; + output CH1_FF_RX_D_12; + output CH0_FF_RX_D_13; + output CH1_FF_RX_D_13; + output CH0_FF_RX_D_14; + output CH1_FF_RX_D_14; + output CH0_FF_RX_D_15; + output CH1_FF_RX_D_15; + output CH0_FF_RX_D_16; + output CH1_FF_RX_D_16; + output CH0_FF_RX_D_17; + output CH1_FF_RX_D_17; + output CH0_FF_RX_D_18; + output CH1_FF_RX_D_18; + output CH0_FF_RX_D_19; + output CH1_FF_RX_D_19; + output CH0_FF_RX_D_20; + output CH1_FF_RX_D_20; + output CH0_FF_RX_D_21; + output CH1_FF_RX_D_21; + output CH0_FF_RX_D_22; + output CH1_FF_RX_D_22; + output CH0_FF_RX_D_23; + output CH1_FF_RX_D_23; + output CH0_FFS_PCIE_DONE; + output CH1_FFS_PCIE_DONE; + output CH0_FFS_PCIE_CON; + output CH1_FFS_PCIE_CON; + output CH0_FFS_RLOS; + output CH1_FFS_RLOS; + output CH0_FFS_LS_SYNC_STATUS; + output CH1_FFS_LS_SYNC_STATUS; + output CH0_FFS_CC_UNDERRUN; + output CH1_FFS_CC_UNDERRUN; + output CH0_FFS_CC_OVERRUN; + output CH1_FFS_CC_OVERRUN; + output CH0_FFS_RXFBFIFO_ERROR; + output CH1_FFS_RXFBFIFO_ERROR; + output CH0_FFS_TXFBFIFO_ERROR; + output CH1_FFS_TXFBFIFO_ERROR; + output CH0_FFS_RLOL; + output CH1_FFS_RLOL; + output CH0_FFS_SKP_ADDED; + output CH1_FFS_SKP_ADDED; + output CH0_FFS_SKP_DELETED; + output CH1_FFS_SKP_DELETED; + output CH0_LDR_RX2CORE; + output CH1_LDR_RX2CORE; + output D_SCIRDATA0; + output D_SCIRDATA1; + output D_SCIRDATA2; + output D_SCIRDATA3; + output D_SCIRDATA4; + output D_SCIRDATA5; + output D_SCIRDATA6; + output D_SCIRDATA7; + output D_SCIINT; + output D_SCAN_OUT_0; + output D_SCAN_OUT_1; + output D_SCAN_OUT_2; + output D_SCAN_OUT_3; + output D_SCAN_OUT_4; + output D_SCAN_OUT_5; + output D_SCAN_OUT_6; + output D_SCAN_OUT_7; + output D_COUT0; + output D_COUT1; + output D_COUT2; + output D_COUT3; + output D_COUT4; + output D_COUT5; + output D_COUT6; + output D_COUT7; + output D_COUT8; + output D_COUT9; + output D_COUT10; + output D_COUT11; + output D_COUT12; + output D_COUT13; + output D_COUT14; + output D_COUT15; + output D_COUT16; + output D_COUT17; + output D_COUT18; + output D_COUT19; + input D_REFCLKI; + output D_FFS_PLOL; + output ; endmodule + diff --git a/techlibs/lattice/cells_bb_xo2.v b/techlibs/lattice/cells_bb_xo2.v index 3363ed5710d..6e6b655c919 100644 --- a/techlibs/lattice/cells_bb_xo2.v +++ b/techlibs/lattice/cells_bb_xo2.v @@ -1,179 +1,153 @@ -(* blackbox *) -module DP8KC( - input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, - input ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0, - input CEA, OCEA, CLKA, WEA, RSTA, - input CSA2, CSA1, CSA0, - output DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, - - input DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0, - input ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, - input CEB, OCEB, CLKB, WEB, RSTB, - input CSB2, CSB1, CSB0, - output DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0 -); - parameter DATA_WIDTH_A = 9; - parameter DATA_WIDTH_B = 9; - - parameter REGMODE_A = "NOREG"; - parameter REGMODE_B = "NOREG"; - - parameter RESETMODE = "SYNC"; - parameter ASYNC_RESET_RELEASE = "SYNC"; - - parameter CSDECODE_A = "0b000"; - parameter CSDECODE_B = "0b000"; - - parameter WRITEMODE_A = "NORMAL"; - parameter WRITEMODE_B = "NORMAL"; +// Created by cells_xtra.py from Lattice models - parameter GSR = "ENABLED"; - parameter INIT_DATA = "STATIC"; - - parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; +(* blackbox *) (* keep *) +module GSR (...); + input GSR; endmodule -(* blackbox *) -module EHXPLLJ ( - input CLKI, CLKFB, - input PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, - input LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD, - input ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE, - input PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0, - input PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0, - output CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK, - output PLLDATO7, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK, - output DPHSRC, CLKINTFB -); - parameter CLKI_DIV = 1; - parameter CLKFB_DIV = 1; - parameter CLKOP_DIV = 8; - parameter CLKOS_DIV = 8; - parameter CLKOS2_DIV = 8; - parameter CLKOS3_DIV = 8; - parameter CLKOP_ENABLE = "ENABLED"; - parameter CLKOS_ENABLE = "ENABLED"; - parameter CLKOS2_ENABLE = "ENABLED"; - parameter CLKOS3_ENABLE = "ENABLED"; - parameter VCO_BYPASS_A0 = "DISABLED"; - parameter VCO_BYPASS_B0 = "DISABLED"; - parameter VCO_BYPASS_C0 = "DISABLED"; - parameter VCO_BYPASS_D0 = "DISABLED"; - parameter CLKOP_CPHASE = 0; - parameter CLKOS_CPHASE = 0; - parameter CLKOS2_CPHASE = 0; - parameter CLKOS3_CPHASE = 0; - parameter CLKOP_FPHASE = 0; - parameter CLKOS_FPHASE = 0; - parameter CLKOS2_FPHASE = 0; - parameter CLKOS3_FPHASE = 0; - parameter FEEDBK_PATH = "CLKOP"; - parameter FRACN_ENABLE = "DISABLED"; - parameter FRACN_DIV = 0; - parameter CLKOP_TRIM_POL = "RISING"; - parameter CLKOP_TRIM_DELAY = 0; - parameter CLKOS_TRIM_POL = "RISING"; - parameter CLKOS_TRIM_DELAY = 0; - parameter PLL_USE_WB = "DISABLED"; - parameter PREDIVIDER_MUXA1 = 0; - parameter PREDIVIDER_MUXB1 = 0; - parameter PREDIVIDER_MUXC1 = 0; - parameter PREDIVIDER_MUXD1 = 0; - parameter OUTDIVIDER_MUXA2 = "DIVA"; - parameter OUTDIVIDER_MUXB2 = "DIVB"; - parameter OUTDIVIDER_MUXC2 = "DIVC"; - parameter OUTDIVIDER_MUXD2 = "DIVD"; - parameter PLL_LOCK_MODE = 0; - parameter STDBY_ENABLE = "DISABLED"; - parameter DPHASE_SOURCE = "DISABLED"; - parameter PLLRST_ENA = "DISABLED"; - parameter MRST_ENA = "DISABLED"; - parameter DCRST_ENA = "DISABLED"; - parameter DDRST_ENA = "DISABLED"; - parameter INTFB_WAKE = "DISABLED"; -endmodule - -(* blackbox *) -module OSCH #( - parameter NOM_FREQ = "2.08" -) ( - input STDBY, - output OSC, - output SEDSTDBY -); -endmodule - -(* blackbox *) -module DCCA ( - input CLKI, - input CE, - output CLKO -); +(* blackbox *) (* keep *) +module SGSR (...); + input GSR; + input CLK; endmodule (* blackbox *) -module DCMA ( - input CLK0, - input CLK1, - input SEL, - output DCMOUT -); +module DP8KC (...); + parameter DATA_WIDTH_A = 9; + parameter DATA_WIDTH_B = 9; + parameter REGMODE_A = "NOREG"; + parameter REGMODE_B = "NOREG"; + parameter CSDECODE_A = "0b000"; + parameter CSDECODE_B = "0b000"; + parameter WRITEMODE_A = "NORMAL"; + parameter WRITEMODE_B = "NORMAL"; + parameter GSR = "ENABLED"; + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter INIT_DATA = "STATIC"; + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + input DIA8; + input DIA7; + input DIA6; + input DIA5; + input DIA4; + input DIA3; + input DIA2; + input DIA1; + input DIA0; + input ADA12; + input ADA11; + input ADA10; + input ADA9; + input ADA8; + input ADA7; + input ADA6; + input ADA5; + input ADA4; + input ADA3; + input ADA2; + input ADA1; + input ADA0; + input CEA; + input OCEA; + input CLKA; + input WEA; + input CSA2; + input CSA1; + input CSA0; + input RSTA; + input DIB8; + input DIB7; + input DIB6; + input DIB5; + input DIB4; + input DIB3; + input DIB2; + input DIB1; + input DIB0; + input ADB12; + input ADB11; + input ADB10; + input ADB9; + input ADB8; + input ADB7; + input ADB6; + input ADB5; + input ADB4; + input ADB3; + input ADB2; + input ADB1; + input ADB0; + input CEB; + input OCEB; + input CLKB; + input WEB; + input CSB2; + input CSB1; + input CSB0; + input RSTB; + output DOA8; + output DOA7; + output DOA6; + output DOA5; + output DOA4; + output DOA3; + output DOA2; + output DOA1; + output DOA0; + output DOB8; + output DOB7; + output DOB6; + output DOB5; + output DOB4; + output DOB3; + output DOB2; + output DOB1; + output DOB0; endmodule (* blackbox *) -module PDPW8KC ( - input DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, - input ADW8, ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, - input BE1, BE0, - input CEW, CLKW, CSW2, CSW1, CSW0, - input ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5, ADR4, ADR3, ADR2, ADR1, ADR0, - input CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, - output DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 -); +module PDPW8KC (...); parameter DATA_WIDTH_W = 18; parameter DATA_WIDTH_R = 9; - - parameter GSR = "ENABLED"; - parameter REGMODE = "NOREG"; - - parameter RESETMODE = "SYNC"; - parameter ASYNC_RESET_RELEASE = "SYNC"; - parameter CSDECODE_W = "0b000"; parameter CSDECODE_R = "0b000"; - + parameter GSR = "ENABLED"; + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter INIT_DATA = "STATIC"; parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; @@ -206,29 +180,90 @@ module PDPW8KC ( parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_DATA = "STATIC"; - + input DI17; + input DI16; + input DI15; + input DI14; + input DI13; + input DI12; + input DI11; + input DI10; + input DI9; + input DI8; + input DI7; + input DI6; + input DI5; + input DI4; + input DI3; + input DI2; + input DI1; + input DI0; + input ADW8; + input ADW7; + input ADW6; + input ADW5; + input ADW4; + input ADW3; + input ADW2; + input ADW1; + input ADW0; + input BE1; + input BE0; + input CEW; + input CLKW; + input CSW2; + input CSW1; + input CSW0; + input ADR12; + input ADR11; + input ADR10; + input ADR9; + input ADR8; + input ADR7; + input ADR6; + input ADR5; + input ADR4; + input ADR3; + input ADR2; + input ADR1; + input ADR0; + input CER; + input OCER; + input CLKR; + input CSR2; + input CSR1; + input CSR0; + input RST; + output DO17; + output DO16; + output DO15; + output DO14; + output DO13; + output DO12; + output DO11; + output DO10; + output DO9; + output DO8; + output DO7; + output DO6; + output DO5; + output DO4; + output DO3; + output DO2; + output DO1; + output DO0; endmodule (* blackbox *) -module SP8KC ( - input DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, - input AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0, - input CE, OCE, CLK, WE, CS2, CS1, CS0, RST, - output DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 -); +module SP8KC (...); parameter DATA_WIDTH = 9; - parameter GSR = "ENABLED"; - parameter REGMODE = "NOREG"; - - parameter RESETMODE = "SYNC"; - parameter ASYNC_RESET_RELEASE = "SYNC"; - parameter CSDECODE = "0b000"; - parameter WRITEMODE = "NORMAL"; - + parameter GSR = "ENABLED"; + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter INIT_DATA = "STATIC"; parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; @@ -261,33 +296,240 @@ module SP8KC ( parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_DATA = "STATIC"; + input DI8; + input DI7; + input DI6; + input DI5; + input DI4; + input DI3; + input DI2; + input DI1; + input DI0; + input AD12; + input AD11; + input AD10; + input AD9; + input AD8; + input AD7; + input AD6; + input AD5; + input AD4; + input AD3; + input AD2; + input AD1; + input AD0; + input CE; + input OCE; + input CLK; + input WE; + input CS2; + input CS1; + input CS0; + input RST; + output DO8; + output DO7; + output DO6; + output DO5; + output DO4; + output DO3; + output DO2; + output DO1; + output DO0; endmodule (* blackbox *) -module FIFO8KB ( - input DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, - input CSW0, CSW1, CSR0, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI, - output DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17, - input EF, AEF, AFF, FF -); +module FIFO8KB (...); parameter DATA_WIDTH_W = 18; parameter DATA_WIDTH_R = 18; - - parameter GSR = "DISABLED"; - parameter REGMODE = "NOREG"; - parameter RESETMODE = "ASYNC"; parameter ASYNC_RESET_RELEASE = "SYNC"; - parameter CSDECODE_W = "0b00"; parameter CSDECODE_R = "0b00"; - - parameter AEPOINTER = "0b00000000000000"; - parameter AEPOINTER1 = "0b00000000000000"; - parameter AFPOINTER = "0b00000000000000"; - parameter AFPOINTER1 = "0b00000000000000"; - parameter FULLPOINTER = "0b00000000000000"; + parameter AEPOINTER = "0b00000000000000"; + parameter AEPOINTER1 = "0b00000000000000"; + parameter AFPOINTER = "0b00000000000000"; + parameter AFPOINTER1 = "0b00000000000000"; + parameter FULLPOINTER = "0b00000000000000"; parameter FULLPOINTER1 = "0b00000000000000"; + parameter GSR = "DISABLED"; + input DI0; + input DI1; + input DI2; + input DI3; + input DI4; + input DI5; + input DI6; + input DI7; + input DI8; + input DI9; + input DI10; + input DI11; + input DI12; + input DI13; + input DI14; + input DI15; + input DI16; + input DI17; + input CSW0; + input CSW1; + input CSR0; + input CSR1; + input WE; + input RE; + input ORE; + input CLKW; + input CLKR; + input RST; + input RPRST; + input FULLI; + input EMPTYI; + output DO0; + output DO1; + output DO2; + output DO3; + output DO4; + output DO5; + output DO6; + output DO7; + output DO8; + output DO9; + output DO10; + output DO11; + output DO12; + output DO13; + output DO14; + output DO15; + output DO16; + output DO17; + output EF; + output AEF; + output AFF; + output FF; +endmodule + +(* blackbox *) +module DCMA (...); + input CLK0; + input CLK1; + input SEL; + output DCMOUT; +endmodule + +(* blackbox *) +module DCCA (...); + input CLKI; + input CE; + output CLKO; +endmodule + +(* blackbox *) +module EHXPLLJ (...); + parameter CLKI_DIV = 1; + parameter CLKFB_DIV = 1; + parameter CLKOP_DIV = 8; + parameter CLKOS_DIV = 8; + parameter CLKOS2_DIV = 8; + parameter CLKOS3_DIV = 8; + parameter CLKOP_ENABLE = "ENABLED"; + parameter CLKOS_ENABLE = "ENABLED"; + parameter CLKOS2_ENABLE = "ENABLED"; + parameter CLKOS3_ENABLE = "ENABLED"; + parameter VCO_BYPASS_A0 = "DISABLED"; + parameter VCO_BYPASS_B0 = "DISABLED"; + parameter VCO_BYPASS_C0 = "DISABLED"; + parameter VCO_BYPASS_D0 = "DISABLED"; + parameter CLKOP_CPHASE = 0; + parameter CLKOS_CPHASE = 0; + parameter CLKOS2_CPHASE = 0; + parameter CLKOS3_CPHASE = 0; + parameter CLKOP_FPHASE = 0; + parameter CLKOS_FPHASE = 0; + parameter CLKOS2_FPHASE = 0; + parameter CLKOS3_FPHASE = 0; + parameter FEEDBK_PATH = "CLKOP"; + parameter FRACN_ENABLE = "DISABLED"; + parameter FRACN_DIV = 0; + parameter CLKOP_TRIM_POL = "RISING"; + parameter CLKOP_TRIM_DELAY = 0; + parameter CLKOS_TRIM_POL = "RISING"; + parameter CLKOS_TRIM_DELAY = 0; + parameter PLL_USE_WB = "DISABLED"; + parameter PREDIVIDER_MUXA1 = 0; + parameter PREDIVIDER_MUXB1 = 0; + parameter PREDIVIDER_MUXC1 = 0; + parameter PREDIVIDER_MUXD1 = 0; + parameter OUTDIVIDER_MUXA2 = "DIVA"; + parameter OUTDIVIDER_MUXB2 = "DIVB"; + parameter OUTDIVIDER_MUXC2 = "DIVC"; + parameter OUTDIVIDER_MUXD2 = "DIVD"; + parameter PLL_LOCK_MODE = 0; + parameter STDBY_ENABLE = "DISABLED"; + parameter DPHASE_SOURCE = "DISABLED"; + parameter PLLRST_ENA = "DISABLED"; + parameter MRST_ENA = "DISABLED"; + parameter DCRST_ENA = "DISABLED"; + parameter DDRST_ENA = "DISABLED"; + parameter INTFB_WAKE = "DISABLED"; + input CLKI; + input CLKFB; + input PHASESEL1; + input PHASESEL0; + input PHASEDIR; + input PHASESTEP; + input LOADREG; + input STDBY; + input PLLWAKESYNC; + input RST; + input RESETM; + input RESETC; + input RESETD; + input ENCLKOP; + input ENCLKOS; + input ENCLKOS2; + input ENCLKOS3; + input PLLCLK; + input PLLRST; + input PLLSTB; + input PLLWE; + input PLLDATI7; + input PLLDATI6; + input PLLDATI5; + input PLLDATI4; + input PLLDATI3; + input PLLDATI2; + input PLLDATI1; + input PLLDATI0; + input PLLADDR4; + input PLLADDR3; + input PLLADDR2; + input PLLADDR1; + input PLLADDR0; + output CLKOP; + output CLKOS; + output CLKOS2; + output CLKOS3; + output LOCK; + output INTLOCK; + output REFCLK; + output PLLDATO7; + output PLLDATO6; + output PLLDATO5; + output PLLDATO4; + output PLLDATO3; + output PLLDATO2; + output PLLDATO1; + output PLLDATO0; + output PLLACK; + output DPHSRC; + output CLKINTFB; endmodule + +(* blackbox *) +module OSCH (...); + parameter NOM_FREQ = "2.08"; + input STDBY; + output OSC; + output SEDSTDBY; +endmodule + diff --git a/techlibs/lattice/cells_bb_xo3.v b/techlibs/lattice/cells_bb_xo3.v index 3363ed5710d..6e6b655c919 100644 --- a/techlibs/lattice/cells_bb_xo3.v +++ b/techlibs/lattice/cells_bb_xo3.v @@ -1,179 +1,153 @@ -(* blackbox *) -module DP8KC( - input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, - input ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0, - input CEA, OCEA, CLKA, WEA, RSTA, - input CSA2, CSA1, CSA0, - output DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, - - input DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0, - input ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, - input CEB, OCEB, CLKB, WEB, RSTB, - input CSB2, CSB1, CSB0, - output DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0 -); - parameter DATA_WIDTH_A = 9; - parameter DATA_WIDTH_B = 9; - - parameter REGMODE_A = "NOREG"; - parameter REGMODE_B = "NOREG"; - - parameter RESETMODE = "SYNC"; - parameter ASYNC_RESET_RELEASE = "SYNC"; - - parameter CSDECODE_A = "0b000"; - parameter CSDECODE_B = "0b000"; - - parameter WRITEMODE_A = "NORMAL"; - parameter WRITEMODE_B = "NORMAL"; +// Created by cells_xtra.py from Lattice models - parameter GSR = "ENABLED"; - parameter INIT_DATA = "STATIC"; - - parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; +(* blackbox *) (* keep *) +module GSR (...); + input GSR; endmodule -(* blackbox *) -module EHXPLLJ ( - input CLKI, CLKFB, - input PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, - input LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD, - input ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE, - input PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0, - input PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0, - output CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK, - output PLLDATO7, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK, - output DPHSRC, CLKINTFB -); - parameter CLKI_DIV = 1; - parameter CLKFB_DIV = 1; - parameter CLKOP_DIV = 8; - parameter CLKOS_DIV = 8; - parameter CLKOS2_DIV = 8; - parameter CLKOS3_DIV = 8; - parameter CLKOP_ENABLE = "ENABLED"; - parameter CLKOS_ENABLE = "ENABLED"; - parameter CLKOS2_ENABLE = "ENABLED"; - parameter CLKOS3_ENABLE = "ENABLED"; - parameter VCO_BYPASS_A0 = "DISABLED"; - parameter VCO_BYPASS_B0 = "DISABLED"; - parameter VCO_BYPASS_C0 = "DISABLED"; - parameter VCO_BYPASS_D0 = "DISABLED"; - parameter CLKOP_CPHASE = 0; - parameter CLKOS_CPHASE = 0; - parameter CLKOS2_CPHASE = 0; - parameter CLKOS3_CPHASE = 0; - parameter CLKOP_FPHASE = 0; - parameter CLKOS_FPHASE = 0; - parameter CLKOS2_FPHASE = 0; - parameter CLKOS3_FPHASE = 0; - parameter FEEDBK_PATH = "CLKOP"; - parameter FRACN_ENABLE = "DISABLED"; - parameter FRACN_DIV = 0; - parameter CLKOP_TRIM_POL = "RISING"; - parameter CLKOP_TRIM_DELAY = 0; - parameter CLKOS_TRIM_POL = "RISING"; - parameter CLKOS_TRIM_DELAY = 0; - parameter PLL_USE_WB = "DISABLED"; - parameter PREDIVIDER_MUXA1 = 0; - parameter PREDIVIDER_MUXB1 = 0; - parameter PREDIVIDER_MUXC1 = 0; - parameter PREDIVIDER_MUXD1 = 0; - parameter OUTDIVIDER_MUXA2 = "DIVA"; - parameter OUTDIVIDER_MUXB2 = "DIVB"; - parameter OUTDIVIDER_MUXC2 = "DIVC"; - parameter OUTDIVIDER_MUXD2 = "DIVD"; - parameter PLL_LOCK_MODE = 0; - parameter STDBY_ENABLE = "DISABLED"; - parameter DPHASE_SOURCE = "DISABLED"; - parameter PLLRST_ENA = "DISABLED"; - parameter MRST_ENA = "DISABLED"; - parameter DCRST_ENA = "DISABLED"; - parameter DDRST_ENA = "DISABLED"; - parameter INTFB_WAKE = "DISABLED"; -endmodule - -(* blackbox *) -module OSCH #( - parameter NOM_FREQ = "2.08" -) ( - input STDBY, - output OSC, - output SEDSTDBY -); -endmodule - -(* blackbox *) -module DCCA ( - input CLKI, - input CE, - output CLKO -); +(* blackbox *) (* keep *) +module SGSR (...); + input GSR; + input CLK; endmodule (* blackbox *) -module DCMA ( - input CLK0, - input CLK1, - input SEL, - output DCMOUT -); +module DP8KC (...); + parameter DATA_WIDTH_A = 9; + parameter DATA_WIDTH_B = 9; + parameter REGMODE_A = "NOREG"; + parameter REGMODE_B = "NOREG"; + parameter CSDECODE_A = "0b000"; + parameter CSDECODE_B = "0b000"; + parameter WRITEMODE_A = "NORMAL"; + parameter WRITEMODE_B = "NORMAL"; + parameter GSR = "ENABLED"; + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter INIT_DATA = "STATIC"; + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + input DIA8; + input DIA7; + input DIA6; + input DIA5; + input DIA4; + input DIA3; + input DIA2; + input DIA1; + input DIA0; + input ADA12; + input ADA11; + input ADA10; + input ADA9; + input ADA8; + input ADA7; + input ADA6; + input ADA5; + input ADA4; + input ADA3; + input ADA2; + input ADA1; + input ADA0; + input CEA; + input OCEA; + input CLKA; + input WEA; + input CSA2; + input CSA1; + input CSA0; + input RSTA; + input DIB8; + input DIB7; + input DIB6; + input DIB5; + input DIB4; + input DIB3; + input DIB2; + input DIB1; + input DIB0; + input ADB12; + input ADB11; + input ADB10; + input ADB9; + input ADB8; + input ADB7; + input ADB6; + input ADB5; + input ADB4; + input ADB3; + input ADB2; + input ADB1; + input ADB0; + input CEB; + input OCEB; + input CLKB; + input WEB; + input CSB2; + input CSB1; + input CSB0; + input RSTB; + output DOA8; + output DOA7; + output DOA6; + output DOA5; + output DOA4; + output DOA3; + output DOA2; + output DOA1; + output DOA0; + output DOB8; + output DOB7; + output DOB6; + output DOB5; + output DOB4; + output DOB3; + output DOB2; + output DOB1; + output DOB0; endmodule (* blackbox *) -module PDPW8KC ( - input DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, - input ADW8, ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, - input BE1, BE0, - input CEW, CLKW, CSW2, CSW1, CSW0, - input ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5, ADR4, ADR3, ADR2, ADR1, ADR0, - input CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, - output DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 -); +module PDPW8KC (...); parameter DATA_WIDTH_W = 18; parameter DATA_WIDTH_R = 9; - - parameter GSR = "ENABLED"; - parameter REGMODE = "NOREG"; - - parameter RESETMODE = "SYNC"; - parameter ASYNC_RESET_RELEASE = "SYNC"; - parameter CSDECODE_W = "0b000"; parameter CSDECODE_R = "0b000"; - + parameter GSR = "ENABLED"; + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter INIT_DATA = "STATIC"; parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; @@ -206,29 +180,90 @@ module PDPW8KC ( parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_DATA = "STATIC"; - + input DI17; + input DI16; + input DI15; + input DI14; + input DI13; + input DI12; + input DI11; + input DI10; + input DI9; + input DI8; + input DI7; + input DI6; + input DI5; + input DI4; + input DI3; + input DI2; + input DI1; + input DI0; + input ADW8; + input ADW7; + input ADW6; + input ADW5; + input ADW4; + input ADW3; + input ADW2; + input ADW1; + input ADW0; + input BE1; + input BE0; + input CEW; + input CLKW; + input CSW2; + input CSW1; + input CSW0; + input ADR12; + input ADR11; + input ADR10; + input ADR9; + input ADR8; + input ADR7; + input ADR6; + input ADR5; + input ADR4; + input ADR3; + input ADR2; + input ADR1; + input ADR0; + input CER; + input OCER; + input CLKR; + input CSR2; + input CSR1; + input CSR0; + input RST; + output DO17; + output DO16; + output DO15; + output DO14; + output DO13; + output DO12; + output DO11; + output DO10; + output DO9; + output DO8; + output DO7; + output DO6; + output DO5; + output DO4; + output DO3; + output DO2; + output DO1; + output DO0; endmodule (* blackbox *) -module SP8KC ( - input DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, - input AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0, - input CE, OCE, CLK, WE, CS2, CS1, CS0, RST, - output DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 -); +module SP8KC (...); parameter DATA_WIDTH = 9; - parameter GSR = "ENABLED"; - parameter REGMODE = "NOREG"; - - parameter RESETMODE = "SYNC"; - parameter ASYNC_RESET_RELEASE = "SYNC"; - parameter CSDECODE = "0b000"; - parameter WRITEMODE = "NORMAL"; - + parameter GSR = "ENABLED"; + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter INIT_DATA = "STATIC"; parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; @@ -261,33 +296,240 @@ module SP8KC ( parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_DATA = "STATIC"; + input DI8; + input DI7; + input DI6; + input DI5; + input DI4; + input DI3; + input DI2; + input DI1; + input DI0; + input AD12; + input AD11; + input AD10; + input AD9; + input AD8; + input AD7; + input AD6; + input AD5; + input AD4; + input AD3; + input AD2; + input AD1; + input AD0; + input CE; + input OCE; + input CLK; + input WE; + input CS2; + input CS1; + input CS0; + input RST; + output DO8; + output DO7; + output DO6; + output DO5; + output DO4; + output DO3; + output DO2; + output DO1; + output DO0; endmodule (* blackbox *) -module FIFO8KB ( - input DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, - input CSW0, CSW1, CSR0, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI, - output DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17, - input EF, AEF, AFF, FF -); +module FIFO8KB (...); parameter DATA_WIDTH_W = 18; parameter DATA_WIDTH_R = 18; - - parameter GSR = "DISABLED"; - parameter REGMODE = "NOREG"; - parameter RESETMODE = "ASYNC"; parameter ASYNC_RESET_RELEASE = "SYNC"; - parameter CSDECODE_W = "0b00"; parameter CSDECODE_R = "0b00"; - - parameter AEPOINTER = "0b00000000000000"; - parameter AEPOINTER1 = "0b00000000000000"; - parameter AFPOINTER = "0b00000000000000"; - parameter AFPOINTER1 = "0b00000000000000"; - parameter FULLPOINTER = "0b00000000000000"; + parameter AEPOINTER = "0b00000000000000"; + parameter AEPOINTER1 = "0b00000000000000"; + parameter AFPOINTER = "0b00000000000000"; + parameter AFPOINTER1 = "0b00000000000000"; + parameter FULLPOINTER = "0b00000000000000"; parameter FULLPOINTER1 = "0b00000000000000"; + parameter GSR = "DISABLED"; + input DI0; + input DI1; + input DI2; + input DI3; + input DI4; + input DI5; + input DI6; + input DI7; + input DI8; + input DI9; + input DI10; + input DI11; + input DI12; + input DI13; + input DI14; + input DI15; + input DI16; + input DI17; + input CSW0; + input CSW1; + input CSR0; + input CSR1; + input WE; + input RE; + input ORE; + input CLKW; + input CLKR; + input RST; + input RPRST; + input FULLI; + input EMPTYI; + output DO0; + output DO1; + output DO2; + output DO3; + output DO4; + output DO5; + output DO6; + output DO7; + output DO8; + output DO9; + output DO10; + output DO11; + output DO12; + output DO13; + output DO14; + output DO15; + output DO16; + output DO17; + output EF; + output AEF; + output AFF; + output FF; +endmodule + +(* blackbox *) +module DCMA (...); + input CLK0; + input CLK1; + input SEL; + output DCMOUT; +endmodule + +(* blackbox *) +module DCCA (...); + input CLKI; + input CE; + output CLKO; +endmodule + +(* blackbox *) +module EHXPLLJ (...); + parameter CLKI_DIV = 1; + parameter CLKFB_DIV = 1; + parameter CLKOP_DIV = 8; + parameter CLKOS_DIV = 8; + parameter CLKOS2_DIV = 8; + parameter CLKOS3_DIV = 8; + parameter CLKOP_ENABLE = "ENABLED"; + parameter CLKOS_ENABLE = "ENABLED"; + parameter CLKOS2_ENABLE = "ENABLED"; + parameter CLKOS3_ENABLE = "ENABLED"; + parameter VCO_BYPASS_A0 = "DISABLED"; + parameter VCO_BYPASS_B0 = "DISABLED"; + parameter VCO_BYPASS_C0 = "DISABLED"; + parameter VCO_BYPASS_D0 = "DISABLED"; + parameter CLKOP_CPHASE = 0; + parameter CLKOS_CPHASE = 0; + parameter CLKOS2_CPHASE = 0; + parameter CLKOS3_CPHASE = 0; + parameter CLKOP_FPHASE = 0; + parameter CLKOS_FPHASE = 0; + parameter CLKOS2_FPHASE = 0; + parameter CLKOS3_FPHASE = 0; + parameter FEEDBK_PATH = "CLKOP"; + parameter FRACN_ENABLE = "DISABLED"; + parameter FRACN_DIV = 0; + parameter CLKOP_TRIM_POL = "RISING"; + parameter CLKOP_TRIM_DELAY = 0; + parameter CLKOS_TRIM_POL = "RISING"; + parameter CLKOS_TRIM_DELAY = 0; + parameter PLL_USE_WB = "DISABLED"; + parameter PREDIVIDER_MUXA1 = 0; + parameter PREDIVIDER_MUXB1 = 0; + parameter PREDIVIDER_MUXC1 = 0; + parameter PREDIVIDER_MUXD1 = 0; + parameter OUTDIVIDER_MUXA2 = "DIVA"; + parameter OUTDIVIDER_MUXB2 = "DIVB"; + parameter OUTDIVIDER_MUXC2 = "DIVC"; + parameter OUTDIVIDER_MUXD2 = "DIVD"; + parameter PLL_LOCK_MODE = 0; + parameter STDBY_ENABLE = "DISABLED"; + parameter DPHASE_SOURCE = "DISABLED"; + parameter PLLRST_ENA = "DISABLED"; + parameter MRST_ENA = "DISABLED"; + parameter DCRST_ENA = "DISABLED"; + parameter DDRST_ENA = "DISABLED"; + parameter INTFB_WAKE = "DISABLED"; + input CLKI; + input CLKFB; + input PHASESEL1; + input PHASESEL0; + input PHASEDIR; + input PHASESTEP; + input LOADREG; + input STDBY; + input PLLWAKESYNC; + input RST; + input RESETM; + input RESETC; + input RESETD; + input ENCLKOP; + input ENCLKOS; + input ENCLKOS2; + input ENCLKOS3; + input PLLCLK; + input PLLRST; + input PLLSTB; + input PLLWE; + input PLLDATI7; + input PLLDATI6; + input PLLDATI5; + input PLLDATI4; + input PLLDATI3; + input PLLDATI2; + input PLLDATI1; + input PLLDATI0; + input PLLADDR4; + input PLLADDR3; + input PLLADDR2; + input PLLADDR1; + input PLLADDR0; + output CLKOP; + output CLKOS; + output CLKOS2; + output CLKOS3; + output LOCK; + output INTLOCK; + output REFCLK; + output PLLDATO7; + output PLLDATO6; + output PLLDATO5; + output PLLDATO4; + output PLLDATO3; + output PLLDATO2; + output PLLDATO1; + output PLLDATO0; + output PLLACK; + output DPHSRC; + output CLKINTFB; endmodule + +(* blackbox *) +module OSCH (...); + parameter NOM_FREQ = "2.08"; + input STDBY; + output OSC; + output SEDSTDBY; +endmodule + diff --git a/techlibs/lattice/cells_bb_xo3d.v b/techlibs/lattice/cells_bb_xo3d.v index 3363ed5710d..c957b00293e 100644 --- a/techlibs/lattice/cells_bb_xo3d.v +++ b/techlibs/lattice/cells_bb_xo3d.v @@ -1,179 +1,153 @@ -(* blackbox *) -module DP8KC( - input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, - input ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0, - input CEA, OCEA, CLKA, WEA, RSTA, - input CSA2, CSA1, CSA0, - output DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, - - input DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0, - input ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, - input CEB, OCEB, CLKB, WEB, RSTB, - input CSB2, CSB1, CSB0, - output DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0 -); - parameter DATA_WIDTH_A = 9; - parameter DATA_WIDTH_B = 9; - - parameter REGMODE_A = "NOREG"; - parameter REGMODE_B = "NOREG"; - - parameter RESETMODE = "SYNC"; - parameter ASYNC_RESET_RELEASE = "SYNC"; - - parameter CSDECODE_A = "0b000"; - parameter CSDECODE_B = "0b000"; - - parameter WRITEMODE_A = "NORMAL"; - parameter WRITEMODE_B = "NORMAL"; +// Created by cells_xtra.py from Lattice models - parameter GSR = "ENABLED"; - parameter INIT_DATA = "STATIC"; - - parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; +(* blackbox *) (* keep *) +module GSR (...); + input GSR; endmodule -(* blackbox *) -module EHXPLLJ ( - input CLKI, CLKFB, - input PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, - input LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD, - input ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE, - input PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0, - input PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0, - output CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK, - output PLLDATO7, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK, - output DPHSRC, CLKINTFB -); - parameter CLKI_DIV = 1; - parameter CLKFB_DIV = 1; - parameter CLKOP_DIV = 8; - parameter CLKOS_DIV = 8; - parameter CLKOS2_DIV = 8; - parameter CLKOS3_DIV = 8; - parameter CLKOP_ENABLE = "ENABLED"; - parameter CLKOS_ENABLE = "ENABLED"; - parameter CLKOS2_ENABLE = "ENABLED"; - parameter CLKOS3_ENABLE = "ENABLED"; - parameter VCO_BYPASS_A0 = "DISABLED"; - parameter VCO_BYPASS_B0 = "DISABLED"; - parameter VCO_BYPASS_C0 = "DISABLED"; - parameter VCO_BYPASS_D0 = "DISABLED"; - parameter CLKOP_CPHASE = 0; - parameter CLKOS_CPHASE = 0; - parameter CLKOS2_CPHASE = 0; - parameter CLKOS3_CPHASE = 0; - parameter CLKOP_FPHASE = 0; - parameter CLKOS_FPHASE = 0; - parameter CLKOS2_FPHASE = 0; - parameter CLKOS3_FPHASE = 0; - parameter FEEDBK_PATH = "CLKOP"; - parameter FRACN_ENABLE = "DISABLED"; - parameter FRACN_DIV = 0; - parameter CLKOP_TRIM_POL = "RISING"; - parameter CLKOP_TRIM_DELAY = 0; - parameter CLKOS_TRIM_POL = "RISING"; - parameter CLKOS_TRIM_DELAY = 0; - parameter PLL_USE_WB = "DISABLED"; - parameter PREDIVIDER_MUXA1 = 0; - parameter PREDIVIDER_MUXB1 = 0; - parameter PREDIVIDER_MUXC1 = 0; - parameter PREDIVIDER_MUXD1 = 0; - parameter OUTDIVIDER_MUXA2 = "DIVA"; - parameter OUTDIVIDER_MUXB2 = "DIVB"; - parameter OUTDIVIDER_MUXC2 = "DIVC"; - parameter OUTDIVIDER_MUXD2 = "DIVD"; - parameter PLL_LOCK_MODE = 0; - parameter STDBY_ENABLE = "DISABLED"; - parameter DPHASE_SOURCE = "DISABLED"; - parameter PLLRST_ENA = "DISABLED"; - parameter MRST_ENA = "DISABLED"; - parameter DCRST_ENA = "DISABLED"; - parameter DDRST_ENA = "DISABLED"; - parameter INTFB_WAKE = "DISABLED"; -endmodule - -(* blackbox *) -module OSCH #( - parameter NOM_FREQ = "2.08" -) ( - input STDBY, - output OSC, - output SEDSTDBY -); -endmodule - -(* blackbox *) -module DCCA ( - input CLKI, - input CE, - output CLKO -); +(* blackbox *) (* keep *) +module SGSR (...); + input GSR; + input CLK; endmodule (* blackbox *) -module DCMA ( - input CLK0, - input CLK1, - input SEL, - output DCMOUT -); +module DP8KC (...); + parameter DATA_WIDTH_A = 9; + parameter DATA_WIDTH_B = 9; + parameter REGMODE_A = "NOREG"; + parameter REGMODE_B = "NOREG"; + parameter CSDECODE_A = "0b000"; + parameter CSDECODE_B = "0b000"; + parameter WRITEMODE_A = "NORMAL"; + parameter WRITEMODE_B = "NORMAL"; + parameter GSR = "ENABLED"; + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter INIT_DATA = "STATIC"; + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + input DIA8; + input DIA7; + input DIA6; + input DIA5; + input DIA4; + input DIA3; + input DIA2; + input DIA1; + input DIA0; + input ADA12; + input ADA11; + input ADA10; + input ADA9; + input ADA8; + input ADA7; + input ADA6; + input ADA5; + input ADA4; + input ADA3; + input ADA2; + input ADA1; + input ADA0; + input CEA; + input OCEA; + input CLKA; + input WEA; + input CSA2; + input CSA1; + input CSA0; + input RSTA; + input DIB8; + input DIB7; + input DIB6; + input DIB5; + input DIB4; + input DIB3; + input DIB2; + input DIB1; + input DIB0; + input ADB12; + input ADB11; + input ADB10; + input ADB9; + input ADB8; + input ADB7; + input ADB6; + input ADB5; + input ADB4; + input ADB3; + input ADB2; + input ADB1; + input ADB0; + input CEB; + input OCEB; + input CLKB; + input WEB; + input CSB2; + input CSB1; + input CSB0; + input RSTB; + output DOA8; + output DOA7; + output DOA6; + output DOA5; + output DOA4; + output DOA3; + output DOA2; + output DOA1; + output DOA0; + output DOB8; + output DOB7; + output DOB6; + output DOB5; + output DOB4; + output DOB3; + output DOB2; + output DOB1; + output DOB0; endmodule (* blackbox *) -module PDPW8KC ( - input DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, - input ADW8, ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, - input BE1, BE0, - input CEW, CLKW, CSW2, CSW1, CSW0, - input ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5, ADR4, ADR3, ADR2, ADR1, ADR0, - input CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, - output DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 -); +module PDPW8KC (...); parameter DATA_WIDTH_W = 18; parameter DATA_WIDTH_R = 9; - - parameter GSR = "ENABLED"; - parameter REGMODE = "NOREG"; - - parameter RESETMODE = "SYNC"; - parameter ASYNC_RESET_RELEASE = "SYNC"; - parameter CSDECODE_W = "0b000"; parameter CSDECODE_R = "0b000"; - + parameter GSR = "ENABLED"; + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter INIT_DATA = "STATIC"; parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; @@ -206,29 +180,90 @@ module PDPW8KC ( parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_DATA = "STATIC"; - + input DI17; + input DI16; + input DI15; + input DI14; + input DI13; + input DI12; + input DI11; + input DI10; + input DI9; + input DI8; + input DI7; + input DI6; + input DI5; + input DI4; + input DI3; + input DI2; + input DI1; + input DI0; + input ADW8; + input ADW7; + input ADW6; + input ADW5; + input ADW4; + input ADW3; + input ADW2; + input ADW1; + input ADW0; + input BE1; + input BE0; + input CEW; + input CLKW; + input CSW2; + input CSW1; + input CSW0; + input ADR12; + input ADR11; + input ADR10; + input ADR9; + input ADR8; + input ADR7; + input ADR6; + input ADR5; + input ADR4; + input ADR3; + input ADR2; + input ADR1; + input ADR0; + input CER; + input OCER; + input CLKR; + input CSR2; + input CSR1; + input CSR0; + input RST; + output DO17; + output DO16; + output DO15; + output DO14; + output DO13; + output DO12; + output DO11; + output DO10; + output DO9; + output DO8; + output DO7; + output DO6; + output DO5; + output DO4; + output DO3; + output DO2; + output DO1; + output DO0; endmodule (* blackbox *) -module SP8KC ( - input DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, - input AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0, - input CE, OCE, CLK, WE, CS2, CS1, CS0, RST, - output DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 -); +module SP8KC (...); parameter DATA_WIDTH = 9; - parameter GSR = "ENABLED"; - parameter REGMODE = "NOREG"; - - parameter RESETMODE = "SYNC"; - parameter ASYNC_RESET_RELEASE = "SYNC"; - parameter CSDECODE = "0b000"; - parameter WRITEMODE = "NORMAL"; - + parameter GSR = "ENABLED"; + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter INIT_DATA = "STATIC"; parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; @@ -261,33 +296,241 @@ module SP8KC ( parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_DATA = "STATIC"; + input DI8; + input DI7; + input DI6; + input DI5; + input DI4; + input DI3; + input DI2; + input DI1; + input DI0; + input AD12; + input AD11; + input AD10; + input AD9; + input AD8; + input AD7; + input AD6; + input AD5; + input AD4; + input AD3; + input AD2; + input AD1; + input AD0; + input CE; + input OCE; + input CLK; + input WE; + input CS2; + input CS1; + input CS0; + input RST; + output DO8; + output DO7; + output DO6; + output DO5; + output DO4; + output DO3; + output DO2; + output DO1; + output DO0; endmodule (* blackbox *) -module FIFO8KB ( - input DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, - input CSW0, CSW1, CSR0, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI, - output DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17, - input EF, AEF, AFF, FF -); +module FIFO8KB (...); parameter DATA_WIDTH_W = 18; parameter DATA_WIDTH_R = 18; - - parameter GSR = "DISABLED"; - parameter REGMODE = "NOREG"; - parameter RESETMODE = "ASYNC"; parameter ASYNC_RESET_RELEASE = "SYNC"; - parameter CSDECODE_W = "0b00"; parameter CSDECODE_R = "0b00"; - - parameter AEPOINTER = "0b00000000000000"; - parameter AEPOINTER1 = "0b00000000000000"; - parameter AFPOINTER = "0b00000000000000"; - parameter AFPOINTER1 = "0b00000000000000"; - parameter FULLPOINTER = "0b00000000000000"; + parameter AEPOINTER = "0b00000000000000"; + parameter AEPOINTER1 = "0b00000000000000"; + parameter AFPOINTER = "0b00000000000000"; + parameter AFPOINTER1 = "0b00000000000000"; + parameter FULLPOINTER = "0b00000000000000"; parameter FULLPOINTER1 = "0b00000000000000"; + parameter GSR = "DISABLED"; + input DI0; + input DI1; + input DI2; + input DI3; + input DI4; + input DI5; + input DI6; + input DI7; + input DI8; + input DI9; + input DI10; + input DI11; + input DI12; + input DI13; + input DI14; + input DI15; + input DI16; + input DI17; + input CSW0; + input CSW1; + input CSR0; + input CSR1; + input WE; + input RE; + input ORE; + input CLKW; + input CLKR; + input RST; + input RPRST; + input FULLI; + input EMPTYI; + output DO0; + output DO1; + output DO2; + output DO3; + output DO4; + output DO5; + output DO6; + output DO7; + output DO8; + output DO9; + output DO10; + output DO11; + output DO12; + output DO13; + output DO14; + output DO15; + output DO16; + output DO17; + output EF; + output AEF; + output AFF; + output FF; +endmodule + +(* blackbox *) +module DCMA (...); + input CLK0; + input CLK1; + input SEL; + output DCMOUT; +endmodule + +(* blackbox *) +module DCCA (...); + input CLKI; + input CE; + output CLKO; +endmodule + +(* blackbox *) +module EHXPLLJ (...); + parameter CLKI_DIV = 1; + parameter CLKFB_DIV = 1; + parameter CLKOP_DIV = 8; + parameter CLKOS_DIV = 8; + parameter CLKOS2_DIV = 8; + parameter CLKOS3_DIV = 8; + parameter CLKOP_ENABLE = "ENABLED"; + parameter CLKOS_ENABLE = "ENABLED"; + parameter CLKOS2_ENABLE = "ENABLED"; + parameter CLKOS3_ENABLE = "ENABLED"; + parameter VCO_BYPASS_A0 = "DISABLED"; + parameter VCO_BYPASS_B0 = "DISABLED"; + parameter VCO_BYPASS_C0 = "DISABLED"; + parameter VCO_BYPASS_D0 = "DISABLED"; + parameter CLKOP_CPHASE = 0; + parameter CLKOS_CPHASE = 0; + parameter CLKOS2_CPHASE = 0; + parameter CLKOS3_CPHASE = 0; + parameter CLKOP_FPHASE = 0; + parameter CLKOS_FPHASE = 0; + parameter CLKOS2_FPHASE = 0; + parameter CLKOS3_FPHASE = 0; + parameter FEEDBK_PATH = "CLKOP"; + parameter FRACN_ENABLE = "DISABLED"; + parameter FRACN_DIV = 0; + parameter CLKOP_TRIM_POL = "RISING"; + parameter CLKOP_TRIM_DELAY = 0; + parameter CLKOS_TRIM_POL = "RISING"; + parameter CLKOS_TRIM_DELAY = 0; + parameter PLL_USE_WB = "DISABLED"; + parameter PREDIVIDER_MUXA1 = 0; + parameter PREDIVIDER_MUXB1 = 0; + parameter PREDIVIDER_MUXC1 = 0; + parameter PREDIVIDER_MUXD1 = 0; + parameter OUTDIVIDER_MUXA2 = "DIVA"; + parameter OUTDIVIDER_MUXB2 = "DIVB"; + parameter OUTDIVIDER_MUXC2 = "DIVC"; + parameter OUTDIVIDER_MUXD2 = "DIVD"; + parameter PLL_LOCK_MODE = 0; + parameter STDBY_ENABLE = "DISABLED"; + parameter DPHASE_SOURCE = "DISABLED"; + parameter PLLRST_ENA = "DISABLED"; + parameter MRST_ENA = "DISABLED"; + parameter DCRST_ENA = "DISABLED"; + parameter DDRST_ENA = "DISABLED"; + parameter INTFB_WAKE = "DISABLED"; + input CLKI; + input CLKFB; + input PHASESEL1; + input PHASESEL0; + input PHASEDIR; + input PHASESTEP; + input LOADREG; + input STDBY; + input PLLWAKESYNC; + input RST; + input RESETM; + input RESETC; + input RESETD; + input ENCLKOP; + input ENCLKOS; + input ENCLKOS2; + input ENCLKOS3; + input PLLCLK; + input PLLRST; + input PLLSTB; + input PLLWE; + input PLLDATI7; + input PLLDATI6; + input PLLDATI5; + input PLLDATI4; + input PLLDATI3; + input PLLDATI2; + input PLLDATI1; + input PLLDATI0; + input PLLADDR4; + input PLLADDR3; + input PLLADDR2; + input PLLADDR1; + input PLLADDR0; + output CLKOP; + output CLKOS; + output CLKOS2; + output CLKOS3; + output LOCK; + output INTLOCK; + output REFCLK; + output PLLDATO7; + output PLLDATO6; + output PLLDATO5; + output PLLDATO4; + output PLLDATO3; + output PLLDATO2; + output PLLDATO1; + output PLLDATO0; + output PLLACK; + output DPHSRC; + output CLKINTFB; endmodule + +(* blackbox *) +module OSCJ (...); + parameter NOM_FREQ = "2.08"; + input STDBY; + output OSC; + output SEDSTDBY; + output OSCESB; +endmodule + diff --git a/techlibs/lattice/cells_xtra.py b/techlibs/lattice/cells_xtra.py new file mode 100644 index 00000000000..f2dd1f29749 --- /dev/null +++ b/techlibs/lattice/cells_xtra.py @@ -0,0 +1,854 @@ +#!/usr/bin/env python3 + +# Based on Xilinx cells_xtra.py; modified for Lattice's structure + +from argparse import ArgumentParser +from io import StringIO +from enum import Enum, auto +import os.path +import sys +import re + + +class Cell: + def __init__(self, name, keep=False, port_attrs={}): + self.name = name + self.keep = keep + self.port_attrs = port_attrs + self.found = False + +class State(Enum): + OUTSIDE = auto() + IN_MODULE = auto() + IN_OTHER_MODULE = auto() + IN_FUNCTION = auto() + IN_TASK = auto() + +devices = [ + ("cells_bb_ecp5.v", "ecp5u", [ + #Cell("AND2"), + #Cell("AND3"), + #Cell("AND4"), + #Cell("AND5"), + #Cell("BB"), + #Cell("BBPD"), + #Cell("BBPU"), + #Cell("CCU2C"), + #Cell("FD1P3AX"), + #Cell("FD1P3AY"), + #Cell("FD1P3BX"), + #Cell("FD1P3DX"), + #Cell("FD1P3IX"), + #Cell("FD1P3JX"), + #Cell("FD1S3AX"), + #Cell("FD1S3AY"), + #Cell("FD1S3BX"), + #Cell("FD1S3DX"), + #Cell("FD1S3IX"), + #Cell("FD1S3JX"), + #Cell("FL1P3AY"), + #Cell("FL1P3AZ"), + #Cell("FL1P3BX"), + #Cell("FL1P3DX"), + #Cell("FL1P3IY"), + #Cell("FL1P3JY"), + #Cell("FL1S3AX"), + #Cell("FL1S3AY"), + Cell("GSR", True), + #Cell("IB"), + #Cell("IBPD"), + #Cell("IBPU"), + #Cell("IFS1P3BX"), + #Cell("IFS1P3DX"), + #Cell("IFS1P3IX"), + #Cell("IFS1P3JX"), + #Cell("IFS1S1B"), + #Cell("IFS1S1D"), + #Cell("IFS1S1I"), + #Cell("IFS1S1J"), + #Cell("ILVDS"), + #Cell("INV"), + #Cell("L6MUX21"), + #Cell("LUT4"), + #Cell("LUT5"), + #Cell("LUT6"), + #Cell("LUT7"), + #Cell("LUT8"), + #Cell("MUX161"), + #Cell("MUX21"), + #Cell("MUX321"), + #Cell("MUX41"), + #Cell("MUX81"), + #Cell("ND2"), + #Cell("ND3"), + #Cell("ND4"), + #Cell("ND5"), + #Cell("NR2"), + #Cell("NR3"), + #Cell("NR4"), + #Cell("NR5"), + #Cell("OB"), + #Cell("OBCO"), + #Cell("OBZ"), + #Cell("OBZPU"), + #Cell("OFS1P3BX"), + #Cell("OFS1P3DX"), + #Cell("OFS1P3IX"), + #Cell("OFS1P3JX"), + #Cell("OLVDS"), + #Cell("OR2"), + #Cell("OR3"), + #Cell("OR4"), + #Cell("OR5"), + #Cell("PFUMX"), + Cell("PUR"), + #Cell("ROM128X1A"), + #Cell("ROM16X1A"), + #Cell("ROM256X1A"), + #Cell("ROM32X1A"), + #Cell("ROM64X1A"), + Cell("SGSR", True), + #Cell("VHI"), + #Cell("VLO"), + #Cell("XNOR2"), + #Cell("XNOR3"), + #Cell("XNOR4"), + #Cell("XNOR5"), + #Cell("XOR11"), + #Cell("XOR2"), + #Cell("XOR21"), + #Cell("XOR3"), + #Cell("XOR4"), + #Cell("XOR5"), + Cell("DP16KD"), + Cell("PDPW16KD"), + #Cell("DPR16X4C"), + #Cell("SPR16X4C"), + #Cell("LVDSOB"), + #Cell("IMIPI"), + #Cell("MULT9X9C"), + #Cell("MULT9X9D"), + #Cell("MULT18X18C"), + Cell("MULT18X18D"), + #Cell("ALU24A"), + #Cell("ALU54A"), + #Cell("ALU24B"), + Cell("ALU54B"), + #Cell("PRADD9A"), + #Cell("PRADD18A"), + #Cell("BCINRD"), + #Cell("BCLVDSOB"), + #Cell("INRDB"), + Cell("CLKDIVF"), + Cell("PCSCLKDIV"), + Cell("DCSC"), + Cell("DCCA"), + Cell("ECLKSYNCB"), + Cell("ECLKBRIDGECS"), + #Cell("PLLREFCS"), + Cell("DELAYF"), + Cell("DELAYG"), + #Cell("START"), + Cell("USRMCLK", True), + Cell("DQSBUFM"), + Cell("DDRDLLA"), + Cell("DLLDELD"), + Cell("IDDRX1F"), + Cell("IDDRX2F"), + Cell("IDDR71B"), + Cell("IDDRX2DQA"), + Cell("ODDRX1F"), + Cell("ODDRX2F"), + Cell("ODDR71B"), + Cell("OSHX2A"), + Cell("TSHX2DQA"), + Cell("TSHX2DQSA"), + Cell("ODDRX2DQA"), + Cell("ODDRX2DQSB"), + Cell("EHXPLLL"), + Cell("DTR"), + Cell("OSCG"), + Cell("EXTREFB"), + Cell("JTAGG", True, port_attrs={'TCK': ['iopad_external_pin'], 'TMS': ['iopad_external_pin'], 'TDO': ['iopad_external_pin'], 'TDI': ['iopad_external_pin']}), + #Cell("SEDGA"), + Cell("DCUA", True, port_attrs={'CH0_HDINP': ['iopad_external_pin'], 'CH1_HDINP': ['iopad_external_pin'], 'CH0_HDINN': ['iopad_external_pin'], 'CH1_HDINN': ['iopad_external_pin']}), + ]), + ("cells_bb_xo2.v", "machxo2", [ + #Cell("AGEB2"), + #Cell("ALEB2"), + #Cell("AND2"), + #Cell("AND3"), + #Cell("AND4"), + #Cell("AND5"), + #Cell("ANEB2"), + #Cell("BB"), + #Cell("BBPD"), + #Cell("BBPU"), + #Cell("BBW"), + #Cell("CB2"), + #Cell("CD2"), + #Cell("CU2"), + #Cell("FADD2B"), + #Cell("FADSU2"), + #Cell("FD1P3AX"), + #Cell("FD1P3AY"), + #Cell("FD1P3BX"), + #Cell("FD1P3DX"), + #Cell("FD1P3IX"), + #Cell("FD1P3JX"), + #Cell("FD1S1A"), + #Cell("FD1S1AY"), + #Cell("FD1S1B"), + #Cell("FD1S1D"), + #Cell("FD1S1I"), + #Cell("FD1S1J"), + #Cell("FD1S3AX"), + #Cell("FD1S3AY"), + #Cell("FD1S3BX"), + #Cell("FD1S3DX"), + #Cell("FD1S3IX"), + #Cell("FD1S3JX"), + #Cell("FL1P3AY"), + #Cell("FL1P3AZ"), + #Cell("FL1P3BX"), + #Cell("FL1P3DX"), + #Cell("FL1P3IY"), + #Cell("FL1P3JY"), + #Cell("FL1S1A"), + #Cell("FL1S1AY"), + #Cell("FL1S1B"), + #Cell("FL1S1D"), + #Cell("FL1S1I"), + #Cell("FL1S1J"), + #Cell("FL1S3AX"), + #Cell("FL1S3AY"), + #Cell("FSUB2B"), + Cell("GSR", True), + #Cell("IB"), + #Cell("IBPD"), + #Cell("IBPU"), + #Cell("IFS1P3BX"), + #Cell("IFS1P3DX"), + #Cell("IFS1P3IX"), + #Cell("IFS1P3JX"), + #Cell("ILVDS"), + #Cell("INV"), + #Cell("L6MUX21"), + #Cell("LB2P3AX"), + #Cell("LB2P3AY"), + #Cell("LB2P3BX"), + #Cell("LB2P3DX"), + #Cell("LB2P3IX"), + #Cell("LB2P3JX"), + #Cell("LD2P3AX"), + #Cell("LD2P3AY"), + #Cell("LD2P3BX"), + #Cell("LD2P3DX"), + #Cell("LD2P3IX"), + #Cell("LD2P3JX"), + #Cell("LU2P3AX"), + #Cell("LU2P3AY"), + #Cell("LU2P3BX"), + #Cell("LU2P3DX"), + #Cell("LU2P3IX"), + #Cell("LU2P3JX"), + #Cell("MULT2"), + #Cell("MUX161"), + #Cell("MUX21"), + #Cell("MUX321"), + #Cell("MUX41"), + #Cell("MUX81"), + #Cell("ND2"), + #Cell("ND3"), + #Cell("ND4"), + #Cell("ND5"), + #Cell("NR2"), + #Cell("NR3"), + #Cell("NR4"), + #Cell("NR5"), + #Cell("OB"), + #Cell("OBCO"), + #Cell("OBZ"), + #Cell("OBZPU"), + #Cell("OFS1P3BX"), + #Cell("OFS1P3DX"), + #Cell("OFS1P3IX"), + #Cell("OFS1P3JX"), + #Cell("OLVDS"), + #Cell("OR2"), + #Cell("OR3"), + #Cell("OR4"), + #Cell("OR5"), + #Cell("LUT4"), + #Cell("LUT5"), + #Cell("LUT6"), + #Cell("LUT7"), + #Cell("LUT8"), + #Cell("PFUMX"), + #Cell("PUR"), + #Cell("ROM128X1A"), + #Cell("ROM16X1A"), + #Cell("ROM256X1A"), + #Cell("ROM32X1A"), + #Cell("ROM64X1A"), + #Cell("CCU2D"), + #Cell("VHI"), + #Cell("VLO"), + #Cell("XNOR2"), + #Cell("XNOR3"), + #Cell("XNOR4"), + #Cell("XNOR5"), + #Cell("XOR11"), + #Cell("XOR2"), + #Cell("XOR21"), + #Cell("XOR3"), + #Cell("XOR4"), + #Cell("XOR5"), + #Cell("IFS1S1B"), + #Cell("IFS1S1D"), + #Cell("IFS1S1I"), + #Cell("IFS1S1J"), + #Cell("DPR16X4C"), + #Cell("SPR16X4C"), + Cell("SGSR", True), + Cell("DP8KC"), + Cell("PDPW8KC"), + Cell("SP8KC"), + Cell("FIFO8KB"), + #Cell("CLKDIVC"), + Cell("DCMA"), + #Cell("ECLKSYNCA"), + #Cell("ECLKBRIDGECS"), + Cell("DCCA"), + #Cell("JTAGF"), + #Cell("START"), + #Cell("SEDFA"), + #Cell("SEDFB"), + #Cell("IDDRXE"), + #Cell("IDDRX2E"), + #Cell("IDDRX4B"), + #Cell("IDDRDQSX1A"), + #Cell("IDDRX71A"), + #Cell("ODDRXE"), + #Cell("ODDRX2E"), + #Cell("ODDRX4B"), + #Cell("ODDRDQSX1A"), + #Cell("ODDRX71A"), + #Cell("TDDRA"), + #Cell("DQSBUFH"), + #Cell("DQSDLLC"), + #Cell("DELAYE"), + #Cell("DELAYD"), + #Cell("DLLDELC"), + #Cell("CLKFBBUFA"), + #Cell("PCNTR"), + #Cell("BCINRD"), + #Cell("BCLVDSO"), + #Cell("INRDB"), + #Cell("LVDSOB"), + #Cell("PG"), + Cell("EHXPLLJ"), + #Cell("PLLREFCS"), + Cell("OSCH"), + #Cell("EFB"), + #Cell("TSALL"), + ]), + ("cells_bb_xo3.v", "machxo3lf", [ + #Cell("AGEB2"), + #Cell("ALEB2"), + #Cell("AND2"), + #Cell("AND3"), + #Cell("AND4"), + #Cell("AND5"), + #Cell("ANEB2"), + #Cell("BB"), + #Cell("BBPD"), + #Cell("BBPU"), + #Cell("BBW"), + #Cell("CB2"), + #Cell("CD2"), + #Cell("CU2"), + #Cell("FADD2B"), + #Cell("FADSU2"), + #Cell("FD1P3AX"), + #Cell("FD1P3AY"), + #Cell("FD1P3BX"), + #Cell("FD1P3DX"), + #Cell("FD1P3IX"), + #Cell("FD1P3JX"), + #Cell("FD1S1A"), + #Cell("FD1S1AY"), + #Cell("FD1S1B"), + #Cell("FD1S1D"), + #Cell("FD1S1I"), + #Cell("FD1S1J"), + #Cell("FD1S3AX"), + #Cell("FD1S3AY"), + #Cell("FD1S3BX"), + #Cell("FD1S3DX"), + #Cell("FD1S3IX"), + #Cell("FD1S3JX"), + #Cell("FL1P3AY"), + #Cell("FL1P3AZ"), + #Cell("FL1P3BX"), + #Cell("FL1P3DX"), + #Cell("FL1P3IY"), + #Cell("FL1P3JY"), + #Cell("FL1S1A"), + #Cell("FL1S1AY"), + #Cell("FL1S1B"), + #Cell("FL1S1D"), + #Cell("FL1S1I"), + #Cell("FL1S1J"), + #Cell("FL1S3AX"), + #Cell("FL1S3AY"), + #Cell("FSUB2B"), + Cell("GSR", True), + #Cell("IB"), + #Cell("IBPD"), + #Cell("IBPU"), + #Cell("IFS1P3BX"), + #Cell("IFS1P3DX"), + #Cell("IFS1P3IX"), + #Cell("IFS1P3JX"), + #Cell("ILVDS"), + #Cell("INV"), + #Cell("L6MUX21"), + #Cell("LB2P3AX"), + #Cell("LB2P3AY"), + #Cell("LB2P3BX"), + #Cell("LB2P3DX"), + #Cell("LB2P3IX"), + #Cell("LB2P3JX"), + #Cell("LD2P3AX"), + #Cell("LD2P3AY"), + #Cell("LD2P3BX"), + #Cell("LD2P3DX"), + #Cell("LD2P3IX"), + #Cell("LD2P3JX"), + #Cell("LU2P3AX"), + #Cell("LU2P3AY"), + #Cell("LU2P3BX"), + #Cell("LU2P3DX"), + #Cell("LU2P3IX"), + #Cell("LU2P3JX"), + #Cell("MULT2"), + #Cell("MUX161"), + #Cell("MUX21"), + #Cell("MUX321"), + #Cell("MUX41"), + #Cell("MUX81"), + #Cell("ND2"), + #Cell("ND3"), + #Cell("ND4"), + #Cell("ND5"), + #Cell("NR2"), + #Cell("NR3"), + #Cell("NR4"), + #Cell("NR5"), + #Cell("OB"), + #Cell("OBCO"), + #Cell("OBZ"), + #Cell("OBZPU"), + #Cell("OFS1P3BX"), + #Cell("OFS1P3DX"), + #Cell("OFS1P3IX"), + #Cell("OFS1P3JX"), + #Cell("OLVDS"), + #Cell("OR2"), + #Cell("OR3"), + #Cell("OR4"), + #Cell("OR5"), + #Cell("LUT4"), + #Cell("LUT5"), + #Cell("LUT6"), + #Cell("LUT7"), + #Cell("LUT8"), + #Cell("PFUMX"), + #Cell("PUR"), + #Cell("ROM128X1A"), + #Cell("ROM16X1A"), + #Cell("ROM256X1A"), + #Cell("ROM32X1A"), + #Cell("ROM64X1A"), + #Cell("CCU2D"), + #Cell("VHI"), + #Cell("VLO"), + #Cell("XNOR2"), + #Cell("XNOR3"), + #Cell("XNOR4"), + #Cell("XNOR5"), + #Cell("XOR11"), + #Cell("XOR2"), + #Cell("XOR21"), + #Cell("XOR3"), + #Cell("XOR4"), + #Cell("XOR5"), + #Cell("IFS1S1B"), + #Cell("IFS1S1D"), + #Cell("IFS1S1I"), + #Cell("IFS1S1J"), + #Cell("DPR16X4C"), + #Cell("SPR16X4C"), + Cell("SGSR", True), + Cell("DP8KC"), + Cell("PDPW8KC"), + Cell("SP8KC"), + Cell("FIFO8KB"), + #Cell("CLKDIVC"), + Cell("DCMA"), + #Cell("ECLKSYNCA"), + #Cell("ECLKBRIDGECS"), + Cell("DCCA"), + #Cell("JTAGF"), + #Cell("START"), + #Cell("SEDFA"), + #Cell("SEDFB"), + #Cell("IDDRXE"), + #Cell("IDDRX2E"), + #Cell("IDDRX4B"), + #Cell("IDDRX71A"), + #Cell("ODDRXE"), + #Cell("ODDRX2E"), + #Cell("ODDRX4B"), + #Cell("ODDRX71A"), + #Cell("DQSDLLC"), + #Cell("DELAYE"), + #Cell("DELAYD"), + #Cell("DLLDELC"), + #Cell("CLKFBBUFA"), + #Cell("PCNTR"), + #Cell("BCINRD"), + #Cell("BCLVDSO"), + #Cell("INRDB"), + #Cell("LVDSOB"), + #Cell("PG"), + Cell("EHXPLLJ"), + #Cell("PLLREFCS"), + Cell("OSCH"), + #Cell("EFB"), + #Cell("TSALL"), + ]), + ("cells_bb_xo3d.v", "machxo3d", [ + #Cell("AGEB2"), + #Cell("ALEB2"), + #Cell("AND2"), + #Cell("AND3"), + #Cell("AND4"), + #Cell("AND5"), + #Cell("ANEB2"), + #Cell("BB"), + #Cell("BBPD"), + #Cell("BBPU"), + #Cell("BBI3C"), + #Cell("BBW"), + #Cell("CB2"), + #Cell("CD2"), + #Cell("CU2"), + #Cell("FADD2B"), + #Cell("FADSU2"), + #Cell("FD1P3AX"), + #Cell("FD1P3AY"), + #Cell("FD1P3BX"), + #Cell("FD1P3DX"), + #Cell("FD1P3IX"), + #Cell("FD1P3JX"), + #Cell("FD1S1A"), + #Cell("FD1S1AY"), + #Cell("FD1S1B"), + #Cell("FD1S1D"), + #Cell("FD1S1I"), + #Cell("FD1S1J"), + #Cell("FD1S3AX"), + #Cell("FD1S3AY"), + #Cell("FD1S3BX"), + #Cell("FD1S3DX"), + #Cell("FD1S3IX"), + #Cell("FD1S3JX"), + #Cell("FL1P3AY"), + #Cell("FL1P3AZ"), + #Cell("FL1P3BX"), + #Cell("FL1P3DX"), + #Cell("FL1P3IY"), + #Cell("FL1P3JY"), + #Cell("FL1S1A"), + #Cell("FL1S1AY"), + #Cell("FL1S1B"), + #Cell("FL1S1D"), + #Cell("FL1S1I"), + #Cell("FL1S1J"), + #Cell("FL1S3AX"), + #Cell("FL1S3AY"), + #Cell("FSUB2B"), + Cell("GSR", True), + #Cell("IB"), + #Cell("IBPD"), + #Cell("IBPU"), + #Cell("IFS1P3BX"), + #Cell("IFS1P3DX"), + #Cell("IFS1P3IX"), + #Cell("IFS1P3JX"), + #Cell("ILVDS"), + #Cell("INV"), + #Cell("L6MUX21"), + #Cell("LB2P3AX"), + #Cell("LB2P3AY"), + #Cell("LB2P3BX"), + #Cell("LB2P3DX"), + #Cell("LB2P3IX"), + #Cell("LB2P3JX"), + #Cell("LD2P3AX"), + #Cell("LD2P3AY"), + #Cell("LD2P3BX"), + #Cell("LD2P3DX"), + #Cell("LD2P3IX"), + #Cell("LD2P3JX"), + #Cell("LU2P3AX"), + #Cell("LU2P3AY"), + #Cell("LU2P3BX"), + #Cell("LU2P3DX"), + #Cell("LU2P3IX"), + #Cell("LU2P3JX"), + #Cell("MULT2"), + #Cell("MUX161"), + #Cell("MUX21"), + #Cell("MUX321"), + #Cell("MUX41"), + #Cell("MUX81"), + #Cell("ND2"), + #Cell("ND3"), + #Cell("ND4"), + #Cell("ND5"), + #Cell("NR2"), + #Cell("NR3"), + #Cell("NR4"), + #Cell("NR5"), + #Cell("OB"), + #Cell("OBCO"), + #Cell("OBZ"), + #Cell("OBZPU"), + #Cell("OFS1P3BX"), + #Cell("OFS1P3DX"), + #Cell("OFS1P3IX"), + #Cell("OFS1P3JX"), + #Cell("OLVDS"), + #Cell("OR2"), + #Cell("OR3"), + #Cell("OR4"), + #Cell("OR5"), + #Cell("LUT4"), + #Cell("LUT5"), + #Cell("LUT6"), + #Cell("LUT7"), + #Cell("LUT8"), + #Cell("PFUMX"), + #Cell("PUR"), + #Cell("ROM128X1A"), + #Cell("ROM16X1A"), + #Cell("ROM256X1A"), + #Cell("ROM32X1A"), + #Cell("ROM64X1A"), + #Cell("CCU2D"), + #Cell("VHI"), + #Cell("VLO"), + #Cell("XNOR2"), + #Cell("XNOR3"), + #Cell("XNOR4"), + #Cell("XNOR5"), + #Cell("XOR11"), + #Cell("XOR2"), + #Cell("XOR21"), + #Cell("XOR3"), + #Cell("XOR4"), + #Cell("XOR5"), + #Cell("IFS1S1B"), + #Cell("IFS1S1D"), + #Cell("IFS1S1I"), + #Cell("IFS1S1J"), + #Cell("DPR16X4C"), + #Cell("SPR16X4C"), + Cell("SGSR", True), + Cell("DP8KC"), + Cell("PDPW8KC"), + Cell("SP8KC"), + Cell("FIFO8KB"), + #Cell("CLKDIVC"), + Cell("DCMA"), + #Cell("ECLKSYNCA"), + #Cell("ECLKBRIDGECS"), + Cell("DCCA"), + #Cell("JTAGF"), + #Cell("START"), + #Cell("SEDFA"), + #Cell("SEDFB"), + #Cell("IDDRXE"), + #Cell("IDDRX2E"), + #Cell("IDDRX4B"), + #Cell("IDDRX71A"), + #Cell("ODDRXE"), + #Cell("ODDRX2E"), + #Cell("ODDRX4B"), + #Cell("ODDRX71A"), + #Cell("DQSDLLC"), + #Cell("DELAYE"), + #Cell("DELAYD"), + #Cell("DLLDELC"), + #Cell("CLKFBBUFA"), + #Cell("PCNTR"), + #Cell("BCINRD"), + #Cell("BCLVDSO"), + #Cell("INRDB"), + #Cell("LVDSOB"), + #Cell("PG"), + Cell("EHXPLLJ"), + #Cell("PLLREFCS"), + Cell("OSCJ"), + #Cell("EFBB"), + #Cell("TSALL"), + #Cell("ESBA"), + #Cell("BCSLEWRATEA"), + ]) +] + +def xtract_cells_decl(device, cells, dirs, outf): + fname = os.path.join(dir, device + '.v') + with open(fname) as f: + state = State.OUTSIDE + # Probably the most horrible Verilog "parser" ever written. + cell = None + kind = None + for l in f: + l, _, comment = l.partition('//') + l = l.strip() + m = re.search(r'synthesis .*black_box_pad_pin="([^"]*)"', comment) + if m: + iopad_pin = set(m.group(1).split(",")) + + if l.startswith("module "): + cell_name = l[7:l.find('(')].strip() + cell = None + kind = None + module_ports = [] + iopad_pin = set() + if state != State.OUTSIDE: + print('Nested modules in {}.'.format(fname)) + sys.exit(1) + for c in cells: + if c.name != cell_name: + continue + cell = c + state = State.IN_MODULE + outf.write('(* blackbox *)') + if cell.keep: + outf.write(' (* keep *)\n') + else: + outf.write('\n') + outf.write('module {} (...);\n'.format(cell.name)) + cell.found = True + if cell is None: + state = State.IN_OTHER_MODULE + elif l.startswith('task '): + if state == State.IN_MODULE: + state = State.IN_TASK + elif l.startswith('function '): + if state == State.IN_MODULE: + state = State.IN_FUNCTION + elif l == 'endtask': + if state == State.IN_TASK: + state = State.IN_MODULE + elif l == 'endfunction': + if state == State.IN_FUNCTION: + state = State.IN_MODULE + elif l == 'endmodule': + if state == State.IN_MODULE: + for kind, rng, port in module_ports: + for attr in cell.port_attrs.get(port, []): + outf.write(' (* {} *)\n'.format(attr)) + if port in iopad_pin: + outf.write(' (* iopad_external_pin *)\n') + if rng is None: + outf.write(' {} {};\n'.format(kind, port)) + else: + outf.write(' {} {} {};\n'.format(kind, rng, port)) + outf.write(l + '\n') + outf.write('\n') + elif state != State.IN_OTHER_MODULE: + print('endmodule in weird place in {}.'.format(cell.name, fname)) + sys.exit(1) + state = State.OUTSIDE + elif l.startswith(('input ', 'output ', 'inout ')) and state == State.IN_MODULE: + l = l.strip() + if l == "": + continue + if l.endswith((';', ',', ")")): + l = l[:-1] + l = l.replace(")","") + if ';' in l: + print('Weird port line in {} [{}].'.format(fname, l)) + sys.exit(1) + kind, _, ports = l.partition(' ') + for port in ports.split(','): + port = port.strip() + if port.startswith('['): + rng, port = port.split() + else: + rng = None + module_ports.append((kind, rng, port)) + elif l.startswith('parameter ') and state == State.IN_MODULE: + l = l.strip() + if l.endswith((';', ',')): + l = l[:-1] + while ' ' in l: + l = l.replace(' ', ' ') + + if "INITVAL" in l: + l = l.replace('"0x', "320'h") + l = l.replace('"', '') + if ';' in l: + print('Weird parameter line in {} [{}].'.format(fname, l)) + sys.exit(1) + outf.write(' {};\n'.format(l)) + elif kind is not None and state == State.IN_MODULE: + l = l.strip() + if l == "": + continue + if l.endswith((';', ',', ")")): + l = l[:-1] + l = l.replace(")","") + if ';' in l: + print('Weird port line in {} [{}].'.format(fname, l)) + sys.exit(1) + ports = l + for port in ports.split(','): + port = port.strip() + if port.startswith('['): + rng, port = port.split() + else: + rng = None + module_ports.append((kind, rng, port)) + + if state != State.OUTSIDE: + print('endmodule not found in {}.'.format(fname)) + sys.exit(1) + for cell in cells: + if not cell.found: + print('cell {} not found in {}.'.format(cell.name, fname)) +if __name__ == '__main__': + parser = ArgumentParser(description='Extract Lattice blackbox cell definitions from Lattice Diamond.') + parser.add_argument('diamond_dir', nargs='?', default='/usr/local/diamond/3.12/') + args = parser.parse_args() + + dirs = [ + os.path.join(args.diamond_dir, 'cae_library/synthesis/verilog/'), + ] + for dir in dirs: + if not os.path.isdir(dir): + print('{} is not a directory'.format(dir)) + + for fn, device, cells in devices: + out = StringIO() + xtract_cells_decl(device, cells, dirs, out) + with open(fn, 'w') as f: + f.write('// Created by cells_xtra.py from Lattice models\n') + f.write('\n') + f.write(out.getvalue()) From 3b9ebfa672c2ecd413123368aff7eba64aecf0e6 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 25 Aug 2023 11:10:20 +0200 Subject: [PATCH 6/7] Addressed code review comments --- techlibs/lattice/synth_lattice.cc | 91 ++----------------------------- tests/arch/machxo2/add_sub.ys | 2 +- tests/arch/machxo2/adffs.ys | 8 +-- tests/arch/machxo2/counter.ys | 2 +- tests/arch/machxo2/dffs.ys | 4 +- tests/arch/machxo2/fsm.ys | 2 +- tests/arch/machxo2/logic.ys | 2 +- tests/arch/machxo2/lutram.ys | 2 +- tests/arch/machxo2/mux.ys | 8 +-- tests/arch/machxo2/shifter.ys | 2 +- tests/arch/machxo2/tribuf.ys | 2 +- 11 files changed, 21 insertions(+), 104 deletions(-) diff --git a/techlibs/lattice/synth_lattice.cc b/techlibs/lattice/synth_lattice.cc index edca6855e08..ff5070b8073 100644 --- a/techlibs/lattice/synth_lattice.cc +++ b/techlibs/lattice/synth_lattice.cc @@ -41,7 +41,7 @@ struct SynthLatticePass : public ScriptPass log("\n"); log(" synth_lattice [options]\n"); log("\n"); - log("This command runs synthesis for Lattice FPGAs.\n"); + log("This command runs synthesis for Lattice FPGAs (excluding iCE40 and Nexus).\n"); log("\n"); log(" -top \n"); log(" use the specified module as top module\n"); @@ -66,10 +66,6 @@ struct SynthLatticePass : public ScriptPass //log(" - lifmd: LIFMD (EXPERIMENTAL)\n"); //log(" - lifmdf: LIFMDF (EXPERIMENTAL)\n"); log("\n"); - log(" -blif \n"); - log(" write the design to the specified BLIF file. writing of an output file\n"); - log(" is omitted if this parameter is not specified.\n"); - log("\n"); log(" -edif \n"); log(" write the design to the specified EDIF file. writing of an output file\n"); log(" is omitted if this parameter is not specified.\n"); @@ -116,10 +112,6 @@ struct SynthLatticePass : public ScriptPass log(" -abc9\n"); log(" use new ABC9 flow (EXPERIMENTAL)\n"); log("\n"); - log(" -vpr\n"); - log(" generate an output netlist (and BLIF file) suitable for VPR\n"); - log(" (this feature is experimental and incomplete)\n"); - log("\n"); log(" -iopad\n"); log(" insert IO buffers\n"); log("\n"); @@ -137,14 +129,13 @@ struct SynthLatticePass : public ScriptPass log("\n"); } - string top_opt, blif_file, edif_file, json_file, family; - bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, iopad, nodsp, vpr, no_rw_check, have_dsp; + string top_opt, edif_file, json_file, family; + bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, iopad, nodsp, no_rw_check, have_dsp; string postfix, arith_map, brams_map, dsp_map; void clear_flags() override { top_opt = "-auto-top"; - blif_file = ""; edif_file = ""; json_file = ""; family = ""; @@ -158,7 +149,6 @@ struct SynthLatticePass : public ScriptPass dff = false; retime = false; abc2 = false; - vpr = false; abc9 = false; iopad = false; nodsp = false; @@ -186,10 +176,6 @@ struct SynthLatticePass : public ScriptPass family = args[++argidx]; continue; } - if (args[argidx] == "-blif" && argidx+1 < args.size()) { - blif_file = args[++argidx]; - continue; - } if (args[argidx] == "-edif" && argidx+1 < args.size()) { edif_file = args[++argidx]; continue; @@ -250,10 +236,6 @@ struct SynthLatticePass : public ScriptPass abc2 = true; continue; } - if (args[argidx] == "-vpr") { - vpr = true; - continue; - } if (args[argidx] == "-abc9") { abc9 = true; continue; @@ -461,10 +443,7 @@ struct SynthLatticePass : public ScriptPass if (check_label("map_cells")) { - if (help_mode) - run("techmap -map +/lattice/cells_map.v", "(skip if -vpr)"); - else if (!vpr) - run("techmap -map +/lattice/cells_map.v"); + run("techmap -map +/lattice/cells_map.v"); run("opt_lut_ins -tech lattice"); run("clean"); } @@ -478,23 +457,6 @@ struct SynthLatticePass : public ScriptPass run("blackbox =A:whitebox"); } - if (check_label("blif")) - { - if (!blif_file.empty() || help_mode) { - if (vpr || help_mode) { - run(stringf("opt_clean -purge"), - " (vpr mode)"); - run(stringf("write_blif -attr -cname -conn -param %s", - help_mode ? "" : blif_file.c_str()), - " (vpr mode)"); - } - if (!vpr) - run(stringf("write_blif -gates -attr -param %s", - help_mode ? "" : blif_file.c_str()), - " (non-vpr mode)"); - } - } - if (check_label("edif")) { if (!edif_file.empty() || help_mode) @@ -526,49 +488,4 @@ struct SynthEcp5Pass : public Pass } SynthEcp5Pass; */ -struct SynthMachXO2Pass : public Pass -{ - SynthMachXO2Pass() : Pass("synth_machxo2", "synthesis for MachXO2 FPGAs.") { } - - void execute(std::vector args, RTLIL::Design *design) override - { - args[0] = "synth_lattice"; - args.insert(args.begin()+1, std::string()); - args.insert(args.begin()+1, std::string()); - args[1] = "-family"; - args[2] = "xo2"; - Pass::call(design, args); - } -} SynthMachXO2Pass; - -struct SynthMachXO3Pass : public Pass -{ - SynthMachXO3Pass() : Pass("synth_machxo3", "synthesis for MachXO3 FPGAs.") { } - - void execute(std::vector args, RTLIL::Design *design) override - { - args[0] = "synth_lattice"; - args.insert(args.begin()+1, std::string()); - args.insert(args.begin()+1, std::string()); - args[1] = "-family"; - args[2] = "xo3"; - Pass::call(design, args); - } -} SynthMachXO3Pass; - -struct SynthMachXO3DPass : public Pass -{ - SynthMachXO3DPass() : Pass("synth_machxo3d", "synthesis for MachXO3D FPGAs.") { } - - void execute(std::vector args, RTLIL::Design *design) override - { - args[0] = "synth_lattice"; - args.insert(args.begin()+1, std::string()); - args.insert(args.begin()+1, std::string()); - args[1] = "-family"; - args[2] = "xo3d"; - Pass::call(design, args); - } -} SynthMachXO3DPass; - PRIVATE_NAMESPACE_END diff --git a/tests/arch/machxo2/add_sub.ys b/tests/arch/machxo2/add_sub.ys index 6897363aaee..cc6ffb41a29 100644 --- a/tests/arch/machxo2/add_sub.ys +++ b/tests/arch/machxo2/add_sub.ys @@ -1,7 +1,7 @@ read_verilog ../common/add_sub.v hierarchy -top top proc -equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 10 t:LUT4 diff --git a/tests/arch/machxo2/adffs.ys b/tests/arch/machxo2/adffs.ys index f1134a6ac67..49e93f9ac30 100644 --- a/tests/arch/machxo2/adffs.ys +++ b/tests/arch/machxo2/adffs.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top adff proc -equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check +equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module select -assert-count 1 t:TRELLIS_FF @@ -12,7 +12,7 @@ select -assert-none t:TRELLIS_FF %% t:* %D design -load read hierarchy -top adffn proc -equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check +equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module select -assert-count 1 t:TRELLIS_FF @@ -22,7 +22,7 @@ select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D design -load read hierarchy -top dffs proc -equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check +equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:TRELLIS_FF @@ -32,7 +32,7 @@ select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D design -load read hierarchy -top ndffnr proc -equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check +equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:TRELLIS_FF diff --git a/tests/arch/machxo2/counter.ys b/tests/arch/machxo2/counter.ys index 11560b551fc..3d68c9900fa 100644 --- a/tests/arch/machxo2/counter.ys +++ b/tests/arch/machxo2/counter.ys @@ -2,7 +2,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -assert -multiclock -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check +equiv_opt -assert -multiclock -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 4 t:CCU2D diff --git a/tests/arch/machxo2/dffs.ys b/tests/arch/machxo2/dffs.ys index 663a64294bf..531d5ca5a27 100644 --- a/tests/arch/machxo2/dffs.ys +++ b/tests/arch/machxo2/dffs.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top dff proc -equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module select -assert-count 1 t:TRELLIS_FF @@ -12,7 +12,7 @@ select -assert-none t:TRELLIS_FF t:TRELLIS_IO %% t:* %D design -load read hierarchy -top dffe proc -equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module select -assert-count 1 t:TRELLIS_FF t:LUT4 diff --git a/tests/arch/machxo2/fsm.ys b/tests/arch/machxo2/fsm.ys index 70e1a632bdf..43dd0c80e35 100644 --- a/tests/arch/machxo2/fsm.ys +++ b/tests/arch/machxo2/fsm.ys @@ -3,7 +3,7 @@ hierarchy -top fsm proc flatten -equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut +equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut miter -equiv -make_assert -flatten gold gate miter sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter diff --git a/tests/arch/machxo2/logic.ys b/tests/arch/machxo2/logic.ys index 5c799530519..dbd702f905e 100644 --- a/tests/arch/machxo2/logic.ys +++ b/tests/arch/machxo2/logic.ys @@ -1,7 +1,7 @@ read_verilog ../common/logic.v hierarchy -top top proc -equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 9 t:LUT4 diff --git a/tests/arch/machxo2/lutram.ys b/tests/arch/machxo2/lutram.ys index 8f1918587c9..bc81c9c8b29 100644 --- a/tests/arch/machxo2/lutram.ys +++ b/tests/arch/machxo2/lutram.ys @@ -2,7 +2,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w1r proc memory -nomap -equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut +equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut memory opt -full diff --git a/tests/arch/machxo2/mux.ys b/tests/arch/machxo2/mux.ys index 4fa1bd2fcc8..0ae9559cb48 100644 --- a/tests/arch/machxo2/mux.ys +++ b/tests/arch/machxo2/mux.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top mux2 proc -equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT4 @@ -12,7 +12,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D design -load read hierarchy -top mux4 proc -equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module select -assert-count 2 t:LUT4 @@ -22,7 +22,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D design -load read hierarchy -top mux8 proc -equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module select -assert-count 5 t:LUT4 @@ -32,7 +32,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D design -load read hierarchy -top mux16 proc -equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module select -assert-max 12 t:LUT4 diff --git a/tests/arch/machxo2/shifter.ys b/tests/arch/machxo2/shifter.ys index f6440c025e8..ca7abb8098b 100644 --- a/tests/arch/machxo2/shifter.ys +++ b/tests/arch/machxo2/shifter.ys @@ -2,7 +2,7 @@ read_verilog ../common/shifter.v hierarchy -top top proc flatten -equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/machxo2/tribuf.ys b/tests/arch/machxo2/tribuf.ys index 08c86008da5..00c7012d748 100644 --- a/tests/arch/machxo2/tribuf.ys +++ b/tests/arch/machxo2/tribuf.ys @@ -2,7 +2,7 @@ read_verilog ../common/tribuf.v hierarchy -top tristate proc flatten -equiv_opt -assert -map +/lattice/cells_sim_xo2.v -map +/simcells.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v -map +/simcells.v synth_lattice -family xo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd tristate # Constrain all select calls below inside the top module select -assert-count 1 t:$_TBUF_ From 0756285710b8ee0e561e9d2f961e3d873921db13 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 25 Aug 2023 11:45:25 +0200 Subject: [PATCH 7/7] enable more primitives supported with nextpnr --- techlibs/lattice/cells_bb_xo2.v | 36 ++++++++++++++++++++++++++++++++ techlibs/lattice/cells_bb_xo3.v | 36 ++++++++++++++++++++++++++++++++ techlibs/lattice/cells_bb_xo3d.v | 36 ++++++++++++++++++++++++++++++++ techlibs/lattice/cells_xtra.py | 36 ++++++++++++++++---------------- techlibs/lattice/common_sim.vh | 9 ++++++++ 5 files changed, 135 insertions(+), 18 deletions(-) diff --git a/techlibs/lattice/cells_bb_xo2.v b/techlibs/lattice/cells_bb_xo2.v index 6e6b655c919..fdf8331b731 100644 --- a/techlibs/lattice/cells_bb_xo2.v +++ b/techlibs/lattice/cells_bb_xo2.v @@ -408,6 +408,17 @@ module FIFO8KB (...); output FF; endmodule +(* blackbox *) +module CLKDIVC (...); + parameter GSR = "DISABLED"; + parameter DIV = "2.0"; + input RST; + input CLKI; + input ALIGNWD; + output CDIV1; + output CDIVX; +endmodule + (* blackbox *) module DCMA (...); input CLK0; @@ -416,6 +427,21 @@ module DCMA (...); output DCMOUT; endmodule +(* blackbox *) +module ECLKSYNCA (...); + input ECLKI; + input STOP; + output ECLKO; +endmodule + +(* blackbox *) +module ECLKBRIDGECS (...); + input CLK0; + input CLK1; + input SEL; + output ECSOUT; +endmodule + (* blackbox *) module DCCA (...); input CLKI; @@ -423,6 +449,11 @@ module DCCA (...); output CLKO; endmodule +(* blackbox *) (* keep *) +module START (...); + input STARTCLK; +endmodule + (* blackbox *) module EHXPLLJ (...); parameter CLKI_DIV = 1; @@ -533,3 +564,8 @@ module OSCH (...); output SEDSTDBY; endmodule +(* blackbox *) (* keep *) +module TSALL (...); + input TSALL; +endmodule + diff --git a/techlibs/lattice/cells_bb_xo3.v b/techlibs/lattice/cells_bb_xo3.v index 6e6b655c919..fdf8331b731 100644 --- a/techlibs/lattice/cells_bb_xo3.v +++ b/techlibs/lattice/cells_bb_xo3.v @@ -408,6 +408,17 @@ module FIFO8KB (...); output FF; endmodule +(* blackbox *) +module CLKDIVC (...); + parameter GSR = "DISABLED"; + parameter DIV = "2.0"; + input RST; + input CLKI; + input ALIGNWD; + output CDIV1; + output CDIVX; +endmodule + (* blackbox *) module DCMA (...); input CLK0; @@ -416,6 +427,21 @@ module DCMA (...); output DCMOUT; endmodule +(* blackbox *) +module ECLKSYNCA (...); + input ECLKI; + input STOP; + output ECLKO; +endmodule + +(* blackbox *) +module ECLKBRIDGECS (...); + input CLK0; + input CLK1; + input SEL; + output ECSOUT; +endmodule + (* blackbox *) module DCCA (...); input CLKI; @@ -423,6 +449,11 @@ module DCCA (...); output CLKO; endmodule +(* blackbox *) (* keep *) +module START (...); + input STARTCLK; +endmodule + (* blackbox *) module EHXPLLJ (...); parameter CLKI_DIV = 1; @@ -533,3 +564,8 @@ module OSCH (...); output SEDSTDBY; endmodule +(* blackbox *) (* keep *) +module TSALL (...); + input TSALL; +endmodule + diff --git a/techlibs/lattice/cells_bb_xo3d.v b/techlibs/lattice/cells_bb_xo3d.v index c957b00293e..84d7d960198 100644 --- a/techlibs/lattice/cells_bb_xo3d.v +++ b/techlibs/lattice/cells_bb_xo3d.v @@ -408,6 +408,17 @@ module FIFO8KB (...); output FF; endmodule +(* blackbox *) +module CLKDIVC (...); + parameter GSR = "DISABLED"; + parameter DIV = "2.0"; + input RST; + input CLKI; + input ALIGNWD; + output CDIV1; + output CDIVX; +endmodule + (* blackbox *) module DCMA (...); input CLK0; @@ -416,6 +427,21 @@ module DCMA (...); output DCMOUT; endmodule +(* blackbox *) +module ECLKSYNCA (...); + input ECLKI; + input STOP; + output ECLKO; +endmodule + +(* blackbox *) +module ECLKBRIDGECS (...); + input CLK0; + input CLK1; + input SEL; + output ECSOUT; +endmodule + (* blackbox *) module DCCA (...); input CLKI; @@ -423,6 +449,11 @@ module DCCA (...); output CLKO; endmodule +(* blackbox *) (* keep *) +module START (...); + input STARTCLK; +endmodule + (* blackbox *) module EHXPLLJ (...); parameter CLKI_DIV = 1; @@ -534,3 +565,8 @@ module OSCJ (...); output OSCESB; endmodule +(* blackbox *) (* keep *) +module TSALL (...); + input TSALL; +endmodule + diff --git a/techlibs/lattice/cells_xtra.py b/techlibs/lattice/cells_xtra.py index f2dd1f29749..fa4e38ace03 100644 --- a/techlibs/lattice/cells_xtra.py +++ b/techlibs/lattice/cells_xtra.py @@ -315,13 +315,13 @@ class State(Enum): Cell("PDPW8KC"), Cell("SP8KC"), Cell("FIFO8KB"), - #Cell("CLKDIVC"), + Cell("CLKDIVC"), Cell("DCMA"), - #Cell("ECLKSYNCA"), - #Cell("ECLKBRIDGECS"), + Cell("ECLKSYNCA"), + Cell("ECLKBRIDGECS"), Cell("DCCA"), - #Cell("JTAGF"), - #Cell("START"), + #Cell("JTAGF", True, port_attrs={'TCK': ['iopad_external_pin'], 'TMS': ['iopad_external_pin'], 'TDO': ['iopad_external_pin'], 'TDI': ['iopad_external_pin']}), + Cell("START", True), #Cell("SEDFA"), #Cell("SEDFB"), #Cell("IDDRXE"), @@ -351,7 +351,7 @@ class State(Enum): #Cell("PLLREFCS"), Cell("OSCH"), #Cell("EFB"), - #Cell("TSALL"), + Cell("TSALL", True), ]), ("cells_bb_xo3.v", "machxo3lf", [ #Cell("AGEB2"), @@ -495,13 +495,13 @@ class State(Enum): Cell("PDPW8KC"), Cell("SP8KC"), Cell("FIFO8KB"), - #Cell("CLKDIVC"), + Cell("CLKDIVC"), Cell("DCMA"), - #Cell("ECLKSYNCA"), - #Cell("ECLKBRIDGECS"), + Cell("ECLKSYNCA"), + Cell("ECLKBRIDGECS"), Cell("DCCA"), - #Cell("JTAGF"), - #Cell("START"), + #Cell("JTAGF", True, port_attrs={'TCK': ['iopad_external_pin'], 'TMS': ['iopad_external_pin'], 'TDO': ['iopad_external_pin'], 'TDI': ['iopad_external_pin']}), + Cell("START", True), #Cell("SEDFA"), #Cell("SEDFB"), #Cell("IDDRXE"), @@ -527,7 +527,7 @@ class State(Enum): #Cell("PLLREFCS"), Cell("OSCH"), #Cell("EFB"), - #Cell("TSALL"), + Cell("TSALL", True), ]), ("cells_bb_xo3d.v", "machxo3d", [ #Cell("AGEB2"), @@ -672,13 +672,13 @@ class State(Enum): Cell("PDPW8KC"), Cell("SP8KC"), Cell("FIFO8KB"), - #Cell("CLKDIVC"), + Cell("CLKDIVC"), Cell("DCMA"), - #Cell("ECLKSYNCA"), - #Cell("ECLKBRIDGECS"), + Cell("ECLKSYNCA"), + Cell("ECLKBRIDGECS"), Cell("DCCA"), - #Cell("JTAGF"), - #Cell("START"), + #Cell("JTAGF", True, port_attrs={'TCK': ['iopad_external_pin'], 'TMS': ['iopad_external_pin'], 'TDO': ['iopad_external_pin'], 'TDI': ['iopad_external_pin']}), + Cell("START", True), #Cell("SEDFA"), #Cell("SEDFB"), #Cell("IDDRXE"), @@ -704,7 +704,7 @@ class State(Enum): #Cell("PLLREFCS"), Cell("OSCJ"), #Cell("EFBB"), - #Cell("TSALL"), + Cell("TSALL", True), #Cell("ESBA"), #Cell("BCSLEWRATEA"), ]) diff --git a/techlibs/lattice/common_sim.vh b/techlibs/lattice/common_sim.vh index e6c2e57b507..2f8e1db1a82 100644 --- a/techlibs/lattice/common_sim.vh +++ b/techlibs/lattice/common_sim.vh @@ -394,6 +394,15 @@ module TRELLIS_COMB( endmodule +// Constants +module VLO(output Z); + assign Z = 1'b0; +endmodule + +module VHI(output Z); + assign Z = 1'b1; +endmodule + `ifndef NO_INCLUDES `include "cells_ff.vh"