From d7d7ca65d8a1314d8f0c8b7b1e9fcbd3d68f5d47 Mon Sep 17 00:00:00 2001
From: Stephen Neuendorffer <stephen.neuendorffer@amd.com>
Date: Tue, 7 May 2024 20:47:43 -0700
Subject: [PATCH] Add support for control connections (#1451)

---
 include/aie/Dialect/AIE/IR/AIEAttrs.td |  3 ++-
 lib/Dialect/AIE/IR/AIETargetModel.cpp  | 19 +++++++++++++++++++
 lib/Targets/AIETargetCDODirect.cpp     |  2 +-
 test/dialect/AIE/switchbox-vc1902.mlir |  4 ++++
 test/dialect/AIE/switchbox-ve2802.mlir |  6 ++++++
 5 files changed, 32 insertions(+), 2 deletions(-)

diff --git a/include/aie/Dialect/AIE/IR/AIEAttrs.td b/include/aie/Dialect/AIE/IR/AIEAttrs.td
index 167a1bf4d9..c5c4befd02 100644
--- a/include/aie/Dialect/AIE/IR/AIEAttrs.td
+++ b/include/aie/Dialect/AIE/IR/AIEAttrs.td
@@ -49,11 +49,12 @@ def EastWire:   I32EnumAttrCase<"East", 6>;
 def PLIOWire:   I32EnumAttrCase<"PLIO", 7>;
 def NOCWire:    I32EnumAttrCase<"NOC", 8>;
 def TraceWire:  I32EnumAttrCase<"Trace", 9>;
+def ControlWire:  I32EnumAttrCase<"Ctrl", 10>;
 
 def WireBundle: I32EnumAttr<"WireBundle", "Bundle of wires",
   [
     CoreWire, DMAWire, FIFOWire, SouthWire, WestWire, NorthWire,
-    EastWire, PLIOWire, NOCWire, TraceWire
+    EastWire, PLIOWire, NOCWire, TraceWire, ControlWire
   ]> {
 
   let cppNamespace = "xilinx::AIE";
diff --git a/lib/Dialect/AIE/IR/AIETargetModel.cpp b/lib/Dialect/AIE/IR/AIETargetModel.cpp
index ab62b23850..9724ce7f9c 100644
--- a/lib/Dialect/AIE/IR/AIETargetModel.cpp
+++ b/lib/Dialect/AIE/IR/AIETargetModel.cpp
@@ -127,6 +127,8 @@ AIE1TargetModel::getNumDestSwitchboxConnections(int col, int row,
         return 0;
       return 4;
     }
+    case WireBundle::Ctrl:
+      return isShimNOCTile(col, row) ? 1 : 0;
     default:
       return 0;
     }
@@ -153,6 +155,8 @@ AIE1TargetModel::getNumDestSwitchboxConnections(int col, int row,
       return 0;
     return 4;
   }
+  case WireBundle::Ctrl:
+    return 1;
   default:
     return 0;
   }
@@ -181,6 +185,8 @@ AIE1TargetModel::getNumSourceSwitchboxConnections(int col, int row,
     }
     case WireBundle::Trace:
       return 1;
+    case WireBundle::Ctrl:
+      return isShimNOCTile(col, row) ? 1 : 0;
     default:
       return 0;
     }
@@ -209,6 +215,8 @@ AIE1TargetModel::getNumSourceSwitchboxConnections(int col, int row,
   }
   case WireBundle::Trace:
     return 2;
+  case WireBundle::Ctrl:
+    return 1;
   default:
     return 0;
   }
@@ -343,6 +351,8 @@ AIE2TargetModel::getNumDestSwitchboxConnections(int col, int row,
       return 6;
     case WireBundle::South:
       return 4;
+    case WireBundle::Ctrl:
+      return 1;
     default:
       return 0;
     }
@@ -365,6 +375,8 @@ AIE2TargetModel::getNumDestSwitchboxConnections(int col, int row,
         return 0;
       return 4;
     }
+    case WireBundle::Ctrl:
+      return isShimNOCTile(col, row) ? 1 : 0;
     default:
       return 0;
     }
@@ -393,6 +405,8 @@ AIE2TargetModel::getNumDestSwitchboxConnections(int col, int row,
       return 0;
     return 4;
   }
+  case WireBundle::Ctrl:
+    return 1;
   default:
     return 0;
   }
@@ -410,6 +424,7 @@ AIE2TargetModel::getNumSourceSwitchboxConnections(int col, int row,
     case WireBundle::South:
       return 6;
     case WireBundle::Trace:
+    case WireBundle::Ctrl:
       return 1;
     default:
       return 0;
@@ -435,6 +450,8 @@ AIE2TargetModel::getNumSourceSwitchboxConnections(int col, int row,
     }
     case WireBundle::Trace:
       return 1;
+    case WireBundle::Ctrl:
+      return isShimNOCTile(col, row) ? 1 : 0;
     default:
       return 0;
     }
@@ -467,6 +484,8 @@ AIE2TargetModel::getNumSourceSwitchboxConnections(int col, int row,
   case WireBundle::Trace:
     // Port 0: core trace. Port 1: memory trace.
     return 2;
+  case WireBundle::Ctrl:
+    return 1;
   default:
     return 0;
   }
diff --git a/lib/Targets/AIETargetCDODirect.cpp b/lib/Targets/AIETargetCDODirect.cpp
index 5f3b94af5f..b3a6324fc0 100644
--- a/lib/Targets/AIETargetCDODirect.cpp
+++ b/lib/Targets/AIETargetCDODirect.cpp
@@ -96,7 +96,7 @@ static const std::map<WireBundle, StrmSwPortType>
     WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE = {
         {WireBundle::Core, StrmSwPortType::CORE},
         {WireBundle::DMA, StrmSwPortType::DMA},
-        // missing control from StrmSwPortType
+        {WireBundle::Ctrl, StrmSwPortType::CTRL},
         {WireBundle::FIFO, StrmSwPortType::FIFO},
         {WireBundle::South, StrmSwPortType::SOUTH},
         {WireBundle::West, StrmSwPortType::WEST},
diff --git a/test/dialect/AIE/switchbox-vc1902.mlir b/test/dialect/AIE/switchbox-vc1902.mlir
index fd5ee94b4c..df6896c056 100644
--- a/test/dialect/AIE/switchbox-vc1902.mlir
+++ b/test/dialect/AIE/switchbox-vc1902.mlir
@@ -22,6 +22,8 @@ module {
       aie.connect<North: 3, South: 3> // 4 southgoing connections
       aie.connect<West: 3, East: 3> // 4 eastgoing connections
       aie.connect<Trace: 0, South: 1>
+      aie.connect<Ctrl: 0, North: 2>
+      aie.connect<North: 2, Ctrl: 0>
     }
 
     %30 = aie.tile(3, 0) // Shim-NOC
@@ -89,6 +91,8 @@ module {
       aie.connect<East: 3, West: 3> // 4 westgoing connections
       aie.connect<North: 3, South: 3> // 4 southgoing connections
       aie.connect<West: 3, East: 3> // 4 eastgoing connections
+      aie.connect<Ctrl: 0, North: 1>
+      aie.connect<North: 2, Ctrl: 0>
     }
   }
 }
diff --git a/test/dialect/AIE/switchbox-ve2802.mlir b/test/dialect/AIE/switchbox-ve2802.mlir
index ace4c863c8..ee4c226e87 100644
--- a/test/dialect/AIE/switchbox-ve2802.mlir
+++ b/test/dialect/AIE/switchbox-ve2802.mlir
@@ -22,6 +22,8 @@ module {
       aie.connect<North: 3, South: 3> // 4 southgoing connections
       aie.connect<West: 3, East: 3> // 4 eastgoing connections
       aie.connect<Trace: 0, South: 1>
+      aie.connect<Ctrl: 0, North: 2>
+      aie.connect<North: 2, Ctrl: 0>
     }
 
     %30 = aie.tile(3, 0) // Shim-NOC
@@ -86,6 +88,8 @@ module {
       aie.connect<South: 5, North: 5> // 6 northgoing connections
       aie.connect<North: 3, South: 3> // 4 southgoing connections
       aie.connect<Trace: 0, South: 1>
+      aie.connect<Ctrl: 0, North: 2>
+      aie.connect<North: 2, Ctrl: 0>
     }
 
     %03 = aie.tile(1, 3) // core tile
@@ -99,6 +103,8 @@ module {
       aie.connect<East: 3, West: 3> // 4 westgoing connections
       aie.connect<North: 3, South: 3> // 4 southgoing connections
       aie.connect<West: 3, East: 3> // 4 eastgoing connections
+      aie.connect<Ctrl: 0, North: 2>
+      aie.connect<North: 2, Ctrl: 0>
     }
   }
 }