From d27c3ddcf03e45564c8565a05e4d3369d95e215a Mon Sep 17 00:00:00 2001 From: max Date: Tue, 19 Dec 2023 22:56:19 -0600 Subject: [PATCH] cervino -> versal_prod --- reference_designs/MM_2x2/circuit_switched_version/aie.mlir | 2 +- .../MM_2x2/objectFifo_circuit_switched_version/aie.mlir | 2 +- reference_designs/MM_2x2/packet_switched_version/aie.mlir | 2 +- .../HDIFF_dual_AIE_objectFIFO_ping_pong/Makefile | 6 +++--- .../HDIFF_dual_AIE_objectFIFO_ping_pong/sim.tcl | 2 +- .../HDIFF_single_AIE_objectFIFO/Makefile | 6 +++--- .../HDIFF_single_AIE_objectFIFO/sim.tcl | 2 +- .../HDIFF_single_AIE_objectFIFO_ping_pong/Makefile | 6 +++--- .../HDIFF_single_AIE_objectFIFO_ping_pong/sim.tcl | 2 +- .../HDIFF_single_AIE_objectFIFO_ping_pong_scaled/Makefile | 4 ++-- .../HDIFF_tri_AIE_objectFIFO_ping_pong/Makefile | 6 +++--- .../HDIFF_tri_AIE_objectFIFO_ping_pong/sim.tcl | 2 +- .../HDIFF_tri_AIE_objectFIFO_ping_pong_scaled/Makefile | 6 +++--- reference_designs/idct/aie.mlir | 2 +- .../idct/objectFifo_circuit_switched_version/aie.mlir | 2 +- tutorials/tutorial-9/external_kernel/sim.tcl | 2 +- tutorials/tutorial-9/matmul_kernel/sim.tcl | 2 +- 17 files changed, 28 insertions(+), 28 deletions(-) diff --git a/reference_designs/MM_2x2/circuit_switched_version/aie.mlir b/reference_designs/MM_2x2/circuit_switched_version/aie.mlir index 78ac0ba8e2..9901ff2fb1 100755 --- a/reference_designs/MM_2x2/circuit_switched_version/aie.mlir +++ b/reference_designs/MM_2x2/circuit_switched_version/aie.mlir @@ -11,7 +11,7 @@ //===----------------------------------------------------------------------===// // REQUIRES: valid_xchess_license -// RUN: xchesscc -p me -P %aietools/data/cervino/lib -c %S/../kernel.cc +// RUN: xchesscc -p me -P %aietools/data/versal_prod/lib -c %S/../kernel.cc // RUN: aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf diff --git a/reference_designs/MM_2x2/objectFifo_circuit_switched_version/aie.mlir b/reference_designs/MM_2x2/objectFifo_circuit_switched_version/aie.mlir index 1b889b9b33..1ef7ebc1bc 100755 --- a/reference_designs/MM_2x2/objectFifo_circuit_switched_version/aie.mlir +++ b/reference_designs/MM_2x2/objectFifo_circuit_switched_version/aie.mlir @@ -11,7 +11,7 @@ //===----------------------------------------------------------------------===// // REQUIRES: valid_xchess_license -// RUN: xchesscc -p me -P %aietools/data/cervino/lib -c %S/../kernel.cc +// RUN: xchesscc -p me -P %aietools/data/versal_prod/lib -c %S/../kernel.cc // RUN: aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf diff --git a/reference_designs/MM_2x2/packet_switched_version/aie.mlir b/reference_designs/MM_2x2/packet_switched_version/aie.mlir index a119b9ec18..f11d908a58 100644 --- a/reference_designs/MM_2x2/packet_switched_version/aie.mlir +++ b/reference_designs/MM_2x2/packet_switched_version/aie.mlir @@ -9,7 +9,7 @@ //===----------------------------------------------------------------------===// // REQUIRES: valid_xchess_license -// RUN: xchesscc -p me -P %aietools/data/cervino/lib -c %S/../kernel.cc +// RUN: xchesscc -p me -P %aietools/data/versal_prod/lib -c %S/../kernel.cc // RUN: aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf diff --git a/reference_designs/horizontal_diffusion/HDIFF_dual_AIE_objectFIFO_ping_pong/Makefile b/reference_designs/horizontal_diffusion/HDIFF_dual_AIE_objectFIFO_ping_pong/Makefile index 571afca3e9..6d83319ae7 100644 --- a/reference_designs/horizontal_diffusion/HDIFF_dual_AIE_objectFIFO_ping_pong/Makefile +++ b/reference_designs/horizontal_diffusion/HDIFF_dual_AIE_objectFIFO_ping_pong/Makefile @@ -14,14 +14,14 @@ f32: f32_chess f32.elf build: xchessmk test.prx sim: - xca_udm_dbg -P $AIETOOLS_ROOT/data/cervino/lib/ -t sim.tcl + xca_udm_dbg -P $AIETOOLS_ROOT/data/versal_prod/lib/ -t sim.tcl i32_chess: - xchesscc -p me -P $AIETOOLS_ROOT/data/cervino/lib/ -L $AIETOOLS_ROOT/data/cervino/lib/ -c ./hdiff_lap.cc ./hdiff_flux.cc + xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c ./hdiff_lap.cc ./hdiff_flux.cc f32_chess: - xchesscc -p me -P $AIETOOLS_ROOT/data/cervino/lib/ -L $AIETOOLS_ROOT/data/cervino/lib/ -c ./hdiff_lap_fp32.cc ./hdiff_flux_fp32.cc + xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c ./hdiff_lap_fp32.cc ./hdiff_flux_fp32.cc i32.elf: aiecc.py --sysroot=$SYSROOT --host-target=aarch64-linux-gnu aie.mlir \ diff --git a/reference_designs/horizontal_diffusion/HDIFF_dual_AIE_objectFIFO_ping_pong/sim.tcl b/reference_designs/horizontal_diffusion/HDIFF_dual_AIE_objectFIFO_ping_pong/sim.tcl index def1f556b1..ea6cfa54c0 100644 --- a/reference_designs/horizontal_diffusion/HDIFF_dual_AIE_objectFIFO_ping_pong/sim.tcl +++ b/reference_designs/horizontal_diffusion/HDIFF_dual_AIE_objectFIFO_ping_pong/sim.tcl @@ -1,5 +1,5 @@ iss::create %PROCESSORNAME% iss -iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/2021.1_daily_latest/installs/lin64/Vitis/2021.1/aietools/data/cervino/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on +iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/2021.1_daily_latest/installs/lin64/Vitis/2021.1/aietools/data/versal_prod/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on iss fileinput add SCD 0 -field -file ./dataset_256x256x64.txt -interval_files {} -position 0 -type {} -radix decimal -filter {} -break_on_wrap 0 -cycle_based 0 -format integer -gen_vcd_event 0 -structured 0 -bin_nbr_bytes 1 -bin_lsb_first 0 iss fileoutput add MCD 0 -field -file ./TestOutputS.txt -radix decimal -format integer #iss fileoutput add MCD 0 -field -file ./TestOutputS.txt -interval_files {} -type {} -radix decimal -format integer -bin_nbr_bytes 1 -bin_lsb_first 0 diff --git a/reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO/Makefile b/reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO/Makefile index 278a4a204c..98f86183af 100644 --- a/reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO/Makefile +++ b/reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO/Makefile @@ -15,14 +15,14 @@ f32: f32_chess f32.elf build: xchessmk test.prx sim: - xca_udm_dbg -P $AIETOOLS_ROOT/data/cervino/lib/ -t sim.tcl + xca_udm_dbg -P $AIETOOLS_ROOT/data/versal_prod/lib/ -t sim.tcl i32_chess: - xchesscc -p me -P $AIETOOLS_ROOT/data/cervino/lib/ -L $AIETOOLS_ROOT/data/cervino/lib/ -c hdiff.cc + xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c hdiff.cc f32_chess: - xchesscc -p me -P $AIETOOLS_ROOT/data/cervino/lib/ -L $AIETOOLS_ROOT/data/cervino/lib/ -c hdiff_fp32.cc + xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c hdiff_fp32.cc i32.elf: diff --git a/reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO/sim.tcl b/reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO/sim.tcl index a5e2cb5525..23dbb20437 100644 --- a/reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO/sim.tcl +++ b/reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO/sim.tcl @@ -1,5 +1,5 @@ iss::create %PROCESSORNAME% iss -iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/2021.1_daily_latest/installs/lin64/Vitis/2021.1/aietools/data/cervino/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on +iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/2021.1_daily_latest/installs/lin64/Vitis/2021.1/aietools/data/versal_prod/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on iss fileinput add SCD 0 -field -file ./dataset_1x256x6.txt -interval_files {} -position 0 -type {} -radix decimal -filter {} -break_on_wrap 0 -cycle_based 0 -format integer -gen_vcd_event 0 -structured 0 -bin_nbr_bytes 1 -bin_lsb_first 0 iss fileoutput add MCD 0 -field -file ./TestOutputS.txt -radix decimal -format integer #iss fileoutput add MCD 0 -field -file ./TestOutputS.txt -interval_files {} -type {} -radix decimal -format integer -bin_nbr_bytes 1 -bin_lsb_first 0 diff --git a/reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO_ping_pong/Makefile b/reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO_ping_pong/Makefile index 6936b5acd2..f1431d8dea 100644 --- a/reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO_ping_pong/Makefile +++ b/reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO_ping_pong/Makefile @@ -14,14 +14,14 @@ f32: f32_chess f32.elf build: xchessmk test.prx sim: - xca_udm_dbg -P $AIETOOLS_ROOT/data/cervino/lib/ -t sim.tcl + xca_udm_dbg -P $AIETOOLS_ROOT/data/versal_prod/lib/ -t sim.tcl i32_chess: - xchesscc -p me -P $AIETOOLS_ROOT/data/cervino/lib/ -L $AIETOOLS_ROOT/data/cervino/lib/ -c hdiff.cc + xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c hdiff.cc f32_chess: - xchesscc -p me -P $AIETOOLS_ROOT/data/cervino/lib/ -L $AIETOOLS_ROOT/data/cervino/lib/ -c hdiff_fp32.cc + xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c hdiff_fp32.cc i32.elf: diff --git a/reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO_ping_pong/sim.tcl b/reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO_ping_pong/sim.tcl index def1f556b1..ea6cfa54c0 100644 --- a/reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO_ping_pong/sim.tcl +++ b/reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO_ping_pong/sim.tcl @@ -1,5 +1,5 @@ iss::create %PROCESSORNAME% iss -iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/2021.1_daily_latest/installs/lin64/Vitis/2021.1/aietools/data/cervino/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on +iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/2021.1_daily_latest/installs/lin64/Vitis/2021.1/aietools/data/versal_prod/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on iss fileinput add SCD 0 -field -file ./dataset_256x256x64.txt -interval_files {} -position 0 -type {} -radix decimal -filter {} -break_on_wrap 0 -cycle_based 0 -format integer -gen_vcd_event 0 -structured 0 -bin_nbr_bytes 1 -bin_lsb_first 0 iss fileoutput add MCD 0 -field -file ./TestOutputS.txt -radix decimal -format integer #iss fileoutput add MCD 0 -field -file ./TestOutputS.txt -interval_files {} -type {} -radix decimal -format integer -bin_nbr_bytes 1 -bin_lsb_first 0 diff --git a/reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO_ping_pong_scaled/Makefile b/reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO_ping_pong_scaled/Makefile index 7882fe334b..8e62dbbc6e 100644 --- a/reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO_ping_pong_scaled/Makefile +++ b/reference_designs/horizontal_diffusion/HDIFF_single_AIE_objectFIFO_ping_pong_scaled/Makefile @@ -14,11 +14,11 @@ all: test.elf build: xchessmk test.prx sim: - xca_udm_dbg -P $AIETOOLS_ROOT/data/cervino/lib/ -t sim.tcl + xca_udm_dbg -P $AIETOOLS_ROOT/data/versal_prod/lib/ -t sim.tcl chess: - xchesscc -p me -P $AIETOOLS_ROOT/data/cervino/lib/ -L $AIETOOLS_ROOT/data/cervino/lib/ -c hdiff.cc + xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c hdiff.cc test.elf: aiecc.py --sysroot=$SYSROOT --host-target=aarch64-linux-gnu aie.mlir \ diff --git a/reference_designs/horizontal_diffusion/HDIFF_tri_AIE_objectFIFO_ping_pong/Makefile b/reference_designs/horizontal_diffusion/HDIFF_tri_AIE_objectFIFO_ping_pong/Makefile index a6a34185d4..edef9ce5bb 100644 --- a/reference_designs/horizontal_diffusion/HDIFF_tri_AIE_objectFIFO_ping_pong/Makefile +++ b/reference_designs/horizontal_diffusion/HDIFF_tri_AIE_objectFIFO_ping_pong/Makefile @@ -14,14 +14,14 @@ f32: f32_chess f32.elf build: xchessmk test.prx sim: - xca_udm_dbg -P $AIETOOLS_ROOT/data/cervino/lib/ -t sim.tcl + xca_udm_dbg -P $AIETOOLS_ROOT/data/versal_prod/lib/ -t sim.tcl i32_chess: - xchesscc -p me -P $AIETOOLS_ROOT/data/cervino/lib/ -L $AIETOOLS_ROOT/data/cervino/lib/ -c ./hdiff_lap.cc ./hdiff_flux1.cc ./hdiff_flux2.cc + xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c ./hdiff_lap.cc ./hdiff_flux1.cc ./hdiff_flux2.cc f32_chess: - xchesscc -p me -P $AIETOOLS_ROOT/data/cervino/lib/ -L $AIETOOLS_ROOT/data/cervino/lib/ -c ./hdiff_lap_fp32.cc ./hdiff_flux1_fp32.cc ./hdiff_flux2_fp32.cc + xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c ./hdiff_lap_fp32.cc ./hdiff_flux1_fp32.cc ./hdiff_flux2_fp32.cc i32.elf: aiecc.py --sysroot=$SYSROOT --host-target=aarch64-linux-gnu aie.mlir \ diff --git a/reference_designs/horizontal_diffusion/HDIFF_tri_AIE_objectFIFO_ping_pong/sim.tcl b/reference_designs/horizontal_diffusion/HDIFF_tri_AIE_objectFIFO_ping_pong/sim.tcl index def1f556b1..ea6cfa54c0 100644 --- a/reference_designs/horizontal_diffusion/HDIFF_tri_AIE_objectFIFO_ping_pong/sim.tcl +++ b/reference_designs/horizontal_diffusion/HDIFF_tri_AIE_objectFIFO_ping_pong/sim.tcl @@ -1,5 +1,5 @@ iss::create %PROCESSORNAME% iss -iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/2021.1_daily_latest/installs/lin64/Vitis/2021.1/aietools/data/cervino/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on +iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/2021.1_daily_latest/installs/lin64/Vitis/2021.1/aietools/data/versal_prod/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on iss fileinput add SCD 0 -field -file ./dataset_256x256x64.txt -interval_files {} -position 0 -type {} -radix decimal -filter {} -break_on_wrap 0 -cycle_based 0 -format integer -gen_vcd_event 0 -structured 0 -bin_nbr_bytes 1 -bin_lsb_first 0 iss fileoutput add MCD 0 -field -file ./TestOutputS.txt -radix decimal -format integer #iss fileoutput add MCD 0 -field -file ./TestOutputS.txt -interval_files {} -type {} -radix decimal -format integer -bin_nbr_bytes 1 -bin_lsb_first 0 diff --git a/reference_designs/horizontal_diffusion/HDIFF_tri_AIE_objectFIFO_ping_pong_scaled/Makefile b/reference_designs/horizontal_diffusion/HDIFF_tri_AIE_objectFIFO_ping_pong_scaled/Makefile index 2174bce0e6..9efb5fdd0a 100644 --- a/reference_designs/horizontal_diffusion/HDIFF_tri_AIE_objectFIFO_ping_pong_scaled/Makefile +++ b/reference_designs/horizontal_diffusion/HDIFF_tri_AIE_objectFIFO_ping_pong_scaled/Makefile @@ -14,14 +14,14 @@ f32: f32_chess f32.elf build: xchessmk test.prx sim: - xca_udm_dbg -P $AIETOOLS_ROOT/data/cervino/lib/ -t sim.tcl + xca_udm_dbg -P $AIETOOLS_ROOT/data/versal_prod/lib/ -t sim.tcl i32_chess: - xchesscc -p me -P $AIETOOLS_ROOT/data/cervino/lib/ -L $AIETOOLS_ROOT/data/cervino/lib/ -c ./hdiff_lap.cc ./hdiff_flux1.cc ./hdiff_flux2.cc + xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c ./hdiff_lap.cc ./hdiff_flux1.cc ./hdiff_flux2.cc f32_chess: - xchesscc -p me -P $AIETOOLS_ROOT/data/cervino/lib/ -L $AIETOOLS_ROOT/data/cervino/lib/ -c ./hdiff_lap_fp32.cc ./hdiff_flux1_fp32.cc ./hdiff_flux2_fp32.cc + xchesscc -p me -P $AIETOOLS_ROOT/data/versal_prod/lib/ -L $AIETOOLS_ROOT/data/versal_prod/lib/ -c ./hdiff_lap_fp32.cc ./hdiff_flux1_fp32.cc ./hdiff_flux2_fp32.cc i32.elf: aiecc.py --sysroot=$SYSROOT --host-target=aarch64-linux-gnu aie_$(b).mlir \ diff --git a/reference_designs/idct/aie.mlir b/reference_designs/idct/aie.mlir index ca8cfcc39d..89f64eb23e 100644 --- a/reference_designs/idct/aie.mlir +++ b/reference_designs/idct/aie.mlir @@ -9,7 +9,7 @@ //===----------------------------------------------------------------------===// // REQUIRES: valid_xchess_license && jackl -// RUN: xchesscc -p me -P %aietools/data/cervino/lib -c %S/kernel.cc %S/dequant.cc %S/pass.cc +// RUN: xchesscc -p me -P %aietools/data/versal_prod/lib -c %S/kernel.cc %S/dequant.cc %S/pass.cc // RUN: aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf diff --git a/reference_designs/idct/objectFifo_circuit_switched_version/aie.mlir b/reference_designs/idct/objectFifo_circuit_switched_version/aie.mlir index 37bd48f6a9..c38f32584d 100755 --- a/reference_designs/idct/objectFifo_circuit_switched_version/aie.mlir +++ b/reference_designs/idct/objectFifo_circuit_switched_version/aie.mlir @@ -9,7 +9,7 @@ //===----------------------------------------------------------------------===// // REQUIRES: valid_xchess_license && jackl -// RUN: xchesscc -p me -P %aietools/data/cervino/lib -c %S/../kernel.cc %S/../dequant.cc %S/../pass.cc +// RUN: xchesscc -p me -P %aietools/data/versal_prod/lib -c %S/../kernel.cc %S/../dequant.cc %S/../pass.cc // RUN: aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf diff --git a/tutorials/tutorial-9/external_kernel/sim.tcl b/tutorials/tutorial-9/external_kernel/sim.tcl index db27e3c9a5..867f3f8b40 100644 --- a/tutorials/tutorial-9/external_kernel/sim.tcl +++ b/tutorials/tutorial-9/external_kernel/sim.tcl @@ -1,6 +1,6 @@ iss::create %PROCESSORNAME% iss -#iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/SWIP/2020.1_0602_1208/installs/lin64/Vitis/2020.1/cardano/data/cervino/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on +#iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/SWIP/2020.1_0602_1208/installs/lin64/Vitis/2020.1/cardano/data/versal_prod/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath %XILINX_VITIS%/aietools/data/aie_ml/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on iss step -1 iss profile save test.prf diff --git a/tutorials/tutorial-9/matmul_kernel/sim.tcl b/tutorials/tutorial-9/matmul_kernel/sim.tcl index db27e3c9a5..867f3f8b40 100644 --- a/tutorials/tutorial-9/matmul_kernel/sim.tcl +++ b/tutorials/tutorial-9/matmul_kernel/sim.tcl @@ -1,6 +1,6 @@ iss::create %PROCESSORNAME% iss -#iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/SWIP/2020.1_0602_1208/installs/lin64/Vitis/2020.1/cardano/data/cervino/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on +#iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath /proj/xbuilds/SWIP/2020.1_0602_1208/installs/lin64/Vitis/2020.1/cardano/data/versal_prod/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath %XILINX_VITIS%/aietools/data/aie_ml/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on iss step -1 iss profile save test.prf