diff --git a/include/aie/Dialect/AIE/IR/AIE.td b/include/aie/Dialect/AIE/IR/AIE.td index 8f8c10376d..ccf805cf8a 100644 --- a/include/aie/Dialect/AIE/IR/AIE.td +++ b/include/aie/Dialect/AIE/IR/AIE.td @@ -14,7 +14,7 @@ include "mlir/IR/OpBase.td" def AIE_Dialect : Dialect { - let name = "AIE"; + let name = "aie"; let cppNamespace = "::xilinx::AIE"; let description = [{ diff --git a/include/aie/Dialect/AIE/IR/AIEOps.td b/include/aie/Dialect/AIE/IR/AIEOps.td index de5938b958..dc749c9fef 100644 --- a/include/aie/Dialect/AIE/IR/AIEOps.td +++ b/include/aie/Dialect/AIE/IR/AIEOps.td @@ -215,7 +215,7 @@ def AIE_ShimMuxOp: AIE_Op<"shim_mux", [ let summary = "Declare a switch in the PL shim"; let description = [{ This operation represents the additional interconnect that is part of a shim interface tile. - Like the `AIE.switchbox` operation, `AIE.shimMux` is configured + Like the `aie.switchbox` operation, `aie.shim_mux` is configured by code in its region, but can only contain connect operations Example: @@ -255,18 +255,18 @@ def AIE_ShimDMAOp: AIE_Op<"shim_dma", [ Example: ``` - %buf = AIE.external_buffer : memref<256xi64> - %lock1 = AIE.lock(%t70, 1) + %buf = aie.external_buffer : memref<256xi64> + %lock1 = aie.lock(%t70, 1) - %dma = AIE.shim_dma(%t70) { - AIE.dma_start(MM2S, 0, ^bd0, ^end) + %dma = aie.shim_dma(%t70) { + aie.dma_start(MM2S, 0, ^bd0, ^end) ^bd0: - AIE.use_lock(%lock1, Acquire, 1) - AIE.dmaBd(<%buf : memref<512 x i16>, 0, 512>, 0) - AIE.use_lock(%lock1, Release, 0) - AIE.next_bd ^bd0 + aie.use_lock(%lock1, Acquire, 1) + aie.dma_bd(<%buf : memref<512 x i16>, 0, 512>, A) + aie.use_lock(%lock1, Release, 0) + aie.next_bd ^bd0 ^end: - AIE.end + aie.end } ``` Create the shim_dma for tile %t70 and setup one DMA channel and one Buffer Descriptor. @@ -308,17 +308,17 @@ def AIE_CoreOp: AIE_Op<"core", [ Examples: ``` %tile = aie.tile(1, 1) - %lock11_8 = AIE.lock(%tile, 8) + %lock11_8 = aie.lock(%tile, 8) aie.core(%tile) { - AIE.use_lock(%lock11_8, "Acquire", 1) - AIE.use_lock(%lock11_8, "Release", 0) - AIE.end + aie.use_lock(%lock11_8, "Acquire", 1) + aie.use_lock(%lock11_8, "Release", 0) + aie.end } ``` ``` - %tile = AIE.tile(3, 3) - AIE.core(%tile) { - AIE.end + %tile = aie.tile(3, 3) + aie.core(%tile) { + aie.end } { stackSize = 2048 : i32, elf_file = "core_33.elf" } ``` }]; @@ -379,7 +379,7 @@ def AIE_ConnectOp: AIE_Op<"connect", [ParentOneOf<["SwitchboxOp", "ShimMuxOp"]> let description = [{ This operation represents a programmed circuit-switched connection in a stream switch. It associates a source bundle and source channel with a destination bundle and a destination channel. - This operation must exist within an `aie.switchbox` or `AIE.shim_switchbox` operation. + This operation must exist within an `aie.switchbox` or `aie.shim_switchbox` operation. All of the `aie.connect` operations in a switchbox must have a different destinations. All of the `aie.connect` operations must also have a destination which is different from all of the `aie.masterset` operations in the same switchbox. @@ -455,10 +455,10 @@ def AIE_AMSelOp: AIE_Op<"amsel", [ Example: ``` - %a0_0 = AIE.amsel<5>(3) - %m1 = AIE.masterset("East" : 0, %a0_0 ) - AIE.packet_rules("South" : 0) { - AIE.rule(0x1F, 0x10, %a0_0) + %a0_0 = aie.amsel<5>(3) + %m1 = aie.masterset("East" : 0, %a0_0 ) + aie.packet_rules("South" : 0) { + aie.rule(0x1F, 0x10, %a0_0) } ``` This code associates arbiter 5 with msel=3. A packet-switched connection is made routing @@ -503,8 +503,8 @@ def AIE_MasterSetOp: AIE_Op<"masterset", [ This operation specifies the configuration for a master port. Example: - %a0_m2 = AIE.amsel<0>(2) - AIE.masterset("Core" : 0, %a0_m2) + %a0_m2 = aie.amsel<0>(2) + aie.masterset("Core" : 0, %a0_m2) The code will configure the master port <"Core" : 0> to use arbiter 0 with msel 2 (see AMSelOp for more details regarding AMSel) @@ -513,12 +513,12 @@ def AIE_MasterSetOp: AIE_Op<"masterset", [ a master port can be activated by different msels from one arbiter Example: - %a1_0 = AIE.amsel<1>(0) - %a1_1 = AIE.amsel<1>(1) - %a2_3 = AIE.amsel<2>(3) + %a1_0 = aie.amsel<1>(0) + %a1_1 = aie.amsel<1>(1) + %a2_3 = aie.amsel<2>(3) - AIE.masterset("West" : 2, %a1_0, %a2_3) // this is illegal, please don't do this - AIE.masterset("West" : 3, %a1_0, %a1_1) // this is OK + aie.masterset("West" : 2, %a1_0, %a2_3) // this is illegal, please don't do this + aie.masterset("West" : 3, %a1_0, %a1_1) // this is OK }]; let assemblyFormat = [{ @@ -560,10 +560,10 @@ def AIE_PacketRulesOp: AIE_Op<"packet_rules", [SingleBlockImplicitTerminator<"En let description = [{ This operation defines packet-switched routing configuration for packets entering a switchbox. It references a port of the containing swithcbox, which be unique among other packetRules - operations and [AIE.connect]($aieconnect-aieconnectop) operations in the containing switchbox. - It contains a region of up to 4 [AIE.rule](#aierule-aiepacketruleop) operations. + operations and [aie.connect]($aieconnect-aieconnectop) operations in the containing switchbox. + It contains a region of up to 4 [aie.rule](#aierule-aiepacketruleop) operations. - See [AIE.rule](#aierule-aiepacketruleop) for an example. + See [aie.rule](#aierule-aiepacketruleop) for an example. }]; let assemblyFormat = [{ `(` $sourceBundle `:` $sourceChannel `)` regions attr-dict }]; @@ -585,7 +585,7 @@ def AIE_PacketRuleOp: AIE_Op<"rule", [HasParent<"PacketRulesOp">]> { let description = [{ This operation defines a matching rule and a destination for packet-switched connections in a switchbox. Routing is based on the ID field of packet arriving on the - matching port of the containing [AIE.packetRules](#aiepacketrules-aiepacketrulesop). + matching port of the containing [aie.packetRules](#aiepacketrules-aiepacketrulesop). The ID is first bitwise-AND'd with the mask and then checked for equality with the given ID. It is routed to arbiter and master set associated with the first matching entry. @@ -603,12 +603,12 @@ def AIE_PacketRuleOp: AIE_Op<"rule", [HasParent<"PacketRulesOp">]> { We encapsulate the configuration table as follows: Example: ``` - %a4_1 = AIE.amsel<4>(1) - %a3_2 = AIE.amsel<3>(2) + %a4_1 = aie.amsel<4>(1) + %a3_2 = aie.amsel<3>(2) - AIE.packetRules("Core" : 0) { - AIE.rule(0x1F, 0x2, %a4_1) - AIE.rule(0x1B, 0x1, %a3_2) + aie.packet_rules("Core" : 0) { + aie.rule(0x1F, 0x2, %a4_1) + aie.rule(0x1B, 0x1, %a3_2) } ``` }]; @@ -635,10 +635,10 @@ def AIE_PacketFlowOp: AIE_Op<"packet_flow", [SingleBlockImplicitTerminator<"EndO Example: ``` - %01 = AIE.tile(0, 1) - AIE.packet_flow(0x10) { - AIE.packet_source<%01, "Core" : 0> - AIE.packet_dest<%01, "Core" : 0> + %01 = aie.tile(0, 1) + aie.packet_flow(0x10) { + aie.packet_source<%01, "Core" : 0> + aie.packet_dest<%01, "Core" : 0> } ``` }]; @@ -660,9 +660,9 @@ def AIE_PacketSourceOp: AIE_Op<"packet_source", [HasParent<"PacketFlowOp">]> { let summary = "A sourceport"; let description = [{ A object representing the destination of a packet-switched flow. This must exist - within an [AIE.packet_flow](#aiepacketflow-aiepacketflowop) operation. + within an [aie.packet_flow](#aiepacketflow-aiepacketflowop) operation. - See [AIE.packet_flow](#aiepacketflow-aiepacketflowop) for an example. + See [aie.packet_flow](#aiepacketflow-aiepacketflowop) for an example. }]; let assemblyFormat = [{ @@ -684,10 +684,10 @@ def AIE_PacketDestOp: AIE_Op<"packet_dest", [HasParent<"PacketFlowOp">]> { let summary = "A destination port"; let description = [{ A object representing the destination of a packet-switched flow. This must exist - within an [AIE.packet_flow](#aiepacketflow-aiepacketflowop) operation. The destination + within an [aie.packet_flow](#aiepacketflow-aiepacketflowop) operation. The destination Must be unique within a design. - See [AIE.packet_flow](#aiepacketflow-aiepacketflowop) for an example. + See [aie.packet_flow](#aiepacketflow-aiepacketflowop) for an example. }]; let assemblyFormat = [{ @@ -706,17 +706,17 @@ def AIE_DMABDPACKETOp: AIE_Op<"dma_bd_packet", []> { This operation enables packet headers for a block descriptor for DMA operations. In particular, it specifies the packet type (3-bits) and packet ID (5-bits). - This operation must be used in an MLIR block that lives inside a MemOp's region, and before AIE.dmaBd. + This operation must be used in an MLIR block that lives inside a MemOp's region, and before aie.dma_bd. The block descriptor specifies what lock to use and the buffer configuration. Example: ``` // this defines a BD that uses lock %lck0 and buffer %buf0 ^bd5: - AIE.use_lock(%lck, "Acquire", 0) - AIE.dma_bd_packet(0x4, 0xD) - AIE.dmaBd(<$buf0 : memref<512xi32>, 0, 512>, 1) - AIE.use_lock(%lck, "Release", 1) + aie.use_lock(%lck, "Acquire", 0) + aie.dma_bd_packet(0x4, 0xD) + aie.dma_bd(<$buf0 : memref<512xi32>, 0, 512>, 1) + aie.use_lock(%lck, "Release", 1) br ^bd6 // point to the next Block, which is also a different Block Descriptor ``` }]; @@ -748,16 +748,16 @@ def AIE_DMABDOp: AIE_Op<"dma_bd", []> { ``` // this defines a BD that uses lock %lck0 and buffer %buf0 ^bd5: - AIE.use_lock(%lck, "Acquire", 0) - AIE.dma_bd(<$buf0 : memref<512xi32>, 0, 512>, 1) - AIE.use_lock(%lck, "Release", 1) + aie.use_lock(%lck, "Acquire", 0) + aie.dma_bd(<$buf0 : memref<512xi32>, 0, 512>, 1) + aie.use_lock(%lck, "Release", 1) br ^bd6 // point to the next Block, which is also a different Block Descriptor ... // this defines a BD that does not use any lock ^bd8: - AIE.dma_bd(<$buf1 : memref<64xi32>, 0, 64>, 0) + aie.dma_bd(<$buf1 : memref<64xi32>, 0, 64>, 0) ``` A DMA channel in a Memory Module can process one block descriptor after another by chaining them. There are 16 block descriptors per Memory Module. They are shared by four DMA channels. @@ -800,7 +800,7 @@ def AIE_DMABDOp: AIE_Op<"dma_bd", []> { elements: ``` - AIE.dma_bd(%buf : memref<128xi32>, 0, 128, [<8, 16>, <2, 1>, <8, 2>]) + aie.dma_bd(%buf : memref<128xi32>, 0, 128, [<8, 16>, <2, 1>, <8, 2>]) ``` }]; @@ -848,19 +848,19 @@ def AIE_DMAStartOp: AIE_Op<"dma_start", [ Example: ``` - AIE.dma_start("MM2S", 0, ^bd0, ^end) + aie.dma_start("MM2S", 0, ^bd0, ^end) ^bd0: - AIE.use_lock(%lock0, "Acquire", 0) - AIE.dma_bd(%buffer : memref<16 x f32>, 0, 16) - AIE.use_lock(%lock0, "Release", 1) + aie.use_lock(%lock0, "Acquire", 0) + aie.dma_bd(%buffer : memref<16 x f32>, 0, 16) + aie.use_lock(%lock0, "Release", 1) br ^bd0 ^end: - AIE.end + aie.end ``` - Conceptually, the AIE.dma_start operation is a terminator that either passes + Conceptually, the aie.dma_start operation is a terminator that either passes control to a basic block containing DMA operations (through its first successor) - or to a basic block for another dma_start, to an AIE.end operation. + or to a basic block for another dma_start, to an aie.end operation. }]; let arguments = ( @@ -893,15 +893,15 @@ def AIE_MemOp: AIE_Op<"mem", [ Example: ``` - m73 = AIE.mem(%t73) { - %srcDma = AIE.dma_start("S2MM", 0, ^bd0, ^end) + m73 = aie.mem(%t73) { + %srcDma = aie.dma_start("S2MM", 0, ^bd0, ^end) ^bd0: - AIE.use_lock(%lock, "Acquire", 0) - AIE.dma_bd(%buf : memref<64xi16>, 0, 64) - AIE.use_lock(%lock, "Release", 1) - AIE.next_bd ^bd0 + aie.use_lock(%lock, "Acquire", 0) + aie.dma_bd(%buf : memref<64xi16>, 0, 64) + aie.use_lock(%lock, "Release", 1) + aie.next_bd ^bd0 ^end: - AIE.end + aie.end } ``` Create the memory module for tile %t73 and setup one DMA channel and one Buffer Descriptor. @@ -944,15 +944,15 @@ def AIE_MemTileDMAOp: AIE_Op<"memtile_dma", [ Example: ``` - m73 = AIE.memtile_dma(%t71) { - %srcDma = AIE.dma_start("S2MM", 0, ^bd0, ^end) + m73 = aie.memtile_dma(%t71) { + %srcDma = aie.dma_start("S2MM", 0, ^bd0, ^end) ^bd0: - AIE.use_lock(%lock, "Acquire", 0) - AIE.dma_bd(%buf : memref<64xi16>, 0, 64>, 0) - AIE.use_lock(%lock, "Release", 1) - AIE.next_bd ^bd0 + aie.use_lock(%lock, "Acquire", 0) + aie.dma_bd(%buf : memref<64xi16>, 0, 64>, 0) + aie.use_lock(%lock, "Release", 1) + aie.next_bd ^bd0 ^end: - AIE.end + aie.end } ``` Create a description for tile %t73 and setup one DMA channel and one Buffer Descriptor. @@ -987,15 +987,15 @@ def AIE_NextBDOp: AIE_Op<"next_bd", [ Example: ``` - m73 = AIE.mem(%t73) { - %srcDma = AIE.dma_start("S2MM", 0, ^bd0, ^end) + m73 = aie.mem(%t73) { + %srcDma = aie.dma_start("S2MM", 0, ^bd0, ^end) ^bd0: - AIE.use_lock(%lock, "Acquire", 0) - AIE.dma_bd(%buf : memref<64xi16>, 0, 64) - AIE.use_lock(%lock, "Release", 1) - AIE.next_bd ^bd0 + aie.use_lock(%lock, "Acquire", 0) + aie.dma_bd(%buf : memref<64xi16>, 0, 64) + aie.use_lock(%lock, "Release", 1) + aie.next_bd ^bd0 ^end: - AIE.end + aie.end } ``` }]; @@ -1018,14 +1018,14 @@ def AIE_LockOp: AIE_Op<"lock", [ Example: ``` - %tile33 = AIE.tile(3, 3) - %lck = AIE.lock(%tile33, 7) + %tile33 = aie.tile(3, 3) + %lck = aie.lock(%tile33, 7) ``` This operation represents a lock that lives in the Memory module of Tile(3, 3) with a lockID of 7 Case when LockID is not assigned: - Before AIEAssignLockIDs: %tile33 = AIE.tile(3) - After AIEAssignLockIDs: %tile33 = AIE.tile(3, $assigned_value) + Before AIEAssignLockIDs: %tile33 = aie.tile(3) + After AIEAssignLockIDs: %tile33 = aie.tile(3, $assigned_value) }]; let arguments = ( @@ -1131,8 +1131,8 @@ def AIE_BufferOp: AIE_Op<"buffer", [ Example: ``` - %tile33 = AIE.tile(3, 3) - %buf = AIE.buffer(%tile33) : memref<256xi64> + %tile33 = aie.tile(3, 3) + %buf = aie.buffer(%tile33) : memref<256xi64> ``` This operation represents a buffer in tile (3, 3) of 256 elements, each a 64-bit integer. }]; @@ -1190,7 +1190,7 @@ def AIE_ExternalBufferOp: AIE_Op<"external_buffer", []>, Results<(outs AnyMemRef Example: ``` - %buf = AIE.external_buffer : memref<256xi64> + %buf = aie.external_buffer : memref<256xi64> ``` This operation represents an external buffer. }]; @@ -1312,13 +1312,13 @@ def AIE_ShimDMAAllocationOp : AIE_Op<"shim_dma_allocation", [HasParent<"DeviceOp Example: ``` - %tile00 = AIE.tile(0, 0) - %tile02 = AIE.tile(0, 2) - AIE.objectfifo @of_in_0 (%tile00, { %tile02 }, 2) : !AIE.objectfifo> + %tile00 = aie.tile(0, 0) + %tile02 = aie.tile(0, 2) + aie.objectfifo @of_in_0 (%tile00, { %tile02 }, 2) : !aie.objectfifo> ``` could produce the following allocation info (channel direction MM2S, channel index 1, and shim column 0): ``` - AIE.shim_dma_allocation @of_in_0 (MM2S, 1, 0) + aie.shim_dma_allocation @of_in_0 (MM2S, 1, 0) ``` }]; @@ -1356,7 +1356,7 @@ def AIE_ObjectFifoCreateOp: AIE_Op<"objectfifo", [HasParent<"DeviceOp">, Symbol] 1-to-1 tile example: ``` - AIE.objectfifo @of1 (%tile12, { %tile23 }, 4 : i32) : !AIE.objectfifo> + aie.objectfifo @of1 (%tile12, { %tile23 }, 4 : i32) : !aie.objectfifo> ``` This operation creates an `objectFifo` between `%tile12` and `%tile23` of 4 elements, each a buffer of 16 32-bit integers. Note: If there are no `ObjectFifoAcquireOps` corresponding to this `objectFifo` on the cores of `%tile12` and `%tile23`, @@ -1365,14 +1365,14 @@ def AIE_ObjectFifoCreateOp: AIE_Op<"objectfifo", [HasParent<"DeviceOp">, Symbol] 1-to-2 tiles broadcast example: ``` - AIE.objectfifo @of2 (%tile12, { %tile13, %tile23 }, 4 : i32) : !AIE.objectfifo> + aie.objectfifo @of2 (%tile12, { %tile13, %tile23 }, 4 : i32) : !aie.objectfifo> ``` This operation creates an `objectFifo` between `%tile12` and tiles `%tile13`, `%tile23` of 4 elements, each a buffer of x16 32-bit integers. 1-to-2 tiles broadcast with explicit sizes example: ``` - AIE.objectfifo @of3 (%tile12, { %tile13, %tile23 }, [2, 3, 4]) : !AIE.objectfifo> + aie.objectfifo @of3 (%tile12, { %tile13, %tile23 }, [2, 3, 4]) : !aie.objectfifo> ``` This operation creates an `objectFifo` between `%tile12`, `%tile13` and `%tile23`. The depths of the `objectFifo` object pool at each tile are respectively 2, 3 and 4 for tiles `%tile12`, `%tile13` and `%tile23`. This overrides the depth analysis @@ -1405,11 +1405,11 @@ def AIE_ObjectFifoCreateOp: AIE_Op<"objectfifo", [HasParent<"DeviceOp">, Symbol] all even indices from the stream, followed by all odd indices: ``` - AIE.objectfifo @of4 (%tile12 toStream [<16, 1>, <16, 16>, <1,1>], + aie.objectfifo @of4 (%tile12 toStream [<16, 1>, <16, 16>, <1,1>], {%tile13 fromStream [], %tile23 fromStream [<2, 1>, <128, 2>]}, 2 : i32 - ) : !AIE.objectfifo> + ) : !aie.objectfifo> ``` }]; @@ -1485,9 +1485,9 @@ def AIE_ObjectFifoLinkOp: AIE_Op<"objectfifo.link", [HasParent<"DeviceOp">]> { Example: ``` - AIE.objectfifo @of1 (%t70, { %t72 }, 2) : !AIE.objectfifo> - AIE.objectfifo @of2 (%t72, { %t74 }, 2) : !AIE.objectfifo> - AIE.objectfifo.link [@of1] -> [@of2] () + aie.objectfifo @of1 (%t70, { %t72 }, 2) : !aie.objectfifo> + aie.objectfifo @of2 (%t72, { %t74 }, 2) : !aie.objectfifo> + aie.objectfifo.link [@of1] -> [@of2] () ``` This operation links two `objectFifos` which have tile `%t72` as a link point. @@ -1540,10 +1540,10 @@ def AIE_ObjectFifoRegisterExternalBuffersOp: AIE_Op<"objectfifo.register_externa Example: ``` - AIE.objectfifo @of1 (%t70, %t73, 2) : !AIE.objectfifo> - %buffer_in_0 = AIE.external_buffer : memref<512 x i16> - %buffer_in_1 = AIE.external_buffer : memref<512 x i16> - AIE.objectfifo.register_external_buffers @of1 (%t70, {buffer_in_0, buffer_in_1}) : (memref<512 x i16>, memref<512 x i16>) + aie.objectfifo @of1 (%t70, %t73, 2) : !aie.objectfifo> + %buffer_in_0 = aie.external_buffer : memref<512 x i16> + %buffer_in_1 = aie.external_buffer : memref<512 x i16> + aie.objectfifo.register_external_buffers @of1 (%t70, {buffer_in_0, buffer_in_1}) : (memref<512 x i16>, memref<512 x i16>) ``` This operation registers external buffers %buffer_in_0 and %buffer_in_1 to use in the shim_dma of shimTile %t70. }]; @@ -1576,7 +1576,7 @@ def AIE_ObjectFifoAcquireOp: AIE_Op<"objectfifo.acquire", []> { (producer: acquire for write, consumer: acquire for read). Then, it returns a subview of the acquired objects which can be used to access them. - This operation is then converted by the `AIEObjectFifoStatefulTransformPass` into `AIE.use_lock` operations on + This operation is then converted by the `AIEObjectFifoStatefulTransformPass` into `aie.use_lock` operations on the locks of the `objectFifo` objects that will be acquired. Under the hood, the operation only performs new acquires if necessary. For example, if two objects have been acquired in the past and none have yet to be released by the same process, then performing another acquire operation on the same `objectFifo` @@ -1585,7 +1585,7 @@ def AIE_ObjectFifoAcquireOp: AIE_Op<"objectfifo.acquire", []> { Example: ``` - %subview = AIE.objectfifo.acquire @of1 (Consume, 2) : !AIE.objectfifosubview> + %subview = aie.objectfifo.acquire @of1 (Consume, 2) : !aie.objectfifosubview> ``` This operation acquires the locks of the next two objects in the `objectFifo` named `@of1` from its consumer port and returns a subview of the acquired objects. @@ -1622,7 +1622,7 @@ def AIE_ObjectFifoReleaseOp: AIE_Op<"objectfifo.release", []> { Example: ``` - AIE.objectfifo.release @of1 (Produce, 1) + aie.objectfifo.release @of1 (Produce, 1) ``` This operation releases the lock of the next object in the `objectFifo` named `@of1` from producer port. }]; @@ -1652,8 +1652,8 @@ def AIE_ObjectFifoSubviewAccessOp : AIE_Op<"objectfifo.subview.access", []> { Example: ``` - %subview = AIE.objectfifo.acquire @of1 (Produce, 3) : !AIE.objectfifosubview> - %elem = AIE.objectfifo.subview.access %subview[0] : !AIE.objectfifosubview> -> memref<16xi32> + %subview = aie.objectfifo.acquire @of1 (Produce, 3) : !aie.objectfifosubview> + %elem = aie.objectfifo.subview.access %subview[0] : !aie.objectfifosubview> -> memref<16xi32> ``` In this example, %elem is the first object of the subview. Note that this may not correspond to the first element of the `objectFifo` if other acquire operations took place beforehand. @@ -1691,13 +1691,13 @@ def AIE_ObjectFifoRegisterProcessOp: AIE_Op<"objectfifo.register_process", []> { Example: ``` - AIE.objectfifo @of1 (%t72, %t73, 2) : !AIE.objectfifo> + aie.objectfifo @of1 (%t72, %t73, 2) : !aie.objectfifo> %length = arith.constant 10 : index %acquirePatternProducer = arith.constant dense<[1, 2, 2, 0]> : tensor<4xi32> %releasePatternProducer = arith.constant dense<[0, 1, 1, 2]> : tensor<4xi32> - func @producer_work(%input : !AIE.objectfifosubview>) -> () { ... } + func @producer_work(%input : !aie.objectfifosubview>) -> () { ... } - AIE.objectfifo.register_process @of1 (Produce, %acquirePatternProducer : tensor<4xi32>, %releasePatternProducer : tensor<4xi32>, @producer_work, %length) + aie.objectfifo.register_process @of1 (Produce, %acquirePatternProducer : tensor<4xi32>, %releasePatternProducer : tensor<4xi32>, @producer_work, %length) ``` This operation registers function @producer_work and associated patterns to the produce end of @of1. @producer_work will be called with the subviews produced when acquiring elements from @of1 following the acquire pattern. diff --git a/include/aie/Dialect/AIE/IR/CMakeLists.txt b/include/aie/Dialect/AIE/IR/CMakeLists.txt index f1592de639..7cfe58e372 100644 --- a/include/aie/Dialect/AIE/IR/CMakeLists.txt +++ b/include/aie/Dialect/AIE/IR/CMakeLists.txt @@ -5,7 +5,7 @@ # # (c) Copyright 2021 Xilinx Inc. -add_mlir_dialect(AIE AIE) +add_mlir_dialect(AIE aie) add_mlir_doc(AIE AIE ./ -gen-dialect-doc) # Add AIE interfaces diff --git a/include/aie/Dialect/AIEX/IR/AIEX.td b/include/aie/Dialect/AIEX/IR/AIEX.td index 8893ff35ad..d450cd4a9a 100644 --- a/include/aie/Dialect/AIEX/IR/AIEX.td +++ b/include/aie/Dialect/AIEX/IR/AIEX.td @@ -21,7 +21,7 @@ include "mlir/Interfaces/CallInterfaces.td" include "mlir/Interfaces/SideEffectInterfaces.td" def AIEX_Dialect : Dialect { - let name = "AIEX"; + let name = "aiex"; let cppNamespace = "::xilinx::AIEX"; let description = [{ @@ -30,7 +30,6 @@ def AIEX_Dialect : Dialect { to the more mature AIE dialect. }]; - let useDefaultTypePrinterParser = 1; } @@ -104,11 +103,11 @@ def AIE_MulticastOp: AIEX_Op<"multicast", [SingleBlockImplicitTerminator<"AIE::E %74 = AIE.tile(7, 4) %63 = AIE.tile(6, 3) %64 = AIE.tile(6, 4) - AIEX.multicast(%70, "DMA" : 0){ - AIEX.multi_dest<%73, "DMA" : 0> - AIEX.multi_dest<%74, "DMA" : 0> - AIEX.multi_dest<%63, "DMA" : 0> - AIEX.multi_dest<%64, "DMA" : 0> + aiex.multicast(%70, "DMA" : 0){ + aiex.multi_dest<%73, "DMA" : 0> + aiex.multi_dest<%74, "DMA" : 0> + aiex.multi_dest<%63, "DMA" : 0> + aiex.multi_dest<%64, "DMA" : 0> } ``` }]; @@ -129,10 +128,10 @@ def AIE_MultiDestOp: AIEX_Op<"multi_dest", [HasParent<"MulticastOp">]> { let summary = "A destination port of multicast flow"; let description = [{ An object representing the destination of a multicast flow. This must exist - within an [AIEX.multicast] operation. There can be multiple destinations within an - AIEX.multicast Op. + within an [aiex.multicast] operation. There can be multiple destinations within an + aiex.multicast Op. - See [AIEX.multicast]for an example. + See [aiex.multicast]for an example. }]; let assemblyFormat = [{ `<` $tile `,` $bundle `:` $channel `>` attr-dict diff --git a/include/aie/Dialect/AIEX/IR/AIEXDialect.h b/include/aie/Dialect/AIEX/IR/AIEXDialect.h index 09db0c626b..5bb636f416 100644 --- a/include/aie/Dialect/AIEX/IR/AIEXDialect.h +++ b/include/aie/Dialect/AIEX/IR/AIEXDialect.h @@ -13,38 +13,8 @@ #include "aie/Dialect/AIE/IR/AIEDialect.h" -#include "mlir/Dialect/Arith/IR/Arith.h" -#include "mlir/Dialect/ControlFlow/IR/ControlFlow.h" -#include "mlir/Dialect/Func/IR/FuncOps.h" -#include "mlir/Dialect/LLVMIR/LLVMDialect.h" -#include "mlir/Dialect/MemRef/IR/MemRef.h" -#include "mlir/Dialect/SCF/IR/SCF.h" -#include "mlir/IR/Builders.h" -#include "mlir/IR/BuiltinAttributes.h" -#include "mlir/IR/BuiltinOps.h" -#include "mlir/IR/BuiltinTypes.h" -#include "mlir/IR/Dialect.h" -#include "mlir/IR/OpDefinition.h" -#include "mlir/IR/OpImplementation.h" -#include "mlir/IR/TypeSupport.h" -#include "mlir/IR/Types.h" -#include "mlir/Pass/Pass.h" - -#include "llvm/ADT/StringSwitch.h" - -#include -#include - -namespace xilinx::AIEX { - -// The Dialect -class AIEXDialect : public mlir::Dialect { -public: - explicit AIEXDialect(mlir::MLIRContext *ctx); - static llvm::StringRef getDialectNamespace() { return "AIEX"; } -}; - -} // namespace xilinx::AIEX +// Include dialect declarations such as parseAttributes, parseType +#include "aie/Dialect/AIEX/IR/AIEXDialect.h.inc" // include TableGen generated Op definitions #define GET_OP_CLASSES diff --git a/include/aie/Dialect/AIEX/IR/CMakeLists.txt b/include/aie/Dialect/AIEX/IR/CMakeLists.txt index 1328d26f48..7fdceaf64d 100644 --- a/include/aie/Dialect/AIEX/IR/CMakeLists.txt +++ b/include/aie/Dialect/AIEX/IR/CMakeLists.txt @@ -5,5 +5,5 @@ # # (c) Copyright 2022 Xilinx Inc. -add_mlir_dialect(AIEX AIEX) -add_mlir_doc(AIEX AIEXDialect ./ -gen-dialect-doc -dialect=AIEX) +add_mlir_dialect(AIEX aiex) +add_mlir_doc(AIEX AIEXDialect ./ -gen-dialect-doc -dialect=aiex) diff --git a/lib/Dialect/AIEX/IR/AIEXDialect.cpp b/lib/Dialect/AIEX/IR/AIEXDialect.cpp index 1d260c5052..3c10547cdb 100644 --- a/lib/Dialect/AIEX/IR/AIEXDialect.cpp +++ b/lib/Dialect/AIEX/IR/AIEXDialect.cpp @@ -9,22 +9,20 @@ //===----------------------------------------------------------------------===// #include "aie/Dialect/AIEX/IR/AIEXDialect.h" -#include "aie/Dialect/AIE/IR/AIEDialect.h" #include "mlir/Dialect/Func/IR/FuncOps.h" -#include "mlir/IR/OpDefinition.h" #include "mlir/Interfaces/FoldInterfaces.h" #include "mlir/Transforms/InliningUtils.h" using namespace mlir; using namespace xilinx; -using namespace xilinx::AIE; + +#include "aie/Dialect/AIEX/IR/AIEXDialect.cpp.inc" namespace xilinx::AIEX { // FIXME: use Tablegen'd dialect class -AIEXDialect::AIEXDialect(MLIRContext *ctx) - : Dialect("AIEX", ctx, TypeID::get()) { +void AIEXDialect::initialize() { addOperations< #define GET_OP_LIST #include "aie/Dialect/AIEX/IR/AIEX.cpp.inc" @@ -37,9 +35,9 @@ AIEXDialect::AIEXDialect(MLIRContext *ctx) #include "aie/Dialect/AIEX/IR/AIEX.cpp.inc" LogicalResult AIEX::UseTokenOp::verify() { - auto parentOp = (*this)->getParentOp(); - if (isa(parentOp) || isa(parentOp) || - isa(parentOp) || isa(parentOp)) + auto *parentOp = (*this)->getParentOp(); + if (isa(parentOp) || isa(parentOp) || + isa(parentOp) || isa(parentOp)) return success(); return failure(); } @@ -49,7 +47,7 @@ LogicalResult AIEX::MulticastOp::verify() { assert(getOperation()->getNumRegions()); assert(!body.empty()); for (auto &ops : body.front()) - if (!isa(ops)) + if (!isa(ops)) return ops.emitOpError("cannot be contained in a Multicast op"); return success(); @@ -60,7 +58,7 @@ LogicalResult AIEX::BroadcastPacketOp::verify() { assert(getOperation()->getNumRegions()); assert(!body.empty()); for (auto &ops : body.front()) - if (!isa(ops)) + if (!isa(ops)) return ops.emitOpError("cannot be contained in a BroadcastPacket op"); return success(); @@ -72,26 +70,26 @@ LogicalResult AIEX::IpuDmaMemcpyNdOp::verify() { return emitOpError("must be used with memref type i32."); uint32_t strides[3]{0, 0, 0}; uint32_t lengths[4]{0, 0, 0, 0}; - if (auto const_op = getStride3().getDefiningOp()) { - strides[2] = static_cast(const_op.value()); + if (auto constOp = getStride3().getDefiningOp()) { + strides[2] = static_cast(constOp.value()); } - if (auto const_op = getStride2().getDefiningOp()) { - strides[1] = static_cast(const_op.value()); + if (auto constOp = getStride2().getDefiningOp()) { + strides[1] = static_cast(constOp.value()); } - if (auto const_op = getStride1().getDefiningOp()) { - strides[0] = static_cast(const_op.value()); + if (auto constOp = getStride1().getDefiningOp()) { + strides[0] = static_cast(constOp.value()); } - if (auto const_op = getLength3().getDefiningOp()) { - lengths[3] = static_cast(const_op.value()); + if (auto constOp = getLength3().getDefiningOp()) { + lengths[3] = static_cast(constOp.value()); } - if (auto const_op = getLength2().getDefiningOp()) { - lengths[2] = static_cast(const_op.value()); + if (auto constOp = getLength2().getDefiningOp()) { + lengths[2] = static_cast(constOp.value()); } - if (auto const_op = getLength1().getDefiningOp()) { - lengths[1] = static_cast(const_op.value()); + if (auto constOp = getLength1().getDefiningOp()) { + lengths[1] = static_cast(constOp.value()); } - if (auto const_op = getLength0().getDefiningOp()) { - lengths[0] = static_cast(const_op.value()); + if (auto constOp = getLength0().getDefiningOp()) { + lengths[0] = static_cast(constOp.value()); } if (lengths[3] > 64) return emitOpError("Length 3 exceeds the [1:64] range."); @@ -109,9 +107,9 @@ LogicalResult AIEX::IpuDmaMemcpyNdOp::verify() { } LogicalResult AIEX::IpuShimTilePushQueueOp::verify() { - const auto &target_model = getTargetModel(*this); - auto num_bds = target_model.getNumBDs(0, 0); // assume shim - if (getBdId() > num_bds) + const auto &targetModel = AIE::getTargetModel(*this); + auto numBds = targetModel.getNumBDs(0, 0); // assume shim + if (getBdId() > numBds) return emitOpError("BD ID exceeds the maximum ID."); if (getRepeatCount() > 255) return emitOpError("Repeat count exceeds the [0:255] range."); @@ -119,9 +117,9 @@ LogicalResult AIEX::IpuShimTilePushQueueOp::verify() { } LogicalResult AIEX::IpuWriteBdExShimTileOp::verify() { - const auto &target_model = getTargetModel(*this); - auto num_bds = target_model.getNumBDs(0, 0); // assume shim - if (getBdId() > num_bds) + const auto &targetModel = AIE::getTargetModel(*this); + auto numBds = targetModel.getNumBDs(0, 0); // assume shim + if (getBdId() > numBds) return emitOpError("BD ID exceeds the maximum ID."); if (getD0Wrap() > 0x3FF) return emitOpError("D0 Wrap exceeds the [0:1023] range."); diff --git a/lib/Dialect/AIEX/Transforms/AIEDmaToIpu.cpp b/lib/Dialect/AIEX/Transforms/AIEDmaToIpu.cpp index 1ceaa557e7..1f1ef6cd47 100644 --- a/lib/Dialect/AIEX/Transforms/AIEDmaToIpu.cpp +++ b/lib/Dialect/AIEX/Transforms/AIEDmaToIpu.cpp @@ -8,6 +8,7 @@ // //===----------------------------------------------------------------------===// +#include "aie/Dialect/AIE/IR/AIEDialect.h" #include "aie/Dialect/AIEX/IR/AIEXDialect.h" #include "aie/Dialect/AIEX/Transforms/AIEXPasses.h" diff --git a/lib/Targets/AIETargetIPU.cpp b/lib/Targets/AIETargetIPU.cpp index dcca57d390..0a4539378f 100644 --- a/lib/Targets/AIETargetIPU.cpp +++ b/lib/Targets/AIETargetIPU.cpp @@ -10,6 +10,7 @@ #include "AIETargets.h" +#include "aie/Dialect/AIE/IR/AIEDialect.h" #include "aie/Dialect/AIEX/IR/AIEXDialect.h" #include "mlir/Dialect/Func/IR/FuncOps.h" @@ -18,6 +19,7 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/TypeSwitch.h" #include "llvm/Support/Format.h" + #include using namespace mlir; diff --git a/python/CMakeLists.txt b/python/CMakeLists.txt index 2ed746464e..10d36e4754 100644 --- a/python/CMakeLists.txt +++ b/python/CMakeLists.txt @@ -46,7 +46,7 @@ declare_mlir_dialect_python_bindings( TD_FILE dialects/AIEBinding.td SOURCES dialects/aie.py - DIALECT_NAME AIE + DIALECT_NAME aie GEN_ENUM_BINDINGS_TD_FILE "dialects/AIEBinding.td" ) @@ -57,7 +57,7 @@ declare_mlir_dialect_python_bindings( TD_FILE dialects/AIEXBinding.td SOURCES dialects/aiex.py - DIALECT_NAME AIEX + DIALECT_NAME aiex ) declare_mlir_dialect_python_bindings( diff --git a/python/compiler/aiecc/main.py b/python/compiler/aiecc/main.py index 12af68b059..167616c9b8 100644 --- a/python/compiler/aiecc/main.py +++ b/python/compiler/aiecc/main.py @@ -835,7 +835,7 @@ async def run_flow(self): [ "lower-affine", "aie-canonicalize-device", - "AIE.device(" + "aie-assign-lock-ids", + "aie.device(" + "aie-assign-lock-ids", "aie-register-objectFifos", "aie-objectFifo-stateful-transform", "aie-lower-broadcast-packet", diff --git a/python/dialects/aie.py b/python/dialects/aie.py index b98491a264..7b6f8c7618 100644 --- a/python/dialects/aie.py +++ b/python/dialects/aie.py @@ -4,8 +4,8 @@ # SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -from ._AIE_enum_gen import * -from ._AIE_ops_gen import * +from ._aie_enum_gen import * +from ._aie_ops_gen import * from .func import CallOp, FuncOp from .._mlir_libs import get_dialect_registry from .._mlir_libs._aie import * @@ -27,6 +27,8 @@ # Comes from _aie register_dialect(get_dialect_registry()) +assert _cext.globals._check_dialect_module_loaded("aie") + def external_func(name, inputs, outputs=None, visibility="private"): if outputs is None: @@ -63,7 +65,7 @@ def __init__(self, calleeOrResults, inputs=[], input_types=[]): def bd_dim_layout(wrap, step): - return Attribute.parse(f"#AIE.bd_dim_layout<{wrap=}, {step=}>") + return Attribute.parse(f"#aie.bd_dim_layout<{wrap=}, {step=}>") @register_attribute_builder("BDDimLayoutArrayAttr") @@ -73,7 +75,7 @@ def bd_dim_layout_array_attr_builder( if isinstance(tups, list) and all(isinstance(t, tuple) for t in tups): tups = list(map(lambda t: bd_dim_layout(*t), tups)) return Attribute.parse( - f'#AIE', context=context + f'#aie', context=context ) @@ -81,7 +83,7 @@ def bd_dim_layout_array_attr_builder( def bd_dim_layout_array_array_attr_builder(tup_arrs: List[List[tuple]], context=None): tup_arrs = list(map(bd_dim_layout_array_attr_builder, tup_arrs)) return Attribute.parse( - f'#AIE', context=context + f'#aie', context=context ) diff --git a/python/dialects/aiex.py b/python/dialects/aiex.py index 45aeeca2f1..0be4c4ea7c 100644 --- a/python/dialects/aiex.py +++ b/python/dialects/aiex.py @@ -2,7 +2,7 @@ from functools import partial from . import arith -from ._AIEX_ops_gen import * +from ._aiex_ops_gen import * from .._mlir_libs import get_dialect_registry from .._mlir_libs._aie import * from ..ir import FlatSymbolRefAttr, IntegerType, IntegerAttr