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Xilinx · May 20, 2024 · 5e93a47 · 5e93a47
1 parent 787790b
commit 5e93a47
Showing 1 changed file with 5 additions and 2 deletions.
diff --git a/test/python/aie_ops.py b/test/python/aie_ops.py
@@ -24,7 +24,7 @@
     cascade_flow,
     WireBundle,
     packetflow,
-    get_target_model
+    get_target_model,
 )
 from aie.ir import InsertionPoint, Block, TypeAttr
 from aie.extras.context import mlir_mod_ctx
@@ -270,6 +270,7 @@ def test_module_context():
 
 test_module_context()
 
+
 # CHECK-LABEL: test_target_model
 # CHECK: xcvc1902 rows 9
 # CHECK: xcvc1902 cols 50
@@ -287,4 +288,6 @@ def test_target_model():
         print(f"{d} rows {tm.rows()}")
         print(f"{d} cols {tm.columns()}")
         print(f"{d} npu {tm.is_npu()}")
-test_target_model()
+
+
+test_target_model()