diff --git a/include/aie/Dialect/AIE/IR/AIEOps.td b/include/aie/Dialect/AIE/IR/AIEOps.td index 195abaf411..572070835a 100644 --- a/include/aie/Dialect/AIE/IR/AIEOps.td +++ b/include/aie/Dialect/AIE/IR/AIEOps.td @@ -1044,17 +1044,24 @@ def AIE_LockOp: AIE_Op<"lock", [TileElement]>, Results<(outs Index)> { let extraClassDeclaration = [{ bool hasName() { - return bool(getOperation()->getAttrOfType(mlir::SymbolTable::getSymbolAttrName())); + return bool(getOperation()->getAttrOfType( + mlir::SymbolTable::getSymbolAttrName())); } + mlir::StringAttr name() { - if(auto attr = getOperation()->getAttrOfType(mlir::SymbolTable::getSymbolAttrName())) + if (auto attr = getOperation()->getAttrOfType( + mlir::SymbolTable::getSymbolAttrName())) return attr; - emitOpError("does not have '") << mlir::SymbolTable::getSymbolAttrName() << "' attribute specified"; + emitOpError("does not have '") + << mlir::SymbolTable::getSymbolAttrName() << "' attribute specified"; + llvm::report_fatal_error("couldn't get name"); } + int getLockIDValue() { assert(getLockID().has_value() && "Lock has no ID value"); return getLockID().value(); } + int colIndex(); int rowIndex(); TileOp getTileOp(); @@ -1105,11 +1112,18 @@ def AIE_UseLockOp: AIE_Op<"useLock", []> { let extraClassDeclaration = [{ bool acquire() { return (getAction() == LockAction::Acquire); } - bool acquire_ge() { return (getAction() == LockAction::AcquireGreaterEqual); } + bool acquireGE() { return (getAction() == LockAction::AcquireGreaterEqual); } bool release() { return (getAction() == LockAction::Release); } int getLockValue() { return getValue(); } - int getTimeout() { if(auto val = getBlocking()) return (int)*val; else return 1;} - LockOp getLockOp() { return llvm::dyn_cast(getLock().getDefiningOp()); } + int getTimeout() { + // LockBlocking is an EnumAttr. + if (auto val = getBlocking()) + return (int)*val; + return 1; + } + LockOp getLockOp() { + return llvm::dyn_cast(getLock().getDefiningOp()); + } }]; } @@ -1134,20 +1148,25 @@ def AIE_BufferOp: AIE_Op<"buffer", [ let extraClassDeclaration = [{ bool hasName() { - return bool(getOperation()->getAttrOfType(mlir::SymbolTable::getSymbolAttrName())); + return bool(getOperation()->getAttrOfType( + mlir::SymbolTable::getSymbolAttrName())); } mlir::StringAttr name() { - if(auto attr = getOperation()->getAttrOfType(mlir::SymbolTable::getSymbolAttrName())) + if (auto attr = getOperation()->getAttrOfType( + mlir::SymbolTable::getSymbolAttrName())) return attr; - emitOpError("does not have '") << mlir::SymbolTable::getSymbolAttrName() << "' attribute specified"; + emitOpError("does not have '") + << mlir::SymbolTable::getSymbolAttrName() << "' attribute specified"; + llvm::report_fatal_error("couldn't get name"); } // Return the address of this buffer int64_t address() { - if(auto attr = getOperation()->getAttrOfType("address")) + if (auto attr = getOperation()->getAttrOfType("address")) return attr.getInt(); emitOpError("does not have 'address' attribute specified"); + llvm::report_fatal_error("couldn't address"); } // Return the number of bytes that need to be allocated for this buffer. @@ -1180,13 +1199,17 @@ def AIE_ExternalBufferOp: AIE_Op<"external_buffer", []>, Results<(outs AnyMemRef let extraClassDeclaration = [{ bool hasName() { - return bool(getOperation()->getAttrOfType(mlir::SymbolTable::getSymbolAttrName())); + return bool(getOperation()->getAttrOfType( + mlir::SymbolTable::getSymbolAttrName())); } mlir::StringAttr name() { - if(auto attr = getOperation()->getAttrOfType(mlir::SymbolTable::getSymbolAttrName())) + if (auto attr = getOperation()->getAttrOfType( + mlir::SymbolTable::getSymbolAttrName())) return attr; - emitOpError("does not have '") << mlir::SymbolTable::getSymbolAttrName() << "' attribute specified"; + emitOpError("does not have '") + << mlir::SymbolTable::getSymbolAttrName() << "' attribute specified"; + llvm::report_fatal_error("couldn't get name"); } }]; } @@ -1220,7 +1243,9 @@ def AIE_GetStreamOp: AIE_Op<"getStream", [ let extraClassDeclaration = [{ bool isWideStream() { return getStreamValue().getType().isInteger(128); } - bool isFloatStream() { return getStreamValue().getType().isa(); } + bool isFloatStream() { + return getStreamValue().getType().isa(); + } }]; } @@ -1241,7 +1266,9 @@ def AIE_PutStreamOp: AIE_Op<"putStream", [HasParent<"CoreOp">]> { let extraClassDeclaration = [{ bool isWideStream() { return getStreamValue().getType().isInteger(128); } - bool isFloatStream() { return getStreamValue().getType().isa(); } + bool isFloatStream() { + return getStreamValue().getType().isa(); + } }]; } @@ -1406,15 +1433,18 @@ def AIE_ObjectFifoCreateOp: AIE_Op<"objectFifo", [HasParent<"DeviceOp">, Symbol] let extraClassDeclaration = [{ int size(int index = 0) { if (llvm::isa(getElemNumber())) - return llvm::dyn_cast(llvm::dyn_cast(getElemNumber())[index]).getInt(); - else + return llvm::dyn_cast( + llvm::dyn_cast(getElemNumber())[index]) + .getInt(); + else return llvm::dyn_cast(getElemNumber()).getInt(); } TileOp getProducerTileOp(); mlir::StringAttr name() { - return getOperation()->getAttrOfType(mlir::SymbolTable::getSymbolAttrName()); + return getOperation()->getAttrOfType( + mlir::SymbolTable::getSymbolAttrName()); } }]; diff --git a/include/aie/Dialect/AIEX/IR/AIEX.td b/include/aie/Dialect/AIEX/IR/AIEX.td index e4a0cf9af0..efb6553e9c 100644 --- a/include/aie/Dialect/AIEX/IR/AIEX.td +++ b/include/aie/Dialect/AIEX/IR/AIEX.td @@ -337,13 +337,15 @@ def AIE_HerdOp: AIEX_Op<"herd", []>, Results<(outs Index)> { AIEI32Attr:$height ); let extraClassDeclaration = [{ - int getHerdWidth() { return getWidth(); } - int getHerdHeight() { return getHeight(); } + int getHerdWidth() { return getWidth(); } + int getHerdHeight() { return getHeight(); } int getNumAIETiles() { return getHerdWidth() * getHerdHeight(); } mlir::StringAttr name() { - if(auto attr = getOperation()->getAttrOfType(mlir::SymbolTable::getSymbolAttrName())) + if (auto attr = getOperation()->getAttrOfType( + mlir::SymbolTable::getSymbolAttrName())) return attr; - emitOpError("does not have '") << mlir::SymbolTable::getSymbolAttrName() << "' attribute specified"; + emitOpError("does not have '") + << mlir::SymbolTable::getSymbolAttrName() << "' attribute specified"; llvm::report_fatal_error("couldn't get name"); } }]; diff --git a/lib/Dialect/AIE/IR/AIEDialect.cpp b/lib/Dialect/AIE/IR/AIEDialect.cpp index 64ad291734..a47e6502eb 100644 --- a/lib/Dialect/AIE/IR/AIEDialect.cpp +++ b/lib/Dialect/AIE/IR/AIEDialect.cpp @@ -412,9 +412,8 @@ xilinx::AIE::HasValidDMAChannels::verifyTrait(Operation *op) { for (auto &bodyOp : element.getBody().getOps()) { // check for duplicate DMA channels within the same MemTileDMAOp if (auto dmaStart = dyn_cast(bodyOp)) { - xilinx::AIE::DMAChannel dmaChan = { - dmaStart.getChannelDir(), - static_cast(dmaStart.getChannelIndex())}; + xilinx::AIE::DMAChannel dmaChan = {dmaStart.getChannelDir(), + dmaStart.getChannelIndex()}; if (usedChannels.count(dmaChan)) return dmaStart.emitOpError() << "duplicate DMA channel " @@ -799,7 +798,7 @@ LogicalResult xilinx::AIE::ObjectFifoSubviewAccessOp::verify() { return emitOpError("must be called from inside a CoreOp"); ObjectFifoAcquireOp acqOp = getSubview().getDefiningOp(); - if ((int)getIndex() >= acqOp.acqNumber()) + if (getIndex() >= acqOp.acqNumber()) return emitOpError("accessed farther than number of acquired elements " "(index out of bounds)."); @@ -1217,9 +1216,8 @@ LogicalResult xilinx::AIE::MemOp::verify() { for (auto &bodyOp : body.getOps()) { // check for duplicate DMA channels within the same MemOp if (auto dmaStart = dyn_cast(bodyOp)) { - xilinx::AIE::DMAChannel dmaChan = { - dmaStart.getChannelDir(), - static_cast(dmaStart.getChannelIndex())}; + xilinx::AIE::DMAChannel dmaChan = {dmaStart.getChannelDir(), + dmaStart.getChannelIndex()}; if (usedChannels.count(dmaChan)) return dmaStart.emitOpError() << "duplicate DMA channel " @@ -1446,8 +1444,7 @@ LogicalResult xilinx::AIE::LockOp::verify() { if (getLockID().has_value()) { const auto &targetModel = xilinx::AIE::getTargetModel(getTileOp()); auto tileOp = getTileOp(); - uint32_t numLocks = - targetModel.getNumLocks(tileOp.getCol(), tileOp.getRow()); + int numLocks = targetModel.getNumLocks(tileOp.getCol(), tileOp.getRow()); if (getLockID().value() >= numLocks) return emitOpError("lock assigned invalid id (maximum is ") << numLocks - 1 << ")"; @@ -1477,7 +1474,7 @@ struct AcquireReleaseOneStateInDMABlock { auto block = op->getBlock(); int acqValue = -1, relValue = -1; for (auto op : block->getOps()) { - if (op.acquire() || op.acquire_ge()) { + if (op.acquire() || op.acquireGE()) { if (acqValue != -1 && acqValue != op.getLockValue()) { return failure(); } @@ -1513,7 +1510,7 @@ LogicalResult xilinx::AIE::UseLockOp::verify() { return (*this)->emitOpError("must be used in a core or memory operation."); const auto &targetModel = getTargetModel(*this); - if (targetModel.getTargetArch() == xilinx::AIE::AIEArch::AIE1 && acquire_ge()) + if (targetModel.getTargetArch() == xilinx::AIE::AIEArch::AIE1 && acquireGE()) return (*this)->emitOpError( "AcquireGreaterEqual is not supported in AIE1."); diff --git a/lib/Dialect/AIE/IR/AIETargetModel.cpp b/lib/Dialect/AIE/IR/AIETargetModel.cpp index bb674e2373..83e1ad13ca 100644 --- a/lib/Dialect/AIE/IR/AIETargetModel.cpp +++ b/lib/Dialect/AIE/IR/AIETargetModel.cpp @@ -540,13 +540,13 @@ void AIETargetModel::validate() const { } // Every tile in a memtile row must be a memtile. - for (int i = 1; i < 1 + (int)getNumMemTileRows(); i++) + for (int i = 1; i < 1 + getNumMemTileRows(); i++) for (int j = 0; j < columns(); j++) assert(isMemTile(j, i) && !isShimPLTile(j, i) && !isShimNOCTile(j, i) && !isCoreTile(j, i)); // Every other tile is a coretile. - for (int i = 1 + (int)getNumMemTileRows(); i < rows(); i++) + for (int i = 1 + getNumMemTileRows(); i < rows(); i++) for (int j = 0; j < columns(); j++) assert(!isMemTile(j, i) && !isShimPLTile(j, i) && !isShimNOCTile(j, i) && isCoreTile(j, i)); diff --git a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp index 5594655314..85b7b58b92 100644 --- a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp +++ b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp @@ -59,12 +59,12 @@ struct AIEAssignBufferAddressesPass } for (auto tile : device.getOps()) { - const auto &target_model = getTargetModel(tile); + const auto &targetModel = getTargetModel(tile); int max_data_memory_size = 0; if (tile.isMemTile()) - max_data_memory_size = target_model.getMemTileSize(); + max_data_memory_size = targetModel.getMemTileSize(); else - max_data_memory_size = target_model.getLocalMemorySize(); + max_data_memory_size = targetModel.getLocalMemorySize(); SmallVector buffers; // Collect all the buffers for this tile. for (auto buffer : device.getOps()) diff --git a/lib/Dialect/AIE/Transforms/AIECoreToStandard.cpp b/lib/Dialect/AIE/Transforms/AIECoreToStandard.cpp index b8f8a5b139..728ef33639 100644 --- a/lib/Dialect/AIE/Transforms/AIECoreToStandard.cpp +++ b/lib/Dialect/AIE/Transforms/AIECoreToStandard.cpp @@ -201,19 +201,19 @@ struct AIEUseLockToStdLowering : public OpConversionPattern { if (!device) { return module.emitOpError("Device Not found!"); } - const auto &target_model = device.getTargetModel(); + const auto &targetModel = device.getTargetModel(); // Generate the intrinsic name std::string funcName = ""; - if (target_model.getTargetArch() == AIEArch::AIE1) + if (targetModel.getTargetArch() == AIEArch::AIE1) funcName = "llvm.aie.lock."; else funcName = "llvm.aie2."; - if (useLock.acquire() || useLock.acquire_ge()) + if (useLock.acquire() || useLock.acquireGE()) funcName += "acquire"; else if (useLock.release()) funcName += "release"; - if (target_model.getTargetArch() == AIEArch::AIE1) + if (targetModel.getTargetArch() == AIEArch::AIE1) funcName += ".reg"; auto useLockFunc = module.lookupSymbol(funcName); @@ -224,7 +224,7 @@ struct AIEUseLockToStdLowering : public OpConversionPattern { auto lockValue = useLock.getLockValue(); // AIE2 acquire greater equal is encoded as a negative value. - if (useLock.acquire_ge()) { + if (useLock.acquireGE()) { lockValue = -lockValue; } args.push_back(rewriter.create( @@ -379,9 +379,9 @@ struct AIECoreToStandardPass signalPassFailure(); } DeviceOp device = *(m.getOps().begin()); - const auto &target_model = device.getTargetModel(); + const auto &targetModel = device.getTargetModel(); const char *triple; - switch (target_model.getTargetArch()) { + switch (targetModel.getTargetArch()) { case AIEArch::AIE1: triple = "aie"; break; diff --git a/lib/Dialect/AIE/Transforms/AIECreatePacketFlows.cpp b/lib/Dialect/AIE/Transforms/AIECreatePacketFlows.cpp index b1419a09fb..66ba853629 100644 --- a/lib/Dialect/AIE/Transforms/AIECreatePacketFlows.cpp +++ b/lib/Dialect/AIE/Transforms/AIECreatePacketFlows.cpp @@ -167,7 +167,6 @@ void buildPSRoute( int yCur = ySrc; WireBundle curBundle; int curChannel; - int xLast, yLast; WireBundle lastBundle; Port lastPort = sourcePort; @@ -180,9 +179,6 @@ void buildPSRoute( LLVM_DEBUG(llvm::dbgs() << "Tile " << xCur << " " << yCur << " "); TileID curCoord = {xCur, yCur}; - xLast = xCur; - yLast = yCur; - SmallVector moves; if (xCur < xDest) diff --git a/lib/Dialect/AIE/Transforms/AIECreatePathFindFlows.cpp b/lib/Dialect/AIE/Transforms/AIECreatePathFindFlows.cpp index f8eaa847f6..798c687b9e 100644 --- a/lib/Dialect/AIE/Transforms/AIECreatePathFindFlows.cpp +++ b/lib/Dialect/AIE/Transforms/AIECreatePathFindFlows.cpp @@ -119,7 +119,7 @@ class DynamicTileAnalysis { << ")" << stringifyWireBundle(srcPort.bundle) << srcPort.channel << " -> (" << dstCoords.col << ", " << dstCoords.row << ")" << stringifyWireBundle(dstPort.bundle) - << (int)dstPort.channel << "\n"); + << dstPort.channel << "\n"); pathfinder.addFlow(srcCoords, srcPort, dstCoords, dstPort); } @@ -288,7 +288,7 @@ struct ConvertFlowsToInterconnect : public OpConversionPattern { << ", " << srcCoords.row << ")" << stringifyWireBundle(srcBundle) << srcChannel << " -> (" << dstCoords.col << ", " << dstCoords.row << ")" << stringifyWireBundle(dstBundle) - << (int)dstChannel << "\n\t"); + << dstChannel << "\n\t"); #endif // if the flow (aka "net") for this FlowOp hasn't been processed yet, @@ -536,14 +536,14 @@ struct AIEPathfinderPass bool attemptFixupMemTileRouting(OpBuilder builder, SwitchboxOp memtileSwOp, SwitchboxOp northSwOp, SwitchboxOp southSwOp, ConnectOp &problemConnect) { - unsigned problemNorthChannel; + int problemNorthChannel; if (problemConnect.getSourceBundle() == WireBundle::North) { problemNorthChannel = problemConnect.getSourceChannel(); } else if (problemConnect.getDestBundle() == WireBundle::North) { problemNorthChannel = problemConnect.getDestChannel(); } else return false; // Problem is not about n-s routing - unsigned problemSouthChannel; + int problemSouthChannel; if (problemConnect.getSourceBundle() == WireBundle::South) { problemSouthChannel = problemConnect.getSourceChannel(); } else if (problemConnect.getDestBundle() == WireBundle::South) { @@ -574,15 +574,15 @@ struct AIEPathfinderPass bool reconnectConnectOps(OpBuilder builder, SwitchboxOp sw, ConnectOp problemConnect, bool isIncomingToSW, - WireBundle problemBundle, unsigned ProblemChan, - unsigned emptyChan) { + WireBundle problemBundle, int problemChan, + int emptyChan) { bool hasEmptyChannelSlot = true; bool foundCandidateForFixup = false; ConnectOp candidate; if (isIncomingToSW) { for (ConnectOp connect : sw.getOps()) { if (connect.getDestBundle() == problemBundle && - connect.getDestChannel() == ProblemChan) { + connect.getDestChannel() == problemChan) { candidate = connect; foundCandidateForFixup = true; } @@ -594,7 +594,7 @@ struct AIEPathfinderPass } else { for (ConnectOp connect : sw.getOps()) { if (connect.getSourceBundle() == problemBundle && - connect.getSourceChannel() == ProblemChan) { + connect.getSourceChannel() == problemChan) { candidate = connect; foundCandidateForFixup = true; } diff --git a/lib/Dialect/AIE/Transforms/AIEFindFlows.cpp b/lib/Dialect/AIE/Transforms/AIEFindFlows.cpp index 72e7fec4c7..fec54b3fc8 100644 --- a/lib/Dialect/AIE/Transforms/AIEFindFlows.cpp +++ b/lib/Dialect/AIE/Transforms/AIEFindFlows.cpp @@ -98,7 +98,7 @@ class ConnectivityAnalysis { LLVM_DEBUG(llvm::dbgs() << "Packet From: " << stringifyWireBundle(connectOp.sourcePort().bundle) << " " - << (int)sourcePort.channel << "\n"); + << sourcePort.channel << "\n"); for (auto masterSetOp : b.getOps()) for (Value amsel : masterSetOp.getAmsels()) for (auto ruleOp : @@ -160,7 +160,7 @@ class ConnectivityAnalysis { LLVM_DEBUG(llvm::dbgs() << "getConnectedTile(" << stringifyWireBundle(port.bundle) << " " - << (int)port.channel << ")"); + << port.channel << ")"); LLVM_DEBUG(tileOp.dump()); // The accumulated result; @@ -257,9 +257,9 @@ static void findFlowsFrom(AIE::TileOp op, ConnectivityAnalysis &analysis, OpBuilder::InsertPoint ip = rewriter.saveInsertionPoint(); rewriter.setInsertionPoint(flowOp.getPorts().front().getTerminator()); rewriter.create(Op->getLoc(), Op->getResult(0), - bundle, (int)i); + bundle, i); rewriter.create(Op->getLoc(), destOp->getResult(0), - destPort.bundle, (int)destPort.channel); + destPort.bundle, destPort.channel); rewriter.restoreInsertionPoint(ip); } } diff --git a/lib/Dialect/AIE/Transforms/AIELocalizeLocks.cpp b/lib/Dialect/AIE/Transforms/AIELocalizeLocks.cpp index f6300b1a1a..211305d671 100644 --- a/lib/Dialect/AIE/Transforms/AIELocalizeLocks.cpp +++ b/lib/Dialect/AIE/Transforms/AIELocalizeLocks.cpp @@ -37,7 +37,7 @@ struct AIELocalizeLocksPass for (auto coreOp : deviceOp.getOps()) { // Collect the locks used in this core. - const auto &target_model = xilinx::AIE::getTargetModel(coreOp); + const auto &targetModel = xilinx::AIE::getTargetModel(coreOp); TileOp thisTile = dyn_cast(coreOp.getTile().getDefiningOp()); int col = thisTile.colIndex(); @@ -49,7 +49,7 @@ struct AIELocalizeLocksPass int dstCol = tile.colIndex(); int dstRow = tile.rowIndex(); - if (target_model.isLegalMemAffinity(col, row, dstCol, dstRow)) + if (targetModel.isLegalMemAffinity(col, row, dstCol, dstRow)) accessibleTiles.push_back(tile); } @@ -58,17 +58,17 @@ struct AIELocalizeLocksPass int dstRow = tile.rowIndex(); int cardinalMemOffset = 0; - const auto &target_model = xilinx::AIE::getTargetModel(tile); - int numLocks = target_model.getNumLocks(dstCol, dstRow); + const auto &targetModel = xilinx::AIE::getTargetModel(tile); + int numLocks = targetModel.getNumLocks(dstCol, dstRow); for (auto user : tile.getResult().getUsers()) if (auto lock = dyn_cast(user)) { - if (target_model.isMemSouth(col, row, dstCol, dstRow)) + if (targetModel.isMemSouth(col, row, dstCol, dstRow)) cardinalMemOffset = 0; - else if (target_model.isMemWest(col, row, dstCol, dstRow)) + else if (targetModel.isMemWest(col, row, dstCol, dstRow)) cardinalMemOffset = numLocks; - else if (target_model.isMemNorth(col, row, dstCol, dstRow)) + else if (targetModel.isMemNorth(col, row, dstCol, dstRow)) cardinalMemOffset = 2 * numLocks; - else if (target_model.isMemEast(col, row, dstCol, dstRow)) + else if (targetModel.isMemEast(col, row, dstCol, dstRow)) cardinalMemOffset = 3 * numLocks; else llvm_unreachable("Found illegal lock user!"); diff --git a/lib/Dialect/AIE/Transforms/AIEObjectFifoStatefulTransform.cpp b/lib/Dialect/AIE/Transforms/AIEObjectFifoStatefulTransform.cpp index c3a063511a..a7daf18548 100644 --- a/lib/Dialect/AIE/Transforms/AIEObjectFifoStatefulTransform.cpp +++ b/lib/Dialect/AIE/Transforms/AIEObjectFifoStatefulTransform.cpp @@ -72,9 +72,9 @@ class LockAnalysis { /// Given a tile, returns next usable lockID for that tile. int getLockID(TileOp &tileOp) { - const auto &target_model = xilinx::AIE::getTargetModel(tileOp); + const auto &targetModel = xilinx::AIE::getTargetModel(tileOp); for (unsigned i = 0; - i < target_model.getNumLocks(tileOp.getCol(), tileOp.getRow()); i++) { + i < targetModel.getNumLocks(tileOp.getCol(), tileOp.getRow()); i++) { int usageCnt = locksPerTile[{tileOp, i}]; if (usageCnt == 0) { locksPerTile[{tileOp, i}] = 1; @@ -178,24 +178,24 @@ struct AIEObjectFifoStatefulTransformPass /// * 1 if it is that of the second input tile, /// * 0 is no memory module is shared. bool isSharedMemory(TileOp a, TileOp b, int *share_direction) { - const auto &target_model = getTargetModel(a.getOperation()); + const auto &targetModel = getTargetModel(a.getOperation()); if ((a.isShimTile() && !b.isShimTile()) || (!a.isShimTile() && b.isShimTile())) { *share_direction = 0; return false; } - if ((target_model.isMemTile(a.getCol(), a.getRow()) && - !target_model.isMemTile(b.getCol(), b.getRow())) || - (!target_model.isMemTile(a.getCol(), a.getRow()) && - target_model.isMemTile(b.getCol(), b.getRow()))) { + if ((targetModel.isMemTile(a.getCol(), a.getRow()) && + !targetModel.isMemTile(b.getCol(), b.getRow())) || + (!targetModel.isMemTile(a.getCol(), a.getRow()) && + targetModel.isMemTile(b.getCol(), b.getRow()))) { *share_direction = 0; return false; } - bool rightShared = target_model.isLegalMemAffinity( + bool rightShared = targetModel.isLegalMemAffinity( a.colIndex(), a.rowIndex(), b.colIndex(), b.rowIndex()); - bool leftShared = target_model.isLegalMemAffinity( + bool leftShared = targetModel.isLegalMemAffinity( b.colIndex(), b.rowIndex(), a.colIndex(), a.rowIndex()); if (leftShared) @@ -713,7 +713,7 @@ struct AIEObjectFifoStatefulTransformPass if (fifoIn.name() == op.name()) break; else - extraOffset += (int)getMemrefTypeSize(elemType); + extraOffset += getMemrefTypeSize(elemType); } } } else if (linkOp->isDistribute()) { @@ -731,7 +731,7 @@ struct AIEObjectFifoStatefulTransformPass if (fifoOut.name() == op.name()) break; else - extraOffset += (int)getMemrefTypeSize(elemType); + extraOffset += getMemrefTypeSize(elemType); } } } else { diff --git a/lib/Dialect/AIE/Utils/AIENetlistAnalysis.cpp b/lib/Dialect/AIE/Utils/AIENetlistAnalysis.cpp index fa0f25849a..85cbc18291 100644 --- a/lib/Dialect/AIE/Utils/AIENetlistAnalysis.cpp +++ b/lib/Dialect/AIE/Utils/AIENetlistAnalysis.cpp @@ -54,8 +54,8 @@ void xilinx::AIE::NetlistAnalysis::collectDMAUsage() { Block *endBlock = &r.back(); for (auto op : r.getOps()) { auto dmaSt = dyn_cast(op.getCondition().getDefiningOp()); - xilinx::AIE::DMAChannel dmaChan = { - dmaSt.getChannelDir(), static_cast(dmaSt.getChannelIndex())}; + xilinx::AIE::DMAChannel dmaChan = {dmaSt.getChannelDir(), + dmaSt.getChannelIndex()}; dmas[{mem, dmaChan}] = dmaSt; Block *firstBd = op.getTrueDest(); Block *curBd = firstBd; diff --git a/lib/Dialect/AIEX/Transforms/AIECreateLocks.cpp b/lib/Dialect/AIEX/Transforms/AIECreateLocks.cpp index d9eedafb1b..37f81a9afd 100644 --- a/lib/Dialect/AIEX/Transforms/AIECreateLocks.cpp +++ b/lib/Dialect/AIEX/Transforms/AIECreateLocks.cpp @@ -117,9 +117,9 @@ struct Token2LockLowering : public OpConversionPattern { static int getLockID(DenseMap, int> &locks, Operation *op) { auto tileOp = cast(op); - const auto &target_model = xilinx::AIE::getTargetModel(op); + const auto &targetModel = xilinx::AIE::getTargetModel(op); for (unsigned i = 0; - i < target_model.getNumLocks(tileOp.getCol(), tileOp.getRow()); i++) { + i < targetModel.getNumLocks(tileOp.getCol(), tileOp.getRow()); i++) { int usageCnt = locks[std::make_pair(tileOp, i)]; if (usageCnt == 0) { locks[std::make_pair(tileOp, i)] = 1; diff --git a/lib/Dialect/AIEX/Utils/AIETokenAnalysis.cpp b/lib/Dialect/AIEX/Utils/AIETokenAnalysis.cpp index adb39f571f..3a7b8b735b 100644 --- a/lib/Dialect/AIEX/Utils/AIETokenAnalysis.cpp +++ b/lib/Dialect/AIEX/Utils/AIETokenAnalysis.cpp @@ -174,12 +174,12 @@ Operation *xilinx::AIEX::TokenAnalysis::getShareableTileOp(Operation *Op1, int col2 = coord2.col; int row2 = coord2.row; - const auto &target_model = xilinx::AIE::getTargetModel(Op1); + const auto &targetModel = xilinx::AIE::getTargetModel(Op1); bool IsOp1ShareableMem = - IsOp1Mem && target_model.isLegalMemAffinity(col2, row2, col1, row1); + IsOp1Mem && targetModel.isLegalMemAffinity(col2, row2, col1, row1); bool IsOp2ShareableMem = - IsOp2Mem && target_model.isLegalMemAffinity(col1, row1, col2, row2); + IsOp2Mem && targetModel.isLegalMemAffinity(col1, row1, col2, row2); if (IsOp1ShareableMem) return tiles[coord1]; @@ -188,11 +188,11 @@ Operation *xilinx::AIEX::TokenAnalysis::getShareableTileOp(Operation *Op1, // both Op1 and Op2 are core ops if (!IsOp1Mem && !IsOp2Mem) { - bool IsS = target_model.isSouth(col1, row1, col2, row2); - bool IsW = target_model.isWest(col1, row1, col2, row2); - bool IsN = target_model.isNorth(col1, row1, col2, row2); - bool IsE = target_model.isEast(col1, row1, col2, row2); - bool IsInternal = target_model.isInternal(col1, row1, col2, row2); + bool IsS = targetModel.isSouth(col1, row1, col2, row2); + bool IsW = targetModel.isWest(col1, row1, col2, row2); + bool IsN = targetModel.isNorth(col1, row1, col2, row2); + bool IsE = targetModel.isEast(col1, row1, col2, row2); + bool IsInternal = targetModel.isInternal(col1, row1, col2, row2); bool IsEvenRow = ((row1 % 2) == 0); // FIXME: This logic appears AIE1 specific. diff --git a/lib/Targets/AIEFlowsToJSON.cpp b/lib/Targets/AIEFlowsToJSON.cpp index cdf74c8a0d..d105bae155 100644 --- a/lib/Targets/AIEFlowsToJSON.cpp +++ b/lib/Targets/AIEFlowsToJSON.cpp @@ -47,8 +47,7 @@ WireBundle getConnectingBundle(WireBundle bundle) { } // returns coordinates in the direction indicated by bundle -std::pair getNextCoords(uint32_t col, uint32_t row, - WireBundle bundle) { +TileID getNextCoords(int col, int row, WireBundle bundle) { switch (bundle) { case WireBundle::North: return {col, row + 1}; @@ -99,8 +98,8 @@ mlir::LogicalResult AIEFlowsToJSON(ModuleOp module, raw_ostream &output) { // write routing demand info uint32_t connectCounts[10]; - for (unsigned int &connect_count : connectCounts) - connect_count = 0; + for (auto &connectCount : connectCounts) + connectCount = 0; for (ConnectOp connectOp : switchboxOp.getOps()) connectCounts[int(connectOp.getDestBundle())]++; @@ -124,8 +123,7 @@ mlir::LogicalResult AIEFlowsToJSON(ModuleOp module, raw_ostream &output) { std::set> flowSources; for (FlowOp flowOp : targetOp.getOps()) { // objects used to trace through the flow - Port currPort = {flowOp.getSourceBundle(), - static_cast(flowOp.getSourceChannel())}; + Port currPort = {flowOp.getSourceBundle(), flowOp.getSourceChannel()}; SwitchboxOp currSwitchbox; TileOp source = cast(flowOp.getSource().getDefiningOp()); @@ -185,16 +183,16 @@ mlir::LogicalResult AIEFlowsToJSON(ModuleOp module, raw_ostream &output) { if (connectOp.getSourceBundle() == currPort.bundle && connectOp.getSourceChannel() == currPort.channel) { nextPorts.push({getConnectingBundle(connectOp.getDestBundle()), - static_cast(connectOp.getDestChannel())}); + connectOp.getDestChannel()}); - std::pair next_coords = + TileID nextCoords = getNextCoords(currSwitchbox.colIndex(), currSwitchbox.rowIndex(), connectOp.getDestBundle()); // search for next switchbox to connect to for (SwitchboxOp switchboxOp : targetOp.getOps()) { - if (uint32_t(switchboxOp.colIndex()) == next_coords.first && - uint32_t(switchboxOp.rowIndex()) == next_coords.second) { + if (switchboxOp.colIndex() == nextCoords.col && + switchboxOp.rowIndex() == nextCoords.row) { nextSwitches.push(switchboxOp); break; } diff --git a/lib/Targets/AIETargetSimulationFiles.cpp b/lib/Targets/AIETargetSimulationFiles.cpp index ef6a50890d..3fb09c2266 100644 --- a/lib/Targets/AIETargetSimulationFiles.cpp +++ b/lib/Targets/AIETargetSimulationFiles.cpp @@ -380,7 +380,7 @@ mlir::LogicalResult AIETranslateGraphXPE(mlir::ModuleOp module, int row = tileOp.rowIndex(); // NOTE: row == 0 assumes shim always row 0 - if (row == 0 || row > (int)targetOp.getTargetModel().getNumMemTileRows()) + if (row == 0 || row > targetOp.getTargetModel().getNumMemTileRows()) continue; // Skip regular tiles (handled above) output << " mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, - const AIETargetModel &target_model, + const AIETargetModel &targetModel, NetlistAnalysis &NL, DenseMap blockMap) { StringRef enable = "XAIE_ENABLE"; @@ -109,23 +109,23 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, foundBd = true; ShapedType bufferType = op.getBuffer().getType().template cast<::mlir::MemRefType>(); - if (op.isA() && !target_model.isShimNOCTile(col, row)) { + if (op.isA() && !targetModel.isShimNOCTile(col, row)) { BaseAddrA = op.getBufferOp().address(); int bufferCol = op.getBufferOp().getTileOp().colIndex(); int bufferRow = op.getBufferOp().getTileOp().rowIndex(); // Memtile DMAs can access neighboring tiles. - if (target_model.isMemTile(col, row)) { - if (target_model.isWest(col, row, bufferCol, bufferRow)) { + if (targetModel.isMemTile(col, row)) { + if (targetModel.isWest(col, row, bufferCol, bufferRow)) { BaseAddrA += 0x0; - } else if (target_model.isInternal(col, row, bufferCol, bufferRow)) { - BaseAddrA += target_model.getMemTileSize() * 1; - } else if (target_model.isEast(col, row, bufferCol, bufferRow)) { - BaseAddrA += target_model.getMemTileSize() * 2; + } else if (targetModel.isInternal(col, row, bufferCol, bufferRow)) { + BaseAddrA += targetModel.getMemTileSize() * 1; + } else if (targetModel.isEast(col, row, bufferCol, bufferRow)) { + BaseAddrA += targetModel.getMemTileSize() * 2; } } } - if (op.isA() || target_model.isShimNOCTile(col, row)) { + if (op.isA() || targetModel.isShimNOCTile(col, row)) { lenA = op.getLenValue(); bytesA = bufferType.getElementTypeBitWidth() / 8; offsetA = op.getOffsetValue() * bytesA; @@ -144,7 +144,7 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, } } - if (0 != ndims && AIEArch::AIE2 != target_model.getTargetArch()) { + if (0 != ndims && AIEArch::AIE2 != targetModel.getTargetArch()) { return memOp.emitOpError("DMA contains at least one multi-dimensional " "buffer descriptor. This is currently only " "supported for AIE-ML devices."); @@ -167,20 +167,20 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, int lockRow = lock.rowIndex(); int lockID = lock.getLockIDValue(); // Memtile DMAs can access neighboring tiles. - if (target_model.isMemTile(col, row)) { - if (target_model.isWest(col, row, lockCol, lockRow)) { + if (targetModel.isMemTile(col, row)) { + if (targetModel.isWest(col, row, lockCol, lockRow)) { lockID += 0; - } else if (target_model.isInternal(col, row, lockCol, lockRow)) { - lockID += target_model.getNumLocks(lockCol, lockRow) * 1; - } else if (target_model.isEast(col, row, lockCol, lockRow)) { - lockID += target_model.getNumLocks(lockCol, lockRow) * 2; + } else if (targetModel.isInternal(col, row, lockCol, lockRow)) { + lockID += targetModel.getNumLocks(lockCol, lockRow) * 1; + } else if (targetModel.isEast(col, row, lockCol, lockRow)) { + lockID += targetModel.getNumLocks(lockCol, lockRow) * 2; } } - if (op.acquire() || op.acquire_ge()) { + if (op.acquire() || op.acquireGE()) { hasAcq = true; acqLockID = lockID; acqValue = op.getLockValue(); - if (op.acquire_ge()) + if (op.acquireGE()) acqValue = -acqValue; } else if (op.release()) { hasRel = true; @@ -223,7 +223,7 @@ mlir::LogicalResult generateDMAConfig(OpType memOp, raw_ostream &output, } if (0 == ndims) { - if (target_model.isShimNOCTile(col, row)) { + if (targetModel.isShimNOCTile(col, row)) { output << "__mlir_aie_try(XAie_DmaSetAddrLen(" << tileDMAInstRefStr(col, row, bdNum) << ", /* addrA */ " << "mlir_aie_external_get_addr_myBuffer_" << col << row << "_" @@ -317,7 +317,7 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { return module.emitOpError("expected AIE.device operation at toplevel"); } DeviceOp targetOp = *(module.getOps().begin()); - const auto &target_model = targetOp.getTargetModel(); + const auto &targetModel = targetOp.getTargetModel(); NetlistAnalysis NL(targetOp, tiles, cores, mems, locks, buffers, switchboxes); NL.collectTiles(tiles); @@ -331,7 +331,7 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { output << " aie_libxaie_ctx_t *ctx = new aie_libxaie_ctx_t;\n"; output << " if (!ctx)\n"; output << " return 0;\n"; - auto arch = target_model.getTargetArch(); + auto arch = targetModel.getTargetArch(); std::string AIE1_device("XAIE_DEV_GEN_AIE"); std::string AIE2_device("XAIE_DEV_GEN_AIEML"); std::string device; @@ -355,21 +355,20 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { output << " ctx->AieConfigPtr.BaseAddr = 0x20000000000;\n"; output << " ctx->AieConfigPtr.ColShift = " << col_shift << ";\n"; output << " ctx->AieConfigPtr.RowShift = " << row_shift << ";\n"; - output << " ctx->AieConfigPtr.NumRows = " << target_model.rows() << ";\n"; - output << " ctx->AieConfigPtr.NumCols = " << target_model.columns() << ";\n"; + output << " ctx->AieConfigPtr.NumRows = " << targetModel.rows() << ";\n"; + output << " ctx->AieConfigPtr.NumCols = " << targetModel.columns() << ";\n"; output << " ctx->AieConfigPtr.ShimRowNum = 0;\n"; output << " ctx->AieConfigPtr.MemTileRowStart = 1;\n"; output << " ctx->AieConfigPtr.MemTileNumRows = " - << target_model.getNumMemTileRows() << ";\n"; + << targetModel.getNumMemTileRows() << ";\n"; output << " // ctx->AieConfigPtr.ReservedRowStart = " "XAIE_RES_TILE_ROW_START;\n"; output << " // ctx->AieConfigPtr.ReservedNumRows = XAIE_RES_TILE_NUM_ROWS;\n"; output << " ctx->AieConfigPtr.AieTileRowStart = " - << (1 + target_model.getNumMemTileRows()) << ";\n"; + << (1 + targetModel.getNumMemTileRows()) << ";\n"; output << " ctx->AieConfigPtr.AieTileNumRows = " - << (target_model.rows() - 1 - target_model.getNumMemTileRows()) - << ";\n"; + << (targetModel.rows() - 1 - targetModel.getNumMemTileRows()) << ";\n"; output << " ctx->AieConfigPtr.PartProp = {0};\n"; output << " ctx->DevInst = {0};\n"; output << " return ctx;\n"; @@ -393,7 +392,7 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { output << "__mlir_aie_try(XAie_CoreDisable(" << deviceInstRef << ", " << tileLocStr(col, row) << "));\n"; // Release locks - int numLocks = target_model.getNumLocks(col, row); + int numLocks = targetModel.getNumLocks(col, row); output << "for (int l = 0; l < " << numLocks << "; ++l)\n" << " __mlir_aie_try(XAie_LockRelease(" << deviceInstRef << ", " << tileLocStr(col, row) << ", XAie_LockInit(l, 0x0), 0));\n"; @@ -488,7 +487,7 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { bdNum++; } } - auto result = generateDMAConfig(memOp, output, target_model, NL, blockMap); + auto result = generateDMAConfig(memOp, output, targetModel, NL, blockMap); if (result.failed()) return result; } @@ -525,7 +524,7 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { else blockMap[&block] = evenBdNum++; } - auto result = generateDMAConfig(memOp, output, target_model, NL, blockMap); + auto result = generateDMAConfig(memOp, output, targetModel, NL, blockMap); if (result.failed()) return result; } @@ -589,7 +588,7 @@ mlir::LogicalResult AIETranslateToXAIEV2(ModuleOp module, raw_ostream &output) { output << "int mlir_aie_configure_shimdma_" << col << row << "(" << ctx_p << ") {\n"; - auto result = generateDMAConfig(op, output, target_model, NL, blockMap); + auto result = generateDMAConfig(op, output, targetModel, NL, blockMap); if (result.failed()) return result; output << "return XAIE_OK;\n"; diff --git a/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp b/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp index a412e414b4..2c86b395f0 100644 --- a/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp +++ b/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp @@ -348,8 +348,7 @@ static LogicalResult createLinearizedAccess(CppEmitter &emitter, Value source, ArrayRef stride = memRefType.getShape(); // The stride and indices size must match - if (stride.size() != indices.size() || - (int)stride.size() != memRefType.getRank()) + if (stride.size() != indices.size() || stride.size() != memRefType.getRank()) return failure(); // A stride contains two parts: