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remove more casts and more snake case and reformat cpp in tablegen
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@makslevental
makslevental committed Nov 7, 2023
1 parent 0f78006 commit 026f81c
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Showing 18 changed files with 157 additions and 136 deletions.
66 changes: 48 additions & 18 deletions include/aie/Dialect/AIE/IR/AIEOps.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1044,17 +1044,24 @@ def AIE_LockOp: AIE_Op<"lock", [TileElement]>, Results<(outs Index)> {

let extraClassDeclaration = [{
bool hasName() {
return bool(getOperation()->getAttrOfType<mlir::StringAttr>(mlir::SymbolTable::getSymbolAttrName()));
return bool(getOperation()->getAttrOfType<mlir::StringAttr>(
mlir::SymbolTable::getSymbolAttrName()));
}

mlir::StringAttr name() {
if(auto attr = getOperation()->getAttrOfType<mlir::StringAttr>(mlir::SymbolTable::getSymbolAttrName()))
if (auto attr = getOperation()->getAttrOfType<mlir::StringAttr>(
mlir::SymbolTable::getSymbolAttrName()))
return attr;
emitOpError("does not have '") << mlir::SymbolTable::getSymbolAttrName() << "' attribute specified";
emitOpError("does not have '")
<< mlir::SymbolTable::getSymbolAttrName() << "' attribute specified";
llvm::report_fatal_error("couldn't get name");
}

int getLockIDValue() {
assert(getLockID().has_value() && "Lock has no ID value");
return getLockID().value();
}

int colIndex();
int rowIndex();
TileOp getTileOp();
Expand Down Expand Up @@ -1105,11 +1112,18 @@ def AIE_UseLockOp: AIE_Op<"useLock", []> {

let extraClassDeclaration = [{
bool acquire() { return (getAction() == LockAction::Acquire); }
bool acquire_ge() { return (getAction() == LockAction::AcquireGreaterEqual); }
bool acquireGE() { return (getAction() == LockAction::AcquireGreaterEqual); }
bool release() { return (getAction() == LockAction::Release); }
int getLockValue() { return getValue(); }
int getTimeout() { if(auto val = getBlocking()) return (int)*val; else return 1;}
LockOp getLockOp() { return llvm::dyn_cast<xilinx::AIE::LockOp>(getLock().getDefiningOp()); }
int getTimeout() {
// LockBlocking is an EnumAttr.
if (auto val = getBlocking())
return (int)*val;
return 1;
}
LockOp getLockOp() {
return llvm::dyn_cast<xilinx::AIE::LockOp>(getLock().getDefiningOp());
}
}];
}

Expand All @@ -1134,20 +1148,25 @@ def AIE_BufferOp: AIE_Op<"buffer", [

let extraClassDeclaration = [{
bool hasName() {
return bool(getOperation()->getAttrOfType<mlir::StringAttr>(mlir::SymbolTable::getSymbolAttrName()));
return bool(getOperation()->getAttrOfType<mlir::StringAttr>(
mlir::SymbolTable::getSymbolAttrName()));
}

mlir::StringAttr name() {
if(auto attr = getOperation()->getAttrOfType<mlir::StringAttr>(mlir::SymbolTable::getSymbolAttrName()))
if (auto attr = getOperation()->getAttrOfType<mlir::StringAttr>(
mlir::SymbolTable::getSymbolAttrName()))
return attr;
emitOpError("does not have '") << mlir::SymbolTable::getSymbolAttrName() << "' attribute specified";
emitOpError("does not have '")
<< mlir::SymbolTable::getSymbolAttrName() << "' attribute specified";
llvm::report_fatal_error("couldn't get name");
}

// Return the address of this buffer
int64_t address() {
if(auto attr = getOperation()->getAttrOfType<mlir::IntegerAttr>("address"))
if (auto attr = getOperation()->getAttrOfType<mlir::IntegerAttr>("address"))
return attr.getInt();
emitOpError("does not have 'address' attribute specified");
llvm::report_fatal_error("couldn't address");
}

// Return the number of bytes that need to be allocated for this buffer.
Expand Down Expand Up @@ -1180,13 +1199,17 @@ def AIE_ExternalBufferOp: AIE_Op<"external_buffer", []>, Results<(outs AnyMemRef

let extraClassDeclaration = [{
bool hasName() {
return bool(getOperation()->getAttrOfType<mlir::StringAttr>(mlir::SymbolTable::getSymbolAttrName()));
return bool(getOperation()->getAttrOfType<mlir::StringAttr>(
mlir::SymbolTable::getSymbolAttrName()));
}

mlir::StringAttr name() {
if(auto attr = getOperation()->getAttrOfType<mlir::StringAttr>(mlir::SymbolTable::getSymbolAttrName()))
if (auto attr = getOperation()->getAttrOfType<mlir::StringAttr>(
mlir::SymbolTable::getSymbolAttrName()))
return attr;
emitOpError("does not have '") << mlir::SymbolTable::getSymbolAttrName() << "' attribute specified";
emitOpError("does not have '")
<< mlir::SymbolTable::getSymbolAttrName() << "' attribute specified";
llvm::report_fatal_error("couldn't get name");
}
}];
}
Expand Down Expand Up @@ -1220,7 +1243,9 @@ def AIE_GetStreamOp: AIE_Op<"getStream", [

let extraClassDeclaration = [{
bool isWideStream() { return getStreamValue().getType().isInteger(128); }
bool isFloatStream() { return getStreamValue().getType().isa<mlir::FloatType>(); }
bool isFloatStream() {
return getStreamValue().getType().isa<mlir::FloatType>();
}
}];
}

Expand All @@ -1241,7 +1266,9 @@ def AIE_PutStreamOp: AIE_Op<"putStream", [HasParent<"CoreOp">]> {

let extraClassDeclaration = [{
bool isWideStream() { return getStreamValue().getType().isInteger(128); }
bool isFloatStream() { return getStreamValue().getType().isa<mlir::FloatType>(); }
bool isFloatStream() {
return getStreamValue().getType().isa<mlir::FloatType>();
}
}];
}

Expand Down Expand Up @@ -1406,15 +1433,18 @@ def AIE_ObjectFifoCreateOp: AIE_Op<"objectFifo", [HasParent<"DeviceOp">, Symbol]
let extraClassDeclaration = [{
int size(int index = 0) {
if (llvm::isa<mlir::ArrayAttr>(getElemNumber()))
return llvm::dyn_cast<mlir::IntegerAttr>(llvm::dyn_cast<mlir::ArrayAttr>(getElemNumber())[index]).getInt();
else
return llvm::dyn_cast<mlir::IntegerAttr>(
llvm::dyn_cast<mlir::ArrayAttr>(getElemNumber())[index])
.getInt();
else
return llvm::dyn_cast<mlir::IntegerAttr>(getElemNumber()).getInt();
}

TileOp getProducerTileOp();

mlir::StringAttr name() {
return getOperation()->getAttrOfType<mlir::StringAttr>(mlir::SymbolTable::getSymbolAttrName());
return getOperation()->getAttrOfType<mlir::StringAttr>(
mlir::SymbolTable::getSymbolAttrName());
}
}];

Expand Down
10 changes: 6 additions & 4 deletions include/aie/Dialect/AIEX/IR/AIEX.td
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Original file line number Diff line number Diff line change
Expand Up @@ -337,13 +337,15 @@ def AIE_HerdOp: AIEX_Op<"herd", []>, Results<(outs Index)> {
AIEI32Attr:$height
);
let extraClassDeclaration = [{
int getHerdWidth() { return getWidth(); }
int getHerdHeight() { return getHeight(); }
int getHerdWidth() { return getWidth(); }
int getHerdHeight() { return getHeight(); }
int getNumAIETiles() { return getHerdWidth() * getHerdHeight(); }
mlir::StringAttr name() {
if(auto attr = getOperation()->getAttrOfType<mlir::StringAttr>(mlir::SymbolTable::getSymbolAttrName()))
if (auto attr = getOperation()->getAttrOfType<mlir::StringAttr>(
mlir::SymbolTable::getSymbolAttrName()))
return attr;
emitOpError("does not have '") << mlir::SymbolTable::getSymbolAttrName() << "' attribute specified";
emitOpError("does not have '")
<< mlir::SymbolTable::getSymbolAttrName() << "' attribute specified";
llvm::report_fatal_error("couldn't get name");
}
}];
Expand Down
19 changes: 8 additions & 11 deletions lib/Dialect/AIE/IR/AIEDialect.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -412,9 +412,8 @@ xilinx::AIE::HasValidDMAChannels<ConcreteType>::verifyTrait(Operation *op) {
for (auto &bodyOp : element.getBody().getOps()) {
// check for duplicate DMA channels within the same MemTileDMAOp
if (auto dmaStart = dyn_cast<xilinx::AIE::DMAStartOp>(bodyOp)) {
xilinx::AIE::DMAChannel dmaChan = {
dmaStart.getChannelDir(),
static_cast<int>(dmaStart.getChannelIndex())};
xilinx::AIE::DMAChannel dmaChan = {dmaStart.getChannelDir(),
dmaStart.getChannelIndex()};
if (usedChannels.count(dmaChan))
return dmaStart.emitOpError()
<< "duplicate DMA channel "
Expand Down Expand Up @@ -799,7 +798,7 @@ LogicalResult xilinx::AIE::ObjectFifoSubviewAccessOp::verify() {
return emitOpError("must be called from inside a CoreOp");

ObjectFifoAcquireOp acqOp = getSubview().getDefiningOp<ObjectFifoAcquireOp>();
if ((int)getIndex() >= acqOp.acqNumber())
if (getIndex() >= acqOp.acqNumber())
return emitOpError("accessed farther than number of acquired elements "
"(index out of bounds).");

Expand Down Expand Up @@ -1217,9 +1216,8 @@ LogicalResult xilinx::AIE::MemOp::verify() {
for (auto &bodyOp : body.getOps()) {
// check for duplicate DMA channels within the same MemOp
if (auto dmaStart = dyn_cast<xilinx::AIE::DMAStartOp>(bodyOp)) {
xilinx::AIE::DMAChannel dmaChan = {
dmaStart.getChannelDir(),
static_cast<int>(dmaStart.getChannelIndex())};
xilinx::AIE::DMAChannel dmaChan = {dmaStart.getChannelDir(),
dmaStart.getChannelIndex()};
if (usedChannels.count(dmaChan))
return dmaStart.emitOpError()
<< "duplicate DMA channel "
Expand Down Expand Up @@ -1446,8 +1444,7 @@ LogicalResult xilinx::AIE::LockOp::verify() {
if (getLockID().has_value()) {
const auto &targetModel = xilinx::AIE::getTargetModel(getTileOp());
auto tileOp = getTileOp();
uint32_t numLocks =
targetModel.getNumLocks(tileOp.getCol(), tileOp.getRow());
int numLocks = targetModel.getNumLocks(tileOp.getCol(), tileOp.getRow());
if (getLockID().value() >= numLocks)
return emitOpError("lock assigned invalid id (maximum is ")
<< numLocks - 1 << ")";
Expand Down Expand Up @@ -1477,7 +1474,7 @@ struct AcquireReleaseOneStateInDMABlock {
auto block = op->getBlock();
int acqValue = -1, relValue = -1;
for (auto op : block->getOps<xilinx::AIE::UseLockOp>()) {
if (op.acquire() || op.acquire_ge()) {
if (op.acquire() || op.acquireGE()) {
if (acqValue != -1 && acqValue != op.getLockValue()) {
return failure();
}
Expand Down Expand Up @@ -1513,7 +1510,7 @@ LogicalResult xilinx::AIE::UseLockOp::verify() {
return (*this)->emitOpError("must be used in a core or memory operation.");

const auto &targetModel = getTargetModel(*this);
if (targetModel.getTargetArch() == xilinx::AIE::AIEArch::AIE1 && acquire_ge())
if (targetModel.getTargetArch() == xilinx::AIE::AIEArch::AIE1 && acquireGE())
return (*this)->emitOpError(
"AcquireGreaterEqual is not supported in AIE1.");

Expand Down
4 changes: 2 additions & 2 deletions lib/Dialect/AIE/IR/AIETargetModel.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -540,13 +540,13 @@ void AIETargetModel::validate() const {
}

// Every tile in a memtile row must be a memtile.
for (int i = 1; i < 1 + (int)getNumMemTileRows(); i++)
for (int i = 1; i < 1 + getNumMemTileRows(); i++)
for (int j = 0; j < columns(); j++)
assert(isMemTile(j, i) && !isShimPLTile(j, i) && !isShimNOCTile(j, i) &&
!isCoreTile(j, i));

// Every other tile is a coretile.
for (int i = 1 + (int)getNumMemTileRows(); i < rows(); i++)
for (int i = 1 + getNumMemTileRows(); i < rows(); i++)
for (int j = 0; j < columns(); j++)
assert(!isMemTile(j, i) && !isShimPLTile(j, i) && !isShimNOCTile(j, i) &&
isCoreTile(j, i));
Expand Down
6 changes: 3 additions & 3 deletions lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -59,12 +59,12 @@ struct AIEAssignBufferAddressesPass
}

for (auto tile : device.getOps<TileOp>()) {
const auto &target_model = getTargetModel(tile);
const auto &targetModel = getTargetModel(tile);
int max_data_memory_size = 0;
if (tile.isMemTile())
max_data_memory_size = target_model.getMemTileSize();
max_data_memory_size = targetModel.getMemTileSize();
else
max_data_memory_size = target_model.getLocalMemorySize();
max_data_memory_size = targetModel.getLocalMemorySize();
SmallVector<BufferOp, 4> buffers;
// Collect all the buffers for this tile.
for (auto buffer : device.getOps<BufferOp>())
Expand Down
14 changes: 7 additions & 7 deletions lib/Dialect/AIE/Transforms/AIECoreToStandard.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -201,19 +201,19 @@ struct AIEUseLockToStdLowering : public OpConversionPattern<UseLockOp> {
if (!device) {
return module.emitOpError("Device Not found!");
}
const auto &target_model = device.getTargetModel();
const auto &targetModel = device.getTargetModel();

// Generate the intrinsic name
std::string funcName = "";
if (target_model.getTargetArch() == AIEArch::AIE1)
if (targetModel.getTargetArch() == AIEArch::AIE1)
funcName = "llvm.aie.lock.";
else
funcName = "llvm.aie2.";
if (useLock.acquire() || useLock.acquire_ge())
if (useLock.acquire() || useLock.acquireGE())
funcName += "acquire";
else if (useLock.release())
funcName += "release";
if (target_model.getTargetArch() == AIEArch::AIE1)
if (targetModel.getTargetArch() == AIEArch::AIE1)
funcName += ".reg";

auto useLockFunc = module.lookupSymbol<func::FuncOp>(funcName);
Expand All @@ -224,7 +224,7 @@ struct AIEUseLockToStdLowering : public OpConversionPattern<UseLockOp> {
auto lockValue = useLock.getLockValue();

// AIE2 acquire greater equal is encoded as a negative value.
if (useLock.acquire_ge()) {
if (useLock.acquireGE()) {
lockValue = -lockValue;
}
args.push_back(rewriter.create<arith::IndexCastOp>(
Expand Down Expand Up @@ -379,9 +379,9 @@ struct AIECoreToStandardPass
signalPassFailure();
}
DeviceOp device = *(m.getOps<DeviceOp>().begin());
const auto &target_model = device.getTargetModel();
const auto &targetModel = device.getTargetModel();
const char *triple;
switch (target_model.getTargetArch()) {
switch (targetModel.getTargetArch()) {
case AIEArch::AIE1:
triple = "aie";
break;
Expand Down
4 changes: 0 additions & 4 deletions lib/Dialect/AIE/Transforms/AIECreatePacketFlows.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -167,7 +167,6 @@ void buildPSRoute(
int yCur = ySrc;
WireBundle curBundle;
int curChannel;
int xLast, yLast;
WireBundle lastBundle;
Port lastPort = sourcePort;

Expand All @@ -180,9 +179,6 @@ void buildPSRoute(
LLVM_DEBUG(llvm::dbgs() << "Tile " << xCur << " " << yCur << " ");

TileID curCoord = {xCur, yCur};
xLast = xCur;
yLast = yCur;

SmallVector<WireBundle, 4> moves;

if (xCur < xDest)
Expand Down
16 changes: 8 additions & 8 deletions lib/Dialect/AIE/Transforms/AIECreatePathFindFlows.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -119,7 +119,7 @@ class DynamicTileAnalysis {
<< ")" << stringifyWireBundle(srcPort.bundle)
<< srcPort.channel << " -> (" << dstCoords.col << ", "
<< dstCoords.row << ")" << stringifyWireBundle(dstPort.bundle)
<< (int)dstPort.channel << "\n");
<< dstPort.channel << "\n");
pathfinder.addFlow(srcCoords, srcPort, dstCoords, dstPort);
}

Expand Down Expand Up @@ -288,7 +288,7 @@ struct ConvertFlowsToInterconnect : public OpConversionPattern<AIE::FlowOp> {
<< ", " << srcCoords.row << ")" << stringifyWireBundle(srcBundle)
<< srcChannel << " -> (" << dstCoords.col << ", "
<< dstCoords.row << ")" << stringifyWireBundle(dstBundle)
<< (int)dstChannel << "\n\t");
<< dstChannel << "\n\t");
#endif

// if the flow (aka "net") for this FlowOp hasn't been processed yet,
Expand Down Expand Up @@ -536,14 +536,14 @@ struct AIEPathfinderPass
bool attemptFixupMemTileRouting(OpBuilder builder, SwitchboxOp memtileSwOp,
SwitchboxOp northSwOp, SwitchboxOp southSwOp,
ConnectOp &problemConnect) {
unsigned problemNorthChannel;
int problemNorthChannel;
if (problemConnect.getSourceBundle() == WireBundle::North) {
problemNorthChannel = problemConnect.getSourceChannel();
} else if (problemConnect.getDestBundle() == WireBundle::North) {
problemNorthChannel = problemConnect.getDestChannel();
} else
return false; // Problem is not about n-s routing
unsigned problemSouthChannel;
int problemSouthChannel;
if (problemConnect.getSourceBundle() == WireBundle::South) {
problemSouthChannel = problemConnect.getSourceChannel();
} else if (problemConnect.getDestBundle() == WireBundle::South) {
Expand Down Expand Up @@ -574,15 +574,15 @@ struct AIEPathfinderPass

bool reconnectConnectOps(OpBuilder builder, SwitchboxOp sw,
ConnectOp problemConnect, bool isIncomingToSW,
WireBundle problemBundle, unsigned ProblemChan,
unsigned emptyChan) {
WireBundle problemBundle, int problemChan,
int emptyChan) {
bool hasEmptyChannelSlot = true;
bool foundCandidateForFixup = false;
ConnectOp candidate;
if (isIncomingToSW) {
for (ConnectOp connect : sw.getOps<ConnectOp>()) {
if (connect.getDestBundle() == problemBundle &&
connect.getDestChannel() == ProblemChan) {
connect.getDestChannel() == problemChan) {
candidate = connect;
foundCandidateForFixup = true;
}
Expand All @@ -594,7 +594,7 @@ struct AIEPathfinderPass
} else {
for (ConnectOp connect : sw.getOps<ConnectOp>()) {
if (connect.getSourceBundle() == problemBundle &&
connect.getSourceChannel() == ProblemChan) {
connect.getSourceChannel() == problemChan) {
candidate = connect;
foundCandidateForFixup = true;
}
Expand Down
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