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[beginner] Question about cybersecurity end2end example #953

Answered by fpjentzsch
ArthurEly asked this question in Q&A
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Hi,

  1. Since this is an FPGA development board only (no ARM CPU or PYNQ support), you will have to integrate the "stitched_ip" generated by FINN into your own block design that streams data in/out of the accelerator via the AXI-Stream interfaces. Maybe you could use a softcore processor to feed the data from memory/storage.

  2. The input width of 40 is correct because it is determined by the folding (parallelism) of the first MVAU layer, more specifically the SIMD folding parameter. You could adjust the folding to process more or fewer bits of the 600 bit input in each FPGA clock cycle.

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