Package FINN IP's from Stitch Project

[smtalds]

Hi , i want to deployment finn's ip (like , streaming model , idma and odma ) to another block design.I opened these ip from stitch project and packaged. I recalled and added ip to my block design. But when i want to validate design , gives this error :

What am i missing ?

[fpjentzsch]

Hi,
did you manage to find the problem? My only idea is that "invalid target" refers to an incorrectly specified FPGA part or a part that is incompatible with the one set in the FINN build flow.

[smtalds]

Yes I found the problem. I was getting IPs from a non-ip shared folder. I was trying to use packed IP. When I use ip shared verilog files the problem was solved. (It was so long time ago, i maynot remember)

[JPPalacios]

Hi,

Would you mind walking me through how you integrated your IP into a larger design? Trying to do the same but adding it to the PYNQ base overlay. I have the FINN flow working on hardware so I am simply trying to make PS stuff in the PL like the input end.

Regards,

[smtalds]

I don't remember exactly, but you might be able to use the design in the ip-shared folder. Take all the Verilog files and add your design, but don't use the closed IP. Alternatively, you can change the training bitwidth. When I was using the Z1, I would decrease the bitwidth to get more FPS. If the FPGA is the same, change your IP design. If the IP is the same, then change your FPGA.

I couldn't find any solution in November. Maybe FINN has different updates now. Can you check?

[fpjentzsch]

Maybe this tutorial can help? https://github.com/Xilinx/finn/tree/dev/tutorials/fpga_flow

[JPPalacios]

@smtalds @fpjentzsch Thanks, I was able to generate the Stitched IP. If I do integrate the FINN IP into a larger design, would the FINN Example Overlay class still work? The input end would directly receive MIPI data into the streaming FIFOs instead of it being pre-processed in the PS. The outputs would ideally go to the PS for post-processing before sending frames off to the DP or a matplotlib window. Target board is the Kria KV260.

Note: I've tried the Kria-PYNQ notebooks but there are no working Base Overlay MIPI examples unfortunately, unresolved I2C issues. The smartcam app works just fine on my kria board though so I know this type of work is possible, just prefer if FINN was handling detection over the DPU :)

Thanks for the help once again!

[JPPalacios]

@fpjentzsch Hi,

I imported the Kria-PYNQ MIPI hierarchy block into the FINN Zynq build Vivado project (with i/o dmas + streamdataflow1) and synthesized the design. I had a few questions about generating hardware files, since I am running into implementation errors.

• After synthesis/bitstream generation, how does FINN generate the XDC/HWH files?
• What files would I need to modify to streamline this process for future iterations?

Many thanks for the support!

[fpjentzsch]

FINN takes the bitfile from the location specified here:

finn/src/finn/transformation/fpgadataflow/make_zynq_proj.py

Line 267 in e3087ad

bitfile_name = vivado_pynq_proj_dir + "/finn_zynq_link.runs/impl_1/top_wrapper.bit"

and .hwh file from one of the locations specified here:

finn/src/finn/transformation/fpgadataflow/make_zynq_proj.py

Line 276 in e3087ad

hwh_name_alts = [

That is all information needed for the "FINN Example Overlay" driver (along with the "io_shape_dict").

[JPPalacios]

Hi, I am exploring importing the FINN ZYNQ project (idma, streamdataflow1, odma) into Kria-PYNQ's Base Overlay. I am working out the details on merging the two first by GUI and then by write_bd_tcl command.

This method will most likely use PYNQ custom IP/Hierarchies per their tutorials to bind to FINN IP's. I believe this is where I transfer the functionality of the FINNExampleOverlay into their corresponding blocks, correct? Perhaps this is outside FINN's scope but hoping you may be able to shed some light on this.

Regards,