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Hi All, |
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This is the closest to a guide I have been able to find: https://github.com/jterry-x/finn-examples/tree/main/build/fpga_flow |
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It seems doing this for the TFC network isn't too difficult of a task - the provided code is pretty comprehensive and easy to adapt. However, I can't say the same about the CNV networks (e.g., the CIFAR-10 variant cnv-w1a1). Have you (or anyone) had any luck deploying those networks to an Artix-7 FPGA? I've been able to deploy it, but the accuracy is far lower than expected, like ~60%. |
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This is the closest to a guide I have been able to find: https://github.com/jterry-x/finn-examples/tree/main/build/fpga_flow
It includes a testbench for the generated FINN IP which may be helpful to decipher how data is loaded into and out of the accelerator.
Hope that is useful