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packet buffer size restrictions #248
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tx doesn't really have a concept of packet buffers: all it has is pointers to the start of the packet and the length. Given that, it's clear that you can invent all sorts of arbitrary allocation strategies for your packet data. Since a given txq will always complete requests in FIFO order, a ring is simple and easy. The mapping from app virtual address space to I/O space is arbitrary at page granularity. Hardware does support 'gather' transmits, and 'pages' can be large, but if you're only sending small packets then it's much easier if I just tell you never to cross a 4KB boundary with a single send. It's not the complete truth, but it is the minimal truth |
Thanks for clarification! It's just lines like this one
Confused me. I tried using CTPIO with DMA buffers of size 128 bytes in it indeed worked. Thanks! |
That documentation will be generic, assuming that you're going to be using the NIC for both rx and tx. I guess it also hasn't been updated for a long time: ancient NICs did require 2KB buffers, but on current NICs you can use |
Hello,
I'm sending (only need TX from ef_vi) really small packets using
ef_vi
(say 100 bytes). From the examples and docs it's not really clear whether I must allocate 2KB packet buffers for them inDMA
mode, or can I use smaller ones. InPIO
, as far as I could understand, there is no notion of packet buffer for transmissions, and the only restriction is that the packet is 64-bytes aligned. 2KB buffers seems too wasteful and also I'm worried that this packets gonna be evicted from cache, which will impact performance ofCTPIO
transmissions, since it also requiresDMA
fallback.The text was updated successfully, but these errors were encountered: