diff --git a/etc/examples/nodes/fpga.conf b/etc/examples/nodes/fpga.conf index c1eb49033..5d6b121e5 100644 --- a/etc/examples/nodes/fpga.conf +++ b/etc/examples/nodes/fpga.conf @@ -11,7 +11,7 @@ fpgas = { id = "10ee:7021" slot = "0000:88:00.0" do_reset = true - ips = "../../fpga/etc/vc707-xbar-pcie/vc707-xbar-pcie-dino-v2.json" + ips = "../../fpga/etc/vc707-xbar-pcie/vc707-xbar-pcie-dino.json" polling = false } } diff --git a/etc/fpga/vc707-xbar-pcie-dino/vc707-xbar-pcie-dino.json b/etc/fpga/vc707-xbar-pcie-dino/vc707-xbar-pcie-dino.json index 89d1e7780..78867a12f 100644 --- a/etc/fpga/vc707-xbar-pcie-dino/vc707-xbar-pcie-dino.json +++ b/etc/fpga/vc707-xbar-pcie-dino/vc707-xbar-pcie-dino.json @@ -229,7 +229,7 @@ "c_use_chipscope": "false", "c_drp_if": "false", "transceivercontrol": "false", - "c_use_crc": "false", + "c_use_crc": "true", "supportlevel": 0, "c_use_byteswap": "false", "c_cpll_fbdiv": 2, @@ -367,7 +367,7 @@ "c_use_chipscope": "false", "c_drp_if": "false", "transceivercontrol": "false", - "c_use_crc": "false", + "c_use_crc": "true", "supportlevel": 0, "c_use_byteswap": "false", "c_cpll_fbdiv": 2, @@ -505,7 +505,7 @@ "c_use_chipscope": "false", "c_drp_if": "false", "transceivercontrol": "false", - "c_use_crc": "false", + "c_use_crc": "true", "supportlevel": 0, "c_use_byteswap": "false", "c_cpll_fbdiv": 2, @@ -913,8 +913,8 @@ "m15_s15_connectivity": 1, "component_name": "design_1_xbar_0", "edk_iptype": "PERIPHERAL", - "c_baseaddr": 0, - "c_highaddr": 1023 + "c_baseaddr": 4096, + "c_highaddr": 5119 }, "ports": [ { @@ -969,7 +969,7 @@ }, { "role": "slave", - "target": "dino_dinoif_fast_0:M00_AXIS", + "target": "dino_dinoif_adc_0:M00_AXIS", "name": "S05_AXIS" }, { @@ -1016,32 +1016,44 @@ "vlnv": "xilinx.com:module_ref:dinoif_dac:1.0", "i2c_channel": 1, "parameters": { - "component_name": "design_1_dinoif_dac_0_0", + "component_name": "design_1_dinoif_adc_0_0", "edk_iptype": "PERIPHERAL" }, "ports": [ { - "role": "slave", - "target": "crossbar_axis_interconnect_0_xbar:M05_AXIS", - "name": "S00_AXIS" + "role": "master", + "target": "crossbar_axis_interconnect_0_xbar:S05_AXIS", + "name": "M00_AXIS" } ] }, - "dino_dinoif_fast_0": { + "dino_dinoif_fast_nologic_0": { "vlnv": "xilinx.com:module_ref:dinoif_fast:1.0", "i2c_channel": 0, "parameters": { - "component_name": "design_1_dinoif_fast_0_0", + "component_name": "design_1_dinoif_dac_0_0", "edk_iptype": "PERIPHERAL" }, "ports": [ { - "role": "master", - "target": "crossbar_axis_interconnect_0_xbar:S05_AXIS", - "name": "M00_AXIS" + "role": "slave", + "target": "crossbar_axis_interconnect_0_xbar:M05_AXIS", + "name": "S00_AXIS" } ] }, + "dino_registerif_0": { + "vlnv": "xilinx.com:module_ref:registerif:1.0", + "parameters": { + "c_axi_data_width": 32, + "c_axi_addr_width": 32, + "reg_addr_width": 10, + "component_name": "design_1_registerif_0_0", + "edk_iptype": "PERIPHERAL", + "c_baseaddr": 20480, + "c_highaddr": 21503 + } + }, "dma_pcie_axi_dma_0": { "vlnv": "xilinx.com:ip:axi_dma:7.1", "parameters": { @@ -1130,6 +1142,29 @@ "s2mm_introut": "dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0:1" } }, + "dma_pcie_axi_read_cache_0": { + "vlnv": "xilinx.com:module_ref:axi_read_cache:1.0", + "parameters": { + "c_axi_data_width": 32, + "c_axi_addr_width": 32, + "word_num": 16, + "component_name": "design_1_axi_read_cache_0_0", + "edk_iptype": "PERIPHERAL", + "c_baseaddr": 24576, + "c_highaddr": 25599 + }, + "memory-view": { + "M_AXI": { + "dma_pcie_pcie_axi_pcie_0": { + "BAR0": { + "baseaddr": 0, + "highaddr": 4294967295, + "size": 4294967296 + } + } + } + } + }, "dma_pcie_pcie_axi_pcie_0": { "vlnv": "xilinx.com:ip:axi_pcie:2.9", "parameters": { @@ -1158,7 +1193,7 @@ "c_interrupt_pin": 0, "c_comp_timeout": 0, "c_include_rc": 0, - "c_s_axi_supports_narrow_burst": 0, + "c_s_axi_supports_narrow_burst": 1, "c_include_baroffset_reg": 1, "c_axibar_num": 1, "c_axibar2pciebar_0": 0, @@ -1281,7 +1316,7 @@ "s_axi_data_width": 64, "m_axi_addr_width": 32, "m_axi_data_width": 64, - "s_axi_supports_narrow_burst": "false", + "s_axi_supports_narrow_burst": "true", "bar_64bit": "false", "xlnx_ref_board": "VC707", "pcie_blk_locn": "X1Y0", @@ -1332,6 +1367,20 @@ "highaddr": 17407, "size": 1024 } + }, + "dino_registerif_0": { + "reg0": { + "baseaddr": 20480, + "highaddr": 21503, + "size": 1024 + } + }, + "dma_pcie_axi_read_cache_0": { + "reg0": { + "baseaddr": 24576, + "highaddr": 25599, + "size": 1024 + } } } }, diff --git a/etc/fpga/vc707-xbar-pcie/vc707-xbar-pcie.json b/etc/fpga/vc707-xbar-pcie/vc707-xbar-pcie.json index 2fe40000b..540447f5c 100644 --- a/etc/fpga/vc707-xbar-pcie/vc707-xbar-pcie.json +++ b/etc/fpga/vc707-xbar-pcie/vc707-xbar-pcie.json @@ -1,5 +1,5 @@ { - "aurora_8b10b_ch0": { + "aurora_aurora_8b10b_ch0": { "vlnv": "xilinx.com:ip:aurora_8b10b:11.1", "parameters": { "component_name": "design_1_aurora_8b10b_0_0", @@ -127,17 +127,17 @@ "ports": [ { "role": "master", - "target": "axis_interconnect_0_xbar:S00_AXIS", + "target": "crossbar_axis_interconnect_0_xbar:S00_AXIS", "name": "USER_DATA_M_AXI_RX" }, { "role": "slave", - "target": "axis_interconnect_0_xbar:M00_AXIS", + "target": "crossbar_axis_interconnect_0_xbar:M00_AXIS", "name": "USER_DATA_S_AXI_TX" } ] }, - "aurora_8b10b_ch1": { + "aurora_aurora_8b10b_ch1": { "vlnv": "xilinx.com:ip:aurora_8b10b:11.1", "parameters": { "component_name": "design_1_aurora_8b10b_1_0", @@ -229,7 +229,7 @@ "c_use_chipscope": "false", "c_drp_if": "false", "transceivercontrol": "false", - "c_use_crc": "false", + "c_use_crc": "true", "supportlevel": 0, "c_use_byteswap": "false", "c_cpll_fbdiv": 2, @@ -265,17 +265,17 @@ "ports": [ { "role": "master", - "target": "axis_interconnect_0_xbar:S01_AXIS", + "target": "crossbar_axis_interconnect_0_xbar:S01_AXIS", "name": "USER_DATA_M_AXI_RX" }, { "role": "slave", - "target": "axis_interconnect_0_xbar:M01_AXIS", + "target": "crossbar_axis_interconnect_0_xbar:M01_AXIS", "name": "USER_DATA_S_AXI_TX" } ] }, - "aurora_8b10b_ch2": { + "aurora_aurora_8b10b_ch2": { "vlnv": "xilinx.com:ip:aurora_8b10b:11.1", "parameters": { "component_name": "design_1_aurora_8b10b_3_0", @@ -367,7 +367,7 @@ "c_use_chipscope": "false", "c_drp_if": "false", "transceivercontrol": "false", - "c_use_crc": "false", + "c_use_crc": "true", "supportlevel": 0, "c_use_byteswap": "false", "c_cpll_fbdiv": 2, @@ -403,17 +403,17 @@ "ports": [ { "role": "master", - "target": "axis_interconnect_0_xbar:S02_AXIS", + "target": "crossbar_axis_interconnect_0_xbar:S02_AXIS", "name": "USER_DATA_M_AXI_RX" }, { "role": "slave", - "target": "axis_interconnect_0_xbar:M02_AXIS", + "target": "crossbar_axis_interconnect_0_xbar:M02_AXIS", "name": "USER_DATA_S_AXI_TX" } ] }, - "aurora_8b10b_ch3": { + "aurora_aurora_8b10b_ch3": { "vlnv": "xilinx.com:ip:aurora_8b10b:11.1", "parameters": { "component_name": "design_1_aurora_8b10b_2_0", @@ -505,7 +505,7 @@ "c_use_chipscope": "false", "c_drp_if": "false", "transceivercontrol": "false", - "c_use_crc": "false", + "c_use_crc": "true", "supportlevel": 0, "c_use_byteswap": "false", "c_cpll_fbdiv": 2, @@ -541,104 +541,16 @@ "ports": [ { "role": "master", - "target": "axis_interconnect_0_xbar:S03_AXIS", + "target": "crossbar_axis_interconnect_0_xbar:S03_AXIS", "name": "USER_DATA_M_AXI_RX" }, { "role": "slave", - "target": "axis_interconnect_0_xbar:M03_AXIS", + "target": "crossbar_axis_interconnect_0_xbar:M03_AXIS", "name": "USER_DATA_S_AXI_TX" } ] }, - "axi_dma_0": { - "vlnv": "xilinx.com:ip:axi_dma:7.1", - "parameters": { - "c_s_axi_lite_addr_width": 10, - "c_s_axi_lite_data_width": 32, - "c_dlytmr_resolution": 125, - "c_prmry_is_aclk_async": 0, - "c_enable_multi_channel": 0, - "c_num_mm2s_channels": 1, - "c_num_s2mm_channels": 1, - "c_include_sg": 1, - "c_sg_include_stscntrl_strm": 0, - "c_sg_use_stsapp_length": 0, - "c_sg_length_width": 14, - "c_m_axi_sg_addr_width": 32, - "c_m_axi_sg_data_width": 32, - "c_m_axis_mm2s_cntrl_tdata_width": 32, - "c_s_axis_s2mm_sts_tdata_width": 32, - "c_micro_dma": 0, - "c_include_mm2s": 1, - "c_include_mm2s_sf": 1, - "c_mm2s_burst_size": 16, - "c_m_axi_mm2s_addr_width": 32, - "c_m_axi_mm2s_data_width": 32, - "c_m_axis_mm2s_tdata_width": 32, - "c_include_mm2s_dre": 0, - "c_include_s2mm": 1, - "c_include_s2mm_sf": 1, - "c_s2mm_burst_size": 16, - "c_m_axi_s2mm_addr_width": 32, - "c_m_axi_s2mm_data_width": 32, - "c_s_axis_s2mm_tdata_width": 32, - "c_include_s2mm_dre": 0, - "c_increase_throughput": 0, - "c_family": "virtex7", - "component_name": "design_1_axi_dma_0_0", - "c_addr_width": 32, - "c_single_interface": 0, - "edk_iptype": "PERIPHERAL", - "c_baseaddr": 12288, - "c_highaddr": 13311 - }, - "memory-view": { - "M_AXI_SG": { - "axi_pcie_0": { - "BAR0": { - "baseaddr": 0, - "highaddr": 4294967295, - "size": 4294967296 - } - } - }, - "M_AXI_MM2S": { - "axi_pcie_0": { - "BAR0": { - "baseaddr": 0, - "highaddr": 4294967295, - "size": 4294967296 - } - } - }, - "M_AXI_S2MM": { - "axi_pcie_0": { - "BAR0": { - "baseaddr": 0, - "highaddr": 4294967295, - "size": 4294967296 - } - } - } - }, - "ports": [ - { - "role": "master", - "target": "axis_interconnect_0_xbar:S04_AXIS", - "name": "MM2S" - }, - { - "role": "slave", - "target": "axis_interconnect_0_xbar:M04_AXIS", - "name": "S2MM" - } - ], - "irqs": { - "mm2s_introut": "axi_pcie_intc_0:0", - "s2mm_introut": "axi_pcie_intc_0:1" - } - }, "axi_gpio_0": { "vlnv": "xilinx.com:ip:axi_gpio:2.0", "parameters": { @@ -666,234 +578,13 @@ "c_highaddr": 127 } }, - "axi_pcie_0": { - "vlnv": "xilinx.com:ip:axi_pcie:2.9", + "crossbar_axis_interconnect_0_xbar": { + "vlnv": "xilinx.com:ip:axis_switch:1.1", "parameters": { "c_family": "virtex7", - "c_instance": "design_1_axi_pcie_0_1", - "c_s_axi_id_width": 2, - "c_s_axi_addr_width": 32, - "c_s_axi_data_width": 64, - "c_m_axi_addr_width": 32, - "c_m_axi_data_width": 64, - "c_no_of_lanes": 1, - "c_max_link_speed": 1, - "c_pcie_use_mode": "3.0", - "c_device_id": 28705, - "c_vendor_id": 4334, - "c_class_code": 360448, - "c_ref_clk_freq": 0, - "c_rev_id": 0, - "c_subsystem_id": 7, - "c_subsystem_vendor_id": 4334, - "c_pcie_cap_slot_implemented": 0, - "c_slot_clock_config": "TRUE", - "c_msi_decode_enable": "TRUE", - "c_int_fifo_depth": 0, - "c_num_msi_req": 5, - "c_interrupt_pin": 0, - "c_comp_timeout": 0, - "c_include_rc": 0, - "c_s_axi_supports_narrow_burst": 0, - "c_include_baroffset_reg": 1, - "c_axibar_num": 1, - "c_axibar2pciebar_0": 0, - "c_axibar2pciebar_1": 0, - "c_axibar2pciebar_2": 0, - "c_axibar2pciebar_3": 0, - "c_axibar2pciebar_4": 0, - "c_axibar2pciebar_5": 0, - "c_axibar_as_0": 0, - "c_axibar_as_1": 0, - "c_axibar_as_2": 0, - "c_axibar_as_3": 0, - "c_axibar_as_4": 0, - "c_axibar_as_5": 0, - "c_axibar_0": 0, - "c_axibar_highaddr_0": 4294967295, - "c_axibar_1": 4294967295, - "c_axibar_highaddr_1": 0, - "c_axibar_2": 4294967295, - "c_axibar_highaddr_2": 0, - "c_axibar_3": 4294967295, - "c_axibar_highaddr_3": 0, - "c_axibar_4": 4294967295, - "c_axibar_highaddr_4": 0, - "c_axibar_5": 4294967295, - "c_axibar_highaddr_5": 0, - "c_pciebar_num": 1, - "c_pciebar_as": 0, - "c_pciebar_len_0": 20, - "c_pciebar2axibar_0": 0, - "c_pciebar2axibar_0_sec": 1, - "c_pciebar_len_1": 16, - "c_pciebar2axibar_1": 4294967295, - "c_pciebar2axibar_1_sec": 1, - "c_pciebar_len_2": 16, - "c_pciebar2axibar_2": 4294967295, - "c_pciebar2axibar_2_sec": 1, - "c_pcie_blk_locn": 3, - "c_xlnx_ref_board": "VC707", - "pcie_ext_clk": "FALSE", - "pcie_ext_gt_common": "FALSE", - "ext_ch_gt_drp": "FALSE", - "shared_logic_in_core": "false", - "transceiver_ctrl_status_ports": "FALSE", - "ext_pipe_interface": "FALSE", - "c_device": "xc7vx485t", - "c_speed": -2, - "axi_aclk_loopback": "false", - "no_slv_err": "false", - "c_rp_bar_hide": "FALSE", - "enable_jtag_dbg": "false", - "c_axibar_chk_slv_err": "false", - "reduce_oob_freq": "false", - "component_name": "design_1_axi_pcie_0_1", - "include_rc": "PCI_Express_Endpoint_device", - "ref_clk_freq": "100_MHz", - "slot_clock_config": "true", - "pcie_use_mode": "GES_and_Production", - "no_of_lanes": "X1", - "max_link_speed": "5.0_GT/s", - "vendor_id": 4334, - "device_id": 28705, - "rev_id": 0, - "subsystem_vendor_id": 4334, - "subsystem_id": 7, - "enable_class_code": "true", - "class_code": 360448, - "base_class_menu": "Memory_controller", - "sub_class_interface_menu": "Other_memory_controller", - "bar0_enabled": "true", - "bar1_enabled": "false", - "bar2_enabled": "false", - "bar0_type": "Memory", - "bar1_type": "N/A", - "bar2_type": "N/A", - "bar0_scale": "Megabytes", - "bar1_scale": "N/A", - "bar2_scale": "N/A", - "bar0_size": 1, - "bar1_size": 8, - "bar2_size": 8, - "pciebar2axibar_0": 0, - "pciebar2axibar_1": 4294967295, - "pciebar2axibar_2": 4294967295, - "pciebar2axibar_1_sec": 1, - "pciebar2axibar_0_sec": 1, - "pciebar2axibar_2_sec": 1, - "interrupt_pin": "false", - "msi_decode_enabled": "true", - "num_msi_req": 5, - "int_fifo_depth": 16, - "comp_timeout": "50us", - "include_baroffset_reg": "true", - "axibar_as_0": "false", - "axibar_as_1": "false", - "axibar_as_2": "false", - "axibar_as_3": "false", - "axibar_as_4": "false", - "axibar_as_5": "false", - "axibar_1": 4294967295, - "axibar_2": 4294967295, - "axibar_3": 4294967295, - "axibar_4": 4294967295, - "axibar_5": 4294967295, - "axibar_highaddr_1": 0, - "axibar_highaddr_2": 0, - "axibar_highaddr_3": 0, - "axibar_highaddr_4": 0, - "axibar_highaddr_5": 0, - "axibar2pciebar_0": 0, - "axibar2pciebar_1": 0, - "axibar2pciebar_2": 0, - "axibar2pciebar_3": 0, - "axibar2pciebar_4": 0, - "axibar2pciebar_5": 0, - "baseaddr": 4096, - "highaddr": 8191, - "s_axi_id_width": 2, - "s_axi_addr_width": 32, - "s_axi_data_width": 64, - "m_axi_addr_width": 32, - "m_axi_data_width": 64, - "s_axi_supports_narrow_burst": "false", - "bar_64bit": "false", - "xlnx_ref_board": "VC707", - "pcie_blk_locn": "X1Y0", - "axibar_num": 1, - "en_ext_clk": "false", - "en_ext_gt_common": "false", - "en_ext_ch_gt_drp": "false", - "en_transceiver_status_ports": "false", - "en_ext_pipe_interface": "false", - "rp_bar_hide": "false", - "edk_iptype": "PERIPHERAL", - "axibar_0": 0, - "axibar_highaddr_0": 4294967295 - }, - "memory-view": { - "M_AXI": { - "axi_gpio_0": { - "Reg": { - "baseaddr": 0, - "highaddr": 127, - "size": 128 - } - }, - "axis_interconnect_0_xbar": { - "Reg": { - "baseaddr": 4096, - "highaddr": 5119, - "size": 1024 - } - }, - "axi_pcie_intc_0": { - "reg0": { - "baseaddr": 8192, - "highaddr": 9215, - "size": 1024 - } - }, - "axi_dma_0": { - "Reg": { - "baseaddr": 12288, - "highaddr": 13311, - "size": 1024 - } - } - } - }, - "axi_bars": { - "BAR0": { - "translation": 0, - "baseaddr": 0, - "highaddr": 4294967295, - "size": 4294967296 - } - }, - "pcie_bars": { - "BAR0": { - "translation": 0 - } - } - }, - "axi_pcie_intc_0": { - "vlnv": "xilinx.com:module_ref:axi_pcie_intc:1.0", - "parameters": { - "component_name": "design_1_axi_pcie_intc_0_0", - "edk_iptype": "PERIPHERAL", - "c_baseaddr": 8192, - "c_highaddr": 9215 - } - }, - "axis_interconnect_0_xbar": { - "vlnv": "xilinx.com:ip:axis_switch:1.1", - "parameters": { - "c_family": "virtex7", - "c_num_si_slots": 5, + "c_num_si_slots": 6, "c_log_si_slots": 3, - "c_num_mi_slots": 5, + "c_num_mi_slots": 6, "c_axis_tdata_width": 32, "c_axis_tid_width": 1, "c_axis_tdest_width": 1, @@ -906,15 +597,15 @@ "c_arb_algorithm": 0, "c_output_reg": 0, "c_decoder_reg": 1, - "c_m_axis_connectivity_array": 33554431, - "c_m_axis_basetdest_array": 10, - "c_m_axis_hightdest_array": 10, + "c_m_axis_connectivity_array": 68719476735, + "c_m_axis_basetdest_array": 42, + "c_m_axis_hightdest_array": 42, "c_routing_mode": 1, "c_s_axi_ctrl_addr_width": 7, "c_s_axi_ctrl_data_width": 32, "c_common_clock": 0, - "num_si": 5, - "num_mi": 5, + "num_si": 6, + "num_mi": 6, "routing_mode": 1, "has_tready": 1, "tdata_num_bytes": 4, @@ -1222,60 +913,468 @@ "m15_s15_connectivity": 1, "component_name": "design_1_xbar_0", "edk_iptype": "PERIPHERAL", - "c_baseaddr": 0, - "c_highaddr": 1023 + "c_baseaddr": 4096, + "c_highaddr": 5119 }, "ports": [ { "role": "slave", - "target": "aurora_8b10b_ch0:USER_DATA_M_AXI_RX", + "target": "aurora_aurora_8b10b_ch0:USER_DATA_M_AXI_RX", "name": "S00_AXIS" }, { "role": "master", - "target": "aurora_8b10b_ch0:USER_DATA_S_AXI_TX", + "target": "aurora_aurora_8b10b_ch0:USER_DATA_S_AXI_TX", "name": "M00_AXIS" }, { "role": "slave", - "target": "aurora_8b10b_ch1:USER_DATA_M_AXI_RX", + "target": "aurora_aurora_8b10b_ch1:USER_DATA_M_AXI_RX", "name": "S01_AXIS" }, { "role": "master", - "target": "aurora_8b10b_ch1:USER_DATA_S_AXI_TX", + "target": "aurora_aurora_8b10b_ch1:USER_DATA_S_AXI_TX", "name": "M01_AXIS" }, { "role": "slave", - "target": "aurora_8b10b_ch2:USER_DATA_M_AXI_RX", + "target": "aurora_aurora_8b10b_ch2:USER_DATA_M_AXI_RX", "name": "S02_AXIS" }, { "role": "master", - "target": "aurora_8b10b_ch2:USER_DATA_S_AXI_TX", + "target": "aurora_aurora_8b10b_ch2:USER_DATA_S_AXI_TX", "name": "M02_AXIS" }, { "role": "slave", - "target": "aurora_8b10b_ch3:USER_DATA_M_AXI_RX", + "target": "aurora_aurora_8b10b_ch3:USER_DATA_M_AXI_RX", "name": "S03_AXIS" }, { "role": "master", - "target": "aurora_8b10b_ch3:USER_DATA_S_AXI_TX", + "target": "aurora_aurora_8b10b_ch3:USER_DATA_S_AXI_TX", "name": "M03_AXIS" }, { "role": "slave", - "target": "axi_dma_0:MM2S", + "target": "dma_pcie_axi_dma_0:MM2S", "name": "S04_AXIS" }, { "role": "master", - "target": "axi_dma_0:S2MM", + "target": "dma_pcie_axi_dma_0:S2MM", "name": "M04_AXIS" + }, + { + "role": "slave", + "target": "dino_dinoif_adc_0:M00_AXIS", + "name": "S05_AXIS" + }, + { + "role": "master", + "target": "dino_dinoif_dac_0:S00_AXIS", + "name": "M05_AXIS" } - ] + ], + "num_ports": 6 + }, + "dino_axi_iic_0": { + "vlnv": "xilinx.com:ip:axi_iic:2.1", + "parameters": { + "c_family": "virtex7", + "c_s_axi_addr_width": 9, + "c_s_axi_data_width": 32, + "c_iic_freq": 100000, + "c_ten_bit_adr": 0, + "c_gpo_width": 1, + "c_s_axi_aclk_freq_hz": 125000000, + "c_scl_inertial_delay": 0, + "c_sda_inertial_delay": 0, + "c_sda_level": 1, + "c_smbus_pmbus_host": 0, + "c_disable_setup_violation_check": 0, + "c_static_timing_reg_width": 0, + "c_timing_reg_width": 32, + "c_default_value": 0, + "component_name": "design_1_axi_iic_0_0", + "ten_bit_adr": "7_bit", + "axi_aclk_freq_mhz": "125.0", + "iic_freq_khz": 100, + "use_board_flow": "false", + "iic_board_interface": "Custom", + "edk_iptype": "PERIPHERAL", + "c_baseaddr": 16384, + "c_highaddr": 17407 + }, + "irqs": { + "iic2intc_irpt": "dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0:2" + } + }, + "dino_registerif_0": { + "vlnv": "xilinx.com:module_ref:registerif:1.0", + "parameters": { + "c_axi_data_width": 32, + "c_axi_addr_width": 32, + "reg_addr_width": 10, + "component_name": "design_1_registerif_0_0", + "edk_iptype": "PERIPHERAL", + "c_baseaddr": 20480, + "c_highaddr": 21503 + } + }, + "dma_pcie_axi_dma_0": { + "vlnv": "xilinx.com:ip:axi_dma:7.1", + "parameters": { + "c_s_axi_lite_addr_width": 10, + "c_s_axi_lite_data_width": 32, + "c_dlytmr_resolution": 125, + "c_prmry_is_aclk_async": 0, + "c_enable_multi_channel": 0, + "c_num_mm2s_channels": 1, + "c_num_s2mm_channels": 1, + "c_include_sg": 1, + "c_sg_include_stscntrl_strm": 0, + "c_sg_use_stsapp_length": 0, + "c_sg_length_width": 14, + "c_m_axi_sg_addr_width": 32, + "c_m_axi_sg_data_width": 32, + "c_m_axis_mm2s_cntrl_tdata_width": 32, + "c_s_axis_s2mm_sts_tdata_width": 32, + "c_micro_dma": 0, + "c_include_mm2s": 1, + "c_include_mm2s_sf": 1, + "c_mm2s_burst_size": 16, + "c_m_axi_mm2s_addr_width": 32, + "c_m_axi_mm2s_data_width": 32, + "c_m_axis_mm2s_tdata_width": 32, + "c_include_mm2s_dre": 0, + "c_include_s2mm": 1, + "c_include_s2mm_sf": 1, + "c_s2mm_burst_size": 16, + "c_m_axi_s2mm_addr_width": 32, + "c_m_axi_s2mm_data_width": 32, + "c_s_axis_s2mm_tdata_width": 32, + "c_include_s2mm_dre": 0, + "c_increase_throughput": 0, + "c_family": "virtex7", + "component_name": "design_1_axi_dma_0_0", + "c_addr_width": 32, + "c_single_interface": 0, + "edk_iptype": "PERIPHERAL", + "c_baseaddr": 12288, + "c_highaddr": 13311 + }, + "memory-view": { + "M_AXI_SG": { + "dma_pcie_pcie_axi_pcie_0": { + "BAR0": { + "baseaddr": 0, + "highaddr": 4294967295, + "size": 4294967296 + } + } + }, + "M_AXI_MM2S": { + "dma_pcie_pcie_axi_pcie_0": { + "BAR0": { + "baseaddr": 0, + "highaddr": 4294967295, + "size": 4294967296 + } + } + }, + "M_AXI_S2MM": { + "dma_pcie_pcie_axi_pcie_0": { + "BAR0": { + "baseaddr": 0, + "highaddr": 4294967295, + "size": 4294967296 + } + } + } + }, + "ports": [ + { + "role": "master", + "target": "crossbar_axis_interconnect_0_xbar:S04_AXIS", + "name": "MM2S" + }, + { + "role": "slave", + "target": "crossbar_axis_interconnect_0_xbar:M04_AXIS", + "name": "S2MM" + } + ], + "irqs": { + "mm2s_introut": "dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0:0", + "s2mm_introut": "dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0:1" + } + }, + "dma_pcie_axi_read_cache_0": { + "vlnv": "xilinx.com:module_ref:axi_read_cache:1.0", + "parameters": { + "c_axi_data_width": 32, + "c_axi_addr_width": 32, + "word_num": 16, + "component_name": "design_1_axi_read_cache_0_0", + "edk_iptype": "PERIPHERAL", + "c_baseaddr": 24576, + "c_highaddr": 25599 + }, + "memory-view": { + "M_AXI": { + "dma_pcie_pcie_axi_pcie_0": { + "BAR0": { + "baseaddr": 0, + "highaddr": 4294967295, + "size": 4294967296 + } + } + } + } + }, + "dma_pcie_pcie_axi_pcie_0": { + "vlnv": "xilinx.com:ip:axi_pcie:2.9", + "parameters": { + "c_family": "virtex7", + "c_instance": "design_1_axi_pcie_0_1", + "c_s_axi_id_width": 2, + "c_s_axi_addr_width": 32, + "c_s_axi_data_width": 64, + "c_m_axi_addr_width": 32, + "c_m_axi_data_width": 64, + "c_no_of_lanes": 1, + "c_max_link_speed": 1, + "c_pcie_use_mode": "3.0", + "c_device_id": 28705, + "c_vendor_id": 4334, + "c_class_code": 360448, + "c_ref_clk_freq": 0, + "c_rev_id": 0, + "c_subsystem_id": 7, + "c_subsystem_vendor_id": 4334, + "c_pcie_cap_slot_implemented": 0, + "c_slot_clock_config": "TRUE", + "c_msi_decode_enable": "TRUE", + "c_int_fifo_depth": 0, + "c_num_msi_req": 4, + "c_interrupt_pin": 0, + "c_comp_timeout": 0, + "c_include_rc": 0, + "c_s_axi_supports_narrow_burst": 1, + "c_include_baroffset_reg": 1, + "c_axibar_num": 1, + "c_axibar2pciebar_0": 0, + "c_axibar2pciebar_1": 0, + "c_axibar2pciebar_2": 0, + "c_axibar2pciebar_3": 0, + "c_axibar2pciebar_4": 0, + "c_axibar2pciebar_5": 0, + "c_axibar_as_0": 0, + "c_axibar_as_1": 0, + "c_axibar_as_2": 0, + "c_axibar_as_3": 0, + "c_axibar_as_4": 0, + "c_axibar_as_5": 0, + "c_axibar_0": 0, + "c_axibar_highaddr_0": 4294967295, + "c_axibar_1": 4294967295, + "c_axibar_highaddr_1": 0, + "c_axibar_2": 4294967295, + "c_axibar_highaddr_2": 0, + "c_axibar_3": 4294967295, + "c_axibar_highaddr_3": 0, + "c_axibar_4": 4294967295, + "c_axibar_highaddr_4": 0, + "c_axibar_5": 4294967295, + "c_axibar_highaddr_5": 0, + "c_pciebar_num": 1, + "c_pciebar_as": 0, + "c_pciebar_len_0": 20, + "c_pciebar2axibar_0": 0, + "c_pciebar2axibar_0_sec": 1, + "c_pciebar_len_1": 16, + "c_pciebar2axibar_1": 4294967295, + "c_pciebar2axibar_1_sec": 1, + "c_pciebar_len_2": 16, + "c_pciebar2axibar_2": 4294967295, + "c_pciebar2axibar_2_sec": 1, + "c_pcie_blk_locn": 3, + "c_xlnx_ref_board": "VC707", + "pcie_ext_clk": "FALSE", + "pcie_ext_gt_common": "FALSE", + "ext_ch_gt_drp": "FALSE", + "shared_logic_in_core": "false", + "transceiver_ctrl_status_ports": "FALSE", + "ext_pipe_interface": "FALSE", + "c_device": "xc7vx485t", + "c_speed": -2, + "axi_aclk_loopback": "false", + "no_slv_err": "false", + "c_rp_bar_hide": "FALSE", + "enable_jtag_dbg": "false", + "c_axibar_chk_slv_err": "false", + "reduce_oob_freq": "false", + "component_name": "design_1_axi_pcie_0_1", + "include_rc": "PCI_Express_Endpoint_device", + "ref_clk_freq": "100_MHz", + "slot_clock_config": "true", + "pcie_use_mode": "GES_and_Production", + "no_of_lanes": "X1", + "max_link_speed": "5.0_GT/s", + "vendor_id": 4334, + "device_id": 28705, + "rev_id": 0, + "subsystem_vendor_id": 4334, + "subsystem_id": 7, + "enable_class_code": "true", + "class_code": 360448, + "base_class_menu": "Memory_controller", + "sub_class_interface_menu": "Other_memory_controller", + "bar0_enabled": "true", + "bar1_enabled": "false", + "bar2_enabled": "false", + "bar0_type": "Memory", + "bar1_type": "N/A", + "bar2_type": "N/A", + "bar0_scale": "Megabytes", + "bar1_scale": "N/A", + "bar2_scale": "N/A", + "bar0_size": 1, + "bar1_size": 8, + "bar2_size": 8, + "pciebar2axibar_0": 0, + "pciebar2axibar_1": 4294967295, + "pciebar2axibar_2": 4294967295, + "pciebar2axibar_1_sec": 1, + "pciebar2axibar_0_sec": 1, + "pciebar2axibar_2_sec": 1, + "interrupt_pin": "false", + "msi_decode_enabled": "true", + "num_msi_req": 4, + "int_fifo_depth": 16, + "comp_timeout": "50us", + "include_baroffset_reg": "true", + "axibar_as_0": "false", + "axibar_as_1": "false", + "axibar_as_2": "false", + "axibar_as_3": "false", + "axibar_as_4": "false", + "axibar_as_5": "false", + "axibar_1": 4294967295, + "axibar_2": 4294967295, + "axibar_3": 4294967295, + "axibar_4": 4294967295, + "axibar_5": 4294967295, + "axibar_highaddr_1": 0, + "axibar_highaddr_2": 0, + "axibar_highaddr_3": 0, + "axibar_highaddr_4": 0, + "axibar_highaddr_5": 0, + "axibar2pciebar_0": 0, + "axibar2pciebar_1": 0, + "axibar2pciebar_2": 0, + "axibar2pciebar_3": 0, + "axibar2pciebar_4": 0, + "axibar2pciebar_5": 0, + "baseaddr": 4096, + "highaddr": 8191, + "s_axi_id_width": 2, + "s_axi_addr_width": 32, + "s_axi_data_width": 64, + "m_axi_addr_width": 32, + "m_axi_data_width": 64, + "s_axi_supports_narrow_burst": "true", + "bar_64bit": "false", + "xlnx_ref_board": "VC707", + "pcie_blk_locn": "X1Y0", + "axibar_num": 1, + "en_ext_clk": "false", + "en_ext_gt_common": "false", + "en_ext_ch_gt_drp": "false", + "en_transceiver_status_ports": "false", + "en_ext_pipe_interface": "false", + "rp_bar_hide": "false", + "edk_iptype": "PERIPHERAL", + "axibar_0": 0, + "axibar_highaddr_0": 4294967295 + }, + "memory-view": { + "M_AXI": { + "axi_gpio_0": { + "Reg": { + "baseaddr": 0, + "highaddr": 127, + "size": 128 + } + }, + "crossbar_axis_interconnect_0_xbar": { + "Reg": { + "baseaddr": 4096, + "highaddr": 5119, + "size": 1024 + } + }, + "dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0": { + "reg0": { + "baseaddr": 8192, + "highaddr": 9215, + "size": 1024 + } + }, + "dma_pcie_axi_dma_0": { + "Reg": { + "baseaddr": 12288, + "highaddr": 13311, + "size": 1024 + } + }, + "dino_axi_iic_0": { + "Reg": { + "baseaddr": 16384, + "highaddr": 17407, + "size": 1024 + } + }, + "dino_registerif_0": { + "reg0": { + "baseaddr": 20480, + "highaddr": 21503, + "size": 1024 + } + }, + "dma_pcie_axi_read_cache_0": { + "reg0": { + "baseaddr": 24576, + "highaddr": 25599, + "size": 1024 + } + } + } + }, + "axi_bars": { + "BAR0": { + "translation": 0, + "baseaddr": 0, + "highaddr": 4294967295, + "size": 4294967296 + } + }, + "pcie_bars": { + "BAR0": { + "translation": 0 + } + } + }, + "dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0": { + "vlnv": "xilinx.com:module_ref:axi_pcie_intc:1.0", + "parameters": { + "component_name": "design_1_axi_pcie_intc_0_0", + "edk_iptype": "PERIPHERAL", + "c_baseaddr": 8192, + "c_highaddr": 9215 + } } } diff --git a/etc/fpga/vc707.json b/etc/fpga/vc707.json index a4580d57c..4cfa3e334 100644 --- a/etc/fpga/vc707.json +++ b/etc/fpga/vc707.json @@ -2,9 +2,9 @@ "fpgas": { "vc707": { "id": "10ee:7021", - "slot": "0000:88:00.0", + "slot": "0000:89:00.0", "do_reset": true, - "ips": "vc707-xbar-pcie-dino/vc707-xbar-pcie-dino-v2.json", + "ips": "vc707-xbar-pcie/vc707-xbar-pcie.json", "polling": true, "interface": "pcie" } diff --git a/etc/fpga/zcu106-dino/zcu106-dino.json b/etc/fpga/zcu106-dino/zcu106-dino.json new file mode 100644 index 000000000..3052ae878 --- /dev/null +++ b/etc/fpga/zcu106-dino/zcu106-dino.json @@ -0,0 +1,2485 @@ +{ + "aurora_aurora_8b10b_ch0": { + "vlnv": "xilinx.com:ip:aurora_8b10b:11.1", + "parameters": { + "component_name": "design_1_aurora_8b10b_0_2", + "channel_enable": "X0Y10", + "c_refclk_loc_p": "W10", + "c_refclk_loc_n": "W9", + "c_column_used": "left", + "c_ucolumn_used": "right", + "c_family": "zynquplus", + "c_device": "xczu7ev", + "c_row_used": "None", + "c_xpackage": "ffvc1156", + "c_xspeedgrade": -2, + "c_aurora_lanes": 1, + "c_lane_width": 2, + "c_active_transceiverquads": 1, + "c_start_quad": "Quad_X0Y2", + "c_start_lane": "X0Y10", + "c_refclk_source": "X0Y10 clk1", + "interface_mode": "Framing", + "c_stream": "false", + "dataflow_config": "Duplex", + "backchannel_mode": "Sidebands", + "c_simplex": "false", + "c_simplex_mode": "TX", + "flow_mode": "None", + "c_nfc": "false", + "c_nfc_mode": "IMM", + "c_ufc": "false", + "c_example_simulation": "false", + "c_gtwiz_out": "false", + "c_line_rate": 2, + "cc_line_rate": 2, + "c_refclk_frequency": 250, + "cc_refclk_frequency": 250, + "c_init_clk": "99.990005", + "drp_freq": "50.0000", + "c_gt_loc_1": 1, + "c_gt_loc_2": "X", + "c_gt_loc_3": "X", + "c_gt_loc_4": "X", + "c_gt_loc_5": "X", + "c_gt_loc_6": "X", + "c_gt_loc_7": "X", + "c_gt_loc_8": "X", + "c_gt_loc_9": "X", + "c_gt_loc_10": "X", + "c_gt_loc_11": "X", + "c_gt_loc_12": "X", + "c_gt_loc_13": "X", + "c_gt_loc_14": "X", + "c_gt_loc_15": "X", + "c_gt_loc_16": "X", + "c_gt_loc_17": "X", + "c_gt_loc_18": "X", + "c_gt_loc_19": "X", + "c_gt_loc_20": "X", + "c_gt_loc_21": "X", + "c_gt_loc_22": "X", + "c_gt_loc_23": "X", + "c_gt_loc_24": "X", + "c_gt_loc_25": "X", + "c_gt_loc_26": "X", + "c_gt_loc_27": "X", + "c_gt_loc_28": "X", + "c_gt_loc_29": "X", + "c_gt_loc_30": "X", + "c_gt_loc_31": "X", + "c_gt_loc_32": "X", + "c_gt_loc_33": "X", + "c_gt_loc_34": "X", + "c_gt_loc_35": "X", + "c_gt_loc_36": "X", + "c_gt_loc_37": "X", + "c_gt_loc_38": "X", + "c_gt_loc_39": "X", + "c_gt_loc_40": "X", + "c_gt_loc_41": "X", + "c_gt_loc_42": "X", + "c_gt_loc_43": "X", + "c_gt_loc_44": "X", + "c_gt_loc_45": "X", + "c_gt_loc_46": "X", + "c_gt_loc_47": "X", + "c_gt_loc_48": "X", + "c_gt_clock_1": "GTHQ0", + "c_gt_clock_2": "None", + "c_use_scrambler": "false", + "c_use_chipscope": "false", + "c_drp_if": "false", + "transceivercontrol": "false", + "c_use_crc": "true", + "supportlevel": 1, + "c_use_byteswap": "false", + "c_cpll_fbdiv": 1, + "c_cpll_fbdiv_45": 5, + "c_cpll_refclk_div": 1, + "c_rxoutdiv": 1, + "c_txoutdiv": 1, + "user_interface": "AXI_4_Streaming", + "c_ufcbuswidthselect": 16, + "c_ufcrembuswidthselect": 1, + "c_ufcstrbbuswidthselect": 2, + "c_rembuswidthselect": 1, + "isv7gth": "false", + "gtquadcnt": 1, + "port7dmonitorout": 7, + "is_7series": "false", + "singleend_initclk": "true", + "singleend_gtrefclk": "false", + "c_double_gtrxreset": "false", + "c_doccport_enable": "false", + "is_board": "zcu106", + "usdrpaddr_width": 9, + "usdmon_width": 15, + "txdiffctrl_width": 4, + "ins_loss_nyq": 14, + "rx_eq_mode": "AUTO", + "rx_coupling": "AC", + "rx_termination": "PROGRAMMABLE", + "rx_termination_prog_value": 800, + "rx_ppm_offset": 200, + "edk_iptype": "PERIPHERAL" + }, + "ports": [ + { + "role": "master", + "target": "axis_interconnect_0_xbar:S02_AXIS", + "name": "USER_DATA_M_AXI_RX" + }, + { + "role": "slave", + "target": "axis_interconnect_0_xbar:M02_AXIS", + "name": "USER_DATA_S_AXI_TX" + } + ] + }, + "axi_iic_0": { + "vlnv": "xilinx.com:ip:axi_iic:2.1", + "parameters": { + "c_family": "zynquplus", + "c_s_axi_addr_width": 9, + "c_s_axi_data_width": 32, + "c_iic_freq": 100000, + "c_ten_bit_adr": 0, + "c_gpo_width": 1, + "c_s_axi_aclk_freq_hz": 99990005, + "c_scl_inertial_delay": 0, + "c_sda_inertial_delay": 0, + "c_sda_level": 1, + "c_smbus_pmbus_host": 0, + "c_disable_setup_violation_check": 0, + "c_static_timing_reg_width": 0, + "c_timing_reg_width": 32, + "c_default_value": 0, + "component_name": "design_1_axi_iic_0_0", + "ten_bit_adr": "7_bit", + "axi_aclk_freq_mhz": "99.990005", + "iic_freq_khz": 100, + "use_board_flow": "false", + "iic_board_interface": "Custom", + "edk_iptype": "PERIPHERAL", + "c_baseaddr": 2684551168, + "c_highaddr": 2684616703 + }, + "irqs": { + "iic2intc_irpt": "zynq_zynq_ultra_ps_e_0:2" + } + }, + "axis_interconnect_0_xbar": { + "vlnv": "xilinx.com:ip:axis_switch:1.1", + "parameters": { + "c_family": "zynquplus", + "c_num_si_slots": 4, + "c_log_si_slots": 2, + "c_num_mi_slots": 4, + "c_axis_tdata_width": 128, + "c_axis_tid_width": 1, + "c_axis_tdest_width": 2, + "c_axis_tuser_width": 1, + "c_axis_signal_set": 91, + "c_arb_on_max_xfers": 1, + "c_arb_on_num_cycles": 0, + "c_arb_on_tlast": 0, + "c_include_arbiter": 1, + "c_arb_algorithm": 0, + "c_output_reg": 0, + "c_decoder_reg": 1, + "c_m_axis_connectivity_array": 65535, + "c_m_axis_basetdest_array": 228, + "c_m_axis_hightdest_array": 228, + "c_routing_mode": 1, + "c_s_axi_ctrl_addr_width": 7, + "c_s_axi_ctrl_data_width": 32, + "c_common_clock": 0, + "num_si": 4, + "num_mi": 4, + "routing_mode": 1, + "has_tready": 1, + "tdata_num_bytes": 16, + "has_tstrb": 0, + "has_tkeep": 1, + "has_tlast": 1, + "tid_width": 0, + "tdest_width": 2, + "tuser_width": 0, + "has_aclken": 0, + "arb_on_max_xfers": 1, + "arb_on_num_cycles": 0, + "arb_on_tlast": 0, + "arb_algorithm": 0, + "decoder_reg": 1, + "output_reg": 0, + "common_clock": 0, + "m00_axis_basetdest": 0, + "m01_axis_basetdest": 1, + "m02_axis_basetdest": 2, + "m03_axis_basetdest": 3, + "m04_axis_basetdest": 4, + "m05_axis_basetdest": 5, + "m06_axis_basetdest": 6, + "m07_axis_basetdest": 7, + "m08_axis_basetdest": 8, + "m09_axis_basetdest": 9, + "m10_axis_basetdest": 10, + "m11_axis_basetdest": 11, + "m12_axis_basetdest": 12, + "m13_axis_basetdest": 13, + "m14_axis_basetdest": 14, + "m15_axis_basetdest": 15, + "m00_axis_hightdest": 0, + "m01_axis_hightdest": 1, + "m02_axis_hightdest": 2, + "m03_axis_hightdest": 3, + "m04_axis_hightdest": 4, + "m05_axis_hightdest": 5, + "m06_axis_hightdest": 6, + "m07_axis_hightdest": 7, + "m08_axis_hightdest": 8, + "m09_axis_hightdest": 9, + "m10_axis_hightdest": 10, + "m11_axis_hightdest": 11, + "m12_axis_hightdest": 12, + "m13_axis_hightdest": 13, + "m14_axis_hightdest": 14, + "m15_axis_hightdest": 15, + "m00_s00_connectivity": 1, + "m00_s01_connectivity": 1, + "m00_s02_connectivity": 1, + "m00_s03_connectivity": 1, + "m00_s04_connectivity": 1, + "m00_s05_connectivity": 1, + "m00_s06_connectivity": 1, + "m00_s07_connectivity": 1, + "m00_s08_connectivity": 1, + "m00_s09_connectivity": 1, + "m00_s10_connectivity": 1, + "m00_s11_connectivity": 1, + "m00_s12_connectivity": 1, + "m00_s13_connectivity": 1, + "m00_s14_connectivity": 1, + "m00_s15_connectivity": 1, + "m01_s00_connectivity": 1, + "m01_s01_connectivity": 1, + "m01_s02_connectivity": 1, + "m01_s03_connectivity": 1, + "m01_s04_connectivity": 1, + "m01_s05_connectivity": 1, + "m01_s06_connectivity": 1, + "m01_s07_connectivity": 1, + "m01_s08_connectivity": 1, + "m01_s09_connectivity": 1, + "m01_s10_connectivity": 1, + "m01_s11_connectivity": 1, + "m01_s12_connectivity": 1, + "m01_s13_connectivity": 1, + "m01_s14_connectivity": 1, + "m01_s15_connectivity": 1, + "m02_s00_connectivity": 1, + "m02_s01_connectivity": 1, + "m02_s02_connectivity": 1, + "m02_s03_connectivity": 1, + "m02_s04_connectivity": 1, + "m02_s05_connectivity": 1, + "m02_s06_connectivity": 1, + "m02_s07_connectivity": 1, + "m02_s08_connectivity": 1, + "m02_s09_connectivity": 1, + "m02_s10_connectivity": 1, + "m02_s11_connectivity": 1, + "m02_s12_connectivity": 1, + "m02_s13_connectivity": 1, + "m02_s14_connectivity": 1, + "m02_s15_connectivity": 1, + "m03_s00_connectivity": 1, + "m03_s01_connectivity": 1, + "m03_s02_connectivity": 1, + "m03_s03_connectivity": 1, + "m03_s04_connectivity": 1, + "m03_s05_connectivity": 1, + "m03_s06_connectivity": 1, + "m03_s07_connectivity": 1, + "m03_s08_connectivity": 1, + "m03_s09_connectivity": 1, + "m03_s10_connectivity": 1, + "m03_s11_connectivity": 1, + "m03_s12_connectivity": 1, + "m03_s13_connectivity": 1, + "m03_s14_connectivity": 1, + "m03_s15_connectivity": 1, + "m04_s00_connectivity": 1, + "m04_s01_connectivity": 1, + "m04_s02_connectivity": 1, + "m04_s03_connectivity": 1, + "m04_s04_connectivity": 1, + "m04_s05_connectivity": 1, + "m04_s06_connectivity": 1, + "m04_s07_connectivity": 1, + "m04_s08_connectivity": 1, + "m04_s09_connectivity": 1, + "m04_s10_connectivity": 1, + "m04_s11_connectivity": 1, + "m04_s12_connectivity": 1, + "m04_s13_connectivity": 1, + "m04_s14_connectivity": 1, + "m04_s15_connectivity": 1, + "m05_s00_connectivity": 1, + "m05_s01_connectivity": 1, + "m05_s02_connectivity": 1, + "m05_s03_connectivity": 1, + "m05_s04_connectivity": 1, + "m05_s05_connectivity": 1, + "m05_s06_connectivity": 1, + "m05_s07_connectivity": 1, + "m05_s08_connectivity": 1, + "m05_s09_connectivity": 1, + "m05_s10_connectivity": 1, + "m05_s11_connectivity": 1, + "m05_s12_connectivity": 1, + "m05_s13_connectivity": 1, + "m05_s14_connectivity": 1, + "m05_s15_connectivity": 1, + "m06_s00_connectivity": 1, + "m06_s01_connectivity": 1, + "m06_s02_connectivity": 1, + "m06_s03_connectivity": 1, + "m06_s04_connectivity": 1, + "m06_s05_connectivity": 1, + "m06_s06_connectivity": 1, + "m06_s07_connectivity": 1, + "m06_s08_connectivity": 1, + "m06_s09_connectivity": 1, + "m06_s10_connectivity": 1, + "m06_s11_connectivity": 1, + "m06_s12_connectivity": 1, + "m06_s13_connectivity": 1, + "m06_s14_connectivity": 1, + "m06_s15_connectivity": 1, + "m07_s00_connectivity": 1, + "m07_s01_connectivity": 1, + "m07_s02_connectivity": 1, + "m07_s03_connectivity": 1, + "m07_s04_connectivity": 1, + "m07_s05_connectivity": 1, + "m07_s06_connectivity": 1, + "m07_s07_connectivity": 1, + "m07_s08_connectivity": 1, + "m07_s09_connectivity": 1, + "m07_s10_connectivity": 1, + "m07_s11_connectivity": 1, + "m07_s12_connectivity": 1, + "m07_s13_connectivity": 1, + "m07_s14_connectivity": 1, + "m07_s15_connectivity": 1, + "m08_s00_connectivity": 1, + "m08_s01_connectivity": 1, + "m08_s02_connectivity": 1, + "m08_s03_connectivity": 1, + "m08_s04_connectivity": 1, + "m08_s05_connectivity": 1, + "m08_s06_connectivity": 1, + "m08_s07_connectivity": 1, + "m08_s08_connectivity": 1, + "m08_s09_connectivity": 1, + "m08_s10_connectivity": 1, + "m08_s11_connectivity": 1, + "m08_s12_connectivity": 1, + "m08_s13_connectivity": 1, + "m08_s14_connectivity": 1, + "m08_s15_connectivity": 1, + "m09_s00_connectivity": 1, + "m09_s01_connectivity": 1, + "m09_s02_connectivity": 1, + "m09_s03_connectivity": 1, + "m09_s04_connectivity": 1, + "m09_s05_connectivity": 1, + "m09_s06_connectivity": 1, + "m09_s07_connectivity": 1, + "m09_s08_connectivity": 1, + "m09_s09_connectivity": 1, + "m09_s10_connectivity": 1, + "m09_s11_connectivity": 1, + "m09_s12_connectivity": 1, + "m09_s13_connectivity": 1, + "m09_s14_connectivity": 1, + "m09_s15_connectivity": 1, + "m10_s00_connectivity": 1, + "m10_s01_connectivity": 1, + "m10_s02_connectivity": 1, + "m10_s03_connectivity": 1, + "m10_s04_connectivity": 1, + "m10_s05_connectivity": 1, + "m10_s06_connectivity": 1, + "m10_s07_connectivity": 1, + "m10_s08_connectivity": 1, + "m10_s09_connectivity": 1, + "m10_s10_connectivity": 1, + "m10_s11_connectivity": 1, + "m10_s12_connectivity": 1, + "m10_s13_connectivity": 1, + "m10_s14_connectivity": 1, + "m10_s15_connectivity": 1, + "m11_s00_connectivity": 1, + "m11_s01_connectivity": 1, + "m11_s02_connectivity": 1, + "m11_s03_connectivity": 1, + "m11_s04_connectivity": 1, + "m11_s05_connectivity": 1, + "m11_s06_connectivity": 1, + "m11_s07_connectivity": 1, + "m11_s08_connectivity": 1, + "m11_s09_connectivity": 1, + "m11_s10_connectivity": 1, + "m11_s11_connectivity": 1, + "m11_s12_connectivity": 1, + "m11_s13_connectivity": 1, + "m11_s14_connectivity": 1, + "m11_s15_connectivity": 1, + "m12_s00_connectivity": 1, + "m12_s01_connectivity": 1, + "m12_s02_connectivity": 1, + "m12_s03_connectivity": 1, + "m12_s04_connectivity": 1, + "m12_s05_connectivity": 1, + "m12_s06_connectivity": 1, + "m12_s07_connectivity": 1, + "m12_s08_connectivity": 1, + "m12_s09_connectivity": 1, + "m12_s10_connectivity": 1, + "m12_s11_connectivity": 1, + "m12_s12_connectivity": 1, + "m12_s13_connectivity": 1, + "m12_s14_connectivity": 1, + "m12_s15_connectivity": 1, + "m13_s00_connectivity": 1, + "m13_s01_connectivity": 1, + "m13_s02_connectivity": 1, + "m13_s03_connectivity": 1, + "m13_s04_connectivity": 1, + "m13_s05_connectivity": 1, + "m13_s06_connectivity": 1, + "m13_s07_connectivity": 1, + "m13_s08_connectivity": 1, + "m13_s09_connectivity": 1, + "m13_s10_connectivity": 1, + "m13_s11_connectivity": 1, + "m13_s12_connectivity": 1, + "m13_s13_connectivity": 1, + "m13_s14_connectivity": 1, + "m13_s15_connectivity": 1, + "m14_s00_connectivity": 1, + "m14_s01_connectivity": 1, + "m14_s02_connectivity": 1, + "m14_s03_connectivity": 1, + "m14_s04_connectivity": 1, + "m14_s05_connectivity": 1, + "m14_s06_connectivity": 1, + "m14_s07_connectivity": 1, + "m14_s08_connectivity": 1, + "m14_s09_connectivity": 1, + "m14_s10_connectivity": 1, + "m14_s11_connectivity": 1, + "m14_s12_connectivity": 1, + "m14_s13_connectivity": 1, + "m14_s14_connectivity": 1, + "m14_s15_connectivity": 1, + "m15_s00_connectivity": 1, + "m15_s01_connectivity": 1, + "m15_s02_connectivity": 1, + "m15_s03_connectivity": 1, + "m15_s04_connectivity": 1, + "m15_s05_connectivity": 1, + "m15_s06_connectivity": 1, + "m15_s07_connectivity": 1, + "m15_s08_connectivity": 1, + "m15_s09_connectivity": 1, + "m15_s10_connectivity": 1, + "m15_s11_connectivity": 1, + "m15_s12_connectivity": 1, + "m15_s13_connectivity": 1, + "m15_s14_connectivity": 1, + "m15_s15_connectivity": 1, + "component_name": "design_1_xbar_0", + "edk_iptype": "PERIPHERAL", + "c_baseaddr": 2684420096, + "c_highaddr": 2684485631 + }, + "ports": [ + { + "role": "slave", + "target": "zynq_axi_dma_0:MM2S", + "name": "S00_AXIS" + }, + { + "role": "master", + "target": "zynq_axi_dma_0:S2MM", + "name": "M00_AXIS" + }, + { + "role": "slave", + "target": "dino_dinoif_adc_0:M00_AXIS", + "name": "S01_AXIS" + }, + { + "role": "master", + "target": "dino_dinoif_dac_0:S00_AXIS", + "name": "M01_AXIS" + }, + { + "role": "slave", + "target": "aurora_aurora_8b10b_ch0:USER_DATA_M_AXI_RX", + "name": "S02_AXIS" + }, + { + "role": "master", + "target": "aurora_aurora_8b10b_ch0:USER_DATA_S_AXI_TX", + "name": "M02_AXIS" + }, + { + "role": "master", + "target": "axis_interconnect_0_xbar:S03_AXIS", + "name": "M03_AXIS" + }, + { + "role": "slave", + "target": "axis_interconnect_0_xbar:M03_AXIS", + "name": "S03_AXIS" + }, + { + "role": "slave", + "target": "axis_interconnect_0_xbar:M03_AXIS", + "name": "S03_AXIS" + }, + { + "role": "master", + "target": "axis_interconnect_0_xbar:S03_AXIS", + "name": "M03_AXIS" + } + ], + "num_ports": 4 + }, + "dino_dinoif_adc_0": { + "vlnv": "xilinx.com:module_ref:dinoif_adc:1.0", + "i2c_channel": 0, + "parameters": { + "component_name": "design_1_dinoif_adc_0_0", + "edk_iptype": "PERIPHERAL" + }, + "ports": [ + { + "role": "master", + "target": "axis_interconnect_0_xbar:S01_AXIS", + "name": "M00_AXIS" + } + ] + }, + "dino_dinoif_dac_0": { + "vlnv": "xilinx.com:module_ref:dinoif_dac:1.0", + "i2c_channel": 1, + "parameters": { + "component_name": "design_1_dinoif_dac_0_0", + "edk_iptype": "PERIPHERAL" + }, + "ports": [ + { + "role": "slave", + "target": "axis_interconnect_0_xbar:M01_AXIS", + "name": "S00_AXIS" + } + ] + }, + "dino_registerif_0": { + "vlnv": "xilinx.com:module_ref:registerif:1.0", + "parameters": { + "c_axi_data_width": 32, + "c_axi_addr_width": 32, + "reg_addr_width": 10, + "component_name": "design_1_registerif_0_0", + "edk_iptype": "PERIPHERAL", + "c_baseaddr": 2684485632, + "c_highaddr": 2684551167 + } + }, + "zynq_axi_dma_0": { + "vlnv": "xilinx.com:ip:axi_dma:7.1", + "parameters": { + "c_s_axi_lite_addr_width": 10, + "c_s_axi_lite_data_width": 32, + "c_dlytmr_resolution": 125, + "c_prmry_is_aclk_async": 0, + "c_enable_multi_channel": 0, + "c_num_mm2s_channels": 1, + "c_num_s2mm_channels": 1, + "c_include_sg": 1, + "c_sg_include_stscntrl_strm": 0, + "c_sg_use_stsapp_length": 0, + "c_sg_length_width": 23, + "c_m_axi_sg_addr_width": 64, + "c_m_axi_sg_data_width": 32, + "c_m_axis_mm2s_cntrl_tdata_width": 32, + "c_s_axis_s2mm_sts_tdata_width": 32, + "c_micro_dma": 0, + "c_include_mm2s": 1, + "c_include_mm2s_sf": 1, + "c_mm2s_burst_size": 16, + "c_m_axi_mm2s_addr_width": 64, + "c_m_axi_mm2s_data_width": 128, + "c_m_axis_mm2s_tdata_width": 128, + "c_include_mm2s_dre": 0, + "c_include_s2mm": 1, + "c_include_s2mm_sf": 1, + "c_s2mm_burst_size": 16, + "c_m_axi_s2mm_addr_width": 64, + "c_m_axi_s2mm_data_width": 128, + "c_s_axis_s2mm_tdata_width": 128, + "c_include_s2mm_dre": 0, + "c_increase_throughput": 0, + "c_family": "zynquplus", + "component_name": "design_1_axi_dma_0_0", + "c_addr_width": 64, + "c_single_interface": 0, + "edk_iptype": "PERIPHERAL", + "c_baseaddr": 2684354560, + "c_highaddr": 2684420095 + }, + "memory-view": { + "M_AXI_MM2S": { + "zynq_zynq_ultra_ps_e_0": { + "HPC0_DDR_LOW": { + "baseaddr": 0, + "highaddr": 2147483647, + "size": 2147483648 + }, + "HPC0_DDR_HIGH": { + "baseaddr": 34359738368, + "highaddr": 68719476735, + "size": 34359738368 + } + } + }, + "M_AXI_S2MM": { + "zynq_zynq_ultra_ps_e_0": { + "HPC0_DDR_LOW": { + "baseaddr": 0, + "highaddr": 2147483647, + "size": 2147483648 + }, + "HPC0_DDR_HIGH": { + "baseaddr": 34359738368, + "highaddr": 68719476735, + "size": 34359738368 + } + } + } + }, + "ports": [ + { + "role": "master", + "target": "axis_interconnect_0_xbar:S00_AXIS", + "name": "MM2S" + }, + { + "role": "slave", + "target": "axis_interconnect_0_xbar:M00_AXIS", + "name": "S2MM" + } + ], + "irqs": { + "mm2s_introut": "zynq_zynq_ultra_ps_e_0:0", + "s2mm_introut": "zynq_zynq_ultra_ps_e_0:1" + } + }, + "zynq_axi_read_cache_0": { + "vlnv": "xilinx.com:module_ref:axi_read_cache:1.0", + "parameters": { + "c_axi_data_width": 32, + "c_axi_addr_width": 64, + "word_num": 16, + "component_name": "design_1_axi_read_cache_0_0", + "edk_iptype": "PERIPHERAL", + "c_baseaddr": 2684616704, + "c_highaddr": 2684682239 + }, + "memory-view": { + "M_AXI": { + "zynq_zynq_ultra_ps_e_0": { + "HPC1_DDR_LOW": { + "baseaddr": 0, + "highaddr": 2147483647, + "size": 2147483648 + }, + "HPC1_DDR_HIGH": { + "baseaddr": 34359738368, + "highaddr": 68719476735, + "size": 34359738368 + } + } + } + } + }, + "zynq_zynq_ultra_ps_e_0": { + "vlnv": "xilinx.com:ip:zynq_ultra_ps_e:3.3", + "parameters": { + "c_dp_use_audio": 0, + "c_dp_use_video": 0, + "c_maxigp0_data_width": 128, + "c_maxigp1_data_width": 128, + "c_maxigp2_data_width": 32, + "c_saxigp0_data_width": 128, + "c_saxigp1_data_width": 128, + "c_saxigp2_data_width": 128, + "c_saxigp3_data_width": 128, + "c_saxigp4_data_width": 128, + "c_saxigp5_data_width": 128, + "c_saxigp6_data_width": 128, + "c_use_diff_rw_clk_gp0": 0, + "c_use_diff_rw_clk_gp1": 0, + "c_use_diff_rw_clk_gp2": 0, + "c_use_diff_rw_clk_gp3": 0, + "c_use_diff_rw_clk_gp4": 0, + "c_use_diff_rw_clk_gp5": 0, + "c_use_diff_rw_clk_gp6": 0, + "c_en_fifo_enet0": 0, + "c_en_fifo_enet1": 0, + "c_en_fifo_enet2": 0, + "c_en_fifo_enet3": 0, + "c_pl_clk0_buf": "TRUE", + "c_pl_clk1_buf": "FALSE", + "c_pl_clk2_buf": "FALSE", + "c_pl_clk3_buf": "FALSE", + "c_trace_pipeline_width": 8, + "c_en_emio_trace": 0, + "c_trace_data_width": 32, + "c_use_debug_test": 0, + "c_sd0_internal_bus_width": 8, + "c_sd1_internal_bus_width": 8, + "c_num_f2p_0_intr_inputs": 3, + "c_num_f2p_1_intr_inputs": 1, + "c_emio_gpio_width": 1, + "c_num_fabric_resets": 1, + "psu_value_silversion": 3, + "psu__use__ddr_intf_requested": 0, + "psu__en_axi_status_ports": 0, + "psu__pss_ref_clk__freqmhz": "33.330", + "psu__pss_alt_ref_clk__freqmhz": "33.333", + "psu__video_ref_clk__freqmhz": "33.333", + "psu__aux_ref_clk__freqmhz": "33.333", + "psu__gt_ref_clk__freqmhz": "33.333", + "psu__video_ref_clk__enable": 0, + "psu__video_ref_clk__io": "", + "psu__can0__peripheral__enable": 0, + "psu__can0__peripheral__io": "", + "psu__can1__peripheral__enable": 1, + "psu__can1__peripheral__io": "MIO 24 .. 25", + "psu__can1__grp_clk__enable": 0, + "psu__can1__grp_clk__io": "", + "psu__gem__tsu__enable": 0, + "psu__gem__tsu__io": "", + "psu__enet1__peripheral__enable": 0, + "psu__enet1__fifo__enable": 0, + "psu__enet1__ptp__enable": 0, + "psu__enet1__peripheral__io": "", + "psu__enet2__peripheral__enable": 0, + "psu__enet2__fifo__enable": 0, + "psu__enet2__ptp__enable": 0, + "psu__enet2__peripheral__io": "", + "psu__enet3__peripheral__enable": 1, + "psu__enet3__fifo__enable": 0, + "psu__enet3__ptp__enable": 0, + "psu__enet3__peripheral__io": "MIO 64 .. 75", + "psu__enet3__grp_mdio__enable": 1, + "psu__enet3__grp_mdio__io": "MIO 76 .. 77", + "psu__gpio_emio__peripheral__enable": 0, + "psu__gpio_emio__peripheral__io": "", + "psu__i2c0__peripheral__enable": 1, + "psu__i2c0__peripheral__io": "MIO 14 .. 15", + "psu__i2c0__grp_int__enable": 0, + "psu__i2c0__grp_int__io": "", + "psu__i2c0_loop_i2c1__enable": 0, + "psu__testscan__peripheral__enable": 0, + "psu__pcie__peripheral__enable": 0, + "psu__pcie__peripheral__endpoint_enable": 1, + "psu__pcie__peripheral__rootport_enable": 0, + "psu__pcie__peripheral__endpoint_io": "", + "psu__pcie__lane0__enable": 0, + "psu__pcie__lane0__io": "", + "psu__pcie__lane2__enable": 0, + "psu__pcie__lane2__io": "", + "psu__pcie__reset__polarity": "Active Low", + "psu__gt__link_speed": "HBR", + "psu__gt__vlt_swng_lvl_4": 0, + "psu__gt__pre_emph_lvl_4": 0, + "psu__usb0__ref_clk_sel": "Ref Clk2", + "psu__usb0__ref_clk_freq": 26, + "psu__usb1__ref_clk_sel": "", + "psu__gem0__ref_clk_sel": "", + "psu__gem1__ref_clk_sel": "", + "psu__gem2__ref_clk_sel": "", + "psu__gem3__ref_clk_sel": "", + "psu__dp__ref_clk_sel": "Ref Clk3", + "psu__dp__ref_clk_freq": 27, + "psu__sata__ref_clk_sel": "Ref Clk1", + "psu__sata__ref_clk_freq": 125, + "psu__pcie__ref_clk_sel": "", + "psu__dp__lane_sel": "Dual Lower", + "psu__pcie__device_port_type": "", + "psu__pcie__link_speed": "", + "psu__pcie__bar0_enable": 0, + "psu__pcie__bar0_type": "", + "psu__pcie__bar0_64bit": 0, + "psu__pcie__bar0_size": "", + "psu__pcie__bar1_scale": "", + "psu__pcie__bar1_val": null, + "psu__pcie__bar1_prefetchable": 0, + "psu__pcie__bar2_enable": 0, + "psu__pcie__bar2_type": "", + "psu__pcie__bar2_64bit": 0, + "psu__pcie__bar2_size": "", + "psu__pcie__bar3_scale": "", + "psu__pcie__bar3_val": null, + "psu__pcie__bar3_prefetchable": 0, + "psu__pcie__bar4_enable": 0, + "psu__pcie__bar4_type": "", + "psu__pcie__bar4_64bit": 0, + "psu__pcie__bar4_size": "", + "psu__pcie__bar5_scale": "", + "psu__pcie__bar5_val": null, + "psu__pcie__bar5_prefetchable": 0, + "psu__pcie__erom_enable": 0, + "psu__pcie__erom_scale": "", + "psu__pcie__erom_val": null, + "psu__pcie__cap_slot_implemented": "", + "psu__pcie__legacy_interrupt": "", + "psu__pcie__use_class_code_lookup_assistant": "", + "psu__pcie__class_code_base": null, + "psu__pcie__class_code_sub": null, + "psu__pcie__class_code_interface": null, + "psu__pcie__class_code_value": null, + "psu__pcie__aer_capability": 0, + "psu__pcie__correctable_int_err": 0, + "psu__pcie__header_log_overflow": 0, + "psu__pcie__receiver_err": 0, + "psu__pcie__surprise_down": 0, + "psu__pcie__flow_control_err": 0, + "psu__pcie__compltion_timeout": 0, + "psu__pcie__completer_abort": 0, + "psu__pcie__receiver_overflow": 0, + "psu__pcie__ecrc_err": 0, + "psu__pcie__acs_violaion": 0, + "psu__pcie__uncorrectabl_int_err": 0, + "psu__pcie__mc_blocked_tlp": 0, + "psu__pcie__atomicop_egress_blocked": 0, + "psu__pcie__tlp_prefix_blocked": 0, + "psu__pcie__flow_control_protocol_err": 0, + "psu__pcie__acs_violation": 0, + "psu__pcie__multiheader": 0, + "psu__pcie__ecrc_check": 0, + "psu__pcie__ecrc_gen": 0, + "psu__pcie__perm_root_err_update": 0, + "psu__pcie__crs_sw_visibility": 0, + "psu__pcie__intx_generation": 0, + "psu__pcie__intx_pin": "", + "psu__pcie__msix_capability": 0, + "psu__pcie__msix_table_size": 0, + "psu__pcie__msix_table_offset": 0, + "psu__pcie__msix_bar_indicator": null, + "psu__pcie__msix_pba_offset": 0, + "psu__pcie__msix_pba_bar_indicator": null, + "psu__pcie__bridge_bar_indicator": "", + "psu_mio_tree_peripherals": "Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1#GPIO0 MIO#GPIO0 MIO#CAN 1#CAN 1#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU GPO 3#PMU GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3", + "psu_mio_tree_signals": "sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#txd#rxd#gpio0[22]#gpio0[23]#phy_tx#phy_rx#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#sdio1_bus_pow#sdio1_wp#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out", + "psu_peripheral_board_preset": null, + "psu__nand__peripheral__io": "", + "psu__nand__ready0_busy__io": "", + "psu__nand__chip_enable__enable": 0, + "psu__nand__chip_enable__io": "", + "psu__pjtag__peripheral__enable": 0, + "psu__pjtag__peripheral__io": "", + "psu__pmu__emio_gpi__enable": 0, + "psu__pmu__emio_gpo__enable": 0, + "psu__pmu__gpi0__enable": 0, + "psu__pmu__gpi1__enable": 0, + "psu__pmu__gpi2__enable": 0, + "psu__pmu__gpi3__enable": 0, + "psu__pmu__gpi4__enable": 0, + "psu__pmu__gpi5__enable": 0, + "psu__pmu__gpo0__enable": 1, + "psu__pmu__gpo1__enable": 1, + "psu__pmu__gpo2__enable": 1, + "psu__pmu__gpo3__enable": 1, + "psu__pmu__gpo4__enable": 1, + "psu__pmu__gpo5__enable": 1, + "psu__pmu__gpi0__io": "", + "psu__pmu__gpi2__io": "", + "psu__pmu__gpi4__io": "", + "psu__pmu__gpo0__io": "MIO 32", + "psu__pmu__gpo1__io": "MIO 33", + "psu__pmu__gpo2__io": "MIO 34", + "psu__pmu__gpo3__io": "MIO 35", + "psu__pmu__gpo4__io": "MIO 36", + "psu__pmu__gpo5__io": "MIO 37", + "psu__pmu__gpo2__polarity": "low", + "psu__pmu__gpo3__polarity": "low", + "psu__pmu__gpo4__polarity": "low", + "psu__pmu__gpo5__polarity": "low", + "psu__csu__peripheral__enable": 0, + "psu__csu__peripheral__io": "", + "psu__sd0__grp_cd__enable": 0, + "psu__sd0__grp_cd__io": "", + "psu__sd0__grp_wp__enable": 0, + "psu__sd0__grp_wp__io": "", + "psu__sd0__reset__enable": 0, + "psu__sd0__data_transfer_mode": "", + "psu__spi0__grp_ss0__enable": 0, + "psu__spi0__grp_ss0__io": "", + "psu__spi0__grp_ss2__enable": 0, + "psu__spi0__grp_ss2__io": "", + "psu__spi1__grp_ss0__enable": 0, + "psu__spi1__grp_ss0__io": "", + "psu__spi1__grp_ss2__enable": 0, + "psu__spi1__grp_ss2__io": "", + "psu__swdt0__reset__io": "", + "psu__swdt1__reset__io": "", + "psu__trace__width": "", + "psu__ttc0__waveout__io": "", + "psu__ttc1__waveout__io": "", + "psu__ttc2__waveout__io": "", + "psu__ttc3__waveout__io": "", + "psu__ddrc__memory_type": "DDR 4", + "psu__ddrc__partno": "", + "psu__ddrc__addr_mirror": 0, + "psu__ddrc__en_2nd_clk": 0, + "psu__ddrc__lpddr3_dualrank_sdp": 0, + "psu__ddrc__per_bank_refresh": 0, + "psu__ddrc__enable_dp_switch": 0, + "psu__ddrc__enable_lp4_slowboot": 0, + "psu__ddrc__enable_lp4_has_ecc_comp": 0, + "psu__ddrc__enable_2t_timing": 0, + "psu__ddrc__rd_dqs_center": 0, + "psu__ddrc__dqmap_0_3": 0, + "psu__ddrc__dqmap_4_7": 0, + "psu__ddrc__dqmap_8_11": 0, + "psu__ddrc__dqmap_12_15": 0, + "psu__ddrc__dqmap_16_19": 0, + "psu__ddrc__dqmap_20_23": 0, + "psu__ddrc__dqmap_24_27": 0, + "psu__ddrc__dqmap_28_31": 0, + "psu__ddrc__dqmap_32_35": 0, + "psu__ddrc__dqmap_36_39": 0, + "psu__ddrc__dqmap_40_43": 0, + "psu__ddrc__dqmap_44_47": 0, + "psu__ddrc__dqmap_48_51": 0, + "psu__ddrc__dqmap_52_55": 0, + "psu__ddrc__dqmap_56_59": 0, + "psu__ddrc__dqmap_60_63": 0, + "psu__ddrc__dqmap_64_67": 0, + "psu__ddrc__dqmap_68_71": 0, + "psu_ddr_ram_highaddr": 4294967295, + "psu_ddr_ram_highaddr_offset": 34359738368, + "psu_ddr_ram_lowaddr_offset": 2147483648, + "psu__ddr_qos_enable": 0, + "psu__ddr_qos_port0_type": "", + "psu__ddr_qos_port1_vn2_type": "", + "psu__ddr_qos_port2_vn2_type": "", + "psu__ddr_qos_port4_type": "", + "psu__ddr_qos_rd_lpr_thrshld": null, + "psu__ddr_qos_rd_hpr_thrshld": null, + "psu__ddr_qos_wr_thrshld": null, + "psu__ddr_qos_hp0_rdqos": null, + "psu__ddr_qos_hp0_wrqos": null, + "psu__ddr_qos_hp1_rdqos": null, + "psu__ddr_qos_hp1_wrqos": null, + "psu__ddr_qos_hp2_rdqos": null, + "psu__ddr_qos_hp2_wrqos": null, + "psu__ddr_qos_hp3_rdqos": null, + "psu__ddr_qos_hp3_wrqos": null, + "psu__ddr_qos_fix_hp0_rdqos": null, + "psu__ddr_qos_fix_hp0_wrqos": null, + "psu__ddr_qos_fix_hp1_rdqos": null, + "psu__ddr_qos_fix_hp1_wrqos": null, + "psu__ddr_qos_fix_hp2_rdqos": null, + "psu__ddr_qos_fix_hp2_wrqos": null, + "psu__ddr_qos_fix_hp3_rdqos": null, + "psu__ddr_qos_fix_hp3_wrqos": null, + "psu__override_hpx_qos": 0, + "psu__fp__power__on": 1, + "psu__pl__power__on": 1, + "psu__ocm_bank0__power__on": 1, + "psu__ocm_bank1__power__on": 1, + "psu__ocm_bank2__power__on": 1, + "psu__ocm_bank3__power__on": 1, + "psu__tcm0a__power__on": 1, + "psu__tcm0b__power__on": 1, + "psu__tcm1a__power__on": 1, + "psu__tcm1b__power__on": 1, + "psu__rpu__power__on": 1, + "psu__l2_bank0__power__on": 1, + "psu__gpu_pp0__power__on": 1, + "psu__gpu_pp1__power__on": 1, + "psu__acpu0__power__on": 1, + "psu__acpu1__power__on": 1, + "psu__acpu2__power__on": 1, + "psu__acpu3__power__on": 1, + "psu__uart0__peripheral__enable": 1, + "psu__uart0__peripheral__io": "MIO 18 .. 19", + "psu__uart0__modem__enable": 0, + "psu__uart1__peripheral__enable": 1, + "psu__uart1__peripheral__io": "MIO 20 .. 21", + "psu__uart1__modem__enable": 0, + "psu__uart0_loop_uart1__enable": 0, + "psu__usb0__peripheral__enable": 1, + "psu__usb0__peripheral__io": "MIO 52 .. 63", + "psu__usb0__reset__enable": 0, + "psu__usb0__reset__io": "", + "psu__usb1__reset__enable": 0, + "psu__usb1__reset__io": "", + "psu__usb3_0__emio__enable": 0, + "psu__usb2_0__emio__enable": 0, + "psu__usb3_1__emio__enable": 0, + "psu__usb2_1__emio__enable": 0, + "psu__use__usb3_0_hub": 0, + "psu__use__usb3_1_hub": 0, + "psu__use__adma": 0, + "psu__use__m_axi_gp0": 1, + "psu__m_axi_gp0_supports_narrow_burst": 1, + "psu__maxigp0__data_width": 128, + "psu__use__m_axi_gp1": 0, + "psu__m_axi_gp1_supports_narrow_burst": 1, + "psu__maxigp1__data_width": 128, + "psu__use__m_axi_gp2": 0, + "psu__m_axi_gp2_supports_narrow_burst": 1, + "psu__maxigp2__data_width": 32, + "psu__use__s_axi_acp": 0, + "psu__use__s_axi_gp0": 1, + "psu__use_diff_rw_clk_gp0": 0, + "psu__saxigp0__data_width": 128, + "psu__use__s_axi_gp1": 1, + "psu__use_diff_rw_clk_gp1": 0, + "psu__saxigp1__data_width": 128, + "psu__use__s_axi_gp2": 0, + "psu__use_diff_rw_clk_gp2": 0, + "psu__saxigp2__data_width": 128, + "psu__use__s_axi_gp3": 0, + "psu__use_diff_rw_clk_gp3": 0, + "psu__saxigp3__data_width": 128, + "psu__use__s_axi_gp4": 0, + "psu__use_diff_rw_clk_gp4": 0, + "psu__saxigp4__data_width": 128, + "psu__use__s_axi_gp5": 0, + "psu__use_diff_rw_clk_gp5": 0, + "psu__saxigp5__data_width": 128, + "psu__use__s_axi_gp6": 0, + "psu__use_diff_rw_clk_gp6": 0, + "psu__saxigp6__data_width": 128, + "psu__use__s_axi_ace": 0, + "psu__trace_pipeline_width": 8, + "psu__en_emio_trace": 0, + "psu__use__audio": 0, + "psu__use__video": 0, + "psu__use__proc_event_bus": 0, + "psu__use__ftm": 0, + "psu__use__cross_trigger": 0, + "psu__ftm__cti_in_0": 0, + "psu__ftm__cti_in_1": 0, + "psu__ftm__cti_in_2": 0, + "psu__ftm__cti_in_3": 0, + "psu__ftm__cti_out_0": 0, + "psu__ftm__cti_out_1": 0, + "psu__ftm__cti_out_2": 0, + "psu__ftm__cti_out_3": 0, + "psu__ftm__gpo": 0, + "psu__ftm__gpi": 0, + "psu__use__gdma": 0, + "psu__use__irq": 0, + "psu__use__irq0": 1, + "psu__use__irq1": 0, + "psu__use__clk0": 0, + "psu__use__clk1": 0, + "psu__use__clk2": 0, + "psu__use__clk3": 0, + "psu__use__rst0": 0, + "psu__use__rst1": 0, + "psu__use__rst2": 0, + "psu__use__rst3": 0, + "psu__use__fabric__rst": 1, + "psu__use__rtc": 0, + "psu__preset_applied": 1, + "psu__use__event_rpu": 0, + "psu__use__apu_legacy_interrupt": 0, + "psu__use__rpu_legacy_interrupt": 0, + "psu__use__stm": 0, + "psu__use__debug__test": 0, + "psu__high_address__enable": 1, + "psu__ddr_high_address_gui_enable": 1, + "psu__expand__lower_lps_slaves": 0, + "psu__expand__coresight": 0, + "psu__expand__gic": 0, + "psu__expand__fpd_slaves": 0, + "psu__expand__upper_lps_slaves": 0, + "psu_mio_0_pullupdown": "pullup", + "psu_mio_0_drive_strength": 12, + "psu_mio_0_polarity": "Default", + "psu_mio_0_input_type": "cmos", + "psu_mio_0_slew": "fast", + "psu_mio_0_direction": "out", + "psu_mio_1_pullupdown": "pullup", + "psu_mio_1_drive_strength": 12, + "psu_mio_1_polarity": "Default", + "psu_mio_1_input_type": "cmos", + "psu_mio_1_slew": "fast", + "psu_mio_1_direction": "inout", + "psu_mio_2_pullupdown": "pullup", + "psu_mio_2_drive_strength": 12, + "psu_mio_2_polarity": "Default", + "psu_mio_2_input_type": "cmos", + "psu_mio_2_slew": "fast", + "psu_mio_2_direction": "inout", + "psu_mio_3_pullupdown": "pullup", + "psu_mio_3_drive_strength": 12, + "psu_mio_3_polarity": "Default", + "psu_mio_3_input_type": "cmos", + "psu_mio_3_slew": "fast", + "psu_mio_3_direction": "inout", + "psu_mio_4_pullupdown": "pullup", + "psu_mio_4_drive_strength": 12, + "psu_mio_4_polarity": "Default", + "psu_mio_4_input_type": "cmos", + "psu_mio_4_slew": "fast", + "psu_mio_4_direction": "inout", + "psu_mio_5_pullupdown": "pullup", + "psu_mio_5_drive_strength": 12, + "psu_mio_5_polarity": "Default", + "psu_mio_5_input_type": "cmos", + "psu_mio_5_slew": "fast", + "psu_mio_5_direction": "out", + "psu_mio_6_pullupdown": "pullup", + "psu_mio_6_drive_strength": 12, + "psu_mio_6_polarity": "Default", + "psu_mio_6_input_type": "cmos", + "psu_mio_6_slew": "fast", + "psu_mio_6_direction": "out", + "psu_mio_7_pullupdown": "pullup", + "psu_mio_7_drive_strength": 12, + "psu_mio_7_polarity": "Default", + "psu_mio_7_input_type": "cmos", + "psu_mio_7_slew": "fast", + "psu_mio_7_direction": "out", + "psu_mio_8_pullupdown": "pullup", + "psu_mio_8_drive_strength": 12, + "psu_mio_8_polarity": "Default", + "psu_mio_8_input_type": "cmos", + "psu_mio_8_slew": "fast", + "psu_mio_8_direction": "inout", + "psu_mio_9_pullupdown": "pullup", + "psu_mio_9_drive_strength": 12, + "psu_mio_9_polarity": "Default", + "psu_mio_9_input_type": "cmos", + "psu_mio_9_slew": "fast", + "psu_mio_9_direction": "inout", + "psu_mio_10_pullupdown": "pullup", + "psu_mio_10_drive_strength": 12, + "psu_mio_10_polarity": "Default", + "psu_mio_10_input_type": "cmos", + "psu_mio_10_slew": "fast", + "psu_mio_10_direction": "inout", + "psu_mio_11_pullupdown": "pullup", + "psu_mio_11_drive_strength": 12, + "psu_mio_11_polarity": "Default", + "psu_mio_11_input_type": "cmos", + "psu_mio_11_slew": "fast", + "psu_mio_11_direction": "inout", + "psu_mio_12_pullupdown": "pullup", + "psu_mio_12_drive_strength": 12, + "psu_mio_12_polarity": "Default", + "psu_mio_12_input_type": "cmos", + "psu_mio_12_slew": "fast", + "psu_mio_12_direction": "out", + "psu_mio_13_pullupdown": "pullup", + "psu_mio_13_drive_strength": 12, + "psu_mio_13_polarity": "Default", + "psu_mio_13_input_type": "cmos", + "psu_mio_13_slew": "fast", + "psu_mio_13_direction": "inout", + "psu_mio_14_pullupdown": "pullup", + "psu_mio_14_drive_strength": 12, + "psu_mio_14_polarity": "Default", + "psu_mio_14_input_type": "cmos", + "psu_mio_14_slew": "fast", + "psu_mio_14_direction": "inout", + "psu_mio_15_pullupdown": "pullup", + "psu_mio_15_drive_strength": 12, + "psu_mio_15_polarity": "Default", + "psu_mio_15_input_type": "cmos", + "psu_mio_15_slew": "fast", + "psu_mio_15_direction": "inout", + "psu_mio_16_pullupdown": "pullup", + "psu_mio_16_drive_strength": 12, + "psu_mio_16_polarity": "Default", + "psu_mio_16_input_type": "cmos", + "psu_mio_16_slew": "fast", + "psu_mio_16_direction": "inout", + "psu_mio_17_pullupdown": "pullup", + "psu_mio_17_drive_strength": 12, + "psu_mio_17_polarity": "Default", + "psu_mio_17_input_type": "cmos", + "psu_mio_17_slew": "fast", + "psu_mio_17_direction": "inout", + "psu_mio_18_pullupdown": "pullup", + "psu_mio_18_drive_strength": 12, + "psu_mio_18_polarity": "Default", + "psu_mio_18_input_type": "cmos", + "psu_mio_18_slew": "fast", + "psu_mio_18_direction": "in", + "psu_mio_19_pullupdown": "pullup", + "psu_mio_19_drive_strength": 12, + "psu_mio_19_polarity": "Default", + "psu_mio_19_input_type": "cmos", + "psu_mio_19_slew": "fast", + "psu_mio_19_direction": "out", + "psu_mio_20_pullupdown": "pullup", + "psu_mio_20_drive_strength": 12, + "psu_mio_20_polarity": "Default", + "psu_mio_20_input_type": "cmos", + "psu_mio_20_slew": "fast", + "psu_mio_20_direction": "out", + "psu_mio_21_pullupdown": "pullup", + "psu_mio_21_drive_strength": 12, + "psu_mio_21_polarity": "Default", + "psu_mio_21_input_type": "cmos", + "psu_mio_21_slew": "fast", + "psu_mio_21_direction": "in", + "psu_mio_22_pullupdown": "pullup", + "psu_mio_22_drive_strength": 12, + "psu_mio_22_polarity": "Default", + "psu_mio_22_input_type": "cmos", + "psu_mio_22_slew": "fast", + "psu_mio_22_direction": "inout", + "psu_mio_23_pullupdown": "pullup", + "psu_mio_23_drive_strength": 12, + "psu_mio_23_polarity": "Default", + "psu_mio_23_input_type": "cmos", + "psu_mio_23_slew": "fast", + "psu_mio_23_direction": "inout", + "psu_mio_24_pullupdown": "pullup", + "psu_mio_24_drive_strength": 12, + "psu_mio_24_polarity": "Default", + "psu_mio_24_input_type": "cmos", + "psu_mio_24_slew": "fast", + "psu_mio_24_direction": "out", + "psu_mio_25_pullupdown": "pullup", + "psu_mio_25_drive_strength": 12, + "psu_mio_25_polarity": "Default", + "psu_mio_25_input_type": "cmos", + "psu_mio_25_slew": "fast", + "psu_mio_25_direction": "in", + "psu_mio_26_pullupdown": "pullup", + "psu_mio_26_drive_strength": 12, + "psu_mio_26_polarity": "Default", + "psu_mio_26_input_type": "cmos", + "psu_mio_26_slew": "fast", + "psu_mio_26_direction": "inout", + "psu_mio_27_pullupdown": "pullup", + "psu_mio_27_drive_strength": 12, + "psu_mio_27_polarity": "Default", + "psu_mio_27_input_type": "cmos", + "psu_mio_27_slew": "fast", + "psu_mio_27_direction": "out", + "psu_mio_28_pullupdown": "pullup", + "psu_mio_28_drive_strength": 12, + "psu_mio_28_polarity": "Default", + "psu_mio_28_input_type": "cmos", + "psu_mio_28_slew": "fast", + "psu_mio_28_direction": "in", + "psu_mio_29_pullupdown": "pullup", + "psu_mio_29_drive_strength": 12, + "psu_mio_29_polarity": "Default", + "psu_mio_29_input_type": "cmos", + "psu_mio_29_slew": "fast", + "psu_mio_29_direction": "out", + "psu_mio_30_pullupdown": "pullup", + "psu_mio_30_drive_strength": 12, + "psu_mio_30_polarity": "Default", + "psu_mio_30_input_type": "cmos", + "psu_mio_30_slew": "fast", + "psu_mio_30_direction": "in", + "psu_mio_31_pullupdown": "pullup", + "psu_mio_31_drive_strength": 12, + "psu_mio_31_polarity": "Default", + "psu_mio_31_input_type": "cmos", + "psu_mio_31_slew": "fast", + "psu_mio_31_direction": "inout", + "psu_mio_32_pullupdown": "pullup", + "psu_mio_32_drive_strength": 12, + "psu_mio_32_polarity": "Default", + "psu_mio_32_input_type": "cmos", + "psu_mio_32_slew": "fast", + "psu_mio_32_direction": "out", + "psu_mio_33_pullupdown": "pullup", + "psu_mio_33_drive_strength": 12, + "psu_mio_33_polarity": "Default", + "psu_mio_33_input_type": "cmos", + "psu_mio_33_slew": "fast", + "psu_mio_33_direction": "out", + "psu_mio_34_pullupdown": "pullup", + "psu_mio_34_drive_strength": 12, + "psu_mio_34_polarity": "Default", + "psu_mio_34_input_type": "cmos", + "psu_mio_34_slew": "fast", + "psu_mio_34_direction": "out", + "psu_mio_35_pullupdown": "pullup", + "psu_mio_35_drive_strength": 12, + "psu_mio_35_polarity": "Default", + "psu_mio_35_input_type": "cmos", + "psu_mio_35_slew": "fast", + "psu_mio_35_direction": "out", + "psu_mio_36_pullupdown": "pullup", + "psu_mio_36_drive_strength": 12, + "psu_mio_36_polarity": "Default", + "psu_mio_36_input_type": "cmos", + "psu_mio_36_slew": "fast", + "psu_mio_36_direction": "out", + "psu_mio_37_pullupdown": "pullup", + "psu_mio_37_drive_strength": 12, + "psu_mio_37_polarity": "Default", + "psu_mio_37_input_type": "cmos", + "psu_mio_37_slew": "fast", + "psu_mio_37_direction": "out", + "psu_mio_38_pullupdown": "pullup", + "psu_mio_38_drive_strength": 12, + "psu_mio_38_polarity": "Default", + "psu_mio_38_input_type": "cmos", + "psu_mio_38_slew": "fast", + "psu_mio_38_direction": "inout", + "psu_mio_39_pullupdown": "pullup", + "psu_mio_39_drive_strength": 12, + "psu_mio_39_polarity": "Default", + "psu_mio_39_input_type": "cmos", + "psu_mio_39_slew": "fast", + "psu_mio_39_direction": "inout", + "psu_mio_40_pullupdown": "pullup", + "psu_mio_40_drive_strength": 12, + "psu_mio_40_polarity": "Default", + "psu_mio_40_input_type": "cmos", + "psu_mio_40_slew": "fast", + "psu_mio_40_direction": "inout", + "psu_mio_41_pullupdown": "pullup", + "psu_mio_41_drive_strength": 12, + "psu_mio_41_polarity": "Default", + "psu_mio_41_input_type": "cmos", + "psu_mio_41_slew": "fast", + "psu_mio_41_direction": "inout", + "psu_mio_42_pullupdown": "pullup", + "psu_mio_42_drive_strength": 12, + "psu_mio_42_polarity": "Default", + "psu_mio_42_input_type": "cmos", + "psu_mio_42_slew": "fast", + "psu_mio_42_direction": "inout", + "psu_mio_43_pullupdown": "pullup", + "psu_mio_43_drive_strength": 12, + "psu_mio_43_polarity": "Default", + "psu_mio_43_input_type": "cmos", + "psu_mio_43_slew": "fast", + "psu_mio_43_direction": "out", + "psu_mio_44_pullupdown": "pullup", + "psu_mio_44_drive_strength": 12, + "psu_mio_44_polarity": "Default", + "psu_mio_44_input_type": "cmos", + "psu_mio_44_slew": "fast", + "psu_mio_44_direction": "in", + "psu_mio_45_pullupdown": "pullup", + "psu_mio_45_drive_strength": 12, + "psu_mio_45_polarity": "Default", + "psu_mio_45_input_type": "cmos", + "psu_mio_45_slew": "fast", + "psu_mio_45_direction": "in", + "psu_mio_46_pullupdown": "pullup", + "psu_mio_46_drive_strength": 12, + "psu_mio_46_polarity": "Default", + "psu_mio_46_input_type": "cmos", + "psu_mio_46_slew": "fast", + "psu_mio_46_direction": "inout", + "psu_mio_47_pullupdown": "pullup", + "psu_mio_47_drive_strength": 12, + "psu_mio_47_polarity": "Default", + "psu_mio_47_input_type": "cmos", + "psu_mio_47_slew": "fast", + "psu_mio_47_direction": "inout", + "psu_mio_48_pullupdown": "pullup", + "psu_mio_48_drive_strength": 12, + "psu_mio_48_polarity": "Default", + "psu_mio_48_input_type": "cmos", + "psu_mio_48_slew": "fast", + "psu_mio_48_direction": "inout", + "psu_mio_49_pullupdown": "pullup", + "psu_mio_49_drive_strength": 12, + "psu_mio_49_polarity": "Default", + "psu_mio_49_input_type": "cmos", + "psu_mio_49_slew": "fast", + "psu_mio_49_direction": "inout", + "psu_mio_50_pullupdown": "pullup", + "psu_mio_50_drive_strength": 12, + "psu_mio_50_polarity": "Default", + "psu_mio_50_input_type": "cmos", + "psu_mio_50_slew": "fast", + "psu_mio_50_direction": "inout", + "psu_mio_51_pullupdown": "pullup", + "psu_mio_51_drive_strength": 12, + "psu_mio_51_polarity": "Default", + "psu_mio_51_input_type": "cmos", + "psu_mio_51_slew": "fast", + "psu_mio_51_direction": "out", + "psu_mio_52_pullupdown": "pullup", + "psu_mio_52_drive_strength": 12, + "psu_mio_52_polarity": "Default", + "psu_mio_52_input_type": "cmos", + "psu_mio_52_slew": "fast", + "psu_mio_52_direction": "in", + "psu_mio_53_pullupdown": "pullup", + "psu_mio_53_drive_strength": 12, + "psu_mio_53_polarity": "Default", + "psu_mio_53_input_type": "cmos", + "psu_mio_53_slew": "fast", + "psu_mio_53_direction": "in", + "psu_mio_54_pullupdown": "pullup", + "psu_mio_54_drive_strength": 12, + "psu_mio_54_polarity": "Default", + "psu_mio_54_input_type": "cmos", + "psu_mio_54_slew": "fast", + "psu_mio_54_direction": "inout", + "psu_mio_55_pullupdown": "pullup", + "psu_mio_55_drive_strength": 12, + "psu_mio_55_polarity": "Default", + "psu_mio_55_input_type": "cmos", + "psu_mio_55_slew": "fast", + "psu_mio_55_direction": "in", + "psu_mio_56_pullupdown": "pullup", + "psu_mio_56_drive_strength": 12, + "psu_mio_56_polarity": "Default", + "psu_mio_56_input_type": "cmos", + "psu_mio_56_slew": "fast", + "psu_mio_56_direction": "inout", + "psu_mio_57_pullupdown": "pullup", + "psu_mio_57_drive_strength": 12, + "psu_mio_57_polarity": "Default", + "psu_mio_57_input_type": "cmos", + "psu_mio_57_slew": "fast", + "psu_mio_57_direction": "inout", + "psu_mio_58_pullupdown": "pullup", + "psu_mio_58_drive_strength": 12, + "psu_mio_58_polarity": "Default", + "psu_mio_58_input_type": "cmos", + "psu_mio_58_slew": "fast", + "psu_mio_58_direction": "out", + "psu_mio_59_pullupdown": "pullup", + "psu_mio_59_drive_strength": 12, + "psu_mio_59_polarity": "Default", + "psu_mio_59_input_type": "cmos", + "psu_mio_59_slew": "fast", + "psu_mio_59_direction": "inout", + "psu_mio_60_pullupdown": "pullup", + "psu_mio_60_drive_strength": 12, + "psu_mio_60_polarity": "Default", + "psu_mio_60_input_type": "cmos", + "psu_mio_60_slew": "fast", + "psu_mio_60_direction": "inout", + "psu_mio_61_pullupdown": "pullup", + "psu_mio_61_drive_strength": 12, + "psu_mio_61_polarity": "Default", + "psu_mio_61_input_type": "cmos", + "psu_mio_61_slew": "fast", + "psu_mio_61_direction": "inout", + "psu_mio_62_pullupdown": "pullup", + "psu_mio_62_drive_strength": 12, + "psu_mio_62_polarity": "Default", + "psu_mio_62_input_type": "cmos", + "psu_mio_62_slew": "fast", + "psu_mio_62_direction": "inout", + "psu_mio_63_pullupdown": "pullup", + "psu_mio_63_drive_strength": 12, + "psu_mio_63_polarity": "Default", + "psu_mio_63_input_type": "cmos", + "psu_mio_63_slew": "fast", + "psu_mio_63_direction": "inout", + "psu_mio_64_pullupdown": "pullup", + "psu_mio_64_drive_strength": 12, + "psu_mio_64_polarity": "Default", + "psu_mio_64_input_type": "cmos", + "psu_mio_64_slew": "fast", + "psu_mio_64_direction": "out", + "psu_mio_65_pullupdown": "pullup", + "psu_mio_65_drive_strength": 12, + "psu_mio_65_polarity": "Default", + "psu_mio_65_input_type": "cmos", + "psu_mio_65_slew": "fast", + "psu_mio_65_direction": "out", + "psu_mio_66_pullupdown": "pullup", + "psu_mio_66_drive_strength": 12, + "psu_mio_66_polarity": "Default", + "psu_mio_66_input_type": "cmos", + "psu_mio_66_slew": "fast", + "psu_mio_66_direction": "out", + "psu_mio_67_pullupdown": "pullup", + "psu_mio_67_drive_strength": 12, + "psu_mio_67_polarity": "Default", + "psu_mio_67_input_type": "cmos", + "psu_mio_67_slew": "fast", + "psu_mio_67_direction": "out", + "psu_mio_68_pullupdown": "pullup", + "psu_mio_68_drive_strength": 12, + "psu_mio_68_polarity": "Default", + "psu_mio_68_input_type": "cmos", + "psu_mio_68_slew": "fast", + "psu_mio_68_direction": "out", + "psu_mio_69_pullupdown": "pullup", + "psu_mio_69_drive_strength": 12, + "psu_mio_69_polarity": "Default", + "psu_mio_69_input_type": "cmos", + "psu_mio_69_slew": "fast", + "psu_mio_69_direction": "out", + "psu_mio_70_pullupdown": "pullup", + "psu_mio_70_drive_strength": 12, + "psu_mio_70_polarity": "Default", + "psu_mio_70_input_type": "cmos", + "psu_mio_70_slew": "fast", + "psu_mio_70_direction": "in", + "psu_mio_71_pullupdown": "pullup", + "psu_mio_71_drive_strength": 12, + "psu_mio_71_polarity": "Default", + "psu_mio_71_input_type": "cmos", + "psu_mio_71_slew": "fast", + "psu_mio_71_direction": "in", + "psu_mio_72_pullupdown": "pullup", + "psu_mio_72_drive_strength": 12, + "psu_mio_72_polarity": "Default", + "psu_mio_72_input_type": "cmos", + "psu_mio_72_slew": "fast", + "psu_mio_72_direction": "in", + "psu_mio_73_pullupdown": "pullup", + "psu_mio_73_drive_strength": 12, + "psu_mio_73_polarity": "Default", + "psu_mio_73_input_type": "cmos", + "psu_mio_73_slew": "fast", + "psu_mio_73_direction": "in", + "psu_mio_74_pullupdown": "pullup", + "psu_mio_74_drive_strength": 12, + "psu_mio_74_polarity": "Default", + "psu_mio_74_input_type": "cmos", + "psu_mio_74_slew": "fast", + "psu_mio_74_direction": "in", + "psu_mio_75_pullupdown": "pullup", + "psu_mio_75_drive_strength": 12, + "psu_mio_75_polarity": "Default", + "psu_mio_75_input_type": "cmos", + "psu_mio_75_slew": "fast", + "psu_mio_75_direction": "in", + "psu_mio_76_pullupdown": "pullup", + "psu_mio_76_drive_strength": 12, + "psu_mio_76_polarity": "Default", + "psu_mio_76_input_type": "cmos", + "psu_mio_76_slew": "fast", + "psu_mio_76_direction": "out", + "psu_mio_77_pullupdown": "pullup", + "psu_mio_77_drive_strength": 12, + "psu_mio_77_polarity": "Default", + "psu_mio_77_input_type": "cmos", + "psu_mio_77_slew": "fast", + "psu_mio_77_direction": "inout", + "psu_bank_0_io_standard": "LVCMOS18", + "psu_bank_1_io_standard": "LVCMOS18", + "psu_bank_2_io_standard": "LVCMOS18", + "psu_bank_3_io_standard": "LVCMOS33", + "psu__crf_apb__apll_ctrl__fracdata": "0.000000", + "psu__crf_apb__vpll_ctrl__fracdata": "0.000000", + "psu__crf_apb__dpll_ctrl__fracdata": "0.000000", + "psu__crl_apb__iopll_ctrl__fracdata": "0.000000", + "psu__crl_apb__rpll_ctrl__fracdata": "0.000000", + "psu__crf_apb__dpll_ctrl__div2": 1, + "psu__crf_apb__apll_ctrl__div2": 1, + "psu__crf_apb__vpll_ctrl__div2": 1, + "psu__crl_apb__iopll_ctrl__div2": 1, + "psu__crl_apb__rpll_ctrl__div2": 1, + "psu__crf_apb__apll_ctrl__fbdiv": 72, + "psu__crf_apb__dpll_ctrl__fbdiv": 64, + "psu__crf_apb__vpll_ctrl__fbdiv": 90, + "psu__crf_apb__apll_to_lpd_ctrl__divisor0": 3, + "psu__crf_apb__dpll_to_lpd_ctrl__divisor0": 2, + "psu__crf_apb__vpll_to_lpd_ctrl__divisor0": 3, + "psu__crf_apb__acpu_ctrl__divisor0": 1, + "psu__crf_apb__dbg_trace_ctrl__divisor0": 5, + "psu__displayport__peripheral__enable": 1, + "psu__displayport__lane0__enable": 1, + "psu__displayport__lane0__io": "GT Lane1", + "psu__displayport__lane1__enable": 1, + "psu__displayport__lane1__io": "GT Lane0", + "psu__crf_apb__dbg_fpd_ctrl__divisor0": 2, + "psu__crf_apb__apm_ctrl__divisor0": 1, + "psu__crf_apb__dp_video_ref_ctrl__divisor0": 5, + "psu__crf_apb__dp_video_ref_ctrl__divisor1": 1, + "psu__crf_apb__dp_audio_ref_ctrl__divisor0": 15, + "psu__crf_apb__dp_audio_ref_ctrl__divisor1": 1, + "psu__crf_apb__dp_stc_ref_ctrl__divisor0": 14, + "psu__crf_apb__dp_stc_ref_ctrl__divisor1": 1, + "psu__crf_apb__ddr_ctrl__divisor0": 2, + "psu__crf_apb__gpu_ref_ctrl__divisor0": 1, + "psu__crf_apb__afi0_ref_ctrl__divisor0": 2, + "psu__crf_apb__afi0_ref__enable": 0, + "psu__crf_apb__afi1_ref_ctrl__divisor0": 2, + "psu__crf_apb__afi1_ref__enable": 0, + "psu__crf_apb__afi2_ref_ctrl__divisor0": 2, + "psu__crf_apb__afi2_ref__enable": 0, + "psu__crf_apb__afi3_ref_ctrl__divisor0": 2, + "psu__crf_apb__afi3_ref__enable": 0, + "psu__crf_apb__afi4_ref_ctrl__divisor0": 2, + "psu__crf_apb__afi4_ref__enable": 0, + "psu__crf_apb__afi5_ref_ctrl__divisor0": 2, + "psu__crf_apb__afi5_ref__enable": 0, + "psu__crf_apb__sata_ref_ctrl__divisor0": 2, + "psu__sata__peripheral__enable": 1, + "psu__sata__lane0__enable": 0, + "psu__sata__lane0__io": "", + "psu__crf_apb__dp_video_ref_ctrl__srcsel": "VPLL", + "psu__crf_apb__dp_audio_ref_ctrl__srcsel": "RPLL", + "psu__crf_apb__dp_stc_ref_ctrl__srcsel": "RPLL", + "psu__crf_apb__ddr_ctrl__srcsel": "DPLL", + "psu__crf_apb__gpu_ref_ctrl__srcsel": "IOPLL", + "psu__crf_apb__afi0_ref_ctrl__srcsel": "DPLL", + "psu__crf_apb__afi1_ref_ctrl__srcsel": "DPLL", + "psu__crf_apb__afi2_ref_ctrl__srcsel": "DPLL", + "psu__crf_apb__afi3_ref_ctrl__srcsel": "DPLL", + "psu__crf_apb__afi4_ref_ctrl__srcsel": "DPLL", + "psu__crf_apb__afi5_ref_ctrl__srcsel": "DPLL", + "psu__crf_apb__sata_ref_ctrl__srcsel": "IOPLL", + "psu__crf_apb__pcie_ref_ctrl__srcsel": "IOPLL", + "psu__crl_apb__pl0_ref_ctrl__srcsel": "IOPLL", + "psu__crl_apb__pl1_ref_ctrl__srcsel": "RPLL", + "psu__crl_apb__pl2_ref_ctrl__srcsel": "RPLL", + "psu__crl_apb__pl3_ref_ctrl__srcsel": "RPLL", + "psu__crf_apb__gdma_ref_ctrl__srcsel": "APLL", + "psu__crf_apb__dpdma_ref_ctrl__srcsel": "APLL", + "psu__crf_apb__topsw_main_ctrl__srcsel": "DPLL", + "psu__crf_apb__topsw_lsbus_ctrl__srcsel": "IOPLL", + "psu__crf_apb__gtgref0_ref_ctrl__srcsel": "NA", + "psu__crf_apb__dbg_tstmp_ctrl__srcsel": "IOPLL", + "psu__crl_apb__iopll_ctrl__srcsel": "PSS_REF_CLK", + "psu__crl_apb__rpll_ctrl__srcsel": "PSS_REF_CLK", + "psu__crl_apb__gem0_ref_ctrl__srcsel": "IOPLL", + "psu__crl_apb__gem1_ref_ctrl__srcsel": "IOPLL", + "psu__crl_apb__gem2_ref_ctrl__srcsel": "IOPLL", + "psu__crl_apb__gem3_ref_ctrl__srcsel": "IOPLL", + "psu__crl_apb__gem_tsu_ref_ctrl__srcsel": "IOPLL", + "psu__crl_apb__usb0_bus_ref_ctrl__srcsel": "IOPLL", + "psu__crl_apb__usb1_bus_ref_ctrl__srcsel": "IOPLL", + "psu__crl_apb__qspi_ref_ctrl__srcsel": "IOPLL", + "psu__crl_apb__sdio0_ref_ctrl__srcsel": "RPLL", + "psu__crl_apb__sdio1_ref_ctrl__srcsel": "IOPLL", + "psu__crl_apb__uart0_ref_ctrl__srcsel": "IOPLL", + "psu__crl_apb__uart1_ref_ctrl__srcsel": "IOPLL", + "psu__crl_apb__i2c0_ref_ctrl__srcsel": "IOPLL", + "psu__crl_apb__i2c1_ref_ctrl__srcsel": "IOPLL", + "psu__crl_apb__spi0_ref_ctrl__srcsel": "RPLL", + "psu__crl_apb__spi1_ref_ctrl__srcsel": "RPLL", + "psu__crl_apb__can0_ref_ctrl__srcsel": "IOPLL", + "psu__crl_apb__can1_ref_ctrl__srcsel": "IOPLL", + "psu__crl_apb__debug_r5_atclk_ctrl__srcsel": "RPLL", + "psu__crl_apb__cpu_r5_ctrl__srcsel": "IOPLL", + "psu__crl_apb__ocm_main_ctrl__srcsel": "IOPLL", + "psu__crl_apb__iou_switch_ctrl__srcsel": "IOPLL", + "psu__crl_apb__csu_pll_ctrl__srcsel": "SysOsc", + "psu__crl_apb__pcap_ctrl__srcsel": "IOPLL", + "psu__crl_apb__lpd_lsbus_ctrl__srcsel": "IOPLL", + "psu__crl_apb__lpd_switch_ctrl__srcsel": "IOPLL", + "psu__crl_apb__dbg_lpd_ctrl__srcsel": "IOPLL", + "psu__crl_apb__nand_ref_ctrl__srcsel": "IOPLL", + "psu__crl_apb__adma_ref_ctrl__srcsel": "IOPLL", + "psu__crl_apb__dll_ref_ctrl__srcsel": "IOPLL", + "psu__crl_apb__ams_ref_ctrl__srcsel": "IOPLL", + "psu__crl_apb__timestamp_ref_ctrl__srcsel": "IOPLL", + "psu__crl_apb__afi6_ref_ctrl__srcsel": "IOPLL", + "psu__crl_apb__usb3_dual_ref_ctrl__srcsel": "IOPLL", + "psu__iou_slcr__wdt_clk_sel__select": "APB", + "psu__fpd_slcr__wdt_clk_sel__select": "APB", + "psu__iou_slcr__iou_ttc_apb_clk__ttc0_sel": "APB", + "psu__iou_slcr__iou_ttc_apb_clk__ttc1_sel": "APB", + "psu__iou_slcr__iou_ttc_apb_clk__ttc2_sel": "APB", + "psu__iou_slcr__iou_ttc_apb_clk__ttc3_sel": "APB", + "psu__crf_apb__apll_frac_cfg__enabled": 0, + "psu__crf_apb__vpll_frac_cfg__enabled": 0, + "psu__crf_apb__dpll_frac_cfg__enabled": 0, + "psu__crl_apb__iopll_frac_cfg__enabled": 0, + "psu__crl_apb__rpll_frac_cfg__enabled": 0, + "psu__crf_apb__dp_video__frac_enabled": 0, + "psu__crf_apb__dp_audio__frac_enabled": 0, + "psu__crf_apb__acpu__frac_enabled": 0, + "psu__override__basic_clock": 0, + "psu__dll__isused": 1, + "psu__pl_clk0_buf": "TRUE", + "psu__pl_clk1_buf": "FALSE", + "psu__pl_clk2_buf": "FALSE", + "psu__pl_clk3_buf": "FALSE", + "psu__crf_apb__apll_ctrl__fracfreq": "27.138", + "psu__crf_apb__vpll_ctrl__fracfreq": "27.138", + "psu__crf_apb__dpll_ctrl__fracfreq": "27.138", + "psu__crl_apb__iopll_ctrl__fracfreq": "27.138", + "psu__crl_apb__rpll_ctrl__fracfreq": "27.138", + "psu__iou_slcr__ttc0__act_freqmhz": "100.000000", + "psu__iou_slcr__ttc1__act_freqmhz": "100.000000", + "psu__iou_slcr__ttc2__act_freqmhz": "100.000000", + "psu__iou_slcr__ttc3__act_freqmhz": "100.000000", + "psu__iou_slcr__wdt0__act_freqmhz": "99.990005", + "psu__fpd_slcr__wdt1__act_freqmhz": "99.990005", + "psu__lpd_slcr__csupmu__act_freqmhz": "100.000000", + "psu__crf_apb__acpu_ctrl__act_freqmhz": "1199.880127", + "psu__crf_apb__dbg_trace_ctrl__act_freqmhz": 250, + "psu__crf_apb__dbg_fpd_ctrl__act_freqmhz": "249.975021", + "psu__crf_apb__apm_ctrl__act_freqmhz": 1, + "psu__crf_apb__dp_video_ref_ctrl__act_freqmhz": "299.970032", + "psu__crf_apb__dp_audio_ref_ctrl__act_freqmhz": "24.997501", + "psu__crf_apb__dp_stc_ref_ctrl__act_freqmhz": "26.783037", + "psu__crf_apb__ddr_ctrl__act_freqmhz": "533.280029", + "psu__ddr__interface__freqmhz": "533.500", + "psu__crf_apb__gpu_ref_ctrl__act_freqmhz": "499.950043", + "psu__crf_apb__afi0_ref_ctrl__act_freqmhz": 667, + "psu__crf_apb__afi1_ref_ctrl__act_freqmhz": 667, + "psu__crf_apb__afi2_ref_ctrl__act_freqmhz": 667, + "psu__crf_apb__afi3_ref_ctrl__act_freqmhz": 667, + "psu__crf_apb__afi4_ref_ctrl__act_freqmhz": 667, + "psu__crf_apb__afi5_ref_ctrl__act_freqmhz": 667, + "psu__crf_apb__sata_ref_ctrl__act_freqmhz": "249.975021", + "psu__crf_apb__pcie_ref_ctrl__act_freqmhz": 250, + "psu__crl_apb__pl0_ref_ctrl__act_freqmhz": "99.990005", + "psu__crl_apb__pl1_ref_ctrl__act_freqmhz": 100, + "psu__crl_apb__pl2_ref_ctrl__act_freqmhz": 100, + "psu__crl_apb__pl3_ref_ctrl__act_freqmhz": 100, + "psu__crf_apb__gdma_ref_ctrl__act_freqmhz": "599.940063", + "psu__crf_apb__dpdma_ref_ctrl__act_freqmhz": "599.940063", + "psu__crf_apb__topsw_main_ctrl__act_freqmhz": "533.280029", + "psu__crf_apb__topsw_lsbus_ctrl__act_freqmhz": "99.990005", + "psu__crf_apb__gtgref0_ref_ctrl__act_freqmhz": -1, + "psu__crf_apb__dbg_tstmp_ctrl__act_freqmhz": "249.975021", + "psu__crl_apb__gem0_ref_ctrl__act_freqmhz": 125, + "psu__crl_apb__gem1_ref_ctrl__act_freqmhz": 125, + "psu__crl_apb__gem2_ref_ctrl__act_freqmhz": 125, + "psu__crl_apb__gem3_ref_ctrl__act_freqmhz": "124.987511", + "psu__crl_apb__gem_tsu_ref_ctrl__act_freqmhz": "249.975021", + "psu__crl_apb__usb0_bus_ref_ctrl__act_freqmhz": "249.975021", + "psu__crl_apb__usb1_bus_ref_ctrl__act_freqmhz": 250, + "psu__crl_apb__qspi_ref_ctrl__act_freqmhz": "124.987511", + "psu__crl_apb__sdio0_ref_ctrl__act_freqmhz": 200, + "psu__crl_apb__sdio1_ref_ctrl__act_freqmhz": "187.481262", + "psu__crl_apb__uart0_ref_ctrl__act_freqmhz": "99.990005", + "psu__crl_apb__uart1_ref_ctrl__act_freqmhz": "99.990005", + "psu__crl_apb__i2c0_ref_ctrl__act_freqmhz": "99.990005", + "psu__crl_apb__i2c1_ref_ctrl__act_freqmhz": "99.990005", + "psu__crl_apb__spi0_ref_ctrl__act_freqmhz": 214, + "psu__crl_apb__spi1_ref_ctrl__act_freqmhz": 214, + "psu__crl_apb__can0_ref_ctrl__act_freqmhz": 100, + "psu__crl_apb__can1_ref_ctrl__act_freqmhz": "99.990005", + "psu__crl_apb__debug_r5_atclk_ctrl__act_freqmhz": 1000, + "psu__crl_apb__cpu_r5_ctrl__act_freqmhz": "499.950043", + "psu__crl_apb__ocm_main_ctrl__act_freqmhz": 500, + "psu__crl_apb__iou_switch_ctrl__act_freqmhz": "249.975021", + "psu__crl_apb__csu_pll_ctrl__act_freqmhz": 180, + "psu__crl_apb__pcap_ctrl__act_freqmhz": "187.481262", + "psu__crl_apb__lpd_lsbus_ctrl__act_freqmhz": "99.990005", + "psu__crl_apb__lpd_switch_ctrl__act_freqmhz": "499.950043", + "psu__crl_apb__dbg_lpd_ctrl__act_freqmhz": "249.975021", + "psu__crl_apb__nand_ref_ctrl__act_freqmhz": 100, + "psu__crl_apb__adma_ref_ctrl__act_freqmhz": "499.950043", + "psu__crl_apb__dll_ref_ctrl__act_freqmhz": "1499.850098", + "psu__crl_apb__ams_ref_ctrl__act_freqmhz": "49.995003", + "psu__crl_apb__timestamp_ref_ctrl__act_freqmhz": "99.990005", + "psu__crl_apb__afi6_ref_ctrl__act_freqmhz": 500, + "psu__crl_apb__usb3_dual_ref_ctrl__act_freqmhz": "19.998001", + "psu__crf_apb__acpu_ctrl__freqmhz": 1200, + "psu__crf_apb__dbg_trace_ctrl__freqmhz": 250, + "psu__crf_apb__dbg_fpd_ctrl__freqmhz": 250, + "psu__crf_apb__apm_ctrl__freqmhz": 1, + "psu__crf_apb__dp_video_ref_ctrl__freqmhz": 300, + "psu__crf_apb__dp_audio_ref_ctrl__freqmhz": 25, + "psu__crf_apb__dp_stc_ref_ctrl__freqmhz": 27, + "psu__crf_apb__ddr_ctrl__freqmhz": 1067, + "psu__crf_apb__gpu_ref_ctrl__freqmhz": 500, + "psu__crf_apb__afi0_ref_ctrl__freqmhz": 667, + "psu__crf_apb__afi1_ref_ctrl__freqmhz": 667, + "psu__crf_apb__afi2_ref_ctrl__freqmhz": 667, + "psu__crf_apb__afi3_ref_ctrl__freqmhz": 667, + "psu__crf_apb__afi4_ref_ctrl__freqmhz": 667, + "psu__crf_apb__afi5_ref_ctrl__freqmhz": 667, + "psu__crf_apb__sata_ref_ctrl__freqmhz": 250, + "psu__crf_apb__pcie_ref_ctrl__freqmhz": 250, + "psu__crl_apb__pl0_ref_ctrl__freqmhz": 100, + "psu__crl_apb__pl1_ref_ctrl__freqmhz": 100, + "psu__crl_apb__pl2_ref_ctrl__freqmhz": 100, + "psu__crl_apb__pl3_ref_ctrl__freqmhz": 100, + "psu__crf_apb__gdma_ref_ctrl__freqmhz": 600, + "psu__crf_apb__dpdma_ref_ctrl__freqmhz": 600, + "psu__crf_apb__topsw_main_ctrl__freqmhz": "533.33", + "psu__crf_apb__topsw_lsbus_ctrl__freqmhz": 100, + "psu__crf_apb__gtgref0_ref_ctrl__freqmhz": -1, + "psu__crf_apb__dbg_tstmp_ctrl__freqmhz": 250, + "psu__crl_apb__gem0_ref_ctrl__freqmhz": 125, + "psu__crl_apb__gem1_ref_ctrl__freqmhz": 125, + "psu__crl_apb__gem2_ref_ctrl__freqmhz": 125, + "psu__crl_apb__gem3_ref_ctrl__freqmhz": 125, + "psu__crl_apb__gem_tsu_ref_ctrl__freqmhz": 250, + "psu__crl_apb__usb0_bus_ref_ctrl__freqmhz": 250, + "psu__crl_apb__usb1_bus_ref_ctrl__freqmhz": 250, + "psu__crl_apb__qspi_ref_ctrl__freqmhz": 125, + "psu__crl_apb__sdio0_ref_ctrl__freqmhz": 200, + "psu__crl_apb__sdio1_ref_ctrl__freqmhz": 200, + "psu__crl_apb__uart0_ref_ctrl__freqmhz": 100, + "psu__crl_apb__uart1_ref_ctrl__freqmhz": 100, + "psu__crl_apb__i2c0_ref_ctrl__freqmhz": 100, + "psu__crl_apb__i2c1_ref_ctrl__freqmhz": 100, + "psu__crl_apb__spi0_ref_ctrl__freqmhz": 200, + "psu__crl_apb__spi1_ref_ctrl__freqmhz": 200, + "psu__crl_apb__can0_ref_ctrl__freqmhz": 100, + "psu__crl_apb__can1_ref_ctrl__freqmhz": 100, + "psu__crl_apb__debug_r5_atclk_ctrl__freqmhz": 1000, + "psu__crl_apb__cpu_r5_ctrl__freqmhz": 500, + "psu__crl_apb__ocm_main_ctrl__freqmhz": 500, + "psu__crl_apb__iou_switch_ctrl__freqmhz": 250, + "psu__crl_apb__csu_pll_ctrl__freqmhz": 180, + "psu__crl_apb__pcap_ctrl__freqmhz": 200, + "psu__crl_apb__lpd_lsbus_ctrl__freqmhz": 100, + "psu__crl_apb__lpd_switch_ctrl__freqmhz": 500, + "psu__crl_apb__dbg_lpd_ctrl__freqmhz": 250, + "psu__crl_apb__nand_ref_ctrl__freqmhz": 100, + "psu__crl_apb__adma_ref_ctrl__freqmhz": 500, + "psu__crl_apb__dll_ref_ctrl__freqmhz": 1500, + "psu__crl_apb__ams_ref_ctrl__freqmhz": 50, + "psu__crl_apb__timestamp_ref_ctrl__freqmhz": 100, + "psu__crl_apb__afi6_ref_ctrl__freqmhz": 500, + "psu__crl_apb__usb3_dual_ref_ctrl__freqmhz": 20, + "psu__iou_slcr__ttc0__freqmhz": "100.000000", + "psu__iou_slcr__ttc1__freqmhz": "100.000000", + "psu__iou_slcr__ttc2__freqmhz": "100.000000", + "psu__iou_slcr__ttc3__freqmhz": "100.000000", + "psu__iou_slcr__wdt0__freqmhz": "99.990005", + "psu__fpd_slcr__wdt1__freqmhz": "99.990005", + "psu__lpd_slcr__csupmu__freqmhz": "100.000000", + "psu__csu__csu_tamper_0__enable": 0, + "psu__csu__csu_tamper_1__enable": 0, + "psu__csu__csu_tamper_2__enable": 0, + "psu__csu__csu_tamper_3__enable": 0, + "psu__csu__csu_tamper_4__enable": 0, + "psu__csu__csu_tamper_5__enable": 0, + "psu__csu__csu_tamper_6__enable": 0, + "psu__csu__csu_tamper_7__enable": 0, + "psu__csu__csu_tamper_8__enable": 0, + "psu__csu__csu_tamper_9__enable": 0, + "psu__csu__csu_tamper_10__enable": 0, + "psu__csu__csu_tamper_11__enable": 0, + "psu__csu__csu_tamper_12__enable": 0, + "psu__csu__csu_tamper_0__erase_bbram": 0, + "psu__csu__csu_tamper_1__erase_bbram": 0, + "psu__csu__csu_tamper_2__erase_bbram": 0, + "psu__csu__csu_tamper_3__erase_bbram": 0, + "psu__csu__csu_tamper_4__erase_bbram": 0, + "psu__csu__csu_tamper_5__erase_bbram": 0, + "psu__csu__csu_tamper_6__erase_bbram": 0, + "psu__csu__csu_tamper_7__erase_bbram": 0, + "psu__csu__csu_tamper_8__erase_bbram": 0, + "psu__csu__csu_tamper_9__erase_bbram": 0, + "psu__csu__csu_tamper_10__erase_bbram": 0, + "psu__csu__csu_tamper_11__erase_bbram": 0, + "psu__csu__csu_tamper_12__erase_bbram": 0, + "psu__csu__csu_tamper_0__response": "", + "psu__csu__csu_tamper_2__response": "", + "psu__csu__csu_tamper_4__response": "", + "psu__csu__csu_tamper_6__response": "", + "psu__csu__csu_tamper_8__response": "", + "psu__csu__csu_tamper_10__response": "", + "psu__csu__csu_tamper_12__response": "", + "psu__irq_p2f_rpu_permon__int": 0, + "psu__irq_p2f_ocm_err__int": 0, + "psu__irq_p2f_lpd_apb__int": 0, + "psu__irq_p2f_r5_core0_ecc_err__int": 0, + "psu__irq_p2f_r5_core1_ecc_err__int": 0, + "psu__irq_p2f_nand__int": 0, + "psu__irq_p2f_qspi__int": 0, + "psu__irq_p2f_gpio__int": 0, + "psu__irq_p2f_i2c0__int": 0, + "psu__irq_p2f_i2c1__int": 0, + "psu__irq_p2f_spi0__int": 0, + "psu__irq_p2f_spi1__int": 0, + "psu__irq_p2f_uart0__int": 0, + "psu__irq_p2f_uart1__int": 0, + "psu__irq_p2f_can0__int": 0, + "psu__irq_p2f_can1__int": 0, + "psu__irq_p2f_lpd_apm__int": 0, + "psu__irq_p2f_rtc_alarm__int": 0, + "psu__irq_p2f_rtc_seconds__int": 0, + "psu__irq_p2f_clkmon__int": 0, + "psu__irq_p2f_pl_ipi__int": 0, + "psu__irq_p2f_rpu_ipi__int": 0, + "psu__irq_p2f_apu_ipi__int": 0, + "psu__irq_p2f_ttc0__int0": 0, + "psu__irq_p2f_ttc0__int1": 0, + "psu__irq_p2f_ttc0__int2": 0, + "psu__irq_p2f_ttc1__int0": 0, + "psu__irq_p2f_ttc1__int1": 0, + "psu__irq_p2f_ttc1__int2": 0, + "psu__irq_p2f_ttc2__int0": 0, + "psu__irq_p2f_ttc2__int1": 0, + "psu__irq_p2f_ttc2__int2": 0, + "psu__irq_p2f_ttc3__int0": 0, + "psu__irq_p2f_ttc3__int1": 0, + "psu__irq_p2f_ttc3__int2": 0, + "psu__irq_p2f_sdio0__int": 0, + "psu__irq_p2f_sdio1__int": 0, + "psu__irq_p2f_sdio0_wake__int": 0, + "psu__irq_p2f_sdio1_wake__int": 0, + "psu__irq_p2f_lp_wdt__int": 0, + "psu__irq_p2f_csupmu_wdt__int": 0, + "psu__irq_p2f_atb_lpd__int": 0, + "psu__irq_p2f_aib_axi__int": 0, + "psu__irq_p2f_ams__int": 0, + "psu__irq_p2f_ent0__int": 0, + "psu__irq_p2f_ent0_wakeup__int": 0, + "psu__irq_p2f_ent1__int": 0, + "psu__irq_p2f_ent1_wakeup__int": 0, + "psu__irq_p2f_ent2__int": 0, + "psu__irq_p2f_ent2_wakeup__int": 0, + "psu__irq_p2f_ent3__int": 0, + "psu__irq_p2f_ent3_wakeup__int": 0, + "psu__irq_p2f_usb3_endpoint__int0": 0, + "psu__irq_p2f_usb3_otg__int0": 0, + "psu__irq_p2f_usb3_endpoint__int1": 0, + "psu__irq_p2f_usb3_otg__int1": 0, + "psu__irq_p2f_usb3_pmu_wakeup__int": 0, + "psu__irq_p2f_adma_chan__int": 0, + "psu__irq_p2f_csu__int": 0, + "psu__irq_p2f_csu_dma__int": 0, + "psu__irq_p2f_efuse__int": 0, + "psu__irq_p2f_xmpu_lpd__int": 0, + "psu__irq_p2f_ddr_ss__int": 0, + "psu__irq_p2f_fp_wdt__int": 0, + "psu__irq_p2f_pcie_msi__int": 0, + "psu__irq_p2f_pcie_legacy__int": 0, + "psu__irq_p2f_pcie_dma__int": 0, + "psu__irq_p2f_pcie_msc__int": 0, + "psu__irq_p2f_dport__int": 0, + "psu__irq_p2f_fpd_apb__int": 0, + "psu__irq_p2f_fpd_atb_err__int": 0, + "psu__irq_p2f_dpdma__int": 0, + "psu__irq_p2f_apm_fpd__int": 0, + "psu__irq_p2f_gdma_chan__int": 0, + "psu__irq_p2f_gpu__int": 0, + "psu__irq_p2f_sata__int": 0, + "psu__irq_p2f_xmpu_fpd__int": 0, + "psu__irq_p2f_apu_cpumnt__int": 0, + "psu__irq_p2f_apu_cti__int": 0, + "psu__irq_p2f_apu_pmu__int": 0, + "psu__irq_p2f_apu_comm__int": 0, + "psu__irq_p2f_apu_l2err__int": 0, + "psu__irq_p2f_apu_exterr__int": 0, + "psu__irq_p2f_apu_regs__int": 0, + "psu__irq_p2f__intf_ppd_cci__int": 0, + "psu__irq_p2f__intf_fpd_smmu__int": 0, + "psu__num_f2p0__intr__inputs": 3, + "psu__num_f2p1__intr__inputs": 1, + "psu__num_fabric_resets": 1, + "psu__gpio_emio_width": 1, + "psu__hpm0_fpd__num_write_threads": 4, + "psu__hpm0_fpd__num_read_threads": 4, + "psu__hpm1_fpd__num_write_threads": 4, + "psu__hpm1_fpd__num_read_threads": 4, + "psu__hpm0_lpd__num_write_threads": 4, + "psu__hpm0_lpd__num_read_threads": 4, + "psu__tristate__inverted": 1, + "psu__gpio_emio__width": "[94:0]", + "psu__report__dbglog": 0, + "iic0_board_interface": "custom", + "iic1_board_interface": "custom", + "qspi_board_interface": "custom", + "nand_board_interface": "custom", + "sd0_board_interface": "custom", + "sd1_board_interface": "custom", + "can0_board_interface": "custom", + "can1_board_interface": "custom", + "pjtag_board_interface": "custom", + "pmu_board_interface": "custom", + "csu_board_interface": "custom", + "spi0_board_interface": "custom", + "spi1_board_interface": "custom", + "uart0_board_interface": "custom", + "uart1_board_interface": "custom", + "gpio_board_interface": "custom", + "swdt0_board_interface": "custom", + "swdt1_board_interface": "custom", + "trace_board_interface": "custom", + "ttc0_board_interface": "custom", + "ttc1_board_interface": "custom", + "ttc2_board_interface": "custom", + "ttc3_board_interface": "custom", + "gem0_board_interface": "custom", + "gem1_board_interface": "custom", + "gem2_board_interface": "custom", + "gem3_board_interface": "custom", + "usb0_board_interface": "custom", + "usb1_board_interface": "custom", + "pcie_board_interface": "custom", + "dp_board_interface": "custom", + "sata_board_interface": "custom", + "preset": "None", + "psu__sd0_route_through_fpd": 0, + "psu__sd1_route_through_fpd": 0, + "psu__nand_route_through_fpd": 0, + "psu__qspi_route_through_fpd": 0, + "psu__gem0_route_through_fpd": 0, + "psu__gem1_route_through_fpd": 0, + "psu__gem2_route_through_fpd": 0, + "psu__gem3_route_through_fpd": 0, + "psu__rpu_coherency": 0, + "psu__pmu_coherency": 0, + "psu__csu_coherency": 0, + "psu__usb0_coherency": 0, + "psu__usb1_coherency": 0, + "psu__lpdma0_coherency": 0, + "psu__lpdma1_coherency": 0, + "psu__lpdma2_coherency": 0, + "psu__lpdma3_coherency": 0, + "psu__lpdma4_coherency": 0, + "psu__lpdma5_coherency": 0, + "psu__lpdma6_coherency": 0, + "psu__lpdma7_coherency": 0, + "psu__sd0_coherency": 0, + "psu__sd1_coherency": 0, + "psu__nand_coherency": 0, + "psu__qspi_coherency": 0, + "psu__enet0__tsu__enable": 0, + "psu__enet1__tsu__enable": 0, + "psu__enet2__tsu__enable": 0, + "psu__enet3__tsu__enable": 0, + "psu__tsu__bufg_port_pair": 0, + "psu__tsu__bufg_port_loopback": 0, + "psu__gem0_coherency": 0, + "psu__gem1_coherency": 0, + "psu__gem2_coherency": 0, + "psu__gem3_coherency": 0, + "psu__afi0_coherency": 0, + "psu__afi1_coherency": 0, + "psu__fpdmasters_coherency": 0, + "psu__enable__ddr__refresh__signals": 0, + "psu__m_axi_gp0__freqmhz": "99.990005", + "psu__m_axi_gp1__freqmhz": 10, + "psu__m_axi_gp2__freqmhz": 10, + "psu__s_axi_gp0__freqmhz": "99.990005", + "psu__s_axi_gp1__freqmhz": "99.990005", + "psu__s_axi_gp2__freqmhz": 10, + "psu__s_axi_gp3__freqmhz": 10, + "psu__s_axi_gp4__freqmhz": 10, + "psu__s_axi_gp5__freqmhz": 10, + "psu__s_axi_gp6__freqmhz": 10, + "psu_sd1_internal_bus_width": 8, + "component_name": "design_1_zynq_ultra_ps_e_0_1", + "edk_iptype": "PERIPHERAL", + "c_baseaddr": 34359738368, + "c_highaddr": 68719476735 + }, + "memory-view": { + "M_AXI_HPM0_FPD": { + "zynq_axi_dma_0": { + "Reg": { + "baseaddr": 2684354560, + "highaddr": 2684420095, + "size": 65536 + } + }, + "axis_interconnect_0_xbar": { + "Reg": { + "baseaddr": 2684420096, + "highaddr": 2684485631, + "size": 65536 + } + }, + "dino_registerif_0": { + "reg0": { + "baseaddr": 2684485632, + "highaddr": 2684551167, + "size": 65536 + } + }, + "axi_iic_0": { + "Reg": { + "baseaddr": 2684551168, + "highaddr": 2684616703, + "size": 65536 + } + }, + "zynq_axi_read_cache_0": { + "reg0": { + "baseaddr": 2684616704, + "highaddr": 2684682239, + "size": 65536 + } + } + } + } + } +} diff --git a/fpga/include/villas/fpga/ips/axis_cache.hpp b/fpga/include/villas/fpga/ips/axis_cache.hpp new file mode 100644 index 000000000..53153164d --- /dev/null +++ b/fpga/include/villas/fpga/ips/axis_cache.hpp @@ -0,0 +1,47 @@ +/* Driver for AXI Stream read cache. This module is used to lower latency of + * a DMA Scatter Gather engine's descriptor fetching. The driver allows for + * invalidating the cache. + * + * Author: Niklas Eiling + * SPDX-FileCopyrightText: 2024 Niklas Eiling + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +namespace villas { +namespace fpga { +namespace ip { + +class AxisCache : public Node { +public: + AxisCache(); + virtual ~AxisCache(); + virtual bool init() override; + virtual bool check() override; + void invalidate(); + +protected: + const size_t registerNum = 1; + const size_t registerSize = 32; + static constexpr char registerMemory[] = "reg0"; + std::list getMemoryBlocks() const override { + return {registerMemory}; + } + bool setRegister(size_t reg, uint32_t value); + bool getRegister(size_t reg, uint32_t &value); + bool resetRegister(size_t reg); + bool resetAllRegisters(); +}; + +} // namespace ip +} // namespace fpga +} // namespace villas + +#ifndef FMT_LEGACY_OSTREAM_FORMATTER +template <> +class fmt::formatter + : public fmt::ostream_formatter {}; +#endif diff --git a/fpga/include/villas/fpga/ips/register.hpp b/fpga/include/villas/fpga/ips/register.hpp index 3ab67bc3e..18657d7ee 100644 --- a/fpga/include/villas/fpga/ips/register.hpp +++ b/fpga/include/villas/fpga/ips/register.hpp @@ -27,7 +27,7 @@ class Register : public Node { void resetAllRegisters(); protected: - const size_t registerNum = 8; + const size_t registerNum = 9; const size_t registerSize = 32; static constexpr char registerMemory[] = "reg0"; std::list getMemoryBlocks() const override { diff --git a/fpga/include/villas/fpga/utils.hpp b/fpga/include/villas/fpga/utils.hpp index b078936fb..ce1b29759 100644 --- a/fpga/include/villas/fpga/utils.hpp +++ b/fpga/include/villas/fpga/utils.hpp @@ -42,7 +42,7 @@ class ConnectString { ConnectString(std::string &connectString, int maxPortNum = 7); void parseString(std::string &connectString); int portStringToInt(std::string &str) const; - void configCrossBar(std::shared_ptr card) const; + bool configCrossBar(std::shared_ptr card) const; bool isBidirectional() const { return bidirectional; }; bool isDmaLoopback() const { return srcType == ConnectType::LOOPBACK; }; bool isSrcStdin() const { return srcType == ConnectType::DMA; }; diff --git a/fpga/lib/CMakeLists.txt b/fpga/lib/CMakeLists.txt index bc7fd9208..e25ded1a8 100644 --- a/fpga/lib/CMakeLists.txt +++ b/fpga/lib/CMakeLists.txt @@ -28,6 +28,7 @@ set(SOURCES ips/timer.cpp ips/i2c.cpp ips/register.cpp + ips/axis_cache.cpp ips/rtds2gpu/rtds2gpu.cpp ips/rtds2gpu/xrtds2gpu.c diff --git a/fpga/lib/dma.cpp b/fpga/lib/dma.cpp index 7ce10b2b5..44178a0d0 100644 --- a/fpga/lib/dma.cpp +++ b/fpga/lib/dma.cpp @@ -65,7 +65,10 @@ villasfpga_handle villasfpga_init(const char *configFile) { // Configure Crossbar switch const fpga::ConnectString parsedConnectString(connectStr); - parsedConnectString.configCrossBar(handle->card); + if (!parsedConnectString.configCrossBar(handle->card)) { + logger->error("Failed to configure crossbar"); + return nullptr; + } return handle; } catch (const RuntimeError &e) { diff --git a/fpga/lib/ips/axis_cache.cpp b/fpga/lib/ips/axis_cache.cpp new file mode 100644 index 000000000..c773befc9 --- /dev/null +++ b/fpga/lib/ips/axis_cache.cpp @@ -0,0 +1,100 @@ +/* Driver for AXI Stream read cache. + * + * This module is used to lower latency of + * a DMA Scatter Gather engine's descriptor fetching. The driver allows for + * invalidating the cache. + * + * Author: Niklas Eiling + * SPDX-FileCopyrightText: 2024 Niklas Eiling + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include + +using namespace villas::fpga::ip; + +#define REGISTER_OUT(NUM) (4 * NUM) + +AxisCache::AxisCache() : Node() {} + +bool AxisCache::init() { + invalidate(); + return true; +} + +bool AxisCache::check() { + + logger->debug("Checking register interface: Base address: 0x{:08x}", + getBaseAddr(registerMemory)); + uint32_t buf; + + // We should not change the rate register, because this can lead to hardware fault, so start at 1 + for (size_t i = 1; i < registerNum; i++) { + setRegister(i, static_cast(0x00FF00FF)); + } + + for (size_t i = 1; i < registerNum; i++) { + if (!getRegister(i, buf)) { + logger->error("Failed to read register {}", i); + return false; + } + if (buf != 0x00FF00FF) { + logger->error("Register {}: 0x{:08x} != 0x{:08x}", i, buf, i); + return false; + } + } + + resetAllRegisters(); + + for (size_t i = 0; i < registerNum; i++) { + if (!getRegister(i, buf)) { + logger->error("Failed to read register {}", i); + return false; + } + logger->debug("Register {}: 0x{:08x}", i, buf); + } + + return true; +} + +void AxisCache::invalidate() { + setRegister(0, 1U << 31); + logger->info("invalidated AXIS cache."); +} + +bool AxisCache::setRegister(size_t reg, uint32_t value) { + if (reg >= registerNum) { + logger->error("Register index out of range: {}/{}", reg, registerNum); + return false; + } + Xil_Out32(getBaseAddr(registerMemory) + REGISTER_OUT(reg), value); + return true; +} + +bool AxisCache::getRegister(size_t reg, uint32_t &value) { + if (reg >= registerNum) { + logger->error("Register index out of range: {}/{}", reg, registerNum); + return false; + } + value = Xil_In32(getBaseAddr(registerMemory) + REGISTER_OUT(reg)); + return true; +} + +bool AxisCache::resetRegister(size_t reg) { return setRegister(reg, 0); } + +bool AxisCache::resetAllRegisters() { + bool result = true; + for (size_t i = 1; i < registerNum; i++) { + result &= resetRegister(i); + } + return result; +} + +AxisCache::~AxisCache() {} + +static char n[] = "axis_cache"; +static char d[] = "Register interface VHDL module 'axi_read_cache'"; +static char v[] = "xilinx.com:module_ref:axi_read_cache:"; +static CorePlugin f; diff --git a/fpga/lib/ips/dino.cpp b/fpga/lib/ips/dino.cpp index 64e158af7..7360746db 100644 --- a/fpga/lib/ips/dino.cpp +++ b/fpga/lib/ips/dino.cpp @@ -140,6 +140,10 @@ void DinoAdc::configureHardware() { void DinoAdc::setRegisterConfig(std::shared_ptr reg, double sampleRate) { constexpr double dinoClk = 25e6; // Dino is clocked with 25 Mhz + // From the data sheets we can assume an analog delay of 828e-9s + // However this will eat into our computation time, so it should be + // configurable. Let's assume 0 until we implement this. + constexpr double dinoDacDelay = 0; // Delay for DAC to settle constexpr size_t dinoRegisterTimer = 0; constexpr size_t dinoRegisterAdcScale = 1; constexpr size_t dinoRegisterAdcOffset = 2; @@ -147,23 +151,41 @@ void DinoAdc::setRegisterConfig(std::shared_ptr reg, constexpr size_t dinoRegisterStsActive = 5; constexpr size_t dinoRegisterDacScale = 6; constexpr size_t dinoRegisterDacOffset = 7; + constexpr size_t dinoRegisterTimerPreThresh = 8; + + // -1 because the timer counts from 0 to the value set in the register. Should really be fixed in hardware. + uint32_t dinoTimerVal = static_cast(dinoClk / sampleRate) - 1; + uint32_t dinoDacDelayCycles = static_cast(dinoClk * dinoDacDelay); + double rateError = dinoClk / (dinoTimerVal + 1) - sampleRate; + + // Timer value for generating ADC trigger signal + reg->setRegister(dinoRegisterTimer, dinoTimerVal); - uint32_t dinoTimerVal = static_cast(dinoClk / sampleRate); - double rateError = dinoClk / dinoTimerVal - sampleRate; - reg->setRegister( - dinoRegisterTimer, - dinoTimerVal); // Timer value for generating ADC trigger signal // The following are calibration values for the ADC and DAC. Scale // sets an factor to be multiplied with the input value. This is the // raw 16 bit ADC value for the ADC and the float value from VILLAS for // the DAC. Offset is a value to be added to the result of the multiplication. // All values are IEE 754 single precision floating point values. + // Calibration for ADC filter with C=330pF and R=2,2kOhm + // TODO: These values should be read from the FPGA or configured via the configuration file. reg->setRegister(dinoRegisterAdcScale, - -0.001615254F); // Scale factor for ADC value - reg->setRegister(dinoRegisterAdcOffset, 10.8061F); // Offset for ADC value + 0.0016874999385349976F); // Scale factor for ADC value + reg->setRegister(dinoRegisterAdcOffset, + -11.365293957141239F); // Offset for ADC value reg->setRegister(dinoRegisterDacScale, - 3448.53852516F); // Scale factor for DAC value - reg->setRegister(dinoRegisterDacOffset, 32767.5F); // Offset for DAC value + 3204.7355379027363F); // Scale factor for DAC value + reg->setRegister(dinoRegisterDacOffset, + 32772.159015058445F); // Offset for DAC value + reg->setRegister(dinoRegisterDacExternalTrig, + (uint32_t)0x0); // External trigger for DAC + + if (dinoTimerVal > dinoDacDelayCycles) { + reg->setRegister(dinoRegisterTimerPreThresh, + dinoTimerVal - dinoDacDelayCycles); + } else { + reg->setRegister(dinoRegisterTimerPreThresh, dinoTimerVal); + } + uint32_t rate = reg->getRegister(dinoRegisterTimer); float adcScale = reg->getRegisterFloat(dinoRegisterAdcScale); float adcOffset = reg->getRegisterFloat(dinoRegisterAdcOffset); @@ -171,12 +193,13 @@ void DinoAdc::setRegisterConfig(std::shared_ptr reg, float dacOffset = reg->getRegisterFloat(dinoRegisterDacOffset); uint32_t dacExternalTrig = reg->getRegister(dinoRegisterDacExternalTrig); uint32_t stsActive = reg->getRegister(dinoRegisterStsActive); + uint32_t ratePreThresh = reg->getRegister(dinoRegisterTimerPreThresh); Log::get("Dino")->info( "Check: Register configuration: TimerThresh: {}, Rate-Error: {} Hz, ADC " "Scale: {}, ADC Offset: {}, DAC Scale: {}, DAC Offset: {}, DAC External " - "Trig: {:#x}, STS Active: {:#x}", + "Trig: {:#x}, STS Active: {:#x}, TimerPreThresh: {}", rate, rateError, adcScale, adcOffset, dacScale, dacOffset, - dacExternalTrig, stsActive); + dacExternalTrig, stsActive, ratePreThresh); } DinoDac::DinoDac() : Dino() {} diff --git a/fpga/lib/ips/i2c.cpp b/fpga/lib/ips/i2c.cpp index 6243f73cf..75ec4dbe3 100644 --- a/fpga/lib/ips/i2c.cpp +++ b/fpga/lib/ips/i2c.cpp @@ -65,7 +65,12 @@ bool I2c::check() { if (!initDone) { throw RuntimeError("I2C not initialized"); } - return getSwitch().selfTest(); + // Note: While testing the I2C switch here would be great, there might not be a switch connected + // Then a call to getSwitch().selfTest() will fail even though the I2C might be working. + // The only reliable thing to do is to assume there is nothing connected to the I2C bus and + // always return true. + // In the future we might check the FMC EEPROM to determine whether the FMC is connected. + return 1; } bool I2c::stop() { return reset(); } diff --git a/fpga/lib/utils.cpp b/fpga/lib/utils.cpp index be0f20b8a..1449c9b96 100644 --- a/fpga/lib/utils.cpp +++ b/fpga/lib/utils.cpp @@ -130,20 +130,20 @@ int fpga::ConnectString::portStringToInt(std::string &str) const { } // parses a string like "1->2" or "1<->stdout" and configures the crossbar accordingly -void fpga::ConnectString::configCrossBar( +bool fpga::ConnectString::configCrossBar( std::shared_ptr card) const { auto dma = std::dynamic_pointer_cast( card->lookupIp(fpga::Vlnv("xilinx.com:ip:axi_dma:"))); if (dma == nullptr) { logger->error("No DMA found on FPGA "); - throw std::runtime_error("No DMA found on FPGA"); + return false; } if (isDmaLoopback()) { log->info("Configuring DMA loopback"); dma->connectLoopback(); - return; + return true; } auto aurora_channels = getAuroraChannels(card); @@ -155,7 +155,7 @@ void fpga::ConnectString::configCrossBar( } auto dinoAdc = std::dynamic_pointer_cast( - card->lookupIp(fpga::Vlnv("xilinx.com:module_ref:dinoif_fast:"))); + card->lookupIp(fpga::Vlnv("xilinx.com:module_ref:dinoif_adc:"))); if (dinoAdc == nullptr) { logger->warn("No Dino ADC found on FPGA "); } @@ -176,7 +176,12 @@ void fpga::ConnectString::configCrossBar( } else if (aurora_channels->size() > 0) { src = (*aurora_channels)[srcAsInt]; } else { - throw std::runtime_error("No Aurora channels found on FPGA"); + logger->error("No Aurora channels found on FPGA"); + return false; + } + if (!src) { + logger->error("Source does not exist"); + return false; } if (dinoDac && dstType == ConnectType::DINO) { @@ -185,6 +190,13 @@ void fpga::ConnectString::configCrossBar( dest = dma; } else if (aurora_channels->size() > 0) { dest = (*aurora_channels)[dstAsInt]; + } else { + logger->error("No Aurora channels found on FPGA"); + return false; + } + if (!dest) { + logger->error("Destination does not exist"); + return false; } src->connect(src->getDefaultMasterPort(), dest->getDefaultSlavePort()); @@ -197,6 +209,7 @@ void fpga::ConnectString::configCrossBar( } dest->connect(dest->getDefaultMasterPort(), src->getDefaultSlavePort()); } + return true; } void fpga::setupColorHandling() { diff --git a/fpga/src/villas-fpga-ctrl.cpp b/fpga/src/villas-fpga-ctrl.cpp index ccf034199..d475bcc30 100644 --- a/fpga/src/villas-fpga-ctrl.cpp +++ b/fpga/src/villas-fpga-ctrl.cpp @@ -186,7 +186,10 @@ int main(int argc, char *argv[]) { // Configure Crossbar switch for (std::string str : connectStr) { const fpga::ConnectString parsedConnectString(str); - parsedConnectString.configCrossBar(card); + if (!parsedConnectString.configCrossBar(card)) { + logger->error("Failed to configure crossbar"); + return -1; + } if (parsedConnectString.isSrcStdin()) { readFromStdin = true; if (parsedConnectString.isBidirectional()) { diff --git a/lib/hooks/cast.cpp b/lib/hooks/cast.cpp index 418fc5a31..73a880b8d 100644 --- a/lib/hooks/cast.cpp +++ b/lib/hooks/cast.cpp @@ -92,9 +92,10 @@ class CastHook : public MultiSignalHook { // Register hook static char n[] = "cast"; static char d[] = "Cast signals types"; -static HookPlugin - p; +static constexpr int flags = (int)Hook::Flags::NODE_READ | + (int)Hook::Flags::NODE_WRITE | + (int)Hook::Flags::PATH; +static HookPlugin p; } // namespace node } // namespace villas diff --git a/lib/nodes/fpga.cpp b/lib/nodes/fpga.cpp index 3e12653c2..8309341b1 100644 --- a/lib/nodes/fpga.cpp +++ b/lib/nodes/fpga.cpp @@ -69,7 +69,10 @@ int FpgaNode::prepare() { // Configure Crossbar switch for (std::string str : connectStrings) { const fpga::ConnectString parsedConnectString(str); - parsedConnectString.configCrossBar(card); + if (!parsedConnectString.configCrossBar(card)) { + logger->error("Failed to configure crossbar"); + return -1; + } } auto reg = std::dynamic_pointer_cast( diff --git a/tools/hwdef-parse.py b/tools/hwdef-parse.py index 510ef0e48..d7741b557 100755 --- a/tools/hwdef-parse.py +++ b/tools/hwdef-parse.py @@ -6,10 +6,12 @@ Author: Daniel Krebs Author: Hatim Kanchwala Author: Pascal Bauer +Author: Niklas Eiling SPDX-FileCopyrightText: 2017-2022 Daniel Krebs SPDX-FileCopyrightText: 2017-2022 Hatim Kanchwala SPDX-FileCopyrightText: 2023 Pascal Bauer +SPDX-FileCopyrightText: 2024 Niklas Eiling SPDX-License-Identifier: GPL-3.0-or-later This program is free software: you can redistribute it and/or modify @@ -47,9 +49,11 @@ ["xilinx.com", "ip", "axi_iic"], ["xilinx.com", "module_ref", "dinoif_fast"], ["xilinx.com", "module_ref", "dinoif_fast_nologic"], + ["xilinx.com", "module_ref", "dinoif_adc"], ["xilinx.com", "module_ref", "dinoif_dac"], ["xilinx.com", "module_ref", "axi_pcie_intc"], ["xilinx.com", "module_ref", "registerif"], + ["xilinx.com", "module_ref", "axi_read_cache"], ["xilinx.com", "hls", "rtds2gpu"], ["xilinx.com", "hls", "mem"], ["acs.eonerc.rwth-aachen.de", "user", "axi_pcie_intc"], @@ -69,6 +73,7 @@ ["xilinx.com", "ip", "axis_register_slice"], ["xilinx.com", "ip", "axis_data_fifo"], ["xilinx.com", "ip", "floating_point"], + ["xilinx.com", "module_ref", "prepend_seqnum"], ] opponent = { @@ -253,14 +258,26 @@ def sanitize_name(name): ips[switch.get("INSTANCE")]["num_ports"] = int(switch_ports / 2) # find interrupt assignments -intc = root.find('.//MODULE[@MODTYPE="axi_pcie_intc"]') -if intc is not None: - intr = intc.xpath('.//PORT[@NAME="intr" and @DIR="I"]')[0] - concat = root.xpath( - './/MODULE[@MODTYPE="xlconcat" and .//PORT[@SIGNAME="{}" and @DIR="O"]]'.format( - intr.get("SIGNAME") - ) - )[0] + + + +# find interrupt assignments +intr_controllers = [] +intr_signals = [] + +intc_pcie = root.findall('.//MODULE[@MODTYPE="axi_pcie_intc"]') +intc_zynq = root.findall('.//MODULE[@MODTYPE="zynq_ultra_ps_e"]') + +intr_controllers += intc_pcie +for intc in intc_pcie: + intr_signals.append(intc.xpath('.//PORT[@NAME="intr" and @DIR="I"]')[0].get("SIGNAME")) + +intr_controllers += intc_zynq +for intc in intc_zynq: + intr_signals.append(intc.xpath('.//PORT[@NAME="pl_ps_irq0" and @DIR="I"]')[0].get("SIGNAME")) + +for intc, intr in zip(intr_controllers, intr_signals): + concat = root.xpath('.//MODULE[@MODTYPE="xlconcat" and .//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(intr))[0] ports = concat.xpath('.//PORT[@DIR="I"]') for port in ports: