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Aem boot delay fix #17
base: aem-4.17.4
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I think this PR got closed accidentally due to target branch removed, so I changed its base (didn't rebase the branch) and reopened. |
I can see Krystian deleted the branch and it made a mess from this PR... Anyway, it was not yet solving the problem I had. |
The mess is the result of me changing the target branch to be able to reopen the PR. Rebasing the top 2 commits will fix this, I just didn't want to fix the PR without fixing your local branch. |
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Map the TPM event log after the TXT regions are mapped to avoid an early page fault when booting with slaunch. Signed-off-by: Michał Żygowski <[email protected]>
Right now the MTRRs were restored in an ugly way, while MTRR enable bit was set and caching was not disabled. Mimic the generic Xen MTRR driver behavior when changing MTRRs. Signed-off-by: Michał Żygowski <[email protected]>
The MTRR capabilities and default type were read before the MTRRs were restored in slaunch flow. The restoration itself updated the MTRR default type MSR, so the mtrr_top_of_ram had invalid state in mtrr_cap and mtrr_def variables. Move reading those MSRs after MTRRs are restored in slaunch flow. Signed-off-by: Michał Żygowski <[email protected]>
Do the check if IA32_FEATURE_CONTROL has the proper bits enabled to run VMX in SMX when slaunch is active. Signed-off-by: Michał Żygowski <[email protected]>
…ities The bootloader should prepare the MTRR masks using MAXPHYADDRs. On modern Intel platforms, the SINIT ACM forces this bit to be 1 according to TXT MLE Software Development Guide Revision 017.4. Signed-off-by: Michał Żygowski <[email protected]>
Signed-off-by: Michał Żygowski <[email protected]>
Signed-off-by: Michał Żygowski <[email protected]>
Report the SMX and TXT capabilitiesso that dom0 can query the Intel TXT support information using xl dmesg. Signed-off-by: Michał Żygowski <[email protected]>
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