feat: update project tt_um_wokwi_407306064811090945 from dlmiles/ttih…

…p0p2-ddr-throughput-test

Commit: 08759f2e61f44df21e0c51d635600d4774c612e5
Workflow: https://github.com/dlmiles/ttihp0p2-ddr-throughput-test/actions/runs/11655643966

projects/tt_um_wokwi_407306064811090945/commit_id.json

@@ -1,7 +1,7 @@
 {
   "app": "Tiny Tapeout tt09 b176ed7c",
   "repo": "https://github.com/dlmiles/ttihp0p2-ddr-throughput-test",
-  "commit": "706c018f9508cd6a45776379402667998d67b85f",
-  "workflow_url": "https://github.com/dlmiles/ttihp0p2-ddr-throughput-test/actions/runs/11647899622",
+  "commit": "08759f2e61f44df21e0c51d635600d4774c612e5",
+  "workflow_url": "https://github.com/dlmiles/ttihp0p2-ddr-throughput-test/actions/runs/11655643966",
   "sort_id": 1730602711845
 }

projects/tt_um_wokwi_407306064811090945/stats/metrics.csv

@@ -1,169 +1,169 @@
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 globalplace__flow__warnings__count,0
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 placeopt__timing__drv__max_slew,0
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-placeopt__power__total,6.30338e-05
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 placeopt__design__io,45
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 design__violations,0
 globalroute__design__instance__displacement__total,0
 globalroute__design__instance__displacement__mean,0
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 globalroute__antenna__violating__pins,0
 globalroute__timing__setup__tns,0
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 globalroute__clock__skew__setup,0
 globalroute__clock__skew__hold,0
-globalroute__timing__drv__max_slew_limit,0.97083
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 globalroute__timing__drv__max_slew,0
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 globalroute__timing__drv__max_cap,0
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 globalroute__design__io,45
 globalroute__design__die__area,32880.6
 globalroute__design__core__area,30427.5
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 globalroute__design__instance__count__stdcell,127
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-globalroute__design__instance__utilization__stdcell,0.0395349
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 globalroute__flow__warnings__count,0
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 cts__clock__skew__setup,0
 cts__clock__skew__hold,0
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-cts__power__internal__total,4.14297e-05
-cts__power__switching__total,2.69044e-05
-cts__power__leakage__total,1.79868e-08
-cts__power__total,6.83522e-05
+cts__power__internal__total,4.05113e-05
+cts__power__switching__total,2.63314e-05
+cts__power__leakage__total,1.72509e-08
+cts__power__total,6.686e-05
 cts__design__io,45
 cts__design__die__area,32880.6
 cts__design__core__area,30427.5
 cts__design__instance__count,127
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 cts__design__instance__count__stdcell,127
-cts__design__instance__area__stdcell,1202.95
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 cts__design__instance__count__macros,0
 cts__design__instance__area__macros,0
-cts__design__instance__utilization,0.0395349
-cts__design__instance__utilization__stdcell,0.0395349
+cts__design__instance__utilization,0.0383423
+cts__design__instance__utilization__stdcell,0.0383423
 cts__flow__warnings__count,73
 cts__flow__errors__count,0
 finish__design_powergrid__voltage__worst__net:VPWR__corner:default,1.19998
 finish__design_powergrid__drop__average__net:VPWR__corner:default,1.2
-finish__design_powergrid__drop__worst__net:VPWR__corner:default,1.63283e-05
-finish__design_powergrid__voltage__worst__net:VGND__corner:default,1.89021e-05
-finish__design_powergrid__drop__average__net:VGND__corner:default,1.39058e-06
-finish__design_powergrid__drop__worst__net:VGND__corner:default,1.89021e-05
-finish__design__instance__count__class:fill_cell,102
+finish__design_powergrid__drop__worst__net:VPWR__corner:default,1.76821e-05
+finish__design_powergrid__voltage__worst__net:VGND__corner:default,1.90231e-05
+finish__design_powergrid__drop__average__net:VGND__corner:default,1.30496e-06
+finish__design_powergrid__drop__worst__net:VGND__corner:default,1.90231e-05
+finish__design__instance__count__class:fill_cell,114
 finish__design__instance__count__class:other,2286
 finish__design__instance__count__class:buffer,24
 finish__design__instance__count__class:clock_buffer,1
@@ -172,46 +172,44 @@ finish__design__instance__count__class:clock_inverter,56
 finish__design__instance__count__class:sequential_cell,5
 finish__design__instance__count__class:multi_input_combinational_cell,30
 finish__timing__setup__tns,0
-finish__timing__setup__ws,5.2354
+finish__timing__setup__ws,5.25762
 finish__clock__skew__setup,0
 finish__clock__skew__hold,0
-finish__timing__drv__max_slew_limit,0.965196
+finish__timing__drv__max_slew_limit,0.962918
 finish__timing__drv__max_slew,0
-finish__timing__drv__max_cap_limit,0.973409
+finish__timing__drv__max_cap_limit,0.953445
 finish__timing__drv__max_cap,0
 finish__timing__drv__max_fanout_limit,8
 finish__timing__drv__max_fanout,0
 finish__timing__drv__setup_violation_count,0
 finish__timing__drv__hold_violation_count,0
-finish__power__internal__total,4.15085e-05
-finish__power__switching__total,2.65145e-05
-finish__power__leakage__total,1.82029e-06
-finish__power__total,6.98433e-05
+finish__power__internal__total,4.06071e-05
+finish__power__switching__total,2.61731e-05
+finish__power__leakage__total,1.81995e-06
+finish__power__total,6.86001e-05
 finish__design__io,45
 finish__design__die__area,32880.6
 finish__design__core__area,30427.5
 finish__design__instance__count,2413
-finish__design__instance__area,30149.9
+finish__design__instance__area,30119
 finish__design__instance__count__stdcell,2413
-finish__design__instance__area__stdcell,30149.9
+finish__design__instance__area__stdcell,30119
 finish__design__instance__count__macros,0
 finish__design__instance__area__macros,0
-finish__design__instance__utilization,0.990877
-finish__design__instance__utilization__stdcell,0.990877
+finish__design__instance__utilization,0.989863
+finish__design__instance__utilization__stdcell,0.989863
 finish__flow__warnings__count,9
 finish__flow__errors__count,0
 detailedroute__route__net,146
 detailedroute__route__net__special,2
-detailedroute__route__drc_errors__iter:1,4
-detailedroute__route__wirelength__iter:1,1218
-detailedroute__route__drc_errors__iter:2,1
-detailedroute__route__wirelength__iter:2,1206
-detailedroute__route__drc_errors__iter:3,0
-detailedroute__route__wirelength__iter:3,1206
+detailedroute__route__drc_errors__iter:1,15
+detailedroute__route__wirelength__iter:1,1137
+detailedroute__route__drc_errors__iter:2,0
+detailedroute__route__wirelength__iter:2,1133
 detailedroute__route__drc_errors,0
-detailedroute__route__wirelength,1206
-detailedroute__route__vias,412
-detailedroute__route__vias__singlecut,412
+detailedroute__route__wirelength,1133
+detailedroute__route__vias,406
+detailedroute__route__vias__singlecut,406
 detailedroute__route__vias__multicut,0
 detailedroute__antenna__violating__nets,0
 detailedroute__antenna__violating__pins,0
@@ -227,21 +225,21 @@ run__flow__platform__current_units,1uA
 run__flow__platform__power_units,1pW
 run__flow__platform__distance_units,1um
 floorplan__timing__setup__tns,0
-floorplan__timing__setup__ws,5.71266
-floorplan__power__internal__total,3.8825e-05
-floorplan__power__switching__total,2.27973e-05
-floorplan__power__leakage__total,1.47842e-08
-floorplan__power__total,6.1637e-05
+floorplan__timing__setup__ws,5.75869
+floorplan__power__internal__total,3.79361e-05
+floorplan__power__switching__total,2.27227e-05
+floorplan__power__leakage__total,1.40483e-08
+floorplan__power__total,6.06728e-05
 floorplan__design__io,43
 floorplan__design__die__area,32880.6
 floorplan__design__core__area,30427.5
 floorplan__design__instance__count,92
-floorplan__design__instance__area,947.117
+floorplan__design__instance__area,910.829
 floorplan__design__instance__count__stdcell,92
-floorplan__design__instance__area__stdcell,947.117
+floorplan__design__instance__area__stdcell,910.829
 floorplan__design__instance__count__macros,0
 floorplan__design__instance__area__macros,0
-floorplan__design__instance__utilization,0.031127
-floorplan__design__instance__utilization__stdcell,0.031127
+floorplan__design__instance__utilization,0.0299344
+floorplan__design__instance__utilization__stdcell,0.0299344
 floorplan__flow__warnings__count,46
 floorplan__flow__errors__count,0

projects/tt_um_wokwi_407306064811090945/stats/synthesis-stats.txt

@@ -15,12 +15,12 @@
    Number of cells:                 92
      sg13g2_and2_2                   8
      sg13g2_buf_1                   24
-     sg13g2_dfrbp_2                  5
+     sg13g2_dfrbp_1                  5
      sg13g2_inv_2                   49
      sg13g2_or2_2                    4
      sg13g2_tiehi                    1
      sg13g2_tielo                    1
 
-   Chip area for module '\tt_um_wokwi_407306064811090945': 947.116800
-     of which used for sequential elements: 272.160000 (28.74%)
+   Chip area for module '\tt_um_wokwi_407306064811090945': 910.828800
+     of which used for sequential elements: 235.872000 (25.90%)