feat: update project tt_um_algofoogle_vga_fun_wrapper from htfab/ttih…

…p0p2-demo-vgafun

Commit: 66b2887f1a7c4b11c0cda86d33040fd80eb51f88
Workflow: https://github.com/htfab/ttihp0p2-demo-vgafun/actions/runs/11671367856

projects/tt_um_algofoogle_vga_fun_wrapper/commit_id.json

@@ -1,7 +1,7 @@
 {
   "app": "Tiny Tapeout tt09 b176ed7c",
   "repo": "https://github.com/htfab/ttihp0p2-demo-vgafun",
-  "commit": "08e90f182fdf9e20e07fc6c260bf5ad84b33f29e",
-  "workflow_url": "https://github.com/htfab/ttihp0p2-demo-vgafun/actions/runs/11658120577",
+  "commit": "66b2887f1a7c4b11c0cda86d33040fd80eb51f88",
+  "workflow_url": "https://github.com/htfab/ttihp0p2-demo-vgafun/actions/runs/11671367856",
   "sort_id": 1730695648016
 }

projects/tt_um_algofoogle_vga_fun_wrapper/stats/synthesis-stats.txt

@@ -3,56 +3,56 @@
 
 === tt_um_algofoogle_vga_fun_wrapper ===
 
-   Number of wires:               2121
-   Number of wire bits:           2156
-   Number of public wires:         132
-   Number of public wire bits:     167
+   Number of wires:               2231
+   Number of wire bits:           2266
+   Number of public wires:         108
+   Number of public wire bits:     143
    Number of ports:                  8
    Number of port bits:             43
    Number of memories:               0
    Number of memory bits:            0
    Number of processes:              0
-   Number of cells:               2009
-     sg13g2_a21o_1                  11
-     sg13g2_a21o_2                   1
-     sg13g2_a21oi_1                153
-     sg13g2_a21oi_2                  8
-     sg13g2_a221oi_1                 6
-     sg13g2_a22oi_1                 16
-     sg13g2_and2_1                   1
-     sg13g2_and3_1                   5
-     sg13g2_buf_1                   86
-     sg13g2_buf_16                   3
-     sg13g2_buf_2                   17
-     sg13g2_buf_4                   12
+   Number of cells:               2143
+     sg13g2_a21o_1                  12
+     sg13g2_a21oi_1                169
+     sg13g2_a21oi_2                 20
+     sg13g2_a221oi_1                10
+     sg13g2_a22oi_1                 23
+     sg13g2_and2_1                   2
+     sg13g2_and3_1                   4
+     sg13g2_buf_1                   77
+     sg13g2_buf_16                   2
+     sg13g2_buf_2                   20
+     sg13g2_buf_4                   22
      sg13g2_buf_8                   24
-     sg13g2_dfrbp_1                128
-     sg13g2_inv_1                  231
-     sg13g2_inv_2                   11
+     sg13g2_dfrbp_1                104
+     sg13g2_inv_1                  239
+     sg13g2_inv_2                   14
      sg13g2_inv_4                    5
+     sg13g2_inv_8                    1
      sg13g2_mux2_1                   5
-     sg13g2_nand2_1                325
-     sg13g2_nand2_2                 99
-     sg13g2_nand2b_1                61
-     sg13g2_nand2b_2                10
-     sg13g2_nand3_1                104
-     sg13g2_nand3b_1                12
-     sg13g2_nand4_1                 19
-     sg13g2_nor2_1                 202
-     sg13g2_nor2_2                  22
-     sg13g2_nor2b_1                 24
-     sg13g2_nor2b_2                  6
-     sg13g2_nor3_1                  92
-     sg13g2_nor3_2                   5
-     sg13g2_nor4_1                  22
+     sg13g2_nand2_1                359
+     sg13g2_nand2_2                125
+     sg13g2_nand2b_1                36
+     sg13g2_nand2b_2                 4
+     sg13g2_nand3_1                171
+     sg13g2_nand3b_1                 9
+     sg13g2_nand4_1                 22
+     sg13g2_nor2_1                 212
+     sg13g2_nor2_2                  24
+     sg13g2_nor2b_1                 35
+     sg13g2_nor2b_2                  7
+     sg13g2_nor3_1                  91
+     sg13g2_nor3_2                   1
+     sg13g2_nor4_1                   8
      sg13g2_nor4_2                   1
-     sg13g2_o21ai_1                123
-     sg13g2_or2_2                    1
+     sg13g2_o21ai_1                111
+     sg13g2_or2_1                    1
      sg13g2_tiehi                    1
      sg13g2_tielo                    1
-     sg13g2_xnor2_1                116
-     sg13g2_xor2_1                  40
+     sg13g2_xnor2_1                141
+     sg13g2_xor2_1                  30
 
-   Chip area for module '\tt_um_algofoogle_vga_fun_wrapper': 23187.427200
-     of which used for sequential elements: 6038.323200 (26.04%)
+   Chip area for module '\tt_um_algofoogle_vga_fun_wrapper': 23553.671400
+     of which used for sequential elements: 4906.137600 (20.83%)
 

projects/tt_um_algofoogle_vga_fun_wrapper/tt_um_algofoogle_vga_fun_wrapper.lef

@@ -411,15 +411,15 @@ MACRO tt_um_algofoogle_vga_fun_wrapper
   END VPWR
   OBS
     LAYER Metal1 ;
-     RECT  2.605 3.215 209.28 154.98 ;
+     RECT  2.555 2.795 209.28 154.98 ;
     LAYER Metal2 ;
-     RECT  2.605 3.215 209.28 154.98 ;
+     RECT  2.555 2.795 209.28 154.98 ;
     LAYER Metal3 ;
-     RECT  2.605 3.215 209.28 154.98 ;
+     RECT  2.555 2.795 209.28 154.98 ;
     LAYER Metal4 ;
-     RECT  2.605 3.215 209.28 154.98 ;
+     RECT  2.555 2.795 209.28 154.98 ;
     LAYER Metal5 ;
-     RECT  2.605 3.215 209.28 154.98 ;
+     RECT  2.555 2.795 209.28 154.98 ;
   END
 END tt_um_algofoogle_vga_fun_wrapper
 END LIBRARY