From 91f5811390e5584ba6cf4004ca167fc0913c2641 Mon Sep 17 00:00:00 2001 From: TinyTapeoutBot <139130078+TinyTapeoutBot@users.noreply.github.com> Date: Fri, 19 Apr 2024 01:36:21 +0300 Subject: [PATCH] feat: update project tt_um_ejfogleman_smsdac from ejfogleman/ef_smsdac Commit: 65fd05492cf31a53f0d17d11e8dfa3052d8aa094 Workflow: https://github.com/ejfogleman/ef_smsdac/actions/runs/8745545111 --- .../tt_um_ejfogleman_smsdac/commit_id.json | 4 +-- projects/tt_um_ejfogleman_smsdac/docs/info.md | 25 ++++++++++++++---- projects/tt_um_ejfogleman_smsdac/info.yaml | 2 +- .../tt_um_ejfogleman_smsdac/stats/metrics.csv | 2 +- .../tt_um_ejfogleman_smsdac.gds | Bin 965438 -> 965438 bytes .../tt_um_ejfogleman_smsdac.spef | 2 +- 6 files changed, 25 insertions(+), 10 deletions(-) diff --git a/projects/tt_um_ejfogleman_smsdac/commit_id.json b/projects/tt_um_ejfogleman_smsdac/commit_id.json index acfb35e..907a79d 100644 --- a/projects/tt_um_ejfogleman_smsdac/commit_id.json +++ b/projects/tt_um_ejfogleman_smsdac/commit_id.json @@ -1,8 +1,8 @@ { "app": "Tiny Tapeout tt06 c74b14ac", "repo": "https://github.com/ejfogleman/ef_smsdac", - "commit": "8ad0831be891e70cbb849361effa274c952b82f3", - "workflow_url": "https://github.com/ejfogleman/ef_smsdac/actions/runs/8743080092", + "commit": "65fd05492cf31a53f0d17d11e8dfa3052d8aa094", + "workflow_url": "https://github.com/ejfogleman/ef_smsdac/actions/runs/8745545111", "sort_id": 1713416365011, "openlane_version": "OpenLane eaba5192c45aa333ab45216ce1773d75d539e9b3", "pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943" diff --git a/projects/tt_um_ejfogleman_smsdac/docs/info.md b/projects/tt_um_ejfogleman_smsdac/docs/info.md index 2d80ca0..2db3b62 100644 --- a/projects/tt_um_ejfogleman_smsdac/docs/info.md +++ b/projects/tt_um_ejfogleman_smsdac/docs/info.md @@ -9,17 +9,32 @@ You can also include images in this folder and reference them in the markdown. E ## Operation -This design implements a linear 8-bit DAC suitable for low-frequency inputs. An analog voltage is produced by connecting the encoder's outputs to a modified R-2R ladder on the PCB. The modification converts it into an R-(4R-4R) ladder. It achieves high-linearity by using segmented mismatch-shaping, so the DAC does not require matched resistors. Error due to resistor mismatch appears at the output as 1st-order highpass shaped noise. The encoder also reduces the bit-width from 8-bits, and quantization error is also 1st-order highpass shaped. Thus, with passive filtering, a linear, low-noise dc output can be achieved. +This design implements a linear 8-bit DAC suitable for dc and low-frequency inputs. An analog voltage is produced by connecting the encoder's outputs to a modified R-2R ladder on the PCB (see External Hardware). It achieves high-linearity by using segmented mismatch-shaping, so the DAC does not require matched resistors. The encoder provides 1st order mismatch and quantization noise shaping. With a clock frequency of 6.144 MHz and a lowpass filter corner of 24 kHz, the oversampling ratio (OSR) is 256. + +Error due to resistor mismatch appears at the output as 1st-order highpass shaped noise. The encoder also reduces the bit-width from 8-bits, and quantization error is also 1st-order highpass shaped. Thus, with passive filtering, a linear, low-noise dc output can be achieved. The theory behind this encoder is described in: [A. Fishov, E. Fogleman, E. Siragusa, I. Galton, "Segmented Mismatch-Shaping D/A Conversion", IEEE International Symposium on Circuits and Systems (ISCAS), 2002](https://https://ieeexplore.ieee.org/document/1010547/) Ideally, this encoder would be buffered through a clean analog supply and retimed to reduce glitches on output transitions. However, reasonable performance should be possible driving the resistor ladder directly from the encoder through the IO supply. ## How to test -Digital testing is possible by applying clock (1-50 MHz), a static data input on ui[7:0], and summing the output on uo[7:0] with the following weights: -d_out = 8*uo[7:6] + 4*uo[5:4] + 2*uo[3:2] + uo[1:0] +DAC input data is provided through `ui_in[7:0]`, and the encoder uses the project clock for mismatch shaping. Clock frequencies in the range of 1-10 MHz are reasonable. Higher clock frequency increases the OSR but may increase glitch error. The encoder output is `uo_out[7:0]`, and it can be reconstructed by summing the bits with the following weights: + + out = 8*uo_out[7]+uo_out[6]) + 4*(uo_out[5]+uo_out[4]) + 2*uo_out[3]+uo_out[2]) + uo_out[1]+uo_out[0] + +The resistor ladder shown below sums the outputs with this weighting. Any output network that can create this weighting will work. -The DAC is free-running off the project clock, and inputs appear at the output immediately after passing through a pair of clock sync registers. +The DAC is free-running off the project clock, and inputs appear at the output immediately after passing through a pair of clock sync registers. A simple dc test can be performed using the input DIP switches and the resistor ladder. It is possible to input dynamic waveforms from the microcontroller as well. + +The encoder has four modes of operation determined by `uio_in[1:0]`: +* 3: 1st order mismatch-shaping with dither +* 2: randomization (flat spectral shaping) +* 1: 1st order shaping, no dither +* 0: static encoding (no linearization) ## External hardware -An external resistor ladder is required to create the analog output voltage, and a capacitor is required to filter high-frequency noise. +Technically, this is a mismatch shaping DAC encoder. For a high-performance DAC, it is best to use a precision reference voltage and a clean clock source for edge retiming. However, it is possible to connect the encoder directly to a resistor ladder. In this case, the digital IO supply acts as the DAC's reference voltage, and timing skews between the `uo_out` bits may impact performance. + +An external resistor ladder is required to create the analog output voltage, and a capacitor is required to filter high-frequency noise. The termination resistors are placed at the ends of the ladder to ensure that each section has nominally identical load resistance. + +The suggested unit R value is 10 kOhm. The equivalent output resistance of the network at __v_out__ is 10 kOhm. A 680 pF output capacitor provides a 23 kHz lowpass corner. With this choice of R, the minimum load resistance on each `uo_out` pin is 60 kOhm, and the driver will source a maximum of 55 uA at 3.3 V. diff --git a/projects/tt_um_ejfogleman_smsdac/info.yaml b/projects/tt_um_ejfogleman_smsdac/info.yaml index c3135ac..d9eeea2 100644 --- a/projects/tt_um_ejfogleman_smsdac/info.yaml +++ b/projects/tt_um_ejfogleman_smsdac/info.yaml @@ -1,6 +1,6 @@ # Tiny Tapeout project information project: - title: "ef_smsdac" # Project title + title: "8-bit DEM R2R DAC" # Project title author: "Eric Fogleman" # Your name discord: "ejfogleman" # Your discord username, for communication and automatically assigning you a Tapeout role (optional) description: "8-bit segmented mismatch-shaping R2R DAC" # One line description of what your project does diff --git a/projects/tt_um_ejfogleman_smsdac/stats/metrics.csv b/projects/tt_um_ejfogleman_smsdac/stats/metrics.csv index 37af341..267727a 100644 --- a/projects/tt_um_ejfogleman_smsdac/stats/metrics.csv +++ b/projects/tt_um_ejfogleman_smsdac/stats/metrics.csv @@ -1,2 +1,2 @@ design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY -/work/src,tt_um_ejfogleman_smsdac,wokwi,flow completed,0h1m0s0ms,0h0m42s0ms,24951.65616617803,0.01795472,12475.828083089014,13.94,17.2811,508.14,169,0,0,0,0,0,0,0,1,1,0,-1,-1,3955,1346,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,2117570.0,0.0,9.24,6.05,0.61,1.35,-1,159,289,108,238,0,0,0,107,2,24,2,0,2,10,2,20,35,32,11,1082,225,0,253,224,1784,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0 +/work/src,tt_um_ejfogleman_smsdac,wokwi,flow completed,0h1m1s0ms,0h0m43s0ms,24951.65616617803,0.01795472,12475.828083089014,13.94,17.2811,508.0,169,0,0,0,0,0,0,0,1,1,0,-1,-1,3955,1346,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,2117570.0,0.0,9.24,6.05,0.61,1.35,-1,159,289,108,238,0,0,0,107,2,24,2,0,2,10,2,20,35,32,11,1082,225,0,253,224,1784,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0 diff --git a/projects/tt_um_ejfogleman_smsdac/tt_um_ejfogleman_smsdac.gds b/projects/tt_um_ejfogleman_smsdac/tt_um_ejfogleman_smsdac.gds index db9b574bb484180289b095fb4570ef39dce700c6..e3950b71976d6598a993cb279d14f325ea062bb9 100644 GIT binary patch delta 874 zcmYjPO=uHA7|qONcDJ!fqjonxHmyp%2tq0-QiF}4P)zRobAf3N19?r3cYqL{JarPzj2M`nB0*=kQ?X&HH}do1Lq5&eb~a z#x%pT!?V}ZLPcMdMelX(<{Ly|Xg*N?63@01LnLcVwT?9%@wucfs?@7lGm(n7PFmBg zw-xu^5WT;#D79-rDl(=LUe($cZ*O#k*vN;CMiS?^OBy10oU7K_;irC=)UDZ6yKbN3 z&uNQA2a3|3A(1`L73*u}{z17Yn_rB&=aA?cLea?LheLJJoNm>{mDfA~!wqDAs7?af z{*iF2bg<5liZlCjj)kC*A!mbZCO}xmE81zn%LbH68U*ej{2fEF2-aqx8u8KVi zREM!gq$CFcgE^88+fNcz#Py#%4Bv|6rQ}hEnPu`OVsAP2oy4}vgHk5fp!knWY_Zw( zn4mvEA9l#HQVC^kN!rt7v)CvMlPUUXn@boldXbLXfe2JYplzIvIw2roh+jpnLh%8; zxcmhZdz=kFzem!R;B7A5vBNk#fh%m>4rG4 zL^YUrOp0<4Fq|dHp!FnSMcnwwgYd0DUP&G`m|G)nL)MlP-$`VbJSdUjDir>asYZ+4 ziU|h&^ihW_D;81K8mGMt7K@F7FrA>Eb~}U)W{UjJ!1ZgaYMa1U)gXPB_1f#=OK#c$ZW)3