From 949014ccde5d256aedfc83f1774e1fa9bacd9a57 Mon Sep 17 00:00:00 2001 From: Cho Moon Date: Fri, 15 Mar 2024 03:28:59 +0000 Subject: [PATCH 01/23] phase 1 for enhanced clock gater handling 1) treat clock gaters like macro cell instances 2) need to change arrival computation Signed-off-by: Cho Moon --- src/cts/include/cts/TritonCTS.h | 11 +- src/cts/src/TreeBuilder.h | 6 + src/cts/src/TritonCTS.cpp | 44 ++++--- src/cts/test/balance_levels.defok | 212 +++++++++--------------------- src/cts/test/balance_levels.ok | 57 +++++--- src/cts/test/balance_levels.py | 3 +- src/cts/test/cts_aux.py | 4 +- 7 files changed, 148 insertions(+), 189 deletions(-) diff --git a/src/cts/include/cts/TritonCTS.h b/src/cts/include/cts/TritonCTS.h index 21de9958136..47ee2bc2ac1 100644 --- a/src/cts/include/cts/TritonCTS.h +++ b/src/cts/include/cts/TritonCTS.h @@ -130,7 +130,7 @@ class TritonCTS // db functions bool masterExists(const std::string& master) const; void populateTritonCTS(); - void writeClockNetsToDb(Clock& clockNet, std::set& clkLeafNets); + void writeClockNetsToDb(TreeBuilder* builder, std::set& clkLeafNets); void writeClockNDRsToDb(const std::set& clkLeafNets); void incrementNumClocks() { ++numberOfClocks_; } void clearNumClocks() { numberOfClocks_ = 0; } @@ -166,7 +166,8 @@ class TritonCTS Clock& clockNet, const std::vector>& registerSinks, odb::dbNet*& firstNet, - odb::dbNet*& secondNet); + odb::dbNet*& secondNet, + std::string& topBufferName); void computeITermPosition(odb::dbITerm* term, int& x, int& y) const; void countSinksPostDbWrite(TreeBuilder* builder, odb::dbNet* net, @@ -212,7 +213,6 @@ class TritonCTS void adjustLatencies(TreeBuilder* macroBuilder, TreeBuilder* registerBuilder); void computeTopBufferDelay(TreeBuilder* builder); odb::dbInst* insertDelayBuffer(odb::dbInst* driver, - int index, const std::string& clockName, int locX, int locY); @@ -240,6 +240,11 @@ class TritonCTS // root buffer and sink bufer candidates std::vector rootBuffers_; std::vector sinkBuffers_; + + // register tree root buffer indices + unsigned regTreeRootBufIndex_ = 0; + // index for delay buffer added for latency adjustment + unsigned delayBufIndex_ = 0; }; } // namespace cts diff --git a/src/cts/src/TreeBuilder.h b/src/cts/src/TreeBuilder.h index 8ac102bc759..ec15843ff06 100644 --- a/src/cts/src/TreeBuilder.h +++ b/src/cts/src/TreeBuilder.h @@ -247,6 +247,10 @@ class TreeBuilder void setTopBufferDelay(float delay) { topBufferDelay_ = delay; } odb::dbInst* getTopBuffer() const { return topBuffer_; } void setTopBuffer(odb::dbInst* inst) { topBuffer_ = inst; } + std::string getTopBufferName() const { return topBufferName_; } + void setTopBufferName(std::string name) { topBufferName_ = name; } + odb::dbNet* getTopInputNet() const { return topInputNet_; } + void setTopInputNet(odb::dbNet* net) { topInputNet_ = net; } protected: CtsOptions* options_ = nullptr; @@ -276,6 +280,8 @@ class TreeBuilder float aveArrival_ = 0.0; float topBufferDelay_ = 0.0; odb::dbInst* topBuffer_ = nullptr; + std::string topBufferName_; + odb::dbNet* topInputNet_ = nullptr; }; } // namespace cts diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index ac1fd07c64c..6dc4d5e5f70 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -359,7 +359,7 @@ void TritonCTS::writeDataToDb() { std::set clkLeafNets; for (TreeBuilder* builder : *builders_) { - writeClockNetsToDb(builder->getClock(), clkLeafNets); + writeClockNetsToDb(builder, clkLeafNets); if (options_->applyNDR()) { writeClockNDRsToDb(clkLeafNets); } @@ -1010,8 +1010,9 @@ HTreeBuilder* TritonCTS::initClockTreeForMacrosAndRegs( // create a new net 'secondNet' to drive register sinks odb::dbNet* secondNet; - Clock clockNet2 - = forkRegisterClockNetwork(clockNet, registerSinks, firstNet, secondNet); + std::string topBufferName; + Clock clockNet2 = forkRegisterClockNetwork( + clockNet, registerSinks, firstNet, secondNet, topBufferName); // add register sinks to secondNet HTreeBuilder* secondBuilder = addClockSinks( @@ -1022,6 +1023,8 @@ HTreeBuilder* TritonCTS::initClockTreeForMacrosAndRegs( "registers"); if (secondBuilder) { secondBuilder->setTreeType(TreeType::RegisterTree); + secondBuilder->setTopBufferName(topBufferName); + secondBuilder->setTopInputNet(firstNet); } return secondBuilder; @@ -1050,7 +1053,8 @@ bool TritonCTS::separateMacroRegSinks( if (iterm->isInputSignal() && inst->isPlaced()) { odb::dbMTerm* mterm = iterm->getMTerm(); - if (hasInsertionDelay(inst, mterm)) { + // Treat clock gaters like macro sink + if (hasInsertionDelay(inst, mterm) || !isSink(iterm)) { macroSinks.emplace_back(inst, mterm); } else { registerSinks.emplace_back(inst, mterm); @@ -1098,7 +1102,8 @@ Clock TritonCTS::forkRegisterClockNetwork( Clock& clockNet, const std::vector>& registerSinks, odb::dbNet*& firstNet, - odb::dbNet*& secondNet) + odb::dbNet*& secondNet, + std::string& topBufferName) { // create a new clock net to drive register sinks std::string newClockName = clockNet.getName() + "_" + "regs"; @@ -1116,8 +1121,10 @@ Clock TritonCTS::forkRegisterClockNetwork( // create a new clock buffer odb::dbMaster* master = db_->findMaster(options_->getRootBuffer().c_str()); - std::string cellName = "clkbuf_regs_0_" + clockNet.getSdcName(); - odb::dbInst* clockBuf = odb::dbInst::create(block_, master, cellName.c_str()); + topBufferName = "clkbuf_regs_" + std::to_string(regTreeRootBufIndex_++) + "_" + + clockNet.getSdcName(); + odb::dbInst* clockBuf + = odb::dbInst::create(block_, master, topBufferName.c_str()); odb::dbITerm* inputTerm = getFirstInput(clockBuf); odb::dbITerm* outputTerm = clockBuf->getFirstOutput(); inputTerm->connect(firstNet); @@ -1162,19 +1169,22 @@ void TritonCTS::computeITermPosition(odb::dbITerm* term, int& x, int& y) const } }; -void TritonCTS::writeClockNetsToDb(Clock& clockNet, +void TritonCTS::writeClockNetsToDb(TreeBuilder* builder, std::set& clkLeafNets) { + Clock& clockNet = builder->getClock(); odb::dbNet* topClockNet = clockNet.getNetObj(); disconnectAllSinksFromNet(topClockNet); // re-connect top buffer that separates macros from registers - std::string topRegBufferName = "clkbuf_regs_0_" + clockNet.getName(); - odb::dbInst* topRegBuffer = block_->findInst(topRegBufferName.c_str()); - if (topRegBuffer) { - odb::dbITerm* topRegBufferInputPin = getFirstInput(topRegBuffer); - topRegBufferInputPin->connect(topClockNet); + if (builder->getTreeType() == TreeType::RegisterTree) { + odb::dbInst* topRegBuffer + = block_->findInst(builder->getTopBufferName().c_str()); + if (topRegBuffer) { + odb::dbITerm* topRegBufferInputPin = getFirstInput(topRegBuffer); + topRegBufferInputPin->connect(builder->getTopInputNet()); + } } createClockBuffers(clockNet); @@ -2032,7 +2042,6 @@ void TritonCTS::adjustLatencies(TreeBuilder* macroBuilder, = builder->legalizeOneBuffer(bufferLoc, options_->getRootBuffer()); odb::dbInst* buffer = insertDelayBuffer(driver, - i, builder->getClock().getSdcName(), legalBufferLoc.getX() * scalingFactor, legalBufferLoc.getY() * scalingFactor); @@ -2050,7 +2059,7 @@ void TritonCTS::computeTopBufferDelay(TreeBuilder* builder) Clock clock = builder->getClock(); std::string topBufferName; if (builder->getTreeType() == TreeType::RegisterTree) { - topBufferName = "clkbuf_regs_0_" + clock.getSdcName(); + topBufferName = builder->getTopBufferName(); } else { topBufferName = "clkbuf_0_" + clock.getName(); } @@ -2084,20 +2093,19 @@ void TritonCTS::computeTopBufferDelay(TreeBuilder* builder) // Create a new delay buffer and connect output pin of driver to input pin of // new buffer. Output pin of new buffer will be connected later. odb::dbInst* TritonCTS::insertDelayBuffer(odb::dbInst* driver, - int index, const std::string& clockName, int locX, int locY) { // creat a new input net std::string newNetName - = "delaynet_" + std::to_string(index) + "_" + clockName; + = "delaynet_" + std::to_string(delayBufIndex_) + "_" + clockName; odb::dbNet* newNet = odb::dbNet::create(block_, newNetName.c_str()); newNet->setSigType(odb::dbSigType::CLOCK); // create a new delay buffer std::string newBufName - = "delaybuf_" + std::to_string(index) + "_" + clockName; + = "delaybuf_" + std::to_string(delayBufIndex_++) + "_" + clockName; odb::dbMaster* master = db_->findMaster(options_->getRootBuffer().c_str()); odb::dbInst* newBuf = odb::dbInst::create(block_, master, newBufName.c_str()); newBuf->setSourceType(odb::dbSourceType::TIMING); diff --git a/src/cts/test/balance_levels.defok b/src/cts/test/balance_levels.defok index c1483a4166b..a231b0515c1 100644 --- a/src/cts/test/balance_levels.defok +++ b/src/cts/test/balance_levels.defok @@ -4,90 +4,45 @@ BUSBITCHARS "[]" ; DESIGN multi_sink ; UNITS DISTANCE MICRONS 2000 ; DIEAREA ( 0 0 ) ( 200000 200000 ) ; -COMPONENTS 383 ; +COMPONENTS 338 ; - CELL/CKGATE BUF_X1 + PLACED ( 100000 100000 ) N ; - clkbuf_0_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 103228 140117 ) N ; - - clkbuf_0_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 103228 51229 ) N ; + - clkbuf_0_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 100250 101225 ) N ; + - clkbuf_0_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 103228 51229 ) N ; + - clkbuf_1_0__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 100250 87225 ) N ; - clkbuf_4_0__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 35318 119627 ) N ; - - clkbuf_4_0__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 37046 24385 ) N ; + - clkbuf_4_0__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 37181 26644 ) N ; - clkbuf_4_10__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 169474 113337 ) N ; - - clkbuf_4_10__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 169474 24449 ) N ; + - clkbuf_4_10__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 169474 24449 ) N ; - clkbuf_4_11__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 176988 120851 ) N ; - - clkbuf_4_11__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 176988 31963 ) N ; + - clkbuf_4_11__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 176988 31963 ) N ; - clkbuf_4_12__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 136180 148710 ) N ; - - clkbuf_4_12__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 135454 59367 ) N ; + - clkbuf_4_12__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 135454 59367 ) N ; - clkbuf_4_13__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 138264 161152 ) N ; - - clkbuf_4_13__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 137599 71599 ) N ; + - clkbuf_4_13__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 137599 71599 ) N ; - clkbuf_4_14__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 175261 148092 ) N ; - - clkbuf_4_14__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 175738 59340 ) N ; + - clkbuf_4_14__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 175738 59340 ) N ; - clkbuf_4_15__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 173171 159411 ) N ; - - clkbuf_4_15__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 173942 71102 ) N ; + - clkbuf_4_15__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 173942 71102 ) N ; - clkbuf_4_1__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 31476 129670 ) N ; - - clkbuf_4_1__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 30387 31043 ) N ; + - clkbuf_4_1__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 28978 35266 ) N ; - clkbuf_4_2__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 68717 119605 ) N ; - - clkbuf_4_2__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 64508 26508 ) N ; + - clkbuf_4_2__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 66913 28914 ) N ; - clkbuf_4_3__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 71061 131581 ) N ; - - clkbuf_4_3__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 71219 35368 ) N ; + - clkbuf_4_3__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 69122 41782 ) N ; - clkbuf_4_4__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 31714 150934 ) N ; - - clkbuf_4_4__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 31830 61223 ) N ; + - clkbuf_4_4__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 30369 61835 ) N ; - clkbuf_4_5__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 33478 164353 ) N ; - - clkbuf_4_5__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 33728 74610 ) N ; + - clkbuf_4_5__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 31247 76899 ) N ; - clkbuf_4_6__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 70729 156126 ) N ; - - clkbuf_4_6__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 68707 60992 ) N ; + - clkbuf_4_6__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 68700 66662 ) N ; - clkbuf_4_7__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 64318 165027 ) N ; - - clkbuf_4_7__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 66599 73858 ) N ; + - clkbuf_4_7__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 64650 75806 ) N ; - clkbuf_4_8__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 141948 115396 ) N ; - - clkbuf_4_8__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 141948 26508 ) N ; + - clkbuf_4_8__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 141948 26508 ) N ; - clkbuf_4_9__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 135237 124256 ) N ; - - clkbuf_4_9__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 135237 35368 ) N ; - - clkbuf_level_0_1_1027_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 133484 35513 ) N ; - - clkbuf_level_0_1_10_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 36329 22762 ) N ; - - clkbuf_level_0_1_1130_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 170571 22017 ) N ; - - clkbuf_level_0_1_1233_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 179381 31532 ) N ; - - clkbuf_level_0_1_1336_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 134033 58567 ) N ; - - clkbuf_level_0_1_1439_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 136203 73072 ) N ; - - clkbuf_level_0_1_1542_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 177253 58502 ) N ; - - clkbuf_level_0_1_1645_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 175553 72615 ) N ; - - clkbuf_level_0_1_23_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 27455 30225 ) N ; - - clkbuf_level_0_1_36_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 66780 23660 ) N ; - - clkbuf_level_0_1_49_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 72971 35513 ) N ; - - clkbuf_level_0_1_512_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 30235 60113 ) N ; - - clkbuf_level_0_1_615_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 31658 77098 ) N ; - - clkbuf_level_0_1_718_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 70393 59940 ) N ; - - clkbuf_level_0_1_821_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 68117 75839 ) N ; - - clkbuf_level_0_1_924_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 139675 23660 ) N ; - - clkbuf_level_1_1_1028_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 131732 35659 ) N ; - - clkbuf_level_1_1_1131_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 171668 19585 ) N ; - - clkbuf_level_1_1_11_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 35613 21140 ) N ; - - clkbuf_level_1_1_1234_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 181774 31102 ) N ; - - clkbuf_level_1_1_1337_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 132612 57767 ) N ; - - clkbuf_level_1_1_1440_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 134807 74545 ) N ; - - clkbuf_level_1_1_1543_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 178768 57665 ) N ; - - clkbuf_level_1_1_1646_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 177165 74128 ) N ; - - clkbuf_level_1_1_24_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 24524 29407 ) N ; - - clkbuf_level_1_1_37_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 69053 20813 ) N ; - - clkbuf_level_1_1_410_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 74723 35659 ) N ; - - clkbuf_level_1_1_513_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 28640 59003 ) N ; - - clkbuf_level_1_1_616_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 29589 79586 ) N ; - - clkbuf_level_1_1_719_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 72079 58888 ) N ; - - clkbuf_level_1_1_822_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 69636 77821 ) N ; - - clkbuf_level_1_1_925_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 137402 20813 ) N ; - - clkbuf_level_2_1_1029_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 129980 35805 ) N ; - - clkbuf_level_2_1_1132_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 172765 17153 ) N ; - - clkbuf_level_2_1_1235_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 184167 30671 ) N ; - - clkbuf_level_2_1_12_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 34897 19518 ) N ; - - clkbuf_level_2_1_1338_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 131192 56967 ) N ; - - clkbuf_level_2_1_1441_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 133411 76018 ) N ; - - clkbuf_level_2_1_1544_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 180283 56828 ) N ; - - clkbuf_level_2_1_1647_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 178776 75641 ) N ; - - clkbuf_level_2_1_25_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 21592 28590 ) N ; - - clkbuf_level_2_1_38_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 71326 17965 ) N ; - - clkbuf_level_2_1_411_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 76476 35805 ) N ; - - clkbuf_level_2_1_514_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 27046 57894 ) N ; - - clkbuf_level_2_1_617_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 27520 82074 ) N ; - - clkbuf_level_2_1_720_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 73765 57836 ) N ; - - clkbuf_level_2_1_823_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 71154 79802 ) N ; - - clkbuf_level_2_1_926_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 135130 17965 ) N ; + - clkbuf_4_9__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 135237 35368 ) N ; + - clkbuf_regs_0_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 99481 48451 ) N ; - ff0 DFF_X1 + PLACED ( 5555 5555 ) N ; - ff1 DFF_X1 + PLACED ( 16666 5555 ) N ; - ff10 DFF_X1 + PLACED ( 116665 5555 ) N ; @@ -395,125 +350,80 @@ PINS 1 ; + LAYER metal6 ( -140 -140 ) ( 140 140 ) + FIXED ( 100000 199860 ) N ; END PINS -NETS 84 ; +NETS 39 ; - CELL/clk2 ( clkbuf_0_CELL\/clk2 A ) ( CELL/CKGATE Z ) + USE CLOCK ; - - clk ( PIN clk ) ( clkbuf_0_clk A ) + USE CLOCK ; + - clk ( PIN clk ) ( clkbuf_regs_0_clk A ) ( clkbuf_0_clk A ) + USE CLOCK ; + - clk_regs ( clkbuf_0_clk_regs A ) ( clkbuf_regs_0_clk Z ) + USE CLOCK ; - clknet_0_CELL\/clk2 ( clkbuf_4_15__f_CELL\/clk2 A ) ( clkbuf_4_14__f_CELL\/clk2 A ) ( clkbuf_4_13__f_CELL\/clk2 A ) ( clkbuf_4_12__f_CELL\/clk2 A ) ( clkbuf_4_11__f_CELL\/clk2 A ) ( clkbuf_4_10__f_CELL\/clk2 A ) ( clkbuf_4_9__f_CELL\/clk2 A ) ( clkbuf_4_8__f_CELL\/clk2 A ) ( clkbuf_4_7__f_CELL\/clk2 A ) ( clkbuf_4_6__f_CELL\/clk2 A ) ( clkbuf_4_5__f_CELL\/clk2 A ) ( clkbuf_4_4__f_CELL\/clk2 A ) ( clkbuf_4_3__f_CELL\/clk2 A ) ( clkbuf_4_2__f_CELL\/clk2 A ) ( clkbuf_4_1__f_CELL\/clk2 A ) ( clkbuf_4_0__f_CELL\/clk2 A ) ( clkbuf_0_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_0_clk ( clkbuf_4_15__f_clk A ) ( clkbuf_4_14__f_clk A ) ( clkbuf_4_13__f_clk A ) ( clkbuf_4_12__f_clk A ) ( clkbuf_4_11__f_clk A ) ( clkbuf_4_10__f_clk A ) ( clkbuf_4_9__f_clk A ) - ( clkbuf_4_8__f_clk A ) ( clkbuf_4_7__f_clk A ) ( clkbuf_4_6__f_clk A ) ( clkbuf_4_5__f_clk A ) ( clkbuf_4_4__f_clk A ) ( clkbuf_4_3__f_clk A ) ( clkbuf_4_2__f_clk A ) ( clkbuf_4_1__f_clk A ) - ( clkbuf_4_0__f_clk A ) ( clkbuf_0_clk Z ) + USE CLOCK ; + - clknet_0_clk ( clkbuf_0_clk Z ) ( clkbuf_1_0__f_clk A ) + USE CLOCK ; + - clknet_0_clk_regs ( clkbuf_4_15__f_clk_regs A ) ( clkbuf_4_14__f_clk_regs A ) ( clkbuf_4_13__f_clk_regs A ) ( clkbuf_4_12__f_clk_regs A ) ( clkbuf_4_11__f_clk_regs A ) ( clkbuf_4_10__f_clk_regs A ) ( clkbuf_4_9__f_clk_regs A ) + ( clkbuf_4_8__f_clk_regs A ) ( clkbuf_4_7__f_clk_regs A ) ( clkbuf_4_6__f_clk_regs A ) ( clkbuf_4_5__f_clk_regs A ) ( clkbuf_4_4__f_clk_regs A ) ( clkbuf_4_3__f_clk_regs A ) ( clkbuf_4_2__f_clk_regs A ) ( clkbuf_4_1__f_clk_regs A ) + ( clkbuf_4_0__f_clk_regs A ) ( clkbuf_0_clk_regs Z ) + USE CLOCK ; + - clknet_1_0__leaf_clk ( CELL/CKGATE A ) ( clkbuf_1_0__f_clk Z ) + USE CLOCK ; - clknet_4_0__leaf_CELL\/clk2 ( ff162 CK ) ( ff163 CK ) ( ff164 CK ) ( ff165 CK ) ( ff180 CK ) ( ff181 CK ) ( ff182 CK ) ( ff183 CK ) ( ff184 CK ) ( clkbuf_4_0__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_0__leaf_clk ( clkbuf_level_0_1_10_clk A ) ( clkbuf_4_0__f_clk Z ) + USE CLOCK ; + - clknet_4_0__leaf_clk_regs ( ff0 CK ) ( ff1 CK ) ( ff2 CK ) ( ff3 CK ) ( ff18 CK ) ( ff19 CK ) ( ff20 CK ) + ( ff21 CK ) ( ff39 CK ) ( ff40 CK ) ( clkbuf_4_0__f_clk_regs Z ) + USE CLOCK ; - clknet_4_10__leaf_CELL\/clk2 ( ff158 CK ) ( ff159 CK ) ( ff160 CK ) ( ff176 CK ) ( ff177 CK ) ( ff178 CK ) ( ff194 CK ) ( clkbuf_4_10__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_10__leaf_clk ( clkbuf_level_0_1_1130_clk A ) ( clkbuf_4_10__f_clk Z ) + USE CLOCK ; + - clknet_4_10__leaf_clk_regs ( ff14 CK ) ( ff15 CK ) ( ff16 CK ) ( ff32 CK ) ( ff33 CK ) ( ff34 CK ) ( ff50 CK ) + ( clkbuf_4_10__f_clk_regs Z ) + USE CLOCK ; - clknet_4_11__leaf_CELL\/clk2 ( ff161 CK ) ( ff179 CK ) ( ff195 CK ) ( ff196 CK ) ( ff197 CK ) ( ff212 CK ) ( ff213 CK ) ( ff214 CK ) ( ff215 CK ) ( clkbuf_4_11__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_11__leaf_clk ( clkbuf_level_0_1_1233_clk A ) ( clkbuf_4_11__f_clk Z ) + USE CLOCK ; + - clknet_4_11__leaf_clk_regs ( ff17 CK ) ( ff35 CK ) ( ff51 CK ) ( ff52 CK ) ( ff53 CK ) ( ff68 CK ) ( ff69 CK ) + ( ff70 CK ) ( ff71 CK ) ( clkbuf_4_11__f_clk_regs Z ) + USE CLOCK ; - clknet_4_12__leaf_CELL\/clk2 ( ff225 CK ) ( ff226 CK ) ( ff227 CK ) ( ff228 CK ) ( ff229 CK ) ( ff243 CK ) ( ff244 CK ) ( ff245 CK ) ( ff246 CK ) ( ff247 CK ) ( clkbuf_4_12__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_12__leaf_clk ( clkbuf_level_0_1_1336_clk A ) ( clkbuf_4_12__f_clk Z ) + USE CLOCK ; + - clknet_4_12__leaf_clk_regs ( ff81 CK ) ( ff82 CK ) ( ff83 CK ) ( ff84 CK ) ( ff85 CK ) ( ff99 CK ) ( ff100 CK ) + ( ff101 CK ) ( ff103 CK ) ( clkbuf_4_12__f_clk_regs Z ) + USE CLOCK ; - clknet_4_13__leaf_CELL\/clk2 ( ff261 CK ) ( ff262 CK ) ( ff263 CK ) ( ff264 CK ) ( ff265 CK ) ( ff279 CK ) ( ff280 CK ) ( ff281 CK ) ( ff282 CK ) ( ff283 CK ) ( ff297 CK ) ( ff298 CK ) ( ff299 CK ) ( clkbuf_4_13__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_13__leaf_clk ( clkbuf_level_0_1_1439_clk A ) ( clkbuf_4_13__f_clk Z ) + USE CLOCK ; + - clknet_4_13__leaf_clk_regs ( ff102 CK ) ( ff117 CK ) ( ff118 CK ) ( ff119 CK ) ( ff120 CK ) ( ff121 CK ) ( ff135 CK ) + ( ff136 CK ) ( ff137 CK ) ( ff138 CK ) ( ff139 CK ) ( clkbuf_4_13__f_clk_regs Z ) + USE CLOCK ; - clknet_4_14__leaf_CELL\/clk2 ( ff230 CK ) ( ff231 CK ) ( ff232 CK ) ( ff233 CK ) ( ff248 CK ) ( ff250 CK ) ( ff251 CK ) ( clkbuf_4_14__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_14__leaf_clk ( clkbuf_level_0_1_1542_clk A ) ( clkbuf_4_14__f_clk Z ) + USE CLOCK ; + - clknet_4_14__leaf_clk_regs ( ff86 CK ) ( ff87 CK ) ( ff88 CK ) ( ff89 CK ) ( ff104 CK ) ( ff106 CK ) ( ff107 CK ) + ( clkbuf_4_14__f_clk_regs Z ) + USE CLOCK ; - clknet_4_15__leaf_CELL\/clk2 ( ff249 CK ) ( ff266 CK ) ( ff267 CK ) ( ff268 CK ) ( ff269 CK ) ( ff284 CK ) ( ff285 CK ) ( ff286 CK ) ( ff287 CK ) ( clkbuf_4_15__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_15__leaf_clk ( clkbuf_level_0_1_1645_clk A ) ( clkbuf_4_15__f_clk Z ) + USE CLOCK ; + - clknet_4_15__leaf_clk_regs ( ff105 CK ) ( ff122 CK ) ( ff123 CK ) ( ff124 CK ) ( ff125 CK ) ( ff140 CK ) ( ff141 CK ) + ( ff142 CK ) ( ff143 CK ) ( clkbuf_4_15__f_clk_regs Z ) + USE CLOCK ; - clknet_4_1__leaf_CELL\/clk2 ( ff198 CK ) ( ff199 CK ) ( ff200 CK ) ( ff201 CK ) ( ff202 CK ) ( ff216 CK ) ( clkbuf_4_1__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_1__leaf_clk ( clkbuf_level_0_1_23_clk A ) ( clkbuf_4_1__f_clk Z ) + USE CLOCK ; + - clknet_4_1__leaf_clk_regs ( ff36 CK ) ( ff37 CK ) ( ff38 CK ) ( ff54 CK ) ( ff55 CK ) ( ff56 CK ) ( ff57 CK ) + ( clkbuf_4_1__f_clk_regs Z ) + USE CLOCK ; - clknet_4_2__leaf_CELL\/clk2 ( ff150 CK ) ( ff151 CK ) ( ff152 CK ) ( ff166 CK ) ( ff167 CK ) ( ff168 CK ) ( ff169 CK ) ( ff170 CK ) ( ff185 CK ) ( ff186 CK ) ( ff187 CK ) ( ff188 CK ) ( clkbuf_4_2__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_2__leaf_clk ( clkbuf_level_0_1_36_clk A ) ( clkbuf_4_2__f_clk Z ) + USE CLOCK ; + - clknet_4_2__leaf_clk_regs ( ff4 CK ) ( ff5 CK ) ( ff6 CK ) ( ff7 CK ) ( ff8 CK ) ( ff22 CK ) ( ff23 CK ) + ( ff24 CK ) ( ff25 CK ) ( ff26 CK ) ( ff41 CK ) ( ff42 CK ) ( ff43 CK ) ( ff44 CK ) ( clkbuf_4_2__f_clk_regs Z ) + USE CLOCK ; - clknet_4_3__leaf_CELL\/clk2 ( ff203 CK ) ( ff204 CK ) ( ff205 CK ) ( ff206 CK ) ( ff220 CK ) ( ff221 CK ) ( ff222 CK ) ( ff223 CK ) ( ff224 CK ) ( clkbuf_4_3__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_3__leaf_clk ( clkbuf_level_0_1_49_clk A ) ( clkbuf_4_3__f_clk Z ) + USE CLOCK ; + - clknet_4_3__leaf_clk_regs ( ff58 CK ) ( ff59 CK ) ( ff60 CK ) ( ff61 CK ) ( ff62 CK ) ( ff76 CK ) ( ff77 CK ) + ( ff78 CK ) ( ff79 CK ) ( ff80 CK ) ( clkbuf_4_3__f_clk_regs Z ) + USE CLOCK ; - clknet_4_4__leaf_CELL\/clk2 ( ff217 CK ) ( ff218 CK ) ( ff219 CK ) ( ff234 CK ) ( ff235 CK ) ( ff236 CK ) ( ff237 CK ) ( ff254 CK ) ( clkbuf_4_4__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_4__leaf_clk ( clkbuf_level_0_1_512_clk A ) ( clkbuf_4_4__f_clk Z ) + USE CLOCK ; + - clknet_4_4__leaf_clk_regs ( ff72 CK ) ( ff73 CK ) ( ff74 CK ) ( ff75 CK ) ( ff90 CK ) ( ff91 CK ) ( ff92 CK ) + ( ff93 CK ) ( clkbuf_4_4__f_clk_regs Z ) + USE CLOCK ; - clknet_4_5__leaf_CELL\/clk2 ( ff252 CK ) ( ff253 CK ) ( ff255 CK ) ( ff270 CK ) ( ff271 CK ) ( ff272 CK ) ( ff273 CK ) ( ff288 CK ) ( ff289 CK ) ( ff290 CK ) ( ff291 CK ) ( clkbuf_4_5__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_5__leaf_clk ( clkbuf_level_0_1_615_clk A ) ( clkbuf_4_5__f_clk Z ) + USE CLOCK ; + - clknet_4_5__leaf_clk_regs ( ff108 CK ) ( ff109 CK ) ( ff110 CK ) ( ff111 CK ) ( ff126 CK ) ( ff127 CK ) ( ff128 CK ) + ( ff129 CK ) ( ff144 CK ) ( ff145 CK ) ( ff146 CK ) ( ff147 CK ) ( clkbuf_4_5__f_clk_regs Z ) + USE CLOCK ; - clknet_4_6__leaf_CELL\/clk2 ( ff238 CK ) ( ff239 CK ) ( ff240 CK ) ( ff241 CK ) ( ff242 CK ) ( ff257 CK ) ( ff259 CK ) ( ff260 CK ) ( clkbuf_4_6__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_6__leaf_clk ( clkbuf_level_0_1_718_clk A ) ( clkbuf_4_6__f_clk Z ) + USE CLOCK ; + - clknet_4_6__leaf_clk_regs ( ff94 CK ) ( ff95 CK ) ( ff96 CK ) ( ff97 CK ) ( ff98 CK ) ( ff113 CK ) ( ff114 CK ) + ( clkbuf_4_6__f_clk_regs Z ) + USE CLOCK ; - clknet_4_7__leaf_CELL\/clk2 ( ff256 CK ) ( ff258 CK ) ( ff274 CK ) ( ff275 CK ) ( ff276 CK ) ( ff277 CK ) ( ff278 CK ) ( ff292 CK ) ( ff293 CK ) ( ff294 CK ) ( ff295 CK ) ( ff296 CK ) ( clkbuf_4_7__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_7__leaf_clk ( CELL/CKGATE A ) ( clkbuf_level_0_1_821_clk A ) ( clkbuf_4_7__f_clk Z ) + USE CLOCK ; + - clknet_4_7__leaf_clk_regs ( ff112 CK ) ( ff115 CK ) ( ff116 CK ) ( ff130 CK ) ( ff131 CK ) ( ff132 CK ) ( ff133 CK ) + ( ff134 CK ) ( ff148 CK ) ( ff149 CK ) ( clkbuf_4_7__f_clk_regs Z ) + USE CLOCK ; - clknet_4_8__leaf_CELL\/clk2 ( ff153 CK ) ( ff154 CK ) ( ff155 CK ) ( ff156 CK ) ( ff157 CK ) ( ff171 CK ) ( ff172 CK ) ( ff173 CK ) ( ff174 CK ) ( ff175 CK ) ( ff191 CK ) ( ff193 CK ) ( clkbuf_4_8__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_8__leaf_clk ( clkbuf_level_0_1_924_clk A ) ( clkbuf_4_8__f_clk Z ) + USE CLOCK ; + - clknet_4_8__leaf_clk_regs ( ff9 CK ) ( ff10 CK ) ( ff11 CK ) ( ff12 CK ) ( ff13 CK ) ( ff27 CK ) ( ff28 CK ) + ( ff29 CK ) ( ff30 CK ) ( ff31 CK ) ( ff47 CK ) ( ff49 CK ) ( clkbuf_4_8__f_clk_regs Z ) + USE CLOCK ; - clknet_4_9__leaf_CELL\/clk2 ( ff189 CK ) ( ff190 CK ) ( ff192 CK ) ( ff207 CK ) ( ff208 CK ) ( ff209 CK ) ( ff210 CK ) ( ff211 CK ) ( clkbuf_4_9__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_9__leaf_clk ( clkbuf_level_0_1_1027_clk A ) ( clkbuf_4_9__f_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1027_clk ( clkbuf_level_1_1_1028_clk A ) ( clkbuf_level_0_1_1027_clk Z ) + USE CLOCK ; - - clknet_level_0_1_10_clk ( clkbuf_level_1_1_11_clk A ) ( clkbuf_level_0_1_10_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1130_clk ( clkbuf_level_1_1_1131_clk A ) ( clkbuf_level_0_1_1130_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1233_clk ( clkbuf_level_1_1_1234_clk A ) ( clkbuf_level_0_1_1233_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1336_clk ( clkbuf_level_1_1_1337_clk A ) ( clkbuf_level_0_1_1336_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1439_clk ( clkbuf_level_1_1_1440_clk A ) ( clkbuf_level_0_1_1439_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1542_clk ( clkbuf_level_1_1_1543_clk A ) ( clkbuf_level_0_1_1542_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1645_clk ( clkbuf_level_1_1_1646_clk A ) ( clkbuf_level_0_1_1645_clk Z ) + USE CLOCK ; - - clknet_level_0_1_23_clk ( clkbuf_level_1_1_24_clk A ) ( clkbuf_level_0_1_23_clk Z ) + USE CLOCK ; - - clknet_level_0_1_36_clk ( clkbuf_level_1_1_37_clk A ) ( clkbuf_level_0_1_36_clk Z ) + USE CLOCK ; - - clknet_level_0_1_49_clk ( clkbuf_level_1_1_410_clk A ) ( clkbuf_level_0_1_49_clk Z ) + USE CLOCK ; - - clknet_level_0_1_512_clk ( clkbuf_level_1_1_513_clk A ) ( clkbuf_level_0_1_512_clk Z ) + USE CLOCK ; - - clknet_level_0_1_615_clk ( clkbuf_level_1_1_616_clk A ) ( clkbuf_level_0_1_615_clk Z ) + USE CLOCK ; - - clknet_level_0_1_718_clk ( clkbuf_level_1_1_719_clk A ) ( clkbuf_level_0_1_718_clk Z ) + USE CLOCK ; - - clknet_level_0_1_821_clk ( clkbuf_level_1_1_822_clk A ) ( clkbuf_level_0_1_821_clk Z ) + USE CLOCK ; - - clknet_level_0_1_924_clk ( clkbuf_level_1_1_925_clk A ) ( clkbuf_level_0_1_924_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1028_clk ( clkbuf_level_2_1_1029_clk A ) ( clkbuf_level_1_1_1028_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1131_clk ( clkbuf_level_2_1_1132_clk A ) ( clkbuf_level_1_1_1131_clk Z ) + USE CLOCK ; - - clknet_level_1_1_11_clk ( clkbuf_level_2_1_12_clk A ) ( clkbuf_level_1_1_11_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1234_clk ( clkbuf_level_2_1_1235_clk A ) ( clkbuf_level_1_1_1234_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1337_clk ( clkbuf_level_2_1_1338_clk A ) ( clkbuf_level_1_1_1337_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1440_clk ( clkbuf_level_2_1_1441_clk A ) ( clkbuf_level_1_1_1440_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1543_clk ( clkbuf_level_2_1_1544_clk A ) ( clkbuf_level_1_1_1543_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1646_clk ( clkbuf_level_2_1_1647_clk A ) ( clkbuf_level_1_1_1646_clk Z ) + USE CLOCK ; - - clknet_level_1_1_24_clk ( clkbuf_level_2_1_25_clk A ) ( clkbuf_level_1_1_24_clk Z ) + USE CLOCK ; - - clknet_level_1_1_37_clk ( clkbuf_level_2_1_38_clk A ) ( clkbuf_level_1_1_37_clk Z ) + USE CLOCK ; - - clknet_level_1_1_410_clk ( clkbuf_level_2_1_411_clk A ) ( clkbuf_level_1_1_410_clk Z ) + USE CLOCK ; - - clknet_level_1_1_513_clk ( clkbuf_level_2_1_514_clk A ) ( clkbuf_level_1_1_513_clk Z ) + USE CLOCK ; - - clknet_level_1_1_616_clk ( clkbuf_level_2_1_617_clk A ) ( clkbuf_level_1_1_616_clk Z ) + USE CLOCK ; - - clknet_level_1_1_719_clk ( clkbuf_level_2_1_720_clk A ) ( clkbuf_level_1_1_719_clk Z ) + USE CLOCK ; - - clknet_level_1_1_822_clk ( clkbuf_level_2_1_823_clk A ) ( clkbuf_level_1_1_822_clk Z ) + USE CLOCK ; - - clknet_level_1_1_925_clk ( clkbuf_level_2_1_926_clk A ) ( clkbuf_level_1_1_925_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1029_clk ( ff45 CK ) ( ff46 CK ) ( ff48 CK ) ( ff63 CK ) ( ff64 CK ) ( ff65 CK ) ( ff66 CK ) - ( ff67 CK ) ( clkbuf_level_2_1_1029_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1132_clk ( ff14 CK ) ( ff15 CK ) ( ff16 CK ) ( ff32 CK ) ( ff33 CK ) ( ff34 CK ) ( ff50 CK ) - ( clkbuf_level_2_1_1132_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1235_clk ( ff17 CK ) ( ff35 CK ) ( ff51 CK ) ( ff52 CK ) ( ff53 CK ) ( ff68 CK ) ( ff69 CK ) - ( ff70 CK ) ( ff71 CK ) ( clkbuf_level_2_1_1235_clk Z ) + USE CLOCK ; - - clknet_level_2_1_12_clk ( ff0 CK ) ( ff2 CK ) ( ff3 CK ) ( ff20 CK ) ( ff21 CK ) ( ff39 CK ) ( ff57 CK ) - ( clkbuf_level_2_1_12_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1338_clk ( ff81 CK ) ( ff82 CK ) ( ff83 CK ) ( ff84 CK ) ( ff85 CK ) ( ff99 CK ) ( ff100 CK ) - ( ff101 CK ) ( ff103 CK ) ( clkbuf_level_2_1_1338_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1441_clk ( ff102 CK ) ( ff117 CK ) ( ff118 CK ) ( ff119 CK ) ( ff120 CK ) ( ff121 CK ) ( ff135 CK ) - ( ff136 CK ) ( ff137 CK ) ( ff138 CK ) ( ff139 CK ) ( clkbuf_level_2_1_1441_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1544_clk ( ff86 CK ) ( ff87 CK ) ( ff88 CK ) ( ff89 CK ) ( ff104 CK ) ( ff106 CK ) ( ff107 CK ) - ( clkbuf_level_2_1_1544_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1647_clk ( ff105 CK ) ( ff122 CK ) ( ff123 CK ) ( ff124 CK ) ( ff125 CK ) ( ff140 CK ) ( ff141 CK ) - ( ff142 CK ) ( ff143 CK ) ( clkbuf_level_2_1_1647_clk Z ) + USE CLOCK ; - - clknet_level_2_1_25_clk ( ff1 CK ) ( ff18 CK ) ( ff19 CK ) ( ff36 CK ) ( ff37 CK ) ( ff38 CK ) ( ff54 CK ) - ( ff55 CK ) ( ff56 CK ) ( clkbuf_level_2_1_25_clk Z ) + USE CLOCK ; - - clknet_level_2_1_38_clk ( ff4 CK ) ( ff5 CK ) ( ff6 CK ) ( ff7 CK ) ( ff8 CK ) ( ff22 CK ) ( ff23 CK ) - ( ff24 CK ) ( ff25 CK ) ( ff26 CK ) ( ff40 CK ) ( ff42 CK ) ( clkbuf_level_2_1_38_clk Z ) + USE CLOCK ; - - clknet_level_2_1_411_clk ( ff41 CK ) ( ff43 CK ) ( ff44 CK ) ( ff58 CK ) ( ff59 CK ) ( ff60 CK ) ( ff61 CK ) - ( ff62 CK ) ( clkbuf_level_2_1_411_clk Z ) + USE CLOCK ; - - clknet_level_2_1_514_clk ( ff72 CK ) ( ff73 CK ) ( ff74 CK ) ( ff75 CK ) ( ff90 CK ) ( ff91 CK ) ( ff92 CK ) - ( ff93 CK ) ( clkbuf_level_2_1_514_clk Z ) + USE CLOCK ; - - clknet_level_2_1_617_clk ( ff108 CK ) ( ff109 CK ) ( ff110 CK ) ( ff111 CK ) ( ff126 CK ) ( ff127 CK ) ( ff128 CK ) - ( ff129 CK ) ( ff144 CK ) ( ff145 CK ) ( ff146 CK ) ( ff147 CK ) ( clkbuf_level_2_1_617_clk Z ) + USE CLOCK ; - - clknet_level_2_1_720_clk ( ff76 CK ) ( ff77 CK ) ( ff78 CK ) ( ff79 CK ) ( ff80 CK ) ( ff94 CK ) ( ff95 CK ) - ( ff96 CK ) ( ff97 CK ) ( ff98 CK ) ( clkbuf_level_2_1_720_clk Z ) + USE CLOCK ; - - clknet_level_2_1_823_clk ( ff112 CK ) ( ff113 CK ) ( ff114 CK ) ( ff115 CK ) ( ff116 CK ) ( ff130 CK ) ( ff131 CK ) - ( ff132 CK ) ( ff133 CK ) ( ff134 CK ) ( ff148 CK ) ( ff149 CK ) ( clkbuf_level_2_1_823_clk Z ) + USE CLOCK ; - - clknet_level_2_1_926_clk ( ff9 CK ) ( ff10 CK ) ( ff11 CK ) ( ff12 CK ) ( ff13 CK ) ( ff27 CK ) ( ff28 CK ) - ( ff29 CK ) ( ff30 CK ) ( ff31 CK ) ( ff47 CK ) ( ff49 CK ) ( clkbuf_level_2_1_926_clk Z ) + USE CLOCK ; + - clknet_4_9__leaf_clk_regs ( ff45 CK ) ( ff46 CK ) ( ff48 CK ) ( ff63 CK ) ( ff64 CK ) ( ff65 CK ) ( ff66 CK ) + ( ff67 CK ) ( clkbuf_4_9__f_clk_regs Z ) + USE CLOCK ; END NETS END DESIGN diff --git a/src/cts/test/balance_levels.ok b/src/cts/test/balance_levels.ok index 7fc24514d43..5e134a7f6f7 100644 --- a/src/cts/test/balance_levels.ok +++ b/src/cts/test/balance_levels.ok @@ -9,14 +9,34 @@ CLKBUF_X3 [INFO CTS-0049] Characterization buffer is CLKBUF_X3. [INFO CTS-0007] Net "clk" found for clock "clk". -[INFO CTS-0010] Clock net "clk" has 151 sinks. +[INFO CTS-0011] Clock net "clk" for macros has 1 sinks. +[INFO CTS-0011] Clock net "clk_regs" for registers has 150 sinks. [INFO CTS-0010] Clock net "CELL/clk2" has 150 sinks. -[INFO CTS-0008] TritonCTS found 2 clock nets. +[INFO CTS-0008] TritonCTS found 3 clock nets. [INFO CTS-0097] Characterization used 1 buffer(s) types. [INFO CTS-0200] 0 placement blockages have been identified. [INFO CTS-0201] 0 placed hard macros will be treated like blockages. [INFO CTS-0027] Generating H-Tree topology for net clk. -[INFO CTS-0028] Total number of sinks: 151. +[INFO CTS-0028] Total number of sinks: 1. +[INFO CTS-0029] Sinks will be clustered in groups of up to 5 and with maximum cluster diameter of 60.0 um. +[INFO CTS-0030] Number of static layers: 1. +[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). +[INFO CTS-0021] Distance between buffers: 7 units (100 um). +[INFO CTS-0023] Original sink region: [(100250, 101225), (100250, 101225)]. +[INFO CTS-0024] Normalized sink region: [(7.16071, 7.23036), (7.16071, 7.23036)]. +[INFO CTS-0025] Width: 0.0000. +[INFO CTS-0026] Height: 0.0000. + Level 1 + Direction: Vertical + Sinks per sub-region: 1 + Sub-region size: 0.0000 X 0.0000 +[INFO CTS-0034] Segment length (rounded): 1. +[INFO CTS-0032] Stop criterion found. Max number of sinks is 15. +[INFO CTS-0035] Number of sinks covered: 1. +[INFO CTS-0200] 0 placement blockages have been identified. +[INFO CTS-0201] 0 placed hard macros will be treated like blockages. +[INFO CTS-0027] Generating H-Tree topology for net clk_regs. +[INFO CTS-0028] Total number of sinks: 150. [INFO CTS-0029] Sinks will be clustered in groups of up to 5 and with maximum cluster diameter of 60.0 um. [INFO CTS-0030] Number of static layers: 1. [INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). @@ -27,7 +47,7 @@ [INFO CTS-0026] Height: 6.3491. Level 1 Direction: Horizontal - Sinks per sub-region: 76 + Sinks per sub-region: 75 Sub-region size: 6.7460 X 6.3491 [INFO CTS-0034] Segment length (rounded): 4. Level 2 @@ -46,7 +66,7 @@ Sub-region size: 3.3730 X 1.5873 [INFO CTS-0034] Segment length (rounded): 1. [INFO CTS-0032] Stop criterion found. Max number of sinks is 15. -[INFO CTS-0035] Number of sinks covered: 151. +[INFO CTS-0035] Number of sinks covered: 150. [INFO CTS-0200] 0 placement blockages have been identified. [INFO CTS-0201] 0 placed hard macros will be treated like blockages. [INFO CTS-0027] Generating H-Tree topology for net CELL\/clk2. @@ -81,13 +101,18 @@ [INFO CTS-0034] Segment length (rounded): 1. [INFO CTS-0032] Stop criterion found. Max number of sinks is 15. [INFO CTS-0035] Number of sinks covered: 150. -[INFO CTS-0093] Fixing tree levels for max depth 5 -Fixing from level 2 (parent=0 + current=2) to max 5 for driver clk -[INFO CTS-0018] Created 65 clock buffers. +[INFO CTS-0018] Created 3 clock buffers. +[INFO CTS-0012] Minimum number of buffers in the clock path: 2. +[INFO CTS-0013] Maximum number of buffers in the clock path: 2. +[INFO CTS-0014] 1 clock nets were removed/fixed. +[INFO CTS-0015] Created 2 clock nets. +[INFO CTS-0016] Fanout distribution for the current clock = 0:1, 1:1.. +[INFO CTS-0017] Max level of the clock tree: 1. +[INFO CTS-0018] Created 17 clock buffers. [INFO CTS-0012] Minimum number of buffers in the clock path: 2. -[INFO CTS-0013] Maximum number of buffers in the clock path: 5. -[INFO CTS-0015] Created 65 clock nets. -[INFO CTS-0016] Fanout distribution for the current clock = 2:1, 7:3, 8:3, 9:4, 10:1, 11:1, 12:4.. +[INFO CTS-0013] Maximum number of buffers in the clock path: 2. +[INFO CTS-0015] Created 17 clock nets. +[INFO CTS-0016] Fanout distribution for the current clock = 7:4, 8:2, 9:3, 10:3, 11:1, 12:2, 14:1.. [INFO CTS-0017] Max level of the clock tree: 4. [INFO CTS-0018] Created 17 clock buffers. [INFO CTS-0012] Minimum number of buffers in the clock path: 2. @@ -95,11 +120,13 @@ Fixing from level 2 (parent=0 + current=2) to max 5 for driver clk [INFO CTS-0015] Created 17 clock nets. [INFO CTS-0016] Fanout distribution for the current clock = 6:1, 7:2, 8:3, 9:4, 10:1, 11:1, 12:3, 13:1.. [INFO CTS-0017] Max level of the clock tree: 4. -[INFO CTS-0098] Clock net "clk" -[INFO CTS-0099] Sinks 151 +[INFO CTS-0124] Clock net "clk" +[INFO CTS-0125] Sinks 1 +[INFO CTS-0098] Clock net "clk_regs" +[INFO CTS-0099] Sinks 150 [INFO CTS-0100] Leaf buffers 0 -[INFO CTS-0101] Average sink wire length 125.08 um -[INFO CTS-0102] Path depth 2 - 5 +[INFO CTS-0101] Average sink wire length 48.98 um +[INFO CTS-0102] Path depth 2 - 2 [INFO CTS-0098] Clock net "CELL\/clk2" [INFO CTS-0099] Sinks 150 [INFO CTS-0100] Leaf buffers 0 diff --git a/src/cts/test/balance_levels.py b/src/cts/test/balance_levels.py index c285c0505f2..0e1cbca069c 100644 --- a/src/cts/test/balance_levels.py +++ b/src/cts/test/balance_levels.py @@ -24,7 +24,8 @@ sink_clustering_max_diameter=60.0, balance_levels=True, num_static_layers=1, - obstruction_aware=True + obstruction_aware=True, + insertion_delay=True ) def_file = helpers.make_result_file("balance_levels.def") diff --git a/src/cts/test/cts_aux.py b/src/cts/test/cts_aux.py index 2b2fd7b6a58..cd9e178d624 100644 --- a/src/cts/test/cts_aux.py +++ b/src/cts/test/cts_aux.py @@ -52,7 +52,8 @@ def clock_tree_synthesis(design, *, num_static_layers=None, sink_clustering_buffer=None, obstruction_aware=False, - apply_ndr=False + apply_ndr=False, + insertion_delay=True ): cts = design.getTritonCts() @@ -62,6 +63,7 @@ def clock_tree_synthesis(design, *, parms.setSinkClustering(sink_clustering_enable) parms.setBalanceLevels(balance_levels) parms.setObstructionAware(obstruction_aware) + parms.enableInsertionDelay(insertion_delay) parms.setApplyNDR(apply_ndr) if is_pos_int(sink_clustering_size): From 747e4a932a3c677a3ed1b342efb1435c97ac74b0 Mon Sep 17 00:00:00 2001 From: Cho Moon Date: Sat, 16 Mar 2024 02:45:18 +0000 Subject: [PATCH 02/23] phase 2 for enhanced clock gater handling 1) arrival computation is now recursive 2) latency adjustments are made from bottom up Signed-off-by: Cho Moon --- src/cts/include/cts/TritonCTS.h | 6 +- src/cts/src/TritonCTS.cpp | 96 ++++++++++++++++++++++--------- src/cts/test/balance_levels.defok | 4 +- 3 files changed, 75 insertions(+), 31 deletions(-) diff --git a/src/cts/include/cts/TritonCTS.h b/src/cts/include/cts/TritonCTS.h index 47ee2bc2ac1..f78d7c386c6 100644 --- a/src/cts/include/cts/TritonCTS.h +++ b/src/cts/include/cts/TritonCTS.h @@ -130,7 +130,8 @@ class TritonCTS // db functions bool masterExists(const std::string& master) const; void populateTritonCTS(); - void writeClockNetsToDb(TreeBuilder* builder, std::set& clkLeafNets); + void writeClockNetsToDb(TreeBuilder* builder, + std::set& clkLeafNets); void writeClockNDRsToDb(const std::set& clkLeafNets); void incrementNumClocks() { ++numberOfClocks_; } void clearNumClocks() { numberOfClocks_ = 0; } @@ -210,6 +211,9 @@ class TritonCTS void printClockNetwork(const Clock& clockNet) const; void balanceMacroRegisterLatencies(); void computeAveSinkArrivals(TreeBuilder* builder); + void computeSinkArrivalRecur(odb::dbITerm* iterm, + float& sumArrivals, + unsigned& numSinks); void adjustLatencies(TreeBuilder* macroBuilder, TreeBuilder* registerBuilder); void computeTopBufferDelay(TreeBuilder* builder); odb::dbInst* insertDelayBuffer(odb::dbInst* driver, diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 6dc4d5e5f70..91b7ded9148 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -1921,7 +1921,10 @@ void TritonCTS::balanceMacroRegisterLatencies() return; } - for (TreeBuilder* registerBuilder : *builders_) { + // Visit builders from bottom up such that latencies are adjusted near bottom + // trees first + for (auto iter = builders_->rbegin(); iter != builders_->rend(); ++iter) { + TreeBuilder* registerBuilder = *iter; if (registerBuilder->getTreeType() == TreeType::RegisterTree) { TreeBuilder* macroBuilder = registerBuilder->getParent(); if (macroBuilder) { @@ -1937,36 +1940,14 @@ void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder) { Clock clock = builder->getClock(); // compute average input arrival at all sinks - float arrival = 0.0; - float ins_delay = 0.0; + float sumArrivals = 0.0; + unsigned numSinks = 0; clock.forEachSink([&](const ClockInst& sink) { odb::dbITerm* iterm = sink.getDbInputPin(); - odb::dbInst* inst = iterm->getInst(); - sta::Pin* pin = network_->dbToSta(iterm); - // ignore arrival fall (no inverters in current clock tree) - arrival - += openSta_->pinArrival(pin, sta::RiseFall::rise(), sta::MinMax::max()); - // add insertion delay - ins_delay = 0.0; - sta::LibertyCell* libCell = network_->libertyCell(network_->dbToSta(inst)); - odb::dbMTerm* mterm = iterm->getMTerm(); - if (libCell && mterm) { - sta::LibertyPort* libPort - = libCell->findLibertyPort(mterm->getConstName()); - if (libPort) { - sta::RiseFallMinMax insDelays = libPort->clockTreePathDelays(); - if (insDelays.hasValue()) { - ins_delay - = (insDelays.value(sta::RiseFall::rise(), sta::MinMax::max()) - + insDelays.value(sta::RiseFall::fall(), sta::MinMax::max())) - / 2.0; - } - } - } - arrival += ins_delay; + computeSinkArrivalRecur(iterm, sumArrivals, numSinks); }); - arrival = arrival / (float) clock.getNumSinks(); - builder->setAveSinkArrival(arrival); + float aveArrival = sumArrivals / (float) numSinks; + builder->setAveSinkArrival(aveArrival); debugPrint(logger_, CTS, "insertion delay", @@ -1978,6 +1959,65 @@ void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder) builder->getAveSinkArrival()); } +void TritonCTS::computeSinkArrivalRecur(odb::dbITerm* iterm, + float& sumArrivals, + unsigned& numSinks) +{ + if (iterm) { + odb::dbInst* inst = iterm->getInst(); + if (inst) { + if (isSink(iterm)) { + // either register or macro input pin + sta::Pin* pin = network_->dbToSta(iterm); + if (pin) { + // ignore arrival fall (no inverters in current clock tree) + float arrival = openSta_->pinArrival( + pin, sta::RiseFall::rise(), sta::MinMax::max()); + // add insertion delay + float insDelay = 0.0; + sta::LibertyCell* libCell + = network_->libertyCell(network_->dbToSta(inst)); + odb::dbMTerm* mterm = iterm->getMTerm(); + if (libCell && mterm) { + sta::LibertyPort* libPort + = libCell->findLibertyPort(mterm->getConstName()); + if (libPort) { + sta::RiseFallMinMax insDelays = libPort->clockTreePathDelays(); + if (insDelays.hasValue()) { + insDelay = (insDelays.value(sta::RiseFall::rise(), + sta::MinMax::max()) + + insDelays.value(sta::RiseFall::fall(), + sta::MinMax::max())) + / 2.0; + } + } + } + sumArrivals += (arrival + insDelay); + numSinks++; + } + return; + } else { + // not a sink, but a clock gater + odb::dbITerm* outTerm = inst->getFirstOutput(); + if (outTerm) { + odb::dbNet* outNet = outTerm->getNet(); + if (outNet) { + odb::dbSet iterms = outNet->getITerms(); + odb::dbSet::iterator iter; + for (iter = iterms.begin(); iter != iterms.end(); ++iter) { + odb::dbITerm* inTerm = *iter; + if (inTerm->getIoType() == odb::dbIoType::INPUT) { + computeSinkArrivalRecur(inTerm, sumArrivals, numSinks); + } + } + } + } + } + } + } + return; +} + // Balance latencies between macro tree and register tree // by adding delay buffers to one tree void TritonCTS::adjustLatencies(TreeBuilder* macroBuilder, diff --git a/src/cts/test/balance_levels.defok b/src/cts/test/balance_levels.defok index a231b0515c1..80b129a6a83 100644 --- a/src/cts/test/balance_levels.defok +++ b/src/cts/test/balance_levels.defok @@ -353,11 +353,11 @@ END PINS NETS 39 ; - CELL/clk2 ( clkbuf_0_CELL\/clk2 A ) ( CELL/CKGATE Z ) + USE CLOCK ; - clk ( PIN clk ) ( clkbuf_regs_0_clk A ) ( clkbuf_0_clk A ) + USE CLOCK ; - - clk_regs ( clkbuf_0_clk_regs A ) ( clkbuf_regs_0_clk Z ) + USE CLOCK ; + - clk_regs ( clkbuf_regs_0_clk Z ) ( clkbuf_0_clk_regs A ) + USE CLOCK ; - clknet_0_CELL\/clk2 ( clkbuf_4_15__f_CELL\/clk2 A ) ( clkbuf_4_14__f_CELL\/clk2 A ) ( clkbuf_4_13__f_CELL\/clk2 A ) ( clkbuf_4_12__f_CELL\/clk2 A ) ( clkbuf_4_11__f_CELL\/clk2 A ) ( clkbuf_4_10__f_CELL\/clk2 A ) ( clkbuf_4_9__f_CELL\/clk2 A ) ( clkbuf_4_8__f_CELL\/clk2 A ) ( clkbuf_4_7__f_CELL\/clk2 A ) ( clkbuf_4_6__f_CELL\/clk2 A ) ( clkbuf_4_5__f_CELL\/clk2 A ) ( clkbuf_4_4__f_CELL\/clk2 A ) ( clkbuf_4_3__f_CELL\/clk2 A ) ( clkbuf_4_2__f_CELL\/clk2 A ) ( clkbuf_4_1__f_CELL\/clk2 A ) ( clkbuf_4_0__f_CELL\/clk2 A ) ( clkbuf_0_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_0_clk ( clkbuf_0_clk Z ) ( clkbuf_1_0__f_clk A ) + USE CLOCK ; + - clknet_0_clk ( clkbuf_1_0__f_clk A ) ( clkbuf_0_clk Z ) + USE CLOCK ; - clknet_0_clk_regs ( clkbuf_4_15__f_clk_regs A ) ( clkbuf_4_14__f_clk_regs A ) ( clkbuf_4_13__f_clk_regs A ) ( clkbuf_4_12__f_clk_regs A ) ( clkbuf_4_11__f_clk_regs A ) ( clkbuf_4_10__f_clk_regs A ) ( clkbuf_4_9__f_clk_regs A ) ( clkbuf_4_8__f_clk_regs A ) ( clkbuf_4_7__f_clk_regs A ) ( clkbuf_4_6__f_clk_regs A ) ( clkbuf_4_5__f_clk_regs A ) ( clkbuf_4_4__f_clk_regs A ) ( clkbuf_4_3__f_clk_regs A ) ( clkbuf_4_2__f_clk_regs A ) ( clkbuf_4_1__f_clk_regs A ) ( clkbuf_4_0__f_clk_regs A ) ( clkbuf_0_clk_regs Z ) + USE CLOCK ; From 5ead700b85cf9e3439ca6619a55e37677bd671e6 Mon Sep 17 00:00:00 2001 From: arthur Date: Mon, 8 Jul 2024 17:31:32 -0300 Subject: [PATCH 03/23] use paths arrival time for insertion delay Signed-off-by: arthur --- src/cts/include/cts/TritonCTS.h | 3 +- src/cts/src/TritonCTS.cpp | 110 +++++++++++++------------------- 2 files changed, 46 insertions(+), 67 deletions(-) diff --git a/src/cts/include/cts/TritonCTS.h b/src/cts/include/cts/TritonCTS.h index 332b74accac..e7882bccdd5 100644 --- a/src/cts/include/cts/TritonCTS.h +++ b/src/cts/include/cts/TritonCTS.h @@ -216,7 +216,8 @@ class TritonCTS void balanceMacroRegisterLatencies(); float getVertexClkArrival(sta::Vertex* sink_vertex, odb::dbNet* topNet); void computeAveSinkArrivals(TreeBuilder* builder); - void computeSinkArrivalRecur(odb::dbITerm* iterm, + void computeSinkArrivalRecur(odb::dbNet* topClokcNet, + odb::dbITerm* iterm, float& sumArrivals, unsigned& numSinks); void adjustLatencies(TreeBuilder* macroBuilder, TreeBuilder* registerBuilder); diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 8b631765a4e..a931f668ade 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -55,15 +55,15 @@ #include "ord/OpenRoad.hh" #include "rsz/Resizer.hh" #include "sta/Fuzzy.hh" -#include "sta/Liberty.hh" -#include "sta/PatternMatch.hh" -#include "sta/Sdc.hh" -#include "utl/Logger.h" #include "sta/Graph.hh" #include "sta/GraphDelayCalc.hh" +#include "sta/Liberty.hh" #include "sta/PathAnalysisPt.hh" #include "sta/PathEnd.hh" #include "sta/PathExpanded.hh" +#include "sta/PatternMatch.hh" +#include "sta/Sdc.hh" +#include "utl/Logger.h" namespace cts { @@ -1192,11 +1192,6 @@ void TritonCTS::writeClockNetsToDb(TreeBuilder* builder, { Clock& clockNet = builder->getClock(); odb::dbNet* topClockNet = clockNet.getNetObj(); - logger_->report("Top clock Net: {}", topClockNet->getName()); - if(builder->getTopInputNet()) { - logger_->report("Builder Top input Net: {}", builder->getTopInputNet()->getName()); - } - disconnectAllSinksFromNet(topClockNet); @@ -1969,9 +1964,10 @@ void TritonCTS::balanceMacroRegisterLatencies() } } -float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet) { +float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet) +{ sta::VertexPathIterator path_iter(sinVertex, openSta_); - /*float clkPathArrival = 0.0;*/ + float clkPathArrival = 0.0; int paths_accepted = 0; while (path_iter.hasNext()) { sta::PathVertex* path = path_iter.next(); @@ -1983,15 +1979,17 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet) sta::PathExpanded expand(path, openSta_); const sta::Clock* clock = path->clock(openSta_); - if(clock) { - sta::PathRef* start = expand.startPath(); - sta::PathRef* end = expand.endPath(); + if (clock) { + const sta::PathRef* start = expand.startPath(); + + odb::dbNet* path_start_net; if (start->clkEdge(openSta_)->transition() != sta::RiseFall::rise()) { // only populate with rising edges continue; } - if (start->dcalcAnalysisPt(openSta_)->delayMinMax() != sta::MinMax::max()) { + if (start->dcalcAnalysisPt(openSta_)->delayMinMax() + != sta::MinMax::max()) { // only populate with max delay continue; } @@ -2000,47 +1998,26 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet) odb::dbBTerm* port; odb::dbModITerm* moditerm; odb::dbModBTerm* modbterm; - sta::Net* sta_net; network_->staToDb(start->pin(openSta_), term, port, moditerm, modbterm); - if(term) { - logger_->report("start_path iterm: {}", term->getName()); + if (term) { + path_start_net = term->getNet(); } - if(port) { - logger_->report("start_path bterm: {}", port->getName()); + if (port) { + path_start_net = port->getNet(); } - - if(moditerm) { - logger_->report("start_path moditerm: {}", moditerm->getName()); + if (path_start_net == topNet) { + clkPathArrival = path->arrival(openSta_); + paths_accepted += 1; } - - if(modbterm) { - logger_->report("start_path modbterm: {}", modbterm->getName()); - } - - sta::Term* term_sta = network_->term(start->pin(openSta_)); - if (term != nullptr) { - sta_net = network_->net(term_sta); - } else { - sta_net = network_->net(start->pin(openSta_)); - } - if(sta_net){ - logger_->report("start_path net: {}", network_->staToDb(sta_net)->getName()); - } - paths_accepted += 1; - // dont add paths that do not share a net at the root - /*if(network_) - logger_->report("start path net: {}", network_->staToDb(startNet)->getName()); - clkPathArrival = path->arrival(openSta_); - if(path->arrival(openSta_) != end->arrival(openSta_)) { - logger_->report("Difference"); - }*/ } } - logger_->report("Paths accepted: {}", paths_accepted); - /*if(paths_accepted > 1 || paths_accepted == 0) { - logger_->report("Paths accepted: {}", paths_accepted); - }*/ - return 0.0; + if (paths_accepted > 1 || paths_accepted == 0) { + logger_->error(CTS, + 1, + "Number of clock paths is not 1. Number of clock paths: {}", + paths_accepted); + } + return clkPathArrival; } void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder) @@ -2050,12 +2027,16 @@ void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder) openSta_->ensureClkNetwork(); openSta_->ensureClkArrivals(); Clock clock = builder->getClock(); + odb::dbNet* topClockNet = clock.getNetObj(); + if (builder->getTreeType() == TreeType::RegisterTree) { + topClockNet = builder->getTopInputNet(); + } // compute average input arrival at all sinks float sumArrivals = 0.0; unsigned numSinks = 0; clock.forEachSink([&](const ClockInst& sink) { odb::dbITerm* iterm = sink.getDbInputPin(); - computeSinkArrivalRecur(iterm, sumArrivals, numSinks); + computeSinkArrivalRecur(topClockNet, iterm, sumArrivals, numSinks); }); float aveArrival = sumArrivals / (float) numSinks; builder->setAveSinkArrival(aveArrival); @@ -2070,7 +2051,8 @@ void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder) builder->getAveSinkArrival()); } -void TritonCTS::computeSinkArrivalRecur(odb::dbITerm* iterm, +void TritonCTS::computeSinkArrivalRecur(odb::dbNet* topClokcNet, + odb::dbITerm* iterm, float& sumArrivals, unsigned& numSinks) { @@ -2083,20 +2065,14 @@ void TritonCTS::computeSinkArrivalRecur(odb::dbITerm* iterm, if (pin) { sta::Graph* graph = openSta_->graph(); sta::Vertex* drvr_vertex = graph->pinDrvrVertex(pin); - sta::Vertex* load_vertex = graph->pinLoadVertex(pin); - logger_->report("sink iterm name: {}", iterm->getName()); - if(drvr_vertex != load_vertex) { - logger_->report("diferentes vertices"); - getVertexClkArrival(drvr_vertex, nullptr); - getVertexClkArrival(load_vertex, nullptr); - } else { - logger_->report("iguais vertices"); - getVertexClkArrival(drvr_vertex, nullptr); - } - + float arrival = getVertexClkArrival(drvr_vertex, topClokcNet); // ignore arrival fall (no inverters in current clock tree) - float arrival = openSta_->pinArrival( + float arrival_pin = openSta_->pinArrival( pin, sta::RiseFall::rise(), sta::MinMax::max()); + if (arrival != arrival_pin) { + logger_->report("returned arrival: {}", arrival); + logger_->report("pin arrival: {}", arrival_pin); + } // add insertion delay float insDelay = 0.0; sta::LibertyCell* libCell @@ -2106,7 +2082,8 @@ void TritonCTS::computeSinkArrivalRecur(odb::dbITerm* iterm, sta::LibertyPort* libPort = libCell->findLibertyPort(mterm->getConstName()); if (libPort) { - sta::RiseFallMinMax insDelays = libPort->clockTreePathDelays(); + const sta::RiseFallMinMax insDelays + = libPort->clockTreePathDelays(); if (insDelays.hasValue()) { insDelay = (insDelays.value(sta::RiseFall::rise(), sta::MinMax::max()) @@ -2131,7 +2108,8 @@ void TritonCTS::computeSinkArrivalRecur(odb::dbITerm* iterm, for (iter = iterms.begin(); iter != iterms.end(); ++iter) { odb::dbITerm* inTerm = *iter; if (inTerm->getIoType() == odb::dbIoType::INPUT) { - computeSinkArrivalRecur(inTerm, sumArrivals, numSinks); + computeSinkArrivalRecur( + topClokcNet, inTerm, sumArrivals, numSinks); } } } From ff2804f8d990bf49a0a9d0be6f6e12276af90e7f Mon Sep 17 00:00:00 2001 From: arthur Date: Mon, 8 Jul 2024 17:32:21 -0300 Subject: [PATCH 04/23] update ok files Signed-off-by: arthur --- src/cts/test/balance_levels.defok | 207 ++++++++++++++---------------- src/cts/test/balance_levels.ok | 10 +- 2 files changed, 98 insertions(+), 119 deletions(-) diff --git a/src/cts/test/balance_levels.defok b/src/cts/test/balance_levels.defok index 6e859e33096..27fc13e0e6d 100644 --- a/src/cts/test/balance_levels.defok +++ b/src/cts/test/balance_levels.defok @@ -4,7 +4,7 @@ BUSBITCHARS "[]" ; DESIGN multi_sink ; UNITS DISTANCE MICRONS 2000 ; DIEAREA ( 0 0 ) ( 200000 200000 ) ; -COMPONENTS 338 ; +COMPONENTS 368 ; - CELL/CKGATE BUF_X1 + PLACED ( 100000 100000 ) N ; - clkbuf_0_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 103228 140117 ) N ; - clkbuf_0_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 100250 101225 ) N ; @@ -43,6 +43,36 @@ COMPONENTS 338 ; - clkbuf_4_9__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 135237 124256 ) N ; - clkbuf_4_9__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 135237 35368 ) N ; - clkbuf_regs_0_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 99481 48451 ) N ; + - clkload0 INV_X2 + SOURCE TIMING + PLACED ( 37181 26644 ) N ; + - clkload1 INV_X4 + SOURCE TIMING + PLACED ( 28978 35266 ) N ; + - clkload10 INV_X2 + SOURCE TIMING + PLACED ( 176988 31963 ) N ; + - clkload11 INV_X2 + SOURCE TIMING + PLACED ( 135454 59367 ) N ; + - clkload12 INV_X2 + SOURCE TIMING + PLACED ( 137599 71599 ) N ; + - clkload13 INV_X4 + SOURCE TIMING + PLACED ( 175738 59340 ) N ; + - clkload14 INV_X2 + SOURCE TIMING + PLACED ( 173942 71102 ) N ; + - clkload15 INV_X2 + SOURCE TIMING + PLACED ( 35318 119627 ) N ; + - clkload16 INV_X4 + SOURCE TIMING + PLACED ( 31476 129670 ) N ; + - clkload17 CLKBUF_X3 + SOURCE TIMING + PLACED ( 68717 119605 ) N ; + - clkload18 INV_X2 + SOURCE TIMING + PLACED ( 71061 131581 ) N ; + - clkload19 INV_X2 + SOURCE TIMING + PLACED ( 31714 150934 ) N ; + - clkload2 INV_X2 + SOURCE TIMING + PLACED ( 69122 41782 ) N ; + - clkload20 INV_X1 + SOURCE TIMING + PLACED ( 33478 164353 ) N ; + - clkload21 INV_X2 + SOURCE TIMING + PLACED ( 70729 156126 ) N ; + - clkload22 CLKBUF_X3 + SOURCE TIMING + PLACED ( 64318 165027 ) N ; + - clkload23 CLKBUF_X3 + SOURCE TIMING + PLACED ( 141948 115396 ) N ; + - clkload24 INV_X2 + SOURCE TIMING + PLACED ( 135237 124256 ) N ; + - clkload25 INV_X4 + SOURCE TIMING + PLACED ( 169474 113337 ) N ; + - clkload26 INV_X2 + SOURCE TIMING + PLACED ( 176988 120851 ) N ; + - clkload27 INV_X2 + SOURCE TIMING + PLACED ( 136180 148710 ) N ; + - clkload28 INV_X4 + SOURCE TIMING + PLACED ( 175261 148092 ) N ; + - clkload29 INV_X2 + SOURCE TIMING + PLACED ( 173171 159411 ) N ; + - clkload3 INV_X4 + SOURCE TIMING + PLACED ( 30369 61835 ) N ; + - clkload4 INV_X1 + SOURCE TIMING + PLACED ( 31247 76899 ) N ; + - clkload5 INV_X4 + SOURCE TIMING + PLACED ( 68700 66662 ) N ; + - clkload6 INV_X2 + SOURCE TIMING + PLACED ( 64650 75806 ) N ; + - clkload7 INV_X1 + SOURCE TIMING + PLACED ( 141948 26508 ) N ; + - clkload8 INV_X4 + SOURCE TIMING + PLACED ( 135237 35368 ) N ; + - clkload9 INV_X4 + SOURCE TIMING + PLACED ( 169474 24449 ) N ; - ff0 DFF_X1 + PLACED ( 5555 5555 ) N ; - ff1 DFF_X1 + PLACED ( 16666 5555 ) N ; - ff10 DFF_X1 + PLACED ( 116665 5555 ) N ; @@ -362,120 +392,69 @@ NETS 39 ; ( clkbuf_4_8__f_clk_regs A ) ( clkbuf_4_7__f_clk_regs A ) ( clkbuf_4_6__f_clk_regs A ) ( clkbuf_4_5__f_clk_regs A ) ( clkbuf_4_4__f_clk_regs A ) ( clkbuf_4_3__f_clk_regs A ) ( clkbuf_4_2__f_clk_regs A ) ( clkbuf_4_1__f_clk_regs A ) ( clkbuf_4_0__f_clk_regs A ) ( clkbuf_0_clk_regs Z ) + USE CLOCK ; - clknet_1_0__leaf_clk ( CELL/CKGATE A ) ( clkbuf_1_0__f_clk Z ) + USE CLOCK ; - - clknet_4_0__leaf_CELL\/clk2 ( ff162 CK ) ( ff163 CK ) ( ff164 CK ) ( ff165 CK ) ( ff180 CK ) ( ff181 CK ) ( ff182 CK ) - ( ff183 CK ) ( ff184 CK ) ( clkbuf_4_0__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_0__leaf_clk_regs ( ff0 CK ) ( ff1 CK ) ( ff2 CK ) ( ff3 CK ) ( ff18 CK ) ( ff19 CK ) ( ff20 CK ) - ( ff21 CK ) ( ff39 CK ) ( ff40 CK ) ( clkbuf_4_0__f_clk_regs Z ) + USE CLOCK ; - - clknet_4_10__leaf_CELL\/clk2 ( ff158 CK ) ( ff159 CK ) ( ff160 CK ) ( ff176 CK ) ( ff177 CK ) ( ff178 CK ) ( ff194 CK ) - ( clkbuf_4_10__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_10__leaf_clk_regs ( ff14 CK ) ( ff15 CK ) ( ff16 CK ) ( ff32 CK ) ( ff33 CK ) ( ff34 CK ) ( ff50 CK ) - ( clkbuf_4_10__f_clk_regs Z ) + USE CLOCK ; - - clknet_4_11__leaf_CELL\/clk2 ( ff161 CK ) ( ff179 CK ) ( ff195 CK ) ( ff196 CK ) ( ff197 CK ) ( ff212 CK ) ( ff213 CK ) - ( ff214 CK ) ( ff215 CK ) ( clkbuf_4_11__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_11__leaf_clk_regs ( ff17 CK ) ( ff35 CK ) ( ff51 CK ) ( ff52 CK ) ( ff53 CK ) ( ff68 CK ) ( ff69 CK ) - ( ff70 CK ) ( ff71 CK ) ( clkbuf_4_11__f_clk_regs Z ) + USE CLOCK ; - - clknet_4_12__leaf_CELL\/clk2 ( ff225 CK ) ( ff226 CK ) ( ff227 CK ) ( ff228 CK ) ( ff229 CK ) ( ff243 CK ) ( ff244 CK ) - ( ff245 CK ) ( ff246 CK ) ( ff247 CK ) ( clkbuf_4_12__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_12__leaf_clk_regs ( ff81 CK ) ( ff82 CK ) ( ff83 CK ) ( ff84 CK ) ( ff85 CK ) ( ff99 CK ) ( ff100 CK ) - ( ff101 CK ) ( ff103 CK ) ( clkbuf_4_12__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_0__leaf_CELL\/clk2 ( clkload15 A ) ( ff162 CK ) ( ff163 CK ) ( ff164 CK ) ( ff165 CK ) ( ff180 CK ) ( ff181 CK ) + ( ff182 CK ) ( ff183 CK ) ( ff184 CK ) ( clkbuf_4_0__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_0__leaf_clk_regs ( clkload0 A ) ( ff0 CK ) ( ff1 CK ) ( ff2 CK ) ( ff3 CK ) ( ff18 CK ) ( ff19 CK ) + ( ff20 CK ) ( ff21 CK ) ( ff39 CK ) ( ff40 CK ) ( clkbuf_4_0__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_10__leaf_CELL\/clk2 ( clkload25 A ) ( ff158 CK ) ( ff159 CK ) ( ff160 CK ) ( ff176 CK ) ( ff177 CK ) ( ff178 CK ) + ( ff194 CK ) ( clkbuf_4_10__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_10__leaf_clk_regs ( clkload9 A ) ( ff14 CK ) ( ff15 CK ) ( ff16 CK ) ( ff32 CK ) ( ff33 CK ) ( ff34 CK ) + ( ff50 CK ) ( clkbuf_4_10__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_11__leaf_CELL\/clk2 ( clkload26 A ) ( ff161 CK ) ( ff179 CK ) ( ff195 CK ) ( ff196 CK ) ( ff197 CK ) ( ff212 CK ) + ( ff213 CK ) ( ff214 CK ) ( ff215 CK ) ( clkbuf_4_11__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_11__leaf_clk_regs ( clkload10 A ) ( ff17 CK ) ( ff35 CK ) ( ff51 CK ) ( ff52 CK ) ( ff53 CK ) ( ff68 CK ) + ( ff69 CK ) ( ff70 CK ) ( ff71 CK ) ( clkbuf_4_11__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_12__leaf_CELL\/clk2 ( clkload27 A ) ( ff225 CK ) ( ff226 CK ) ( ff227 CK ) ( ff228 CK ) ( ff229 CK ) ( ff243 CK ) + ( ff244 CK ) ( ff245 CK ) ( ff246 CK ) ( ff247 CK ) ( clkbuf_4_12__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_12__leaf_clk_regs ( clkload11 A ) ( ff81 CK ) ( ff82 CK ) ( ff83 CK ) ( ff84 CK ) ( ff85 CK ) ( ff99 CK ) + ( ff100 CK ) ( ff101 CK ) ( ff103 CK ) ( clkbuf_4_12__f_clk_regs Z ) + USE CLOCK ; - clknet_4_13__leaf_CELL\/clk2 ( ff261 CK ) ( ff262 CK ) ( ff263 CK ) ( ff264 CK ) ( ff265 CK ) ( ff279 CK ) ( ff280 CK ) ( ff281 CK ) ( ff282 CK ) ( ff283 CK ) ( ff297 CK ) ( ff298 CK ) ( ff299 CK ) ( clkbuf_4_13__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_13__leaf_clk ( clkbuf_level_0_1_1439_clk A ) ( clkbuf_4_13__f_clk Z ) + USE CLOCK ; - - clknet_4_14__leaf_CELL\/clk2 ( ff230 CK ) ( ff231 CK ) ( ff232 CK ) ( ff233 CK ) ( ff248 CK ) ( ff250 CK ) ( ff251 CK ) - ( clkbuf_4_14__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_14__leaf_clk ( clkbuf_level_0_1_1542_clk A ) ( clkbuf_4_14__f_clk Z ) + USE CLOCK ; - - clknet_4_15__leaf_CELL\/clk2 ( ff249 CK ) ( ff266 CK ) ( ff267 CK ) ( ff268 CK ) ( ff269 CK ) ( ff284 CK ) ( ff285 CK ) - ( ff286 CK ) ( ff287 CK ) ( clkbuf_4_15__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_15__leaf_clk ( clkbuf_level_0_1_1645_clk A ) ( clkbuf_4_15__f_clk Z ) + USE CLOCK ; - - clknet_4_1__leaf_CELL\/clk2 ( ff198 CK ) ( ff199 CK ) ( ff200 CK ) ( ff201 CK ) ( ff202 CK ) ( ff216 CK ) ( clkbuf_4_1__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_1__leaf_clk ( clkbuf_level_0_1_23_clk A ) ( clkbuf_4_1__f_clk Z ) + USE CLOCK ; - - clknet_4_2__leaf_CELL\/clk2 ( ff150 CK ) ( ff151 CK ) ( ff152 CK ) ( ff166 CK ) ( ff167 CK ) ( ff168 CK ) ( ff169 CK ) - ( ff170 CK ) ( ff185 CK ) ( ff186 CK ) ( ff187 CK ) ( ff188 CK ) ( clkbuf_4_2__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_2__leaf_clk ( clkbuf_level_0_1_36_clk A ) ( clkbuf_4_2__f_clk Z ) + USE CLOCK ; - - clknet_4_3__leaf_CELL\/clk2 ( ff203 CK ) ( ff204 CK ) ( ff205 CK ) ( ff206 CK ) ( ff220 CK ) ( ff221 CK ) ( ff222 CK ) - ( ff223 CK ) ( ff224 CK ) ( clkbuf_4_3__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_3__leaf_clk ( clkbuf_level_0_1_49_clk A ) ( clkbuf_4_3__f_clk Z ) + USE CLOCK ; - - clknet_4_4__leaf_CELL\/clk2 ( ff217 CK ) ( ff218 CK ) ( ff219 CK ) ( ff234 CK ) ( ff235 CK ) ( ff236 CK ) ( ff237 CK ) - ( ff254 CK ) ( clkbuf_4_4__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_4__leaf_clk ( clkbuf_level_0_1_512_clk A ) ( clkbuf_4_4__f_clk Z ) + USE CLOCK ; - - clknet_4_5__leaf_CELL\/clk2 ( ff252 CK ) ( ff253 CK ) ( ff255 CK ) ( ff270 CK ) ( ff271 CK ) ( ff272 CK ) ( ff273 CK ) - ( ff288 CK ) ( ff289 CK ) ( ff290 CK ) ( ff291 CK ) ( clkbuf_4_5__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_5__leaf_clk ( clkbuf_level_0_1_615_clk A ) ( clkbuf_4_5__f_clk Z ) + USE CLOCK ; - - clknet_4_6__leaf_CELL\/clk2 ( ff238 CK ) ( ff239 CK ) ( ff240 CK ) ( ff241 CK ) ( ff242 CK ) ( ff257 CK ) ( ff259 CK ) - ( ff260 CK ) ( clkbuf_4_6__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_6__leaf_clk ( clkbuf_level_0_1_718_clk A ) ( clkbuf_4_6__f_clk Z ) + USE CLOCK ; - - clknet_4_7__leaf_CELL\/clk2 ( ff256 CK ) ( ff258 CK ) ( ff274 CK ) ( ff275 CK ) ( ff276 CK ) ( ff277 CK ) ( ff278 CK ) - ( ff292 CK ) ( ff293 CK ) ( ff294 CK ) ( ff295 CK ) ( ff296 CK ) ( clkbuf_4_7__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_7__leaf_clk ( CELL/CKGATE A ) ( clkbuf_level_0_1_821_clk A ) ( clkbuf_4_7__f_clk Z ) + USE CLOCK ; - - clknet_4_8__leaf_CELL\/clk2 ( ff153 CK ) ( ff154 CK ) ( ff155 CK ) ( ff156 CK ) ( ff157 CK ) ( ff171 CK ) ( ff172 CK ) - ( ff173 CK ) ( ff174 CK ) ( ff175 CK ) ( ff191 CK ) ( ff193 CK ) ( clkbuf_4_8__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_8__leaf_clk ( clkbuf_level_0_1_924_clk A ) ( clkbuf_4_8__f_clk Z ) + USE CLOCK ; - - clknet_4_9__leaf_CELL\/clk2 ( ff189 CK ) ( ff190 CK ) ( ff192 CK ) ( ff207 CK ) ( ff208 CK ) ( ff209 CK ) ( ff210 CK ) - ( ff211 CK ) ( clkbuf_4_9__f_CELL\/clk2 Z ) + USE CLOCK ; - - clknet_4_9__leaf_clk ( clkbuf_level_0_1_1027_clk A ) ( clkbuf_4_9__f_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1027_clk ( clkbuf_level_1_1_1028_clk A ) ( clkbuf_level_0_1_1027_clk Z ) + USE CLOCK ; - - clknet_level_0_1_10_clk ( clkbuf_level_1_1_11_clk A ) ( clkbuf_level_0_1_10_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1130_clk ( clkbuf_level_1_1_1131_clk A ) ( clkbuf_level_0_1_1130_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1233_clk ( clkbuf_level_1_1_1234_clk A ) ( clkbuf_level_0_1_1233_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1336_clk ( clkbuf_level_1_1_1337_clk A ) ( clkbuf_level_0_1_1336_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1439_clk ( clkbuf_level_1_1_1440_clk A ) ( clkbuf_level_0_1_1439_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1542_clk ( clkbuf_level_1_1_1543_clk A ) ( clkbuf_level_0_1_1542_clk Z ) + USE CLOCK ; - - clknet_level_0_1_1645_clk ( clkbuf_level_1_1_1646_clk A ) ( clkbuf_level_0_1_1645_clk Z ) + USE CLOCK ; - - clknet_level_0_1_23_clk ( clkbuf_level_1_1_24_clk A ) ( clkbuf_level_0_1_23_clk Z ) + USE CLOCK ; - - clknet_level_0_1_36_clk ( clkbuf_level_1_1_37_clk A ) ( clkbuf_level_0_1_36_clk Z ) + USE CLOCK ; - - clknet_level_0_1_49_clk ( clkbuf_level_1_1_410_clk A ) ( clkbuf_level_0_1_49_clk Z ) + USE CLOCK ; - - clknet_level_0_1_512_clk ( clkbuf_level_1_1_513_clk A ) ( clkbuf_level_0_1_512_clk Z ) + USE CLOCK ; - - clknet_level_0_1_615_clk ( clkbuf_level_1_1_616_clk A ) ( clkbuf_level_0_1_615_clk Z ) + USE CLOCK ; - - clknet_level_0_1_718_clk ( clkbuf_level_1_1_719_clk A ) ( clkbuf_level_0_1_718_clk Z ) + USE CLOCK ; - - clknet_level_0_1_821_clk ( clkbuf_level_1_1_822_clk A ) ( clkbuf_level_0_1_821_clk Z ) + USE CLOCK ; - - clknet_level_0_1_924_clk ( clkbuf_level_1_1_925_clk A ) ( clkbuf_level_0_1_924_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1028_clk ( clkbuf_level_2_1_1029_clk A ) ( clkbuf_level_1_1_1028_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1131_clk ( clkbuf_level_2_1_1132_clk A ) ( clkbuf_level_1_1_1131_clk Z ) + USE CLOCK ; - - clknet_level_1_1_11_clk ( clkbuf_level_2_1_12_clk A ) ( clkbuf_level_1_1_11_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1234_clk ( clkbuf_level_2_1_1235_clk A ) ( clkbuf_level_1_1_1234_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1337_clk ( clkbuf_level_2_1_1338_clk A ) ( clkbuf_level_1_1_1337_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1440_clk ( clkbuf_level_2_1_1441_clk A ) ( clkbuf_level_1_1_1440_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1543_clk ( clkbuf_level_2_1_1544_clk A ) ( clkbuf_level_1_1_1543_clk Z ) + USE CLOCK ; - - clknet_level_1_1_1646_clk ( clkbuf_level_2_1_1647_clk A ) ( clkbuf_level_1_1_1646_clk Z ) + USE CLOCK ; - - clknet_level_1_1_24_clk ( clkbuf_level_2_1_25_clk A ) ( clkbuf_level_1_1_24_clk Z ) + USE CLOCK ; - - clknet_level_1_1_37_clk ( clkbuf_level_2_1_38_clk A ) ( clkbuf_level_1_1_37_clk Z ) + USE CLOCK ; - - clknet_level_1_1_410_clk ( clkbuf_level_2_1_411_clk A ) ( clkbuf_level_1_1_410_clk Z ) + USE CLOCK ; - - clknet_level_1_1_513_clk ( clkbuf_level_2_1_514_clk A ) ( clkbuf_level_1_1_513_clk Z ) + USE CLOCK ; - - clknet_level_1_1_616_clk ( clkbuf_level_2_1_617_clk A ) ( clkbuf_level_1_1_616_clk Z ) + USE CLOCK ; - - clknet_level_1_1_719_clk ( clkbuf_level_2_1_720_clk A ) ( clkbuf_level_1_1_719_clk Z ) + USE CLOCK ; - - clknet_level_1_1_822_clk ( clkbuf_level_2_1_823_clk A ) ( clkbuf_level_1_1_822_clk Z ) + USE CLOCK ; - - clknet_level_1_1_925_clk ( clkbuf_level_2_1_926_clk A ) ( clkbuf_level_1_1_925_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1029_clk ( ff45 CK ) ( ff46 CK ) ( ff48 CK ) ( ff63 CK ) ( ff64 CK ) ( ff65 CK ) ( ff66 CK ) - ( ff67 CK ) ( clkbuf_level_2_1_1029_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1132_clk ( ff14 CK ) ( ff15 CK ) ( ff16 CK ) ( ff32 CK ) ( ff33 CK ) ( ff34 CK ) ( ff50 CK ) - ( clkbuf_level_2_1_1132_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1235_clk ( ff17 CK ) ( ff35 CK ) ( ff51 CK ) ( ff52 CK ) ( ff53 CK ) ( ff68 CK ) ( ff69 CK ) - ( ff70 CK ) ( ff71 CK ) ( clkbuf_level_2_1_1235_clk Z ) + USE CLOCK ; - - clknet_level_2_1_12_clk ( ff0 CK ) ( ff2 CK ) ( ff3 CK ) ( ff20 CK ) ( ff21 CK ) ( ff39 CK ) ( ff57 CK ) - ( clkbuf_level_2_1_12_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1338_clk ( ff81 CK ) ( ff82 CK ) ( ff83 CK ) ( ff84 CK ) ( ff85 CK ) ( ff99 CK ) ( ff100 CK ) - ( ff101 CK ) ( ff103 CK ) ( clkbuf_level_2_1_1338_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1441_clk ( ff102 CK ) ( ff117 CK ) ( ff118 CK ) ( ff119 CK ) ( ff120 CK ) ( ff121 CK ) ( ff135 CK ) - ( ff136 CK ) ( ff137 CK ) ( ff138 CK ) ( ff139 CK ) ( clkbuf_level_2_1_1441_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1544_clk ( ff86 CK ) ( ff87 CK ) ( ff88 CK ) ( ff89 CK ) ( ff104 CK ) ( ff106 CK ) ( ff107 CK ) - ( clkbuf_level_2_1_1544_clk Z ) + USE CLOCK ; - - clknet_level_2_1_1647_clk ( ff105 CK ) ( ff122 CK ) ( ff123 CK ) ( ff124 CK ) ( ff125 CK ) ( ff140 CK ) ( ff141 CK ) - ( ff142 CK ) ( ff143 CK ) ( clkbuf_level_2_1_1647_clk Z ) + USE CLOCK ; - - clknet_level_2_1_25_clk ( ff1 CK ) ( ff18 CK ) ( ff19 CK ) ( ff36 CK ) ( ff37 CK ) ( ff38 CK ) ( ff54 CK ) - ( ff55 CK ) ( ff56 CK ) ( clkbuf_level_2_1_25_clk Z ) + USE CLOCK ; - - clknet_level_2_1_38_clk ( ff4 CK ) ( ff5 CK ) ( ff6 CK ) ( ff7 CK ) ( ff8 CK ) ( ff22 CK ) ( ff23 CK ) - ( ff24 CK ) ( ff25 CK ) ( ff26 CK ) ( ff40 CK ) ( ff42 CK ) ( clkbuf_level_2_1_38_clk Z ) + USE CLOCK ; - - clknet_level_2_1_411_clk ( ff41 CK ) ( ff43 CK ) ( ff44 CK ) ( ff58 CK ) ( ff59 CK ) ( ff60 CK ) ( ff61 CK ) - ( ff62 CK ) ( clkbuf_level_2_1_411_clk Z ) + USE CLOCK ; - - clknet_level_2_1_514_clk ( ff72 CK ) ( ff73 CK ) ( ff74 CK ) ( ff75 CK ) ( ff90 CK ) ( ff91 CK ) ( ff92 CK ) - ( ff93 CK ) ( clkbuf_level_2_1_514_clk Z ) + USE CLOCK ; - - clknet_level_2_1_617_clk ( ff108 CK ) ( ff109 CK ) ( ff110 CK ) ( ff111 CK ) ( ff126 CK ) ( ff127 CK ) ( ff128 CK ) - ( ff129 CK ) ( ff144 CK ) ( ff145 CK ) ( ff146 CK ) ( ff147 CK ) ( clkbuf_level_2_1_617_clk Z ) + USE CLOCK ; - - clknet_level_2_1_720_clk ( ff76 CK ) ( ff77 CK ) ( ff78 CK ) ( ff79 CK ) ( ff80 CK ) ( ff94 CK ) ( ff95 CK ) - ( ff96 CK ) ( ff97 CK ) ( ff98 CK ) ( clkbuf_level_2_1_720_clk Z ) + USE CLOCK ; - - clknet_level_2_1_823_clk ( ff112 CK ) ( ff113 CK ) ( ff114 CK ) ( ff115 CK ) ( ff116 CK ) ( ff130 CK ) ( ff131 CK ) - ( ff132 CK ) ( ff133 CK ) ( ff134 CK ) ( ff148 CK ) ( ff149 CK ) ( clkbuf_level_2_1_823_clk Z ) + USE CLOCK ; - - clknet_level_2_1_926_clk ( ff9 CK ) ( ff10 CK ) ( ff11 CK ) ( ff12 CK ) ( ff13 CK ) ( ff27 CK ) ( ff28 CK ) - ( ff29 CK ) ( ff30 CK ) ( ff31 CK ) ( ff47 CK ) ( ff49 CK ) ( clkbuf_level_2_1_926_clk Z ) + USE CLOCK ; + - clknet_4_13__leaf_clk_regs ( clkload12 A ) ( ff102 CK ) ( ff117 CK ) ( ff118 CK ) ( ff119 CK ) ( ff120 CK ) ( ff121 CK ) + ( ff135 CK ) ( ff136 CK ) ( ff137 CK ) ( ff138 CK ) ( ff139 CK ) ( clkbuf_4_13__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_14__leaf_CELL\/clk2 ( clkload28 A ) ( ff230 CK ) ( ff231 CK ) ( ff232 CK ) ( ff233 CK ) ( ff248 CK ) ( ff250 CK ) + ( ff251 CK ) ( clkbuf_4_14__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_14__leaf_clk_regs ( clkload13 A ) ( ff86 CK ) ( ff87 CK ) ( ff88 CK ) ( ff89 CK ) ( ff104 CK ) ( ff106 CK ) + ( ff107 CK ) ( clkbuf_4_14__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_15__leaf_CELL\/clk2 ( clkload29 A ) ( ff249 CK ) ( ff266 CK ) ( ff267 CK ) ( ff268 CK ) ( ff269 CK ) ( ff284 CK ) + ( ff285 CK ) ( ff286 CK ) ( ff287 CK ) ( clkbuf_4_15__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_15__leaf_clk_regs ( clkload14 A ) ( ff105 CK ) ( ff122 CK ) ( ff123 CK ) ( ff124 CK ) ( ff125 CK ) ( ff140 CK ) + ( ff141 CK ) ( ff142 CK ) ( ff143 CK ) ( clkbuf_4_15__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_1__leaf_CELL\/clk2 ( clkload16 A ) ( ff198 CK ) ( ff199 CK ) ( ff200 CK ) ( ff201 CK ) ( ff202 CK ) ( ff216 CK ) + ( clkbuf_4_1__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_1__leaf_clk_regs ( clkload1 A ) ( ff36 CK ) ( ff37 CK ) ( ff38 CK ) ( ff54 CK ) ( ff55 CK ) ( ff56 CK ) + ( ff57 CK ) ( clkbuf_4_1__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_2__leaf_CELL\/clk2 ( clkload17 A ) ( ff150 CK ) ( ff151 CK ) ( ff152 CK ) ( ff166 CK ) ( ff167 CK ) ( ff168 CK ) + ( ff169 CK ) ( ff170 CK ) ( ff185 CK ) ( ff186 CK ) ( ff187 CK ) ( ff188 CK ) ( clkbuf_4_2__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_2__leaf_clk_regs ( ff4 CK ) ( ff5 CK ) ( ff6 CK ) ( ff7 CK ) ( ff8 CK ) ( ff22 CK ) ( ff23 CK ) + ( ff24 CK ) ( ff25 CK ) ( ff26 CK ) ( ff41 CK ) ( ff42 CK ) ( ff43 CK ) ( ff44 CK ) ( clkbuf_4_2__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_3__leaf_CELL\/clk2 ( clkload18 A ) ( ff203 CK ) ( ff204 CK ) ( ff205 CK ) ( ff206 CK ) ( ff220 CK ) ( ff221 CK ) + ( ff222 CK ) ( ff223 CK ) ( ff224 CK ) ( clkbuf_4_3__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_3__leaf_clk_regs ( clkload2 A ) ( ff58 CK ) ( ff59 CK ) ( ff60 CK ) ( ff61 CK ) ( ff62 CK ) ( ff76 CK ) + ( ff77 CK ) ( ff78 CK ) ( ff79 CK ) ( ff80 CK ) ( clkbuf_4_3__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_4__leaf_CELL\/clk2 ( clkload19 A ) ( ff217 CK ) ( ff218 CK ) ( ff219 CK ) ( ff234 CK ) ( ff235 CK ) ( ff236 CK ) + ( ff237 CK ) ( ff254 CK ) ( clkbuf_4_4__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_4__leaf_clk_regs ( clkload3 A ) ( ff72 CK ) ( ff73 CK ) ( ff74 CK ) ( ff75 CK ) ( ff90 CK ) ( ff91 CK ) + ( ff92 CK ) ( ff93 CK ) ( clkbuf_4_4__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_5__leaf_CELL\/clk2 ( clkload20 A ) ( ff252 CK ) ( ff253 CK ) ( ff255 CK ) ( ff270 CK ) ( ff271 CK ) ( ff272 CK ) + ( ff273 CK ) ( ff288 CK ) ( ff289 CK ) ( ff290 CK ) ( ff291 CK ) ( clkbuf_4_5__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_5__leaf_clk_regs ( clkload4 A ) ( ff108 CK ) ( ff109 CK ) ( ff110 CK ) ( ff111 CK ) ( ff126 CK ) ( ff127 CK ) + ( ff128 CK ) ( ff129 CK ) ( ff144 CK ) ( ff145 CK ) ( ff146 CK ) ( ff147 CK ) ( clkbuf_4_5__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_6__leaf_CELL\/clk2 ( clkload21 A ) ( ff238 CK ) ( ff239 CK ) ( ff240 CK ) ( ff241 CK ) ( ff242 CK ) ( ff257 CK ) + ( ff259 CK ) ( ff260 CK ) ( clkbuf_4_6__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_6__leaf_clk_regs ( clkload5 A ) ( ff94 CK ) ( ff95 CK ) ( ff96 CK ) ( ff97 CK ) ( ff98 CK ) ( ff113 CK ) + ( ff114 CK ) ( clkbuf_4_6__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_7__leaf_CELL\/clk2 ( clkload22 A ) ( ff256 CK ) ( ff258 CK ) ( ff274 CK ) ( ff275 CK ) ( ff276 CK ) ( ff277 CK ) + ( ff278 CK ) ( ff292 CK ) ( ff293 CK ) ( ff294 CK ) ( ff295 CK ) ( ff296 CK ) ( clkbuf_4_7__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_7__leaf_clk_regs ( clkload6 A ) ( ff112 CK ) ( ff115 CK ) ( ff116 CK ) ( ff130 CK ) ( ff131 CK ) ( ff132 CK ) + ( ff133 CK ) ( ff134 CK ) ( ff148 CK ) ( ff149 CK ) ( clkbuf_4_7__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_8__leaf_CELL\/clk2 ( clkload23 A ) ( ff153 CK ) ( ff154 CK ) ( ff155 CK ) ( ff156 CK ) ( ff157 CK ) ( ff171 CK ) + ( ff172 CK ) ( ff173 CK ) ( ff174 CK ) ( ff175 CK ) ( ff191 CK ) ( ff193 CK ) ( clkbuf_4_8__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_8__leaf_clk_regs ( clkload7 A ) ( ff9 CK ) ( ff10 CK ) ( ff11 CK ) ( ff12 CK ) ( ff13 CK ) ( ff27 CK ) + ( ff28 CK ) ( ff29 CK ) ( ff30 CK ) ( ff31 CK ) ( ff47 CK ) ( ff49 CK ) ( clkbuf_4_8__f_clk_regs Z ) + USE CLOCK ; + - clknet_4_9__leaf_CELL\/clk2 ( clkload24 A ) ( ff189 CK ) ( ff190 CK ) ( ff192 CK ) ( ff207 CK ) ( ff208 CK ) ( ff209 CK ) + ( ff210 CK ) ( ff211 CK ) ( clkbuf_4_9__f_CELL\/clk2 Z ) + USE CLOCK ; + - clknet_4_9__leaf_clk_regs ( clkload8 A ) ( ff45 CK ) ( ff46 CK ) ( ff48 CK ) ( ff63 CK ) ( ff64 CK ) ( ff65 CK ) + ( ff66 CK ) ( ff67 CK ) ( clkbuf_4_9__f_clk_regs Z ) + USE CLOCK ; END NETS END DESIGN diff --git a/src/cts/test/balance_levels.ok b/src/cts/test/balance_levels.ok index 00f1f0a771c..9ee00fc2d59 100644 --- a/src/cts/test/balance_levels.ok +++ b/src/cts/test/balance_levels.ok @@ -97,12 +97,11 @@ [INFO CTS-0034] Segment length (rounded): 1. [INFO CTS-0032] Stop criterion found. Max number of sinks is 15. [INFO CTS-0035] Number of sinks covered: 150. -[INFO CTS-0018] Created 3 clock buffers. +[INFO CTS-0018] Created 2 clock buffers. [INFO CTS-0012] Minimum number of buffers in the clock path: 2. [INFO CTS-0013] Maximum number of buffers in the clock path: 2. -[INFO CTS-0014] 1 clock nets were removed/fixed. [INFO CTS-0015] Created 2 clock nets. -[INFO CTS-0016] Fanout distribution for the current clock = 0:1, 1:1.. +[INFO CTS-0016] Fanout distribution for the current clock = 1:1.. [INFO CTS-0017] Max level of the clock tree: 1. [INFO CTS-0018] Created 17 clock buffers. [INFO CTS-0012] Minimum number of buffers in the clock path: 2. @@ -119,10 +118,11 @@ [INFO CTS-0124] Clock net "clk" [INFO CTS-0125] Sinks 1 [INFO CTS-0098] Clock net "clk_regs" -[INFO CTS-0099] Sinks 150 +[INFO CTS-0099] Sinks 165 [INFO CTS-0100] Leaf buffers 0 -[INFO CTS-0101] Average sink wire length 48.98 um +[INFO CTS-0101] Average sink wire length 48.10 um [INFO CTS-0102] Path depth 2 - 2 +[INFO CTS-0207] Leaf load cells 30 [INFO CTS-0098] Clock net "CELL\/clk2" [INFO CTS-0099] Sinks 165 [INFO CTS-0100] Leaf buffers 0 From c6b48589bd67f7039cd48ef4b81e30687714fb5b Mon Sep 17 00:00:00 2001 From: arthur Date: Thu, 11 Jul 2024 10:13:52 -0300 Subject: [PATCH 05/23] remove debug prints Signed-off-by: arthur --- src/cts/src/TritonCTS.cpp | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index a931f668ade..1b32abcf7bc 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -2069,10 +2069,7 @@ void TritonCTS::computeSinkArrivalRecur(odb::dbNet* topClokcNet, // ignore arrival fall (no inverters in current clock tree) float arrival_pin = openSta_->pinArrival( pin, sta::RiseFall::rise(), sta::MinMax::max()); - if (arrival != arrival_pin) { - logger_->report("returned arrival: {}", arrival); - logger_->report("pin arrival: {}", arrival_pin); - } + // add insertion delay float insDelay = 0.0; sta::LibertyCell* libCell From 34311deb91190adc151e36088fb01728a62b9229 Mon Sep 17 00:00:00 2001 From: arthur Date: Tue, 16 Jul 2024 12:33:47 -0300 Subject: [PATCH 06/23] fix error message Signed-off-by: arthur --- src/cts/src/TritonCTS.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 1b32abcf7bc..44d2eda4afa 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -2013,7 +2013,7 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet) } if (paths_accepted > 1 || paths_accepted == 0) { logger_->error(CTS, - 1, + 2, "Number of clock paths is not 1. Number of clock paths: {}", paths_accepted); } From 9db8841b9027b4e27f824e7d39ac3fc3a03b431e Mon Sep 17 00:00:00 2001 From: arthur Date: Tue, 16 Jul 2024 15:18:43 -0300 Subject: [PATCH 07/23] debug prints Signed-off-by: arthur --- src/cts/include/cts/TritonCTS.h | 2 +- src/cts/src/TritonCTS.cpp | 12 ++++++++---- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/cts/include/cts/TritonCTS.h b/src/cts/include/cts/TritonCTS.h index e7882bccdd5..1fed3d094ac 100644 --- a/src/cts/include/cts/TritonCTS.h +++ b/src/cts/include/cts/TritonCTS.h @@ -214,7 +214,7 @@ class TritonCTS ClockInst& dummyClock); void printClockNetwork(const Clock& clockNet) const; void balanceMacroRegisterLatencies(); - float getVertexClkArrival(sta::Vertex* sink_vertex, odb::dbNet* topNet); + float getVertexClkArrival(sta::Vertex* sink_vertex, odb::dbNet* topNet, odb::dbITerm* iterm); void computeAveSinkArrivals(TreeBuilder* builder); void computeSinkArrivalRecur(odb::dbNet* topClokcNet, odb::dbITerm* iterm, diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 44d2eda4afa..46a06914f5b 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -1964,7 +1964,7 @@ void TritonCTS::balanceMacroRegisterLatencies() } } -float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet) +float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, odb::dbITerm* iterm) { sta::VertexPathIterator path_iter(sinVertex, openSta_); float clkPathArrival = 0.0; @@ -2008,13 +2008,17 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet) if (path_start_net == topNet) { clkPathArrival = path->arrival(openSta_); paths_accepted += 1; + } else{ + logger_->report("Path start net regected: {}",path_start_net->getName()); } } } if (paths_accepted > 1 || paths_accepted == 0) { + logger_->error(CTS, 2, - "Number of clock paths is not 1. Number of clock paths: {}", + "Number of clock paths is not 1 for pin {}. Number of clock paths: {}", + iterm->getName(), paths_accepted); } return clkPathArrival; @@ -2028,7 +2032,7 @@ void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder) openSta_->ensureClkArrivals(); Clock clock = builder->getClock(); odb::dbNet* topClockNet = clock.getNetObj(); - if (builder->getTreeType() == TreeType::RegisterTree) { + if (builder->getTopInputNet() != nullptr) { topClockNet = builder->getTopInputNet(); } // compute average input arrival at all sinks @@ -2065,7 +2069,7 @@ void TritonCTS::computeSinkArrivalRecur(odb::dbNet* topClokcNet, if (pin) { sta::Graph* graph = openSta_->graph(); sta::Vertex* drvr_vertex = graph->pinDrvrVertex(pin); - float arrival = getVertexClkArrival(drvr_vertex, topClokcNet); + float arrival = getVertexClkArrival(drvr_vertex, topClokcNet, iterm); // ignore arrival fall (no inverters in current clock tree) float arrival_pin = openSta_->pinArrival( pin, sta::RiseFall::rise(), sta::MinMax::max()); From 11fc3b7d8dc852faf14a443f0386e9e0fbbfff97 Mon Sep 17 00:00:00 2001 From: arthur Date: Wed, 17 Jul 2024 17:14:22 -0300 Subject: [PATCH 08/23] store the input clock net information on the tree builder Signed-off-by: arthur --- src/cts/include/cts/TritonCTS.h | 7 +++-- src/cts/src/TreeBuilder.h | 3 ++ src/cts/src/TritonCTS.cpp | 54 ++++++++++++++++++++++++--------- 3 files changed, 48 insertions(+), 16 deletions(-) diff --git a/src/cts/include/cts/TritonCTS.h b/src/cts/include/cts/TritonCTS.h index 1fed3d094ac..bb5b384071e 100644 --- a/src/cts/include/cts/TritonCTS.h +++ b/src/cts/include/cts/TritonCTS.h @@ -138,9 +138,11 @@ class TritonCTS void clearNumClocks() { numberOfClocks_ = 0; } unsigned getNumClocks() const { return numberOfClocks_; } void initOneClockTree(odb::dbNet* driverNet, + odb::dbNet* clkInputNet, const std::string& sdcClockName, TreeBuilder* parent); - TreeBuilder* initClock(odb::dbNet* net, + TreeBuilder* initClock(odb::dbNet* firstNet, + odb::dbNet* clkInputNet, const std::string& sdcClock, TreeBuilder* parentBuilder); void disconnectAllSinksFromNet(odb::dbNet* net); @@ -148,7 +150,8 @@ class TritonCTS void checkUpstreamConnections(odb::dbNet* net); void createClockBuffers(Clock& clockNet); HTreeBuilder* initClockTreeForMacrosAndRegs( - odb::dbNet*& net, + odb::dbNet*& firstNet, + odb::dbNet* clkInputNet, const std::unordered_set& buffer_masters, Clock& ClockNet, TreeBuilder* parentBuilder); diff --git a/src/cts/src/TreeBuilder.h b/src/cts/src/TreeBuilder.h index ec15843ff06..4109587f7dd 100644 --- a/src/cts/src/TreeBuilder.h +++ b/src/cts/src/TreeBuilder.h @@ -251,6 +251,8 @@ class TreeBuilder void setTopBufferName(std::string name) { topBufferName_ = name; } odb::dbNet* getTopInputNet() const { return topInputNet_; } void setTopInputNet(odb::dbNet* net) { topInputNet_ = net; } + odb::dbNet* getDrivingNet() const { return drivingNet_; } + void setDrivingNet(odb::dbNet* net) { drivingNet_ = net; } protected: CtsOptions* options_ = nullptr; @@ -281,6 +283,7 @@ class TreeBuilder float topBufferDelay_ = 0.0; odb::dbInst* topBuffer_ = nullptr; std::string topBufferName_; + odb::dbNet* drivingNet_ = nullptr; odb::dbNet* topInputNet_ = nullptr; }; diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 46a06914f5b..51ca0634b02 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -189,6 +189,7 @@ void TritonCTS::buildClockTrees() } void TritonCTS::initOneClockTree(odb::dbNet* driverNet, + odb::dbNet* clkInputNet, const std::string& sdcClockName, TreeBuilder* parent) { @@ -197,7 +198,7 @@ void TritonCTS::initOneClockTree(odb::dbNet* driverNet, logger_->info( CTS, 116, "Special net \"{}\" skipped.", driverNet->getName()); } else { - clockBuilder = initClock(driverNet, sdcClockName, parent); + clockBuilder = initClock(driverNet, clkInputNet, sdcClockName, parent); } // Treat gated clocks as separate clock trees // TODO: include sinks from gated clocks together with other sinks and build @@ -214,7 +215,7 @@ void TritonCTS::initOneClockTree(odb::dbNet* driverNet, if (visitedClockNets_.find(outputNet) == visitedClockNets_.end() && !openSta_->sdc()->isLeafPinClock( network_->dbToSta(outputPin))) { - initOneClockTree(outputNet, sdcClockName, clockBuilder); + initOneClockTree(outputNet, clkInputNet, sdcClockName, clockBuilder); } } } @@ -865,7 +866,7 @@ void TritonCTS::populateTritonCTS() // Initializes the net in TritonCTS. If the number of sinks is less than // 2, the net is discarded. if (visitedClockNets_.find(net) == visitedClockNets_.end()) { - initOneClockTree(net, clkName, nullptr); + initOneClockTree(net, net, clkName, nullptr); } } else { logger_->warn( @@ -886,6 +887,7 @@ void TritonCTS::populateTritonCTS() } TreeBuilder* TritonCTS::initClock(odb::dbNet* firstNet, + odb::dbNet* clkInputNet, const std::string& sdcClock, TreeBuilder* parentBuilder) { @@ -941,7 +943,7 @@ TreeBuilder* TritonCTS::initClock(odb::dbNet* firstNet, // Build a clock tree to drive macro cells with insertion delays // separated from registers or leaves without insertion delays HTreeBuilder* builder = initClockTreeForMacrosAndRegs( - firstNet, buffer_masters, clockNet, parentBuilder); + firstNet, clkInputNet, buffer_masters, clockNet, parentBuilder); return builder; } @@ -964,6 +966,7 @@ TreeBuilder* TritonCTS::initClock(odb::dbNet* firstNet, // HTreeBuilder* TritonCTS::initClockTreeForMacrosAndRegs( odb::dbNet*& firstNet, + odb::dbNet* clkInputNet, const std::unordered_set& buffer_masters, Clock& clockNet, TreeBuilder* parentBuilder) @@ -1024,6 +1027,7 @@ HTreeBuilder* TritonCTS::initClockTreeForMacrosAndRegs( "macros"); if (firstBuilder) { firstBuilder->setTreeType(TreeType::MacroTree); + firstBuilder->setTopInputNet(clkInputNet); } // create a new net 'secondNet' to drive register sinks @@ -1042,7 +1046,8 @@ HTreeBuilder* TritonCTS::initClockTreeForMacrosAndRegs( if (secondBuilder) { secondBuilder->setTreeType(TreeType::RegisterTree); secondBuilder->setTopBufferName(topBufferName); - secondBuilder->setTopInputNet(firstNet); + secondBuilder->setDrivingNet(firstNet); + secondBuilder->setTopInputNet(clkInputNet); } return secondBuilder; @@ -1201,7 +1206,7 @@ void TritonCTS::writeClockNetsToDb(TreeBuilder* builder, = block_->findInst(builder->getTopBufferName().c_str()); if (topRegBuffer) { odb::dbITerm* topRegBufferInputPin = getFirstInput(topRegBuffer); - topRegBufferInputPin->connect(builder->getTopInputNet()); + topRegBufferInputPin->connect(builder->getDrivingNet()); } } @@ -1970,11 +1975,24 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, float clkPathArrival = 0.0; int paths_accepted = 0; while (path_iter.hasNext()) { - sta::PathVertex* path = path_iter.next(); + sta::Path* path = path_iter.next(); + bool path_transition = true; + bool path_min_max = true; if (path->dcalcAnalysisPt(openSta_)->corner() != openSta_->cmdCorner()) { continue; } + if (path->clkEdge(openSta_)->transition() != sta::RiseFall::rise()) { + // only populate with rising edges + path_transition = false; + continue; + } + if (path->dcalcAnalysisPt(openSta_)->delayMinMax() + != sta::MinMax::max()) { + // only populate with max delay + path_min_max = false; + continue; + } sta::PathExpanded expand(path, openSta_); @@ -1985,13 +2003,23 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, odb::dbNet* path_start_net; if (start->clkEdge(openSta_)->transition() != sta::RiseFall::rise()) { // only populate with rising edges - continue; + if(path_transition) { + logger_->report("Não são o mesmo transitions"); + } } if (start->dcalcAnalysisPt(openSta_)->delayMinMax() != sta::MinMax::max()) { + if(path_min_max) { + logger_->report("Não são o mesmo MinMax"); + } // only populate with max delay - continue; + } + if(!path_transition) { + logger_->report("Não são o mesmo transitions"); + } + if(!path_min_max) { + logger_->report("Não são o mesmo MinMax"); } odb::dbITerm* term; @@ -2008,8 +2036,6 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, if (path_start_net == topNet) { clkPathArrival = path->arrival(openSta_); paths_accepted += 1; - } else{ - logger_->report("Path start net regected: {}",path_start_net->getName()); } } } @@ -2031,16 +2057,16 @@ void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder) openSta_->ensureClkNetwork(); openSta_->ensureClkArrivals(); Clock clock = builder->getClock(); - odb::dbNet* topClockNet = clock.getNetObj(); + odb::dbNet* topInputClockNet = clock.getNetObj(); if (builder->getTopInputNet() != nullptr) { - topClockNet = builder->getTopInputNet(); + topInputClockNet = builder->getTopInputNet(); } // compute average input arrival at all sinks float sumArrivals = 0.0; unsigned numSinks = 0; clock.forEachSink([&](const ClockInst& sink) { odb::dbITerm* iterm = sink.getDbInputPin(); - computeSinkArrivalRecur(topClockNet, iterm, sumArrivals, numSinks); + computeSinkArrivalRecur(topInputClockNet, iterm, sumArrivals, numSinks); }); float aveArrival = sumArrivals / (float) numSinks; builder->setAveSinkArrival(aveArrival); From d97cac15bce714454d4f5c963b8c8b354834b1e7 Mon Sep 17 00:00:00 2001 From: arthurjolo Date: Thu, 18 Jul 2024 20:36:28 +0000 Subject: [PATCH 09/23] debug prints Signed-off-by: arthurjolo --- src/cts/src/TritonCTS.cpp | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 51ca0634b02..feb4ae0f9b9 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -1971,6 +1971,7 @@ void TritonCTS::balanceMacroRegisterLatencies() float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, odb::dbITerm* iterm) { + logger_->report("Analisando iterm: {}", iterm->getName()); sta::VertexPathIterator path_iter(sinVertex, openSta_); float clkPathArrival = 0.0; int paths_accepted = 0; @@ -1978,20 +1979,14 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, sta::Path* path = path_iter.next(); bool path_transition = true; bool path_min_max = true; - - if (path->dcalcAnalysisPt(openSta_)->corner() != openSta_->cmdCorner()) { - continue; - } if (path->clkEdge(openSta_)->transition() != sta::RiseFall::rise()) { // only populate with rising edges - path_transition = false; - continue; + path_transition = false; } if (path->dcalcAnalysisPt(openSta_)->delayMinMax() != sta::MinMax::max()) { // only populate with max delay path_min_max = false; - continue; } sta::PathExpanded expand(path, openSta_); @@ -2003,7 +1998,8 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, odb::dbNet* path_start_net; if (start->clkEdge(openSta_)->transition() != sta::RiseFall::rise()) { // only populate with rising edges - if(path_transition) { + continue; + if(path_transition) { logger_->report("Não são o mesmo transitions"); } } @@ -2013,6 +2009,7 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, if(path_min_max) { logger_->report("Não são o mesmo MinMax"); } + continue; // only populate with max delay } if(!path_transition) { @@ -2029,14 +2026,23 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, network_->staToDb(start->pin(openSta_), term, port, moditerm, modbterm); if (term) { path_start_net = term->getNet(); + if (iterm->getName() == "u_ca53_noram/u_ca53tlb/u_tlb_pagewalk/g_protection_pw6_walk_cache_ecc_err_early_reg/CK") { + logger_->report("iterm do start: {}", term->getName()); + } } if (port) { path_start_net = port->getNet(); + if (iterm->getName() == "u_ca53_noram/u_ca53tlb/u_tlb_pagewalk/g_protection_pw6_walk_cache_ecc_err_early_reg/CK") { + logger_->report("iterm do start: {}", port->getName()); + } } if (path_start_net == topNet) { clkPathArrival = path->arrival(openSta_); paths_accepted += 1; - } + return clkPathArrival; + } else if (iterm->getName() == "u_ca53_noram/u_ca53tlb/u_tlb_pagewalk/g_protection_pw6_walk_cache_ecc_err_early_reg/CK") { + logger_->report("Rejeitou: {}, Queria: {}",path_start_net->getName(), topNet->getName()); + } } } if (paths_accepted > 1 || paths_accepted == 0) { @@ -2097,7 +2103,7 @@ void TritonCTS::computeSinkArrivalRecur(odb::dbNet* topClokcNet, sta::Vertex* drvr_vertex = graph->pinDrvrVertex(pin); float arrival = getVertexClkArrival(drvr_vertex, topClokcNet, iterm); // ignore arrival fall (no inverters in current clock tree) - float arrival_pin = openSta_->pinArrival( + float pin_arrival = openSta_->pinArrival( pin, sta::RiseFall::rise(), sta::MinMax::max()); // add insertion delay From e2c3b7fae5ad1895fd79ccbb854ac33522396044 Mon Sep 17 00:00:00 2001 From: arthurjolo Date: Tue, 23 Jul 2024 02:54:51 +0000 Subject: [PATCH 10/23] remove debug print Signed-off-by: arthurjolo --- src/cts/src/TritonCTS.cpp | 29 +++++------------------------ 1 file changed, 5 insertions(+), 24 deletions(-) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index feb4ae0f9b9..d7281aa5a74 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -1206,6 +1206,7 @@ void TritonCTS::writeClockNetsToDb(TreeBuilder* builder, = block_->findInst(builder->getTopBufferName().c_str()); if (topRegBuffer) { odb::dbITerm* topRegBufferInputPin = getFirstInput(topRegBuffer); + odb::dbITerm* topRegBufferOutPin = topRegBuffer->getFirstOutput(); topRegBufferInputPin->connect(builder->getDrivingNet()); } } @@ -1971,7 +1972,6 @@ void TritonCTS::balanceMacroRegisterLatencies() float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, odb::dbITerm* iterm) { - logger_->report("Analisando iterm: {}", iterm->getName()); sta::VertexPathIterator path_iter(sinVertex, openSta_); float clkPathArrival = 0.0; int paths_accepted = 0; @@ -1999,25 +1999,13 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, if (start->clkEdge(openSta_)->transition() != sta::RiseFall::rise()) { // only populate with rising edges continue; - if(path_transition) { - logger_->report("Não são o mesmo transitions"); - } } if (start->dcalcAnalysisPt(openSta_)->delayMinMax() != sta::MinMax::max()) { - if(path_min_max) { - logger_->report("Não são o mesmo MinMax"); - } continue; // only populate with max delay } - if(!path_transition) { - logger_->report("Não são o mesmo transitions"); - } - if(!path_min_max) { - logger_->report("Não são o mesmo MinMax"); - } odb::dbITerm* term; odb::dbBTerm* port; @@ -2026,30 +2014,23 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, network_->staToDb(start->pin(openSta_), term, port, moditerm, modbterm); if (term) { path_start_net = term->getNet(); - if (iterm->getName() == "u_ca53_noram/u_ca53tlb/u_tlb_pagewalk/g_protection_pw6_walk_cache_ecc_err_early_reg/CK") { - logger_->report("iterm do start: {}", term->getName()); - } + + } if (port) { path_start_net = port->getNet(); - if (iterm->getName() == "u_ca53_noram/u_ca53tlb/u_tlb_pagewalk/g_protection_pw6_walk_cache_ecc_err_early_reg/CK") { - logger_->report("iterm do start: {}", port->getName()); - } + } if (path_start_net == topNet) { clkPathArrival = path->arrival(openSta_); paths_accepted += 1; return clkPathArrival; - } else if (iterm->getName() == "u_ca53_noram/u_ca53tlb/u_tlb_pagewalk/g_protection_pw6_walk_cache_ecc_err_early_reg/CK") { - logger_->report("Rejeitou: {}, Queria: {}",path_start_net->getName(), topNet->getName()); } } } if (paths_accepted > 1 || paths_accepted == 0) { - logger_->error(CTS, - 2, - "Number of clock paths is not 1 for pin {}. Number of clock paths: {}", + logger_->report("Number of clock paths is not 1 for pin {}. Number of clock paths: {}", iterm->getName(), paths_accepted); } From 079addee18c4e74e95219cf2d6fd8bd94c531e4a Mon Sep 17 00:00:00 2001 From: arthur Date: Fri, 23 Aug 2024 10:56:07 -0300 Subject: [PATCH 11/23] format code Signed-off-by: arthur --- src/cts/src/TritonCTS.cpp | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index d7281aa5a74..9d83300d37c 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -2003,7 +2003,7 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, if (start->dcalcAnalysisPt(openSta_)->delayMinMax() != sta::MinMax::max()) { - continue; + continue; // only populate with max delay } @@ -2014,8 +2014,6 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, network_->staToDb(start->pin(openSta_), term, port, moditerm, modbterm); if (term) { path_start_net = term->getNet(); - - } if (port) { path_start_net = port->getNet(); @@ -2024,7 +2022,7 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, if (path_start_net == topNet) { clkPathArrival = path->arrival(openSta_); paths_accepted += 1; - return clkPathArrival; + return clkPathArrival; } } } From 17c46015f66bda2b44ec1a283cfaad966ccbdbee Mon Sep 17 00:00:00 2001 From: arthur Date: Mon, 26 Aug 2024 16:10:12 -0300 Subject: [PATCH 12/23] update graph information correctly Signed-off-by: arthur --- src/cts/include/cts/TritonCTS.h | 6 +++-- src/cts/src/TritonCTS.cpp | 41 +++++++++++++-------------------- 2 files changed, 20 insertions(+), 27 deletions(-) diff --git a/src/cts/include/cts/TritonCTS.h b/src/cts/include/cts/TritonCTS.h index b58dfe02bb5..d69abaa6275 100644 --- a/src/cts/include/cts/TritonCTS.h +++ b/src/cts/include/cts/TritonCTS.h @@ -59,6 +59,7 @@ class dbNetwork; class Unit; class LibertyCell; class Vertex; +class Graph; } // namespace sta namespace stt { @@ -210,11 +211,12 @@ class TritonCTS void printClockNetwork(const Clock& clockNet) const; void balanceMacroRegisterLatencies(); float getVertexClkArrival(sta::Vertex* sink_vertex, odb::dbNet* topNet, odb::dbITerm* iterm); - void computeAveSinkArrivals(TreeBuilder* builder); + void computeAveSinkArrivals(TreeBuilder* builder, sta::Graph* graph); void computeSinkArrivalRecur(odb::dbNet* topClokcNet, odb::dbITerm* iterm, float& sumArrivals, - unsigned& numSinks); + unsigned& numSinks, + sta::Graph* graph); void adjustLatencies(TreeBuilder* macroBuilder, TreeBuilder* registerBuilder); void computeTopBufferDelay(TreeBuilder* builder); odb::dbInst* insertDelayBuffer(odb::dbInst* driver, diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 127f0de1abe..bb6f9587b91 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -2023,14 +2023,23 @@ void TritonCTS::balanceMacroRegisterLatencies() // Visit builders from bottom up such that latencies are adjusted near bottom // trees first + openSta_->ensureGraph(); + openSta_->searchPreamble(); + openSta_->ensureClkNetwork(); + openSta_->ensureClkArrivals(); + sta::Graph* graph = openSta_->graph(); for (auto iter = builders_->rbegin(); iter != builders_->rend(); ++iter) { TreeBuilder* registerBuilder = *iter; if (registerBuilder->getTreeType() == TreeType::RegisterTree) { TreeBuilder* macroBuilder = registerBuilder->getParent(); if (macroBuilder) { - computeAveSinkArrivals(registerBuilder); - computeAveSinkArrivals(macroBuilder); + computeAveSinkArrivals(registerBuilder, graph); + computeAveSinkArrivals(macroBuilder, graph); adjustLatencies(macroBuilder, registerBuilder); + // Update graph information after possible buffers inserted + openSta_->updateTiming(false); + openSta_->ensureClkNetwork(); + openSta_->ensureClkArrivals(); } } } @@ -2043,17 +2052,6 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, int paths_accepted = 0; while (path_iter.hasNext()) { sta::Path* path = path_iter.next(); - bool path_transition = true; - bool path_min_max = true; - if (path->clkEdge(openSta_)->transition() != sta::RiseFall::rise()) { - // only populate with rising edges - path_transition = false; - } - if (path->dcalcAnalysisPt(openSta_)->delayMinMax() - != sta::MinMax::max()) { - // only populate with max delay - path_min_max = false; - } sta::PathExpanded expand(path, openSta_); @@ -2101,12 +2099,8 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, return clkPathArrival; } -void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder) +void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder, sta::Graph* graph) { - openSta_->ensureGraph(); - openSta_->searchPreamble(); - openSta_->ensureClkNetwork(); - openSta_->ensureClkArrivals(); Clock clock = builder->getClock(); odb::dbNet* topInputClockNet = clock.getNetObj(); if (builder->getTopInputNet() != nullptr) { @@ -2117,7 +2111,7 @@ void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder) unsigned numSinks = 0; clock.forEachSink([&](const ClockInst& sink) { odb::dbITerm* iterm = sink.getDbInputPin(); - computeSinkArrivalRecur(topInputClockNet, iterm, sumArrivals, numSinks); + computeSinkArrivalRecur(topInputClockNet, iterm, sumArrivals, numSinks, graph); }); float aveArrival = sumArrivals / (float) numSinks; builder->setAveSinkArrival(aveArrival); @@ -2135,7 +2129,8 @@ void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder) void TritonCTS::computeSinkArrivalRecur(odb::dbNet* topClokcNet, odb::dbITerm* iterm, float& sumArrivals, - unsigned& numSinks) + unsigned& numSinks, + sta::Graph* graph) { if (iterm) { odb::dbInst* inst = iterm->getInst(); @@ -2144,12 +2139,8 @@ void TritonCTS::computeSinkArrivalRecur(odb::dbNet* topClokcNet, // either register or macro input pin sta::Pin* pin = network_->dbToSta(iterm); if (pin) { - sta::Graph* graph = openSta_->graph(); sta::Vertex* drvr_vertex = graph->pinDrvrVertex(pin); float arrival = getVertexClkArrival(drvr_vertex, topClokcNet, iterm); - // ignore arrival fall (no inverters in current clock tree) - float pin_arrival = openSta_->pinArrival( - pin, sta::RiseFall::rise(), sta::MinMax::max()); // add insertion delay float insDelay = 0.0; @@ -2186,7 +2177,7 @@ void TritonCTS::computeSinkArrivalRecur(odb::dbNet* topClokcNet, odb::dbITerm* inTerm = *iter; if (inTerm->getIoType() == odb::dbIoType::INPUT) { computeSinkArrivalRecur( - topClokcNet, inTerm, sumArrivals, numSinks); + topClokcNet, inTerm, sumArrivals, numSinks, graph); } } } From 56b61547f624f722ba0773d06e4ecc623bf15e8f Mon Sep 17 00:00:00 2001 From: arthur Date: Thu, 29 Aug 2024 14:29:06 -0300 Subject: [PATCH 13/23] enable obstruction awere Signed-off-by: arthur --- src/cts/src/CtsOptions.h | 2 +- src/cts/src/TritonCTS.cpp | 2 +- src/cts/src/TritonCTS.tcl | 5 +---- 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/src/cts/src/CtsOptions.h b/src/cts/src/CtsOptions.h index 7aabbf95865..b2070c24a2a 100644 --- a/src/cts/src/CtsOptions.h +++ b/src/cts/src/CtsOptions.h @@ -296,7 +296,7 @@ class CtsOptions std::vector clockNetsObjs_; utl::Logger* logger_ = nullptr; stt::SteinerTreeBuilder* sttBuilder_ = nullptr; - bool obsAware_ = false; + bool obsAware_ = true; bool applyNDR_ = false; bool insertionDelay_ = true; bool bufferListInferred_ = false; diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index bb6f9587b91..5d2d1f74c24 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -2037,9 +2037,9 @@ void TritonCTS::balanceMacroRegisterLatencies() computeAveSinkArrivals(macroBuilder, graph); adjustLatencies(macroBuilder, registerBuilder); // Update graph information after possible buffers inserted - openSta_->updateTiming(false); openSta_->ensureClkNetwork(); openSta_->ensureClkArrivals(); + openSta_->updateTiming(false); } } } diff --git a/src/cts/src/TritonCTS.tcl b/src/cts/src/TritonCTS.tcl index 5b5a95acca4..02f04a9a73d 100644 --- a/src/cts/src/TritonCTS.tcl +++ b/src/cts/src/TritonCTS.tcl @@ -84,7 +84,6 @@ sta::define_cmd_args "clock_tree_synthesis" {[-wire_unit unit] [-sink_clustering_levels levels] \ [-num_static_layers] \ [-sink_clustering_buffer] \ - [-obstruction_aware] \ [-apply_ndr] \ [-sink_buffer_max_cap_derate] \ [-dont_use_dummy_load] \ @@ -101,7 +100,7 @@ proc clock_tree_synthesis { args } { -sink_clustering_levels -tree_buf \ -sink_buffer_max_cap_derate -delay_buffer_derate} \ flags {-post_cts_disable -sink_clustering_enable -balance_levels \ - -obstruction_aware -apply_ndr -dont_use_dummy_load + -apply_ndr -dont_use_dummy_load };# checker off sta::check_argc_eq0 "clock_tree_synthesis" $args @@ -209,8 +208,6 @@ proc clock_tree_synthesis { args } { cts::set_delay_buffer_derate $buffer_derate } - cts::set_obstruction_aware [info exists flags(-obstruction_aware)] - if { [info exists flags(-dont_use_dummy_load)] } { cts::set_dummy_load false } else { From a6a247ec3120de64235b39fd7b2f6b55aae8449a Mon Sep 17 00:00:00 2001 From: arthur Date: Thu, 5 Sep 2024 14:02:55 -0300 Subject: [PATCH 14/23] rename varibles Signed-off-by: arthur --- src/cts/include/cts/TritonCTS.h | 2 +- src/cts/src/TritonCTS.cpp | 45 ++++++++++++++++++--------------- 2 files changed, 26 insertions(+), 21 deletions(-) diff --git a/src/cts/include/cts/TritonCTS.h b/src/cts/include/cts/TritonCTS.h index d69abaa6275..b4b4e964103 100644 --- a/src/cts/include/cts/TritonCTS.h +++ b/src/cts/include/cts/TritonCTS.h @@ -210,7 +210,7 @@ class TritonCTS ClockInst& dummyClock); void printClockNetwork(const Clock& clockNet) const; void balanceMacroRegisterLatencies(); - float getVertexClkArrival(sta::Vertex* sink_vertex, odb::dbNet* topNet, odb::dbITerm* iterm); + float getVertexClkArrival(sta::Vertex* sinkVertex, odb::dbNet* topNet, odb::dbITerm* iterm); void computeAveSinkArrivals(TreeBuilder* builder, sta::Graph* graph); void computeSinkArrivalRecur(odb::dbNet* topClokcNet, odb::dbITerm* iterm, diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index ad1827e1170..846b2930b5f 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -2034,14 +2034,14 @@ void TritonCTS::balanceMacroRegisterLatencies() openSta_->ensureGraph(); openSta_->searchPreamble(); openSta_->ensureClkNetwork(); - openSta_->ensureClkArrivals(); + openSta_->updateTiming(false); sta::Graph* graph = openSta_->graph(); for (auto iter = builders_->rbegin(); iter != builders_->rend(); ++iter) { TreeBuilder* registerBuilder = *iter; if (registerBuilder->getTreeType() == TreeType::RegisterTree) { TreeBuilder* macroBuilder = registerBuilder->getParent(); if (macroBuilder) { - computeAveSinkArrivals(registerBuilder, graph); + computeAveSinkArrivals(registerBuilder, graph);// -> computeSinkArrivalRecur -> getVertexClkArrival computeAveSinkArrivals(macroBuilder, graph); adjustLatencies(macroBuilder, registerBuilder); // Update graph information after possible buffers inserted @@ -2053,21 +2053,22 @@ void TritonCTS::balanceMacroRegisterLatencies() } } -float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, odb::dbITerm* iterm) +float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex, odb::dbNet* topNet, odb::dbITerm* iterm) { - sta::VertexPathIterator path_iter(sinVertex, openSta_); + //logger_->report("Sink: {}", iterm->getName()); + sta::VertexPathIterator pathIter(sinkVertex, openSta_); float clkPathArrival = 0.0; - int paths_accepted = 0; - while (path_iter.hasNext()) { - sta::Path* path = path_iter.next(); + int pathsAccepted = 0; + while (pathIter.hasNext()) { + sta::Path* path = pathIter.next(); sta::PathExpanded expand(path, openSta_); const sta::Clock* clock = path->clock(openSta_); - if (clock) { + if (clock || !clock) { const sta::PathRef* start = expand.startPath(); - odb::dbNet* path_start_net; + odb::dbNet* pathStartNet = nullptr; if (start->clkEdge(openSta_)->transition() != sta::RiseFall::rise()) { // only populate with rising edges continue; @@ -2085,24 +2086,24 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinVertex, odb::dbNet* topNet, odb::dbModBTerm* modbterm; network_->staToDb(start->pin(openSta_), term, port, moditerm, modbterm); if (term) { - path_start_net = term->getNet(); + pathStartNet = term->getNet(); } if (port) { - path_start_net = port->getNet(); + pathStartNet = port->getNet(); } - if (path_start_net == topNet) { + if (pathStartNet == topNet) { clkPathArrival = path->arrival(openSta_); - paths_accepted += 1; - return clkPathArrival; - } + pathsAccepted += 1; + return clkPathArrival; + } } } - if (paths_accepted > 1 || paths_accepted == 0) { + if (pathsAccepted > 1 || pathsAccepted == 0) { logger_->report("Number of clock paths is not 1 for pin {}. Number of clock paths: {}", iterm->getName(), - paths_accepted); + pathsAccepted); } return clkPathArrival; } @@ -2147,9 +2148,13 @@ void TritonCTS::computeSinkArrivalRecur(odb::dbNet* topClokcNet, // either register or macro input pin sta::Pin* pin = network_->dbToSta(iterm); if (pin) { - sta::Vertex* drvr_vertex = graph->pinDrvrVertex(pin); - float arrival = getVertexClkArrival(drvr_vertex, topClokcNet, iterm); - + sta::Vertex* regVertex = graph->pinDrvrVertex(pin); + float arrival = getVertexClkArrival(regVertex, topClokcNet, iterm); + float inputArrival = openSta_->pinArrival( + pin, sta::RiseFall::rise(), sta::MinMax::max()); + if(arrival != inputArrival) { + logger_->report("arrival: {}, pin Arrival: {}", arrival, inputArrival); + } // add insertion delay float insDelay = 0.0; sta::LibertyCell* libCell From cf74a73ba9678860bda1a32e89d961783f0d2065 Mon Sep 17 00:00:00 2001 From: arthur Date: Mon, 16 Sep 2024 17:04:37 -0300 Subject: [PATCH 15/23] fix merge Signed-off-by: arthur --- src/cts/src/TritonCTS.cpp | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 895b0a76a3b..faa20d6fe6b 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -1181,8 +1181,9 @@ Clock TritonCTS::forkRegisterClockNetwork( // create a new clock buffer odb::dbMaster* master = db_->findMaster(options_->getRootBuffer().c_str()); - std::string cellName = "clkbuf_regs_0_" + clockNet.getSdcName(); - odb::dbInst* clockBuf = odb::dbInst::create(block_, master, cellName.c_str(), false, target_module); + topBufferName = "clkbuf_regs_" + std::to_string(regTreeRootBufIndex_++) + "_" + + clockNet.getSdcName(); + odb::dbInst* clockBuf = odb::dbInst::create(block_, master, topBufferName.c_str(), false, target_module); odb::dbITerm* inputTerm = getFirstInput(clockBuf); odb::dbITerm* outputTerm = clockBuf->getFirstOutput(); inputTerm->connect(firstNet); @@ -2042,7 +2043,7 @@ void TritonCTS::balanceMacroRegisterLatencies() float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex, odb::dbNet* topNet, odb::dbITerm* iterm) { - //logger_->report("Sink: {}", iterm->getName()); + sta::VertexPathIterator pathIter(sinkVertex, openSta_); float clkPathArrival = 0.0; int pathsAccepted = 0; From 22625ec6d04bfc6e3a5565eb1cccf1a94bffc748 Mon Sep 17 00:00:00 2001 From: arthur Date: Tue, 24 Sep 2024 14:13:05 -0300 Subject: [PATCH 16/23] remove unused variables Signed-off-by: arthur --- src/cts/src/TritonCTS.cpp | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 5a8fd2b4e35..0890de283be 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -2023,20 +2023,17 @@ void TritonCTS::balanceMacroRegisterLatencies() openSta_->ensureGraph(); openSta_->searchPreamble(); openSta_->ensureClkNetwork(); - openSta_->updateTiming(false); sta::Graph* graph = openSta_->graph(); for (auto iter = builders_->rbegin(); iter != builders_->rend(); ++iter) { TreeBuilder* registerBuilder = *iter; if (registerBuilder->getTreeType() == TreeType::RegisterTree) { TreeBuilder* macroBuilder = registerBuilder->getParent(); if (macroBuilder) { - computeAveSinkArrivals(registerBuilder, graph);// -> computeSinkArrivalRecur -> getVertexClkArrival - computeAveSinkArrivals(macroBuilder, graph); - adjustLatencies(macroBuilder, registerBuilder); // Update graph information after possible buffers inserted - openSta_->ensureClkNetwork(); - openSta_->ensureClkArrivals(); openSta_->updateTiming(false); + computeAveSinkArrivals(registerBuilder, graph); + computeAveSinkArrivals(macroBuilder, graph); + adjustLatencies(macroBuilder, registerBuilder); } } } @@ -2137,13 +2134,8 @@ void TritonCTS::computeSinkArrivalRecur(odb::dbNet* topClokcNet, // either register or macro input pin sta::Pin* pin = network_->dbToSta(iterm); if (pin) { - sta::Vertex* regVertex = graph->pinDrvrVertex(pin); - float arrival = getVertexClkArrival(regVertex, topClokcNet, iterm); - float inputArrival = openSta_->pinArrival( - pin, sta::RiseFall::rise(), sta::MinMax::max()); - if(arrival != inputArrival) { - logger_->report("arrival: {}, pin Arrival: {}", arrival, inputArrival); - } + sta::Vertex* sinkVertex = graph->pinDrvrVertex(pin); + float arrival = getVertexClkArrival(sinkVertex, topClokcNet, iterm); // add insertion delay float insDelay = 0.0; sta::LibertyCell* libCell From 6d95db03a7c9969f3e54d9cf0841f63171b8cfc1 Mon Sep 17 00:00:00 2001 From: arthur Date: Tue, 24 Sep 2024 14:22:00 -0300 Subject: [PATCH 17/23] remove unused variables Signed-off-by: arthur --- src/cts/src/TritonCTS.cpp | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 0890de283be..30aba9b826c 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -1239,10 +1239,6 @@ void TritonCTS::writeClockNetsToDb(TreeBuilder* builder, const std::string topRegBufferName = "clkbuf_regs_0_" + clockNet.getSdcName(); odb::dbInst* topRegBuffer = block_->findInst(topRegBufferName.c_str()); - odb::dbNet* topNet = nullptr; - if (topRegBuffer) { - topNet = getFirstInput(topRegBuffer)->getNet(); - } disconnectAllSinksFromNet(topClockNet); @@ -1252,7 +1248,6 @@ void TritonCTS::writeClockNetsToDb(TreeBuilder* builder, = block_->findInst(builder->getTopBufferName().c_str()); if (topRegBuffer) { odb::dbITerm* topRegBufferInputPin = getFirstInput(topRegBuffer); - odb::dbITerm* topRegBufferOutPin = topRegBuffer->getFirstOutput(); topRegBufferInputPin->connect(builder->getDrivingNet()); } } From 07c3b2366a9393d5ff864a293bb0207868574ed0 Mon Sep 17 00:00:00 2001 From: arthur Date: Mon, 7 Oct 2024 16:14:23 -0300 Subject: [PATCH 18/23] update ok fles Signed-off-by: arthur --- src/cts/src/TritonCTS.cpp | 5 +-- src/cts/test/array.tcl | 3 +- src/cts/test/array_dummy.tcl | 1 - src/cts/test/array_full_flow.tcl | 3 +- src/cts/test/array_ins_delay.tcl | 3 +- src/cts/test/array_no_blockages.tcl | 3 +- src/cts/test/balance_levels.py | 1 - src/cts/test/balance_levels.tcl | 3 +- src/cts/test/check_buffers.py | 1 - src/cts/test/check_buffers.tcl | 3 +- src/cts/test/check_buffers_blockages.tcl | 3 +- src/cts/test/check_charBuf.py | 1 - src/cts/test/check_charBuf.tcl | 3 +- src/cts/test/check_max_fanout1.tcl | 3 +- src/cts/test/check_max_fanout2.tcl | 3 +- src/cts/test/check_wire_rc_cts.py | 1 - src/cts/test/check_wire_rc_cts.tcl | 3 +- src/cts/test/cts_aux.py | 3 -- src/cts/test/dummy_load.tcl | 3 +- src/cts/test/find_clock.py | 1 - src/cts/test/find_clock.tcl | 3 +- src/cts/test/find_clock_pad.py | 2 +- src/cts/test/find_clock_pad.tcl | 3 +- src/cts/test/insertion_delay.tcl | 3 +- src/cts/test/lvt_lib.ok | 44 +++++++++++++++---- src/cts/test/max_cap.py | 1 - src/cts/test/max_cap.tcl | 3 +- src/cts/test/no_clocks.py | 1 - src/cts/test/no_clocks.tcl | 3 +- src/cts/test/no_sinks.py | 1 - src/cts/test/no_sinks.tcl | 3 +- src/cts/test/post_cts_opt.tcl | 3 +- src/cts/test/simple_test.py | 1 - src/cts/test/simple_test.tcl | 1 - src/cts/test/simple_test_clustered.py | 1 - src/cts/test/simple_test_clustered.tcl | 3 +- src/cts/test/simple_test_clustered_max_cap.py | 1 - .../test/simple_test_clustered_max_cap.tcl | 3 +- src/cts/test/simple_test_hier.tcl | 2 +- 39 files changed, 59 insertions(+), 73 deletions(-) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 70836f3c6ed..a8a2bacd1c2 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -1278,9 +1278,6 @@ void TritonCTS::writeClockNetsToDb(TreeBuilder* builder, odb::dbModule* top_module = network_->getNetDriverParentModule(network_->dbToSta(topClockNet)); - const std::string topRegBufferName = "clkbuf_regs_0_" + clockNet.getSdcName(); - odb::dbInst* topRegBuffer = block_->findInst(topRegBufferName.c_str()); - disconnectAllSinksFromNet(topClockNet); // re-connect top buffer that separates macros from registers @@ -2123,7 +2120,7 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex, odb::dbNet* topNet } if (pathsAccepted > 1 || pathsAccepted == 0) { - logger_->report("Number of clock paths is not 1 for pin {}. Number of clock paths: {}", + logger_->warn(CTS, 1, "Number of clock paths is not 1 for pin {}. Number of clock paths: {}", iterm->getName(), pathsAccepted); } diff --git a/src/cts/test/array.tcl b/src/cts/test/array.tcl index e053ce69cdc..f88c10a7b7a 100644 --- a/src/cts/test/array.tcl +++ b/src/cts/test/array.tcl @@ -136,8 +136,7 @@ clock_tree_synthesis -root_buf $cts_buffer \ -buf_list $cts_buffer \ -sink_clustering_enable \ -sink_clustering_max_diameter $cts_cluster_diameter \ - -balance_levels \ - -obstruction_aware + -balance_levels set_propagated_clock [all_clocks] estimate_parasitics -placement diff --git a/src/cts/test/array_dummy.tcl b/src/cts/test/array_dummy.tcl index 348afb25f84..875768f5207 100644 --- a/src/cts/test/array_dummy.tcl +++ b/src/cts/test/array_dummy.tcl @@ -137,7 +137,6 @@ clock_tree_synthesis -root_buf $cts_buffer \ -sink_clustering_enable \ -sink_clustering_max_diameter $cts_cluster_diameter \ -balance_levels \ - -obstruction_aware \ -use_dummy_load set_propagated_clock [all_clocks] diff --git a/src/cts/test/array_full_flow.tcl b/src/cts/test/array_full_flow.tcl index ec6c472f516..9a1f2878508 100644 --- a/src/cts/test/array_full_flow.tcl +++ b/src/cts/test/array_full_flow.tcl @@ -136,8 +136,7 @@ clock_tree_synthesis -root_buf $cts_buffer \ -buf_list $cts_buffer \ -sink_clustering_enable \ -sink_clustering_max_diameter $cts_cluster_diameter \ - -balance_levels \ - -obstruction_aware + -balance_levels set_propagated_clock [all_clocks] estimate_parasitics -placement diff --git a/src/cts/test/array_ins_delay.tcl b/src/cts/test/array_ins_delay.tcl index a16a6f6ed31..902f1179c54 100644 --- a/src/cts/test/array_ins_delay.tcl +++ b/src/cts/test/array_ins_delay.tcl @@ -136,8 +136,7 @@ clock_tree_synthesis -root_buf $cts_buffer \ -buf_list $cts_buffer \ -sink_clustering_enable \ -sink_clustering_max_diameter $cts_cluster_diameter \ - -balance_levels \ - -obstruction_aware + -balance_levels set_propagated_clock [all_clocks] estimate_parasitics -placement diff --git a/src/cts/test/array_no_blockages.tcl b/src/cts/test/array_no_blockages.tcl index e5723afb831..d8e5b511cf3 100644 --- a/src/cts/test/array_no_blockages.tcl +++ b/src/cts/test/array_no_blockages.tcl @@ -134,8 +134,7 @@ clock_tree_synthesis -root_buf $cts_buffer \ -buf_list $cts_buffer \ -sink_clustering_enable \ -sink_clustering_max_diameter $cts_cluster_diameter \ - -balance_levels \ - -obstruction_aware + -balance_levels set_propagated_clock [all_clocks] estimate_parasitics -placement diff --git a/src/cts/test/balance_levels.py b/src/cts/test/balance_levels.py index cd6426d8754..f140cdd32e8 100644 --- a/src/cts/test/balance_levels.py +++ b/src/cts/test/balance_levels.py @@ -25,7 +25,6 @@ sink_clustering_max_diameter=60.0, balance_levels=True, num_static_layers=1, - obstruction_aware=True, ) def_file = helpers.make_result_file("balance_levels.def") diff --git a/src/cts/test/balance_levels.tcl b/src/cts/test/balance_levels.tcl index 5640ffb2415..377e37d1469 100644 --- a/src/cts/test/balance_levels.tcl +++ b/src/cts/test/balance_levels.tcl @@ -20,8 +20,7 @@ clock_tree_synthesis -root_buf CLKBUF_X3 \ -sink_clustering_size 5 \ -sink_clustering_max_diameter 60 \ -balance_levels \ - -num_static_layers 1 \ - -obstruction_aware + -num_static_layers 1 set def_file [make_result_file balance_levels.def] write_def $def_file diff --git a/src/cts/test/check_buffers.py b/src/cts/test/check_buffers.py index af03e152214..4e0efe6ea45 100644 --- a/src/cts/test/check_buffers.py +++ b/src/cts/test/check_buffers.py @@ -23,7 +23,6 @@ sink_clustering_size=10, sink_clustering_max_diameter=60.0, num_static_layers=1, - obstruction_aware=True, ) # This is only for checking clock tree results and not testing per se diff --git a/src/cts/test/check_buffers.tcl b/src/cts/test/check_buffers.tcl index fcdb54e5362..e2a10025912 100644 --- a/src/cts/test/check_buffers.tcl +++ b/src/cts/test/check_buffers.tcl @@ -14,8 +14,7 @@ clock_tree_synthesis -root_buf CLKBUF_X3 \ -distance_between_buffers 100 \ -sink_clustering_size 10 \ -sink_clustering_max_diameter 60 \ - -num_static_layers 1 \ - -obstruction_aware + -num_static_layers 1 set unconnected_buffers 0 foreach buf [get_cells clkbuf_*_clk] { diff --git a/src/cts/test/check_buffers_blockages.tcl b/src/cts/test/check_buffers_blockages.tcl index bf44969f560..07a7fab1e88 100644 --- a/src/cts/test/check_buffers_blockages.tcl +++ b/src/cts/test/check_buffers_blockages.tcl @@ -16,8 +16,7 @@ clock_tree_synthesis -root_buf CLKBUF_X3 \ -distance_between_buffers 100 \ -sink_clustering_size 10 \ -sink_clustering_max_diameter 60 \ - -num_static_layers 1 \ - -obstruction_aware + -num_static_layers 1 set unconnected_buffers 0 foreach buf [get_cells clkbuf_*_clk] { diff --git a/src/cts/test/check_charBuf.py b/src/cts/test/check_charBuf.py index 30a91b126e4..5d9c1dbf2ae 100644 --- a/src/cts/test/check_charBuf.py +++ b/src/cts/test/check_charBuf.py @@ -17,5 +17,4 @@ root_buf="CLKBUF_X3", buf_list="CLKBUF_X3 CLKBUF_X2 BUF_X4 CLKBUF_X1", wire_unit=20, - obstruction_aware=True, ) diff --git a/src/cts/test/check_charBuf.tcl b/src/cts/test/check_charBuf.tcl index 76c5bdb597a..9f460a73df3 100644 --- a/src/cts/test/check_charBuf.tcl +++ b/src/cts/test/check_charBuf.tcl @@ -9,5 +9,4 @@ set_wire_rc -clock -layer metal3 clock_tree_synthesis -root_buf CLKBUF_X3 \ -buf_list "CLKBUF_X3 CLKBUF_X2 BUF_X4 CLKBUF_X1" \ - -wire_unit 20 \ - -obstruction_aware + -wire_unit 20 diff --git a/src/cts/test/check_max_fanout1.tcl b/src/cts/test/check_max_fanout1.tcl index 4dd2fb1080b..380411ce9f1 100644 --- a/src/cts/test/check_max_fanout1.tcl +++ b/src/cts/test/check_max_fanout1.tcl @@ -17,8 +17,7 @@ clock_tree_synthesis -root_buf sg13g2_buf_4 \ -distance_between_buffers 100 \ -sink_clustering_size 10 \ -sink_clustering_max_diameter 60 \ - -num_static_layers 1 \ - -obstruction_aware + -num_static_layers 1 set_propagated_clock [all_clocks] estimate_parasitics -placement diff --git a/src/cts/test/check_max_fanout2.tcl b/src/cts/test/check_max_fanout2.tcl index e075542a5ce..54b9b27c10e 100644 --- a/src/cts/test/check_max_fanout2.tcl +++ b/src/cts/test/check_max_fanout2.tcl @@ -21,8 +21,7 @@ clock_tree_synthesis -root_buf CLKBUF_X3 \ -distance_between_buffers 100 \ -sink_clustering_size 10 \ -sink_clustering_max_diameter 60 \ - -num_static_layers 1 \ - -obstruction_aware + -num_static_layers 1 set_propagated_clock [all_clocks] estimate_parasitics -placement diff --git a/src/cts/test/check_wire_rc_cts.py b/src/cts/test/check_wire_rc_cts.py index e14acffe84e..fe7752835ec 100644 --- a/src/cts/test/check_wire_rc_cts.py +++ b/src/cts/test/check_wire_rc_cts.py @@ -22,7 +22,6 @@ sink_clustering_size=10, sink_clustering_max_diameter=60.0, num_static_layers=1, - obstruction_aware=True, ) # This is only for checking clock tree results and not testing per se diff --git a/src/cts/test/check_wire_rc_cts.tcl b/src/cts/test/check_wire_rc_cts.tcl index 54d27649d16..3917a46c0d8 100644 --- a/src/cts/test/check_wire_rc_cts.tcl +++ b/src/cts/test/check_wire_rc_cts.tcl @@ -15,8 +15,7 @@ clock_tree_synthesis -root_buf CLKBUF_X3 \ -distance_between_buffers 100 \ -sink_clustering_size 10 \ -sink_clustering_max_diameter 60 \ - -num_static_layers 1 \ - -obstruction_aware + -num_static_layers 1 set unconnected_buffers 0 foreach buf [get_cells clkbuf_*_clk] { diff --git a/src/cts/test/cts_aux.py b/src/cts/test/cts_aux.py index a1d2a33bab7..896228f58c7 100644 --- a/src/cts/test/cts_aux.py +++ b/src/cts/test/cts_aux.py @@ -54,7 +54,6 @@ def clock_tree_synthesis( sink_clustering_levels=None, num_static_layers=None, sink_clustering_buffer=None, - obstruction_aware=False, apply_ndr=False, ): cts = design.getTritonCts() @@ -63,8 +62,6 @@ def clock_tree_synthesis( # Boolean parms.setSinkClustering(sink_clustering_enable) parms.setBalanceLevels(balance_levels) - parms.setObstructionAware(obstruction_aware) - parms.enableInsertionDelay(insertion_delay) parms.setApplyNDR(apply_ndr) if is_pos_int(sink_clustering_size): diff --git a/src/cts/test/dummy_load.tcl b/src/cts/test/dummy_load.tcl index afa2cbdebe9..0f538e08eb3 100644 --- a/src/cts/test/dummy_load.tcl +++ b/src/cts/test/dummy_load.tcl @@ -16,8 +16,7 @@ clock_tree_synthesis -root_buf CLKBUF_X3 \ -distance_between_buffers 100 \ -sink_clustering_size 10 \ -sink_clustering_max_diameter 60 \ - -num_static_layers 1 \ - -obstruction_aware + -num_static_layers 1 set unconnected_buffers 0 foreach buf [get_cells clkbuf_*_clk] { diff --git a/src/cts/test/find_clock.py b/src/cts/test/find_clock.py index e983b169867..47b21cfa0b1 100644 --- a/src/cts/test/find_clock.py +++ b/src/cts/test/find_clock.py @@ -17,5 +17,4 @@ root_buf="CLKBUF_X3", buf_list="CLKBUF_X3", wire_unit=20, - obstruction_aware=True, ) diff --git a/src/cts/test/find_clock.tcl b/src/cts/test/find_clock.tcl index c08a6b55804..d740e11f6fb 100644 --- a/src/cts/test/find_clock.tcl +++ b/src/cts/test/find_clock.tcl @@ -8,5 +8,4 @@ create_clock -period 5 clk clock_tree_synthesis -root_buf CLKBUF_X3 \ -buf_list CLKBUF_X3 \ - -wire_unit 20 \ - -obstruction_aware + -wire_unit 20 diff --git a/src/cts/test/find_clock_pad.py b/src/cts/test/find_clock_pad.py index 8a0f8e23531..ed0bbfaa930 100644 --- a/src/cts/test/find_clock_pad.py +++ b/src/cts/test/find_clock_pad.py @@ -14,4 +14,4 @@ design.evalTclString("create_clock -name clk -period 10 clk1") design.evalTclString("set_wire_rc -clock -layer metal5") -cts_aux.clock_tree_synthesis(design, buf_list="BUF_X1", obstruction_aware=True) +cts_aux.clock_tree_synthesis(design, buf_list="BUF_X1") diff --git a/src/cts/test/find_clock_pad.tcl b/src/cts/test/find_clock_pad.tcl index c88f9d33e45..a3bbfff9989 100644 --- a/src/cts/test/find_clock_pad.tcl +++ b/src/cts/test/find_clock_pad.tcl @@ -14,6 +14,5 @@ create_clock -name clk -period 10 clk1 set_wire_rc -clock -layer metal5 -clock_tree_synthesis -buf_list "BUF_X1" \ - -obstruction_aware +clock_tree_synthesis -buf_list "BUF_X1" diff --git a/src/cts/test/insertion_delay.tcl b/src/cts/test/insertion_delay.tcl index a4a3307412f..f05a2f14a42 100755 --- a/src/cts/test/insertion_delay.tcl +++ b/src/cts/test/insertion_delay.tcl @@ -25,8 +25,7 @@ clock_tree_synthesis -root_buf CLKBUF_X3 \ -distance_between_buffers 100 \ -sink_clustering_size 10 \ -sink_clustering_max_diameter 60 \ - -num_static_layers 1 \ - -obstruction_aware + -num_static_layers 1 set unconnected_buffers 0 foreach buf [get_cells clkbuf_*] { diff --git a/src/cts/test/lvt_lib.ok b/src/cts/test/lvt_lib.ok index 9560c02ec12..d754950c415 100644 --- a/src/cts/test/lvt_lib.ok +++ b/src/cts/test/lvt_lib.ok @@ -7,14 +7,32 @@ CLKBUF_X1_L [INFO CTS-0049] Characterization buffer is CLKBUF_X1_L. [INFO CTS-0007] Net "clk" found for clock "clk". -[INFO CTS-0010] Clock net "clk" has 151 sinks. +[INFO CTS-0011] Clock net "clk" for macros has 1 sinks. +[INFO CTS-0011] Clock net "clk_regs" for registers has 150 sinks. [INFO CTS-0010] Clock net "CELL/clk2" has 150 sinks. -[INFO CTS-0008] TritonCTS found 2 clock nets. +[INFO CTS-0008] TritonCTS found 3 clock nets. [INFO CTS-0097] Characterization used 1 buffer(s) types. [INFO CTS-0200] 0 placement blockages have been identified. [INFO CTS-0201] 0 placed hard macros will be treated like blockages. [INFO CTS-0027] Generating H-Tree topology for net clk. -[INFO CTS-0028] Total number of sinks: 151. +[INFO CTS-0028] Total number of sinks: 1. +[INFO CTS-0030] Number of static layers: 0. +[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). +[INFO CTS-0023] Original sink region: [(100250, 101225), (100250, 101225)]. +[INFO CTS-0024] Normalized sink region: [(7.16071, 7.23036), (7.16071, 7.23036)]. +[INFO CTS-0025] Width: 0.0000. +[INFO CTS-0026] Height: 0.0000. + Level 1 + Direction: Vertical + Sinks per sub-region: 1 + Sub-region size: 0.0000 X 0.0000 +[INFO CTS-0034] Segment length (rounded): 1. +[INFO CTS-0032] Stop criterion found. Max number of sinks is 15. +[INFO CTS-0035] Number of sinks covered: 1. +[INFO CTS-0200] 0 placement blockages have been identified. +[INFO CTS-0201] 0 placed hard macros will be treated like blockages. +[INFO CTS-0027] Generating H-Tree topology for net clk_regs. +[INFO CTS-0028] Total number of sinks: 150. [INFO CTS-0030] Number of static layers: 0. [INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). [INFO CTS-0023] Original sink region: [(8785, 6785), (197672, 95673)]. @@ -23,7 +41,7 @@ [INFO CTS-0026] Height: 6.3491. Level 1 Direction: Horizontal - Sinks per sub-region: 76 + Sinks per sub-region: 75 Sub-region size: 6.7460 X 6.3491 [INFO CTS-0034] Segment length (rounded): 4. Level 2 @@ -42,7 +60,7 @@ Sub-region size: 3.3730 X 1.5873 [INFO CTS-0034] Segment length (rounded): 1. [INFO CTS-0032] Stop criterion found. Max number of sinks is 15. -[INFO CTS-0035] Number of sinks covered: 151. +[INFO CTS-0035] Number of sinks covered: 150. [INFO CTS-0200] 0 placement blockages have been identified. [INFO CTS-0201] 0 placed hard macros will be treated like blockages. [INFO CTS-0027] Generating H-Tree topology for net CELL\/clk2. @@ -75,11 +93,17 @@ [INFO CTS-0034] Segment length (rounded): 1. [INFO CTS-0032] Stop criterion found. Max number of sinks is 15. [INFO CTS-0035] Number of sinks covered: 150. +[INFO CTS-0018] Created 2 clock buffers. +[INFO CTS-0012] Minimum number of buffers in the clock path: 2. +[INFO CTS-0013] Maximum number of buffers in the clock path: 2. +[INFO CTS-0015] Created 2 clock nets. +[INFO CTS-0016] Fanout distribution for the current clock = 1:1.. +[INFO CTS-0017] Max level of the clock tree: 1. [INFO CTS-0018] Created 17 clock buffers. [INFO CTS-0012] Minimum number of buffers in the clock path: 2. [INFO CTS-0013] Maximum number of buffers in the clock path: 2. [INFO CTS-0015] Created 17 clock nets. -[INFO CTS-0016] Fanout distribution for the current clock = 7:1, 8:4, 9:5, 10:3, 12:2, 13:1.. +[INFO CTS-0016] Fanout distribution for the current clock = 7:1, 8:4, 9:6, 10:2, 12:2, 13:1.. [INFO CTS-0017] Max level of the clock tree: 4. [INFO CTS-0018] Created 17 clock buffers. [INFO CTS-0012] Minimum number of buffers in the clock path: 2. @@ -87,10 +111,12 @@ [INFO CTS-0015] Created 17 clock nets. [INFO CTS-0016] Fanout distribution for the current clock = 7:3, 8:2, 9:4, 10:4, 12:2, 13:1.. [INFO CTS-0017] Max level of the clock tree: 4. -[INFO CTS-0098] Clock net "clk" -[INFO CTS-0099] Sinks 166 +[INFO CTS-0124] Clock net "clk" +[INFO CTS-0125] Sinks 1 +[INFO CTS-0098] Clock net "clk_regs" +[INFO CTS-0099] Sinks 165 [INFO CTS-0100] Leaf buffers 0 -[INFO CTS-0101] Average sink wire length 121.61 um +[INFO CTS-0101] Average sink wire length 48.97 um [INFO CTS-0102] Path depth 2 - 2 [INFO CTS-0207] Leaf load cells 30 [INFO CTS-0098] Clock net "CELL\/clk2" diff --git a/src/cts/test/max_cap.py b/src/cts/test/max_cap.py index 56010761778..0e91c01739c 100644 --- a/src/cts/test/max_cap.py +++ b/src/cts/test/max_cap.py @@ -34,7 +34,6 @@ design, root_buf="sky130_fd_sc_hs__clkbuf_1", buf_list="sky130_fd_sc_hs__clkbuf_1", - obstruction_aware=True, ) tcl_strg3 = """set_propagated_clock clk1 diff --git a/src/cts/test/max_cap.tcl b/src/cts/test/max_cap.tcl index 04e02688567..23f3ba7a478 100644 --- a/src/cts/test/max_cap.tcl +++ b/src/cts/test/max_cap.tcl @@ -23,8 +23,7 @@ set_wire_rc -clock -layer met3 #set_wire_rc -clock -capacitance [expr 100e-10 * 1e-6 * 1e+12] -resistance [expr 166800.0 * 1e-6 * 1e-3] clock_tree_synthesis -root_buf sky130_fd_sc_hs__clkbuf_1 \ - -buf_list sky130_fd_sc_hs__clkbuf_1 \ - -obstruction_aware + -buf_list sky130_fd_sc_hs__clkbuf_1 set_propagated_clock clk1 estimate_parasitics -placement diff --git a/src/cts/test/no_clocks.py b/src/cts/test/no_clocks.py index 701e7da3ffd..8e1ef2c9f83 100644 --- a/src/cts/test/no_clocks.py +++ b/src/cts/test/no_clocks.py @@ -17,7 +17,6 @@ root_buf="CLKBUF_X3", buf_list="CLKBUF_X3", wire_unit=20, - obstruction_aware=True, ) except Exception as inst: print(inst.args[0]) diff --git a/src/cts/test/no_clocks.tcl b/src/cts/test/no_clocks.tcl index 286072345e6..4d60a502ffc 100644 --- a/src/cts/test/no_clocks.tcl +++ b/src/cts/test/no_clocks.tcl @@ -7,6 +7,5 @@ set_wire_rc -clock -layer metal5 catch {clock_tree_synthesis \ -root_buf CLKBUF_X3 \ -buf_list CLKBUF_X3 \ - -wire_unit 20 \ - -obstruction_aware} error + -wire_unit 20} error puts $error diff --git a/src/cts/test/no_sinks.py b/src/cts/test/no_sinks.py index cbd2c1508ec..c8c302a274a 100644 --- a/src/cts/test/no_sinks.py +++ b/src/cts/test/no_sinks.py @@ -19,7 +19,6 @@ buf_list="CLKBUF_X3", wire_unit=20, clk_nets="clk", - obstruction_aware=True, ) except Exception as inst: print(inst.args[0]) diff --git a/src/cts/test/no_sinks.tcl b/src/cts/test/no_sinks.tcl index 291485a2bdc..a9736c7723f 100644 --- a/src/cts/test/no_sinks.tcl +++ b/src/cts/test/no_sinks.tcl @@ -9,7 +9,6 @@ set_wire_rc -clock -layer metal5 catch {clock_tree_synthesis -root_buf CLKBUF_X3 \ -buf_list CLKBUF_X3 \ -wire_unit 20 \ - -clk_nets "clk" \ - -obstruction_aware} error + -clk_nets "clk"} error puts $error diff --git a/src/cts/test/post_cts_opt.tcl b/src/cts/test/post_cts_opt.tcl index 4850c8cadb7..e24b888659a 100644 --- a/src/cts/test/post_cts_opt.tcl +++ b/src/cts/test/post_cts_opt.tcl @@ -21,5 +21,4 @@ clock_tree_synthesis -root_buf CLKBUF_X3 \ -wire_unit 20 \ -sink_clustering_enable \ -distance_between_buffers 100 \ - -num_static_layers 1 \ - -obstruction_aware + -num_static_layers 1 diff --git a/src/cts/test/simple_test.py b/src/cts/test/simple_test.py index d40432bbad2..84026276371 100644 --- a/src/cts/test/simple_test.py +++ b/src/cts/test/simple_test.py @@ -17,7 +17,6 @@ root_buf="CLKBUF_X3", buf_list="CLKBUF_X3", wire_unit=20, - obstruction_aware=True, apply_ndr=True, ) diff --git a/src/cts/test/simple_test.tcl b/src/cts/test/simple_test.tcl index 0e1e423ab60..3f44cddc2ef 100644 --- a/src/cts/test/simple_test.tcl +++ b/src/cts/test/simple_test.tcl @@ -10,7 +10,6 @@ set_wire_rc -clock -layer metal3 clock_tree_synthesis -root_buf CLKBUF_X3 \ -buf_list CLKBUF_X3 \ -wire_unit 20 \ - -obstruction_aware \ -apply_ndr set def_file [make_result_file simple_test_out.def] diff --git a/src/cts/test/simple_test_clustered.py b/src/cts/test/simple_test_clustered.py index 06117b0e0f1..15d11add434 100644 --- a/src/cts/test/simple_test_clustered.py +++ b/src/cts/test/simple_test_clustered.py @@ -24,5 +24,4 @@ sink_clustering_size=10, sink_clustering_max_diameter=60.0, num_static_layers=1, - obstruction_aware=True, ) diff --git a/src/cts/test/simple_test_clustered.tcl b/src/cts/test/simple_test_clustered.tcl index 5a8e592e6f5..815d9a0b444 100644 --- a/src/cts/test/simple_test_clustered.tcl +++ b/src/cts/test/simple_test_clustered.tcl @@ -18,5 +18,4 @@ clock_tree_synthesis -root_buf CLKBUF_X3 \ -distance_between_buffers 100 \ -sink_clustering_size 10 \ -sink_clustering_max_diameter 60 \ - -num_static_layers 1 \ - -obstruction_aware + -num_static_layers 1 \ No newline at end of file diff --git a/src/cts/test/simple_test_clustered_max_cap.py b/src/cts/test/simple_test_clustered_max_cap.py index bf11da54b06..02b3f18a35b 100644 --- a/src/cts/test/simple_test_clustered_max_cap.py +++ b/src/cts/test/simple_test_clustered_max_cap.py @@ -23,5 +23,4 @@ sink_clustering_enable=True, distance_between_buffers=100.0, num_static_layers=1, - obstruction_aware=True, ) diff --git a/src/cts/test/simple_test_clustered_max_cap.tcl b/src/cts/test/simple_test_clustered_max_cap.tcl index ade72cf5645..d7606340ec5 100644 --- a/src/cts/test/simple_test_clustered_max_cap.tcl +++ b/src/cts/test/simple_test_clustered_max_cap.tcl @@ -17,5 +17,4 @@ clock_tree_synthesis -root_buf CLKBUF_X3 \ -wire_unit 20 \ -sink_clustering_enable \ -distance_between_buffers 100 \ - -num_static_layers 1 \ - -obstruction_aware + -num_static_layers 1 diff --git a/src/cts/test/simple_test_hier.tcl b/src/cts/test/simple_test_hier.tcl index ed65c2e645e..29fa404866a 100644 --- a/src/cts/test/simple_test_hier.tcl +++ b/src/cts/test/simple_test_hier.tcl @@ -20,7 +20,7 @@ create_clock -period 5 clk set_wire_rc -clock -layer metal3 -clock_tree_synthesis -root_buf CLKBUF_X3 -buf_list CLKBUF_X3 -wire_unit 20 -obstruction_aware -apply_ndr +clock_tree_synthesis -root_buf CLKBUF_X3 -buf_list CLKBUF_X3 -wire_unit 20 -apply_ndr set verilog_file [make_result_file simple_test_hier_out.v] write_verilog $verilog_file From 90d978a8b61cc1c72469cf6cba40cf5e0693c354 Mon Sep 17 00:00:00 2001 From: arthur Date: Mon, 7 Oct 2024 16:14:54 -0300 Subject: [PATCH 19/23] clang format Signed-off-by: arthur --- src/cts/src/TritonCTS.cpp | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index a8a2bacd1c2..aa0f78da043 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -293,7 +293,8 @@ void TritonCTS::initOneClockTree(odb::dbNet* driverNet, if (visitedClockNets_.find(outputNet) == visitedClockNets_.end() && !openSta_->sdc()->isLeafPinClock( network_->dbToSta(outputPin))) { - initOneClockTree(outputNet, clkInputNet, sdcClockName, clockBuilder); + initOneClockTree( + outputNet, clkInputNet, sdcClockName, clockBuilder); } } } @@ -1224,7 +1225,8 @@ Clock TritonCTS::forkRegisterClockNetwork( odb::dbMaster* master = db_->findMaster(options_->getRootBuffer().c_str()); topBufferName = "clkbuf_regs_" + std::to_string(regTreeRootBufIndex_++) + "_" + clockNet.getSdcName(); - odb::dbInst* clockBuf = odb::dbInst::create(block_, master, topBufferName.c_str(), false, target_module); + odb::dbInst* clockBuf = odb::dbInst::create( + block_, master, topBufferName.c_str(), false, target_module); odb::dbITerm* inputTerm = getFirstInput(clockBuf); odb::dbITerm* outputTerm = clockBuf->getFirstOutput(); inputTerm->connect(firstNet); @@ -2072,9 +2074,10 @@ void TritonCTS::balanceMacroRegisterLatencies() } } -float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex, odb::dbNet* topNet, odb::dbITerm* iterm) +float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex, + odb::dbNet* topNet, + odb::dbITerm* iterm) { - sta::VertexPathIterator pathIter(sinkVertex, openSta_); float clkPathArrival = 0.0; int pathsAccepted = 0; @@ -2095,7 +2098,7 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex, odb::dbNet* topNet if (start->dcalcAnalysisPt(openSta_)->delayMinMax() != sta::MinMax::max()) { - continue; + continue; // only populate with max delay } @@ -2109,7 +2112,6 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex, odb::dbNet* topNet } if (port) { pathStartNet = port->getNet(); - } if (pathStartNet == topNet) { clkPathArrival = path->arrival(openSta_); @@ -2119,10 +2121,12 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex, odb::dbNet* topNet } } if (pathsAccepted > 1 || pathsAccepted == 0) { - - logger_->warn(CTS, 1, "Number of clock paths is not 1 for pin {}. Number of clock paths: {}", - iterm->getName(), - pathsAccepted); + logger_->warn( + CTS, + 1, + "Number of clock paths is not 1 for pin {}. Number of clock paths: {}", + iterm->getName(), + pathsAccepted); } return clkPathArrival; } @@ -2139,7 +2143,8 @@ void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder, sta::Graph* graph) unsigned numSinks = 0; clock.forEachSink([&](const ClockInst& sink) { odb::dbITerm* iterm = sink.getDbInputPin(); - computeSinkArrivalRecur(topInputClockNet, iterm, sumArrivals, numSinks, graph); + computeSinkArrivalRecur( + topInputClockNet, iterm, sumArrivals, numSinks, graph); }); float aveArrival = sumArrivals / (float) numSinks; builder->setAveSinkArrival(aveArrival); From 5fc884fc0cd7d0b440bfba5936ac081cd4977e50 Mon Sep 17 00:00:00 2001 From: arthur Date: Tue, 8 Oct 2024 09:51:52 -0300 Subject: [PATCH 20/23] change warning number Signed-off-by: arthur --- src/cts/src/TritonCTS.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index aa0f78da043..1d7aafcc7cd 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -2123,7 +2123,7 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex, if (pathsAccepted > 1 || pathsAccepted == 0) { logger_->warn( CTS, - 1, + 2, "Number of clock paths is not 1 for pin {}. Number of clock paths: {}", iterm->getName(), pathsAccepted); From 15cfa3547c9fb42a0e6c03355866bca6e9654037 Mon Sep 17 00:00:00 2001 From: arthur Date: Tue, 8 Oct 2024 13:43:18 -0300 Subject: [PATCH 21/23] Compute clk arrival times Signed-off-by: arthur --- src/cts/src/TritonCTS.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 1d7aafcc7cd..34079052d74 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -2058,6 +2058,7 @@ void TritonCTS::balanceMacroRegisterLatencies() openSta_->ensureGraph(); openSta_->searchPreamble(); openSta_->ensureClkNetwork(); + openSta_->ensureClkArrivals(); sta::Graph* graph = openSta_->graph(); for (auto iter = builders_->rbegin(); iter != builders_->rend(); ++iter) { TreeBuilder* registerBuilder = *iter; From 62ea7322cd48644eed0e5870e29989dfd4b307dd Mon Sep 17 00:00:00 2001 From: arthur Date: Tue, 8 Oct 2024 13:47:47 -0300 Subject: [PATCH 22/23] code format Signed-off-by: arthur --- src/cts/include/cts/TritonCTS.h | 4 +++- src/cts/src/TritonCTS.tcl | 3 +-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/cts/include/cts/TritonCTS.h b/src/cts/include/cts/TritonCTS.h index 3542344a5ff..d8c207b4888 100644 --- a/src/cts/include/cts/TritonCTS.h +++ b/src/cts/include/cts/TritonCTS.h @@ -207,7 +207,9 @@ class TritonCTS ClockInst& dummyClock); void printClockNetwork(const Clock& clockNet) const; void balanceMacroRegisterLatencies(); - float getVertexClkArrival(sta::Vertex* sinkVertex, odb::dbNet* topNet, odb::dbITerm* iterm); + float getVertexClkArrival(sta::Vertex* sinkVertex, + odb::dbNet* topNet, + odb::dbITerm* iterm); void computeAveSinkArrivals(TreeBuilder* builder, sta::Graph* graph); void computeSinkArrivalRecur(odb::dbNet* topClokcNet, odb::dbITerm* iterm, diff --git a/src/cts/src/TritonCTS.tcl b/src/cts/src/TritonCTS.tcl index d339bbbe02f..b38d188e207 100644 --- a/src/cts/src/TritonCTS.tcl +++ b/src/cts/src/TritonCTS.tcl @@ -101,8 +101,7 @@ proc clock_tree_synthesis { args } { -sink_clustering_levels -tree_buf \ -sink_buffer_max_cap_derate -delay_buffer_derate -library} \ flags {-post_cts_disable -sink_clustering_enable -balance_levels \ - -apply_ndr -dont_use_dummy_load - };# checker off + -apply_ndr -dont_use_dummy_load};# checker off sta::check_argc_eq0 "clock_tree_synthesis" $args From dfc20a6c44c8b6944fa7aa242a46394513a82f50 Mon Sep 17 00:00:00 2001 From: arthur Date: Tue, 8 Oct 2024 14:50:52 -0300 Subject: [PATCH 23/23] address calng tidy sugestion Signed-off-by: arthur --- src/cts/src/TritonCTS.cpp | 13 ++----------- src/cts/src/TritonCTS.tcl | 2 +- 2 files changed, 3 insertions(+), 12 deletions(-) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 34079052d74..d52f6dcf107 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -2081,7 +2081,7 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex, { sta::VertexPathIterator pathIter(sinkVertex, openSta_); float clkPathArrival = 0.0; - int pathsAccepted = 0; + while (pathIter.hasNext()) { sta::Path* path = pathIter.next(); @@ -2116,19 +2116,11 @@ float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex, } if (pathStartNet == topNet) { clkPathArrival = path->arrival(openSta_); - pathsAccepted += 1; return clkPathArrival; } } } - if (pathsAccepted > 1 || pathsAccepted == 0) { - logger_->warn( - CTS, - 2, - "Number of clock paths is not 1 for pin {}. Number of clock paths: {}", - iterm->getName(), - pathsAccepted); - } + logger_->warn(CTS, 2, "No paths found for pin {}.", iterm->getName()); return clkPathArrival; } @@ -2197,7 +2189,6 @@ void TritonCTS::computeSinkArrivalRecur(odb::dbNet* topClokcNet, sumArrivals += (arrival + insDelay); numSinks++; } - return; } else { // not a sink, but a clock gater odb::dbITerm* outTerm = inst->getFirstOutput(); diff --git a/src/cts/src/TritonCTS.tcl b/src/cts/src/TritonCTS.tcl index b38d188e207..d629d5dbb51 100644 --- a/src/cts/src/TritonCTS.tcl +++ b/src/cts/src/TritonCTS.tcl @@ -101,7 +101,7 @@ proc clock_tree_synthesis { args } { -sink_clustering_levels -tree_buf \ -sink_buffer_max_cap_derate -delay_buffer_derate -library} \ flags {-post_cts_disable -sink_clustering_enable -balance_levels \ - -apply_ndr -dont_use_dummy_load};# checker off + -apply_ndr -dont_use_dummy_load} ;# checker off sta::check_argc_eq0 "clock_tree_synthesis" $args